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An experimental small core based on VexRiscv, written in Scala
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a2p/build/litex/a2p/verilog/A2P_WB_normal.v

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// Generator : SpinalHDL v1.4.0 git head : ecb5a80b713566f417ea3ea061f9969e73770a7f
// Date : 31/10/2021, 08:50:20
// Component : A2P_WB
`define TgtCtrlEnum_defaultEncoding_type [0:0]
`define TgtCtrlEnum_defaultEncoding_RT 1'b0
`define TgtCtrlEnum_defaultEncoding_RA 1'b1
`define Src1CtrlEnum_defaultEncoding_type [2:0]
`define Src1CtrlEnum_defaultEncoding_RA 3'b000
`define Src1CtrlEnum_defaultEncoding_RA_N 3'b001
`define Src1CtrlEnum_defaultEncoding_RA_NIA 3'b010
`define Src1CtrlEnum_defaultEncoding_RA_0 3'b011
`define Src1CtrlEnum_defaultEncoding_RS 3'b100
`define Src2CtrlEnum_defaultEncoding_type [2:0]
`define Src2CtrlEnum_defaultEncoding_RB 3'b000
`define Src2CtrlEnum_defaultEncoding_RB_0 3'b001
`define Src2CtrlEnum_defaultEncoding_RB_M1 3'b010
`define Src2CtrlEnum_defaultEncoding_RB_UI 3'b011
`define Src2CtrlEnum_defaultEncoding_RB_SI 3'b100
`define Src2CtrlEnum_defaultEncoding_RB_SH 3'b101
`define Src2CtrlEnum_defaultEncoding_RB_PCISD 3'b110
`define Src2CtrlEnum_defaultEncoding_RA 3'b111
`define AluCtrlEnum_defaultEncoding_type [1:0]
`define AluCtrlEnum_defaultEncoding_ADD 2'b00
`define AluCtrlEnum_defaultEncoding_BIT_1 2'b01
`define AluCtrlEnum_defaultEncoding_RIMI 2'b10
`define AluCtrlEnum_defaultEncoding_SPEC 2'b11
`define Src3CtrlEnum_defaultEncoding_type [1:0]
`define Src3CtrlEnum_defaultEncoding_CA 2'b00
`define Src3CtrlEnum_defaultEncoding_CA_0 2'b01
`define Src3CtrlEnum_defaultEncoding_CA_1 2'b10
`define DataSizeEnum_defaultEncoding_type [1:0]
`define DataSizeEnum_defaultEncoding_B 2'b00
`define DataSizeEnum_defaultEncoding_H 2'b01
`define DataSizeEnum_defaultEncoding_HA 2'b10
`define DataSizeEnum_defaultEncoding_W 2'b11
`define CRMoveCtrlEnum_defaultEncoding_type [1:0]
`define CRMoveCtrlEnum_defaultEncoding_MCRF 2'b00
`define CRMoveCtrlEnum_defaultEncoding_MCRXRX 2'b01
`define CRMoveCtrlEnum_defaultEncoding_MTCRF 2'b10
`define AluBitwiseCtrlEnum_defaultEncoding_type [3:0]
`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 4'b0000
`define AluBitwiseCtrlEnum_defaultEncoding_ANDC 4'b0001
`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 4'b0010
`define AluBitwiseCtrlEnum_defaultEncoding_ORC 4'b0011
`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 4'b0100
`define AluBitwiseCtrlEnum_defaultEncoding_XORC 4'b0101
`define AluBitwiseCtrlEnum_defaultEncoding_EQV 4'b0110
`define AluBitwiseCtrlEnum_defaultEncoding_NAND_1 4'b0111
`define AluBitwiseCtrlEnum_defaultEncoding_NOR_1 4'b1000
`define AluBitwiseCtrlEnum_defaultEncoding_EXTSB 4'b1001
`define AluBitwiseCtrlEnum_defaultEncoding_EXTSH 4'b1010
`define EndianEnum_defaultEncoding_type [0:0]
`define EndianEnum_defaultEncoding_BE 1'b0
`define EndianEnum_defaultEncoding_LE 1'b1
`define AluSpecCtrlEnum_defaultEncoding_type [2:0]
`define AluSpecCtrlEnum_defaultEncoding_CNTLZW 3'b000
`define AluSpecCtrlEnum_defaultEncoding_CNTTZW 3'b001
`define AluSpecCtrlEnum_defaultEncoding_POPCNTB 3'b010
`define AluSpecCtrlEnum_defaultEncoding_POPCNTW 3'b011
`define AluSpecCtrlEnum_defaultEncoding_CMPB 3'b100
`define AluSpecCtrlEnum_defaultEncoding_PRTYW 3'b101
`define AluRimiCtrlEnum_defaultEncoding_type [2:0]
`define AluRimiCtrlEnum_defaultEncoding_ROT 3'b000
`define AluRimiCtrlEnum_defaultEncoding_INS 3'b001
`define AluRimiCtrlEnum_defaultEncoding_SHIFTL 3'b010
`define AluRimiCtrlEnum_defaultEncoding_SHIFTR 3'b011
`define AluRimiCtrlEnum_defaultEncoding_SHIFTRA 3'b100
`define CRBusCmdEnum_defaultEncoding_type [4:0]
`define CRBusCmdEnum_defaultEncoding_NOP 5'b00000
`define CRBusCmdEnum_defaultEncoding_CR0 5'b00001
`define CRBusCmdEnum_defaultEncoding_CR1 5'b00010
`define CRBusCmdEnum_defaultEncoding_CR6 5'b00011
`define CRBusCmdEnum_defaultEncoding_CMP 5'b00100
`define CRBusCmdEnum_defaultEncoding_AND_1 5'b00101
`define CRBusCmdEnum_defaultEncoding_OR_1 5'b00110
`define CRBusCmdEnum_defaultEncoding_XOR_1 5'b00111
`define CRBusCmdEnum_defaultEncoding_NAND_1 5'b01000
`define CRBusCmdEnum_defaultEncoding_NOR_1 5'b01001
`define CRBusCmdEnum_defaultEncoding_EQV 5'b01010
`define CRBusCmdEnum_defaultEncoding_ANDC 5'b01011
`define CRBusCmdEnum_defaultEncoding_ORC 5'b01100
`define CRBusCmdEnum_defaultEncoding_MCRF 5'b01101
`define CRBusCmdEnum_defaultEncoding_MCRXRX 5'b01110
`define CRBusCmdEnum_defaultEncoding_MTOCRF 5'b01111
`define CRBusCmdEnum_defaultEncoding_MTCRF 5'b10000
`define CRBusCmdEnum_defaultEncoding_DEC 5'b10001
`define CRBusCmdEnum_defaultEncoding_LNK 5'b10010
`define CRBusCmdEnum_defaultEncoding_DECLNK 5'b10011
`define CRLogCtrlEnum_defaultEncoding_type [2:0]
`define CRLogCtrlEnum_defaultEncoding_AND_1 3'b000
`define CRLogCtrlEnum_defaultEncoding_OR_1 3'b001
`define CRLogCtrlEnum_defaultEncoding_XOR_1 3'b010
`define CRLogCtrlEnum_defaultEncoding_NAND_1 3'b011
`define CRLogCtrlEnum_defaultEncoding_NOR_1 3'b100
`define CRLogCtrlEnum_defaultEncoding_EQV 3'b101
`define CRLogCtrlEnum_defaultEncoding_ANDC 3'b110
`define CRLogCtrlEnum_defaultEncoding_ORC 3'b111
`define BranchCtrlEnum_defaultEncoding_type [2:0]
`define BranchCtrlEnum_defaultEncoding_NONE 3'b000
`define BranchCtrlEnum_defaultEncoding_BU 3'b001
`define BranchCtrlEnum_defaultEncoding_BC 3'b010
`define BranchCtrlEnum_defaultEncoding_BCLR 3'b011
`define BranchCtrlEnum_defaultEncoding_BCCTR 3'b100
`define BranchCtrlEnum_defaultEncoding_BCTAR 3'b101
`define EnvCtrlEnum_defaultEncoding_type [3:0]
`define EnvCtrlEnum_defaultEncoding_NONE 4'b0000
`define EnvCtrlEnum_defaultEncoding_MFMSR 4'b0001
`define EnvCtrlEnum_defaultEncoding_MTMSR 4'b0010
`define EnvCtrlEnum_defaultEncoding_SC 4'b0011
`define EnvCtrlEnum_defaultEncoding_SCV 4'b0100
`define EnvCtrlEnum_defaultEncoding_RFI 4'b0101
`define EnvCtrlEnum_defaultEncoding_RFSCV 4'b0110
`define EnvCtrlEnum_defaultEncoding_TW 4'b0111
`define EnvCtrlEnum_defaultEncoding_TWI 4'b1000
`define AluRimiAmtEnum_defaultEncoding_type [0:0]
`define AluRimiAmtEnum_defaultEncoding_IMM 1'b0
`define AluRimiAmtEnum_defaultEncoding_RB 1'b1
`define ExcpEnum_defaultEncoding_type [4:0]
`define ExcpEnum_defaultEncoding_NONE 5'b00000
`define ExcpEnum_defaultEncoding_SC 5'b00001
`define ExcpEnum_defaultEncoding_SCV 5'b00010
`define ExcpEnum_defaultEncoding_TRAP 5'b00011
`define ExcpEnum_defaultEncoding_RFI 5'b00100
`define ExcpEnum_defaultEncoding_RFSCV 5'b00101
`define ExcpEnum_defaultEncoding_DSI 5'b00110
`define ExcpEnum_defaultEncoding_DSI_PROT 5'b00111
`define ExcpEnum_defaultEncoding_DSS 5'b01000
`define ExcpEnum_defaultEncoding_ISI 5'b01001
`define ExcpEnum_defaultEncoding_ISI_PROT 5'b01010
`define ExcpEnum_defaultEncoding_ISS 5'b01011
`define ExcpEnum_defaultEncoding_ALG 5'b01100
`define ExcpEnum_defaultEncoding_PGM_ILL 5'b01101
`define ExcpEnum_defaultEncoding_PGM_PRV 5'b01110
`define ExcpEnum_defaultEncoding_FP 5'b01111
`define ExcpEnum_defaultEncoding_VEC 5'b10000
`define ExcpEnum_defaultEncoding_VSX 5'b10001
`define ExcpEnum_defaultEncoding_FAC 5'b10010
`define ExcpEnum_defaultEncoding_SR 5'b10011
`define ExcpEnum_defaultEncoding_MC 5'b10100
`define ExcpEnum_defaultEncoding_EXT 5'b10101
`define ExcpEnum_defaultEncoding_DEC 5'b10110
`define ExcpEnum_defaultEncoding_TR 5'b10111
`define ExcpEnum_defaultEncoding_PM 5'b11000
module InstructionCache (
input io_flush,
input io_cpu_prefetch_isValid,
output reg io_cpu_prefetch_haltIt,
input [31:0] io_cpu_prefetch_pc,
input io_cpu_fetch_isValid,
input io_cpu_fetch_isStuck,
input io_cpu_fetch_isRemoved,
input [31:0] io_cpu_fetch_pc,
output [31:0] io_cpu_fetch_data,
output io_cpu_fetch_mmuBus_cmd_isValid,
output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress,
output io_cpu_fetch_mmuBus_cmd_bypassTranslation,
input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress,
input io_cpu_fetch_mmuBus_rsp_isIoAccess,
input io_cpu_fetch_mmuBus_rsp_allowRead,
input io_cpu_fetch_mmuBus_rsp_allowWrite,
input io_cpu_fetch_mmuBus_rsp_allowExecute,
input io_cpu_fetch_mmuBus_rsp_exception,
input io_cpu_fetch_mmuBus_rsp_refilling,
output io_cpu_fetch_mmuBus_spr_valid,
output [9:0] io_cpu_fetch_mmuBus_spr_payload_id,
output [31:0] io_cpu_fetch_mmuBus_spr_payload_data,
output io_cpu_fetch_mmuBus_end,
input io_cpu_fetch_mmuBus_busy,
output [31:0] io_cpu_fetch_physicalAddress,
output [3:0] io_cpu_fetch_exceptionType,
input io_cpu_fetch_bypassTranslation,
output io_cpu_fetch_haltIt,
input io_cpu_decode_isValid,
input io_cpu_decode_isStuck,
input [31:0] io_cpu_decode_pc,
output [31:0] io_cpu_decode_physicalAddress,
output [31:0] io_cpu_decode_data,
output io_cpu_decode_cacheMiss,
output io_cpu_decode_error,
output io_cpu_decode_mmuRefilling,
output io_cpu_decode_mmuException,
input io_cpu_decode_isUser,
output [3:0] io_cpu_decode_exceptionType,
input io_cpu_fill_valid,
input [31:0] io_cpu_fill_payload,
output io_mem_cmd_valid,
input io_mem_cmd_ready,
output [31:0] io_mem_cmd_payload_address,
output [2:0] io_mem_cmd_payload_size,
input io_mem_rsp_valid,
input [31:0] io_mem_rsp_payload_data,
input io_mem_rsp_payload_error,
input io_spr_valid,
input [9:0] io_spr_payload_id,
input [31:0] io_spr_payload_data,
input clk,
input reset
);
reg [21:0] _zz_11_;
reg [31:0] _zz_12_;
wire _zz_13_;
wire _zz_14_;
wire [0:0] _zz_15_;
wire [0:0] _zz_16_;
wire [21:0] _zz_17_;
reg _zz_1_;
reg _zz_2_;
reg lineLoader_fire;
reg lineLoader_valid;
(* syn_keep , keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ;
reg lineLoader_hadError;
reg lineLoader_flushPending;
reg [7:0] lineLoader_flushCounter;
reg _zz_3_;
reg lineLoader_cmdSent;
reg lineLoader_wayToAllocate_willIncrement;
wire lineLoader_wayToAllocate_willClear;
wire lineLoader_wayToAllocate_willOverflowIfInc;
wire lineLoader_wayToAllocate_willOverflow;
(* syn_keep , keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ;
wire lineLoader_write_tag_0_valid;
wire [6:0] lineLoader_write_tag_0_payload_address;
wire lineLoader_write_tag_0_payload_data_valid;
wire lineLoader_write_tag_0_payload_data_error;
wire [19:0] lineLoader_write_tag_0_payload_data_address;
wire lineLoader_write_data_0_valid;
wire [9:0] lineLoader_write_data_0_payload_address;
wire [31:0] lineLoader_write_data_0_payload_data;
wire _zz_4_;
wire [6:0] _zz_5_;
wire _zz_6_;
wire fetchStage_read_waysValues_0_tag_valid;
wire fetchStage_read_waysValues_0_tag_error;
wire [19:0] fetchStage_read_waysValues_0_tag_address;
wire [21:0] _zz_7_;
wire [9:0] _zz_8_;
wire _zz_9_;
wire [31:0] fetchStage_read_waysValues_0_data;
reg [31:0] decodeStage_mmuRsp_physicalAddress;
reg decodeStage_mmuRsp_isIoAccess;
reg decodeStage_mmuRsp_allowRead;
reg decodeStage_mmuRsp_allowWrite;
reg decodeStage_mmuRsp_allowExecute;
reg decodeStage_mmuRsp_exception;
reg decodeStage_mmuRsp_refilling;
reg decodeStage_hit_tags_0_valid;
reg decodeStage_hit_tags_0_error;
reg [19:0] decodeStage_hit_tags_0_address;
wire decodeStage_hit_hits_0;
wire decodeStage_hit_valid;
reg [31:0] _zz_10_;
wire [31:0] decodeStage_hit_data;
wire decodeStage_protError;
reg [21:0] ways_0_tags [0:127];
reg [31:0] ways_0_datas [0:1023];
assign _zz_13_ = (! lineLoader_flushCounter[7]);
assign _zz_14_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid)));
assign _zz_15_ = _zz_7_[0 : 0];
assign _zz_16_ = _zz_7_[1 : 1];
assign _zz_17_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}};
always @ (posedge clk) begin
if(_zz_2_) begin
ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_17_;
end
end
always @ (posedge clk) begin
if(_zz_6_) begin
_zz_11_ <= ways_0_tags[_zz_5_];
end
end
always @ (posedge clk) begin
if(_zz_1_) begin
ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data;
end
end
always @ (posedge clk) begin
if(_zz_9_) begin
_zz_12_ <= ways_0_datas[_zz_8_];
end
end
always @ (*) begin
_zz_1_ = 1'b0;
if(lineLoader_write_data_0_valid)begin
_zz_1_ = 1'b1;
end
end
always @ (*) begin
_zz_2_ = 1'b0;
if(lineLoader_write_tag_0_valid)begin
_zz_2_ = 1'b1;
end
end
assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy;
always @ (*) begin
lineLoader_fire = 1'b0;
if(io_mem_rsp_valid)begin
if((lineLoader_wordIndex == (3'b111)))begin
lineLoader_fire = 1'b1;
end
end
end
always @ (*) begin
io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending);
if(_zz_13_)begin
io_cpu_prefetch_haltIt = 1'b1;
end
if((! _zz_3_))begin
io_cpu_prefetch_haltIt = 1'b1;
end
if(io_flush)begin
io_cpu_prefetch_haltIt = 1'b1;
end
end
assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent));
assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0};
assign io_mem_cmd_payload_size = (3'b101);
always @ (*) begin
lineLoader_wayToAllocate_willIncrement = 1'b0;
if((! lineLoader_valid))begin
lineLoader_wayToAllocate_willIncrement = 1'b1;
end
end
assign lineLoader_wayToAllocate_willClear = 1'b0;
assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1;
assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement);
assign _zz_4_ = 1'b1;
assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[7]));
assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]);
assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7];
assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error);
assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12];
assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_);
assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex};
assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data;
assign _zz_5_ = io_cpu_prefetch_pc[11 : 5];
assign _zz_6_ = (! io_cpu_fetch_isStuck);
assign _zz_7_ = _zz_11_;
assign fetchStage_read_waysValues_0_tag_valid = _zz_15_[0];
assign fetchStage_read_waysValues_0_tag_error = _zz_16_[0];
assign fetchStage_read_waysValues_0_tag_address = _zz_7_[21 : 2];
assign _zz_8_ = io_cpu_prefetch_pc[11 : 2];
assign _zz_9_ = (! io_cpu_fetch_isStuck);
assign fetchStage_read_waysValues_0_data = _zz_12_;
assign io_cpu_fetch_data = fetchStage_read_waysValues_0_data;
assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid;
assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc;
assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = io_cpu_fetch_bypassTranslation;
assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved);
assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress;
assign io_cpu_fetch_mmuBus_spr_valid = io_spr_valid;
assign io_cpu_fetch_mmuBus_spr_payload_id = io_spr_payload_id;
assign io_cpu_fetch_mmuBus_spr_payload_data = io_spr_payload_data;
assign decodeStage_hit_hits_0 = (decodeStage_hit_tags_0_valid && (decodeStage_hit_tags_0_address == decodeStage_mmuRsp_physicalAddress[31 : 12]));
assign decodeStage_hit_valid = (decodeStage_hit_hits_0 != (1'b0));
assign decodeStage_hit_data = _zz_10_;
assign io_cpu_decode_data = decodeStage_hit_data;
assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid);
assign io_cpu_decode_error = decodeStage_hit_tags_0_error;
assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling;
assign io_cpu_decode_mmuException = ((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_exception);
assign decodeStage_protError = (io_cpu_decode_isValid && ((! decodeStage_mmuRsp_refilling) && ((! decodeStage_mmuRsp_allowRead) || (! decodeStage_mmuRsp_allowExecute))));
assign io_cpu_decode_exceptionType = {{{decodeStage_mmuRsp_allowRead,decodeStage_mmuRsp_allowWrite},decodeStage_mmuRsp_allowExecute},decodeStage_protError};
assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress;
always @ (posedge clk or posedge reset) begin
if (reset) begin
lineLoader_valid <= 1'b0;
lineLoader_hadError <= 1'b0;
lineLoader_flushPending <= 1'b1;
lineLoader_cmdSent <= 1'b0;
lineLoader_wordIndex <= (3'b000);
end else begin
if(lineLoader_fire)begin
lineLoader_valid <= 1'b0;
end
if(lineLoader_fire)begin
lineLoader_hadError <= 1'b0;
end
if(io_cpu_fill_valid)begin
lineLoader_valid <= 1'b1;
end
if(io_flush)begin
lineLoader_flushPending <= 1'b1;
end
if(_zz_14_)begin
lineLoader_flushPending <= 1'b0;
end
if((io_mem_cmd_valid && io_mem_cmd_ready))begin
lineLoader_cmdSent <= 1'b1;
end
if(lineLoader_fire)begin
lineLoader_cmdSent <= 1'b0;
end
if(io_mem_rsp_valid)begin
lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001));
if(io_mem_rsp_payload_error)begin
lineLoader_hadError <= 1'b1;
end
end
end
end
always @ (posedge clk) begin
if(io_cpu_fill_valid)begin
lineLoader_address <= io_cpu_fill_payload;
end
if(_zz_13_)begin
lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01);
end
_zz_3_ <= lineLoader_flushCounter[7];
if(_zz_14_)begin
lineLoader_flushCounter <= 8'h0;
end
if((! io_cpu_decode_isStuck))begin
decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress;
decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuBus_rsp_isIoAccess;
decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuBus_rsp_allowRead;
decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuBus_rsp_allowWrite;
decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuBus_rsp_allowExecute;
decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuBus_rsp_exception;
decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuBus_rsp_refilling;
end
if((! io_cpu_decode_isStuck))begin
decodeStage_hit_tags_0_valid <= fetchStage_read_waysValues_0_tag_valid;
decodeStage_hit_tags_0_error <= fetchStage_read_waysValues_0_tag_error;
decodeStage_hit_tags_0_address <= fetchStage_read_waysValues_0_tag_address;
end
if((! io_cpu_decode_isStuck))begin
_zz_10_ <= fetchStage_read_waysValues_0_data;
end
end
endmodule
module DataCache (
input io_cpu_execute_isValid,
input [31:0] io_cpu_execute_address,
input io_cpu_execute_args_wr,
input [31:0] io_cpu_execute_args_data,
input [1:0] io_cpu_execute_args_size,
input io_cpu_memory_isValid,
input io_cpu_memory_isStuck,
input io_cpu_memory_isRemoved,
output io_cpu_memory_isWrite,
input [31:0] io_cpu_memory_address,
output io_cpu_memory_mmuBus_cmd_isValid,
output [31:0] io_cpu_memory_mmuBus_cmd_virtualAddress,
output io_cpu_memory_mmuBus_cmd_bypassTranslation,
input [31:0] io_cpu_memory_mmuBus_rsp_physicalAddress,
input io_cpu_memory_mmuBus_rsp_isIoAccess,
input io_cpu_memory_mmuBus_rsp_allowRead,
input io_cpu_memory_mmuBus_rsp_allowWrite,
input io_cpu_memory_mmuBus_rsp_allowExecute,
input io_cpu_memory_mmuBus_rsp_exception,
input io_cpu_memory_mmuBus_rsp_refilling,
output io_cpu_memory_mmuBus_spr_valid,
output [9:0] io_cpu_memory_mmuBus_spr_payload_id,
output [31:0] io_cpu_memory_mmuBus_spr_payload_data,
output io_cpu_memory_mmuBus_end,
input io_cpu_memory_mmuBus_busy,
input io_cpu_memory_bypassTranslation,
input io_cpu_writeBack_isValid,
input io_cpu_writeBack_isStuck,
input io_cpu_writeBack_isUser,
output reg io_cpu_writeBack_haltIt,
output io_cpu_writeBack_isWrite,
output reg [31:0] io_cpu_writeBack_data,
input [31:0] io_cpu_writeBack_address,
output io_cpu_writeBack_mmuException,
output io_cpu_writeBack_unalignedAccess,
output reg io_cpu_writeBack_accessError,
output [3:0] io_cpu_writeBack_exceptionType,
output reg io_cpu_redo,
input io_cpu_flush_valid,
output reg io_cpu_flush_ready,
output reg io_mem_cmd_valid,
input io_mem_cmd_ready,
output reg io_mem_cmd_payload_wr,
output reg [31:0] io_mem_cmd_payload_address,
output [31:0] io_mem_cmd_payload_data,
output [3:0] io_mem_cmd_payload_mask,
output reg [2:0] io_mem_cmd_payload_length,
output reg io_mem_cmd_payload_last,
input io_mem_rsp_valid,
input [31:0] io_mem_rsp_payload_data,
input io_mem_rsp_payload_error,
input clk,
input reset
);
reg [21:0] _zz_10_;
reg [31:0] _zz_11_;
wire _zz_12_;
wire _zz_13_;
wire _zz_14_;
wire _zz_15_;
wire _zz_16_;
wire [0:0] _zz_17_;
wire [0:0] _zz_18_;
wire [0:0] _zz_19_;
wire [2:0] _zz_20_;
wire [1:0] _zz_21_;
wire [21:0] _zz_22_;
reg _zz_1_;
reg _zz_2_;
wire haltCpu;
reg tagsReadCmd_valid;
reg [6:0] tagsReadCmd_payload;
reg tagsWriteCmd_valid;
reg [0:0] tagsWriteCmd_payload_way;
reg [6:0] tagsWriteCmd_payload_address;
reg tagsWriteCmd_payload_data_valid;
reg tagsWriteCmd_payload_data_error;
reg [19:0] tagsWriteCmd_payload_data_address;
reg tagsWriteLastCmd_valid;
reg [0:0] tagsWriteLastCmd_payload_way;
reg [6:0] tagsWriteLastCmd_payload_address;
reg tagsWriteLastCmd_payload_data_valid;
reg tagsWriteLastCmd_payload_data_error;
reg [19:0] tagsWriteLastCmd_payload_data_address;
reg dataReadCmd_valid;
reg [9:0] dataReadCmd_payload;
reg dataWriteCmd_valid;
reg [0:0] dataWriteCmd_payload_way;
reg [9:0] dataWriteCmd_payload_address;
reg [31:0] dataWriteCmd_payload_data;
reg [3:0] dataWriteCmd_payload_mask;
wire _zz_3_;
wire DC_DIR_tagsReadRsp_valid;
wire DC_DIR_tagsReadRsp_error;
wire [19:0] DC_DIR_tagsReadRsp_address;
wire [21:0] _zz_4_;
wire _zz_5_;
wire [31:0] DC_DIR_dataReadRsp;
reg [3:0] _zz_6_;
wire [3:0] stage0_mask;
wire [0:0] stage0_colisions;
reg stageA_request_wr;
reg [31:0] stageA_request_data;
reg [1:0] stageA_request_size;
reg [3:0] stageA_mask;
wire stageA_wayHits_0;
reg [0:0] stage0_colisions_regNextWhen;
wire [0:0] _zz_7_;
wire [0:0] stageA_colisions;
reg stageB_request_wr;
reg [31:0] stageB_request_data;
reg [1:0] stageB_request_size;
reg stageB_mmuRspFreeze;
reg [31:0] stageB_mmuRsp_physicalAddress;
reg stageB_mmuRsp_isIoAccess;
reg stageB_mmuRsp_allowRead;
reg stageB_mmuRsp_allowWrite;
reg stageB_mmuRsp_allowExecute;
reg stageB_mmuRsp_exception;
reg stageB_mmuRsp_refilling;
reg stageB_tagsReadRsp_0_valid;
reg stageB_tagsReadRsp_0_error;
reg [19:0] stageB_tagsReadRsp_0_address;
reg [31:0] stageB_dataReadRsp_0;
wire [0:0] _zz_8_;
reg [0:0] stageB_waysHits;
wire stageB_waysHit;
wire [31:0] stageB_dataMux;
reg [3:0] stageB_mask;
reg [0:0] stageB_colisions;
reg stageB_loaderValid;
reg stageB_flusher_valid;
reg stageB_flusher_start;
wire [31:0] stageB_requestDataBypass;
wire stageB_isAmo;
reg stageB_memCmdSent;
wire stageB_protError;
wire [0:0] _zz_9_;
reg loader_valid;
reg loader_counter_willIncrement;
wire loader_counter_willClear;
reg [2:0] loader_counter_valueNext;
reg [2:0] loader_counter_value;
wire loader_counter_willOverflowIfInc;
wire loader_counter_willOverflow;
reg [0:0] loader_waysAllocator;
reg loader_error;
reg [21:0] DC_DIR_tags [0:127];
reg [7:0] DC_DIR_data_symbol0 [0:1023];
reg [7:0] DC_DIR_data_symbol1 [0:1023];
reg [7:0] DC_DIR_data_symbol2 [0:1023];
reg [7:0] DC_DIR_data_symbol3 [0:1023];
reg [7:0] _zz_23_;
reg [7:0] _zz_24_;
reg [7:0] _zz_25_;
reg [7:0] _zz_26_;
assign _zz_12_ = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck));
assign _zz_13_ = ((((stageB_mmuRsp_refilling || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess) || stageB_protError);
assign _zz_14_ = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmo)));
assign _zz_15_ = (loader_valid && io_mem_rsp_valid);
assign _zz_16_ = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f);
assign _zz_17_ = _zz_4_[0 : 0];
assign _zz_18_ = _zz_4_[1 : 1];
assign _zz_19_ = loader_counter_willIncrement;
assign _zz_20_ = {2'd0, _zz_19_};
assign _zz_21_ = {loader_waysAllocator,loader_waysAllocator[0]};
assign _zz_22_ = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}};
always @ (posedge clk) begin
if(_zz_3_) begin
_zz_10_ <= DC_DIR_tags[tagsReadCmd_payload];
end
end
always @ (posedge clk) begin
if(_zz_2_) begin
DC_DIR_tags[tagsWriteCmd_payload_address] <= _zz_22_;
end
end
always @ (*) begin
_zz_11_ = {_zz_26_, _zz_25_, _zz_24_, _zz_23_};
end
always @ (posedge clk) begin
if(_zz_5_) begin
_zz_23_ <= DC_DIR_data_symbol0[dataReadCmd_payload];
_zz_24_ <= DC_DIR_data_symbol1[dataReadCmd_payload];
_zz_25_ <= DC_DIR_data_symbol2[dataReadCmd_payload];
_zz_26_ <= DC_DIR_data_symbol3[dataReadCmd_payload];
end
end
always @ (posedge clk) begin
if(dataWriteCmd_payload_mask[0] && _zz_1_) begin
DC_DIR_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0];
end
if(dataWriteCmd_payload_mask[1] && _zz_1_) begin
DC_DIR_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8];
end
if(dataWriteCmd_payload_mask[2] && _zz_1_) begin
DC_DIR_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16];
end
if(dataWriteCmd_payload_mask[3] && _zz_1_) begin
DC_DIR_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24];
end
end
always @ (*) begin
_zz_1_ = 1'b0;
if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin
_zz_1_ = 1'b1;
end
end
always @ (*) begin
_zz_2_ = 1'b0;
if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin
_zz_2_ = 1'b1;
end
end
assign haltCpu = 1'b0;
assign _zz_3_ = (tagsReadCmd_valid && (! io_cpu_memory_isStuck));
assign _zz_4_ = _zz_10_;
assign DC_DIR_tagsReadRsp_valid = _zz_17_[0];
assign DC_DIR_tagsReadRsp_error = _zz_18_[0];
assign DC_DIR_tagsReadRsp_address = _zz_4_[21 : 2];
assign _zz_5_ = (dataReadCmd_valid && (! io_cpu_memory_isStuck));
assign DC_DIR_dataReadRsp = _zz_11_;
always @ (*) begin
tagsReadCmd_valid = 1'b0;
if(_zz_12_)begin
tagsReadCmd_valid = 1'b1;
end
end
always @ (*) begin
tagsReadCmd_payload = 7'h0;
if(_zz_12_)begin
tagsReadCmd_payload = io_cpu_execute_address[11 : 5];
end
end
always @ (*) begin
dataReadCmd_valid = 1'b0;
if(_zz_12_)begin
dataReadCmd_valid = 1'b1;
end
end
always @ (*) begin
dataReadCmd_payload = 10'h0;
if(_zz_12_)begin
dataReadCmd_payload = io_cpu_execute_address[11 : 2];
end
end
always @ (*) begin
tagsWriteCmd_valid = 1'b0;
if(stageB_flusher_valid)begin
tagsWriteCmd_valid = stageB_flusher_valid;
end
if(_zz_13_)begin
tagsWriteCmd_valid = 1'b0;
end
if(loader_counter_willOverflow)begin
tagsWriteCmd_valid = 1'b1;
end
end
always @ (*) begin
tagsWriteCmd_payload_way = (1'bx);
if(stageB_flusher_valid)begin
tagsWriteCmd_payload_way = (1'b1);
end
if(loader_counter_willOverflow)begin
tagsWriteCmd_payload_way = loader_waysAllocator;
end
end
always @ (*) begin
tagsWriteCmd_payload_address = 7'h0;
if(stageB_flusher_valid)begin
tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5];
end
if(loader_counter_willOverflow)begin
tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5];
end
end
always @ (*) begin
tagsWriteCmd_payload_data_valid = 1'bx;
if(stageB_flusher_valid)begin
tagsWriteCmd_payload_data_valid = 1'b0;
end
if(loader_counter_willOverflow)begin
tagsWriteCmd_payload_data_valid = 1'b1;
end
end
always @ (*) begin
tagsWriteCmd_payload_data_error = 1'bx;
if(loader_counter_willOverflow)begin
tagsWriteCmd_payload_data_error = (loader_error || io_mem_rsp_payload_error);
end
end
always @ (*) begin
tagsWriteCmd_payload_data_address = 20'h0;
if(loader_counter_willOverflow)begin
tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12];
end
end
always @ (*) begin
dataWriteCmd_valid = 1'b0;
if(io_cpu_writeBack_isValid)begin
if(! stageB_mmuRsp_isIoAccess) begin
if(_zz_14_)begin
if((stageB_request_wr && stageB_waysHit))begin
dataWriteCmd_valid = 1'b1;
end
end
end
end
if(_zz_13_)begin
dataWriteCmd_valid = 1'b0;
end
if(_zz_15_)begin
dataWriteCmd_valid = 1'b1;
end
end
always @ (*) begin
dataWriteCmd_payload_way = (1'bx);
if(io_cpu_writeBack_isValid)begin
if(! stageB_mmuRsp_isIoAccess) begin
if(_zz_14_)begin
dataWriteCmd_payload_way = stageB_waysHits;
end
end
end
if(_zz_15_)begin
dataWriteCmd_payload_way = loader_waysAllocator;
end
end
always @ (*) begin
dataWriteCmd_payload_address = 10'h0;
if(io_cpu_writeBack_isValid)begin
if(! stageB_mmuRsp_isIoAccess) begin
if(_zz_14_)begin
dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2];
end
end
end
if(_zz_15_)begin
dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value};
end
end
always @ (*) begin
dataWriteCmd_payload_data = 32'h0;
if(io_cpu_writeBack_isValid)begin
if(! stageB_mmuRsp_isIoAccess) begin
if(_zz_14_)begin
dataWriteCmd_payload_data = stageB_requestDataBypass;
end
end
end
if(_zz_15_)begin
dataWriteCmd_payload_data = io_mem_rsp_payload_data;
end
end
always @ (*) begin
dataWriteCmd_payload_mask = (4'bxxxx);
if(io_cpu_writeBack_isValid)begin
if(! stageB_mmuRsp_isIoAccess) begin
if(_zz_14_)begin
dataWriteCmd_payload_mask = stageB_mask;
end
end
end
if(_zz_15_)begin
dataWriteCmd_payload_mask = (4'b1111);
end
end
always @ (*) begin
case(io_cpu_execute_args_size)
2'b00 : begin
_zz_6_ = (4'b0001);
end
2'b01 : begin
_zz_6_ = (4'b0011);
end
default : begin
_zz_6_ = (4'b1111);
end
endcase
end
assign stage0_mask = (_zz_6_ <<< io_cpu_execute_address[1 : 0]);
assign stage0_colisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_execute_address[11 : 2])) && ((stage0_mask & dataWriteCmd_payload_mask) != (4'b0000)));
assign io_cpu_memory_mmuBus_cmd_isValid = io_cpu_memory_isValid;
assign io_cpu_memory_mmuBus_cmd_virtualAddress = io_cpu_memory_address;
assign io_cpu_memory_mmuBus_cmd_bypassTranslation = io_cpu_memory_bypassTranslation;
assign io_cpu_memory_mmuBus_end = ((! io_cpu_memory_isStuck) || io_cpu_memory_isRemoved);
assign io_cpu_memory_mmuBus_spr_valid = 1'b0;
assign io_cpu_memory_mmuBus_spr_payload_id = 10'h0;
assign io_cpu_memory_mmuBus_spr_payload_data = 32'h0;
assign io_cpu_memory_isWrite = stageA_request_wr;
assign stageA_wayHits_0 = ((io_cpu_memory_mmuBus_rsp_physicalAddress[31 : 12] == DC_DIR_tagsReadRsp_address) && DC_DIR_tagsReadRsp_valid);
assign _zz_7_[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_memory_address[11 : 2])) && ((stageA_mask & dataWriteCmd_payload_mask) != (4'b0000)));
assign stageA_colisions = (stage0_colisions_regNextWhen | _zz_7_);
always @ (*) begin
stageB_mmuRspFreeze = 1'b0;
if((stageB_loaderValid || loader_valid))begin
stageB_mmuRspFreeze = 1'b1;
end
end
assign _zz_8_[0] = stageA_wayHits_0;
assign stageB_waysHit = (stageB_waysHits != (1'b0));
assign stageB_dataMux = stageB_dataReadRsp_0;
always @ (*) begin
stageB_loaderValid = 1'b0;
if(io_cpu_writeBack_isValid)begin
if(! stageB_mmuRsp_isIoAccess) begin
if(! _zz_14_) begin
if(io_mem_cmd_ready)begin
stageB_loaderValid = 1'b1;
end
end
end
end
if(_zz_13_)begin
stageB_loaderValid = 1'b0;
end
end
always @ (*) begin
io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid;
if(stageB_flusher_valid)begin
io_cpu_writeBack_haltIt = 1'b1;
end
if(io_cpu_writeBack_isValid)begin
if(stageB_mmuRsp_isIoAccess)begin
if((stageB_request_wr ? io_mem_cmd_ready : io_mem_rsp_valid))begin
io_cpu_writeBack_haltIt = 1'b0;
end
end else begin
if(_zz_14_)begin
if(((! stageB_request_wr) || io_mem_cmd_ready))begin
io_cpu_writeBack_haltIt = 1'b0;
end
end
end
end
if(_zz_13_)begin
io_cpu_writeBack_haltIt = 1'b0;
end
end
always @ (*) begin
io_cpu_flush_ready = 1'b0;
if(stageB_flusher_start)begin
io_cpu_flush_ready = 1'b1;
end
end
assign stageB_requestDataBypass = stageB_request_data;
assign stageB_isAmo = 1'b0;
always @ (*) begin
io_cpu_redo = 1'b0;
if(io_cpu_writeBack_isValid)begin
if(! stageB_mmuRsp_isIoAccess) begin
if(_zz_14_)begin
if((((! stageB_request_wr) || stageB_isAmo) && ((stageB_colisions & stageB_waysHits) != (1'b0))))begin
io_cpu_redo = 1'b1;
end
end
end
end
if((io_cpu_writeBack_isValid && stageB_mmuRsp_refilling))begin
io_cpu_redo = 1'b1;
end
if(loader_valid)begin
io_cpu_redo = 1'b1;
end
end
always @ (*) begin
io_cpu_writeBack_accessError = 1'b0;
if(stageB_mmuRsp_isIoAccess)begin
io_cpu_writeBack_accessError = (io_mem_rsp_valid && io_mem_rsp_payload_error);
end else begin
io_cpu_writeBack_accessError = ((stageB_waysHits & _zz_9_) != (1'b0));
end
end
assign io_cpu_writeBack_mmuException = (io_cpu_writeBack_isValid && stageB_mmuRsp_exception);
assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && (((stageB_request_size == (2'b10)) && (stageB_mmuRsp_physicalAddress[1 : 0] != (2'b00))) || ((stageB_request_size == (2'b01)) && (stageB_mmuRsp_physicalAddress[0 : 0] != (1'b0)))));
assign io_cpu_writeBack_isWrite = stageB_request_wr;
assign stageB_protError = (io_cpu_writeBack_isValid && ((! stageB_mmuRsp_refilling) && (((! stageB_mmuRsp_allowRead) && (! stageB_request_wr)) || ((! stageB_mmuRsp_allowWrite) && stageB_request_wr))));
assign io_cpu_writeBack_exceptionType = {{{stageB_mmuRsp_allowRead,stageB_mmuRsp_allowWrite},stageB_mmuRsp_allowExecute},stageB_protError};
always @ (*) begin
io_mem_cmd_valid = 1'b0;
if(io_cpu_writeBack_isValid)begin
if(stageB_mmuRsp_isIoAccess)begin
io_mem_cmd_valid = (! stageB_memCmdSent);
end else begin
if(_zz_14_)begin
if(stageB_request_wr)begin
io_mem_cmd_valid = 1'b1;
end
end else begin
if((! stageB_memCmdSent))begin
io_mem_cmd_valid = 1'b1;
end
end
end
end
if(_zz_13_)begin
io_mem_cmd_valid = 1'b0;
end
end
always @ (*) begin
io_mem_cmd_payload_address = 32'h0;
if(io_cpu_writeBack_isValid)begin
if(stageB_mmuRsp_isIoAccess)begin
io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)};
end else begin
if(_zz_14_)begin
io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)};
end else begin
io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0};
end
end
end
end
always @ (*) begin
io_mem_cmd_payload_length = (3'bxxx);
if(io_cpu_writeBack_isValid)begin
if(stageB_mmuRsp_isIoAccess)begin
io_mem_cmd_payload_length = (3'b000);
end else begin
if(_zz_14_)begin
io_mem_cmd_payload_length = (3'b000);
end else begin
io_mem_cmd_payload_length = (3'b111);
end
end
end
end
always @ (*) begin
io_mem_cmd_payload_last = 1'bx;
if(io_cpu_writeBack_isValid)begin
if(stageB_mmuRsp_isIoAccess)begin
io_mem_cmd_payload_last = 1'b1;
end else begin
if(_zz_14_)begin
io_mem_cmd_payload_last = 1'b1;
end else begin
io_mem_cmd_payload_last = 1'b1;
end
end
end
end
always @ (*) begin
io_mem_cmd_payload_wr = stageB_request_wr;
if(io_cpu_writeBack_isValid)begin
if(! stageB_mmuRsp_isIoAccess) begin
if(! _zz_14_) begin
io_mem_cmd_payload_wr = 1'b0;
end
end
end
end
assign io_mem_cmd_payload_mask = stageB_mask;
assign io_mem_cmd_payload_data = stageB_requestDataBypass;
always @ (*) begin
if(stageB_mmuRsp_isIoAccess)begin
io_cpu_writeBack_data = io_mem_rsp_payload_data;
end else begin
io_cpu_writeBack_data = stageB_dataMux;
end
end
assign _zz_9_[0] = stageB_tagsReadRsp_0_error;
always @ (*) begin
loader_counter_willIncrement = 1'b0;
if(_zz_15_)begin
loader_counter_willIncrement = 1'b1;
end
end
assign loader_counter_willClear = 1'b0;
assign loader_counter_willOverflowIfInc = (loader_counter_value == (3'b111));
assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement);
always @ (*) begin
loader_counter_valueNext = (loader_counter_value + _zz_20_);
if(loader_counter_willClear)begin
loader_counter_valueNext = (3'b000);
end
end
always @ (posedge clk) begin
tagsWriteLastCmd_valid <= tagsWriteCmd_valid;
tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way;
tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address;
tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid;
tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error;
tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address;
if((! io_cpu_memory_isStuck))begin
stageA_request_wr <= io_cpu_execute_args_wr;
stageA_request_data <= io_cpu_execute_args_data;
stageA_request_size <= io_cpu_execute_args_size;
end
if((! io_cpu_memory_isStuck))begin
stageA_mask <= stage0_mask;
end
if((! io_cpu_memory_isStuck))begin
stage0_colisions_regNextWhen <= stage0_colisions;
end
if((! io_cpu_writeBack_isStuck))begin
stageB_request_wr <= stageA_request_wr;
stageB_request_data <= stageA_request_data;
stageB_request_size <= stageA_request_size;
end
if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin
stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuBus_rsp_physicalAddress;
stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuBus_rsp_isIoAccess;
stageB_mmuRsp_allowRead <= io_cpu_memory_mmuBus_rsp_allowRead;
stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuBus_rsp_allowWrite;
stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuBus_rsp_allowExecute;
stageB_mmuRsp_exception <= io_cpu_memory_mmuBus_rsp_exception;
stageB_mmuRsp_refilling <= io_cpu_memory_mmuBus_rsp_refilling;
end
if((! io_cpu_writeBack_isStuck))begin
stageB_tagsReadRsp_0_valid <= DC_DIR_tagsReadRsp_valid;
stageB_tagsReadRsp_0_error <= DC_DIR_tagsReadRsp_error;
stageB_tagsReadRsp_0_address <= DC_DIR_tagsReadRsp_address;
end
if((! io_cpu_writeBack_isStuck))begin
stageB_dataReadRsp_0 <= DC_DIR_dataReadRsp;
end
if((! io_cpu_writeBack_isStuck))begin
stageB_waysHits <= _zz_8_;
end
if((! io_cpu_writeBack_isStuck))begin
stageB_mask <= stageA_mask;
end
if((! io_cpu_writeBack_isStuck))begin
stageB_colisions <= stageA_colisions;
end
if(stageB_flusher_valid)begin
if(_zz_16_)begin
stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01);
end
end
if(stageB_flusher_start)begin
stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0;
end
end
always @ (posedge clk or posedge reset) begin
if (reset) begin
stageB_flusher_valid <= 1'b0;
stageB_flusher_start <= 1'b1;
stageB_memCmdSent <= 1'b0;
loader_valid <= 1'b0;
loader_counter_value <= (3'b000);
loader_waysAllocator <= (1'b1);
loader_error <= 1'b0;
end else begin
if(stageB_flusher_valid)begin
if(! _zz_16_) begin
stageB_flusher_valid <= 1'b0;
end
end
stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo));
if(stageB_flusher_start)begin
stageB_flusher_valid <= 1'b1;
end
if(io_mem_cmd_ready)begin
stageB_memCmdSent <= 1'b1;
end
if((! io_cpu_writeBack_isStuck))begin
stageB_memCmdSent <= 1'b0;
end
if(stageB_loaderValid)begin
loader_valid <= 1'b1;
end
loader_counter_value <= loader_counter_valueNext;
if(_zz_15_)begin
loader_error <= (loader_error || io_mem_rsp_payload_error);
end
if(loader_counter_willOverflow)begin
loader_valid <= 1'b0;
loader_error <= 1'b0;
end
if((! loader_valid))begin
loader_waysAllocator <= _zz_21_[0:0];
end
end
end
endmodule
module A2P_WB (
input [31:0] externalResetVector,
input timerInterrupt,
input externalInterrupt,
input softwareInterrupt,
input externalInterruptS,
output reg iBusWB_CYC,
output reg iBusWB_STB,
input iBusWB_ACK,
output iBusWB_WE,
output [29:0] iBusWB_ADR,
input [31:0] iBusWB_DAT_MISO,
output [31:0] iBusWB_DAT_MOSI,
output [3:0] iBusWB_SEL,
input iBusWB_ERR,
output [1:0] iBusWB_BTE,
output [2:0] iBusWB_CTI,
output dBusWB_CYC,
output dBusWB_STB,
input dBusWB_ACK,
output dBusWB_WE,
output [29:0] dBusWB_ADR,
input [31:0] dBusWB_DAT_MISO,
output [31:0] dBusWB_DAT_MOSI,
output [3:0] dBusWB_SEL,
input dBusWB_ERR,
output [1:0] dBusWB_BTE,
output [2:0] dBusWB_CTI,
input clk,
input reset
);
wire _zz_366_;
wire _zz_367_;
wire _zz_368_;
wire _zz_369_;
wire _zz_370_;
wire _zz_371_;
wire _zz_372_;
wire _zz_373_;
reg _zz_374_;
wire [9:0] _zz_375_;
wire _zz_376_;
wire [31:0] _zz_377_;
reg [31:0] _zz_378_;
wire _zz_379_;
wire [31:0] _zz_380_;
reg _zz_381_;
wire _zz_382_;
wire _zz_383_;
wire _zz_384_;
wire [31:0] _zz_385_;
wire _zz_386_;
wire _zz_387_;
reg [53:0] _zz_388_;
reg [31:0] _zz_389_;
reg [31:0] _zz_390_;
reg [31:0] _zz_391_;
reg [31:0] _zz_392_;
wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress;
wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt;
wire [3:0] IBusCachedPlugin_cache_io_cpu_fetch_exceptionType;
wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress;
wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation;
wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end;
wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_spr_valid;
wire [9:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_spr_payload_id;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_spr_payload_data;
wire IBusCachedPlugin_cache_io_cpu_decode_error;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuException;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data;
wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress;
wire [3:0] IBusCachedPlugin_cache_io_cpu_decode_exceptionType;
wire IBusCachedPlugin_cache_io_mem_cmd_valid;
wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address;
wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size;
wire dataCache_1__io_cpu_memory_isWrite;
wire dataCache_1__io_cpu_memory_mmuBus_cmd_isValid;
wire [31:0] dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress;
wire dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation;
wire dataCache_1__io_cpu_memory_mmuBus_end;
wire dataCache_1__io_cpu_memory_mmuBus_spr_valid;
wire [9:0] dataCache_1__io_cpu_memory_mmuBus_spr_payload_id;
wire [31:0] dataCache_1__io_cpu_memory_mmuBus_spr_payload_data;
wire dataCache_1__io_cpu_writeBack_haltIt;
wire [31:0] dataCache_1__io_cpu_writeBack_data;
wire dataCache_1__io_cpu_writeBack_mmuException;
wire dataCache_1__io_cpu_writeBack_unalignedAccess;
wire dataCache_1__io_cpu_writeBack_accessError;
wire dataCache_1__io_cpu_writeBack_isWrite;
wire [3:0] dataCache_1__io_cpu_writeBack_exceptionType;
wire dataCache_1__io_cpu_flush_ready;
wire dataCache_1__io_cpu_redo;
wire dataCache_1__io_mem_cmd_valid;
wire dataCache_1__io_mem_cmd_payload_wr;
wire [31:0] dataCache_1__io_mem_cmd_payload_address;
wire [31:0] dataCache_1__io_mem_cmd_payload_data;
wire [3:0] dataCache_1__io_mem_cmd_payload_mask;
wire [2:0] dataCache_1__io_mem_cmd_payload_length;
wire dataCache_1__io_mem_cmd_payload_last;
wire _zz_393_;
wire _zz_394_;
wire _zz_395_;
wire _zz_396_;
wire _zz_397_;
wire _zz_398_;
wire _zz_399_;
wire _zz_400_;
wire _zz_401_;
wire _zz_402_;
wire _zz_403_;
wire _zz_404_;
wire _zz_405_;
wire _zz_406_;
wire _zz_407_;
wire _zz_408_;
wire _zz_409_;
wire _zz_410_;
wire _zz_411_;
wire _zz_412_;
wire _zz_413_;
wire _zz_414_;
wire _zz_415_;
wire _zz_416_;
wire _zz_417_;
wire _zz_418_;
wire _zz_419_;
wire _zz_420_;
wire _zz_421_;
wire _zz_422_;
wire _zz_423_;
wire _zz_424_;
wire _zz_425_;
wire _zz_426_;
wire _zz_427_;
wire _zz_428_;
wire _zz_429_;
wire _zz_430_;
wire _zz_431_;
wire _zz_432_;
wire _zz_433_;
wire _zz_434_;
wire _zz_435_;
wire _zz_436_;
wire _zz_437_;
wire _zz_438_;
wire _zz_439_;
wire [7:0] _zz_440_;
wire [2:0] _zz_441_;
wire [2:0] _zz_442_;
wire [1:0] _zz_443_;
wire [1:0] _zz_444_;
wire [2:0] _zz_445_;
wire [0:0] _zz_446_;
wire [0:0] _zz_447_;
wire [0:0] _zz_448_;
wire [0:0] _zz_449_;
wire [0:0] _zz_450_;
wire [0:0] _zz_451_;
wire [51:0] _zz_452_;
wire [51:0] _zz_453_;
wire [51:0] _zz_454_;
wire [32:0] _zz_455_;
wire [51:0] _zz_456_;
wire [49:0] _zz_457_;
wire [51:0] _zz_458_;
wire [49:0] _zz_459_;
wire [51:0] _zz_460_;
wire [0:0] _zz_461_;
wire [0:0] _zz_462_;
wire [0:0] _zz_463_;
wire [0:0] _zz_464_;
wire [0:0] _zz_465_;
wire [0:0] _zz_466_;
wire [0:0] _zz_467_;
wire [0:0] _zz_468_;
wire [0:0] _zz_469_;
wire [0:0] _zz_470_;
wire [0:0] _zz_471_;
wire [0:0] _zz_472_;
wire [0:0] _zz_473_;
wire [0:0] _zz_474_;
wire [0:0] _zz_475_;
wire [0:0] _zz_476_;
wire [0:0] _zz_477_;
wire [0:0] _zz_478_;
wire [0:0] _zz_479_;
wire [0:0] _zz_480_;
wire [0:0] _zz_481_;
wire [0:0] _zz_482_;
wire [0:0] _zz_483_;
wire [0:0] _zz_484_;
wire [0:0] _zz_485_;
wire [0:0] _zz_486_;
wire [0:0] _zz_487_;
wire [0:0] _zz_488_;
wire [0:0] _zz_489_;
wire [0:0] _zz_490_;
wire [0:0] _zz_491_;
wire [0:0] _zz_492_;
wire [0:0] _zz_493_;
wire [0:0] _zz_494_;
wire [0:0] _zz_495_;
wire [0:0] _zz_496_;
wire [2:0] _zz_497_;
wire [2:0] _zz_498_;
wire [31:0] _zz_499_;
wire [9:0] _zz_500_;
wire [29:0] _zz_501_;
wire [9:0] _zz_502_;
wire [19:0] _zz_503_;
wire [1:0] _zz_504_;
wire [0:0] _zz_505_;
wire [1:0] _zz_506_;
wire [0:0] _zz_507_;
wire [1:0] _zz_508_;
wire [1:0] _zz_509_;
wire [0:0] _zz_510_;
wire [1:0] _zz_511_;
wire [0:0] _zz_512_;
wire [1:0] _zz_513_;
wire [2:0] _zz_514_;
wire [2:0] _zz_515_;
wire [10:0] _zz_516_;
wire [31:0] _zz_517_;
wire [10:0] _zz_518_;
wire [31:0] _zz_519_;
wire [31:0] _zz_520_;
wire [31:0] _zz_521_;
wire [31:0] _zz_522_;
wire [31:0] _zz_523_;
wire [31:0] _zz_524_;
wire [31:0] _zz_525_;
wire [5:0] _zz_526_;
wire [5:0] _zz_527_;
wire [31:0] _zz_528_;
wire [31:0] _zz_529_;
wire [31:0] _zz_530_;
wire [31:0] _zz_531_;
wire [31:0] _zz_532_;
wire [31:0] _zz_533_;
wire [31:0] _zz_534_;
wire [31:0] _zz_535_;
wire [31:0] _zz_536_;
wire [31:0] _zz_537_;
wire [31:0] _zz_538_;
wire [31:0] _zz_539_;
wire [31:0] _zz_540_;
wire [31:0] _zz_541_;
wire [31:0] _zz_542_;
wire [31:0] _zz_543_;
wire [31:0] _zz_544_;
wire [31:0] _zz_545_;
wire [31:0] _zz_546_;
wire [31:0] _zz_547_;
wire [31:0] _zz_548_;
wire [31:0] _zz_549_;
wire [31:0] _zz_550_;
wire [31:0] _zz_551_;
wire [31:0] _zz_552_;
wire [4:0] _zz_553_;
wire [2:0] _zz_554_;
wire [31:0] _zz_555_;
wire [31:0] _zz_556_;
wire [31:0] _zz_557_;
wire [32:0] _zz_558_;
wire [32:0] _zz_559_;
wire [31:0] _zz_560_;
wire [31:0] _zz_561_;
wire [65:0] _zz_562_;
wire [65:0] _zz_563_;
wire [31:0] _zz_564_;
wire [31:0] _zz_565_;
wire [0:0] _zz_566_;
wire [5:0] _zz_567_;
wire [32:0] _zz_568_;
wire [31:0] _zz_569_;
wire [31:0] _zz_570_;
wire [32:0] _zz_571_;
wire [32:0] _zz_572_;
wire [32:0] _zz_573_;
wire [32:0] _zz_574_;
wire [0:0] _zz_575_;
wire [32:0] _zz_576_;
wire [0:0] _zz_577_;
wire [32:0] _zz_578_;
wire [0:0] _zz_579_;
wire [31:0] _zz_580_;
wire [4:0] _zz_581_;
wire [4:0] _zz_582_;
wire [4:0] _zz_583_;
wire [4:0] _zz_584_;
wire [4:0] _zz_585_;
wire [4:0] _zz_586_;
wire [4:0] _zz_587_;
wire [4:0] _zz_588_;
wire [4:0] _zz_589_;
wire [4:0] _zz_590_;
wire [4:0] _zz_591_;
wire [4:0] _zz_592_;
wire [4:0] _zz_593_;
wire [4:0] _zz_594_;
wire [4:0] _zz_595_;
wire [4:0] _zz_596_;
wire [4:0] _zz_597_;
wire [4:0] _zz_598_;
wire [4:0] _zz_599_;
wire [4:0] _zz_600_;
wire [4:0] _zz_601_;
wire [4:0] _zz_602_;
wire [4:0] _zz_603_;
wire [4:0] _zz_604_;
wire [31:0] _zz_605_;
wire [31:0] _zz_606_;
wire [31:0] _zz_607_;
wire [31:0] _zz_608_;
wire [1:0] _zz_609_;
wire [4:0] _zz_610_;
wire [1:0] _zz_611_;
wire [4:0] _zz_612_;
wire [4:0] _zz_613_;
wire [1:0] _zz_614_;
wire [4:0] _zz_615_;
wire [4:0] _zz_616_;
wire [1:0] _zz_617_;
wire [4:0] _zz_618_;
wire [4:0] _zz_619_;
wire [1:0] _zz_620_;
wire [4:0] _zz_621_;
wire [3:0] _zz_622_;
wire [1:0] _zz_623_;
wire [3:0] _zz_624_;
wire [3:0] _zz_625_;
wire [1:0] _zz_626_;
wire [3:0] _zz_627_;
wire [2:0] _zz_628_;
wire [1:0] _zz_629_;
wire [2:0] _zz_630_;
wire [1:0] _zz_631_;
wire [1:0] _zz_632_;
wire [1:0] _zz_633_;
wire [1:0] _zz_634_;
wire [31:0] _zz_635_;
wire [31:0] _zz_636_;
wire [31:0] _zz_637_;
wire [31:0] _zz_638_;
wire [31:0] _zz_639_;
wire [31:0] _zz_640_;
wire [31:0] _zz_641_;
wire [31:0] _zz_642_;
wire [0:0] _zz_643_;
wire [0:0] _zz_644_;
wire [0:0] _zz_645_;
wire [0:0] _zz_646_;
wire [0:0] _zz_647_;
wire [0:0] _zz_648_;
wire [0:0] _zz_649_;
wire [0:0] _zz_650_;
wire [0:0] _zz_651_;
wire [0:0] _zz_652_;
wire [0:0] _zz_653_;
wire [0:0] _zz_654_;
wire [0:0] _zz_655_;
wire [26:0] _zz_656_;
wire [53:0] _zz_657_;
wire _zz_658_;
wire _zz_659_;
wire _zz_660_;
wire [1:0] _zz_661_;
wire [0:0] _zz_662_;
wire [92:0] _zz_663_;
wire [0:0] _zz_664_;
wire [84:0] _zz_665_;
wire [31:0] _zz_666_;
wire _zz_667_;
wire [0:0] _zz_668_;
wire [75:0] _zz_669_;
wire [31:0] _zz_670_;
wire [31:0] _zz_671_;
wire _zz_672_;
wire [0:0] _zz_673_;
wire [68:0] _zz_674_;
wire [31:0] _zz_675_;
wire [31:0] _zz_676_;
wire [31:0] _zz_677_;
wire _zz_678_;
wire [0:0] _zz_679_;
wire [62:0] _zz_680_;
wire [31:0] _zz_681_;
wire [31:0] _zz_682_;
wire [31:0] _zz_683_;
wire _zz_684_;
wire [0:0] _zz_685_;
wire [56:0] _zz_686_;
wire [31:0] _zz_687_;
wire [31:0] _zz_688_;
wire [31:0] _zz_689_;
wire _zz_690_;
wire [0:0] _zz_691_;
wire [50:0] _zz_692_;
wire [31:0] _zz_693_;
wire [31:0] _zz_694_;
wire [31:0] _zz_695_;
wire _zz_696_;
wire [0:0] _zz_697_;
wire [44:0] _zz_698_;
wire [31:0] _zz_699_;
wire [31:0] _zz_700_;
wire [31:0] _zz_701_;
wire _zz_702_;
wire [0:0] _zz_703_;
wire [38:0] _zz_704_;
wire [31:0] _zz_705_;
wire [31:0] _zz_706_;
wire [31:0] _zz_707_;
wire _zz_708_;
wire [0:0] _zz_709_;
wire [32:0] _zz_710_;
wire [31:0] _zz_711_;
wire [31:0] _zz_712_;
wire [31:0] _zz_713_;
wire _zz_714_;
wire [0:0] _zz_715_;
wire [26:0] _zz_716_;
wire [31:0] _zz_717_;
wire [31:0] _zz_718_;
wire [31:0] _zz_719_;
wire _zz_720_;
wire [0:0] _zz_721_;
wire [20:0] _zz_722_;
wire [31:0] _zz_723_;
wire [31:0] _zz_724_;
wire [31:0] _zz_725_;
wire _zz_726_;
wire [0:0] _zz_727_;
wire [14:0] _zz_728_;
wire [31:0] _zz_729_;
wire [31:0] _zz_730_;
wire [31:0] _zz_731_;
wire _zz_732_;
wire [0:0] _zz_733_;
wire [8:0] _zz_734_;
wire [31:0] _zz_735_;
wire [31:0] _zz_736_;
wire [31:0] _zz_737_;
wire _zz_738_;
wire [0:0] _zz_739_;
wire [2:0] _zz_740_;
wire [31:0] _zz_741_;
wire [31:0] _zz_742_;
wire _zz_743_;
wire [0:0] _zz_744_;
wire [0:0] _zz_745_;
wire _zz_746_;
wire _zz_747_;
wire [3:0] _zz_748_;
wire [3:0] _zz_749_;
wire _zz_750_;
wire [0:0] _zz_751_;
wire [73:0] _zz_752_;
wire [31:0] _zz_753_;
wire [0:0] _zz_754_;
wire [0:0] _zz_755_;
wire _zz_756_;
wire [0:0] _zz_757_;
wire [5:0] _zz_758_;
wire [0:0] _zz_759_;
wire [18:0] _zz_760_;
wire [0:0] _zz_761_;
wire [0:0] _zz_762_;
wire _zz_763_;
wire [0:0] _zz_764_;
wire [70:0] _zz_765_;
wire [31:0] _zz_766_;
wire [31:0] _zz_767_;
wire [31:0] _zz_768_;
wire [31:0] _zz_769_;
wire [31:0] _zz_770_;
wire _zz_771_;
wire [0:0] _zz_772_;
wire [3:0] _zz_773_;
wire [31:0] _zz_774_;
wire [31:0] _zz_775_;
wire [0:0] _zz_776_;
wire [16:0] _zz_777_;
wire [31:0] _zz_778_;
wire [31:0] _zz_779_;
wire _zz_780_;
wire [19:0] _zz_781_;
wire [19:0] _zz_782_;
wire _zz_783_;
wire [0:0] _zz_784_;
wire [68:0] _zz_785_;
wire [31:0] _zz_786_;
wire [31:0] _zz_787_;
wire [31:0] _zz_788_;
wire _zz_789_;
wire [0:0] _zz_790_;
wire [1:0] _zz_791_;
wire [0:0] _zz_792_;
wire [14:0] _zz_793_;
wire [31:0] _zz_794_;
wire _zz_795_;
wire [0:0] _zz_796_;
wire [17:0] _zz_797_;
wire [3:0] _zz_798_;
wire [3:0] _zz_799_;
wire _zz_800_;
wire [0:0] _zz_801_;
wire [66:0] _zz_802_;
wire [31:0] _zz_803_;
wire [31:0] _zz_804_;
wire [31:0] _zz_805_;
wire _zz_806_;
wire _zz_807_;
wire [0:0] _zz_808_;
wire [12:0] _zz_809_;
wire [31:0] _zz_810_;
wire [31:0] _zz_811_;
wire [31:0] _zz_812_;
wire _zz_813_;
wire [0:0] _zz_814_;
wire [15:0] _zz_815_;
wire _zz_816_;
wire [0:0] _zz_817_;
wire [1:0] _zz_818_;
wire [0:0] _zz_819_;
wire [2:0] _zz_820_;
wire [3:0] _zz_821_;
wire [3:0] _zz_822_;
wire _zz_823_;
wire [0:0] _zz_824_;
wire [64:0] _zz_825_;
wire [31:0] _zz_826_;
wire [31:0] _zz_827_;
wire [0:0] _zz_828_;
wire [10:0] _zz_829_;
wire [31:0] _zz_830_;
wire [0:0] _zz_831_;
wire [13:0] _zz_832_;
wire [31:0] _zz_833_;
wire _zz_834_;
wire _zz_835_;
wire [0:0] _zz_836_;
wire [0:0] _zz_837_;
wire [0:0] _zz_838_;
wire [1:0] _zz_839_;
wire [0:0] _zz_840_;
wire [0:0] _zz_841_;
wire [8:0] _zz_842_;
wire [8:0] _zz_843_;
wire _zz_844_;
wire [0:0] _zz_845_;
wire [62:0] _zz_846_;
wire [0:0] _zz_847_;
wire [8:0] _zz_848_;
wire [0:0] _zz_849_;
wire [11:0] _zz_850_;
wire [31:0] _zz_851_;
wire [31:0] _zz_852_;
wire [31:0] _zz_853_;
wire [31:0] _zz_854_;
wire [31:0] _zz_855_;
wire [31:0] _zz_856_;
wire _zz_857_;
wire [0:0] _zz_858_;
wire [6:0] _zz_859_;
wire [0:0] _zz_860_;
wire [1:0] _zz_861_;
wire [24:0] _zz_862_;
wire [24:0] _zz_863_;
wire _zz_864_;
wire [0:0] _zz_865_;
wire [60:0] _zz_866_;
wire [0:0] _zz_867_;
wire [6:0] _zz_868_;
wire _zz_869_;
wire [0:0] _zz_870_;
wire [9:0] _zz_871_;
wire [31:0] _zz_872_;
wire [31:0] _zz_873_;
wire [31:0] _zz_874_;
wire _zz_875_;
wire [0:0] _zz_876_;
wire [4:0] _zz_877_;
wire [31:0] _zz_878_;
wire [31:0] _zz_879_;
wire _zz_880_;
wire _zz_881_;
wire _zz_882_;
wire [0:0] _zz_883_;
wire [22:0] _zz_884_;
wire [0:0] _zz_885_;
wire [0:0] _zz_886_;
wire [1:0] _zz_887_;
wire [1:0] _zz_888_;
wire _zz_889_;
wire [0:0] _zz_890_;
wire [58:0] _zz_891_;
wire [0:0] _zz_892_;
wire [5:0] _zz_893_;
wire [31:0] _zz_894_;
wire [31:0] _zz_895_;
wire _zz_896_;
wire [0:0] _zz_897_;
wire [8:0] _zz_898_;
wire [31:0] _zz_899_;
wire [31:0] _zz_900_;
wire [31:0] _zz_901_;
wire _zz_902_;
wire [0:0] _zz_903_;
wire [3:0] _zz_904_;
wire [31:0] _zz_905_;
wire [31:0] _zz_906_;
wire [31:0] _zz_907_;
wire [31:0] _zz_908_;
wire [31:0] _zz_909_;
wire [31:0] _zz_910_;
wire [31:0] _zz_911_;
wire [0:0] _zz_912_;
wire [21:0] _zz_913_;
wire _zz_914_;
wire _zz_915_;
wire [0:0] _zz_916_;
wire [0:0] _zz_917_;
wire [2:0] _zz_918_;
wire [2:0] _zz_919_;
wire _zz_920_;
wire [0:0] _zz_921_;
wire [57:0] _zz_922_;
wire [0:0] _zz_923_;
wire [4:0] _zz_924_;
wire [31:0] _zz_925_;
wire [31:0] _zz_926_;
wire [31:0] _zz_927_;
wire _zz_928_;
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