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a2p/build/openroad/litex/build/caravel_user/software/include/generated/csr.h

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//--------------------------------------------------------------------------------
// Auto-generated by Migen (9a0be7a) & LiteX (85d6cb4b) on 2021-11-25 13:53:32
//--------------------------------------------------------------------------------
#include <generated/soc.h>
#ifndef __GENERATED_CSR_H
#define __GENERATED_CSR_H
#include <stdint.h>
#include <system.h>
#ifndef CSR_ACCESSORS_DEFINED
#include <hw/common.h>
#endif /* ! CSR_ACCESSORS_DEFINED */
#ifndef CSR_BASE
#define CSR_BASE 0xfff00000L
#endif
/* i2c */
#define CSR_I2C_BASE (CSR_BASE + 0x800L)
#define CSR_I2C_W_ADDR (CSR_BASE + 0x800L)
#define CSR_I2C_W_SIZE 1
static inline uint32_t i2c_w_read(void) {
return csr_read_simple(CSR_BASE + 0x800L);
}
static inline void i2c_w_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x800L);
}
#define CSR_I2C_W_SCL_OFFSET 0
#define CSR_I2C_W_SCL_SIZE 1
static inline uint32_t i2c_w_scl_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t i2c_w_scl_read(void) {
uint32_t word = i2c_w_read();
return i2c_w_scl_extract(word);
}
static inline uint32_t i2c_w_scl_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void i2c_w_scl_write(uint32_t plain_value) {
uint32_t oldword = i2c_w_read();
uint32_t newword = i2c_w_scl_replace(oldword, plain_value);
i2c_w_write(newword);
}
#define CSR_I2C_W_OE_OFFSET 1
#define CSR_I2C_W_OE_SIZE 1
static inline uint32_t i2c_w_oe_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t i2c_w_oe_read(void) {
uint32_t word = i2c_w_read();
return i2c_w_oe_extract(word);
}
static inline uint32_t i2c_w_oe_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void i2c_w_oe_write(uint32_t plain_value) {
uint32_t oldword = i2c_w_read();
uint32_t newword = i2c_w_oe_replace(oldword, plain_value);
i2c_w_write(newword);
}
#define CSR_I2C_W_SDA_OFFSET 2
#define CSR_I2C_W_SDA_SIZE 1
static inline uint32_t i2c_w_sda_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 2) & mask );
}
static inline uint32_t i2c_w_sda_read(void) {
uint32_t word = i2c_w_read();
return i2c_w_sda_extract(word);
}
static inline uint32_t i2c_w_sda_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 2))) | (mask & plain_value)<< 2 ;
}
static inline void i2c_w_sda_write(uint32_t plain_value) {
uint32_t oldword = i2c_w_read();
uint32_t newword = i2c_w_sda_replace(oldword, plain_value);
i2c_w_write(newword);
}
#define CSR_I2C_R_ADDR (CSR_BASE + 0x804L)
#define CSR_I2C_R_SIZE 1
static inline uint32_t i2c_r_read(void) {
return csr_read_simple(CSR_BASE + 0x804L);
}
#define CSR_I2C_R_SDA_OFFSET 0
#define CSR_I2C_R_SDA_SIZE 1
static inline uint32_t i2c_r_sda_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t i2c_r_sda_read(void) {
uint32_t word = i2c_r_read();
return i2c_r_sda_extract(word);
}
/* uart_0_phy */
#define CSR_UART_0_PHY_BASE (CSR_BASE + 0x1000L)
#define CSR_UART_0_PHY_TUNING_WORD_ADDR (CSR_BASE + 0x1000L)
#define CSR_UART_0_PHY_TUNING_WORD_SIZE 1
static inline uint32_t uart_0_phy_tuning_word_read(void) {
return csr_read_simple(CSR_BASE + 0x1000L);
}
static inline void uart_0_phy_tuning_word_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x1000L);
}
/* uart_0 */
#define CSR_UART_0_BASE (CSR_BASE + 0x1800L)
#define CSR_UART_0_RXTX_ADDR (CSR_BASE + 0x1800L)
#define CSR_UART_0_RXTX_SIZE 1
static inline uint32_t uart_0_rxtx_read(void) {
return csr_read_simple(CSR_BASE + 0x1800L);
}
static inline void uart_0_rxtx_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x1800L);
}
#define CSR_UART_0_TXFULL_ADDR (CSR_BASE + 0x1804L)
#define CSR_UART_0_TXFULL_SIZE 1
static inline uint32_t uart_0_txfull_read(void) {
return csr_read_simple(CSR_BASE + 0x1804L);
}
#define CSR_UART_0_RXEMPTY_ADDR (CSR_BASE + 0x1808L)
#define CSR_UART_0_RXEMPTY_SIZE 1
static inline uint32_t uart_0_rxempty_read(void) {
return csr_read_simple(CSR_BASE + 0x1808L);
}
#define CSR_UART_0_EV_STATUS_ADDR (CSR_BASE + 0x180cL)
#define CSR_UART_0_EV_STATUS_SIZE 1
static inline uint32_t uart_0_ev_status_read(void) {
return csr_read_simple(CSR_BASE + 0x180cL);
}
#define CSR_UART_0_EV_STATUS_TX_OFFSET 0
#define CSR_UART_0_EV_STATUS_TX_SIZE 1
static inline uint32_t uart_0_ev_status_tx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t uart_0_ev_status_tx_read(void) {
uint32_t word = uart_0_ev_status_read();
return uart_0_ev_status_tx_extract(word);
}
#define CSR_UART_0_EV_STATUS_RX_OFFSET 1
#define CSR_UART_0_EV_STATUS_RX_SIZE 1
static inline uint32_t uart_0_ev_status_rx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t uart_0_ev_status_rx_read(void) {
uint32_t word = uart_0_ev_status_read();
return uart_0_ev_status_rx_extract(word);
}
#define CSR_UART_0_EV_PENDING_ADDR (CSR_BASE + 0x1810L)
#define CSR_UART_0_EV_PENDING_SIZE 1
static inline uint32_t uart_0_ev_pending_read(void) {
return csr_read_simple(CSR_BASE + 0x1810L);
}
static inline void uart_0_ev_pending_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x1810L);
}
#define CSR_UART_0_EV_PENDING_TX_OFFSET 0
#define CSR_UART_0_EV_PENDING_TX_SIZE 1
static inline uint32_t uart_0_ev_pending_tx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t uart_0_ev_pending_tx_read(void) {
uint32_t word = uart_0_ev_pending_read();
return uart_0_ev_pending_tx_extract(word);
}
static inline uint32_t uart_0_ev_pending_tx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void uart_0_ev_pending_tx_write(uint32_t plain_value) {
uint32_t oldword = uart_0_ev_pending_read();
uint32_t newword = uart_0_ev_pending_tx_replace(oldword, plain_value);
uart_0_ev_pending_write(newword);
}
#define CSR_UART_0_EV_PENDING_RX_OFFSET 1
#define CSR_UART_0_EV_PENDING_RX_SIZE 1
static inline uint32_t uart_0_ev_pending_rx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t uart_0_ev_pending_rx_read(void) {
uint32_t word = uart_0_ev_pending_read();
return uart_0_ev_pending_rx_extract(word);
}
static inline uint32_t uart_0_ev_pending_rx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void uart_0_ev_pending_rx_write(uint32_t plain_value) {
uint32_t oldword = uart_0_ev_pending_read();
uint32_t newword = uart_0_ev_pending_rx_replace(oldword, plain_value);
uart_0_ev_pending_write(newword);
}
#define CSR_UART_0_EV_ENABLE_ADDR (CSR_BASE + 0x1814L)
#define CSR_UART_0_EV_ENABLE_SIZE 1
static inline uint32_t uart_0_ev_enable_read(void) {
return csr_read_simple(CSR_BASE + 0x1814L);
}
static inline void uart_0_ev_enable_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x1814L);
}
#define CSR_UART_0_EV_ENABLE_TX_OFFSET 0
#define CSR_UART_0_EV_ENABLE_TX_SIZE 1
static inline uint32_t uart_0_ev_enable_tx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t uart_0_ev_enable_tx_read(void) {
uint32_t word = uart_0_ev_enable_read();
return uart_0_ev_enable_tx_extract(word);
}
static inline uint32_t uart_0_ev_enable_tx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void uart_0_ev_enable_tx_write(uint32_t plain_value) {
uint32_t oldword = uart_0_ev_enable_read();
uint32_t newword = uart_0_ev_enable_tx_replace(oldword, plain_value);
uart_0_ev_enable_write(newword);
}
#define CSR_UART_0_EV_ENABLE_RX_OFFSET 1
#define CSR_UART_0_EV_ENABLE_RX_SIZE 1
static inline uint32_t uart_0_ev_enable_rx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t uart_0_ev_enable_rx_read(void) {
uint32_t word = uart_0_ev_enable_read();
return uart_0_ev_enable_rx_extract(word);
}
static inline uint32_t uart_0_ev_enable_rx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void uart_0_ev_enable_rx_write(uint32_t plain_value) {
uint32_t oldword = uart_0_ev_enable_read();
uint32_t newword = uart_0_ev_enable_rx_replace(oldword, plain_value);
uart_0_ev_enable_write(newword);
}
#define CSR_UART_0_TXEMPTY_ADDR (CSR_BASE + 0x1818L)
#define CSR_UART_0_TXEMPTY_SIZE 1
static inline uint32_t uart_0_txempty_read(void) {
return csr_read_simple(CSR_BASE + 0x1818L);
}
#define CSR_UART_0_RXFULL_ADDR (CSR_BASE + 0x181cL)
#define CSR_UART_0_RXFULL_SIZE 1
static inline uint32_t uart_0_rxfull_read(void) {
return csr_read_simple(CSR_BASE + 0x181cL);
}
/* uart_1_phy */
#define CSR_UART_1_PHY_BASE (CSR_BASE + 0x2000L)
#define CSR_UART_1_PHY_TUNING_WORD_ADDR (CSR_BASE + 0x2000L)
#define CSR_UART_1_PHY_TUNING_WORD_SIZE 1
static inline uint32_t uart_1_phy_tuning_word_read(void) {
return csr_read_simple(CSR_BASE + 0x2000L);
}
static inline void uart_1_phy_tuning_word_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x2000L);
}
/* uart_1 */
#define CSR_UART_1_BASE (CSR_BASE + 0x2800L)
#define CSR_UART_1_RXTX_ADDR (CSR_BASE + 0x2800L)
#define CSR_UART_1_RXTX_SIZE 1
static inline uint32_t uart_1_rxtx_read(void) {
return csr_read_simple(CSR_BASE + 0x2800L);
}
static inline void uart_1_rxtx_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x2800L);
}
#define CSR_UART_1_TXFULL_ADDR (CSR_BASE + 0x2804L)
#define CSR_UART_1_TXFULL_SIZE 1
static inline uint32_t uart_1_txfull_read(void) {
return csr_read_simple(CSR_BASE + 0x2804L);
}
#define CSR_UART_1_RXEMPTY_ADDR (CSR_BASE + 0x2808L)
#define CSR_UART_1_RXEMPTY_SIZE 1
static inline uint32_t uart_1_rxempty_read(void) {
return csr_read_simple(CSR_BASE + 0x2808L);
}
#define CSR_UART_1_EV_STATUS_ADDR (CSR_BASE + 0x280cL)
#define CSR_UART_1_EV_STATUS_SIZE 1
static inline uint32_t uart_1_ev_status_read(void) {
return csr_read_simple(CSR_BASE + 0x280cL);
}
#define CSR_UART_1_EV_STATUS_TX_OFFSET 0
#define CSR_UART_1_EV_STATUS_TX_SIZE 1
static inline uint32_t uart_1_ev_status_tx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t uart_1_ev_status_tx_read(void) {
uint32_t word = uart_1_ev_status_read();
return uart_1_ev_status_tx_extract(word);
}
#define CSR_UART_1_EV_STATUS_RX_OFFSET 1
#define CSR_UART_1_EV_STATUS_RX_SIZE 1
static inline uint32_t uart_1_ev_status_rx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t uart_1_ev_status_rx_read(void) {
uint32_t word = uart_1_ev_status_read();
return uart_1_ev_status_rx_extract(word);
}
#define CSR_UART_1_EV_PENDING_ADDR (CSR_BASE + 0x2810L)
#define CSR_UART_1_EV_PENDING_SIZE 1
static inline uint32_t uart_1_ev_pending_read(void) {
return csr_read_simple(CSR_BASE + 0x2810L);
}
static inline void uart_1_ev_pending_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x2810L);
}
#define CSR_UART_1_EV_PENDING_TX_OFFSET 0
#define CSR_UART_1_EV_PENDING_TX_SIZE 1
static inline uint32_t uart_1_ev_pending_tx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t uart_1_ev_pending_tx_read(void) {
uint32_t word = uart_1_ev_pending_read();
return uart_1_ev_pending_tx_extract(word);
}
static inline uint32_t uart_1_ev_pending_tx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void uart_1_ev_pending_tx_write(uint32_t plain_value) {
uint32_t oldword = uart_1_ev_pending_read();
uint32_t newword = uart_1_ev_pending_tx_replace(oldword, plain_value);
uart_1_ev_pending_write(newword);
}
#define CSR_UART_1_EV_PENDING_RX_OFFSET 1
#define CSR_UART_1_EV_PENDING_RX_SIZE 1
static inline uint32_t uart_1_ev_pending_rx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t uart_1_ev_pending_rx_read(void) {
uint32_t word = uart_1_ev_pending_read();
return uart_1_ev_pending_rx_extract(word);
}
static inline uint32_t uart_1_ev_pending_rx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void uart_1_ev_pending_rx_write(uint32_t plain_value) {
uint32_t oldword = uart_1_ev_pending_read();
uint32_t newword = uart_1_ev_pending_rx_replace(oldword, plain_value);
uart_1_ev_pending_write(newword);
}
#define CSR_UART_1_EV_ENABLE_ADDR (CSR_BASE + 0x2814L)
#define CSR_UART_1_EV_ENABLE_SIZE 1
static inline uint32_t uart_1_ev_enable_read(void) {
return csr_read_simple(CSR_BASE + 0x2814L);
}
static inline void uart_1_ev_enable_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x2814L);
}
#define CSR_UART_1_EV_ENABLE_TX_OFFSET 0
#define CSR_UART_1_EV_ENABLE_TX_SIZE 1
static inline uint32_t uart_1_ev_enable_tx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t uart_1_ev_enable_tx_read(void) {
uint32_t word = uart_1_ev_enable_read();
return uart_1_ev_enable_tx_extract(word);
}
static inline uint32_t uart_1_ev_enable_tx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void uart_1_ev_enable_tx_write(uint32_t plain_value) {
uint32_t oldword = uart_1_ev_enable_read();
uint32_t newword = uart_1_ev_enable_tx_replace(oldword, plain_value);
uart_1_ev_enable_write(newword);
}
#define CSR_UART_1_EV_ENABLE_RX_OFFSET 1
#define CSR_UART_1_EV_ENABLE_RX_SIZE 1
static inline uint32_t uart_1_ev_enable_rx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t uart_1_ev_enable_rx_read(void) {
uint32_t word = uart_1_ev_enable_read();
return uart_1_ev_enable_rx_extract(word);
}
static inline uint32_t uart_1_ev_enable_rx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void uart_1_ev_enable_rx_write(uint32_t plain_value) {
uint32_t oldword = uart_1_ev_enable_read();
uint32_t newword = uart_1_ev_enable_rx_replace(oldword, plain_value);
uart_1_ev_enable_write(newword);
}
#define CSR_UART_1_TXEMPTY_ADDR (CSR_BASE + 0x2818L)
#define CSR_UART_1_TXEMPTY_SIZE 1
static inline uint32_t uart_1_txempty_read(void) {
return csr_read_simple(CSR_BASE + 0x2818L);
}
#define CSR_UART_1_RXFULL_ADDR (CSR_BASE + 0x281cL)
#define CSR_UART_1_RXFULL_SIZE 1
static inline uint32_t uart_1_rxfull_read(void) {
return csr_read_simple(CSR_BASE + 0x281cL);
}
/* ctrl */
#define CSR_CTRL_BASE (CSR_BASE + 0x3000L)
#define CSR_CTRL_RESET_ADDR (CSR_BASE + 0x3000L)
#define CSR_CTRL_RESET_SIZE 1
static inline uint32_t ctrl_reset_read(void) {
return csr_read_simple(CSR_BASE + 0x3000L);
}
static inline void ctrl_reset_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x3000L);
}
#define CSR_CTRL_RESET_SOC_RST_OFFSET 0
#define CSR_CTRL_RESET_SOC_RST_SIZE 1
static inline uint32_t ctrl_reset_soc_rst_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t ctrl_reset_soc_rst_read(void) {
uint32_t word = ctrl_reset_read();
return ctrl_reset_soc_rst_extract(word);
}
static inline uint32_t ctrl_reset_soc_rst_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void ctrl_reset_soc_rst_write(uint32_t plain_value) {
uint32_t oldword = ctrl_reset_read();
uint32_t newword = ctrl_reset_soc_rst_replace(oldword, plain_value);
ctrl_reset_write(newword);
}
#define CSR_CTRL_RESET_CPU_RST_OFFSET 1
#define CSR_CTRL_RESET_CPU_RST_SIZE 1
static inline uint32_t ctrl_reset_cpu_rst_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t ctrl_reset_cpu_rst_read(void) {
uint32_t word = ctrl_reset_read();
return ctrl_reset_cpu_rst_extract(word);
}
static inline uint32_t ctrl_reset_cpu_rst_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void ctrl_reset_cpu_rst_write(uint32_t plain_value) {
uint32_t oldword = ctrl_reset_read();
uint32_t newword = ctrl_reset_cpu_rst_replace(oldword, plain_value);
ctrl_reset_write(newword);
}
#define CSR_CTRL_SCRATCH_ADDR (CSR_BASE + 0x3004L)
#define CSR_CTRL_SCRATCH_SIZE 1
static inline uint32_t ctrl_scratch_read(void) {
return csr_read_simple(CSR_BASE + 0x3004L);
}
static inline void ctrl_scratch_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x3004L);
}
#define CSR_CTRL_BUS_ERRORS_ADDR (CSR_BASE + 0x3008L)
#define CSR_CTRL_BUS_ERRORS_SIZE 1
static inline uint32_t ctrl_bus_errors_read(void) {
return csr_read_simple(CSR_BASE + 0x3008L);
}
/* identifier_mem */
#define CSR_IDENTIFIER_MEM_BASE (CSR_BASE + 0x3800L)
/* timer0 */
#define CSR_TIMER0_BASE (CSR_BASE + 0x4000L)
#define CSR_TIMER0_LOAD_ADDR (CSR_BASE + 0x4000L)
#define CSR_TIMER0_LOAD_SIZE 1
static inline uint32_t timer0_load_read(void) {
return csr_read_simple(CSR_BASE + 0x4000L);
}
static inline void timer0_load_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x4000L);
}
#define CSR_TIMER0_RELOAD_ADDR (CSR_BASE + 0x4004L)
#define CSR_TIMER0_RELOAD_SIZE 1
static inline uint32_t timer0_reload_read(void) {
return csr_read_simple(CSR_BASE + 0x4004L);
}
static inline void timer0_reload_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x4004L);
}
#define CSR_TIMER0_EN_ADDR (CSR_BASE + 0x4008L)
#define CSR_TIMER0_EN_SIZE 1
static inline uint32_t timer0_en_read(void) {
return csr_read_simple(CSR_BASE + 0x4008L);
}
static inline void timer0_en_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x4008L);
}
#define CSR_TIMER0_UPDATE_VALUE_ADDR (CSR_BASE + 0x400cL)
#define CSR_TIMER0_UPDATE_VALUE_SIZE 1
static inline uint32_t timer0_update_value_read(void) {
return csr_read_simple(CSR_BASE + 0x400cL);
}
static inline void timer0_update_value_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x400cL);
}
#define CSR_TIMER0_VALUE_ADDR (CSR_BASE + 0x4010L)
#define CSR_TIMER0_VALUE_SIZE 1
static inline uint32_t timer0_value_read(void) {
return csr_read_simple(CSR_BASE + 0x4010L);
}
#define CSR_TIMER0_EV_STATUS_ADDR (CSR_BASE + 0x4014L)
#define CSR_TIMER0_EV_STATUS_SIZE 1
static inline uint32_t timer0_ev_status_read(void) {
return csr_read_simple(CSR_BASE + 0x4014L);
}
#define CSR_TIMER0_EV_STATUS_ZERO_OFFSET 0
#define CSR_TIMER0_EV_STATUS_ZERO_SIZE 1
static inline uint32_t timer0_ev_status_zero_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t timer0_ev_status_zero_read(void) {
uint32_t word = timer0_ev_status_read();
return timer0_ev_status_zero_extract(word);
}
#define CSR_TIMER0_EV_PENDING_ADDR (CSR_BASE + 0x4018L)
#define CSR_TIMER0_EV_PENDING_SIZE 1
static inline uint32_t timer0_ev_pending_read(void) {
return csr_read_simple(CSR_BASE + 0x4018L);
}
static inline void timer0_ev_pending_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x4018L);
}
#define CSR_TIMER0_EV_PENDING_ZERO_OFFSET 0
#define CSR_TIMER0_EV_PENDING_ZERO_SIZE 1
static inline uint32_t timer0_ev_pending_zero_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t timer0_ev_pending_zero_read(void) {
uint32_t word = timer0_ev_pending_read();
return timer0_ev_pending_zero_extract(word);
}
static inline uint32_t timer0_ev_pending_zero_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void timer0_ev_pending_zero_write(uint32_t plain_value) {
uint32_t oldword = timer0_ev_pending_read();
uint32_t newword = timer0_ev_pending_zero_replace(oldword, plain_value);
timer0_ev_pending_write(newword);
}
#define CSR_TIMER0_EV_ENABLE_ADDR (CSR_BASE + 0x401cL)
#define CSR_TIMER0_EV_ENABLE_SIZE 1
static inline uint32_t timer0_ev_enable_read(void) {
return csr_read_simple(CSR_BASE + 0x401cL);
}
static inline void timer0_ev_enable_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x401cL);
}
#define CSR_TIMER0_EV_ENABLE_ZERO_OFFSET 0
#define CSR_TIMER0_EV_ENABLE_ZERO_SIZE 1
static inline uint32_t timer0_ev_enable_zero_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t timer0_ev_enable_zero_read(void) {
uint32_t word = timer0_ev_enable_read();
return timer0_ev_enable_zero_extract(word);
}
static inline uint32_t timer0_ev_enable_zero_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void timer0_ev_enable_zero_write(uint32_t plain_value) {
uint32_t oldword = timer0_ev_enable_read();
uint32_t newword = timer0_ev_enable_zero_replace(oldword, plain_value);
timer0_ev_enable_write(newword);
}
#endif
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