// -----------------------------------------------------------------------------
// Auto-Generated by:        __   _ __      _  __
//                          / /  (_) /____ | |/_/
//                         / /__/ / __/ -_)>  <
//                        /____/_/\__/\__/_/|_|
//                     Build your hardware, easily!
//                   https://github.com/enjoy-digital/litex
//
// Filename   : litedram_core.v
// Device     : 
// LiteX sha1 : bc1f1f52b
// Date       : 2025-02-15 19:54:53
//------------------------------------------------------------------------------

`timescale 1ns / 1ps

//------------------------------------------------------------------------------
// Module
//------------------------------------------------------------------------------

module litedram_core (
    input  wire          clk,
    output wire          init_done,
    output wire          init_error,
    input  wire          sim_trace,
    output wire          user_clk,
    input  wire   [23:0] user_port_native_0_cmd_addr,
    output wire          user_port_native_0_cmd_ready,
    input  wire          user_port_native_0_cmd_valid,
    input  wire          user_port_native_0_cmd_we,
    output wire  [127:0] user_port_native_0_rdata_data,
    input  wire          user_port_native_0_rdata_ready,
    output wire          user_port_native_0_rdata_valid,
    input  wire  [127:0] user_port_native_0_wdata_data,
    output wire          user_port_native_0_wdata_ready,
    input  wire          user_port_native_0_wdata_valid,
    input  wire   [15:0] user_port_native_0_wdata_we,
    output wire          user_rst,
    output wire          wb_ctrl_ack,
    input  wire   [29:0] wb_ctrl_adr,
    input  wire    [1:0] wb_ctrl_bte,
    input  wire    [2:0] wb_ctrl_cti,
    input  wire          wb_ctrl_cyc,
    output wire   [31:0] wb_ctrl_dat_r,
    input  wire   [31:0] wb_ctrl_dat_w,
    output wire          wb_ctrl_err,
    input  wire    [3:0] wb_ctrl_sel,
    input  wire          wb_ctrl_stb,
    input  wire          wb_ctrl_we
);


//------------------------------------------------------------------------------
// Hierarchy
//------------------------------------------------------------------------------

/*
LiteDRAMCore
└─── bus (SoCBusHandler)
│    └─── _interconnect (InterconnectPointToPoint)
└─── csr (SoCCSRHandler)
└─── irq (SoCIRQHandler)
└─── cpu (CPUNone)
└─── crg (CRG)
└─── ddrphy (SDRAMPHYModel)
│    └─── dfiphasemodel_0* (DFIPhaseModel)
│    └─── dfiphasemodel_1* (DFIPhaseModel)
│    └─── dfiphasemodel_2* (DFIPhaseModel)
│    └─── dfiphasemodel_3* (DFIPhaseModel)
│    └─── bankmodel_0* (BankModel)
│    └─── bankmodel_1* (BankModel)
│    └─── bankmodel_2* (BankModel)
│    └─── bankmodel_3* (BankModel)
│    └─── bankmodel_4* (BankModel)
│    └─── bankmodel_5* (BankModel)
│    └─── bankmodel_6* (BankModel)
│    └─── bankmodel_7* (BankModel)
└─── sdram (LiteDRAMCore)
│    └─── dfii (DFIInjector)
│    │    └─── pi0 (PhaseInjector)
│    │    └─── pi1 (PhaseInjector)
│    │    └─── pi2 (PhaseInjector)
│    │    └─── pi3 (PhaseInjector)
│    └─── controller (LiteDRAMController)
│    │    └─── refresher (Refresher)
│    │    │    └─── timer (RefreshTimer)
│    │    │    └─── postponer (RefreshPostponer)
│    │    │    └─── sequencer (RefreshSequencer)
│    │    │    │    └─── refreshexecuter_0* (RefreshExecuter)
│    │    │    └─── zqcs_timer (RefreshTimer)
│    │    │    └─── zqs_executer (ZQCSExecuter)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_0* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_1* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_2* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_3* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_4* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_5* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_6* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_7* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── multiplexer (Multiplexer)
│    │    │    └─── choose_cmd (_CommandChooser)
│    │    │    │    └─── roundrobin_0* (RoundRobin)
│    │    │    └─── choose_req (_CommandChooser)
│    │    │    │    └─── roundrobin_0* (RoundRobin)
│    │    │    └─── _steerer_0* (_Steerer)
│    │    │    └─── trrdcon (tXXDController)
│    │    │    └─── tfawcon (tFAWController)
│    │    │    └─── tccdcon (tXXDController)
│    │    │    └─── twtrcon (tXXDController)
│    │    │    └─── fsm (FSM)
│    └─── crossbar (LiteDRAMCrossbar)
│    │    └─── roundrobin_0* (RoundRobin)
│    │    └─── roundrobin_1* (RoundRobin)
│    │    └─── roundrobin_2* (RoundRobin)
│    │    └─── roundrobin_3* (RoundRobin)
│    │    └─── roundrobin_4* (RoundRobin)
│    │    └─── roundrobin_5* (RoundRobin)
│    │    └─── roundrobin_6* (RoundRobin)
│    │    └─── roundrobin_7* (RoundRobin)
└─── ddrctrl (LiteDRAMCoreControl)
└─── csr_bridge (Wishbone2CSR)
│    └─── fsm (FSM)
└─── csr_bankarray (CSRBankArray)
│    └─── csrbank_0* (CSRBank)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstorage_1* (CSRStorage)
│    └─── csrbank_1* (CSRBank)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstorage_1* (CSRStorage)
│    │    └─── csrstorage_2* (CSRStorage)
│    │    └─── csrstorage_3* (CSRStorage)
│    │    └─── csrstorage_4* (CSRStorage)
│    │    └─── csrstatus_0* (CSRStatus)
│    │    └─── csrstorage_5* (CSRStorage)
│    │    └─── csrstorage_6* (CSRStorage)
│    │    └─── csrstorage_7* (CSRStorage)
│    │    └─── csrstorage_8* (CSRStorage)
│    │    └─── csrstatus_1* (CSRStatus)
│    │    └─── csrstorage_9* (CSRStorage)
│    │    └─── csrstorage_10* (CSRStorage)
│    │    └─── csrstorage_11* (CSRStorage)
│    │    └─── csrstorage_12* (CSRStorage)
│    │    └─── csrstatus_2* (CSRStatus)
│    │    └─── csrstorage_13* (CSRStorage)
│    │    └─── csrstorage_14* (CSRStorage)
│    │    └─── csrstorage_15* (CSRStorage)
│    │    └─── csrstorage_16* (CSRStorage)
│    │    └─── csrstatus_3* (CSRStatus)
└─── csr_interconnect (InterconnectShared)
* : Generated name.
[]: BlackBox.
*/

//------------------------------------------------------------------------------
// Signals
//------------------------------------------------------------------------------

wire   [13:0] adr;
reg     [3:0] bankmachine0_next_state = 4'd0;
reg     [3:0] bankmachine0_state = 4'd0;
reg     [3:0] bankmachine1_next_state = 4'd0;
reg     [3:0] bankmachine1_state = 4'd0;
reg     [3:0] bankmachine2_next_state = 4'd0;
reg     [3:0] bankmachine2_state = 4'd0;
reg     [3:0] bankmachine3_next_state = 4'd0;
reg     [3:0] bankmachine3_state = 4'd0;
reg     [3:0] bankmachine4_next_state = 4'd0;
reg     [3:0] bankmachine4_state = 4'd0;
reg     [3:0] bankmachine5_next_state = 4'd0;
reg     [3:0] bankmachine5_state = 4'd0;
reg     [3:0] bankmachine6_next_state = 4'd0;
reg     [3:0] bankmachine6_state = 4'd0;
reg     [3:0] bankmachine7_next_state = 4'd0;
reg     [3:0] bankmachine7_state = 4'd0;
wire          csrbank0_init_done0_r;
reg           csrbank0_init_done0_re = 1'd0;
wire          csrbank0_init_done0_w;
reg           csrbank0_init_done0_we = 1'd0;
wire          csrbank0_init_error0_r;
reg           csrbank0_init_error0_re = 1'd0;
wire          csrbank0_init_error0_w;
reg           csrbank0_init_error0_we = 1'd0;
wire          csrbank0_sel;
wire    [3:0] csrbank1_dfii_control0_r;
reg           csrbank1_dfii_control0_re = 1'd0;
wire    [3:0] csrbank1_dfii_control0_w;
reg           csrbank1_dfii_control0_we = 1'd0;
wire   [13:0] csrbank1_dfii_pi0_address0_r;
reg           csrbank1_dfii_pi0_address0_re = 1'd0;
wire   [13:0] csrbank1_dfii_pi0_address0_w;
reg           csrbank1_dfii_pi0_address0_we = 1'd0;
wire    [2:0] csrbank1_dfii_pi0_baddress0_r;
reg           csrbank1_dfii_pi0_baddress0_re = 1'd0;
wire    [2:0] csrbank1_dfii_pi0_baddress0_w;
reg           csrbank1_dfii_pi0_baddress0_we = 1'd0;
wire    [7:0] csrbank1_dfii_pi0_command0_r;
reg           csrbank1_dfii_pi0_command0_re = 1'd0;
wire    [7:0] csrbank1_dfii_pi0_command0_w;
reg           csrbank1_dfii_pi0_command0_we = 1'd0;
wire   [31:0] csrbank1_dfii_pi0_rddata_r;
reg           csrbank1_dfii_pi0_rddata_re = 1'd0;
wire   [31:0] csrbank1_dfii_pi0_rddata_w;
reg           csrbank1_dfii_pi0_rddata_we = 1'd0;
wire   [31:0] csrbank1_dfii_pi0_wrdata0_r;
reg           csrbank1_dfii_pi0_wrdata0_re = 1'd0;
wire   [31:0] csrbank1_dfii_pi0_wrdata0_w;
reg           csrbank1_dfii_pi0_wrdata0_we = 1'd0;
wire   [13:0] csrbank1_dfii_pi1_address0_r;
reg           csrbank1_dfii_pi1_address0_re = 1'd0;
wire   [13:0] csrbank1_dfii_pi1_address0_w;
reg           csrbank1_dfii_pi1_address0_we = 1'd0;
wire    [2:0] csrbank1_dfii_pi1_baddress0_r;
reg           csrbank1_dfii_pi1_baddress0_re = 1'd0;
wire    [2:0] csrbank1_dfii_pi1_baddress0_w;
reg           csrbank1_dfii_pi1_baddress0_we = 1'd0;
wire    [7:0] csrbank1_dfii_pi1_command0_r;
reg           csrbank1_dfii_pi1_command0_re = 1'd0;
wire    [7:0] csrbank1_dfii_pi1_command0_w;
reg           csrbank1_dfii_pi1_command0_we = 1'd0;
wire   [31:0] csrbank1_dfii_pi1_rddata_r;
reg           csrbank1_dfii_pi1_rddata_re = 1'd0;
wire   [31:0] csrbank1_dfii_pi1_rddata_w;
reg           csrbank1_dfii_pi1_rddata_we = 1'd0;
wire   [31:0] csrbank1_dfii_pi1_wrdata0_r;
reg           csrbank1_dfii_pi1_wrdata0_re = 1'd0;
wire   [31:0] csrbank1_dfii_pi1_wrdata0_w;
reg           csrbank1_dfii_pi1_wrdata0_we = 1'd0;
wire   [13:0] csrbank1_dfii_pi2_address0_r;
reg           csrbank1_dfii_pi2_address0_re = 1'd0;
wire   [13:0] csrbank1_dfii_pi2_address0_w;
reg           csrbank1_dfii_pi2_address0_we = 1'd0;
wire    [2:0] csrbank1_dfii_pi2_baddress0_r;
reg           csrbank1_dfii_pi2_baddress0_re = 1'd0;
wire    [2:0] csrbank1_dfii_pi2_baddress0_w;
reg           csrbank1_dfii_pi2_baddress0_we = 1'd0;
wire    [7:0] csrbank1_dfii_pi2_command0_r;
reg           csrbank1_dfii_pi2_command0_re = 1'd0;
wire    [7:0] csrbank1_dfii_pi2_command0_w;
reg           csrbank1_dfii_pi2_command0_we = 1'd0;
wire   [31:0] csrbank1_dfii_pi2_rddata_r;
reg           csrbank1_dfii_pi2_rddata_re = 1'd0;
wire   [31:0] csrbank1_dfii_pi2_rddata_w;
reg           csrbank1_dfii_pi2_rddata_we = 1'd0;
wire   [31:0] csrbank1_dfii_pi2_wrdata0_r;
reg           csrbank1_dfii_pi2_wrdata0_re = 1'd0;
wire   [31:0] csrbank1_dfii_pi2_wrdata0_w;
reg           csrbank1_dfii_pi2_wrdata0_we = 1'd0;
wire   [13:0] csrbank1_dfii_pi3_address0_r;
reg           csrbank1_dfii_pi3_address0_re = 1'd0;
wire   [13:0] csrbank1_dfii_pi3_address0_w;
reg           csrbank1_dfii_pi3_address0_we = 1'd0;
wire    [2:0] csrbank1_dfii_pi3_baddress0_r;
reg           csrbank1_dfii_pi3_baddress0_re = 1'd0;
wire    [2:0] csrbank1_dfii_pi3_baddress0_w;
reg           csrbank1_dfii_pi3_baddress0_we = 1'd0;
wire    [7:0] csrbank1_dfii_pi3_command0_r;
reg           csrbank1_dfii_pi3_command0_re = 1'd0;
wire    [7:0] csrbank1_dfii_pi3_command0_w;
reg           csrbank1_dfii_pi3_command0_we = 1'd0;
wire   [31:0] csrbank1_dfii_pi3_rddata_r;
reg           csrbank1_dfii_pi3_rddata_re = 1'd0;
wire   [31:0] csrbank1_dfii_pi3_rddata_w;
reg           csrbank1_dfii_pi3_rddata_we = 1'd0;
wire   [31:0] csrbank1_dfii_pi3_wrdata0_r;
reg           csrbank1_dfii_pi3_wrdata0_re = 1'd0;
wire   [31:0] csrbank1_dfii_pi3_wrdata0_w;
reg           csrbank1_dfii_pi3_wrdata0_we = 1'd0;
wire          csrbank1_sel;
wire   [31:0] dat_r;
wire   [31:0] dat_w;
reg           interface0_ack = 1'd0;
wire   [29:0] interface0_adr;
wire   [13:0] interface0_bank_bus_adr;
reg    [31:0] interface0_bank_bus_dat_r = 32'd0;
wire   [31:0] interface0_bank_bus_dat_w;
wire          interface0_bank_bus_re;
wire          interface0_bank_bus_we;
wire    [1:0] interface0_bte;
wire    [2:0] interface0_cti;
wire          interface0_cyc;
reg    [31:0] interface0_dat_r = 32'd0;
wire   [31:0] interface0_dat_w;
reg           interface0_err = 1'd0;
wire    [3:0] interface0_sel;
wire          interface0_stb;
wire          interface0_we;
reg    [13:0] interface1_adr = 14'd0;
reg    [13:0] interface1_adr_next_value1 = 14'd0;
reg           interface1_adr_next_value_ce1 = 1'd0;
wire   [13:0] interface1_bank_bus_adr;
reg    [31:0] interface1_bank_bus_dat_r = 32'd0;
wire   [31:0] interface1_bank_bus_dat_w;
wire          interface1_bank_bus_re;
wire          interface1_bank_bus_we;
wire   [31:0] interface1_dat_r;
reg    [31:0] interface1_dat_w = 32'd0;
reg    [31:0] interface1_dat_w_next_value0 = 32'd0;
reg           interface1_dat_w_next_value_ce0 = 1'd0;
reg           interface1_re = 1'd0;
reg           interface1_re_next_value2 = 1'd0;
reg           interface1_re_next_value_ce2 = 1'd0;
reg           interface1_we = 1'd0;
reg           interface1_we_next_value3 = 1'd0;
reg           interface1_we_next_value_ce3 = 1'd0;
reg           locked0 = 1'd0;
reg           locked1 = 1'd0;
reg           locked2 = 1'd0;
reg           locked3 = 1'd0;
reg           locked4 = 1'd0;
reg           locked5 = 1'd0;
reg           locked6 = 1'd0;
reg           locked7 = 1'd0;
reg     [3:0] multiplexer_next_state = 4'd0;
reg     [3:0] multiplexer_state = 4'd0;
reg           new_master_rdata_valid0 = 1'd0;
reg           new_master_rdata_valid1 = 1'd0;
reg           new_master_rdata_valid2 = 1'd0;
reg           new_master_rdata_valid3 = 1'd0;
reg           new_master_rdata_valid4 = 1'd0;
reg           new_master_rdata_valid5 = 1'd0;
reg           new_master_rdata_valid6 = 1'd0;
reg           new_master_rdata_valid7 = 1'd0;
reg           new_master_rdata_valid8 = 1'd0;
reg           new_master_wdata_ready0 = 1'd0;
reg           new_master_wdata_ready1 = 1'd0;
reg     [1:0] next_state = 2'd0;
wire          por_clk;
wire          re;
reg     [1:0] refresher_next_state = 2'd0;
reg     [1:0] refresher_state = 2'd0;
reg           rhs_self0 = 1'd0;
reg    [13:0] rhs_self1 = 14'd0;
reg           rhs_self10 = 1'd0;
reg           rhs_self11 = 1'd0;
reg    [20:0] rhs_self12 = 21'd0;
reg           rhs_self13 = 1'd0;
reg           rhs_self14 = 1'd0;
reg    [20:0] rhs_self15 = 21'd0;
reg           rhs_self16 = 1'd0;
reg           rhs_self17 = 1'd0;
reg    [20:0] rhs_self18 = 21'd0;
reg           rhs_self19 = 1'd0;
reg     [2:0] rhs_self2 = 3'd0;
reg           rhs_self20 = 1'd0;
reg    [20:0] rhs_self21 = 21'd0;
reg           rhs_self22 = 1'd0;
reg           rhs_self23 = 1'd0;
reg    [20:0] rhs_self24 = 21'd0;
reg           rhs_self25 = 1'd0;
reg           rhs_self26 = 1'd0;
reg    [20:0] rhs_self27 = 21'd0;
reg           rhs_self28 = 1'd0;
reg           rhs_self29 = 1'd0;
reg           rhs_self3 = 1'd0;
reg    [20:0] rhs_self30 = 21'd0;
reg           rhs_self31 = 1'd0;
reg           rhs_self32 = 1'd0;
reg    [20:0] rhs_self33 = 21'd0;
reg           rhs_self34 = 1'd0;
reg           rhs_self35 = 1'd0;
reg           rhs_self4 = 1'd0;
reg           rhs_self5 = 1'd0;
reg           rhs_self6 = 1'd0;
reg    [13:0] rhs_self7 = 14'd0;
reg     [2:0] rhs_self8 = 3'd0;
reg           rhs_self9 = 1'd0;
wire          roundrobin0_ce;
wire          roundrobin0_grant;
wire          roundrobin0_request;
wire          roundrobin1_ce;
wire          roundrobin1_grant;
wire          roundrobin1_request;
wire          roundrobin2_ce;
wire          roundrobin2_grant;
wire          roundrobin2_request;
wire          roundrobin3_ce;
wire          roundrobin3_grant;
wire          roundrobin3_request;
wire          roundrobin4_ce;
wire          roundrobin4_grant;
wire          roundrobin4_request;
wire          roundrobin5_ce;
wire          roundrobin5_grant;
wire          roundrobin5_request;
wire          roundrobin6_ce;
wire          roundrobin6_grant;
wire          roundrobin6_request;
wire          roundrobin7_ce;
wire          roundrobin7_grant;
wire          roundrobin7_request;
reg     [2:0] self0 = 3'd0;
reg    [13:0] self1 = 14'd0;
reg           self10 = 1'd0;
reg           self11 = 1'd0;
reg           self12 = 1'd0;
reg           self13 = 1'd0;
reg     [2:0] self14 = 3'd0;
reg    [13:0] self15 = 14'd0;
reg           self16 = 1'd0;
reg           self17 = 1'd0;
reg           self18 = 1'd0;
reg           self19 = 1'd0;
reg           self2 = 1'd0;
reg           self20 = 1'd0;
reg     [2:0] self21 = 3'd0;
reg    [13:0] self22 = 14'd0;
reg           self23 = 1'd0;
reg           self24 = 1'd0;
reg           self25 = 1'd0;
reg           self26 = 1'd0;
reg           self27 = 1'd0;
reg           self3 = 1'd0;
reg           self4 = 1'd0;
reg           self5 = 1'd0;
reg           self6 = 1'd0;
reg     [2:0] self7 = 3'd0;
reg    [13:0] self8 = 14'd0;
reg           self9 = 1'd0;
wire   [24:0] slice_proxy0;
wire   [24:0] slice_proxy1;
wire   [24:0] slice_proxy10;
wire   [24:0] slice_proxy11;
wire   [24:0] slice_proxy12;
wire   [24:0] slice_proxy13;
wire   [24:0] slice_proxy14;
wire   [24:0] slice_proxy15;
wire   [24:0] slice_proxy2;
wire   [24:0] slice_proxy3;
wire   [24:0] slice_proxy4;
wire   [24:0] slice_proxy5;
wire   [24:0] slice_proxy6;
wire   [24:0] slice_proxy7;
wire   [24:0] slice_proxy8;
wire   [24:0] slice_proxy9;
reg     [3:0] soc_ddrphy_activates0 = 4'd0;
reg     [3:0] soc_ddrphy_activates1 = 4'd0;
reg     [3:0] soc_ddrphy_activates2 = 4'd0;
reg     [3:0] soc_ddrphy_activates3 = 4'd0;
reg     [3:0] soc_ddrphy_activates4 = 4'd0;
reg     [3:0] soc_ddrphy_activates5 = 4'd0;
reg     [3:0] soc_ddrphy_activates6 = 4'd0;
reg     [3:0] soc_ddrphy_activates7 = 4'd0;
reg           soc_ddrphy_bank_write0 = 1'd0;
reg           soc_ddrphy_bank_write1 = 1'd0;
reg           soc_ddrphy_bank_write2 = 1'd0;
reg           soc_ddrphy_bank_write3 = 1'd0;
reg           soc_ddrphy_bank_write4 = 1'd0;
reg           soc_ddrphy_bank_write5 = 1'd0;
reg           soc_ddrphy_bank_write6 = 1'd0;
reg           soc_ddrphy_bank_write7 = 1'd0;
reg     [9:0] soc_ddrphy_bank_write_col0 = 10'd0;
reg     [9:0] soc_ddrphy_bank_write_col1 = 10'd0;
reg     [9:0] soc_ddrphy_bank_write_col2 = 10'd0;
reg     [9:0] soc_ddrphy_bank_write_col3 = 10'd0;
reg     [9:0] soc_ddrphy_bank_write_col4 = 10'd0;
reg     [9:0] soc_ddrphy_bank_write_col5 = 10'd0;
reg     [9:0] soc_ddrphy_bank_write_col6 = 10'd0;
reg     [9:0] soc_ddrphy_bank_write_col7 = 10'd0;
reg           soc_ddrphy_bankmodel0_activate = 1'd0;
reg    [13:0] soc_ddrphy_bankmodel0_activate_row = 14'd0;
reg           soc_ddrphy_bankmodel0_active = 1'd0;
reg           soc_ddrphy_bankmodel0_precharge = 1'd0;
wire   [20:0] soc_ddrphy_bankmodel0_rdaddr;
reg           soc_ddrphy_bankmodel0_read = 1'd0;
reg     [9:0] soc_ddrphy_bankmodel0_read_col = 10'd0;
reg   [127:0] soc_ddrphy_bankmodel0_read_data = 128'd0;
reg    [20:0] soc_ddrphy_bankmodel0_read_port_adr = 21'd0;
wire  [127:0] soc_ddrphy_bankmodel0_read_port_dat_r;
reg    [13:0] soc_ddrphy_bankmodel0_row = 14'd0;
wire   [20:0] soc_ddrphy_bankmodel0_wraddr;
wire          soc_ddrphy_bankmodel0_write;
wire    [9:0] soc_ddrphy_bankmodel0_write_col;
wire  [127:0] soc_ddrphy_bankmodel0_write_data;
wire   [15:0] soc_ddrphy_bankmodel0_write_mask;
reg    [20:0] soc_ddrphy_bankmodel0_write_port_adr = 21'd0;
wire  [127:0] soc_ddrphy_bankmodel0_write_port_dat_r;
reg   [127:0] soc_ddrphy_bankmodel0_write_port_dat_w = 128'd0;
reg    [15:0] soc_ddrphy_bankmodel0_write_port_we = 16'd0;
reg           soc_ddrphy_bankmodel1_activate = 1'd0;
reg    [13:0] soc_ddrphy_bankmodel1_activate_row = 14'd0;
reg           soc_ddrphy_bankmodel1_active = 1'd0;
reg           soc_ddrphy_bankmodel1_precharge = 1'd0;
wire   [20:0] soc_ddrphy_bankmodel1_rdaddr;
reg           soc_ddrphy_bankmodel1_read = 1'd0;
reg     [9:0] soc_ddrphy_bankmodel1_read_col = 10'd0;
reg   [127:0] soc_ddrphy_bankmodel1_read_data = 128'd0;
reg    [20:0] soc_ddrphy_bankmodel1_read_port_adr = 21'd0;
wire  [127:0] soc_ddrphy_bankmodel1_read_port_dat_r;
reg    [13:0] soc_ddrphy_bankmodel1_row = 14'd0;
wire   [20:0] soc_ddrphy_bankmodel1_wraddr;
wire          soc_ddrphy_bankmodel1_write;
wire    [9:0] soc_ddrphy_bankmodel1_write_col;
wire  [127:0] soc_ddrphy_bankmodel1_write_data;
wire   [15:0] soc_ddrphy_bankmodel1_write_mask;
reg    [20:0] soc_ddrphy_bankmodel1_write_port_adr = 21'd0;
wire  [127:0] soc_ddrphy_bankmodel1_write_port_dat_r;
reg   [127:0] soc_ddrphy_bankmodel1_write_port_dat_w = 128'd0;
reg    [15:0] soc_ddrphy_bankmodel1_write_port_we = 16'd0;
reg           soc_ddrphy_bankmodel2_activate = 1'd0;
reg    [13:0] soc_ddrphy_bankmodel2_activate_row = 14'd0;
reg           soc_ddrphy_bankmodel2_active = 1'd0;
reg           soc_ddrphy_bankmodel2_precharge = 1'd0;
wire   [20:0] soc_ddrphy_bankmodel2_rdaddr;
reg           soc_ddrphy_bankmodel2_read = 1'd0;
reg     [9:0] soc_ddrphy_bankmodel2_read_col = 10'd0;
reg   [127:0] soc_ddrphy_bankmodel2_read_data = 128'd0;
reg    [20:0] soc_ddrphy_bankmodel2_read_port_adr = 21'd0;
wire  [127:0] soc_ddrphy_bankmodel2_read_port_dat_r;
reg    [13:0] soc_ddrphy_bankmodel2_row = 14'd0;
wire   [20:0] soc_ddrphy_bankmodel2_wraddr;
wire          soc_ddrphy_bankmodel2_write;
wire    [9:0] soc_ddrphy_bankmodel2_write_col;
wire  [127:0] soc_ddrphy_bankmodel2_write_data;
wire   [15:0] soc_ddrphy_bankmodel2_write_mask;
reg    [20:0] soc_ddrphy_bankmodel2_write_port_adr = 21'd0;
wire  [127:0] soc_ddrphy_bankmodel2_write_port_dat_r;
reg   [127:0] soc_ddrphy_bankmodel2_write_port_dat_w = 128'd0;
reg    [15:0] soc_ddrphy_bankmodel2_write_port_we = 16'd0;
reg           soc_ddrphy_bankmodel3_activate = 1'd0;
reg    [13:0] soc_ddrphy_bankmodel3_activate_row = 14'd0;
reg           soc_ddrphy_bankmodel3_active = 1'd0;
reg           soc_ddrphy_bankmodel3_precharge = 1'd0;
wire   [20:0] soc_ddrphy_bankmodel3_rdaddr;
reg           soc_ddrphy_bankmodel3_read = 1'd0;
reg     [9:0] soc_ddrphy_bankmodel3_read_col = 10'd0;
reg   [127:0] soc_ddrphy_bankmodel3_read_data = 128'd0;
reg    [20:0] soc_ddrphy_bankmodel3_read_port_adr = 21'd0;
wire  [127:0] soc_ddrphy_bankmodel3_read_port_dat_r;
reg    [13:0] soc_ddrphy_bankmodel3_row = 14'd0;
wire   [20:0] soc_ddrphy_bankmodel3_wraddr;
wire          soc_ddrphy_bankmodel3_write;
wire    [9:0] soc_ddrphy_bankmodel3_write_col;
wire  [127:0] soc_ddrphy_bankmodel3_write_data;
wire   [15:0] soc_ddrphy_bankmodel3_write_mask;
reg    [20:0] soc_ddrphy_bankmodel3_write_port_adr = 21'd0;
wire  [127:0] soc_ddrphy_bankmodel3_write_port_dat_r;
reg   [127:0] soc_ddrphy_bankmodel3_write_port_dat_w = 128'd0;
reg    [15:0] soc_ddrphy_bankmodel3_write_port_we = 16'd0;
reg           soc_ddrphy_bankmodel4_activate = 1'd0;
reg    [13:0] soc_ddrphy_bankmodel4_activate_row = 14'd0;
reg           soc_ddrphy_bankmodel4_active = 1'd0;
reg           soc_ddrphy_bankmodel4_precharge = 1'd0;
wire   [20:0] soc_ddrphy_bankmodel4_rdaddr;
reg           soc_ddrphy_bankmodel4_read = 1'd0;
reg     [9:0] soc_ddrphy_bankmodel4_read_col = 10'd0;
reg   [127:0] soc_ddrphy_bankmodel4_read_data = 128'd0;
reg    [20:0] soc_ddrphy_bankmodel4_read_port_adr = 21'd0;
wire  [127:0] soc_ddrphy_bankmodel4_read_port_dat_r;
reg    [13:0] soc_ddrphy_bankmodel4_row = 14'd0;
wire   [20:0] soc_ddrphy_bankmodel4_wraddr;
wire          soc_ddrphy_bankmodel4_write;
wire    [9:0] soc_ddrphy_bankmodel4_write_col;
wire  [127:0] soc_ddrphy_bankmodel4_write_data;
wire   [15:0] soc_ddrphy_bankmodel4_write_mask;
reg    [20:0] soc_ddrphy_bankmodel4_write_port_adr = 21'd0;
wire  [127:0] soc_ddrphy_bankmodel4_write_port_dat_r;
reg   [127:0] soc_ddrphy_bankmodel4_write_port_dat_w = 128'd0;
reg    [15:0] soc_ddrphy_bankmodel4_write_port_we = 16'd0;
reg           soc_ddrphy_bankmodel5_activate = 1'd0;
reg    [13:0] soc_ddrphy_bankmodel5_activate_row = 14'd0;
reg           soc_ddrphy_bankmodel5_active = 1'd0;
reg           soc_ddrphy_bankmodel5_precharge = 1'd0;
wire   [20:0] soc_ddrphy_bankmodel5_rdaddr;
reg           soc_ddrphy_bankmodel5_read = 1'd0;
reg     [9:0] soc_ddrphy_bankmodel5_read_col = 10'd0;
reg   [127:0] soc_ddrphy_bankmodel5_read_data = 128'd0;
reg    [20:0] soc_ddrphy_bankmodel5_read_port_adr = 21'd0;
wire  [127:0] soc_ddrphy_bankmodel5_read_port_dat_r;
reg    [13:0] soc_ddrphy_bankmodel5_row = 14'd0;
wire   [20:0] soc_ddrphy_bankmodel5_wraddr;
wire          soc_ddrphy_bankmodel5_write;
wire    [9:0] soc_ddrphy_bankmodel5_write_col;
wire  [127:0] soc_ddrphy_bankmodel5_write_data;
wire   [15:0] soc_ddrphy_bankmodel5_write_mask;
reg    [20:0] soc_ddrphy_bankmodel5_write_port_adr = 21'd0;
wire  [127:0] soc_ddrphy_bankmodel5_write_port_dat_r;
reg   [127:0] soc_ddrphy_bankmodel5_write_port_dat_w = 128'd0;
reg    [15:0] soc_ddrphy_bankmodel5_write_port_we = 16'd0;
reg           soc_ddrphy_bankmodel6_activate = 1'd0;
reg    [13:0] soc_ddrphy_bankmodel6_activate_row = 14'd0;
reg           soc_ddrphy_bankmodel6_active = 1'd0;
reg           soc_ddrphy_bankmodel6_precharge = 1'd0;
wire   [20:0] soc_ddrphy_bankmodel6_rdaddr;
reg           soc_ddrphy_bankmodel6_read = 1'd0;
reg     [9:0] soc_ddrphy_bankmodel6_read_col = 10'd0;
reg   [127:0] soc_ddrphy_bankmodel6_read_data = 128'd0;
reg    [20:0] soc_ddrphy_bankmodel6_read_port_adr = 21'd0;
wire  [127:0] soc_ddrphy_bankmodel6_read_port_dat_r;
reg    [13:0] soc_ddrphy_bankmodel6_row = 14'd0;
wire   [20:0] soc_ddrphy_bankmodel6_wraddr;
wire          soc_ddrphy_bankmodel6_write;
wire    [9:0] soc_ddrphy_bankmodel6_write_col;
wire  [127:0] soc_ddrphy_bankmodel6_write_data;
wire   [15:0] soc_ddrphy_bankmodel6_write_mask;
reg    [20:0] soc_ddrphy_bankmodel6_write_port_adr = 21'd0;
wire  [127:0] soc_ddrphy_bankmodel6_write_port_dat_r;
reg   [127:0] soc_ddrphy_bankmodel6_write_port_dat_w = 128'd0;
reg    [15:0] soc_ddrphy_bankmodel6_write_port_we = 16'd0;
reg           soc_ddrphy_bankmodel7_activate = 1'd0;
reg    [13:0] soc_ddrphy_bankmodel7_activate_row = 14'd0;
reg           soc_ddrphy_bankmodel7_active = 1'd0;
reg           soc_ddrphy_bankmodel7_precharge = 1'd0;
wire   [20:0] soc_ddrphy_bankmodel7_rdaddr;
reg           soc_ddrphy_bankmodel7_read = 1'd0;
reg     [9:0] soc_ddrphy_bankmodel7_read_col = 10'd0;
reg   [127:0] soc_ddrphy_bankmodel7_read_data = 128'd0;
reg    [20:0] soc_ddrphy_bankmodel7_read_port_adr = 21'd0;
wire  [127:0] soc_ddrphy_bankmodel7_read_port_dat_r;
reg    [13:0] soc_ddrphy_bankmodel7_row = 14'd0;
wire   [20:0] soc_ddrphy_bankmodel7_wraddr;
wire          soc_ddrphy_bankmodel7_write;
wire    [9:0] soc_ddrphy_bankmodel7_write_col;
wire  [127:0] soc_ddrphy_bankmodel7_write_data;
wire   [15:0] soc_ddrphy_bankmodel7_write_mask;
reg    [20:0] soc_ddrphy_bankmodel7_write_port_adr = 21'd0;
wire  [127:0] soc_ddrphy_bankmodel7_write_port_dat_r;
reg   [127:0] soc_ddrphy_bankmodel7_write_port_dat_w = 128'd0;
reg    [15:0] soc_ddrphy_bankmodel7_write_port_we = 16'd0;
wire          soc_ddrphy_banks_read;
wire  [127:0] soc_ddrphy_banks_read_data;
wire          soc_ddrphy_dfi_p0_act_n;
wire   [13:0] soc_ddrphy_dfi_p0_address;
wire    [2:0] soc_ddrphy_dfi_p0_bank;
wire          soc_ddrphy_dfi_p0_cas_n;
wire          soc_ddrphy_dfi_p0_cke;
wire          soc_ddrphy_dfi_p0_cs_n;
wire          soc_ddrphy_dfi_p0_odt;
wire          soc_ddrphy_dfi_p0_ras_n;
wire   [31:0] soc_ddrphy_dfi_p0_rddata;
wire          soc_ddrphy_dfi_p0_rddata_en;
wire          soc_ddrphy_dfi_p0_rddata_valid;
wire          soc_ddrphy_dfi_p0_reset_n;
wire          soc_ddrphy_dfi_p0_we_n;
wire   [31:0] soc_ddrphy_dfi_p0_wrdata;
wire          soc_ddrphy_dfi_p0_wrdata_en;
wire    [3:0] soc_ddrphy_dfi_p0_wrdata_mask;
wire          soc_ddrphy_dfi_p1_act_n;
wire   [13:0] soc_ddrphy_dfi_p1_address;
wire    [2:0] soc_ddrphy_dfi_p1_bank;
wire          soc_ddrphy_dfi_p1_cas_n;
wire          soc_ddrphy_dfi_p1_cke;
wire          soc_ddrphy_dfi_p1_cs_n;
wire          soc_ddrphy_dfi_p1_odt;
wire          soc_ddrphy_dfi_p1_ras_n;
wire   [31:0] soc_ddrphy_dfi_p1_rddata;
wire          soc_ddrphy_dfi_p1_rddata_en;
wire          soc_ddrphy_dfi_p1_rddata_valid;
wire          soc_ddrphy_dfi_p1_reset_n;
wire          soc_ddrphy_dfi_p1_we_n;
wire   [31:0] soc_ddrphy_dfi_p1_wrdata;
wire          soc_ddrphy_dfi_p1_wrdata_en;
wire    [3:0] soc_ddrphy_dfi_p1_wrdata_mask;
wire          soc_ddrphy_dfi_p2_act_n;
wire   [13:0] soc_ddrphy_dfi_p2_address;
wire    [2:0] soc_ddrphy_dfi_p2_bank;
wire          soc_ddrphy_dfi_p2_cas_n;
wire          soc_ddrphy_dfi_p2_cke;
wire          soc_ddrphy_dfi_p2_cs_n;
wire          soc_ddrphy_dfi_p2_odt;
wire          soc_ddrphy_dfi_p2_ras_n;
wire   [31:0] soc_ddrphy_dfi_p2_rddata;
wire          soc_ddrphy_dfi_p2_rddata_en;
wire          soc_ddrphy_dfi_p2_rddata_valid;
wire          soc_ddrphy_dfi_p2_reset_n;
wire          soc_ddrphy_dfi_p2_we_n;
wire   [31:0] soc_ddrphy_dfi_p2_wrdata;
wire          soc_ddrphy_dfi_p2_wrdata_en;
wire    [3:0] soc_ddrphy_dfi_p2_wrdata_mask;
wire          soc_ddrphy_dfi_p3_act_n;
wire   [13:0] soc_ddrphy_dfi_p3_address;
wire    [2:0] soc_ddrphy_dfi_p3_bank;
wire          soc_ddrphy_dfi_p3_cas_n;
wire          soc_ddrphy_dfi_p3_cke;
wire          soc_ddrphy_dfi_p3_cs_n;
wire          soc_ddrphy_dfi_p3_odt;
wire          soc_ddrphy_dfi_p3_ras_n;
wire   [31:0] soc_ddrphy_dfi_p3_rddata;
wire          soc_ddrphy_dfi_p3_rddata_en;
wire          soc_ddrphy_dfi_p3_rddata_valid;
wire          soc_ddrphy_dfi_p3_reset_n;
wire          soc_ddrphy_dfi_p3_we_n;
wire   [31:0] soc_ddrphy_dfi_p3_wrdata;
wire          soc_ddrphy_dfi_p3_wrdata_en;
wire    [3:0] soc_ddrphy_dfi_p3_wrdata_mask;
reg           soc_ddrphy_dfiphasemodel0_activate = 1'd0;
reg           soc_ddrphy_dfiphasemodel0_precharge = 1'd0;
reg           soc_ddrphy_dfiphasemodel0_read = 1'd0;
reg           soc_ddrphy_dfiphasemodel0_write = 1'd0;
reg           soc_ddrphy_dfiphasemodel1_activate = 1'd0;
reg           soc_ddrphy_dfiphasemodel1_precharge = 1'd0;
reg           soc_ddrphy_dfiphasemodel1_read = 1'd0;
reg           soc_ddrphy_dfiphasemodel1_write = 1'd0;
reg           soc_ddrphy_dfiphasemodel2_activate = 1'd0;
reg           soc_ddrphy_dfiphasemodel2_precharge = 1'd0;
reg           soc_ddrphy_dfiphasemodel2_read = 1'd0;
reg           soc_ddrphy_dfiphasemodel2_write = 1'd0;
reg           soc_ddrphy_dfiphasemodel3_activate = 1'd0;
reg           soc_ddrphy_dfiphasemodel3_precharge = 1'd0;
reg           soc_ddrphy_dfiphasemodel3_read = 1'd0;
reg           soc_ddrphy_dfiphasemodel3_write = 1'd0;
reg           soc_ddrphy_new_bank_write0 = 1'd0;
reg           soc_ddrphy_new_bank_write1 = 1'd0;
reg           soc_ddrphy_new_bank_write2 = 1'd0;
reg           soc_ddrphy_new_bank_write3 = 1'd0;
reg           soc_ddrphy_new_bank_write4 = 1'd0;
reg           soc_ddrphy_new_bank_write5 = 1'd0;
reg           soc_ddrphy_new_bank_write6 = 1'd0;
reg           soc_ddrphy_new_bank_write7 = 1'd0;
reg     [9:0] soc_ddrphy_new_bank_write_col0 = 10'd0;
reg     [9:0] soc_ddrphy_new_bank_write_col1 = 10'd0;
reg     [9:0] soc_ddrphy_new_bank_write_col2 = 10'd0;
reg     [9:0] soc_ddrphy_new_bank_write_col3 = 10'd0;
reg     [9:0] soc_ddrphy_new_bank_write_col4 = 10'd0;
reg     [9:0] soc_ddrphy_new_bank_write_col5 = 10'd0;
reg     [9:0] soc_ddrphy_new_bank_write_col6 = 10'd0;
reg     [9:0] soc_ddrphy_new_bank_write_col7 = 10'd0;
reg           soc_ddrphy_new_banks_read0 = 1'd0;
reg           soc_ddrphy_new_banks_read1 = 1'd0;
reg           soc_ddrphy_new_banks_read2 = 1'd0;
reg           soc_ddrphy_new_banks_read3 = 1'd0;
reg           soc_ddrphy_new_banks_read4 = 1'd0;
reg           soc_ddrphy_new_banks_read5 = 1'd0;
reg           soc_ddrphy_new_banks_read6 = 1'd0;
reg           soc_ddrphy_new_banks_read7 = 1'd0;
reg   [127:0] soc_ddrphy_new_banks_read_data0 = 128'd0;
reg   [127:0] soc_ddrphy_new_banks_read_data1 = 128'd0;
reg   [127:0] soc_ddrphy_new_banks_read_data2 = 128'd0;
reg   [127:0] soc_ddrphy_new_banks_read_data3 = 128'd0;
reg   [127:0] soc_ddrphy_new_banks_read_data4 = 128'd0;
reg   [127:0] soc_ddrphy_new_banks_read_data5 = 128'd0;
reg   [127:0] soc_ddrphy_new_banks_read_data6 = 128'd0;
reg   [127:0] soc_ddrphy_new_banks_read_data7 = 128'd0;
reg     [3:0] soc_ddrphy_precharges0 = 4'd0;
reg     [3:0] soc_ddrphy_precharges1 = 4'd0;
reg     [3:0] soc_ddrphy_precharges2 = 4'd0;
reg     [3:0] soc_ddrphy_precharges3 = 4'd0;
reg     [3:0] soc_ddrphy_precharges4 = 4'd0;
reg     [3:0] soc_ddrphy_precharges5 = 4'd0;
reg     [3:0] soc_ddrphy_precharges6 = 4'd0;
reg     [3:0] soc_ddrphy_precharges7 = 4'd0;
reg     [3:0] soc_ddrphy_reads0 = 4'd0;
reg     [3:0] soc_ddrphy_reads1 = 4'd0;
reg     [3:0] soc_ddrphy_reads2 = 4'd0;
reg     [3:0] soc_ddrphy_reads3 = 4'd0;
reg     [3:0] soc_ddrphy_reads4 = 4'd0;
reg     [3:0] soc_ddrphy_reads5 = 4'd0;
reg     [3:0] soc_ddrphy_reads6 = 4'd0;
reg     [3:0] soc_ddrphy_reads7 = 4'd0;
reg     [3:0] soc_ddrphy_writes0 = 4'd0;
reg     [3:0] soc_ddrphy_writes1 = 4'd0;
reg     [3:0] soc_ddrphy_writes2 = 4'd0;
reg     [3:0] soc_ddrphy_writes3 = 4'd0;
reg     [3:0] soc_ddrphy_writes4 = 4'd0;
reg     [3:0] soc_ddrphy_writes5 = 4'd0;
reg     [3:0] soc_ddrphy_writes6 = 4'd0;
reg     [3:0] soc_ddrphy_writes7 = 4'd0;
reg           soc_init_done_re = 1'd0;
reg           soc_init_done_storage = 1'd0;
reg           soc_init_error_re = 1'd0;
reg           soc_init_error_storage = 1'd0;
reg           soc_int_rst = 1'd1;
reg           soc_litedramcore_bankmachine0_auto_precharge = 1'd0;
reg    [13:0] soc_litedramcore_bankmachine0_cmd_payload_a = 14'd0;
wire    [2:0] soc_litedramcore_bankmachine0_cmd_payload_ba;
reg           soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
reg           soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
reg           soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
reg           soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
reg           soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
reg           soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
reg           soc_litedramcore_bankmachine0_cmd_ready = 1'd0;
reg           soc_litedramcore_bankmachine0_cmd_valid = 1'd0;
reg     [3:0] soc_litedramcore_bankmachine0_consume = 4'd0;
wire          soc_litedramcore_bankmachine0_do_read;
wire          soc_litedramcore_bankmachine0_fifo_in_first;
wire          soc_litedramcore_bankmachine0_fifo_in_last;
wire   [20:0] soc_litedramcore_bankmachine0_fifo_in_payload_addr;
wire          soc_litedramcore_bankmachine0_fifo_in_payload_we;
wire          soc_litedramcore_bankmachine0_fifo_out_first;
wire          soc_litedramcore_bankmachine0_fifo_out_last;
wire   [20:0] soc_litedramcore_bankmachine0_fifo_out_payload_addr;
wire          soc_litedramcore_bankmachine0_fifo_out_payload_we;
reg     [4:0] soc_litedramcore_bankmachine0_level = 5'd0;
wire          soc_litedramcore_bankmachine0_pipe_valid_sink_first;
wire          soc_litedramcore_bankmachine0_pipe_valid_sink_last;
wire   [20:0] soc_litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
wire          soc_litedramcore_bankmachine0_pipe_valid_sink_payload_we;
wire          soc_litedramcore_bankmachine0_pipe_valid_sink_ready;
wire          soc_litedramcore_bankmachine0_pipe_valid_sink_valid;
reg           soc_litedramcore_bankmachine0_pipe_valid_source_first = 1'd0;
reg           soc_litedramcore_bankmachine0_pipe_valid_source_last = 1'd0;
reg    [20:0] soc_litedramcore_bankmachine0_pipe_valid_source_payload_addr = 21'd0;
reg           soc_litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0;
wire          soc_litedramcore_bankmachine0_pipe_valid_source_ready;
reg           soc_litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0;
reg     [3:0] soc_litedramcore_bankmachine0_produce = 4'd0;
wire    [3:0] soc_litedramcore_bankmachine0_rdport_adr;
wire   [23:0] soc_litedramcore_bankmachine0_rdport_dat_r;
reg           soc_litedramcore_bankmachine0_refresh_gnt = 1'd0;
wire          soc_litedramcore_bankmachine0_refresh_req;
reg           soc_litedramcore_bankmachine0_replace = 1'd0;
wire   [20:0] soc_litedramcore_bankmachine0_req_addr;
wire          soc_litedramcore_bankmachine0_req_lock;
reg           soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
wire          soc_litedramcore_bankmachine0_req_ready;
wire          soc_litedramcore_bankmachine0_req_valid;
reg           soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
wire          soc_litedramcore_bankmachine0_req_we;
reg    [13:0] soc_litedramcore_bankmachine0_row = 14'd0;
reg           soc_litedramcore_bankmachine0_row_close = 1'd0;
reg           soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
wire          soc_litedramcore_bankmachine0_row_hit;
reg           soc_litedramcore_bankmachine0_row_open = 1'd0;
reg           soc_litedramcore_bankmachine0_row_opened = 1'd0;
reg           soc_litedramcore_bankmachine0_sink_first = 1'd0;
reg           soc_litedramcore_bankmachine0_sink_last = 1'd0;
wire   [20:0] soc_litedramcore_bankmachine0_sink_payload_addr;
wire          soc_litedramcore_bankmachine0_sink_payload_we;
wire          soc_litedramcore_bankmachine0_sink_ready;
wire          soc_litedramcore_bankmachine0_sink_sink_first;
wire          soc_litedramcore_bankmachine0_sink_sink_last;
wire   [20:0] soc_litedramcore_bankmachine0_sink_sink_payload_addr;
wire          soc_litedramcore_bankmachine0_sink_sink_payload_we;
wire          soc_litedramcore_bankmachine0_sink_sink_ready;
wire          soc_litedramcore_bankmachine0_sink_sink_valid;
wire          soc_litedramcore_bankmachine0_sink_valid;
wire          soc_litedramcore_bankmachine0_source_first;
wire          soc_litedramcore_bankmachine0_source_last;
wire   [20:0] soc_litedramcore_bankmachine0_source_payload_addr;
wire          soc_litedramcore_bankmachine0_source_payload_we;
wire          soc_litedramcore_bankmachine0_source_ready;
wire          soc_litedramcore_bankmachine0_source_source_first;
wire          soc_litedramcore_bankmachine0_source_source_last;
wire   [20:0] soc_litedramcore_bankmachine0_source_source_payload_addr;
wire          soc_litedramcore_bankmachine0_source_source_payload_we;
wire          soc_litedramcore_bankmachine0_source_source_ready;
wire          soc_litedramcore_bankmachine0_source_source_valid;
wire          soc_litedramcore_bankmachine0_source_valid;
wire   [23:0] soc_litedramcore_bankmachine0_syncfifo0_din;
wire   [23:0] soc_litedramcore_bankmachine0_syncfifo0_dout;
wire          soc_litedramcore_bankmachine0_syncfifo0_re;
wire          soc_litedramcore_bankmachine0_syncfifo0_readable;
wire          soc_litedramcore_bankmachine0_syncfifo0_we;
wire          soc_litedramcore_bankmachine0_syncfifo0_writable;
reg     [2:0] soc_litedramcore_bankmachine0_trascon_count = 3'd0;
reg           soc_litedramcore_bankmachine0_trascon_ready = 1'd0;
wire          soc_litedramcore_bankmachine0_trascon_valid;
reg     [2:0] soc_litedramcore_bankmachine0_trccon_count = 3'd0;
reg           soc_litedramcore_bankmachine0_trccon_ready = 1'd0;
wire          soc_litedramcore_bankmachine0_trccon_valid;
reg     [2:0] soc_litedramcore_bankmachine0_twtpcon_count = 3'd0;
reg           soc_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
wire          soc_litedramcore_bankmachine0_twtpcon_valid;
reg     [3:0] soc_litedramcore_bankmachine0_wrport_adr = 4'd0;
wire   [23:0] soc_litedramcore_bankmachine0_wrport_dat_r;
wire   [23:0] soc_litedramcore_bankmachine0_wrport_dat_w;
wire          soc_litedramcore_bankmachine0_wrport_we;
reg           soc_litedramcore_bankmachine1_auto_precharge = 1'd0;
reg    [13:0] soc_litedramcore_bankmachine1_cmd_payload_a = 14'd0;
wire    [2:0] soc_litedramcore_bankmachine1_cmd_payload_ba;
reg           soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
reg           soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
reg           soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
reg           soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
reg           soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
reg           soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
reg           soc_litedramcore_bankmachine1_cmd_ready = 1'd0;
reg           soc_litedramcore_bankmachine1_cmd_valid = 1'd0;
reg     [3:0] soc_litedramcore_bankmachine1_consume = 4'd0;
wire          soc_litedramcore_bankmachine1_do_read;
wire          soc_litedramcore_bankmachine1_fifo_in_first;
wire          soc_litedramcore_bankmachine1_fifo_in_last;
wire   [20:0] soc_litedramcore_bankmachine1_fifo_in_payload_addr;
wire          soc_litedramcore_bankmachine1_fifo_in_payload_we;
wire          soc_litedramcore_bankmachine1_fifo_out_first;
wire          soc_litedramcore_bankmachine1_fifo_out_last;
wire   [20:0] soc_litedramcore_bankmachine1_fifo_out_payload_addr;
wire          soc_litedramcore_bankmachine1_fifo_out_payload_we;
reg     [4:0] soc_litedramcore_bankmachine1_level = 5'd0;
wire          soc_litedramcore_bankmachine1_pipe_valid_sink_first;
wire          soc_litedramcore_bankmachine1_pipe_valid_sink_last;
wire   [20:0] soc_litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
wire          soc_litedramcore_bankmachine1_pipe_valid_sink_payload_we;
wire          soc_litedramcore_bankmachine1_pipe_valid_sink_ready;
wire          soc_litedramcore_bankmachine1_pipe_valid_sink_valid;
reg           soc_litedramcore_bankmachine1_pipe_valid_source_first = 1'd0;
reg           soc_litedramcore_bankmachine1_pipe_valid_source_last = 1'd0;
reg    [20:0] soc_litedramcore_bankmachine1_pipe_valid_source_payload_addr = 21'd0;
reg           soc_litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0;
wire          soc_litedramcore_bankmachine1_pipe_valid_source_ready;
reg           soc_litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0;
reg     [3:0] soc_litedramcore_bankmachine1_produce = 4'd0;
wire    [3:0] soc_litedramcore_bankmachine1_rdport_adr;
wire   [23:0] soc_litedramcore_bankmachine1_rdport_dat_r;
reg           soc_litedramcore_bankmachine1_refresh_gnt = 1'd0;
wire          soc_litedramcore_bankmachine1_refresh_req;
reg           soc_litedramcore_bankmachine1_replace = 1'd0;
wire   [20:0] soc_litedramcore_bankmachine1_req_addr;
wire          soc_litedramcore_bankmachine1_req_lock;
reg           soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
wire          soc_litedramcore_bankmachine1_req_ready;
wire          soc_litedramcore_bankmachine1_req_valid;
reg           soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
wire          soc_litedramcore_bankmachine1_req_we;
reg    [13:0] soc_litedramcore_bankmachine1_row = 14'd0;
reg           soc_litedramcore_bankmachine1_row_close = 1'd0;
reg           soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
wire          soc_litedramcore_bankmachine1_row_hit;
reg           soc_litedramcore_bankmachine1_row_open = 1'd0;
reg           soc_litedramcore_bankmachine1_row_opened = 1'd0;
reg           soc_litedramcore_bankmachine1_sink_first = 1'd0;
reg           soc_litedramcore_bankmachine1_sink_last = 1'd0;
wire   [20:0] soc_litedramcore_bankmachine1_sink_payload_addr;
wire          soc_litedramcore_bankmachine1_sink_payload_we;
wire          soc_litedramcore_bankmachine1_sink_ready;
wire          soc_litedramcore_bankmachine1_sink_sink_first;
wire          soc_litedramcore_bankmachine1_sink_sink_last;
wire   [20:0] soc_litedramcore_bankmachine1_sink_sink_payload_addr;
wire          soc_litedramcore_bankmachine1_sink_sink_payload_we;
wire          soc_litedramcore_bankmachine1_sink_sink_ready;
wire          soc_litedramcore_bankmachine1_sink_sink_valid;
wire          soc_litedramcore_bankmachine1_sink_valid;
wire          soc_litedramcore_bankmachine1_source_first;
wire          soc_litedramcore_bankmachine1_source_last;
wire   [20:0] soc_litedramcore_bankmachine1_source_payload_addr;
wire          soc_litedramcore_bankmachine1_source_payload_we;
wire          soc_litedramcore_bankmachine1_source_ready;
wire          soc_litedramcore_bankmachine1_source_source_first;
wire          soc_litedramcore_bankmachine1_source_source_last;
wire   [20:0] soc_litedramcore_bankmachine1_source_source_payload_addr;
wire          soc_litedramcore_bankmachine1_source_source_payload_we;
wire          soc_litedramcore_bankmachine1_source_source_ready;
wire          soc_litedramcore_bankmachine1_source_source_valid;
wire          soc_litedramcore_bankmachine1_source_valid;
wire   [23:0] soc_litedramcore_bankmachine1_syncfifo1_din;
wire   [23:0] soc_litedramcore_bankmachine1_syncfifo1_dout;
wire          soc_litedramcore_bankmachine1_syncfifo1_re;
wire          soc_litedramcore_bankmachine1_syncfifo1_readable;
wire          soc_litedramcore_bankmachine1_syncfifo1_we;
wire          soc_litedramcore_bankmachine1_syncfifo1_writable;
reg     [2:0] soc_litedramcore_bankmachine1_trascon_count = 3'd0;
reg           soc_litedramcore_bankmachine1_trascon_ready = 1'd0;
wire          soc_litedramcore_bankmachine1_trascon_valid;
reg     [2:0] soc_litedramcore_bankmachine1_trccon_count = 3'd0;
reg           soc_litedramcore_bankmachine1_trccon_ready = 1'd0;
wire          soc_litedramcore_bankmachine1_trccon_valid;
reg     [2:0] soc_litedramcore_bankmachine1_twtpcon_count = 3'd0;
reg           soc_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
wire          soc_litedramcore_bankmachine1_twtpcon_valid;
reg     [3:0] soc_litedramcore_bankmachine1_wrport_adr = 4'd0;
wire   [23:0] soc_litedramcore_bankmachine1_wrport_dat_r;
wire   [23:0] soc_litedramcore_bankmachine1_wrport_dat_w;
wire          soc_litedramcore_bankmachine1_wrport_we;
reg           soc_litedramcore_bankmachine2_auto_precharge = 1'd0;
reg    [13:0] soc_litedramcore_bankmachine2_cmd_payload_a = 14'd0;
wire    [2:0] soc_litedramcore_bankmachine2_cmd_payload_ba;
reg           soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
reg           soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
reg           soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
reg           soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
reg           soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
reg           soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
reg           soc_litedramcore_bankmachine2_cmd_ready = 1'd0;
reg           soc_litedramcore_bankmachine2_cmd_valid = 1'd0;
reg     [3:0] soc_litedramcore_bankmachine2_consume = 4'd0;
wire          soc_litedramcore_bankmachine2_do_read;
wire          soc_litedramcore_bankmachine2_fifo_in_first;
wire          soc_litedramcore_bankmachine2_fifo_in_last;
wire   [20:0] soc_litedramcore_bankmachine2_fifo_in_payload_addr;
wire          soc_litedramcore_bankmachine2_fifo_in_payload_we;
wire          soc_litedramcore_bankmachine2_fifo_out_first;
wire          soc_litedramcore_bankmachine2_fifo_out_last;
wire   [20:0] soc_litedramcore_bankmachine2_fifo_out_payload_addr;
wire          soc_litedramcore_bankmachine2_fifo_out_payload_we;
reg     [4:0] soc_litedramcore_bankmachine2_level = 5'd0;
wire          soc_litedramcore_bankmachine2_pipe_valid_sink_first;
wire          soc_litedramcore_bankmachine2_pipe_valid_sink_last;
wire   [20:0] soc_litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
wire          soc_litedramcore_bankmachine2_pipe_valid_sink_payload_we;
wire          soc_litedramcore_bankmachine2_pipe_valid_sink_ready;
wire          soc_litedramcore_bankmachine2_pipe_valid_sink_valid;
reg           soc_litedramcore_bankmachine2_pipe_valid_source_first = 1'd0;
reg           soc_litedramcore_bankmachine2_pipe_valid_source_last = 1'd0;
reg    [20:0] soc_litedramcore_bankmachine2_pipe_valid_source_payload_addr = 21'd0;
reg           soc_litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0;
wire          soc_litedramcore_bankmachine2_pipe_valid_source_ready;
reg           soc_litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0;
reg     [3:0] soc_litedramcore_bankmachine2_produce = 4'd0;
wire    [3:0] soc_litedramcore_bankmachine2_rdport_adr;
wire   [23:0] soc_litedramcore_bankmachine2_rdport_dat_r;
reg           soc_litedramcore_bankmachine2_refresh_gnt = 1'd0;
wire          soc_litedramcore_bankmachine2_refresh_req;
reg           soc_litedramcore_bankmachine2_replace = 1'd0;
wire   [20:0] soc_litedramcore_bankmachine2_req_addr;
wire          soc_litedramcore_bankmachine2_req_lock;
reg           soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
wire          soc_litedramcore_bankmachine2_req_ready;
wire          soc_litedramcore_bankmachine2_req_valid;
reg           soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
wire          soc_litedramcore_bankmachine2_req_we;
reg    [13:0] soc_litedramcore_bankmachine2_row = 14'd0;
reg           soc_litedramcore_bankmachine2_row_close = 1'd0;
reg           soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
wire          soc_litedramcore_bankmachine2_row_hit;
reg           soc_litedramcore_bankmachine2_row_open = 1'd0;
reg           soc_litedramcore_bankmachine2_row_opened = 1'd0;
reg           soc_litedramcore_bankmachine2_sink_first = 1'd0;
reg           soc_litedramcore_bankmachine2_sink_last = 1'd0;
wire   [20:0] soc_litedramcore_bankmachine2_sink_payload_addr;
wire          soc_litedramcore_bankmachine2_sink_payload_we;
wire          soc_litedramcore_bankmachine2_sink_ready;
wire          soc_litedramcore_bankmachine2_sink_sink_first;
wire          soc_litedramcore_bankmachine2_sink_sink_last;
wire   [20:0] soc_litedramcore_bankmachine2_sink_sink_payload_addr;
wire          soc_litedramcore_bankmachine2_sink_sink_payload_we;
wire          soc_litedramcore_bankmachine2_sink_sink_ready;
wire          soc_litedramcore_bankmachine2_sink_sink_valid;
wire          soc_litedramcore_bankmachine2_sink_valid;
wire          soc_litedramcore_bankmachine2_source_first;
wire          soc_litedramcore_bankmachine2_source_last;
wire   [20:0] soc_litedramcore_bankmachine2_source_payload_addr;
wire          soc_litedramcore_bankmachine2_source_payload_we;
wire          soc_litedramcore_bankmachine2_source_ready;
wire          soc_litedramcore_bankmachine2_source_source_first;
wire          soc_litedramcore_bankmachine2_source_source_last;
wire   [20:0] soc_litedramcore_bankmachine2_source_source_payload_addr;
wire          soc_litedramcore_bankmachine2_source_source_payload_we;
wire          soc_litedramcore_bankmachine2_source_source_ready;
wire          soc_litedramcore_bankmachine2_source_source_valid;
wire          soc_litedramcore_bankmachine2_source_valid;
wire   [23:0] soc_litedramcore_bankmachine2_syncfifo2_din;
wire   [23:0] soc_litedramcore_bankmachine2_syncfifo2_dout;
wire          soc_litedramcore_bankmachine2_syncfifo2_re;
wire          soc_litedramcore_bankmachine2_syncfifo2_readable;
wire          soc_litedramcore_bankmachine2_syncfifo2_we;
wire          soc_litedramcore_bankmachine2_syncfifo2_writable;
reg     [2:0] soc_litedramcore_bankmachine2_trascon_count = 3'd0;
reg           soc_litedramcore_bankmachine2_trascon_ready = 1'd0;
wire          soc_litedramcore_bankmachine2_trascon_valid;
reg     [2:0] soc_litedramcore_bankmachine2_trccon_count = 3'd0;
reg           soc_litedramcore_bankmachine2_trccon_ready = 1'd0;
wire          soc_litedramcore_bankmachine2_trccon_valid;
reg     [2:0] soc_litedramcore_bankmachine2_twtpcon_count = 3'd0;
reg           soc_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
wire          soc_litedramcore_bankmachine2_twtpcon_valid;
reg     [3:0] soc_litedramcore_bankmachine2_wrport_adr = 4'd0;
wire   [23:0] soc_litedramcore_bankmachine2_wrport_dat_r;
wire   [23:0] soc_litedramcore_bankmachine2_wrport_dat_w;
wire          soc_litedramcore_bankmachine2_wrport_we;
reg           soc_litedramcore_bankmachine3_auto_precharge = 1'd0;
reg    [13:0] soc_litedramcore_bankmachine3_cmd_payload_a = 14'd0;
wire    [2:0] soc_litedramcore_bankmachine3_cmd_payload_ba;
reg           soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
reg           soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
reg           soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
reg           soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
reg           soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
reg           soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
reg           soc_litedramcore_bankmachine3_cmd_ready = 1'd0;
reg           soc_litedramcore_bankmachine3_cmd_valid = 1'd0;
reg     [3:0] soc_litedramcore_bankmachine3_consume = 4'd0;
wire          soc_litedramcore_bankmachine3_do_read;
wire          soc_litedramcore_bankmachine3_fifo_in_first;
wire          soc_litedramcore_bankmachine3_fifo_in_last;
wire   [20:0] soc_litedramcore_bankmachine3_fifo_in_payload_addr;
wire          soc_litedramcore_bankmachine3_fifo_in_payload_we;
wire          soc_litedramcore_bankmachine3_fifo_out_first;
wire          soc_litedramcore_bankmachine3_fifo_out_last;
wire   [20:0] soc_litedramcore_bankmachine3_fifo_out_payload_addr;
wire          soc_litedramcore_bankmachine3_fifo_out_payload_we;
reg     [4:0] soc_litedramcore_bankmachine3_level = 5'd0;
wire          soc_litedramcore_bankmachine3_pipe_valid_sink_first;
wire          soc_litedramcore_bankmachine3_pipe_valid_sink_last;
wire   [20:0] soc_litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
wire          soc_litedramcore_bankmachine3_pipe_valid_sink_payload_we;
wire          soc_litedramcore_bankmachine3_pipe_valid_sink_ready;
wire          soc_litedramcore_bankmachine3_pipe_valid_sink_valid;
reg           soc_litedramcore_bankmachine3_pipe_valid_source_first = 1'd0;
reg           soc_litedramcore_bankmachine3_pipe_valid_source_last = 1'd0;
reg    [20:0] soc_litedramcore_bankmachine3_pipe_valid_source_payload_addr = 21'd0;
reg           soc_litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0;
wire          soc_litedramcore_bankmachine3_pipe_valid_source_ready;
reg           soc_litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0;
reg     [3:0] soc_litedramcore_bankmachine3_produce = 4'd0;
wire    [3:0] soc_litedramcore_bankmachine3_rdport_adr;
wire   [23:0] soc_litedramcore_bankmachine3_rdport_dat_r;
reg           soc_litedramcore_bankmachine3_refresh_gnt = 1'd0;
wire          soc_litedramcore_bankmachine3_refresh_req;
reg           soc_litedramcore_bankmachine3_replace = 1'd0;
wire   [20:0] soc_litedramcore_bankmachine3_req_addr;
wire          soc_litedramcore_bankmachine3_req_lock;
reg           soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
wire          soc_litedramcore_bankmachine3_req_ready;
wire          soc_litedramcore_bankmachine3_req_valid;
reg           soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
wire          soc_litedramcore_bankmachine3_req_we;
reg    [13:0] soc_litedramcore_bankmachine3_row = 14'd0;
reg           soc_litedramcore_bankmachine3_row_close = 1'd0;
reg           soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
wire          soc_litedramcore_bankmachine3_row_hit;
reg           soc_litedramcore_bankmachine3_row_open = 1'd0;
reg           soc_litedramcore_bankmachine3_row_opened = 1'd0;
reg           soc_litedramcore_bankmachine3_sink_first = 1'd0;
reg           soc_litedramcore_bankmachine3_sink_last = 1'd0;
wire   [20:0] soc_litedramcore_bankmachine3_sink_payload_addr;
wire          soc_litedramcore_bankmachine3_sink_payload_we;
wire          soc_litedramcore_bankmachine3_sink_ready;
wire          soc_litedramcore_bankmachine3_sink_sink_first;
wire          soc_litedramcore_bankmachine3_sink_sink_last;
wire   [20:0] soc_litedramcore_bankmachine3_sink_sink_payload_addr;
wire          soc_litedramcore_bankmachine3_sink_sink_payload_we;
wire          soc_litedramcore_bankmachine3_sink_sink_ready;
wire          soc_litedramcore_bankmachine3_sink_sink_valid;
wire          soc_litedramcore_bankmachine3_sink_valid;
wire          soc_litedramcore_bankmachine3_source_first;
wire          soc_litedramcore_bankmachine3_source_last;
wire   [20:0] soc_litedramcore_bankmachine3_source_payload_addr;
wire          soc_litedramcore_bankmachine3_source_payload_we;
wire          soc_litedramcore_bankmachine3_source_ready;
wire          soc_litedramcore_bankmachine3_source_source_first;
wire          soc_litedramcore_bankmachine3_source_source_last;
wire   [20:0] soc_litedramcore_bankmachine3_source_source_payload_addr;
wire          soc_litedramcore_bankmachine3_source_source_payload_we;
wire          soc_litedramcore_bankmachine3_source_source_ready;
wire          soc_litedramcore_bankmachine3_source_source_valid;
wire          soc_litedramcore_bankmachine3_source_valid;
wire   [23:0] soc_litedramcore_bankmachine3_syncfifo3_din;
wire   [23:0] soc_litedramcore_bankmachine3_syncfifo3_dout;
wire          soc_litedramcore_bankmachine3_syncfifo3_re;
wire          soc_litedramcore_bankmachine3_syncfifo3_readable;
wire          soc_litedramcore_bankmachine3_syncfifo3_we;
wire          soc_litedramcore_bankmachine3_syncfifo3_writable;
reg     [2:0] soc_litedramcore_bankmachine3_trascon_count = 3'd0;
reg           soc_litedramcore_bankmachine3_trascon_ready = 1'd0;
wire          soc_litedramcore_bankmachine3_trascon_valid;
reg     [2:0] soc_litedramcore_bankmachine3_trccon_count = 3'd0;
reg           soc_litedramcore_bankmachine3_trccon_ready = 1'd0;
wire          soc_litedramcore_bankmachine3_trccon_valid;
reg     [2:0] soc_litedramcore_bankmachine3_twtpcon_count = 3'd0;
reg           soc_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
wire          soc_litedramcore_bankmachine3_twtpcon_valid;
reg     [3:0] soc_litedramcore_bankmachine3_wrport_adr = 4'd0;
wire   [23:0] soc_litedramcore_bankmachine3_wrport_dat_r;
wire   [23:0] soc_litedramcore_bankmachine3_wrport_dat_w;
wire          soc_litedramcore_bankmachine3_wrport_we;
reg           soc_litedramcore_bankmachine4_auto_precharge = 1'd0;
reg    [13:0] soc_litedramcore_bankmachine4_cmd_payload_a = 14'd0;
wire    [2:0] soc_litedramcore_bankmachine4_cmd_payload_ba;
reg           soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
reg           soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
reg           soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
reg           soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
reg           soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
reg           soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
reg           soc_litedramcore_bankmachine4_cmd_ready = 1'd0;
reg           soc_litedramcore_bankmachine4_cmd_valid = 1'd0;
reg     [3:0] soc_litedramcore_bankmachine4_consume = 4'd0;
wire          soc_litedramcore_bankmachine4_do_read;
wire          soc_litedramcore_bankmachine4_fifo_in_first;
wire          soc_litedramcore_bankmachine4_fifo_in_last;
wire   [20:0] soc_litedramcore_bankmachine4_fifo_in_payload_addr;
wire          soc_litedramcore_bankmachine4_fifo_in_payload_we;
wire          soc_litedramcore_bankmachine4_fifo_out_first;
wire          soc_litedramcore_bankmachine4_fifo_out_last;
wire   [20:0] soc_litedramcore_bankmachine4_fifo_out_payload_addr;
wire          soc_litedramcore_bankmachine4_fifo_out_payload_we;
reg     [4:0] soc_litedramcore_bankmachine4_level = 5'd0;
wire          soc_litedramcore_bankmachine4_pipe_valid_sink_first;
wire          soc_litedramcore_bankmachine4_pipe_valid_sink_last;
wire   [20:0] soc_litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
wire          soc_litedramcore_bankmachine4_pipe_valid_sink_payload_we;
wire          soc_litedramcore_bankmachine4_pipe_valid_sink_ready;
wire          soc_litedramcore_bankmachine4_pipe_valid_sink_valid;
reg           soc_litedramcore_bankmachine4_pipe_valid_source_first = 1'd0;
reg           soc_litedramcore_bankmachine4_pipe_valid_source_last = 1'd0;
reg    [20:0] soc_litedramcore_bankmachine4_pipe_valid_source_payload_addr = 21'd0;
reg           soc_litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0;
wire          soc_litedramcore_bankmachine4_pipe_valid_source_ready;
reg           soc_litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0;
reg     [3:0] soc_litedramcore_bankmachine4_produce = 4'd0;
wire    [3:0] soc_litedramcore_bankmachine4_rdport_adr;
wire   [23:0] soc_litedramcore_bankmachine4_rdport_dat_r;
reg           soc_litedramcore_bankmachine4_refresh_gnt = 1'd0;
wire          soc_litedramcore_bankmachine4_refresh_req;
reg           soc_litedramcore_bankmachine4_replace = 1'd0;
wire   [20:0] soc_litedramcore_bankmachine4_req_addr;
wire          soc_litedramcore_bankmachine4_req_lock;
reg           soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
wire          soc_litedramcore_bankmachine4_req_ready;
wire          soc_litedramcore_bankmachine4_req_valid;
reg           soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
wire          soc_litedramcore_bankmachine4_req_we;
reg    [13:0] soc_litedramcore_bankmachine4_row = 14'd0;
reg           soc_litedramcore_bankmachine4_row_close = 1'd0;
reg           soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
wire          soc_litedramcore_bankmachine4_row_hit;
reg           soc_litedramcore_bankmachine4_row_open = 1'd0;
reg           soc_litedramcore_bankmachine4_row_opened = 1'd0;
reg           soc_litedramcore_bankmachine4_sink_first = 1'd0;
reg           soc_litedramcore_bankmachine4_sink_last = 1'd0;
wire   [20:0] soc_litedramcore_bankmachine4_sink_payload_addr;
wire          soc_litedramcore_bankmachine4_sink_payload_we;
wire          soc_litedramcore_bankmachine4_sink_ready;
wire          soc_litedramcore_bankmachine4_sink_sink_first;
wire          soc_litedramcore_bankmachine4_sink_sink_last;
wire   [20:0] soc_litedramcore_bankmachine4_sink_sink_payload_addr;
wire          soc_litedramcore_bankmachine4_sink_sink_payload_we;
wire          soc_litedramcore_bankmachine4_sink_sink_ready;
wire          soc_litedramcore_bankmachine4_sink_sink_valid;
wire          soc_litedramcore_bankmachine4_sink_valid;
wire          soc_litedramcore_bankmachine4_source_first;
wire          soc_litedramcore_bankmachine4_source_last;
wire   [20:0] soc_litedramcore_bankmachine4_source_payload_addr;
wire          soc_litedramcore_bankmachine4_source_payload_we;
wire          soc_litedramcore_bankmachine4_source_ready;
wire          soc_litedramcore_bankmachine4_source_source_first;
wire          soc_litedramcore_bankmachine4_source_source_last;
wire   [20:0] soc_litedramcore_bankmachine4_source_source_payload_addr;
wire          soc_litedramcore_bankmachine4_source_source_payload_we;
wire          soc_litedramcore_bankmachine4_source_source_ready;
wire          soc_litedramcore_bankmachine4_source_source_valid;
wire          soc_litedramcore_bankmachine4_source_valid;
wire   [23:0] soc_litedramcore_bankmachine4_syncfifo4_din;
wire   [23:0] soc_litedramcore_bankmachine4_syncfifo4_dout;
wire          soc_litedramcore_bankmachine4_syncfifo4_re;
wire          soc_litedramcore_bankmachine4_syncfifo4_readable;
wire          soc_litedramcore_bankmachine4_syncfifo4_we;
wire          soc_litedramcore_bankmachine4_syncfifo4_writable;
reg     [2:0] soc_litedramcore_bankmachine4_trascon_count = 3'd0;
reg           soc_litedramcore_bankmachine4_trascon_ready = 1'd0;
wire          soc_litedramcore_bankmachine4_trascon_valid;
reg     [2:0] soc_litedramcore_bankmachine4_trccon_count = 3'd0;
reg           soc_litedramcore_bankmachine4_trccon_ready = 1'd0;
wire          soc_litedramcore_bankmachine4_trccon_valid;
reg     [2:0] soc_litedramcore_bankmachine4_twtpcon_count = 3'd0;
reg           soc_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
wire          soc_litedramcore_bankmachine4_twtpcon_valid;
reg     [3:0] soc_litedramcore_bankmachine4_wrport_adr = 4'd0;
wire   [23:0] soc_litedramcore_bankmachine4_wrport_dat_r;
wire   [23:0] soc_litedramcore_bankmachine4_wrport_dat_w;
wire          soc_litedramcore_bankmachine4_wrport_we;
reg           soc_litedramcore_bankmachine5_auto_precharge = 1'd0;
reg    [13:0] soc_litedramcore_bankmachine5_cmd_payload_a = 14'd0;
wire    [2:0] soc_litedramcore_bankmachine5_cmd_payload_ba;
reg           soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
reg           soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
reg           soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
reg           soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
reg           soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
reg           soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
reg           soc_litedramcore_bankmachine5_cmd_ready = 1'd0;
reg           soc_litedramcore_bankmachine5_cmd_valid = 1'd0;
reg     [3:0] soc_litedramcore_bankmachine5_consume = 4'd0;
wire          soc_litedramcore_bankmachine5_do_read;
wire          soc_litedramcore_bankmachine5_fifo_in_first;
wire          soc_litedramcore_bankmachine5_fifo_in_last;
wire   [20:0] soc_litedramcore_bankmachine5_fifo_in_payload_addr;
wire          soc_litedramcore_bankmachine5_fifo_in_payload_we;
wire          soc_litedramcore_bankmachine5_fifo_out_first;
wire          soc_litedramcore_bankmachine5_fifo_out_last;
wire   [20:0] soc_litedramcore_bankmachine5_fifo_out_payload_addr;
wire          soc_litedramcore_bankmachine5_fifo_out_payload_we;
reg     [4:0] soc_litedramcore_bankmachine5_level = 5'd0;
wire          soc_litedramcore_bankmachine5_pipe_valid_sink_first;
wire          soc_litedramcore_bankmachine5_pipe_valid_sink_last;
wire   [20:0] soc_litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
wire          soc_litedramcore_bankmachine5_pipe_valid_sink_payload_we;
wire          soc_litedramcore_bankmachine5_pipe_valid_sink_ready;
wire          soc_litedramcore_bankmachine5_pipe_valid_sink_valid;
reg           soc_litedramcore_bankmachine5_pipe_valid_source_first = 1'd0;
reg           soc_litedramcore_bankmachine5_pipe_valid_source_last = 1'd0;
reg    [20:0] soc_litedramcore_bankmachine5_pipe_valid_source_payload_addr = 21'd0;
reg           soc_litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0;
wire          soc_litedramcore_bankmachine5_pipe_valid_source_ready;
reg           soc_litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0;
reg     [3:0] soc_litedramcore_bankmachine5_produce = 4'd0;
wire    [3:0] soc_litedramcore_bankmachine5_rdport_adr;
wire   [23:0] soc_litedramcore_bankmachine5_rdport_dat_r;
reg           soc_litedramcore_bankmachine5_refresh_gnt = 1'd0;
wire          soc_litedramcore_bankmachine5_refresh_req;
reg           soc_litedramcore_bankmachine5_replace = 1'd0;
wire   [20:0] soc_litedramcore_bankmachine5_req_addr;
wire          soc_litedramcore_bankmachine5_req_lock;
reg           soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
wire          soc_litedramcore_bankmachine5_req_ready;
wire          soc_litedramcore_bankmachine5_req_valid;
reg           soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
wire          soc_litedramcore_bankmachine5_req_we;
reg    [13:0] soc_litedramcore_bankmachine5_row = 14'd0;
reg           soc_litedramcore_bankmachine5_row_close = 1'd0;
reg           soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
wire          soc_litedramcore_bankmachine5_row_hit;
reg           soc_litedramcore_bankmachine5_row_open = 1'd0;
reg           soc_litedramcore_bankmachine5_row_opened = 1'd0;
reg           soc_litedramcore_bankmachine5_sink_first = 1'd0;
reg           soc_litedramcore_bankmachine5_sink_last = 1'd0;
wire   [20:0] soc_litedramcore_bankmachine5_sink_payload_addr;
wire          soc_litedramcore_bankmachine5_sink_payload_we;
wire          soc_litedramcore_bankmachine5_sink_ready;
wire          soc_litedramcore_bankmachine5_sink_sink_first;
wire          soc_litedramcore_bankmachine5_sink_sink_last;
wire   [20:0] soc_litedramcore_bankmachine5_sink_sink_payload_addr;
wire          soc_litedramcore_bankmachine5_sink_sink_payload_we;
wire          soc_litedramcore_bankmachine5_sink_sink_ready;
wire          soc_litedramcore_bankmachine5_sink_sink_valid;
wire          soc_litedramcore_bankmachine5_sink_valid;
wire          soc_litedramcore_bankmachine5_source_first;
wire          soc_litedramcore_bankmachine5_source_last;
wire   [20:0] soc_litedramcore_bankmachine5_source_payload_addr;
wire          soc_litedramcore_bankmachine5_source_payload_we;
wire          soc_litedramcore_bankmachine5_source_ready;
wire          soc_litedramcore_bankmachine5_source_source_first;
wire          soc_litedramcore_bankmachine5_source_source_last;
wire   [20:0] soc_litedramcore_bankmachine5_source_source_payload_addr;
wire          soc_litedramcore_bankmachine5_source_source_payload_we;
wire          soc_litedramcore_bankmachine5_source_source_ready;
wire          soc_litedramcore_bankmachine5_source_source_valid;
wire          soc_litedramcore_bankmachine5_source_valid;
wire   [23:0] soc_litedramcore_bankmachine5_syncfifo5_din;
wire   [23:0] soc_litedramcore_bankmachine5_syncfifo5_dout;
wire          soc_litedramcore_bankmachine5_syncfifo5_re;
wire          soc_litedramcore_bankmachine5_syncfifo5_readable;
wire          soc_litedramcore_bankmachine5_syncfifo5_we;
wire          soc_litedramcore_bankmachine5_syncfifo5_writable;
reg     [2:0] soc_litedramcore_bankmachine5_trascon_count = 3'd0;
reg           soc_litedramcore_bankmachine5_trascon_ready = 1'd0;
wire          soc_litedramcore_bankmachine5_trascon_valid;
reg     [2:0] soc_litedramcore_bankmachine5_trccon_count = 3'd0;
reg           soc_litedramcore_bankmachine5_trccon_ready = 1'd0;
wire          soc_litedramcore_bankmachine5_trccon_valid;
reg     [2:0] soc_litedramcore_bankmachine5_twtpcon_count = 3'd0;
reg           soc_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
wire          soc_litedramcore_bankmachine5_twtpcon_valid;
reg     [3:0] soc_litedramcore_bankmachine5_wrport_adr = 4'd0;
wire   [23:0] soc_litedramcore_bankmachine5_wrport_dat_r;
wire   [23:0] soc_litedramcore_bankmachine5_wrport_dat_w;
wire          soc_litedramcore_bankmachine5_wrport_we;
reg           soc_litedramcore_bankmachine6_auto_precharge = 1'd0;
reg    [13:0] soc_litedramcore_bankmachine6_cmd_payload_a = 14'd0;
wire    [2:0] soc_litedramcore_bankmachine6_cmd_payload_ba;
reg           soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
reg           soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
reg           soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
reg           soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
reg           soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
reg           soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
reg           soc_litedramcore_bankmachine6_cmd_ready = 1'd0;
reg           soc_litedramcore_bankmachine6_cmd_valid = 1'd0;
reg     [3:0] soc_litedramcore_bankmachine6_consume = 4'd0;
wire          soc_litedramcore_bankmachine6_do_read;
wire          soc_litedramcore_bankmachine6_fifo_in_first;
wire          soc_litedramcore_bankmachine6_fifo_in_last;
wire   [20:0] soc_litedramcore_bankmachine6_fifo_in_payload_addr;
wire          soc_litedramcore_bankmachine6_fifo_in_payload_we;
wire          soc_litedramcore_bankmachine6_fifo_out_first;
wire          soc_litedramcore_bankmachine6_fifo_out_last;
wire   [20:0] soc_litedramcore_bankmachine6_fifo_out_payload_addr;
wire          soc_litedramcore_bankmachine6_fifo_out_payload_we;
reg     [4:0] soc_litedramcore_bankmachine6_level = 5'd0;
wire          soc_litedramcore_bankmachine6_pipe_valid_sink_first;
wire          soc_litedramcore_bankmachine6_pipe_valid_sink_last;
wire   [20:0] soc_litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
wire          soc_litedramcore_bankmachine6_pipe_valid_sink_payload_we;
wire          soc_litedramcore_bankmachine6_pipe_valid_sink_ready;
wire          soc_litedramcore_bankmachine6_pipe_valid_sink_valid;
reg           soc_litedramcore_bankmachine6_pipe_valid_source_first = 1'd0;
reg           soc_litedramcore_bankmachine6_pipe_valid_source_last = 1'd0;
reg    [20:0] soc_litedramcore_bankmachine6_pipe_valid_source_payload_addr = 21'd0;
reg           soc_litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0;
wire          soc_litedramcore_bankmachine6_pipe_valid_source_ready;
reg           soc_litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0;
reg     [3:0] soc_litedramcore_bankmachine6_produce = 4'd0;
wire    [3:0] soc_litedramcore_bankmachine6_rdport_adr;
wire   [23:0] soc_litedramcore_bankmachine6_rdport_dat_r;
reg           soc_litedramcore_bankmachine6_refresh_gnt = 1'd0;
wire          soc_litedramcore_bankmachine6_refresh_req;
reg           soc_litedramcore_bankmachine6_replace = 1'd0;
wire   [20:0] soc_litedramcore_bankmachine6_req_addr;
wire          soc_litedramcore_bankmachine6_req_lock;
reg           soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
wire          soc_litedramcore_bankmachine6_req_ready;
wire          soc_litedramcore_bankmachine6_req_valid;
reg           soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
wire          soc_litedramcore_bankmachine6_req_we;
reg    [13:0] soc_litedramcore_bankmachine6_row = 14'd0;
reg           soc_litedramcore_bankmachine6_row_close = 1'd0;
reg           soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
wire          soc_litedramcore_bankmachine6_row_hit;
reg           soc_litedramcore_bankmachine6_row_open = 1'd0;
reg           soc_litedramcore_bankmachine6_row_opened = 1'd0;
reg           soc_litedramcore_bankmachine6_sink_first = 1'd0;
reg           soc_litedramcore_bankmachine6_sink_last = 1'd0;
wire   [20:0] soc_litedramcore_bankmachine6_sink_payload_addr;
wire          soc_litedramcore_bankmachine6_sink_payload_we;
wire          soc_litedramcore_bankmachine6_sink_ready;
wire          soc_litedramcore_bankmachine6_sink_sink_first;
wire          soc_litedramcore_bankmachine6_sink_sink_last;
wire   [20:0] soc_litedramcore_bankmachine6_sink_sink_payload_addr;
wire          soc_litedramcore_bankmachine6_sink_sink_payload_we;
wire          soc_litedramcore_bankmachine6_sink_sink_ready;
wire          soc_litedramcore_bankmachine6_sink_sink_valid;
wire          soc_litedramcore_bankmachine6_sink_valid;
wire          soc_litedramcore_bankmachine6_source_first;
wire          soc_litedramcore_bankmachine6_source_last;
wire   [20:0] soc_litedramcore_bankmachine6_source_payload_addr;
wire          soc_litedramcore_bankmachine6_source_payload_we;
wire          soc_litedramcore_bankmachine6_source_ready;
wire          soc_litedramcore_bankmachine6_source_source_first;
wire          soc_litedramcore_bankmachine6_source_source_last;
wire   [20:0] soc_litedramcore_bankmachine6_source_source_payload_addr;
wire          soc_litedramcore_bankmachine6_source_source_payload_we;
wire          soc_litedramcore_bankmachine6_source_source_ready;
wire          soc_litedramcore_bankmachine6_source_source_valid;
wire          soc_litedramcore_bankmachine6_source_valid;
wire   [23:0] soc_litedramcore_bankmachine6_syncfifo6_din;
wire   [23:0] soc_litedramcore_bankmachine6_syncfifo6_dout;
wire          soc_litedramcore_bankmachine6_syncfifo6_re;
wire          soc_litedramcore_bankmachine6_syncfifo6_readable;
wire          soc_litedramcore_bankmachine6_syncfifo6_we;
wire          soc_litedramcore_bankmachine6_syncfifo6_writable;
reg     [2:0] soc_litedramcore_bankmachine6_trascon_count = 3'd0;
reg           soc_litedramcore_bankmachine6_trascon_ready = 1'd0;
wire          soc_litedramcore_bankmachine6_trascon_valid;
reg     [2:0] soc_litedramcore_bankmachine6_trccon_count = 3'd0;
reg           soc_litedramcore_bankmachine6_trccon_ready = 1'd0;
wire          soc_litedramcore_bankmachine6_trccon_valid;
reg     [2:0] soc_litedramcore_bankmachine6_twtpcon_count = 3'd0;
reg           soc_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
wire          soc_litedramcore_bankmachine6_twtpcon_valid;
reg     [3:0] soc_litedramcore_bankmachine6_wrport_adr = 4'd0;
wire   [23:0] soc_litedramcore_bankmachine6_wrport_dat_r;
wire   [23:0] soc_litedramcore_bankmachine6_wrport_dat_w;
wire          soc_litedramcore_bankmachine6_wrport_we;
reg           soc_litedramcore_bankmachine7_auto_precharge = 1'd0;
reg    [13:0] soc_litedramcore_bankmachine7_cmd_payload_a = 14'd0;
wire    [2:0] soc_litedramcore_bankmachine7_cmd_payload_ba;
reg           soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
reg           soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
reg           soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
reg           soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
reg           soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
reg           soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
reg           soc_litedramcore_bankmachine7_cmd_ready = 1'd0;
reg           soc_litedramcore_bankmachine7_cmd_valid = 1'd0;
reg     [3:0] soc_litedramcore_bankmachine7_consume = 4'd0;
wire          soc_litedramcore_bankmachine7_do_read;
wire          soc_litedramcore_bankmachine7_fifo_in_first;
wire          soc_litedramcore_bankmachine7_fifo_in_last;
wire   [20:0] soc_litedramcore_bankmachine7_fifo_in_payload_addr;
wire          soc_litedramcore_bankmachine7_fifo_in_payload_we;
wire          soc_litedramcore_bankmachine7_fifo_out_first;
wire          soc_litedramcore_bankmachine7_fifo_out_last;
wire   [20:0] soc_litedramcore_bankmachine7_fifo_out_payload_addr;
wire          soc_litedramcore_bankmachine7_fifo_out_payload_we;
reg     [4:0] soc_litedramcore_bankmachine7_level = 5'd0;
wire          soc_litedramcore_bankmachine7_pipe_valid_sink_first;
wire          soc_litedramcore_bankmachine7_pipe_valid_sink_last;
wire   [20:0] soc_litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
wire          soc_litedramcore_bankmachine7_pipe_valid_sink_payload_we;
wire          soc_litedramcore_bankmachine7_pipe_valid_sink_ready;
wire          soc_litedramcore_bankmachine7_pipe_valid_sink_valid;
reg           soc_litedramcore_bankmachine7_pipe_valid_source_first = 1'd0;
reg           soc_litedramcore_bankmachine7_pipe_valid_source_last = 1'd0;
reg    [20:0] soc_litedramcore_bankmachine7_pipe_valid_source_payload_addr = 21'd0;
reg           soc_litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0;
wire          soc_litedramcore_bankmachine7_pipe_valid_source_ready;
reg           soc_litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0;
reg     [3:0] soc_litedramcore_bankmachine7_produce = 4'd0;
wire    [3:0] soc_litedramcore_bankmachine7_rdport_adr;
wire   [23:0] soc_litedramcore_bankmachine7_rdport_dat_r;
reg           soc_litedramcore_bankmachine7_refresh_gnt = 1'd0;
wire          soc_litedramcore_bankmachine7_refresh_req;
reg           soc_litedramcore_bankmachine7_replace = 1'd0;
wire   [20:0] soc_litedramcore_bankmachine7_req_addr;
wire          soc_litedramcore_bankmachine7_req_lock;
reg           soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
wire          soc_litedramcore_bankmachine7_req_ready;
wire          soc_litedramcore_bankmachine7_req_valid;
reg           soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
wire          soc_litedramcore_bankmachine7_req_we;
reg    [13:0] soc_litedramcore_bankmachine7_row = 14'd0;
reg           soc_litedramcore_bankmachine7_row_close = 1'd0;
reg           soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
wire          soc_litedramcore_bankmachine7_row_hit;
reg           soc_litedramcore_bankmachine7_row_open = 1'd0;
reg           soc_litedramcore_bankmachine7_row_opened = 1'd0;
reg           soc_litedramcore_bankmachine7_sink_first = 1'd0;
reg           soc_litedramcore_bankmachine7_sink_last = 1'd0;
wire   [20:0] soc_litedramcore_bankmachine7_sink_payload_addr;
wire          soc_litedramcore_bankmachine7_sink_payload_we;
wire          soc_litedramcore_bankmachine7_sink_ready;
wire          soc_litedramcore_bankmachine7_sink_sink_first;
wire          soc_litedramcore_bankmachine7_sink_sink_last;
wire   [20:0] soc_litedramcore_bankmachine7_sink_sink_payload_addr;
wire          soc_litedramcore_bankmachine7_sink_sink_payload_we;
wire          soc_litedramcore_bankmachine7_sink_sink_ready;
wire          soc_litedramcore_bankmachine7_sink_sink_valid;
wire          soc_litedramcore_bankmachine7_sink_valid;
wire          soc_litedramcore_bankmachine7_source_first;
wire          soc_litedramcore_bankmachine7_source_last;
wire   [20:0] soc_litedramcore_bankmachine7_source_payload_addr;
wire          soc_litedramcore_bankmachine7_source_payload_we;
wire          soc_litedramcore_bankmachine7_source_ready;
wire          soc_litedramcore_bankmachine7_source_source_first;
wire          soc_litedramcore_bankmachine7_source_source_last;
wire   [20:0] soc_litedramcore_bankmachine7_source_source_payload_addr;
wire          soc_litedramcore_bankmachine7_source_source_payload_we;
wire          soc_litedramcore_bankmachine7_source_source_ready;
wire          soc_litedramcore_bankmachine7_source_source_valid;
wire          soc_litedramcore_bankmachine7_source_valid;
wire   [23:0] soc_litedramcore_bankmachine7_syncfifo7_din;
wire   [23:0] soc_litedramcore_bankmachine7_syncfifo7_dout;
wire          soc_litedramcore_bankmachine7_syncfifo7_re;
wire          soc_litedramcore_bankmachine7_syncfifo7_readable;
wire          soc_litedramcore_bankmachine7_syncfifo7_we;
wire          soc_litedramcore_bankmachine7_syncfifo7_writable;
reg     [2:0] soc_litedramcore_bankmachine7_trascon_count = 3'd0;
reg           soc_litedramcore_bankmachine7_trascon_ready = 1'd0;
wire          soc_litedramcore_bankmachine7_trascon_valid;
reg     [2:0] soc_litedramcore_bankmachine7_trccon_count = 3'd0;
reg           soc_litedramcore_bankmachine7_trccon_ready = 1'd0;
wire          soc_litedramcore_bankmachine7_trccon_valid;
reg     [2:0] soc_litedramcore_bankmachine7_twtpcon_count = 3'd0;
reg           soc_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
wire          soc_litedramcore_bankmachine7_twtpcon_valid;
reg     [3:0] soc_litedramcore_bankmachine7_wrport_adr = 4'd0;
wire   [23:0] soc_litedramcore_bankmachine7_wrport_dat_r;
wire   [23:0] soc_litedramcore_bankmachine7_wrport_dat_w;
wire          soc_litedramcore_bankmachine7_wrport_we;
wire          soc_litedramcore_cas_allowed;
wire          soc_litedramcore_choose_cmd_ce;
wire   [13:0] soc_litedramcore_choose_cmd_cmd_payload_a;
wire    [2:0] soc_litedramcore_choose_cmd_cmd_payload_ba;
reg           soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
wire          soc_litedramcore_choose_cmd_cmd_payload_is_cmd;
wire          soc_litedramcore_choose_cmd_cmd_payload_is_read;
wire          soc_litedramcore_choose_cmd_cmd_payload_is_write;
reg           soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
reg           soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
reg           soc_litedramcore_choose_cmd_cmd_ready = 1'd0;
wire          soc_litedramcore_choose_cmd_cmd_valid;
reg     [2:0] soc_litedramcore_choose_cmd_grant = 3'd0;
wire    [7:0] soc_litedramcore_choose_cmd_request;
reg     [7:0] soc_litedramcore_choose_cmd_valids = 8'd0;
reg           soc_litedramcore_choose_cmd_want_activates = 1'd0;
reg           soc_litedramcore_choose_cmd_want_cmds = 1'd0;
reg           soc_litedramcore_choose_cmd_want_reads = 1'd0;
reg           soc_litedramcore_choose_cmd_want_writes = 1'd0;
wire          soc_litedramcore_choose_req_ce;
wire   [13:0] soc_litedramcore_choose_req_cmd_payload_a;
wire    [2:0] soc_litedramcore_choose_req_cmd_payload_ba;
reg           soc_litedramcore_choose_req_cmd_payload_cas = 1'd0;
wire          soc_litedramcore_choose_req_cmd_payload_is_cmd;
wire          soc_litedramcore_choose_req_cmd_payload_is_read;
wire          soc_litedramcore_choose_req_cmd_payload_is_write;
reg           soc_litedramcore_choose_req_cmd_payload_ras = 1'd0;
reg           soc_litedramcore_choose_req_cmd_payload_we = 1'd0;
reg           soc_litedramcore_choose_req_cmd_ready = 1'd0;
wire          soc_litedramcore_choose_req_cmd_valid;
reg     [2:0] soc_litedramcore_choose_req_grant = 3'd0;
wire    [7:0] soc_litedramcore_choose_req_request;
reg     [7:0] soc_litedramcore_choose_req_valids = 8'd0;
reg           soc_litedramcore_choose_req_want_activates = 1'd0;
reg           soc_litedramcore_choose_req_want_cmds = 1'd0;
reg           soc_litedramcore_choose_req_want_reads = 1'd0;
reg           soc_litedramcore_choose_req_want_writes = 1'd0;
wire          soc_litedramcore_cke;
reg           soc_litedramcore_cmd_last = 1'd0;
reg    [13:0] soc_litedramcore_cmd_payload_a = 14'd0;
reg     [2:0] soc_litedramcore_cmd_payload_ba = 3'd0;
reg           soc_litedramcore_cmd_payload_cas = 1'd0;
reg           soc_litedramcore_cmd_payload_is_read = 1'd0;
reg           soc_litedramcore_cmd_payload_is_write = 1'd0;
reg           soc_litedramcore_cmd_payload_ras = 1'd0;
reg           soc_litedramcore_cmd_payload_we = 1'd0;
reg           soc_litedramcore_cmd_ready = 1'd0;
reg           soc_litedramcore_cmd_valid = 1'd0;
reg           soc_litedramcore_csr_dfi_p0_act_n = 1'd1;
wire   [13:0] soc_litedramcore_csr_dfi_p0_address;
wire    [2:0] soc_litedramcore_csr_dfi_p0_bank;
reg           soc_litedramcore_csr_dfi_p0_cas_n = 1'd1;
wire          soc_litedramcore_csr_dfi_p0_cke;
reg           soc_litedramcore_csr_dfi_p0_cs_n = 1'd1;
wire          soc_litedramcore_csr_dfi_p0_odt;
reg           soc_litedramcore_csr_dfi_p0_ras_n = 1'd1;
reg    [31:0] soc_litedramcore_csr_dfi_p0_rddata = 32'd0;
wire          soc_litedramcore_csr_dfi_p0_rddata_en;
reg           soc_litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
wire          soc_litedramcore_csr_dfi_p0_reset_n;
reg           soc_litedramcore_csr_dfi_p0_we_n = 1'd1;
wire   [31:0] soc_litedramcore_csr_dfi_p0_wrdata;
wire          soc_litedramcore_csr_dfi_p0_wrdata_en;
wire    [3:0] soc_litedramcore_csr_dfi_p0_wrdata_mask;
reg           soc_litedramcore_csr_dfi_p1_act_n = 1'd1;
wire   [13:0] soc_litedramcore_csr_dfi_p1_address;
wire    [2:0] soc_litedramcore_csr_dfi_p1_bank;
reg           soc_litedramcore_csr_dfi_p1_cas_n = 1'd1;
wire          soc_litedramcore_csr_dfi_p1_cke;
reg           soc_litedramcore_csr_dfi_p1_cs_n = 1'd1;
wire          soc_litedramcore_csr_dfi_p1_odt;
reg           soc_litedramcore_csr_dfi_p1_ras_n = 1'd1;
reg    [31:0] soc_litedramcore_csr_dfi_p1_rddata = 32'd0;
wire          soc_litedramcore_csr_dfi_p1_rddata_en;
reg           soc_litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
wire          soc_litedramcore_csr_dfi_p1_reset_n;
reg           soc_litedramcore_csr_dfi_p1_we_n = 1'd1;
wire   [31:0] soc_litedramcore_csr_dfi_p1_wrdata;
wire          soc_litedramcore_csr_dfi_p1_wrdata_en;
wire    [3:0] soc_litedramcore_csr_dfi_p1_wrdata_mask;
reg           soc_litedramcore_csr_dfi_p2_act_n = 1'd1;
wire   [13:0] soc_litedramcore_csr_dfi_p2_address;
wire    [2:0] soc_litedramcore_csr_dfi_p2_bank;
reg           soc_litedramcore_csr_dfi_p2_cas_n = 1'd1;
wire          soc_litedramcore_csr_dfi_p2_cke;
reg           soc_litedramcore_csr_dfi_p2_cs_n = 1'd1;
wire          soc_litedramcore_csr_dfi_p2_odt;
reg           soc_litedramcore_csr_dfi_p2_ras_n = 1'd1;
reg    [31:0] soc_litedramcore_csr_dfi_p2_rddata = 32'd0;
wire          soc_litedramcore_csr_dfi_p2_rddata_en;
reg           soc_litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
wire          soc_litedramcore_csr_dfi_p2_reset_n;
reg           soc_litedramcore_csr_dfi_p2_we_n = 1'd1;
wire   [31:0] soc_litedramcore_csr_dfi_p2_wrdata;
wire          soc_litedramcore_csr_dfi_p2_wrdata_en;
wire    [3:0] soc_litedramcore_csr_dfi_p2_wrdata_mask;
reg           soc_litedramcore_csr_dfi_p3_act_n = 1'd1;
wire   [13:0] soc_litedramcore_csr_dfi_p3_address;
wire    [2:0] soc_litedramcore_csr_dfi_p3_bank;
reg           soc_litedramcore_csr_dfi_p3_cas_n = 1'd1;
wire          soc_litedramcore_csr_dfi_p3_cke;
reg           soc_litedramcore_csr_dfi_p3_cs_n = 1'd1;
wire          soc_litedramcore_csr_dfi_p3_odt;
reg           soc_litedramcore_csr_dfi_p3_ras_n = 1'd1;
reg    [31:0] soc_litedramcore_csr_dfi_p3_rddata = 32'd0;
wire          soc_litedramcore_csr_dfi_p3_rddata_en;
reg           soc_litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
wire          soc_litedramcore_csr_dfi_p3_reset_n;
reg           soc_litedramcore_csr_dfi_p3_we_n = 1'd1;
wire   [31:0] soc_litedramcore_csr_dfi_p3_wrdata;
wire          soc_litedramcore_csr_dfi_p3_wrdata_en;
wire    [3:0] soc_litedramcore_csr_dfi_p3_wrdata_mask;
reg           soc_litedramcore_dfi_p0_act_n = 1'd1;
reg    [13:0] soc_litedramcore_dfi_p0_address = 14'd0;
reg     [2:0] soc_litedramcore_dfi_p0_bank = 3'd0;
reg           soc_litedramcore_dfi_p0_cas_n = 1'd1;
wire          soc_litedramcore_dfi_p0_cke;
reg           soc_litedramcore_dfi_p0_cs_n = 1'd1;
wire          soc_litedramcore_dfi_p0_odt;
reg           soc_litedramcore_dfi_p0_ras_n = 1'd1;
wire   [31:0] soc_litedramcore_dfi_p0_rddata;
reg           soc_litedramcore_dfi_p0_rddata_en = 1'd0;
wire          soc_litedramcore_dfi_p0_rddata_valid;
wire          soc_litedramcore_dfi_p0_reset_n;
reg           soc_litedramcore_dfi_p0_we_n = 1'd1;
wire   [31:0] soc_litedramcore_dfi_p0_wrdata;
reg           soc_litedramcore_dfi_p0_wrdata_en = 1'd0;
wire    [3:0] soc_litedramcore_dfi_p0_wrdata_mask;
reg           soc_litedramcore_dfi_p1_act_n = 1'd1;
reg    [13:0] soc_litedramcore_dfi_p1_address = 14'd0;
reg     [2:0] soc_litedramcore_dfi_p1_bank = 3'd0;
reg           soc_litedramcore_dfi_p1_cas_n = 1'd1;
wire          soc_litedramcore_dfi_p1_cke;
reg           soc_litedramcore_dfi_p1_cs_n = 1'd1;
wire          soc_litedramcore_dfi_p1_odt;
reg           soc_litedramcore_dfi_p1_ras_n = 1'd1;
wire   [31:0] soc_litedramcore_dfi_p1_rddata;
reg           soc_litedramcore_dfi_p1_rddata_en = 1'd0;
wire          soc_litedramcore_dfi_p1_rddata_valid;
wire          soc_litedramcore_dfi_p1_reset_n;
reg           soc_litedramcore_dfi_p1_we_n = 1'd1;
wire   [31:0] soc_litedramcore_dfi_p1_wrdata;
reg           soc_litedramcore_dfi_p1_wrdata_en = 1'd0;
wire    [3:0] soc_litedramcore_dfi_p1_wrdata_mask;
reg           soc_litedramcore_dfi_p2_act_n = 1'd1;
reg    [13:0] soc_litedramcore_dfi_p2_address = 14'd0;
reg     [2:0] soc_litedramcore_dfi_p2_bank = 3'd0;
reg           soc_litedramcore_dfi_p2_cas_n = 1'd1;
wire          soc_litedramcore_dfi_p2_cke;
reg           soc_litedramcore_dfi_p2_cs_n = 1'd1;
wire          soc_litedramcore_dfi_p2_odt;
reg           soc_litedramcore_dfi_p2_ras_n = 1'd1;
wire   [31:0] soc_litedramcore_dfi_p2_rddata;
reg           soc_litedramcore_dfi_p2_rddata_en = 1'd0;
wire          soc_litedramcore_dfi_p2_rddata_valid;
wire          soc_litedramcore_dfi_p2_reset_n;
reg           soc_litedramcore_dfi_p2_we_n = 1'd1;
wire   [31:0] soc_litedramcore_dfi_p2_wrdata;
reg           soc_litedramcore_dfi_p2_wrdata_en = 1'd0;
wire    [3:0] soc_litedramcore_dfi_p2_wrdata_mask;
reg           soc_litedramcore_dfi_p3_act_n = 1'd1;
reg    [13:0] soc_litedramcore_dfi_p3_address = 14'd0;
reg     [2:0] soc_litedramcore_dfi_p3_bank = 3'd0;
reg           soc_litedramcore_dfi_p3_cas_n = 1'd1;
wire          soc_litedramcore_dfi_p3_cke;
reg           soc_litedramcore_dfi_p3_cs_n = 1'd1;
wire          soc_litedramcore_dfi_p3_odt;
reg           soc_litedramcore_dfi_p3_ras_n = 1'd1;
wire   [31:0] soc_litedramcore_dfi_p3_rddata;
reg           soc_litedramcore_dfi_p3_rddata_en = 1'd0;
wire          soc_litedramcore_dfi_p3_rddata_valid;
wire          soc_litedramcore_dfi_p3_reset_n;
reg           soc_litedramcore_dfi_p3_we_n = 1'd1;
wire   [31:0] soc_litedramcore_dfi_p3_wrdata;
reg           soc_litedramcore_dfi_p3_wrdata_en = 1'd0;
wire    [3:0] soc_litedramcore_dfi_p3_wrdata_mask;
reg           soc_litedramcore_en0 = 1'd0;
reg           soc_litedramcore_en1 = 1'd0;
reg           soc_litedramcore_ext_dfi_p0_act_n = 1'd1;
reg    [13:0] soc_litedramcore_ext_dfi_p0_address = 14'd0;
reg     [2:0] soc_litedramcore_ext_dfi_p0_bank = 3'd0;
reg           soc_litedramcore_ext_dfi_p0_cas_n = 1'd1;
reg           soc_litedramcore_ext_dfi_p0_cke = 1'd0;
reg           soc_litedramcore_ext_dfi_p0_cs_n = 1'd1;
reg           soc_litedramcore_ext_dfi_p0_odt = 1'd0;
reg           soc_litedramcore_ext_dfi_p0_ras_n = 1'd1;
reg    [31:0] soc_litedramcore_ext_dfi_p0_rddata = 32'd0;
reg           soc_litedramcore_ext_dfi_p0_rddata_en = 1'd0;
reg           soc_litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
reg           soc_litedramcore_ext_dfi_p0_reset_n = 1'd0;
reg           soc_litedramcore_ext_dfi_p0_we_n = 1'd1;
reg    [31:0] soc_litedramcore_ext_dfi_p0_wrdata = 32'd0;
reg           soc_litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
reg     [3:0] soc_litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
reg           soc_litedramcore_ext_dfi_p1_act_n = 1'd1;
reg    [13:0] soc_litedramcore_ext_dfi_p1_address = 14'd0;
reg     [2:0] soc_litedramcore_ext_dfi_p1_bank = 3'd0;
reg           soc_litedramcore_ext_dfi_p1_cas_n = 1'd1;
reg           soc_litedramcore_ext_dfi_p1_cke = 1'd0;
reg           soc_litedramcore_ext_dfi_p1_cs_n = 1'd1;
reg           soc_litedramcore_ext_dfi_p1_odt = 1'd0;
reg           soc_litedramcore_ext_dfi_p1_ras_n = 1'd1;
reg    [31:0] soc_litedramcore_ext_dfi_p1_rddata = 32'd0;
reg           soc_litedramcore_ext_dfi_p1_rddata_en = 1'd0;
reg           soc_litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
reg           soc_litedramcore_ext_dfi_p1_reset_n = 1'd0;
reg           soc_litedramcore_ext_dfi_p1_we_n = 1'd1;
reg    [31:0] soc_litedramcore_ext_dfi_p1_wrdata = 32'd0;
reg           soc_litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
reg     [3:0] soc_litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
reg           soc_litedramcore_ext_dfi_p2_act_n = 1'd1;
reg    [13:0] soc_litedramcore_ext_dfi_p2_address = 14'd0;
reg     [2:0] soc_litedramcore_ext_dfi_p2_bank = 3'd0;
reg           soc_litedramcore_ext_dfi_p2_cas_n = 1'd1;
reg           soc_litedramcore_ext_dfi_p2_cke = 1'd0;
reg           soc_litedramcore_ext_dfi_p2_cs_n = 1'd1;
reg           soc_litedramcore_ext_dfi_p2_odt = 1'd0;
reg           soc_litedramcore_ext_dfi_p2_ras_n = 1'd1;
reg    [31:0] soc_litedramcore_ext_dfi_p2_rddata = 32'd0;
reg           soc_litedramcore_ext_dfi_p2_rddata_en = 1'd0;
reg           soc_litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
reg           soc_litedramcore_ext_dfi_p2_reset_n = 1'd0;
reg           soc_litedramcore_ext_dfi_p2_we_n = 1'd1;
reg    [31:0] soc_litedramcore_ext_dfi_p2_wrdata = 32'd0;
reg           soc_litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
reg     [3:0] soc_litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
reg           soc_litedramcore_ext_dfi_p3_act_n = 1'd1;
reg    [13:0] soc_litedramcore_ext_dfi_p3_address = 14'd0;
reg     [2:0] soc_litedramcore_ext_dfi_p3_bank = 3'd0;
reg           soc_litedramcore_ext_dfi_p3_cas_n = 1'd1;
reg           soc_litedramcore_ext_dfi_p3_cke = 1'd0;
reg           soc_litedramcore_ext_dfi_p3_cs_n = 1'd1;
reg           soc_litedramcore_ext_dfi_p3_odt = 1'd0;
reg           soc_litedramcore_ext_dfi_p3_ras_n = 1'd1;
reg    [31:0] soc_litedramcore_ext_dfi_p3_rddata = 32'd0;
reg           soc_litedramcore_ext_dfi_p3_rddata_en = 1'd0;
reg           soc_litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
reg           soc_litedramcore_ext_dfi_p3_reset_n = 1'd0;
reg           soc_litedramcore_ext_dfi_p3_we_n = 1'd1;
reg    [31:0] soc_litedramcore_ext_dfi_p3_wrdata = 32'd0;
reg           soc_litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
reg     [3:0] soc_litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
reg           soc_litedramcore_ext_dfi_sel = 1'd0;
wire          soc_litedramcore_go_to_refresh;
wire   [20:0] soc_litedramcore_interface_bank0_addr;
wire          soc_litedramcore_interface_bank0_lock;
wire          soc_litedramcore_interface_bank0_rdata_valid;
wire          soc_litedramcore_interface_bank0_ready;
wire          soc_litedramcore_interface_bank0_valid;
wire          soc_litedramcore_interface_bank0_wdata_ready;
wire          soc_litedramcore_interface_bank0_we;
wire   [20:0] soc_litedramcore_interface_bank1_addr;
wire          soc_litedramcore_interface_bank1_lock;
wire          soc_litedramcore_interface_bank1_rdata_valid;
wire          soc_litedramcore_interface_bank1_ready;
wire          soc_litedramcore_interface_bank1_valid;
wire          soc_litedramcore_interface_bank1_wdata_ready;
wire          soc_litedramcore_interface_bank1_we;
wire   [20:0] soc_litedramcore_interface_bank2_addr;
wire          soc_litedramcore_interface_bank2_lock;
wire          soc_litedramcore_interface_bank2_rdata_valid;
wire          soc_litedramcore_interface_bank2_ready;
wire          soc_litedramcore_interface_bank2_valid;
wire          soc_litedramcore_interface_bank2_wdata_ready;
wire          soc_litedramcore_interface_bank2_we;
wire   [20:0] soc_litedramcore_interface_bank3_addr;
wire          soc_litedramcore_interface_bank3_lock;
wire          soc_litedramcore_interface_bank3_rdata_valid;
wire          soc_litedramcore_interface_bank3_ready;
wire          soc_litedramcore_interface_bank3_valid;
wire          soc_litedramcore_interface_bank3_wdata_ready;
wire          soc_litedramcore_interface_bank3_we;
wire   [20:0] soc_litedramcore_interface_bank4_addr;
wire          soc_litedramcore_interface_bank4_lock;
wire          soc_litedramcore_interface_bank4_rdata_valid;
wire          soc_litedramcore_interface_bank4_ready;
wire          soc_litedramcore_interface_bank4_valid;
wire          soc_litedramcore_interface_bank4_wdata_ready;
wire          soc_litedramcore_interface_bank4_we;
wire   [20:0] soc_litedramcore_interface_bank5_addr;
wire          soc_litedramcore_interface_bank5_lock;
wire          soc_litedramcore_interface_bank5_rdata_valid;
wire          soc_litedramcore_interface_bank5_ready;
wire          soc_litedramcore_interface_bank5_valid;
wire          soc_litedramcore_interface_bank5_wdata_ready;
wire          soc_litedramcore_interface_bank5_we;
wire   [20:0] soc_litedramcore_interface_bank6_addr;
wire          soc_litedramcore_interface_bank6_lock;
wire          soc_litedramcore_interface_bank6_rdata_valid;
wire          soc_litedramcore_interface_bank6_ready;
wire          soc_litedramcore_interface_bank6_valid;
wire          soc_litedramcore_interface_bank6_wdata_ready;
wire          soc_litedramcore_interface_bank6_we;
wire   [20:0] soc_litedramcore_interface_bank7_addr;
wire          soc_litedramcore_interface_bank7_lock;
wire          soc_litedramcore_interface_bank7_rdata_valid;
wire          soc_litedramcore_interface_bank7_ready;
wire          soc_litedramcore_interface_bank7_valid;
wire          soc_litedramcore_interface_bank7_wdata_ready;
wire          soc_litedramcore_interface_bank7_we;
wire  [127:0] soc_litedramcore_interface_rdata;
reg   [127:0] soc_litedramcore_interface_wdata = 128'd0;
reg    [15:0] soc_litedramcore_interface_wdata_we = 16'd0;
reg           soc_litedramcore_master_p0_act_n = 1'd1;
reg    [13:0] soc_litedramcore_master_p0_address = 14'd0;
reg     [2:0] soc_litedramcore_master_p0_bank = 3'd0;
reg           soc_litedramcore_master_p0_cas_n = 1'd1;
reg           soc_litedramcore_master_p0_cke = 1'd0;
reg           soc_litedramcore_master_p0_cs_n = 1'd1;
reg           soc_litedramcore_master_p0_odt = 1'd0;
reg           soc_litedramcore_master_p0_ras_n = 1'd1;
wire   [31:0] soc_litedramcore_master_p0_rddata;
reg           soc_litedramcore_master_p0_rddata_en = 1'd0;
wire          soc_litedramcore_master_p0_rddata_valid;
reg           soc_litedramcore_master_p0_reset_n = 1'd0;
reg           soc_litedramcore_master_p0_we_n = 1'd1;
reg    [31:0] soc_litedramcore_master_p0_wrdata = 32'd0;
reg           soc_litedramcore_master_p0_wrdata_en = 1'd0;
reg     [3:0] soc_litedramcore_master_p0_wrdata_mask = 4'd0;
reg           soc_litedramcore_master_p1_act_n = 1'd1;
reg    [13:0] soc_litedramcore_master_p1_address = 14'd0;
reg     [2:0] soc_litedramcore_master_p1_bank = 3'd0;
reg           soc_litedramcore_master_p1_cas_n = 1'd1;
reg           soc_litedramcore_master_p1_cke = 1'd0;
reg           soc_litedramcore_master_p1_cs_n = 1'd1;
reg           soc_litedramcore_master_p1_odt = 1'd0;
reg           soc_litedramcore_master_p1_ras_n = 1'd1;
wire   [31:0] soc_litedramcore_master_p1_rddata;
reg           soc_litedramcore_master_p1_rddata_en = 1'd0;
wire          soc_litedramcore_master_p1_rddata_valid;
reg           soc_litedramcore_master_p1_reset_n = 1'd0;
reg           soc_litedramcore_master_p1_we_n = 1'd1;
reg    [31:0] soc_litedramcore_master_p1_wrdata = 32'd0;
reg           soc_litedramcore_master_p1_wrdata_en = 1'd0;
reg     [3:0] soc_litedramcore_master_p1_wrdata_mask = 4'd0;
reg           soc_litedramcore_master_p2_act_n = 1'd1;
reg    [13:0] soc_litedramcore_master_p2_address = 14'd0;
reg     [2:0] soc_litedramcore_master_p2_bank = 3'd0;
reg           soc_litedramcore_master_p2_cas_n = 1'd1;
reg           soc_litedramcore_master_p2_cke = 1'd0;
reg           soc_litedramcore_master_p2_cs_n = 1'd1;
reg           soc_litedramcore_master_p2_odt = 1'd0;
reg           soc_litedramcore_master_p2_ras_n = 1'd1;
wire   [31:0] soc_litedramcore_master_p2_rddata;
reg           soc_litedramcore_master_p2_rddata_en = 1'd0;
wire          soc_litedramcore_master_p2_rddata_valid;
reg           soc_litedramcore_master_p2_reset_n = 1'd0;
reg           soc_litedramcore_master_p2_we_n = 1'd1;
reg    [31:0] soc_litedramcore_master_p2_wrdata = 32'd0;
reg           soc_litedramcore_master_p2_wrdata_en = 1'd0;
reg     [3:0] soc_litedramcore_master_p2_wrdata_mask = 4'd0;
reg           soc_litedramcore_master_p3_act_n = 1'd1;
reg    [13:0] soc_litedramcore_master_p3_address = 14'd0;
reg     [2:0] soc_litedramcore_master_p3_bank = 3'd0;
reg           soc_litedramcore_master_p3_cas_n = 1'd1;
reg           soc_litedramcore_master_p3_cke = 1'd0;
reg           soc_litedramcore_master_p3_cs_n = 1'd1;
reg           soc_litedramcore_master_p3_odt = 1'd0;
reg           soc_litedramcore_master_p3_ras_n = 1'd1;
wire   [31:0] soc_litedramcore_master_p3_rddata;
reg           soc_litedramcore_master_p3_rddata_en = 1'd0;
wire          soc_litedramcore_master_p3_rddata_valid;
reg           soc_litedramcore_master_p3_reset_n = 1'd0;
reg           soc_litedramcore_master_p3_we_n = 1'd1;
reg    [31:0] soc_litedramcore_master_p3_wrdata = 32'd0;
reg           soc_litedramcore_master_p3_wrdata_en = 1'd0;
reg     [3:0] soc_litedramcore_master_p3_wrdata_mask = 4'd0;
wire          soc_litedramcore_max_time0;
wire          soc_litedramcore_max_time1;
reg    [13:0] soc_litedramcore_nop_a = 14'd0;
reg     [2:0] soc_litedramcore_nop_ba = 3'd0;
wire          soc_litedramcore_odt;
reg           soc_litedramcore_phaseinjector0_address_re = 1'd0;
reg    [13:0] soc_litedramcore_phaseinjector0_address_storage = 14'd0;
reg           soc_litedramcore_phaseinjector0_baddress_re = 1'd0;
reg     [2:0] soc_litedramcore_phaseinjector0_baddress_storage = 3'd0;
wire          soc_litedramcore_phaseinjector0_command_issue_r;
reg           soc_litedramcore_phaseinjector0_command_issue_re = 1'd0;
reg           soc_litedramcore_phaseinjector0_command_issue_w = 1'd0;
reg           soc_litedramcore_phaseinjector0_command_issue_we = 1'd0;
reg           soc_litedramcore_phaseinjector0_command_re = 1'd0;
reg     [7:0] soc_litedramcore_phaseinjector0_command_storage = 8'd0;
wire          soc_litedramcore_phaseinjector0_csrfield_cas;
wire          soc_litedramcore_phaseinjector0_csrfield_cs;
wire          soc_litedramcore_phaseinjector0_csrfield_cs_bottom;
wire          soc_litedramcore_phaseinjector0_csrfield_cs_top;
wire          soc_litedramcore_phaseinjector0_csrfield_ras;
wire          soc_litedramcore_phaseinjector0_csrfield_rden;
wire          soc_litedramcore_phaseinjector0_csrfield_we;
wire          soc_litedramcore_phaseinjector0_csrfield_wren;
reg           soc_litedramcore_phaseinjector0_rddata_re = 1'd0;
reg    [31:0] soc_litedramcore_phaseinjector0_rddata_status = 32'd0;
wire          soc_litedramcore_phaseinjector0_rddata_we;
reg           soc_litedramcore_phaseinjector0_wrdata_re = 1'd0;
reg    [31:0] soc_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
reg           soc_litedramcore_phaseinjector1_address_re = 1'd0;
reg    [13:0] soc_litedramcore_phaseinjector1_address_storage = 14'd0;
reg           soc_litedramcore_phaseinjector1_baddress_re = 1'd0;
reg     [2:0] soc_litedramcore_phaseinjector1_baddress_storage = 3'd0;
wire          soc_litedramcore_phaseinjector1_command_issue_r;
reg           soc_litedramcore_phaseinjector1_command_issue_re = 1'd0;
reg           soc_litedramcore_phaseinjector1_command_issue_w = 1'd0;
reg           soc_litedramcore_phaseinjector1_command_issue_we = 1'd0;
reg           soc_litedramcore_phaseinjector1_command_re = 1'd0;
reg     [7:0] soc_litedramcore_phaseinjector1_command_storage = 8'd0;
wire          soc_litedramcore_phaseinjector1_csrfield_cas;
wire          soc_litedramcore_phaseinjector1_csrfield_cs;
wire          soc_litedramcore_phaseinjector1_csrfield_cs_bottom;
wire          soc_litedramcore_phaseinjector1_csrfield_cs_top;
wire          soc_litedramcore_phaseinjector1_csrfield_ras;
wire          soc_litedramcore_phaseinjector1_csrfield_rden;
wire          soc_litedramcore_phaseinjector1_csrfield_we;
wire          soc_litedramcore_phaseinjector1_csrfield_wren;
reg           soc_litedramcore_phaseinjector1_rddata_re = 1'd0;
reg    [31:0] soc_litedramcore_phaseinjector1_rddata_status = 32'd0;
wire          soc_litedramcore_phaseinjector1_rddata_we;
reg           soc_litedramcore_phaseinjector1_wrdata_re = 1'd0;
reg    [31:0] soc_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
reg           soc_litedramcore_phaseinjector2_address_re = 1'd0;
reg    [13:0] soc_litedramcore_phaseinjector2_address_storage = 14'd0;
reg           soc_litedramcore_phaseinjector2_baddress_re = 1'd0;
reg     [2:0] soc_litedramcore_phaseinjector2_baddress_storage = 3'd0;
wire          soc_litedramcore_phaseinjector2_command_issue_r;
reg           soc_litedramcore_phaseinjector2_command_issue_re = 1'd0;
reg           soc_litedramcore_phaseinjector2_command_issue_w = 1'd0;
reg           soc_litedramcore_phaseinjector2_command_issue_we = 1'd0;
reg           soc_litedramcore_phaseinjector2_command_re = 1'd0;
reg     [7:0] soc_litedramcore_phaseinjector2_command_storage = 8'd0;
wire          soc_litedramcore_phaseinjector2_csrfield_cas;
wire          soc_litedramcore_phaseinjector2_csrfield_cs;
wire          soc_litedramcore_phaseinjector2_csrfield_cs_bottom;
wire          soc_litedramcore_phaseinjector2_csrfield_cs_top;
wire          soc_litedramcore_phaseinjector2_csrfield_ras;
wire          soc_litedramcore_phaseinjector2_csrfield_rden;
wire          soc_litedramcore_phaseinjector2_csrfield_we;
wire          soc_litedramcore_phaseinjector2_csrfield_wren;
reg           soc_litedramcore_phaseinjector2_rddata_re = 1'd0;
reg    [31:0] soc_litedramcore_phaseinjector2_rddata_status = 32'd0;
wire          soc_litedramcore_phaseinjector2_rddata_we;
reg           soc_litedramcore_phaseinjector2_wrdata_re = 1'd0;
reg    [31:0] soc_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
reg           soc_litedramcore_phaseinjector3_address_re = 1'd0;
reg    [13:0] soc_litedramcore_phaseinjector3_address_storage = 14'd0;
reg           soc_litedramcore_phaseinjector3_baddress_re = 1'd0;
reg     [2:0] soc_litedramcore_phaseinjector3_baddress_storage = 3'd0;
wire          soc_litedramcore_phaseinjector3_command_issue_r;
reg           soc_litedramcore_phaseinjector3_command_issue_re = 1'd0;
reg           soc_litedramcore_phaseinjector3_command_issue_w = 1'd0;
reg           soc_litedramcore_phaseinjector3_command_issue_we = 1'd0;
reg           soc_litedramcore_phaseinjector3_command_re = 1'd0;
reg     [7:0] soc_litedramcore_phaseinjector3_command_storage = 8'd0;
wire          soc_litedramcore_phaseinjector3_csrfield_cas;
wire          soc_litedramcore_phaseinjector3_csrfield_cs;
wire          soc_litedramcore_phaseinjector3_csrfield_cs_bottom;
wire          soc_litedramcore_phaseinjector3_csrfield_cs_top;
wire          soc_litedramcore_phaseinjector3_csrfield_ras;
wire          soc_litedramcore_phaseinjector3_csrfield_rden;
wire          soc_litedramcore_phaseinjector3_csrfield_we;
wire          soc_litedramcore_phaseinjector3_csrfield_wren;
reg           soc_litedramcore_phaseinjector3_rddata_re = 1'd0;
reg    [31:0] soc_litedramcore_phaseinjector3_rddata_status = 32'd0;
wire          soc_litedramcore_phaseinjector3_rddata_we;
reg           soc_litedramcore_phaseinjector3_wrdata_re = 1'd0;
reg    [31:0] soc_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
reg           soc_litedramcore_postponer_count = 1'd0;
wire          soc_litedramcore_postponer_req_i;
reg           soc_litedramcore_postponer_req_o = 1'd0;
wire          soc_litedramcore_ras_allowed;
reg           soc_litedramcore_re = 1'd0;
wire          soc_litedramcore_read_available;
wire          soc_litedramcore_reset_n;
wire          soc_litedramcore_sel;
reg           soc_litedramcore_sequencer_count = 1'd0;
wire          soc_litedramcore_sequencer_done0;
reg           soc_litedramcore_sequencer_done1 = 1'd0;
reg           soc_litedramcore_sequencer_start0 = 1'd0;
wire          soc_litedramcore_sequencer_start1;
reg     [5:0] soc_litedramcore_sequencer_trigger = 6'd0;
wire          soc_litedramcore_slave_p0_act_n;
wire   [13:0] soc_litedramcore_slave_p0_address;
wire    [2:0] soc_litedramcore_slave_p0_bank;
wire          soc_litedramcore_slave_p0_cas_n;
wire          soc_litedramcore_slave_p0_cke;
wire          soc_litedramcore_slave_p0_cs_n;
wire          soc_litedramcore_slave_p0_odt;
wire          soc_litedramcore_slave_p0_ras_n;
reg    [31:0] soc_litedramcore_slave_p0_rddata = 32'd0;
wire          soc_litedramcore_slave_p0_rddata_en;
reg           soc_litedramcore_slave_p0_rddata_valid = 1'd0;
wire          soc_litedramcore_slave_p0_reset_n;
wire          soc_litedramcore_slave_p0_we_n;
wire   [31:0] soc_litedramcore_slave_p0_wrdata;
wire          soc_litedramcore_slave_p0_wrdata_en;
wire    [3:0] soc_litedramcore_slave_p0_wrdata_mask;
wire          soc_litedramcore_slave_p1_act_n;
wire   [13:0] soc_litedramcore_slave_p1_address;
wire    [2:0] soc_litedramcore_slave_p1_bank;
wire          soc_litedramcore_slave_p1_cas_n;
wire          soc_litedramcore_slave_p1_cke;
wire          soc_litedramcore_slave_p1_cs_n;
wire          soc_litedramcore_slave_p1_odt;
wire          soc_litedramcore_slave_p1_ras_n;
reg    [31:0] soc_litedramcore_slave_p1_rddata = 32'd0;
wire          soc_litedramcore_slave_p1_rddata_en;
reg           soc_litedramcore_slave_p1_rddata_valid = 1'd0;
wire          soc_litedramcore_slave_p1_reset_n;
wire          soc_litedramcore_slave_p1_we_n;
wire   [31:0] soc_litedramcore_slave_p1_wrdata;
wire          soc_litedramcore_slave_p1_wrdata_en;
wire    [3:0] soc_litedramcore_slave_p1_wrdata_mask;
wire          soc_litedramcore_slave_p2_act_n;
wire   [13:0] soc_litedramcore_slave_p2_address;
wire    [2:0] soc_litedramcore_slave_p2_bank;
wire          soc_litedramcore_slave_p2_cas_n;
wire          soc_litedramcore_slave_p2_cke;
wire          soc_litedramcore_slave_p2_cs_n;
wire          soc_litedramcore_slave_p2_odt;
wire          soc_litedramcore_slave_p2_ras_n;
reg    [31:0] soc_litedramcore_slave_p2_rddata = 32'd0;
wire          soc_litedramcore_slave_p2_rddata_en;
reg           soc_litedramcore_slave_p2_rddata_valid = 1'd0;
wire          soc_litedramcore_slave_p2_reset_n;
wire          soc_litedramcore_slave_p2_we_n;
wire   [31:0] soc_litedramcore_slave_p2_wrdata;
wire          soc_litedramcore_slave_p2_wrdata_en;
wire    [3:0] soc_litedramcore_slave_p2_wrdata_mask;
wire          soc_litedramcore_slave_p3_act_n;
wire   [13:0] soc_litedramcore_slave_p3_address;
wire    [2:0] soc_litedramcore_slave_p3_bank;
wire          soc_litedramcore_slave_p3_cas_n;
wire          soc_litedramcore_slave_p3_cke;
wire          soc_litedramcore_slave_p3_cs_n;
wire          soc_litedramcore_slave_p3_odt;
wire          soc_litedramcore_slave_p3_ras_n;
reg    [31:0] soc_litedramcore_slave_p3_rddata = 32'd0;
wire          soc_litedramcore_slave_p3_rddata_en;
reg           soc_litedramcore_slave_p3_rddata_valid = 1'd0;
wire          soc_litedramcore_slave_p3_reset_n;
wire          soc_litedramcore_slave_p3_we_n;
wire   [31:0] soc_litedramcore_slave_p3_wrdata;
wire          soc_litedramcore_slave_p3_wrdata_en;
wire    [3:0] soc_litedramcore_slave_p3_wrdata_mask;
reg     [1:0] soc_litedramcore_steerer0 = 2'd0;
reg     [1:0] soc_litedramcore_steerer1 = 2'd0;
reg           soc_litedramcore_steerer10 = 1'd1;
reg           soc_litedramcore_steerer11 = 1'd1;
reg     [1:0] soc_litedramcore_steerer2 = 2'd0;
reg     [1:0] soc_litedramcore_steerer3 = 2'd0;
reg           soc_litedramcore_steerer4 = 1'd1;
reg           soc_litedramcore_steerer5 = 1'd1;
reg           soc_litedramcore_steerer6 = 1'd1;
reg           soc_litedramcore_steerer7 = 1'd1;
reg           soc_litedramcore_steerer8 = 1'd1;
reg           soc_litedramcore_steerer9 = 1'd1;
reg     [3:0] soc_litedramcore_storage = 4'd1;
reg           soc_litedramcore_tccdcon_count = 1'd0;
reg           soc_litedramcore_tccdcon_ready = 1'd0;
wire          soc_litedramcore_tccdcon_valid;
wire    [2:0] soc_litedramcore_tfawcon_count;
reg           soc_litedramcore_tfawcon_ready = 1'd1;
wire          soc_litedramcore_tfawcon_valid;
reg     [4:0] soc_litedramcore_tfawcon_window = 5'd0;
reg     [4:0] soc_litedramcore_time0 = 5'd0;
reg     [3:0] soc_litedramcore_time1 = 4'd0;
wire    [9:0] soc_litedramcore_timer_count0;
reg     [9:0] soc_litedramcore_timer_count1 = 10'd781;
wire          soc_litedramcore_timer_done0;
wire          soc_litedramcore_timer_done1;
wire          soc_litedramcore_timer_wait;
reg           soc_litedramcore_trrdcon_count = 1'd0;
reg           soc_litedramcore_trrdcon_ready = 1'd0;
wire          soc_litedramcore_trrdcon_valid;
reg     [2:0] soc_litedramcore_twtrcon_count = 3'd0;
reg           soc_litedramcore_twtrcon_ready = 1'd0;
wire          soc_litedramcore_twtrcon_valid;
wire          soc_litedramcore_wants_refresh;
wire          soc_litedramcore_wants_zqcs;
wire          soc_litedramcore_write_available;
reg           soc_litedramcore_zqcs_executer_done = 1'd0;
reg           soc_litedramcore_zqcs_executer_start = 1'd0;
reg     [4:0] soc_litedramcore_zqcs_executer_trigger = 5'd0;
wire   [26:0] soc_litedramcore_zqcs_timer_count0;
reg    [26:0] soc_litedramcore_zqcs_timer_count1 = 27'd99999999;
wire          soc_litedramcore_zqcs_timer_done0;
wire          soc_litedramcore_zqcs_timer_done1;
wire          soc_litedramcore_zqcs_timer_wait;
wire          soc_user_enable;
wire   [23:0] soc_user_port_cmd_payload_addr;
wire          soc_user_port_cmd_payload_we;
wire          soc_user_port_cmd_ready;
wire          soc_user_port_cmd_valid;
wire  [127:0] soc_user_port_rdata_payload_data;
wire          soc_user_port_rdata_ready;
wire          soc_user_port_rdata_valid;
wire  [127:0] soc_user_port_wdata_payload_data;
wire   [15:0] soc_user_port_wdata_payload_we;
wire          soc_user_port_wdata_ready;
wire          soc_user_port_wdata_valid;
wire          soc_wb_bus_ack;
wire   [29:0] soc_wb_bus_adr;
wire    [1:0] soc_wb_bus_bte;
wire    [2:0] soc_wb_bus_cti;
wire          soc_wb_bus_cyc;
wire   [31:0] soc_wb_bus_dat_r;
wire   [31:0] soc_wb_bus_dat_w;
wire          soc_wb_bus_err;
wire    [3:0] soc_wb_bus_sel;
wire          soc_wb_bus_stb;
wire          soc_wb_bus_we;
reg     [1:0] state = 2'd0;
wire          sys_clk;
wire          sys_rst;
reg           t_self0 = 1'd0;
reg           t_self1 = 1'd0;
reg           t_self2 = 1'd0;
reg           t_self3 = 1'd0;
reg           t_self4 = 1'd0;
reg           t_self5 = 1'd0;
wire          we;

//------------------------------------------------------------------------------
// Combinatorial Logic
//------------------------------------------------------------------------------

assign init_done = soc_init_done_storage;
assign init_error = soc_init_error_storage;
assign soc_wb_bus_adr = wb_ctrl_adr;
assign soc_wb_bus_dat_w = wb_ctrl_dat_w;
assign wb_ctrl_dat_r = soc_wb_bus_dat_r;
assign soc_wb_bus_sel = wb_ctrl_sel;
assign soc_wb_bus_cyc = wb_ctrl_cyc;
assign soc_wb_bus_stb = wb_ctrl_stb;
assign wb_ctrl_ack = soc_wb_bus_ack;
assign soc_wb_bus_we = wb_ctrl_we;
assign soc_wb_bus_cti = wb_ctrl_cti;
assign soc_wb_bus_bte = wb_ctrl_bte;
assign wb_ctrl_err = soc_wb_bus_err;
assign user_clk = sys_clk;
assign user_rst = sys_rst;
assign soc_user_enable = 1'd1;
assign soc_user_port_cmd_valid = (user_port_native_0_cmd_valid & soc_user_enable);
assign user_port_native_0_cmd_ready = (soc_user_port_cmd_ready & soc_user_enable);
assign soc_user_port_cmd_payload_we = user_port_native_0_cmd_we;
assign soc_user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
assign soc_user_port_wdata_valid = (user_port_native_0_wdata_valid & soc_user_enable);
assign user_port_native_0_wdata_ready = (soc_user_port_wdata_ready & soc_user_enable);
assign soc_user_port_wdata_payload_we = user_port_native_0_wdata_we;
assign soc_user_port_wdata_payload_data = user_port_native_0_wdata_data;
assign user_port_native_0_rdata_valid = (soc_user_port_rdata_valid & soc_user_enable);
assign soc_user_port_rdata_ready = (user_port_native_0_rdata_ready & soc_user_enable);
assign user_port_native_0_rdata_data = soc_user_port_rdata_payload_data;
assign interface0_adr = soc_wb_bus_adr;
assign interface0_dat_w = soc_wb_bus_dat_w;
assign soc_wb_bus_dat_r = interface0_dat_r;
assign interface0_sel = soc_wb_bus_sel;
assign interface0_cyc = soc_wb_bus_cyc;
assign interface0_stb = soc_wb_bus_stb;
assign soc_wb_bus_ack = interface0_ack;
assign interface0_we = soc_wb_bus_we;
assign interface0_cti = soc_wb_bus_cti;
assign interface0_bte = soc_wb_bus_bte;
assign soc_wb_bus_err = interface0_err;
assign sys_clk = clk;
assign por_clk = clk;
assign sys_rst = soc_int_rst;
always @(*) begin
    soc_ddrphy_activates0 <= 4'd0;
    soc_ddrphy_activates0[0] <= soc_ddrphy_dfiphasemodel0_activate;
    soc_ddrphy_activates0[1] <= soc_ddrphy_dfiphasemodel1_activate;
    soc_ddrphy_activates0[2] <= soc_ddrphy_dfiphasemodel2_activate;
    soc_ddrphy_activates0[3] <= soc_ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
    soc_ddrphy_bankmodel0_activate <= 1'd0;
    case (soc_ddrphy_activates0)
        1'd1: begin
            soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p0_bank == 1'd0);
        end
        2'd2: begin
            soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p1_bank == 1'd0);
        end
        3'd4: begin
            soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p2_bank == 1'd0);
        end
        4'd8: begin
            soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p3_bank == 1'd0);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_bankmodel0_activate_row <= 14'd0;
    case (soc_ddrphy_activates0)
        1'd1: begin
            soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p0_address;
        end
        2'd2: begin
            soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p1_address;
        end
        3'd4: begin
            soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p2_address;
        end
        4'd8: begin
            soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p3_address;
        end
    endcase
end
always @(*) begin
    soc_ddrphy_precharges0 <= 4'd0;
    soc_ddrphy_precharges0[0] <= soc_ddrphy_dfiphasemodel0_precharge;
    soc_ddrphy_precharges0[1] <= soc_ddrphy_dfiphasemodel1_precharge;
    soc_ddrphy_precharges0[2] <= soc_ddrphy_dfiphasemodel2_precharge;
    soc_ddrphy_precharges0[3] <= soc_ddrphy_dfiphasemodel3_precharge;
end
always @(*) begin
    soc_ddrphy_bankmodel0_precharge <= 1'd0;
    case (soc_ddrphy_precharges0)
        1'd1: begin
            soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p0_bank == 1'd0) | soc_ddrphy_dfi_p0_address[10]);
        end
        2'd2: begin
            soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p1_bank == 1'd0) | soc_ddrphy_dfi_p1_address[10]);
        end
        3'd4: begin
            soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p2_bank == 1'd0) | soc_ddrphy_dfi_p2_address[10]);
        end
        4'd8: begin
            soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p3_bank == 1'd0) | soc_ddrphy_dfi_p3_address[10]);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_writes0 <= 4'd0;
    soc_ddrphy_writes0[0] <= soc_ddrphy_dfiphasemodel0_write;
    soc_ddrphy_writes0[1] <= soc_ddrphy_dfiphasemodel1_write;
    soc_ddrphy_writes0[2] <= soc_ddrphy_dfiphasemodel2_write;
    soc_ddrphy_writes0[3] <= soc_ddrphy_dfiphasemodel3_write;
end
always @(*) begin
    soc_ddrphy_bank_write0 <= 1'd0;
    case (soc_ddrphy_writes0)
        1'd1: begin
            soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p0_bank == 1'd0);
        end
        2'd2: begin
            soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p1_bank == 1'd0);
        end
        3'd4: begin
            soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p2_bank == 1'd0);
        end
        4'd8: begin
            soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p3_bank == 1'd0);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_bank_write_col0 <= 10'd0;
    case (soc_ddrphy_writes0)
        1'd1: begin
            soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p0_address;
        end
        2'd2: begin
            soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p1_address;
        end
        3'd4: begin
            soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p2_address;
        end
        4'd8: begin
            soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p3_address;
        end
    endcase
end
assign soc_ddrphy_bankmodel0_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata};
assign soc_ddrphy_bankmodel0_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask};
assign soc_ddrphy_bankmodel0_write = soc_ddrphy_new_bank_write0;
assign soc_ddrphy_bankmodel0_write_col = soc_ddrphy_new_bank_write_col0;
always @(*) begin
    soc_ddrphy_reads0 <= 4'd0;
    soc_ddrphy_reads0[0] <= soc_ddrphy_dfiphasemodel0_read;
    soc_ddrphy_reads0[1] <= soc_ddrphy_dfiphasemodel1_read;
    soc_ddrphy_reads0[2] <= soc_ddrphy_dfiphasemodel2_read;
    soc_ddrphy_reads0[3] <= soc_ddrphy_dfiphasemodel3_read;
end
always @(*) begin
    soc_ddrphy_bankmodel0_read_col <= 10'd0;
    case (soc_ddrphy_reads0)
        1'd1: begin
            soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p0_address;
        end
        2'd2: begin
            soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p1_address;
        end
        3'd4: begin
            soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p2_address;
        end
        4'd8: begin
            soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p3_address;
        end
    endcase
end
always @(*) begin
    soc_ddrphy_bankmodel0_read <= 1'd0;
    case (soc_ddrphy_reads0)
        1'd1: begin
            soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p0_bank == 1'd0);
        end
        2'd2: begin
            soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p1_bank == 1'd0);
        end
        3'd4: begin
            soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p2_bank == 1'd0);
        end
        4'd8: begin
            soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p3_bank == 1'd0);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_activates1 <= 4'd0;
    soc_ddrphy_activates1[0] <= soc_ddrphy_dfiphasemodel0_activate;
    soc_ddrphy_activates1[1] <= soc_ddrphy_dfiphasemodel1_activate;
    soc_ddrphy_activates1[2] <= soc_ddrphy_dfiphasemodel2_activate;
    soc_ddrphy_activates1[3] <= soc_ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
    soc_ddrphy_bankmodel1_activate <= 1'd0;
    case (soc_ddrphy_activates1)
        1'd1: begin
            soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p0_bank == 1'd1);
        end
        2'd2: begin
            soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p1_bank == 1'd1);
        end
        3'd4: begin
            soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p2_bank == 1'd1);
        end
        4'd8: begin
            soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p3_bank == 1'd1);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_bankmodel1_activate_row <= 14'd0;
    case (soc_ddrphy_activates1)
        1'd1: begin
            soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p0_address;
        end
        2'd2: begin
            soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p1_address;
        end
        3'd4: begin
            soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p2_address;
        end
        4'd8: begin
            soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p3_address;
        end
    endcase
end
always @(*) begin
    soc_ddrphy_precharges1 <= 4'd0;
    soc_ddrphy_precharges1[0] <= soc_ddrphy_dfiphasemodel0_precharge;
    soc_ddrphy_precharges1[1] <= soc_ddrphy_dfiphasemodel1_precharge;
    soc_ddrphy_precharges1[2] <= soc_ddrphy_dfiphasemodel2_precharge;
    soc_ddrphy_precharges1[3] <= soc_ddrphy_dfiphasemodel3_precharge;
end
always @(*) begin
    soc_ddrphy_bankmodel1_precharge <= 1'd0;
    case (soc_ddrphy_precharges1)
        1'd1: begin
            soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p0_bank == 1'd1) | soc_ddrphy_dfi_p0_address[10]);
        end
        2'd2: begin
            soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p1_bank == 1'd1) | soc_ddrphy_dfi_p1_address[10]);
        end
        3'd4: begin
            soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p2_bank == 1'd1) | soc_ddrphy_dfi_p2_address[10]);
        end
        4'd8: begin
            soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p3_bank == 1'd1) | soc_ddrphy_dfi_p3_address[10]);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_writes1 <= 4'd0;
    soc_ddrphy_writes1[0] <= soc_ddrphy_dfiphasemodel0_write;
    soc_ddrphy_writes1[1] <= soc_ddrphy_dfiphasemodel1_write;
    soc_ddrphy_writes1[2] <= soc_ddrphy_dfiphasemodel2_write;
    soc_ddrphy_writes1[3] <= soc_ddrphy_dfiphasemodel3_write;
end
always @(*) begin
    soc_ddrphy_bank_write_col1 <= 10'd0;
    case (soc_ddrphy_writes1)
        1'd1: begin
            soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p0_address;
        end
        2'd2: begin
            soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p1_address;
        end
        3'd4: begin
            soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p2_address;
        end
        4'd8: begin
            soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p3_address;
        end
    endcase
end
always @(*) begin
    soc_ddrphy_bank_write1 <= 1'd0;
    case (soc_ddrphy_writes1)
        1'd1: begin
            soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p0_bank == 1'd1);
        end
        2'd2: begin
            soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p1_bank == 1'd1);
        end
        3'd4: begin
            soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p2_bank == 1'd1);
        end
        4'd8: begin
            soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p3_bank == 1'd1);
        end
    endcase
end
assign soc_ddrphy_bankmodel1_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata};
assign soc_ddrphy_bankmodel1_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask};
assign soc_ddrphy_bankmodel1_write = soc_ddrphy_new_bank_write1;
assign soc_ddrphy_bankmodel1_write_col = soc_ddrphy_new_bank_write_col1;
always @(*) begin
    soc_ddrphy_reads1 <= 4'd0;
    soc_ddrphy_reads1[0] <= soc_ddrphy_dfiphasemodel0_read;
    soc_ddrphy_reads1[1] <= soc_ddrphy_dfiphasemodel1_read;
    soc_ddrphy_reads1[2] <= soc_ddrphy_dfiphasemodel2_read;
    soc_ddrphy_reads1[3] <= soc_ddrphy_dfiphasemodel3_read;
end
always @(*) begin
    soc_ddrphy_bankmodel1_read <= 1'd0;
    case (soc_ddrphy_reads1)
        1'd1: begin
            soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p0_bank == 1'd1);
        end
        2'd2: begin
            soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p1_bank == 1'd1);
        end
        3'd4: begin
            soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p2_bank == 1'd1);
        end
        4'd8: begin
            soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p3_bank == 1'd1);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_bankmodel1_read_col <= 10'd0;
    case (soc_ddrphy_reads1)
        1'd1: begin
            soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p0_address;
        end
        2'd2: begin
            soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p1_address;
        end
        3'd4: begin
            soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p2_address;
        end
        4'd8: begin
            soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p3_address;
        end
    endcase
end
always @(*) begin
    soc_ddrphy_activates2 <= 4'd0;
    soc_ddrphy_activates2[0] <= soc_ddrphy_dfiphasemodel0_activate;
    soc_ddrphy_activates2[1] <= soc_ddrphy_dfiphasemodel1_activate;
    soc_ddrphy_activates2[2] <= soc_ddrphy_dfiphasemodel2_activate;
    soc_ddrphy_activates2[3] <= soc_ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
    soc_ddrphy_bankmodel2_activate_row <= 14'd0;
    case (soc_ddrphy_activates2)
        1'd1: begin
            soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p0_address;
        end
        2'd2: begin
            soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p1_address;
        end
        3'd4: begin
            soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p2_address;
        end
        4'd8: begin
            soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p3_address;
        end
    endcase
end
always @(*) begin
    soc_ddrphy_bankmodel2_activate <= 1'd0;
    case (soc_ddrphy_activates2)
        1'd1: begin
            soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p0_bank == 2'd2);
        end
        2'd2: begin
            soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p1_bank == 2'd2);
        end
        3'd4: begin
            soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p2_bank == 2'd2);
        end
        4'd8: begin
            soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p3_bank == 2'd2);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_precharges2 <= 4'd0;
    soc_ddrphy_precharges2[0] <= soc_ddrphy_dfiphasemodel0_precharge;
    soc_ddrphy_precharges2[1] <= soc_ddrphy_dfiphasemodel1_precharge;
    soc_ddrphy_precharges2[2] <= soc_ddrphy_dfiphasemodel2_precharge;
    soc_ddrphy_precharges2[3] <= soc_ddrphy_dfiphasemodel3_precharge;
end
always @(*) begin
    soc_ddrphy_bankmodel2_precharge <= 1'd0;
    case (soc_ddrphy_precharges2)
        1'd1: begin
            soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p0_bank == 2'd2) | soc_ddrphy_dfi_p0_address[10]);
        end
        2'd2: begin
            soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p1_bank == 2'd2) | soc_ddrphy_dfi_p1_address[10]);
        end
        3'd4: begin
            soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p2_bank == 2'd2) | soc_ddrphy_dfi_p2_address[10]);
        end
        4'd8: begin
            soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p3_bank == 2'd2) | soc_ddrphy_dfi_p3_address[10]);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_writes2 <= 4'd0;
    soc_ddrphy_writes2[0] <= soc_ddrphy_dfiphasemodel0_write;
    soc_ddrphy_writes2[1] <= soc_ddrphy_dfiphasemodel1_write;
    soc_ddrphy_writes2[2] <= soc_ddrphy_dfiphasemodel2_write;
    soc_ddrphy_writes2[3] <= soc_ddrphy_dfiphasemodel3_write;
end
always @(*) begin
    soc_ddrphy_bank_write2 <= 1'd0;
    case (soc_ddrphy_writes2)
        1'd1: begin
            soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p0_bank == 2'd2);
        end
        2'd2: begin
            soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p1_bank == 2'd2);
        end
        3'd4: begin
            soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p2_bank == 2'd2);
        end
        4'd8: begin
            soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p3_bank == 2'd2);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_bank_write_col2 <= 10'd0;
    case (soc_ddrphy_writes2)
        1'd1: begin
            soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p0_address;
        end
        2'd2: begin
            soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p1_address;
        end
        3'd4: begin
            soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p2_address;
        end
        4'd8: begin
            soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p3_address;
        end
    endcase
end
assign soc_ddrphy_bankmodel2_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata};
assign soc_ddrphy_bankmodel2_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask};
assign soc_ddrphy_bankmodel2_write = soc_ddrphy_new_bank_write2;
assign soc_ddrphy_bankmodel2_write_col = soc_ddrphy_new_bank_write_col2;
always @(*) begin
    soc_ddrphy_reads2 <= 4'd0;
    soc_ddrphy_reads2[0] <= soc_ddrphy_dfiphasemodel0_read;
    soc_ddrphy_reads2[1] <= soc_ddrphy_dfiphasemodel1_read;
    soc_ddrphy_reads2[2] <= soc_ddrphy_dfiphasemodel2_read;
    soc_ddrphy_reads2[3] <= soc_ddrphy_dfiphasemodel3_read;
end
always @(*) begin
    soc_ddrphy_bankmodel2_read <= 1'd0;
    case (soc_ddrphy_reads2)
        1'd1: begin
            soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p0_bank == 2'd2);
        end
        2'd2: begin
            soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p1_bank == 2'd2);
        end
        3'd4: begin
            soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p2_bank == 2'd2);
        end
        4'd8: begin
            soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p3_bank == 2'd2);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_bankmodel2_read_col <= 10'd0;
    case (soc_ddrphy_reads2)
        1'd1: begin
            soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p0_address;
        end
        2'd2: begin
            soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p1_address;
        end
        3'd4: begin
            soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p2_address;
        end
        4'd8: begin
            soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p3_address;
        end
    endcase
end
always @(*) begin
    soc_ddrphy_activates3 <= 4'd0;
    soc_ddrphy_activates3[0] <= soc_ddrphy_dfiphasemodel0_activate;
    soc_ddrphy_activates3[1] <= soc_ddrphy_dfiphasemodel1_activate;
    soc_ddrphy_activates3[2] <= soc_ddrphy_dfiphasemodel2_activate;
    soc_ddrphy_activates3[3] <= soc_ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
    soc_ddrphy_bankmodel3_activate <= 1'd0;
    case (soc_ddrphy_activates3)
        1'd1: begin
            soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p0_bank == 2'd3);
        end
        2'd2: begin
            soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p1_bank == 2'd3);
        end
        3'd4: begin
            soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p2_bank == 2'd3);
        end
        4'd8: begin
            soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p3_bank == 2'd3);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_bankmodel3_activate_row <= 14'd0;
    case (soc_ddrphy_activates3)
        1'd1: begin
            soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p0_address;
        end
        2'd2: begin
            soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p1_address;
        end
        3'd4: begin
            soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p2_address;
        end
        4'd8: begin
            soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p3_address;
        end
    endcase
end
always @(*) begin
    soc_ddrphy_precharges3 <= 4'd0;
    soc_ddrphy_precharges3[0] <= soc_ddrphy_dfiphasemodel0_precharge;
    soc_ddrphy_precharges3[1] <= soc_ddrphy_dfiphasemodel1_precharge;
    soc_ddrphy_precharges3[2] <= soc_ddrphy_dfiphasemodel2_precharge;
    soc_ddrphy_precharges3[3] <= soc_ddrphy_dfiphasemodel3_precharge;
end
always @(*) begin
    soc_ddrphy_bankmodel3_precharge <= 1'd0;
    case (soc_ddrphy_precharges3)
        1'd1: begin
            soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p0_bank == 2'd3) | soc_ddrphy_dfi_p0_address[10]);
        end
        2'd2: begin
            soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p1_bank == 2'd3) | soc_ddrphy_dfi_p1_address[10]);
        end
        3'd4: begin
            soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p2_bank == 2'd3) | soc_ddrphy_dfi_p2_address[10]);
        end
        4'd8: begin
            soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p3_bank == 2'd3) | soc_ddrphy_dfi_p3_address[10]);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_writes3 <= 4'd0;
    soc_ddrphy_writes3[0] <= soc_ddrphy_dfiphasemodel0_write;
    soc_ddrphy_writes3[1] <= soc_ddrphy_dfiphasemodel1_write;
    soc_ddrphy_writes3[2] <= soc_ddrphy_dfiphasemodel2_write;
    soc_ddrphy_writes3[3] <= soc_ddrphy_dfiphasemodel3_write;
end
always @(*) begin
    soc_ddrphy_bank_write3 <= 1'd0;
    case (soc_ddrphy_writes3)
        1'd1: begin
            soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p0_bank == 2'd3);
        end
        2'd2: begin
            soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p1_bank == 2'd3);
        end
        3'd4: begin
            soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p2_bank == 2'd3);
        end
        4'd8: begin
            soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p3_bank == 2'd3);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_bank_write_col3 <= 10'd0;
    case (soc_ddrphy_writes3)
        1'd1: begin
            soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p0_address;
        end
        2'd2: begin
            soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p1_address;
        end
        3'd4: begin
            soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p2_address;
        end
        4'd8: begin
            soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p3_address;
        end
    endcase
end
assign soc_ddrphy_bankmodel3_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata};
assign soc_ddrphy_bankmodel3_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask};
assign soc_ddrphy_bankmodel3_write = soc_ddrphy_new_bank_write3;
assign soc_ddrphy_bankmodel3_write_col = soc_ddrphy_new_bank_write_col3;
always @(*) begin
    soc_ddrphy_reads3 <= 4'd0;
    soc_ddrphy_reads3[0] <= soc_ddrphy_dfiphasemodel0_read;
    soc_ddrphy_reads3[1] <= soc_ddrphy_dfiphasemodel1_read;
    soc_ddrphy_reads3[2] <= soc_ddrphy_dfiphasemodel2_read;
    soc_ddrphy_reads3[3] <= soc_ddrphy_dfiphasemodel3_read;
end
always @(*) begin
    soc_ddrphy_bankmodel3_read <= 1'd0;
    case (soc_ddrphy_reads3)
        1'd1: begin
            soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p0_bank == 2'd3);
        end
        2'd2: begin
            soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p1_bank == 2'd3);
        end
        3'd4: begin
            soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p2_bank == 2'd3);
        end
        4'd8: begin
            soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p3_bank == 2'd3);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_bankmodel3_read_col <= 10'd0;
    case (soc_ddrphy_reads3)
        1'd1: begin
            soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p0_address;
        end
        2'd2: begin
            soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p1_address;
        end
        3'd4: begin
            soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p2_address;
        end
        4'd8: begin
            soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p3_address;
        end
    endcase
end
always @(*) begin
    soc_ddrphy_activates4 <= 4'd0;
    soc_ddrphy_activates4[0] <= soc_ddrphy_dfiphasemodel0_activate;
    soc_ddrphy_activates4[1] <= soc_ddrphy_dfiphasemodel1_activate;
    soc_ddrphy_activates4[2] <= soc_ddrphy_dfiphasemodel2_activate;
    soc_ddrphy_activates4[3] <= soc_ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
    soc_ddrphy_bankmodel4_activate <= 1'd0;
    case (soc_ddrphy_activates4)
        1'd1: begin
            soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p0_bank == 3'd4);
        end
        2'd2: begin
            soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p1_bank == 3'd4);
        end
        3'd4: begin
            soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p2_bank == 3'd4);
        end
        4'd8: begin
            soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p3_bank == 3'd4);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_bankmodel4_activate_row <= 14'd0;
    case (soc_ddrphy_activates4)
        1'd1: begin
            soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p0_address;
        end
        2'd2: begin
            soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p1_address;
        end
        3'd4: begin
            soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p2_address;
        end
        4'd8: begin
            soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p3_address;
        end
    endcase
end
always @(*) begin
    soc_ddrphy_precharges4 <= 4'd0;
    soc_ddrphy_precharges4[0] <= soc_ddrphy_dfiphasemodel0_precharge;
    soc_ddrphy_precharges4[1] <= soc_ddrphy_dfiphasemodel1_precharge;
    soc_ddrphy_precharges4[2] <= soc_ddrphy_dfiphasemodel2_precharge;
    soc_ddrphy_precharges4[3] <= soc_ddrphy_dfiphasemodel3_precharge;
end
always @(*) begin
    soc_ddrphy_bankmodel4_precharge <= 1'd0;
    case (soc_ddrphy_precharges4)
        1'd1: begin
            soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd4) | soc_ddrphy_dfi_p0_address[10]);
        end
        2'd2: begin
            soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd4) | soc_ddrphy_dfi_p1_address[10]);
        end
        3'd4: begin
            soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd4) | soc_ddrphy_dfi_p2_address[10]);
        end
        4'd8: begin
            soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd4) | soc_ddrphy_dfi_p3_address[10]);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_writes4 <= 4'd0;
    soc_ddrphy_writes4[0] <= soc_ddrphy_dfiphasemodel0_write;
    soc_ddrphy_writes4[1] <= soc_ddrphy_dfiphasemodel1_write;
    soc_ddrphy_writes4[2] <= soc_ddrphy_dfiphasemodel2_write;
    soc_ddrphy_writes4[3] <= soc_ddrphy_dfiphasemodel3_write;
end
always @(*) begin
    soc_ddrphy_bank_write4 <= 1'd0;
    case (soc_ddrphy_writes4)
        1'd1: begin
            soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p0_bank == 3'd4);
        end
        2'd2: begin
            soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p1_bank == 3'd4);
        end
        3'd4: begin
            soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p2_bank == 3'd4);
        end
        4'd8: begin
            soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p3_bank == 3'd4);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_bank_write_col4 <= 10'd0;
    case (soc_ddrphy_writes4)
        1'd1: begin
            soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p0_address;
        end
        2'd2: begin
            soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p1_address;
        end
        3'd4: begin
            soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p2_address;
        end
        4'd8: begin
            soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p3_address;
        end
    endcase
end
assign soc_ddrphy_bankmodel4_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata};
assign soc_ddrphy_bankmodel4_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask};
assign soc_ddrphy_bankmodel4_write = soc_ddrphy_new_bank_write4;
assign soc_ddrphy_bankmodel4_write_col = soc_ddrphy_new_bank_write_col4;
always @(*) begin
    soc_ddrphy_reads4 <= 4'd0;
    soc_ddrphy_reads4[0] <= soc_ddrphy_dfiphasemodel0_read;
    soc_ddrphy_reads4[1] <= soc_ddrphy_dfiphasemodel1_read;
    soc_ddrphy_reads4[2] <= soc_ddrphy_dfiphasemodel2_read;
    soc_ddrphy_reads4[3] <= soc_ddrphy_dfiphasemodel3_read;
end
always @(*) begin
    soc_ddrphy_bankmodel4_read <= 1'd0;
    case (soc_ddrphy_reads4)
        1'd1: begin
            soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p0_bank == 3'd4);
        end
        2'd2: begin
            soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p1_bank == 3'd4);
        end
        3'd4: begin
            soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p2_bank == 3'd4);
        end
        4'd8: begin
            soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p3_bank == 3'd4);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_bankmodel4_read_col <= 10'd0;
    case (soc_ddrphy_reads4)
        1'd1: begin
            soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p0_address;
        end
        2'd2: begin
            soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p1_address;
        end
        3'd4: begin
            soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p2_address;
        end
        4'd8: begin
            soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p3_address;
        end
    endcase
end
always @(*) begin
    soc_ddrphy_activates5 <= 4'd0;
    soc_ddrphy_activates5[0] <= soc_ddrphy_dfiphasemodel0_activate;
    soc_ddrphy_activates5[1] <= soc_ddrphy_dfiphasemodel1_activate;
    soc_ddrphy_activates5[2] <= soc_ddrphy_dfiphasemodel2_activate;
    soc_ddrphy_activates5[3] <= soc_ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
    soc_ddrphy_bankmodel5_activate <= 1'd0;
    case (soc_ddrphy_activates5)
        1'd1: begin
            soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p0_bank == 3'd5);
        end
        2'd2: begin
            soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p1_bank == 3'd5);
        end
        3'd4: begin
            soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p2_bank == 3'd5);
        end
        4'd8: begin
            soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p3_bank == 3'd5);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_bankmodel5_activate_row <= 14'd0;
    case (soc_ddrphy_activates5)
        1'd1: begin
            soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p0_address;
        end
        2'd2: begin
            soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p1_address;
        end
        3'd4: begin
            soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p2_address;
        end
        4'd8: begin
            soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p3_address;
        end
    endcase
end
always @(*) begin
    soc_ddrphy_precharges5 <= 4'd0;
    soc_ddrphy_precharges5[0] <= soc_ddrphy_dfiphasemodel0_precharge;
    soc_ddrphy_precharges5[1] <= soc_ddrphy_dfiphasemodel1_precharge;
    soc_ddrphy_precharges5[2] <= soc_ddrphy_dfiphasemodel2_precharge;
    soc_ddrphy_precharges5[3] <= soc_ddrphy_dfiphasemodel3_precharge;
end
always @(*) begin
    soc_ddrphy_bankmodel5_precharge <= 1'd0;
    case (soc_ddrphy_precharges5)
        1'd1: begin
            soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd5) | soc_ddrphy_dfi_p0_address[10]);
        end
        2'd2: begin
            soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd5) | soc_ddrphy_dfi_p1_address[10]);
        end
        3'd4: begin
            soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd5) | soc_ddrphy_dfi_p2_address[10]);
        end
        4'd8: begin
            soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd5) | soc_ddrphy_dfi_p3_address[10]);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_writes5 <= 4'd0;
    soc_ddrphy_writes5[0] <= soc_ddrphy_dfiphasemodel0_write;
    soc_ddrphy_writes5[1] <= soc_ddrphy_dfiphasemodel1_write;
    soc_ddrphy_writes5[2] <= soc_ddrphy_dfiphasemodel2_write;
    soc_ddrphy_writes5[3] <= soc_ddrphy_dfiphasemodel3_write;
end
always @(*) begin
    soc_ddrphy_bank_write_col5 <= 10'd0;
    case (soc_ddrphy_writes5)
        1'd1: begin
            soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p0_address;
        end
        2'd2: begin
            soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p1_address;
        end
        3'd4: begin
            soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p2_address;
        end
        4'd8: begin
            soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p3_address;
        end
    endcase
end
always @(*) begin
    soc_ddrphy_bank_write5 <= 1'd0;
    case (soc_ddrphy_writes5)
        1'd1: begin
            soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p0_bank == 3'd5);
        end
        2'd2: begin
            soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p1_bank == 3'd5);
        end
        3'd4: begin
            soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p2_bank == 3'd5);
        end
        4'd8: begin
            soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p3_bank == 3'd5);
        end
    endcase
end
assign soc_ddrphy_bankmodel5_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata};
assign soc_ddrphy_bankmodel5_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask};
assign soc_ddrphy_bankmodel5_write = soc_ddrphy_new_bank_write5;
assign soc_ddrphy_bankmodel5_write_col = soc_ddrphy_new_bank_write_col5;
always @(*) begin
    soc_ddrphy_reads5 <= 4'd0;
    soc_ddrphy_reads5[0] <= soc_ddrphy_dfiphasemodel0_read;
    soc_ddrphy_reads5[1] <= soc_ddrphy_dfiphasemodel1_read;
    soc_ddrphy_reads5[2] <= soc_ddrphy_dfiphasemodel2_read;
    soc_ddrphy_reads5[3] <= soc_ddrphy_dfiphasemodel3_read;
end
always @(*) begin
    soc_ddrphy_bankmodel5_read_col <= 10'd0;
    case (soc_ddrphy_reads5)
        1'd1: begin
            soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p0_address;
        end
        2'd2: begin
            soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p1_address;
        end
        3'd4: begin
            soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p2_address;
        end
        4'd8: begin
            soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p3_address;
        end
    endcase
end
always @(*) begin
    soc_ddrphy_bankmodel5_read <= 1'd0;
    case (soc_ddrphy_reads5)
        1'd1: begin
            soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p0_bank == 3'd5);
        end
        2'd2: begin
            soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p1_bank == 3'd5);
        end
        3'd4: begin
            soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p2_bank == 3'd5);
        end
        4'd8: begin
            soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p3_bank == 3'd5);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_activates6 <= 4'd0;
    soc_ddrphy_activates6[0] <= soc_ddrphy_dfiphasemodel0_activate;
    soc_ddrphy_activates6[1] <= soc_ddrphy_dfiphasemodel1_activate;
    soc_ddrphy_activates6[2] <= soc_ddrphy_dfiphasemodel2_activate;
    soc_ddrphy_activates6[3] <= soc_ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
    soc_ddrphy_bankmodel6_activate <= 1'd0;
    case (soc_ddrphy_activates6)
        1'd1: begin
            soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p0_bank == 3'd6);
        end
        2'd2: begin
            soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p1_bank == 3'd6);
        end
        3'd4: begin
            soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p2_bank == 3'd6);
        end
        4'd8: begin
            soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p3_bank == 3'd6);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_bankmodel6_activate_row <= 14'd0;
    case (soc_ddrphy_activates6)
        1'd1: begin
            soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p0_address;
        end
        2'd2: begin
            soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p1_address;
        end
        3'd4: begin
            soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p2_address;
        end
        4'd8: begin
            soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p3_address;
        end
    endcase
end
always @(*) begin
    soc_ddrphy_precharges6 <= 4'd0;
    soc_ddrphy_precharges6[0] <= soc_ddrphy_dfiphasemodel0_precharge;
    soc_ddrphy_precharges6[1] <= soc_ddrphy_dfiphasemodel1_precharge;
    soc_ddrphy_precharges6[2] <= soc_ddrphy_dfiphasemodel2_precharge;
    soc_ddrphy_precharges6[3] <= soc_ddrphy_dfiphasemodel3_precharge;
end
always @(*) begin
    soc_ddrphy_bankmodel6_precharge <= 1'd0;
    case (soc_ddrphy_precharges6)
        1'd1: begin
            soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd6) | soc_ddrphy_dfi_p0_address[10]);
        end
        2'd2: begin
            soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd6) | soc_ddrphy_dfi_p1_address[10]);
        end
        3'd4: begin
            soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd6) | soc_ddrphy_dfi_p2_address[10]);
        end
        4'd8: begin
            soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd6) | soc_ddrphy_dfi_p3_address[10]);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_writes6 <= 4'd0;
    soc_ddrphy_writes6[0] <= soc_ddrphy_dfiphasemodel0_write;
    soc_ddrphy_writes6[1] <= soc_ddrphy_dfiphasemodel1_write;
    soc_ddrphy_writes6[2] <= soc_ddrphy_dfiphasemodel2_write;
    soc_ddrphy_writes6[3] <= soc_ddrphy_dfiphasemodel3_write;
end
always @(*) begin
    soc_ddrphy_bank_write6 <= 1'd0;
    case (soc_ddrphy_writes6)
        1'd1: begin
            soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p0_bank == 3'd6);
        end
        2'd2: begin
            soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p1_bank == 3'd6);
        end
        3'd4: begin
            soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p2_bank == 3'd6);
        end
        4'd8: begin
            soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p3_bank == 3'd6);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_bank_write_col6 <= 10'd0;
    case (soc_ddrphy_writes6)
        1'd1: begin
            soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p0_address;
        end
        2'd2: begin
            soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p1_address;
        end
        3'd4: begin
            soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p2_address;
        end
        4'd8: begin
            soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p3_address;
        end
    endcase
end
assign soc_ddrphy_bankmodel6_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata};
assign soc_ddrphy_bankmodel6_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask};
assign soc_ddrphy_bankmodel6_write = soc_ddrphy_new_bank_write6;
assign soc_ddrphy_bankmodel6_write_col = soc_ddrphy_new_bank_write_col6;
always @(*) begin
    soc_ddrphy_reads6 <= 4'd0;
    soc_ddrphy_reads6[0] <= soc_ddrphy_dfiphasemodel0_read;
    soc_ddrphy_reads6[1] <= soc_ddrphy_dfiphasemodel1_read;
    soc_ddrphy_reads6[2] <= soc_ddrphy_dfiphasemodel2_read;
    soc_ddrphy_reads6[3] <= soc_ddrphy_dfiphasemodel3_read;
end
always @(*) begin
    soc_ddrphy_bankmodel6_read <= 1'd0;
    case (soc_ddrphy_reads6)
        1'd1: begin
            soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p0_bank == 3'd6);
        end
        2'd2: begin
            soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p1_bank == 3'd6);
        end
        3'd4: begin
            soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p2_bank == 3'd6);
        end
        4'd8: begin
            soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p3_bank == 3'd6);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_bankmodel6_read_col <= 10'd0;
    case (soc_ddrphy_reads6)
        1'd1: begin
            soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p0_address;
        end
        2'd2: begin
            soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p1_address;
        end
        3'd4: begin
            soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p2_address;
        end
        4'd8: begin
            soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p3_address;
        end
    endcase
end
always @(*) begin
    soc_ddrphy_activates7 <= 4'd0;
    soc_ddrphy_activates7[0] <= soc_ddrphy_dfiphasemodel0_activate;
    soc_ddrphy_activates7[1] <= soc_ddrphy_dfiphasemodel1_activate;
    soc_ddrphy_activates7[2] <= soc_ddrphy_dfiphasemodel2_activate;
    soc_ddrphy_activates7[3] <= soc_ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
    soc_ddrphy_bankmodel7_activate_row <= 14'd0;
    case (soc_ddrphy_activates7)
        1'd1: begin
            soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p0_address;
        end
        2'd2: begin
            soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p1_address;
        end
        3'd4: begin
            soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p2_address;
        end
        4'd8: begin
            soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p3_address;
        end
    endcase
end
always @(*) begin
    soc_ddrphy_bankmodel7_activate <= 1'd0;
    case (soc_ddrphy_activates7)
        1'd1: begin
            soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p0_bank == 3'd7);
        end
        2'd2: begin
            soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p1_bank == 3'd7);
        end
        3'd4: begin
            soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p2_bank == 3'd7);
        end
        4'd8: begin
            soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p3_bank == 3'd7);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_precharges7 <= 4'd0;
    soc_ddrphy_precharges7[0] <= soc_ddrphy_dfiphasemodel0_precharge;
    soc_ddrphy_precharges7[1] <= soc_ddrphy_dfiphasemodel1_precharge;
    soc_ddrphy_precharges7[2] <= soc_ddrphy_dfiphasemodel2_precharge;
    soc_ddrphy_precharges7[3] <= soc_ddrphy_dfiphasemodel3_precharge;
end
always @(*) begin
    soc_ddrphy_bankmodel7_precharge <= 1'd0;
    case (soc_ddrphy_precharges7)
        1'd1: begin
            soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd7) | soc_ddrphy_dfi_p0_address[10]);
        end
        2'd2: begin
            soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd7) | soc_ddrphy_dfi_p1_address[10]);
        end
        3'd4: begin
            soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd7) | soc_ddrphy_dfi_p2_address[10]);
        end
        4'd8: begin
            soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd7) | soc_ddrphy_dfi_p3_address[10]);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_writes7 <= 4'd0;
    soc_ddrphy_writes7[0] <= soc_ddrphy_dfiphasemodel0_write;
    soc_ddrphy_writes7[1] <= soc_ddrphy_dfiphasemodel1_write;
    soc_ddrphy_writes7[2] <= soc_ddrphy_dfiphasemodel2_write;
    soc_ddrphy_writes7[3] <= soc_ddrphy_dfiphasemodel3_write;
end
always @(*) begin
    soc_ddrphy_bank_write7 <= 1'd0;
    case (soc_ddrphy_writes7)
        1'd1: begin
            soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p0_bank == 3'd7);
        end
        2'd2: begin
            soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p1_bank == 3'd7);
        end
        3'd4: begin
            soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p2_bank == 3'd7);
        end
        4'd8: begin
            soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p3_bank == 3'd7);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_bank_write_col7 <= 10'd0;
    case (soc_ddrphy_writes7)
        1'd1: begin
            soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p0_address;
        end
        2'd2: begin
            soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p1_address;
        end
        3'd4: begin
            soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p2_address;
        end
        4'd8: begin
            soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p3_address;
        end
    endcase
end
assign soc_ddrphy_bankmodel7_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata};
assign soc_ddrphy_bankmodel7_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask};
assign soc_ddrphy_bankmodel7_write = soc_ddrphy_new_bank_write7;
assign soc_ddrphy_bankmodel7_write_col = soc_ddrphy_new_bank_write_col7;
always @(*) begin
    soc_ddrphy_reads7 <= 4'd0;
    soc_ddrphy_reads7[0] <= soc_ddrphy_dfiphasemodel0_read;
    soc_ddrphy_reads7[1] <= soc_ddrphy_dfiphasemodel1_read;
    soc_ddrphy_reads7[2] <= soc_ddrphy_dfiphasemodel2_read;
    soc_ddrphy_reads7[3] <= soc_ddrphy_dfiphasemodel3_read;
end
always @(*) begin
    soc_ddrphy_bankmodel7_read <= 1'd0;
    case (soc_ddrphy_reads7)
        1'd1: begin
            soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p0_bank == 3'd7);
        end
        2'd2: begin
            soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p1_bank == 3'd7);
        end
        3'd4: begin
            soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p2_bank == 3'd7);
        end
        4'd8: begin
            soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p3_bank == 3'd7);
        end
    endcase
end
always @(*) begin
    soc_ddrphy_bankmodel7_read_col <= 10'd0;
    case (soc_ddrphy_reads7)
        1'd1: begin
            soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p0_address;
        end
        2'd2: begin
            soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p1_address;
        end
        3'd4: begin
            soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p2_address;
        end
        4'd8: begin
            soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p3_address;
        end
    endcase
end
assign soc_ddrphy_banks_read = (((((((soc_ddrphy_bankmodel0_read | soc_ddrphy_bankmodel1_read) | soc_ddrphy_bankmodel2_read) | soc_ddrphy_bankmodel3_read) | soc_ddrphy_bankmodel4_read) | soc_ddrphy_bankmodel5_read) | soc_ddrphy_bankmodel6_read) | soc_ddrphy_bankmodel7_read);
assign soc_ddrphy_banks_read_data = (((((((soc_ddrphy_bankmodel0_read_data | soc_ddrphy_bankmodel1_read_data) | soc_ddrphy_bankmodel2_read_data) | soc_ddrphy_bankmodel3_read_data) | soc_ddrphy_bankmodel4_read_data) | soc_ddrphy_bankmodel5_read_data) | soc_ddrphy_bankmodel6_read_data) | soc_ddrphy_bankmodel7_read_data);
assign {soc_ddrphy_dfi_p3_rddata_valid, soc_ddrphy_dfi_p2_rddata_valid, soc_ddrphy_dfi_p1_rddata_valid, soc_ddrphy_dfi_p0_rddata_valid} = soc_ddrphy_new_banks_read7;
assign {soc_ddrphy_dfi_p3_rddata_valid, soc_ddrphy_dfi_p2_rddata_valid, soc_ddrphy_dfi_p1_rddata_valid, soc_ddrphy_dfi_p0_rddata_valid} = soc_ddrphy_new_banks_read7;
assign {soc_ddrphy_dfi_p3_rddata_valid, soc_ddrphy_dfi_p2_rddata_valid, soc_ddrphy_dfi_p1_rddata_valid, soc_ddrphy_dfi_p0_rddata_valid} = soc_ddrphy_new_banks_read7;
assign {soc_ddrphy_dfi_p3_rddata_valid, soc_ddrphy_dfi_p2_rddata_valid, soc_ddrphy_dfi_p1_rddata_valid, soc_ddrphy_dfi_p0_rddata_valid} = soc_ddrphy_new_banks_read7;
assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rddata, soc_ddrphy_dfi_p0_rddata} = soc_ddrphy_new_banks_read_data7;
assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rddata, soc_ddrphy_dfi_p0_rddata} = soc_ddrphy_new_banks_read_data7;
assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rddata, soc_ddrphy_dfi_p0_rddata} = soc_ddrphy_new_banks_read_data7;
assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rddata, soc_ddrphy_dfi_p0_rddata} = soc_ddrphy_new_banks_read_data7;
always @(*) begin
    soc_ddrphy_dfiphasemodel0_activate <= 1'd0;
    if ((((~soc_ddrphy_dfi_p0_cs_n) & (~soc_ddrphy_dfi_p0_ras_n)) & soc_ddrphy_dfi_p0_cas_n)) begin
        soc_ddrphy_dfiphasemodel0_activate <= soc_ddrphy_dfi_p0_we_n;
    end
end
always @(*) begin
    soc_ddrphy_dfiphasemodel0_precharge <= 1'd0;
    if ((((~soc_ddrphy_dfi_p0_cs_n) & (~soc_ddrphy_dfi_p0_ras_n)) & soc_ddrphy_dfi_p0_cas_n)) begin
        soc_ddrphy_dfiphasemodel0_precharge <= (~soc_ddrphy_dfi_p0_we_n);
    end
end
always @(*) begin
    soc_ddrphy_dfiphasemodel0_write <= 1'd0;
    if ((((~soc_ddrphy_dfi_p0_cs_n) & soc_ddrphy_dfi_p0_ras_n) & (~soc_ddrphy_dfi_p0_cas_n))) begin
        soc_ddrphy_dfiphasemodel0_write <= (~soc_ddrphy_dfi_p0_we_n);
    end
end
always @(*) begin
    soc_ddrphy_dfiphasemodel0_read <= 1'd0;
    if ((((~soc_ddrphy_dfi_p0_cs_n) & soc_ddrphy_dfi_p0_ras_n) & (~soc_ddrphy_dfi_p0_cas_n))) begin
        soc_ddrphy_dfiphasemodel0_read <= soc_ddrphy_dfi_p0_we_n;
    end
end
always @(*) begin
    soc_ddrphy_dfiphasemodel1_activate <= 1'd0;
    if ((((~soc_ddrphy_dfi_p1_cs_n) & (~soc_ddrphy_dfi_p1_ras_n)) & soc_ddrphy_dfi_p1_cas_n)) begin
        soc_ddrphy_dfiphasemodel1_activate <= soc_ddrphy_dfi_p1_we_n;
    end
end
always @(*) begin
    soc_ddrphy_dfiphasemodel1_precharge <= 1'd0;
    if ((((~soc_ddrphy_dfi_p1_cs_n) & (~soc_ddrphy_dfi_p1_ras_n)) & soc_ddrphy_dfi_p1_cas_n)) begin
        soc_ddrphy_dfiphasemodel1_precharge <= (~soc_ddrphy_dfi_p1_we_n);
    end
end
always @(*) begin
    soc_ddrphy_dfiphasemodel1_read <= 1'd0;
    if ((((~soc_ddrphy_dfi_p1_cs_n) & soc_ddrphy_dfi_p1_ras_n) & (~soc_ddrphy_dfi_p1_cas_n))) begin
        soc_ddrphy_dfiphasemodel1_read <= soc_ddrphy_dfi_p1_we_n;
    end
end
always @(*) begin
    soc_ddrphy_dfiphasemodel1_write <= 1'd0;
    if ((((~soc_ddrphy_dfi_p1_cs_n) & soc_ddrphy_dfi_p1_ras_n) & (~soc_ddrphy_dfi_p1_cas_n))) begin
        soc_ddrphy_dfiphasemodel1_write <= (~soc_ddrphy_dfi_p1_we_n);
    end
end
always @(*) begin
    soc_ddrphy_dfiphasemodel2_activate <= 1'd0;
    if ((((~soc_ddrphy_dfi_p2_cs_n) & (~soc_ddrphy_dfi_p2_ras_n)) & soc_ddrphy_dfi_p2_cas_n)) begin
        soc_ddrphy_dfiphasemodel2_activate <= soc_ddrphy_dfi_p2_we_n;
    end
end
always @(*) begin
    soc_ddrphy_dfiphasemodel2_precharge <= 1'd0;
    if ((((~soc_ddrphy_dfi_p2_cs_n) & (~soc_ddrphy_dfi_p2_ras_n)) & soc_ddrphy_dfi_p2_cas_n)) begin
        soc_ddrphy_dfiphasemodel2_precharge <= (~soc_ddrphy_dfi_p2_we_n);
    end
end
always @(*) begin
    soc_ddrphy_dfiphasemodel2_write <= 1'd0;
    if ((((~soc_ddrphy_dfi_p2_cs_n) & soc_ddrphy_dfi_p2_ras_n) & (~soc_ddrphy_dfi_p2_cas_n))) begin
        soc_ddrphy_dfiphasemodel2_write <= (~soc_ddrphy_dfi_p2_we_n);
    end
end
always @(*) begin
    soc_ddrphy_dfiphasemodel2_read <= 1'd0;
    if ((((~soc_ddrphy_dfi_p2_cs_n) & soc_ddrphy_dfi_p2_ras_n) & (~soc_ddrphy_dfi_p2_cas_n))) begin
        soc_ddrphy_dfiphasemodel2_read <= soc_ddrphy_dfi_p2_we_n;
    end
end
always @(*) begin
    soc_ddrphy_dfiphasemodel3_precharge <= 1'd0;
    if ((((~soc_ddrphy_dfi_p3_cs_n) & (~soc_ddrphy_dfi_p3_ras_n)) & soc_ddrphy_dfi_p3_cas_n)) begin
        soc_ddrphy_dfiphasemodel3_precharge <= (~soc_ddrphy_dfi_p3_we_n);
    end
end
always @(*) begin
    soc_ddrphy_dfiphasemodel3_activate <= 1'd0;
    if ((((~soc_ddrphy_dfi_p3_cs_n) & (~soc_ddrphy_dfi_p3_ras_n)) & soc_ddrphy_dfi_p3_cas_n)) begin
        soc_ddrphy_dfiphasemodel3_activate <= soc_ddrphy_dfi_p3_we_n;
    end
end
always @(*) begin
    soc_ddrphy_dfiphasemodel3_write <= 1'd0;
    if ((((~soc_ddrphy_dfi_p3_cs_n) & soc_ddrphy_dfi_p3_ras_n) & (~soc_ddrphy_dfi_p3_cas_n))) begin
        soc_ddrphy_dfiphasemodel3_write <= (~soc_ddrphy_dfi_p3_we_n);
    end
end
always @(*) begin
    soc_ddrphy_dfiphasemodel3_read <= 1'd0;
    if ((((~soc_ddrphy_dfi_p3_cs_n) & soc_ddrphy_dfi_p3_ras_n) & (~soc_ddrphy_dfi_p3_cas_n))) begin
        soc_ddrphy_dfiphasemodel3_read <= soc_ddrphy_dfi_p3_we_n;
    end
end
assign soc_ddrphy_bankmodel0_wraddr = slice_proxy0[24:3];
assign soc_ddrphy_bankmodel0_rdaddr = slice_proxy1[24:3];
always @(*) begin
    soc_ddrphy_bankmodel0_read_data <= 128'd0;
    if (soc_ddrphy_bankmodel0_active) begin
        if (soc_ddrphy_bankmodel0_read) begin
            soc_ddrphy_bankmodel0_read_data <= soc_ddrphy_bankmodel0_read_port_dat_r;
        end
    end
end
always @(*) begin
    soc_ddrphy_bankmodel0_write_port_adr <= 21'd0;
    if (soc_ddrphy_bankmodel0_active) begin
        soc_ddrphy_bankmodel0_write_port_adr <= soc_ddrphy_bankmodel0_wraddr;
    end
end
always @(*) begin
    soc_ddrphy_bankmodel0_write_port_we <= 16'd0;
    if (soc_ddrphy_bankmodel0_active) begin
        if (4'd8) begin
            soc_ddrphy_bankmodel0_write_port_we <= ({16{soc_ddrphy_bankmodel0_write}} & (~soc_ddrphy_bankmodel0_write_mask));
        end else begin
            soc_ddrphy_bankmodel0_write_port_we <= soc_ddrphy_bankmodel0_write;
        end
    end
end
always @(*) begin
    soc_ddrphy_bankmodel0_write_port_dat_w <= 128'd0;
    if (soc_ddrphy_bankmodel0_active) begin
        soc_ddrphy_bankmodel0_write_port_dat_w <= soc_ddrphy_bankmodel0_write_data;
    end
end
always @(*) begin
    soc_ddrphy_bankmodel0_read_port_adr <= 21'd0;
    if (soc_ddrphy_bankmodel0_active) begin
        if (soc_ddrphy_bankmodel0_read) begin
            soc_ddrphy_bankmodel0_read_port_adr <= soc_ddrphy_bankmodel0_rdaddr;
        end
    end
end
assign soc_ddrphy_bankmodel1_wraddr = slice_proxy2[24:3];
assign soc_ddrphy_bankmodel1_rdaddr = slice_proxy3[24:3];
always @(*) begin
    soc_ddrphy_bankmodel1_write_port_adr <= 21'd0;
    if (soc_ddrphy_bankmodel1_active) begin
        soc_ddrphy_bankmodel1_write_port_adr <= soc_ddrphy_bankmodel1_wraddr;
    end
end
always @(*) begin
    soc_ddrphy_bankmodel1_write_port_we <= 16'd0;
    if (soc_ddrphy_bankmodel1_active) begin
        if (4'd8) begin
            soc_ddrphy_bankmodel1_write_port_we <= ({16{soc_ddrphy_bankmodel1_write}} & (~soc_ddrphy_bankmodel1_write_mask));
        end else begin
            soc_ddrphy_bankmodel1_write_port_we <= soc_ddrphy_bankmodel1_write;
        end
    end
end
always @(*) begin
    soc_ddrphy_bankmodel1_write_port_dat_w <= 128'd0;
    if (soc_ddrphy_bankmodel1_active) begin
        soc_ddrphy_bankmodel1_write_port_dat_w <= soc_ddrphy_bankmodel1_write_data;
    end
end
always @(*) begin
    soc_ddrphy_bankmodel1_read_port_adr <= 21'd0;
    if (soc_ddrphy_bankmodel1_active) begin
        if (soc_ddrphy_bankmodel1_read) begin
            soc_ddrphy_bankmodel1_read_port_adr <= soc_ddrphy_bankmodel1_rdaddr;
        end
    end
end
always @(*) begin
    soc_ddrphy_bankmodel1_read_data <= 128'd0;
    if (soc_ddrphy_bankmodel1_active) begin
        if (soc_ddrphy_bankmodel1_read) begin
            soc_ddrphy_bankmodel1_read_data <= soc_ddrphy_bankmodel1_read_port_dat_r;
        end
    end
end
assign soc_ddrphy_bankmodel2_wraddr = slice_proxy4[24:3];
assign soc_ddrphy_bankmodel2_rdaddr = slice_proxy5[24:3];
always @(*) begin
    soc_ddrphy_bankmodel2_write_port_adr <= 21'd0;
    if (soc_ddrphy_bankmodel2_active) begin
        soc_ddrphy_bankmodel2_write_port_adr <= soc_ddrphy_bankmodel2_wraddr;
    end
end
always @(*) begin
    soc_ddrphy_bankmodel2_write_port_we <= 16'd0;
    if (soc_ddrphy_bankmodel2_active) begin
        if (4'd8) begin
            soc_ddrphy_bankmodel2_write_port_we <= ({16{soc_ddrphy_bankmodel2_write}} & (~soc_ddrphy_bankmodel2_write_mask));
        end else begin
            soc_ddrphy_bankmodel2_write_port_we <= soc_ddrphy_bankmodel2_write;
        end
    end
end
always @(*) begin
    soc_ddrphy_bankmodel2_write_port_dat_w <= 128'd0;
    if (soc_ddrphy_bankmodel2_active) begin
        soc_ddrphy_bankmodel2_write_port_dat_w <= soc_ddrphy_bankmodel2_write_data;
    end
end
always @(*) begin
    soc_ddrphy_bankmodel2_read_port_adr <= 21'd0;
    if (soc_ddrphy_bankmodel2_active) begin
        if (soc_ddrphy_bankmodel2_read) begin
            soc_ddrphy_bankmodel2_read_port_adr <= soc_ddrphy_bankmodel2_rdaddr;
        end
    end
end
always @(*) begin
    soc_ddrphy_bankmodel2_read_data <= 128'd0;
    if (soc_ddrphy_bankmodel2_active) begin
        if (soc_ddrphy_bankmodel2_read) begin
            soc_ddrphy_bankmodel2_read_data <= soc_ddrphy_bankmodel2_read_port_dat_r;
        end
    end
end
assign soc_ddrphy_bankmodel3_wraddr = slice_proxy6[24:3];
assign soc_ddrphy_bankmodel3_rdaddr = slice_proxy7[24:3];
always @(*) begin
    soc_ddrphy_bankmodel3_write_port_we <= 16'd0;
    if (soc_ddrphy_bankmodel3_active) begin
        if (4'd8) begin
            soc_ddrphy_bankmodel3_write_port_we <= ({16{soc_ddrphy_bankmodel3_write}} & (~soc_ddrphy_bankmodel3_write_mask));
        end else begin
            soc_ddrphy_bankmodel3_write_port_we <= soc_ddrphy_bankmodel3_write;
        end
    end
end
always @(*) begin
    soc_ddrphy_bankmodel3_write_port_dat_w <= 128'd0;
    if (soc_ddrphy_bankmodel3_active) begin
        soc_ddrphy_bankmodel3_write_port_dat_w <= soc_ddrphy_bankmodel3_write_data;
    end
end
always @(*) begin
    soc_ddrphy_bankmodel3_read_port_adr <= 21'd0;
    if (soc_ddrphy_bankmodel3_active) begin
        if (soc_ddrphy_bankmodel3_read) begin
            soc_ddrphy_bankmodel3_read_port_adr <= soc_ddrphy_bankmodel3_rdaddr;
        end
    end
end
always @(*) begin
    soc_ddrphy_bankmodel3_read_data <= 128'd0;
    if (soc_ddrphy_bankmodel3_active) begin
        if (soc_ddrphy_bankmodel3_read) begin
            soc_ddrphy_bankmodel3_read_data <= soc_ddrphy_bankmodel3_read_port_dat_r;
        end
    end
end
always @(*) begin
    soc_ddrphy_bankmodel3_write_port_adr <= 21'd0;
    if (soc_ddrphy_bankmodel3_active) begin
        soc_ddrphy_bankmodel3_write_port_adr <= soc_ddrphy_bankmodel3_wraddr;
    end
end
assign soc_ddrphy_bankmodel4_wraddr = slice_proxy8[24:3];
assign soc_ddrphy_bankmodel4_rdaddr = slice_proxy9[24:3];
always @(*) begin
    soc_ddrphy_bankmodel4_read_port_adr <= 21'd0;
    if (soc_ddrphy_bankmodel4_active) begin
        if (soc_ddrphy_bankmodel4_read) begin
            soc_ddrphy_bankmodel4_read_port_adr <= soc_ddrphy_bankmodel4_rdaddr;
        end
    end
end
always @(*) begin
    soc_ddrphy_bankmodel4_read_data <= 128'd0;
    if (soc_ddrphy_bankmodel4_active) begin
        if (soc_ddrphy_bankmodel4_read) begin
            soc_ddrphy_bankmodel4_read_data <= soc_ddrphy_bankmodel4_read_port_dat_r;
        end
    end
end
always @(*) begin
    soc_ddrphy_bankmodel4_write_port_adr <= 21'd0;
    if (soc_ddrphy_bankmodel4_active) begin
        soc_ddrphy_bankmodel4_write_port_adr <= soc_ddrphy_bankmodel4_wraddr;
    end
end
always @(*) begin
    soc_ddrphy_bankmodel4_write_port_we <= 16'd0;
    if (soc_ddrphy_bankmodel4_active) begin
        if (4'd8) begin
            soc_ddrphy_bankmodel4_write_port_we <= ({16{soc_ddrphy_bankmodel4_write}} & (~soc_ddrphy_bankmodel4_write_mask));
        end else begin
            soc_ddrphy_bankmodel4_write_port_we <= soc_ddrphy_bankmodel4_write;
        end
    end
end
always @(*) begin
    soc_ddrphy_bankmodel4_write_port_dat_w <= 128'd0;
    if (soc_ddrphy_bankmodel4_active) begin
        soc_ddrphy_bankmodel4_write_port_dat_w <= soc_ddrphy_bankmodel4_write_data;
    end
end
assign soc_ddrphy_bankmodel5_wraddr = slice_proxy10[24:3];
assign soc_ddrphy_bankmodel5_rdaddr = slice_proxy11[24:3];
always @(*) begin
    soc_ddrphy_bankmodel5_read_data <= 128'd0;
    if (soc_ddrphy_bankmodel5_active) begin
        if (soc_ddrphy_bankmodel5_read) begin
            soc_ddrphy_bankmodel5_read_data <= soc_ddrphy_bankmodel5_read_port_dat_r;
        end
    end
end
always @(*) begin
    soc_ddrphy_bankmodel5_write_port_adr <= 21'd0;
    if (soc_ddrphy_bankmodel5_active) begin
        soc_ddrphy_bankmodel5_write_port_adr <= soc_ddrphy_bankmodel5_wraddr;
    end
end
always @(*) begin
    soc_ddrphy_bankmodel5_write_port_we <= 16'd0;
    if (soc_ddrphy_bankmodel5_active) begin
        if (4'd8) begin
            soc_ddrphy_bankmodel5_write_port_we <= ({16{soc_ddrphy_bankmodel5_write}} & (~soc_ddrphy_bankmodel5_write_mask));
        end else begin
            soc_ddrphy_bankmodel5_write_port_we <= soc_ddrphy_bankmodel5_write;
        end
    end
end
always @(*) begin
    soc_ddrphy_bankmodel5_write_port_dat_w <= 128'd0;
    if (soc_ddrphy_bankmodel5_active) begin
        soc_ddrphy_bankmodel5_write_port_dat_w <= soc_ddrphy_bankmodel5_write_data;
    end
end
always @(*) begin
    soc_ddrphy_bankmodel5_read_port_adr <= 21'd0;
    if (soc_ddrphy_bankmodel5_active) begin
        if (soc_ddrphy_bankmodel5_read) begin
            soc_ddrphy_bankmodel5_read_port_adr <= soc_ddrphy_bankmodel5_rdaddr;
        end
    end
end
assign soc_ddrphy_bankmodel6_wraddr = slice_proxy12[24:3];
assign soc_ddrphy_bankmodel6_rdaddr = slice_proxy13[24:3];
always @(*) begin
    soc_ddrphy_bankmodel6_read_data <= 128'd0;
    if (soc_ddrphy_bankmodel6_active) begin
        if (soc_ddrphy_bankmodel6_read) begin
            soc_ddrphy_bankmodel6_read_data <= soc_ddrphy_bankmodel6_read_port_dat_r;
        end
    end
end
always @(*) begin
    soc_ddrphy_bankmodel6_write_port_adr <= 21'd0;
    if (soc_ddrphy_bankmodel6_active) begin
        soc_ddrphy_bankmodel6_write_port_adr <= soc_ddrphy_bankmodel6_wraddr;
    end
end
always @(*) begin
    soc_ddrphy_bankmodel6_write_port_we <= 16'd0;
    if (soc_ddrphy_bankmodel6_active) begin
        if (4'd8) begin
            soc_ddrphy_bankmodel6_write_port_we <= ({16{soc_ddrphy_bankmodel6_write}} & (~soc_ddrphy_bankmodel6_write_mask));
        end else begin
            soc_ddrphy_bankmodel6_write_port_we <= soc_ddrphy_bankmodel6_write;
        end
    end
end
always @(*) begin
    soc_ddrphy_bankmodel6_write_port_dat_w <= 128'd0;
    if (soc_ddrphy_bankmodel6_active) begin
        soc_ddrphy_bankmodel6_write_port_dat_w <= soc_ddrphy_bankmodel6_write_data;
    end
end
always @(*) begin
    soc_ddrphy_bankmodel6_read_port_adr <= 21'd0;
    if (soc_ddrphy_bankmodel6_active) begin
        if (soc_ddrphy_bankmodel6_read) begin
            soc_ddrphy_bankmodel6_read_port_adr <= soc_ddrphy_bankmodel6_rdaddr;
        end
    end
end
assign soc_ddrphy_bankmodel7_wraddr = slice_proxy14[24:3];
assign soc_ddrphy_bankmodel7_rdaddr = slice_proxy15[24:3];
always @(*) begin
    soc_ddrphy_bankmodel7_read_data <= 128'd0;
    if (soc_ddrphy_bankmodel7_active) begin
        if (soc_ddrphy_bankmodel7_read) begin
            soc_ddrphy_bankmodel7_read_data <= soc_ddrphy_bankmodel7_read_port_dat_r;
        end
    end
end
always @(*) begin
    soc_ddrphy_bankmodel7_write_port_adr <= 21'd0;
    if (soc_ddrphy_bankmodel7_active) begin
        soc_ddrphy_bankmodel7_write_port_adr <= soc_ddrphy_bankmodel7_wraddr;
    end
end
always @(*) begin
    soc_ddrphy_bankmodel7_write_port_we <= 16'd0;
    if (soc_ddrphy_bankmodel7_active) begin
        if (4'd8) begin
            soc_ddrphy_bankmodel7_write_port_we <= ({16{soc_ddrphy_bankmodel7_write}} & (~soc_ddrphy_bankmodel7_write_mask));
        end else begin
            soc_ddrphy_bankmodel7_write_port_we <= soc_ddrphy_bankmodel7_write;
        end
    end
end
always @(*) begin
    soc_ddrphy_bankmodel7_write_port_dat_w <= 128'd0;
    if (soc_ddrphy_bankmodel7_active) begin
        soc_ddrphy_bankmodel7_write_port_dat_w <= soc_ddrphy_bankmodel7_write_data;
    end
end
always @(*) begin
    soc_ddrphy_bankmodel7_read_port_adr <= 21'd0;
    if (soc_ddrphy_bankmodel7_active) begin
        if (soc_ddrphy_bankmodel7_read) begin
            soc_ddrphy_bankmodel7_read_port_adr <= soc_ddrphy_bankmodel7_rdaddr;
        end
    end
end
assign soc_ddrphy_dfi_p0_address = soc_litedramcore_master_p0_address;
assign soc_ddrphy_dfi_p0_bank = soc_litedramcore_master_p0_bank;
assign soc_ddrphy_dfi_p0_cas_n = soc_litedramcore_master_p0_cas_n;
assign soc_ddrphy_dfi_p0_cs_n = soc_litedramcore_master_p0_cs_n;
assign soc_ddrphy_dfi_p0_ras_n = soc_litedramcore_master_p0_ras_n;
assign soc_ddrphy_dfi_p0_we_n = soc_litedramcore_master_p0_we_n;
assign soc_ddrphy_dfi_p0_cke = soc_litedramcore_master_p0_cke;
assign soc_ddrphy_dfi_p0_odt = soc_litedramcore_master_p0_odt;
assign soc_ddrphy_dfi_p0_reset_n = soc_litedramcore_master_p0_reset_n;
assign soc_ddrphy_dfi_p0_act_n = soc_litedramcore_master_p0_act_n;
assign soc_ddrphy_dfi_p0_wrdata = soc_litedramcore_master_p0_wrdata;
assign soc_ddrphy_dfi_p0_wrdata_en = soc_litedramcore_master_p0_wrdata_en;
assign soc_ddrphy_dfi_p0_wrdata_mask = soc_litedramcore_master_p0_wrdata_mask;
assign soc_ddrphy_dfi_p0_rddata_en = soc_litedramcore_master_p0_rddata_en;
assign soc_litedramcore_master_p0_rddata = soc_ddrphy_dfi_p0_rddata;
assign soc_litedramcore_master_p0_rddata_valid = soc_ddrphy_dfi_p0_rddata_valid;
assign soc_ddrphy_dfi_p1_address = soc_litedramcore_master_p1_address;
assign soc_ddrphy_dfi_p1_bank = soc_litedramcore_master_p1_bank;
assign soc_ddrphy_dfi_p1_cas_n = soc_litedramcore_master_p1_cas_n;
assign soc_ddrphy_dfi_p1_cs_n = soc_litedramcore_master_p1_cs_n;
assign soc_ddrphy_dfi_p1_ras_n = soc_litedramcore_master_p1_ras_n;
assign soc_ddrphy_dfi_p1_we_n = soc_litedramcore_master_p1_we_n;
assign soc_ddrphy_dfi_p1_cke = soc_litedramcore_master_p1_cke;
assign soc_ddrphy_dfi_p1_odt = soc_litedramcore_master_p1_odt;
assign soc_ddrphy_dfi_p1_reset_n = soc_litedramcore_master_p1_reset_n;
assign soc_ddrphy_dfi_p1_act_n = soc_litedramcore_master_p1_act_n;
assign soc_ddrphy_dfi_p1_wrdata = soc_litedramcore_master_p1_wrdata;
assign soc_ddrphy_dfi_p1_wrdata_en = soc_litedramcore_master_p1_wrdata_en;
assign soc_ddrphy_dfi_p1_wrdata_mask = soc_litedramcore_master_p1_wrdata_mask;
assign soc_ddrphy_dfi_p1_rddata_en = soc_litedramcore_master_p1_rddata_en;
assign soc_litedramcore_master_p1_rddata = soc_ddrphy_dfi_p1_rddata;
assign soc_litedramcore_master_p1_rddata_valid = soc_ddrphy_dfi_p1_rddata_valid;
assign soc_ddrphy_dfi_p2_address = soc_litedramcore_master_p2_address;
assign soc_ddrphy_dfi_p2_bank = soc_litedramcore_master_p2_bank;
assign soc_ddrphy_dfi_p2_cas_n = soc_litedramcore_master_p2_cas_n;
assign soc_ddrphy_dfi_p2_cs_n = soc_litedramcore_master_p2_cs_n;
assign soc_ddrphy_dfi_p2_ras_n = soc_litedramcore_master_p2_ras_n;
assign soc_ddrphy_dfi_p2_we_n = soc_litedramcore_master_p2_we_n;
assign soc_ddrphy_dfi_p2_cke = soc_litedramcore_master_p2_cke;
assign soc_ddrphy_dfi_p2_odt = soc_litedramcore_master_p2_odt;
assign soc_ddrphy_dfi_p2_reset_n = soc_litedramcore_master_p2_reset_n;
assign soc_ddrphy_dfi_p2_act_n = soc_litedramcore_master_p2_act_n;
assign soc_ddrphy_dfi_p2_wrdata = soc_litedramcore_master_p2_wrdata;
assign soc_ddrphy_dfi_p2_wrdata_en = soc_litedramcore_master_p2_wrdata_en;
assign soc_ddrphy_dfi_p2_wrdata_mask = soc_litedramcore_master_p2_wrdata_mask;
assign soc_ddrphy_dfi_p2_rddata_en = soc_litedramcore_master_p2_rddata_en;
assign soc_litedramcore_master_p2_rddata = soc_ddrphy_dfi_p2_rddata;
assign soc_litedramcore_master_p2_rddata_valid = soc_ddrphy_dfi_p2_rddata_valid;
assign soc_ddrphy_dfi_p3_address = soc_litedramcore_master_p3_address;
assign soc_ddrphy_dfi_p3_bank = soc_litedramcore_master_p3_bank;
assign soc_ddrphy_dfi_p3_cas_n = soc_litedramcore_master_p3_cas_n;
assign soc_ddrphy_dfi_p3_cs_n = soc_litedramcore_master_p3_cs_n;
assign soc_ddrphy_dfi_p3_ras_n = soc_litedramcore_master_p3_ras_n;
assign soc_ddrphy_dfi_p3_we_n = soc_litedramcore_master_p3_we_n;
assign soc_ddrphy_dfi_p3_cke = soc_litedramcore_master_p3_cke;
assign soc_ddrphy_dfi_p3_odt = soc_litedramcore_master_p3_odt;
assign soc_ddrphy_dfi_p3_reset_n = soc_litedramcore_master_p3_reset_n;
assign soc_ddrphy_dfi_p3_act_n = soc_litedramcore_master_p3_act_n;
assign soc_ddrphy_dfi_p3_wrdata = soc_litedramcore_master_p3_wrdata;
assign soc_ddrphy_dfi_p3_wrdata_en = soc_litedramcore_master_p3_wrdata_en;
assign soc_ddrphy_dfi_p3_wrdata_mask = soc_litedramcore_master_p3_wrdata_mask;
assign soc_ddrphy_dfi_p3_rddata_en = soc_litedramcore_master_p3_rddata_en;
assign soc_litedramcore_master_p3_rddata = soc_ddrphy_dfi_p3_rddata;
assign soc_litedramcore_master_p3_rddata_valid = soc_ddrphy_dfi_p3_rddata_valid;
assign soc_litedramcore_slave_p0_address = soc_litedramcore_dfi_p0_address;
assign soc_litedramcore_slave_p0_bank = soc_litedramcore_dfi_p0_bank;
assign soc_litedramcore_slave_p0_cas_n = soc_litedramcore_dfi_p0_cas_n;
assign soc_litedramcore_slave_p0_cs_n = soc_litedramcore_dfi_p0_cs_n;
assign soc_litedramcore_slave_p0_ras_n = soc_litedramcore_dfi_p0_ras_n;
assign soc_litedramcore_slave_p0_we_n = soc_litedramcore_dfi_p0_we_n;
assign soc_litedramcore_slave_p0_cke = soc_litedramcore_dfi_p0_cke;
assign soc_litedramcore_slave_p0_odt = soc_litedramcore_dfi_p0_odt;
assign soc_litedramcore_slave_p0_reset_n = soc_litedramcore_dfi_p0_reset_n;
assign soc_litedramcore_slave_p0_act_n = soc_litedramcore_dfi_p0_act_n;
assign soc_litedramcore_slave_p0_wrdata = soc_litedramcore_dfi_p0_wrdata;
assign soc_litedramcore_slave_p0_wrdata_en = soc_litedramcore_dfi_p0_wrdata_en;
assign soc_litedramcore_slave_p0_wrdata_mask = soc_litedramcore_dfi_p0_wrdata_mask;
assign soc_litedramcore_slave_p0_rddata_en = soc_litedramcore_dfi_p0_rddata_en;
assign soc_litedramcore_dfi_p0_rddata = soc_litedramcore_slave_p0_rddata;
assign soc_litedramcore_dfi_p0_rddata_valid = soc_litedramcore_slave_p0_rddata_valid;
assign soc_litedramcore_slave_p1_address = soc_litedramcore_dfi_p1_address;
assign soc_litedramcore_slave_p1_bank = soc_litedramcore_dfi_p1_bank;
assign soc_litedramcore_slave_p1_cas_n = soc_litedramcore_dfi_p1_cas_n;
assign soc_litedramcore_slave_p1_cs_n = soc_litedramcore_dfi_p1_cs_n;
assign soc_litedramcore_slave_p1_ras_n = soc_litedramcore_dfi_p1_ras_n;
assign soc_litedramcore_slave_p1_we_n = soc_litedramcore_dfi_p1_we_n;
assign soc_litedramcore_slave_p1_cke = soc_litedramcore_dfi_p1_cke;
assign soc_litedramcore_slave_p1_odt = soc_litedramcore_dfi_p1_odt;
assign soc_litedramcore_slave_p1_reset_n = soc_litedramcore_dfi_p1_reset_n;
assign soc_litedramcore_slave_p1_act_n = soc_litedramcore_dfi_p1_act_n;
assign soc_litedramcore_slave_p1_wrdata = soc_litedramcore_dfi_p1_wrdata;
assign soc_litedramcore_slave_p1_wrdata_en = soc_litedramcore_dfi_p1_wrdata_en;
assign soc_litedramcore_slave_p1_wrdata_mask = soc_litedramcore_dfi_p1_wrdata_mask;
assign soc_litedramcore_slave_p1_rddata_en = soc_litedramcore_dfi_p1_rddata_en;
assign soc_litedramcore_dfi_p1_rddata = soc_litedramcore_slave_p1_rddata;
assign soc_litedramcore_dfi_p1_rddata_valid = soc_litedramcore_slave_p1_rddata_valid;
assign soc_litedramcore_slave_p2_address = soc_litedramcore_dfi_p2_address;
assign soc_litedramcore_slave_p2_bank = soc_litedramcore_dfi_p2_bank;
assign soc_litedramcore_slave_p2_cas_n = soc_litedramcore_dfi_p2_cas_n;
assign soc_litedramcore_slave_p2_cs_n = soc_litedramcore_dfi_p2_cs_n;
assign soc_litedramcore_slave_p2_ras_n = soc_litedramcore_dfi_p2_ras_n;
assign soc_litedramcore_slave_p2_we_n = soc_litedramcore_dfi_p2_we_n;
assign soc_litedramcore_slave_p2_cke = soc_litedramcore_dfi_p2_cke;
assign soc_litedramcore_slave_p2_odt = soc_litedramcore_dfi_p2_odt;
assign soc_litedramcore_slave_p2_reset_n = soc_litedramcore_dfi_p2_reset_n;
assign soc_litedramcore_slave_p2_act_n = soc_litedramcore_dfi_p2_act_n;
assign soc_litedramcore_slave_p2_wrdata = soc_litedramcore_dfi_p2_wrdata;
assign soc_litedramcore_slave_p2_wrdata_en = soc_litedramcore_dfi_p2_wrdata_en;
assign soc_litedramcore_slave_p2_wrdata_mask = soc_litedramcore_dfi_p2_wrdata_mask;
assign soc_litedramcore_slave_p2_rddata_en = soc_litedramcore_dfi_p2_rddata_en;
assign soc_litedramcore_dfi_p2_rddata = soc_litedramcore_slave_p2_rddata;
assign soc_litedramcore_dfi_p2_rddata_valid = soc_litedramcore_slave_p2_rddata_valid;
assign soc_litedramcore_slave_p3_address = soc_litedramcore_dfi_p3_address;
assign soc_litedramcore_slave_p3_bank = soc_litedramcore_dfi_p3_bank;
assign soc_litedramcore_slave_p3_cas_n = soc_litedramcore_dfi_p3_cas_n;
assign soc_litedramcore_slave_p3_cs_n = soc_litedramcore_dfi_p3_cs_n;
assign soc_litedramcore_slave_p3_ras_n = soc_litedramcore_dfi_p3_ras_n;
assign soc_litedramcore_slave_p3_we_n = soc_litedramcore_dfi_p3_we_n;
assign soc_litedramcore_slave_p3_cke = soc_litedramcore_dfi_p3_cke;
assign soc_litedramcore_slave_p3_odt = soc_litedramcore_dfi_p3_odt;
assign soc_litedramcore_slave_p3_reset_n = soc_litedramcore_dfi_p3_reset_n;
assign soc_litedramcore_slave_p3_act_n = soc_litedramcore_dfi_p3_act_n;
assign soc_litedramcore_slave_p3_wrdata = soc_litedramcore_dfi_p3_wrdata;
assign soc_litedramcore_slave_p3_wrdata_en = soc_litedramcore_dfi_p3_wrdata_en;
assign soc_litedramcore_slave_p3_wrdata_mask = soc_litedramcore_dfi_p3_wrdata_mask;
assign soc_litedramcore_slave_p3_rddata_en = soc_litedramcore_dfi_p3_rddata_en;
assign soc_litedramcore_dfi_p3_rddata = soc_litedramcore_slave_p3_rddata;
assign soc_litedramcore_dfi_p3_rddata_valid = soc_litedramcore_slave_p3_rddata_valid;
always @(*) begin
    soc_litedramcore_ext_dfi_p3_rddata <= 32'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_ext_dfi_p3_rddata <= soc_litedramcore_master_p3_rddata;
        end else begin
        end
    end else begin
    end
end
always @(*) begin
    soc_litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_ext_dfi_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid;
        end else begin
        end
    end else begin
    end
end
always @(*) begin
    soc_litedramcore_slave_p1_rddata <= 32'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
        end else begin
            soc_litedramcore_slave_p1_rddata <= soc_litedramcore_master_p1_rddata;
        end
    end else begin
    end
end
always @(*) begin
    soc_litedramcore_slave_p1_rddata_valid <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
        end else begin
            soc_litedramcore_slave_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid;
        end
    end else begin
    end
end
always @(*) begin
    soc_litedramcore_slave_p2_rddata <= 32'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
        end else begin
            soc_litedramcore_slave_p2_rddata <= soc_litedramcore_master_p2_rddata;
        end
    end else begin
    end
end
always @(*) begin
    soc_litedramcore_slave_p2_rddata_valid <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
        end else begin
            soc_litedramcore_slave_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid;
        end
    end else begin
    end
end
always @(*) begin
    soc_litedramcore_slave_p3_rddata <= 32'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
        end else begin
            soc_litedramcore_slave_p3_rddata <= soc_litedramcore_master_p3_rddata;
        end
    end else begin
    end
end
always @(*) begin
    soc_litedramcore_slave_p3_rddata_valid <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
        end else begin
            soc_litedramcore_slave_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid;
        end
    end else begin
    end
end
always @(*) begin
    soc_litedramcore_master_p0_address <= 14'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p0_address <= soc_litedramcore_ext_dfi_p0_address;
        end else begin
            soc_litedramcore_master_p0_address <= soc_litedramcore_slave_p0_address;
        end
    end else begin
        soc_litedramcore_master_p0_address <= soc_litedramcore_csr_dfi_p0_address;
    end
end
always @(*) begin
    soc_litedramcore_master_p0_bank <= 3'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p0_bank <= soc_litedramcore_ext_dfi_p0_bank;
        end else begin
            soc_litedramcore_master_p0_bank <= soc_litedramcore_slave_p0_bank;
        end
    end else begin
        soc_litedramcore_master_p0_bank <= soc_litedramcore_csr_dfi_p0_bank;
    end
end
always @(*) begin
    soc_litedramcore_master_p0_cas_n <= 1'd1;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p0_cas_n <= soc_litedramcore_ext_dfi_p0_cas_n;
        end else begin
            soc_litedramcore_master_p0_cas_n <= soc_litedramcore_slave_p0_cas_n;
        end
    end else begin
        soc_litedramcore_master_p0_cas_n <= soc_litedramcore_csr_dfi_p0_cas_n;
    end
end
always @(*) begin
    soc_litedramcore_master_p0_cs_n <= 1'd1;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p0_cs_n <= soc_litedramcore_ext_dfi_p0_cs_n;
        end else begin
            soc_litedramcore_master_p0_cs_n <= soc_litedramcore_slave_p0_cs_n;
            if (1'd0) begin
                soc_litedramcore_master_p0_cs_n <= {2{soc_litedramcore_slave_p0_cs_n}};
            end
        end
    end else begin
        soc_litedramcore_master_p0_cs_n <= soc_litedramcore_csr_dfi_p0_cs_n;
    end
end
always @(*) begin
    soc_litedramcore_master_p0_ras_n <= 1'd1;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p0_ras_n <= soc_litedramcore_ext_dfi_p0_ras_n;
        end else begin
            soc_litedramcore_master_p0_ras_n <= soc_litedramcore_slave_p0_ras_n;
        end
    end else begin
        soc_litedramcore_master_p0_ras_n <= soc_litedramcore_csr_dfi_p0_ras_n;
    end
end
always @(*) begin
    soc_litedramcore_master_p0_we_n <= 1'd1;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p0_we_n <= soc_litedramcore_ext_dfi_p0_we_n;
        end else begin
            soc_litedramcore_master_p0_we_n <= soc_litedramcore_slave_p0_we_n;
        end
    end else begin
        soc_litedramcore_master_p0_we_n <= soc_litedramcore_csr_dfi_p0_we_n;
    end
end
always @(*) begin
    soc_litedramcore_master_p0_cke <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p0_cke <= soc_litedramcore_ext_dfi_p0_cke;
        end else begin
            soc_litedramcore_master_p0_cke <= soc_litedramcore_slave_p0_cke;
        end
    end else begin
        soc_litedramcore_master_p0_cke <= soc_litedramcore_csr_dfi_p0_cke;
    end
end
always @(*) begin
    soc_litedramcore_master_p0_odt <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p0_odt <= soc_litedramcore_ext_dfi_p0_odt;
        end else begin
            soc_litedramcore_master_p0_odt <= soc_litedramcore_slave_p0_odt;
        end
    end else begin
        soc_litedramcore_master_p0_odt <= soc_litedramcore_csr_dfi_p0_odt;
    end
end
always @(*) begin
    soc_litedramcore_master_p0_reset_n <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p0_reset_n <= soc_litedramcore_ext_dfi_p0_reset_n;
        end else begin
            soc_litedramcore_master_p0_reset_n <= soc_litedramcore_slave_p0_reset_n;
        end
    end else begin
        soc_litedramcore_master_p0_reset_n <= soc_litedramcore_csr_dfi_p0_reset_n;
    end
end
always @(*) begin
    soc_litedramcore_master_p0_act_n <= 1'd1;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p0_act_n <= soc_litedramcore_ext_dfi_p0_act_n;
        end else begin
            soc_litedramcore_master_p0_act_n <= soc_litedramcore_slave_p0_act_n;
        end
    end else begin
        soc_litedramcore_master_p0_act_n <= soc_litedramcore_csr_dfi_p0_act_n;
    end
end
always @(*) begin
    soc_litedramcore_master_p0_wrdata <= 32'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p0_wrdata <= soc_litedramcore_ext_dfi_p0_wrdata;
        end else begin
            soc_litedramcore_master_p0_wrdata <= soc_litedramcore_slave_p0_wrdata;
        end
    end else begin
        soc_litedramcore_master_p0_wrdata <= soc_litedramcore_csr_dfi_p0_wrdata;
    end
end
always @(*) begin
    soc_litedramcore_master_p0_wrdata_en <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_ext_dfi_p0_wrdata_en;
        end else begin
            soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_slave_p0_wrdata_en;
        end
    end else begin
        soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_csr_dfi_p0_wrdata_en;
    end
end
always @(*) begin
    soc_litedramcore_master_p0_wrdata_mask <= 4'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_ext_dfi_p0_wrdata_mask;
        end else begin
            soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_slave_p0_wrdata_mask;
        end
    end else begin
        soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_csr_dfi_p0_wrdata_mask;
    end
end
always @(*) begin
    soc_litedramcore_master_p0_rddata_en <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_ext_dfi_p0_rddata_en;
        end else begin
            soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_slave_p0_rddata_en;
        end
    end else begin
        soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_csr_dfi_p0_rddata_en;
    end
end
always @(*) begin
    soc_litedramcore_master_p1_address <= 14'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p1_address <= soc_litedramcore_ext_dfi_p1_address;
        end else begin
            soc_litedramcore_master_p1_address <= soc_litedramcore_slave_p1_address;
        end
    end else begin
        soc_litedramcore_master_p1_address <= soc_litedramcore_csr_dfi_p1_address;
    end
end
always @(*) begin
    soc_litedramcore_master_p1_bank <= 3'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p1_bank <= soc_litedramcore_ext_dfi_p1_bank;
        end else begin
            soc_litedramcore_master_p1_bank <= soc_litedramcore_slave_p1_bank;
        end
    end else begin
        soc_litedramcore_master_p1_bank <= soc_litedramcore_csr_dfi_p1_bank;
    end
end
always @(*) begin
    soc_litedramcore_master_p1_cas_n <= 1'd1;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p1_cas_n <= soc_litedramcore_ext_dfi_p1_cas_n;
        end else begin
            soc_litedramcore_master_p1_cas_n <= soc_litedramcore_slave_p1_cas_n;
        end
    end else begin
        soc_litedramcore_master_p1_cas_n <= soc_litedramcore_csr_dfi_p1_cas_n;
    end
end
always @(*) begin
    soc_litedramcore_master_p1_cs_n <= 1'd1;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p1_cs_n <= soc_litedramcore_ext_dfi_p1_cs_n;
        end else begin
            soc_litedramcore_master_p1_cs_n <= soc_litedramcore_slave_p1_cs_n;
            if (1'd0) begin
                soc_litedramcore_master_p1_cs_n <= {2{soc_litedramcore_slave_p1_cs_n}};
            end
        end
    end else begin
        soc_litedramcore_master_p1_cs_n <= soc_litedramcore_csr_dfi_p1_cs_n;
    end
end
always @(*) begin
    soc_litedramcore_master_p1_ras_n <= 1'd1;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p1_ras_n <= soc_litedramcore_ext_dfi_p1_ras_n;
        end else begin
            soc_litedramcore_master_p1_ras_n <= soc_litedramcore_slave_p1_ras_n;
        end
    end else begin
        soc_litedramcore_master_p1_ras_n <= soc_litedramcore_csr_dfi_p1_ras_n;
    end
end
always @(*) begin
    soc_litedramcore_master_p1_we_n <= 1'd1;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p1_we_n <= soc_litedramcore_ext_dfi_p1_we_n;
        end else begin
            soc_litedramcore_master_p1_we_n <= soc_litedramcore_slave_p1_we_n;
        end
    end else begin
        soc_litedramcore_master_p1_we_n <= soc_litedramcore_csr_dfi_p1_we_n;
    end
end
always @(*) begin
    soc_litedramcore_master_p1_cke <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p1_cke <= soc_litedramcore_ext_dfi_p1_cke;
        end else begin
            soc_litedramcore_master_p1_cke <= soc_litedramcore_slave_p1_cke;
        end
    end else begin
        soc_litedramcore_master_p1_cke <= soc_litedramcore_csr_dfi_p1_cke;
    end
end
always @(*) begin
    soc_litedramcore_master_p1_odt <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p1_odt <= soc_litedramcore_ext_dfi_p1_odt;
        end else begin
            soc_litedramcore_master_p1_odt <= soc_litedramcore_slave_p1_odt;
        end
    end else begin
        soc_litedramcore_master_p1_odt <= soc_litedramcore_csr_dfi_p1_odt;
    end
end
always @(*) begin
    soc_litedramcore_master_p1_reset_n <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p1_reset_n <= soc_litedramcore_ext_dfi_p1_reset_n;
        end else begin
            soc_litedramcore_master_p1_reset_n <= soc_litedramcore_slave_p1_reset_n;
        end
    end else begin
        soc_litedramcore_master_p1_reset_n <= soc_litedramcore_csr_dfi_p1_reset_n;
    end
end
always @(*) begin
    soc_litedramcore_master_p1_act_n <= 1'd1;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p1_act_n <= soc_litedramcore_ext_dfi_p1_act_n;
        end else begin
            soc_litedramcore_master_p1_act_n <= soc_litedramcore_slave_p1_act_n;
        end
    end else begin
        soc_litedramcore_master_p1_act_n <= soc_litedramcore_csr_dfi_p1_act_n;
    end
end
always @(*) begin
    soc_litedramcore_master_p1_wrdata <= 32'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p1_wrdata <= soc_litedramcore_ext_dfi_p1_wrdata;
        end else begin
            soc_litedramcore_master_p1_wrdata <= soc_litedramcore_slave_p1_wrdata;
        end
    end else begin
        soc_litedramcore_master_p1_wrdata <= soc_litedramcore_csr_dfi_p1_wrdata;
    end
end
always @(*) begin
    soc_litedramcore_master_p1_wrdata_en <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_ext_dfi_p1_wrdata_en;
        end else begin
            soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_slave_p1_wrdata_en;
        end
    end else begin
        soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_csr_dfi_p1_wrdata_en;
    end
end
always @(*) begin
    soc_litedramcore_master_p1_wrdata_mask <= 4'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_ext_dfi_p1_wrdata_mask;
        end else begin
            soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_slave_p1_wrdata_mask;
        end
    end else begin
        soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_csr_dfi_p1_wrdata_mask;
    end
end
always @(*) begin
    soc_litedramcore_master_p1_rddata_en <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_ext_dfi_p1_rddata_en;
        end else begin
            soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_slave_p1_rddata_en;
        end
    end else begin
        soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_csr_dfi_p1_rddata_en;
    end
end
always @(*) begin
    soc_litedramcore_master_p2_address <= 14'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p2_address <= soc_litedramcore_ext_dfi_p2_address;
        end else begin
            soc_litedramcore_master_p2_address <= soc_litedramcore_slave_p2_address;
        end
    end else begin
        soc_litedramcore_master_p2_address <= soc_litedramcore_csr_dfi_p2_address;
    end
end
always @(*) begin
    soc_litedramcore_master_p2_bank <= 3'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p2_bank <= soc_litedramcore_ext_dfi_p2_bank;
        end else begin
            soc_litedramcore_master_p2_bank <= soc_litedramcore_slave_p2_bank;
        end
    end else begin
        soc_litedramcore_master_p2_bank <= soc_litedramcore_csr_dfi_p2_bank;
    end
end
always @(*) begin
    soc_litedramcore_master_p2_cas_n <= 1'd1;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p2_cas_n <= soc_litedramcore_ext_dfi_p2_cas_n;
        end else begin
            soc_litedramcore_master_p2_cas_n <= soc_litedramcore_slave_p2_cas_n;
        end
    end else begin
        soc_litedramcore_master_p2_cas_n <= soc_litedramcore_csr_dfi_p2_cas_n;
    end
end
always @(*) begin
    soc_litedramcore_master_p2_cs_n <= 1'd1;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p2_cs_n <= soc_litedramcore_ext_dfi_p2_cs_n;
        end else begin
            soc_litedramcore_master_p2_cs_n <= soc_litedramcore_slave_p2_cs_n;
            if (1'd0) begin
                soc_litedramcore_master_p2_cs_n <= {2{soc_litedramcore_slave_p2_cs_n}};
            end
        end
    end else begin
        soc_litedramcore_master_p2_cs_n <= soc_litedramcore_csr_dfi_p2_cs_n;
    end
end
always @(*) begin
    soc_litedramcore_master_p2_ras_n <= 1'd1;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p2_ras_n <= soc_litedramcore_ext_dfi_p2_ras_n;
        end else begin
            soc_litedramcore_master_p2_ras_n <= soc_litedramcore_slave_p2_ras_n;
        end
    end else begin
        soc_litedramcore_master_p2_ras_n <= soc_litedramcore_csr_dfi_p2_ras_n;
    end
end
always @(*) begin
    soc_litedramcore_master_p2_we_n <= 1'd1;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p2_we_n <= soc_litedramcore_ext_dfi_p2_we_n;
        end else begin
            soc_litedramcore_master_p2_we_n <= soc_litedramcore_slave_p2_we_n;
        end
    end else begin
        soc_litedramcore_master_p2_we_n <= soc_litedramcore_csr_dfi_p2_we_n;
    end
end
always @(*) begin
    soc_litedramcore_master_p2_cke <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p2_cke <= soc_litedramcore_ext_dfi_p2_cke;
        end else begin
            soc_litedramcore_master_p2_cke <= soc_litedramcore_slave_p2_cke;
        end
    end else begin
        soc_litedramcore_master_p2_cke <= soc_litedramcore_csr_dfi_p2_cke;
    end
end
always @(*) begin
    soc_litedramcore_master_p2_odt <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p2_odt <= soc_litedramcore_ext_dfi_p2_odt;
        end else begin
            soc_litedramcore_master_p2_odt <= soc_litedramcore_slave_p2_odt;
        end
    end else begin
        soc_litedramcore_master_p2_odt <= soc_litedramcore_csr_dfi_p2_odt;
    end
end
always @(*) begin
    soc_litedramcore_master_p2_reset_n <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p2_reset_n <= soc_litedramcore_ext_dfi_p2_reset_n;
        end else begin
            soc_litedramcore_master_p2_reset_n <= soc_litedramcore_slave_p2_reset_n;
        end
    end else begin
        soc_litedramcore_master_p2_reset_n <= soc_litedramcore_csr_dfi_p2_reset_n;
    end
end
always @(*) begin
    soc_litedramcore_master_p2_act_n <= 1'd1;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p2_act_n <= soc_litedramcore_ext_dfi_p2_act_n;
        end else begin
            soc_litedramcore_master_p2_act_n <= soc_litedramcore_slave_p2_act_n;
        end
    end else begin
        soc_litedramcore_master_p2_act_n <= soc_litedramcore_csr_dfi_p2_act_n;
    end
end
always @(*) begin
    soc_litedramcore_master_p2_wrdata <= 32'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p2_wrdata <= soc_litedramcore_ext_dfi_p2_wrdata;
        end else begin
            soc_litedramcore_master_p2_wrdata <= soc_litedramcore_slave_p2_wrdata;
        end
    end else begin
        soc_litedramcore_master_p2_wrdata <= soc_litedramcore_csr_dfi_p2_wrdata;
    end
end
always @(*) begin
    soc_litedramcore_master_p2_wrdata_en <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_ext_dfi_p2_wrdata_en;
        end else begin
            soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_slave_p2_wrdata_en;
        end
    end else begin
        soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_csr_dfi_p2_wrdata_en;
    end
end
always @(*) begin
    soc_litedramcore_master_p2_wrdata_mask <= 4'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_ext_dfi_p2_wrdata_mask;
        end else begin
            soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_slave_p2_wrdata_mask;
        end
    end else begin
        soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_csr_dfi_p2_wrdata_mask;
    end
end
always @(*) begin
    soc_litedramcore_master_p2_rddata_en <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_ext_dfi_p2_rddata_en;
        end else begin
            soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_slave_p2_rddata_en;
        end
    end else begin
        soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_csr_dfi_p2_rddata_en;
    end
end
always @(*) begin
    soc_litedramcore_master_p3_address <= 14'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p3_address <= soc_litedramcore_ext_dfi_p3_address;
        end else begin
            soc_litedramcore_master_p3_address <= soc_litedramcore_slave_p3_address;
        end
    end else begin
        soc_litedramcore_master_p3_address <= soc_litedramcore_csr_dfi_p3_address;
    end
end
always @(*) begin
    soc_litedramcore_master_p3_bank <= 3'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p3_bank <= soc_litedramcore_ext_dfi_p3_bank;
        end else begin
            soc_litedramcore_master_p3_bank <= soc_litedramcore_slave_p3_bank;
        end
    end else begin
        soc_litedramcore_master_p3_bank <= soc_litedramcore_csr_dfi_p3_bank;
    end
end
always @(*) begin
    soc_litedramcore_master_p3_cas_n <= 1'd1;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p3_cas_n <= soc_litedramcore_ext_dfi_p3_cas_n;
        end else begin
            soc_litedramcore_master_p3_cas_n <= soc_litedramcore_slave_p3_cas_n;
        end
    end else begin
        soc_litedramcore_master_p3_cas_n <= soc_litedramcore_csr_dfi_p3_cas_n;
    end
end
always @(*) begin
    soc_litedramcore_master_p3_cs_n <= 1'd1;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p3_cs_n <= soc_litedramcore_ext_dfi_p3_cs_n;
        end else begin
            soc_litedramcore_master_p3_cs_n <= soc_litedramcore_slave_p3_cs_n;
            if (1'd0) begin
                soc_litedramcore_master_p3_cs_n <= {2{soc_litedramcore_slave_p3_cs_n}};
            end
        end
    end else begin
        soc_litedramcore_master_p3_cs_n <= soc_litedramcore_csr_dfi_p3_cs_n;
    end
end
always @(*) begin
    soc_litedramcore_master_p3_ras_n <= 1'd1;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p3_ras_n <= soc_litedramcore_ext_dfi_p3_ras_n;
        end else begin
            soc_litedramcore_master_p3_ras_n <= soc_litedramcore_slave_p3_ras_n;
        end
    end else begin
        soc_litedramcore_master_p3_ras_n <= soc_litedramcore_csr_dfi_p3_ras_n;
    end
end
always @(*) begin
    soc_litedramcore_master_p3_we_n <= 1'd1;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p3_we_n <= soc_litedramcore_ext_dfi_p3_we_n;
        end else begin
            soc_litedramcore_master_p3_we_n <= soc_litedramcore_slave_p3_we_n;
        end
    end else begin
        soc_litedramcore_master_p3_we_n <= soc_litedramcore_csr_dfi_p3_we_n;
    end
end
always @(*) begin
    soc_litedramcore_master_p3_cke <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p3_cke <= soc_litedramcore_ext_dfi_p3_cke;
        end else begin
            soc_litedramcore_master_p3_cke <= soc_litedramcore_slave_p3_cke;
        end
    end else begin
        soc_litedramcore_master_p3_cke <= soc_litedramcore_csr_dfi_p3_cke;
    end
end
always @(*) begin
    soc_litedramcore_master_p3_odt <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p3_odt <= soc_litedramcore_ext_dfi_p3_odt;
        end else begin
            soc_litedramcore_master_p3_odt <= soc_litedramcore_slave_p3_odt;
        end
    end else begin
        soc_litedramcore_master_p3_odt <= soc_litedramcore_csr_dfi_p3_odt;
    end
end
always @(*) begin
    soc_litedramcore_master_p3_reset_n <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p3_reset_n <= soc_litedramcore_ext_dfi_p3_reset_n;
        end else begin
            soc_litedramcore_master_p3_reset_n <= soc_litedramcore_slave_p3_reset_n;
        end
    end else begin
        soc_litedramcore_master_p3_reset_n <= soc_litedramcore_csr_dfi_p3_reset_n;
    end
end
always @(*) begin
    soc_litedramcore_master_p3_act_n <= 1'd1;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p3_act_n <= soc_litedramcore_ext_dfi_p3_act_n;
        end else begin
            soc_litedramcore_master_p3_act_n <= soc_litedramcore_slave_p3_act_n;
        end
    end else begin
        soc_litedramcore_master_p3_act_n <= soc_litedramcore_csr_dfi_p3_act_n;
    end
end
always @(*) begin
    soc_litedramcore_master_p3_wrdata <= 32'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p3_wrdata <= soc_litedramcore_ext_dfi_p3_wrdata;
        end else begin
            soc_litedramcore_master_p3_wrdata <= soc_litedramcore_slave_p3_wrdata;
        end
    end else begin
        soc_litedramcore_master_p3_wrdata <= soc_litedramcore_csr_dfi_p3_wrdata;
    end
end
always @(*) begin
    soc_litedramcore_master_p3_wrdata_en <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_ext_dfi_p3_wrdata_en;
        end else begin
            soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_slave_p3_wrdata_en;
        end
    end else begin
        soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_csr_dfi_p3_wrdata_en;
    end
end
always @(*) begin
    soc_litedramcore_master_p3_wrdata_mask <= 4'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_ext_dfi_p3_wrdata_mask;
        end else begin
            soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_slave_p3_wrdata_mask;
        end
    end else begin
        soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_csr_dfi_p3_wrdata_mask;
    end
end
always @(*) begin
    soc_litedramcore_master_p3_rddata_en <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_ext_dfi_p3_rddata_en;
        end else begin
            soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_slave_p3_rddata_en;
        end
    end else begin
        soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_csr_dfi_p3_rddata_en;
    end
end
always @(*) begin
    soc_litedramcore_csr_dfi_p0_rddata <= 32'd0;
    if (soc_litedramcore_sel) begin
    end else begin
        soc_litedramcore_csr_dfi_p0_rddata <= soc_litedramcore_master_p0_rddata;
    end
end
always @(*) begin
    soc_litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
    if (soc_litedramcore_sel) begin
    end else begin
        soc_litedramcore_csr_dfi_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid;
    end
end
always @(*) begin
    soc_litedramcore_csr_dfi_p1_rddata <= 32'd0;
    if (soc_litedramcore_sel) begin
    end else begin
        soc_litedramcore_csr_dfi_p1_rddata <= soc_litedramcore_master_p1_rddata;
    end
end
always @(*) begin
    soc_litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
    if (soc_litedramcore_sel) begin
    end else begin
        soc_litedramcore_csr_dfi_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid;
    end
end
always @(*) begin
    soc_litedramcore_csr_dfi_p2_rddata <= 32'd0;
    if (soc_litedramcore_sel) begin
    end else begin
        soc_litedramcore_csr_dfi_p2_rddata <= soc_litedramcore_master_p2_rddata;
    end
end
always @(*) begin
    soc_litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
    if (soc_litedramcore_sel) begin
    end else begin
        soc_litedramcore_csr_dfi_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid;
    end
end
always @(*) begin
    soc_litedramcore_csr_dfi_p3_rddata <= 32'd0;
    if (soc_litedramcore_sel) begin
    end else begin
        soc_litedramcore_csr_dfi_p3_rddata <= soc_litedramcore_master_p3_rddata;
    end
end
always @(*) begin
    soc_litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
    if (soc_litedramcore_sel) begin
    end else begin
        soc_litedramcore_csr_dfi_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid;
    end
end
always @(*) begin
    soc_litedramcore_ext_dfi_p0_rddata <= 32'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_ext_dfi_p0_rddata <= soc_litedramcore_master_p0_rddata;
        end else begin
        end
    end else begin
    end
end
always @(*) begin
    soc_litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_ext_dfi_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid;
        end else begin
        end
    end else begin
    end
end
always @(*) begin
    soc_litedramcore_ext_dfi_p1_rddata <= 32'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_ext_dfi_p1_rddata <= soc_litedramcore_master_p1_rddata;
        end else begin
        end
    end else begin
    end
end
always @(*) begin
    soc_litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_ext_dfi_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid;
        end else begin
        end
    end else begin
    end
end
always @(*) begin
    soc_litedramcore_ext_dfi_p2_rddata <= 32'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_ext_dfi_p2_rddata <= soc_litedramcore_master_p2_rddata;
        end else begin
        end
    end else begin
    end
end
always @(*) begin
    soc_litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
            soc_litedramcore_ext_dfi_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid;
        end else begin
        end
    end else begin
    end
end
always @(*) begin
    soc_litedramcore_slave_p0_rddata <= 32'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
        end else begin
            soc_litedramcore_slave_p0_rddata <= soc_litedramcore_master_p0_rddata;
        end
    end else begin
    end
end
always @(*) begin
    soc_litedramcore_slave_p0_rddata_valid <= 1'd0;
    if (soc_litedramcore_sel) begin
        if (soc_litedramcore_ext_dfi_sel) begin
        end else begin
            soc_litedramcore_slave_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid;
        end
    end else begin
    end
end
assign soc_litedramcore_csr_dfi_p0_cke = soc_litedramcore_cke;
assign soc_litedramcore_csr_dfi_p1_cke = soc_litedramcore_cke;
assign soc_litedramcore_csr_dfi_p2_cke = soc_litedramcore_cke;
assign soc_litedramcore_csr_dfi_p3_cke = soc_litedramcore_cke;
assign soc_litedramcore_csr_dfi_p0_odt = soc_litedramcore_odt;
assign soc_litedramcore_csr_dfi_p1_odt = soc_litedramcore_odt;
assign soc_litedramcore_csr_dfi_p2_odt = soc_litedramcore_odt;
assign soc_litedramcore_csr_dfi_p3_odt = soc_litedramcore_odt;
assign soc_litedramcore_csr_dfi_p0_reset_n = soc_litedramcore_reset_n;
assign soc_litedramcore_csr_dfi_p1_reset_n = soc_litedramcore_reset_n;
assign soc_litedramcore_csr_dfi_p2_reset_n = soc_litedramcore_reset_n;
assign soc_litedramcore_csr_dfi_p3_reset_n = soc_litedramcore_reset_n;
always @(*) begin
    soc_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
    if (soc_litedramcore_phaseinjector0_command_issue_re) begin
        soc_litedramcore_csr_dfi_p0_cas_n <= (~soc_litedramcore_phaseinjector0_csrfield_cas);
    end else begin
        soc_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
    end
end
always @(*) begin
    soc_litedramcore_csr_dfi_p0_cs_n <= 1'd1;
    if (soc_litedramcore_phaseinjector0_command_issue_re) begin
        if (soc_litedramcore_phaseinjector0_csrfield_cs_top) begin
            soc_litedramcore_csr_dfi_p0_cs_n <= 2'd2;
        end else begin
            if (soc_litedramcore_phaseinjector0_csrfield_cs_bottom) begin
                soc_litedramcore_csr_dfi_p0_cs_n <= 1'd1;
            end else begin
                soc_litedramcore_csr_dfi_p0_cs_n <= {1{(~soc_litedramcore_phaseinjector0_csrfield_cs)}};
            end
        end
    end else begin
        soc_litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
    end
end
always @(*) begin
    soc_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
    if (soc_litedramcore_phaseinjector0_command_issue_re) begin
        soc_litedramcore_csr_dfi_p0_ras_n <= (~soc_litedramcore_phaseinjector0_csrfield_ras);
    end else begin
        soc_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
    end
end
always @(*) begin
    soc_litedramcore_csr_dfi_p0_we_n <= 1'd1;
    if (soc_litedramcore_phaseinjector0_command_issue_re) begin
        soc_litedramcore_csr_dfi_p0_we_n <= (~soc_litedramcore_phaseinjector0_csrfield_we);
    end else begin
        soc_litedramcore_csr_dfi_p0_we_n <= 1'd1;
    end
end
assign soc_litedramcore_csr_dfi_p0_address = soc_litedramcore_phaseinjector0_address_storage;
assign soc_litedramcore_csr_dfi_p0_bank = soc_litedramcore_phaseinjector0_baddress_storage;
assign soc_litedramcore_csr_dfi_p0_wrdata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_csrfield_wren);
assign soc_litedramcore_csr_dfi_p0_rddata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_csrfield_rden);
assign soc_litedramcore_csr_dfi_p0_wrdata = soc_litedramcore_phaseinjector0_wrdata_storage;
assign soc_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
always @(*) begin
    soc_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
    if (soc_litedramcore_phaseinjector1_command_issue_re) begin
        soc_litedramcore_csr_dfi_p1_cas_n <= (~soc_litedramcore_phaseinjector1_csrfield_cas);
    end else begin
        soc_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
    end
end
always @(*) begin
    soc_litedramcore_csr_dfi_p1_cs_n <= 1'd1;
    if (soc_litedramcore_phaseinjector1_command_issue_re) begin
        if (soc_litedramcore_phaseinjector1_csrfield_cs_top) begin
            soc_litedramcore_csr_dfi_p1_cs_n <= 2'd2;
        end else begin
            if (soc_litedramcore_phaseinjector1_csrfield_cs_bottom) begin
                soc_litedramcore_csr_dfi_p1_cs_n <= 1'd1;
            end else begin
                soc_litedramcore_csr_dfi_p1_cs_n <= {1{(~soc_litedramcore_phaseinjector1_csrfield_cs)}};
            end
        end
    end else begin
        soc_litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
    end
end
always @(*) begin
    soc_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
    if (soc_litedramcore_phaseinjector1_command_issue_re) begin
        soc_litedramcore_csr_dfi_p1_ras_n <= (~soc_litedramcore_phaseinjector1_csrfield_ras);
    end else begin
        soc_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
    end
end
always @(*) begin
    soc_litedramcore_csr_dfi_p1_we_n <= 1'd1;
    if (soc_litedramcore_phaseinjector1_command_issue_re) begin
        soc_litedramcore_csr_dfi_p1_we_n <= (~soc_litedramcore_phaseinjector1_csrfield_we);
    end else begin
        soc_litedramcore_csr_dfi_p1_we_n <= 1'd1;
    end
end
assign soc_litedramcore_csr_dfi_p1_address = soc_litedramcore_phaseinjector1_address_storage;
assign soc_litedramcore_csr_dfi_p1_bank = soc_litedramcore_phaseinjector1_baddress_storage;
assign soc_litedramcore_csr_dfi_p1_wrdata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_csrfield_wren);
assign soc_litedramcore_csr_dfi_p1_rddata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_csrfield_rden);
assign soc_litedramcore_csr_dfi_p1_wrdata = soc_litedramcore_phaseinjector1_wrdata_storage;
assign soc_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
always @(*) begin
    soc_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
    if (soc_litedramcore_phaseinjector2_command_issue_re) begin
        soc_litedramcore_csr_dfi_p2_cas_n <= (~soc_litedramcore_phaseinjector2_csrfield_cas);
    end else begin
        soc_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
    end
end
always @(*) begin
    soc_litedramcore_csr_dfi_p2_cs_n <= 1'd1;
    if (soc_litedramcore_phaseinjector2_command_issue_re) begin
        if (soc_litedramcore_phaseinjector2_csrfield_cs_top) begin
            soc_litedramcore_csr_dfi_p2_cs_n <= 2'd2;
        end else begin
            if (soc_litedramcore_phaseinjector2_csrfield_cs_bottom) begin
                soc_litedramcore_csr_dfi_p2_cs_n <= 1'd1;
            end else begin
                soc_litedramcore_csr_dfi_p2_cs_n <= {1{(~soc_litedramcore_phaseinjector2_csrfield_cs)}};
            end
        end
    end else begin
        soc_litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
    end
end
always @(*) begin
    soc_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
    if (soc_litedramcore_phaseinjector2_command_issue_re) begin
        soc_litedramcore_csr_dfi_p2_ras_n <= (~soc_litedramcore_phaseinjector2_csrfield_ras);
    end else begin
        soc_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
    end
end
always @(*) begin
    soc_litedramcore_csr_dfi_p2_we_n <= 1'd1;
    if (soc_litedramcore_phaseinjector2_command_issue_re) begin
        soc_litedramcore_csr_dfi_p2_we_n <= (~soc_litedramcore_phaseinjector2_csrfield_we);
    end else begin
        soc_litedramcore_csr_dfi_p2_we_n <= 1'd1;
    end
end
assign soc_litedramcore_csr_dfi_p2_address = soc_litedramcore_phaseinjector2_address_storage;
assign soc_litedramcore_csr_dfi_p2_bank = soc_litedramcore_phaseinjector2_baddress_storage;
assign soc_litedramcore_csr_dfi_p2_wrdata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_csrfield_wren);
assign soc_litedramcore_csr_dfi_p2_rddata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_csrfield_rden);
assign soc_litedramcore_csr_dfi_p2_wrdata = soc_litedramcore_phaseinjector2_wrdata_storage;
assign soc_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
always @(*) begin
    soc_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
    if (soc_litedramcore_phaseinjector3_command_issue_re) begin
        soc_litedramcore_csr_dfi_p3_cas_n <= (~soc_litedramcore_phaseinjector3_csrfield_cas);
    end else begin
        soc_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
    end
end
always @(*) begin
    soc_litedramcore_csr_dfi_p3_cs_n <= 1'd1;
    if (soc_litedramcore_phaseinjector3_command_issue_re) begin
        if (soc_litedramcore_phaseinjector3_csrfield_cs_top) begin
            soc_litedramcore_csr_dfi_p3_cs_n <= 2'd2;
        end else begin
            if (soc_litedramcore_phaseinjector3_csrfield_cs_bottom) begin
                soc_litedramcore_csr_dfi_p3_cs_n <= 1'd1;
            end else begin
                soc_litedramcore_csr_dfi_p3_cs_n <= {1{(~soc_litedramcore_phaseinjector3_csrfield_cs)}};
            end
        end
    end else begin
        soc_litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
    end
end
always @(*) begin
    soc_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
    if (soc_litedramcore_phaseinjector3_command_issue_re) begin
        soc_litedramcore_csr_dfi_p3_ras_n <= (~soc_litedramcore_phaseinjector3_csrfield_ras);
    end else begin
        soc_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
    end
end
always @(*) begin
    soc_litedramcore_csr_dfi_p3_we_n <= 1'd1;
    if (soc_litedramcore_phaseinjector3_command_issue_re) begin
        soc_litedramcore_csr_dfi_p3_we_n <= (~soc_litedramcore_phaseinjector3_csrfield_we);
    end else begin
        soc_litedramcore_csr_dfi_p3_we_n <= 1'd1;
    end
end
assign soc_litedramcore_csr_dfi_p3_address = soc_litedramcore_phaseinjector3_address_storage;
assign soc_litedramcore_csr_dfi_p3_bank = soc_litedramcore_phaseinjector3_baddress_storage;
assign soc_litedramcore_csr_dfi_p3_wrdata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_csrfield_wren);
assign soc_litedramcore_csr_dfi_p3_rddata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_csrfield_rden);
assign soc_litedramcore_csr_dfi_p3_wrdata = soc_litedramcore_phaseinjector3_wrdata_storage;
assign soc_litedramcore_csr_dfi_p3_wrdata_mask = 1'd0;
assign soc_litedramcore_bankmachine0_req_valid = soc_litedramcore_interface_bank0_valid;
assign soc_litedramcore_interface_bank0_ready = soc_litedramcore_bankmachine0_req_ready;
assign soc_litedramcore_bankmachine0_req_we = soc_litedramcore_interface_bank0_we;
assign soc_litedramcore_bankmachine0_req_addr = soc_litedramcore_interface_bank0_addr;
assign soc_litedramcore_interface_bank0_lock = soc_litedramcore_bankmachine0_req_lock;
assign soc_litedramcore_interface_bank0_wdata_ready = soc_litedramcore_bankmachine0_req_wdata_ready;
assign soc_litedramcore_interface_bank0_rdata_valid = soc_litedramcore_bankmachine0_req_rdata_valid;
assign soc_litedramcore_bankmachine1_req_valid = soc_litedramcore_interface_bank1_valid;
assign soc_litedramcore_interface_bank1_ready = soc_litedramcore_bankmachine1_req_ready;
assign soc_litedramcore_bankmachine1_req_we = soc_litedramcore_interface_bank1_we;
assign soc_litedramcore_bankmachine1_req_addr = soc_litedramcore_interface_bank1_addr;
assign soc_litedramcore_interface_bank1_lock = soc_litedramcore_bankmachine1_req_lock;
assign soc_litedramcore_interface_bank1_wdata_ready = soc_litedramcore_bankmachine1_req_wdata_ready;
assign soc_litedramcore_interface_bank1_rdata_valid = soc_litedramcore_bankmachine1_req_rdata_valid;
assign soc_litedramcore_bankmachine2_req_valid = soc_litedramcore_interface_bank2_valid;
assign soc_litedramcore_interface_bank2_ready = soc_litedramcore_bankmachine2_req_ready;
assign soc_litedramcore_bankmachine2_req_we = soc_litedramcore_interface_bank2_we;
assign soc_litedramcore_bankmachine2_req_addr = soc_litedramcore_interface_bank2_addr;
assign soc_litedramcore_interface_bank2_lock = soc_litedramcore_bankmachine2_req_lock;
assign soc_litedramcore_interface_bank2_wdata_ready = soc_litedramcore_bankmachine2_req_wdata_ready;
assign soc_litedramcore_interface_bank2_rdata_valid = soc_litedramcore_bankmachine2_req_rdata_valid;
assign soc_litedramcore_bankmachine3_req_valid = soc_litedramcore_interface_bank3_valid;
assign soc_litedramcore_interface_bank3_ready = soc_litedramcore_bankmachine3_req_ready;
assign soc_litedramcore_bankmachine3_req_we = soc_litedramcore_interface_bank3_we;
assign soc_litedramcore_bankmachine3_req_addr = soc_litedramcore_interface_bank3_addr;
assign soc_litedramcore_interface_bank3_lock = soc_litedramcore_bankmachine3_req_lock;
assign soc_litedramcore_interface_bank3_wdata_ready = soc_litedramcore_bankmachine3_req_wdata_ready;
assign soc_litedramcore_interface_bank3_rdata_valid = soc_litedramcore_bankmachine3_req_rdata_valid;
assign soc_litedramcore_bankmachine4_req_valid = soc_litedramcore_interface_bank4_valid;
assign soc_litedramcore_interface_bank4_ready = soc_litedramcore_bankmachine4_req_ready;
assign soc_litedramcore_bankmachine4_req_we = soc_litedramcore_interface_bank4_we;
assign soc_litedramcore_bankmachine4_req_addr = soc_litedramcore_interface_bank4_addr;
assign soc_litedramcore_interface_bank4_lock = soc_litedramcore_bankmachine4_req_lock;
assign soc_litedramcore_interface_bank4_wdata_ready = soc_litedramcore_bankmachine4_req_wdata_ready;
assign soc_litedramcore_interface_bank4_rdata_valid = soc_litedramcore_bankmachine4_req_rdata_valid;
assign soc_litedramcore_bankmachine5_req_valid = soc_litedramcore_interface_bank5_valid;
assign soc_litedramcore_interface_bank5_ready = soc_litedramcore_bankmachine5_req_ready;
assign soc_litedramcore_bankmachine5_req_we = soc_litedramcore_interface_bank5_we;
assign soc_litedramcore_bankmachine5_req_addr = soc_litedramcore_interface_bank5_addr;
assign soc_litedramcore_interface_bank5_lock = soc_litedramcore_bankmachine5_req_lock;
assign soc_litedramcore_interface_bank5_wdata_ready = soc_litedramcore_bankmachine5_req_wdata_ready;
assign soc_litedramcore_interface_bank5_rdata_valid = soc_litedramcore_bankmachine5_req_rdata_valid;
assign soc_litedramcore_bankmachine6_req_valid = soc_litedramcore_interface_bank6_valid;
assign soc_litedramcore_interface_bank6_ready = soc_litedramcore_bankmachine6_req_ready;
assign soc_litedramcore_bankmachine6_req_we = soc_litedramcore_interface_bank6_we;
assign soc_litedramcore_bankmachine6_req_addr = soc_litedramcore_interface_bank6_addr;
assign soc_litedramcore_interface_bank6_lock = soc_litedramcore_bankmachine6_req_lock;
assign soc_litedramcore_interface_bank6_wdata_ready = soc_litedramcore_bankmachine6_req_wdata_ready;
assign soc_litedramcore_interface_bank6_rdata_valid = soc_litedramcore_bankmachine6_req_rdata_valid;
assign soc_litedramcore_bankmachine7_req_valid = soc_litedramcore_interface_bank7_valid;
assign soc_litedramcore_interface_bank7_ready = soc_litedramcore_bankmachine7_req_ready;
assign soc_litedramcore_bankmachine7_req_we = soc_litedramcore_interface_bank7_we;
assign soc_litedramcore_bankmachine7_req_addr = soc_litedramcore_interface_bank7_addr;
assign soc_litedramcore_interface_bank7_lock = soc_litedramcore_bankmachine7_req_lock;
assign soc_litedramcore_interface_bank7_wdata_ready = soc_litedramcore_bankmachine7_req_wdata_ready;
assign soc_litedramcore_interface_bank7_rdata_valid = soc_litedramcore_bankmachine7_req_rdata_valid;
assign soc_litedramcore_timer_wait = (~soc_litedramcore_timer_done0);
assign soc_litedramcore_postponer_req_i = soc_litedramcore_timer_done0;
assign soc_litedramcore_wants_refresh = soc_litedramcore_postponer_req_o;
assign soc_litedramcore_wants_zqcs = soc_litedramcore_zqcs_timer_done0;
assign soc_litedramcore_zqcs_timer_wait = (~soc_litedramcore_zqcs_executer_done);
assign soc_litedramcore_timer_done1 = (soc_litedramcore_timer_count1 == 1'd0);
assign soc_litedramcore_timer_done0 = soc_litedramcore_timer_done1;
assign soc_litedramcore_timer_count0 = soc_litedramcore_timer_count1;
assign soc_litedramcore_sequencer_start1 = (soc_litedramcore_sequencer_start0 | (soc_litedramcore_sequencer_count != 1'd0));
assign soc_litedramcore_sequencer_done0 = (soc_litedramcore_sequencer_done1 & (soc_litedramcore_sequencer_count == 1'd0));
assign soc_litedramcore_zqcs_timer_done1 = (soc_litedramcore_zqcs_timer_count1 == 1'd0);
assign soc_litedramcore_zqcs_timer_done0 = soc_litedramcore_zqcs_timer_done1;
assign soc_litedramcore_zqcs_timer_count0 = soc_litedramcore_zqcs_timer_count1;
always @(*) begin
    refresher_next_state <= 2'd0;
    refresher_next_state <= refresher_state;
    case (refresher_state)
        1'd1: begin
            if (soc_litedramcore_cmd_ready) begin
                refresher_next_state <= 2'd2;
            end
        end
        2'd2: begin
            if (soc_litedramcore_sequencer_done0) begin
                if (soc_litedramcore_wants_zqcs) begin
                    refresher_next_state <= 2'd3;
                end else begin
                    refresher_next_state <= 1'd0;
                end
            end
        end
        2'd3: begin
            if (soc_litedramcore_zqcs_executer_done) begin
                refresher_next_state <= 1'd0;
            end
        end
        default: begin
            if (1'd1) begin
                if (soc_litedramcore_wants_refresh) begin
                    refresher_next_state <= 1'd1;
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_sequencer_start0 <= 1'd0;
    case (refresher_state)
        1'd1: begin
            if (soc_litedramcore_cmd_ready) begin
                soc_litedramcore_sequencer_start0 <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_cmd_valid <= 1'd0;
    case (refresher_state)
        1'd1: begin
            soc_litedramcore_cmd_valid <= 1'd1;
        end
        2'd2: begin
            soc_litedramcore_cmd_valid <= 1'd1;
            if (soc_litedramcore_sequencer_done0) begin
                if (soc_litedramcore_wants_zqcs) begin
                end else begin
                    soc_litedramcore_cmd_valid <= 1'd0;
                end
            end
        end
        2'd3: begin
            soc_litedramcore_cmd_valid <= 1'd1;
            if (soc_litedramcore_zqcs_executer_done) begin
                soc_litedramcore_cmd_valid <= 1'd0;
            end
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_zqcs_executer_start <= 1'd0;
    case (refresher_state)
        1'd1: begin
        end
        2'd2: begin
            if (soc_litedramcore_sequencer_done0) begin
                if (soc_litedramcore_wants_zqcs) begin
                    soc_litedramcore_zqcs_executer_start <= 1'd1;
                end else begin
                end
            end
        end
        2'd3: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_cmd_last <= 1'd0;
    case (refresher_state)
        1'd1: begin
        end
        2'd2: begin
            if (soc_litedramcore_sequencer_done0) begin
                if (soc_litedramcore_wants_zqcs) begin
                end else begin
                    soc_litedramcore_cmd_last <= 1'd1;
                end
            end
        end
        2'd3: begin
            if (soc_litedramcore_zqcs_executer_done) begin
                soc_litedramcore_cmd_last <= 1'd1;
            end
        end
        default: begin
        end
    endcase
end
assign soc_litedramcore_bankmachine0_sink_valid = soc_litedramcore_bankmachine0_req_valid;
assign soc_litedramcore_bankmachine0_req_ready = soc_litedramcore_bankmachine0_sink_ready;
assign soc_litedramcore_bankmachine0_sink_payload_we = soc_litedramcore_bankmachine0_req_we;
assign soc_litedramcore_bankmachine0_sink_payload_addr = soc_litedramcore_bankmachine0_req_addr;
assign soc_litedramcore_bankmachine0_sink_sink_valid = soc_litedramcore_bankmachine0_source_valid;
assign soc_litedramcore_bankmachine0_source_ready = soc_litedramcore_bankmachine0_sink_sink_ready;
assign soc_litedramcore_bankmachine0_sink_sink_first = soc_litedramcore_bankmachine0_source_first;
assign soc_litedramcore_bankmachine0_sink_sink_last = soc_litedramcore_bankmachine0_source_last;
assign soc_litedramcore_bankmachine0_sink_sink_payload_we = soc_litedramcore_bankmachine0_source_payload_we;
assign soc_litedramcore_bankmachine0_sink_sink_payload_addr = soc_litedramcore_bankmachine0_source_payload_addr;
assign soc_litedramcore_bankmachine0_source_source_ready = (soc_litedramcore_bankmachine0_req_wdata_ready | soc_litedramcore_bankmachine0_req_rdata_valid);
assign soc_litedramcore_bankmachine0_req_lock = (soc_litedramcore_bankmachine0_source_valid | soc_litedramcore_bankmachine0_source_source_valid);
assign soc_litedramcore_bankmachine0_row_hit = (soc_litedramcore_bankmachine0_row == soc_litedramcore_bankmachine0_source_source_payload_addr[20:7]);
assign soc_litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
always @(*) begin
    soc_litedramcore_bankmachine0_cmd_payload_a <= 14'd0;
    if (soc_litedramcore_bankmachine0_row_col_n_addr_sel) begin
        soc_litedramcore_bankmachine0_cmd_payload_a <= soc_litedramcore_bankmachine0_source_source_payload_addr[20:7];
    end else begin
        soc_litedramcore_bankmachine0_cmd_payload_a <= ((soc_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}});
    end
end
assign soc_litedramcore_bankmachine0_twtpcon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_cmd_payload_is_write);
assign soc_litedramcore_bankmachine0_trccon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open);
assign soc_litedramcore_bankmachine0_trascon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open);
always @(*) begin
    soc_litedramcore_bankmachine0_auto_precharge <= 1'd0;
    if ((soc_litedramcore_bankmachine0_source_valid & soc_litedramcore_bankmachine0_source_source_valid)) begin
        if ((soc_litedramcore_bankmachine0_source_payload_addr[20:7] != soc_litedramcore_bankmachine0_source_source_payload_addr[20:7])) begin
            soc_litedramcore_bankmachine0_auto_precharge <= (soc_litedramcore_bankmachine0_row_close == 1'd0);
        end
    end
end
assign soc_litedramcore_bankmachine0_syncfifo0_din = {soc_litedramcore_bankmachine0_fifo_in_last, soc_litedramcore_bankmachine0_fifo_in_first, soc_litedramcore_bankmachine0_fifo_in_payload_addr, soc_litedramcore_bankmachine0_fifo_in_payload_we};
assign {soc_litedramcore_bankmachine0_fifo_out_last, soc_litedramcore_bankmachine0_fifo_out_first, soc_litedramcore_bankmachine0_fifo_out_payload_addr, soc_litedramcore_bankmachine0_fifo_out_payload_we} = soc_litedramcore_bankmachine0_syncfifo0_dout;
assign {soc_litedramcore_bankmachine0_fifo_out_last, soc_litedramcore_bankmachine0_fifo_out_first, soc_litedramcore_bankmachine0_fifo_out_payload_addr, soc_litedramcore_bankmachine0_fifo_out_payload_we} = soc_litedramcore_bankmachine0_syncfifo0_dout;
assign {soc_litedramcore_bankmachine0_fifo_out_last, soc_litedramcore_bankmachine0_fifo_out_first, soc_litedramcore_bankmachine0_fifo_out_payload_addr, soc_litedramcore_bankmachine0_fifo_out_payload_we} = soc_litedramcore_bankmachine0_syncfifo0_dout;
assign {soc_litedramcore_bankmachine0_fifo_out_last, soc_litedramcore_bankmachine0_fifo_out_first, soc_litedramcore_bankmachine0_fifo_out_payload_addr, soc_litedramcore_bankmachine0_fifo_out_payload_we} = soc_litedramcore_bankmachine0_syncfifo0_dout;
assign soc_litedramcore_bankmachine0_sink_ready = soc_litedramcore_bankmachine0_syncfifo0_writable;
assign soc_litedramcore_bankmachine0_syncfifo0_we = soc_litedramcore_bankmachine0_sink_valid;
assign soc_litedramcore_bankmachine0_fifo_in_first = soc_litedramcore_bankmachine0_sink_first;
assign soc_litedramcore_bankmachine0_fifo_in_last = soc_litedramcore_bankmachine0_sink_last;
assign soc_litedramcore_bankmachine0_fifo_in_payload_we = soc_litedramcore_bankmachine0_sink_payload_we;
assign soc_litedramcore_bankmachine0_fifo_in_payload_addr = soc_litedramcore_bankmachine0_sink_payload_addr;
assign soc_litedramcore_bankmachine0_source_valid = soc_litedramcore_bankmachine0_syncfifo0_readable;
assign soc_litedramcore_bankmachine0_source_first = soc_litedramcore_bankmachine0_fifo_out_first;
assign soc_litedramcore_bankmachine0_source_last = soc_litedramcore_bankmachine0_fifo_out_last;
assign soc_litedramcore_bankmachine0_source_payload_we = soc_litedramcore_bankmachine0_fifo_out_payload_we;
assign soc_litedramcore_bankmachine0_source_payload_addr = soc_litedramcore_bankmachine0_fifo_out_payload_addr;
assign soc_litedramcore_bankmachine0_syncfifo0_re = soc_litedramcore_bankmachine0_source_ready;
always @(*) begin
    soc_litedramcore_bankmachine0_wrport_adr <= 4'd0;
    if (soc_litedramcore_bankmachine0_replace) begin
        soc_litedramcore_bankmachine0_wrport_adr <= (soc_litedramcore_bankmachine0_produce - 1'd1);
    end else begin
        soc_litedramcore_bankmachine0_wrport_adr <= soc_litedramcore_bankmachine0_produce;
    end
end
assign soc_litedramcore_bankmachine0_wrport_dat_w = soc_litedramcore_bankmachine0_syncfifo0_din;
assign soc_litedramcore_bankmachine0_wrport_we = (soc_litedramcore_bankmachine0_syncfifo0_we & (soc_litedramcore_bankmachine0_syncfifo0_writable | soc_litedramcore_bankmachine0_replace));
assign soc_litedramcore_bankmachine0_do_read = (soc_litedramcore_bankmachine0_syncfifo0_readable & soc_litedramcore_bankmachine0_syncfifo0_re);
assign soc_litedramcore_bankmachine0_rdport_adr = soc_litedramcore_bankmachine0_consume;
assign soc_litedramcore_bankmachine0_syncfifo0_dout = soc_litedramcore_bankmachine0_rdport_dat_r;
assign soc_litedramcore_bankmachine0_syncfifo0_writable = (soc_litedramcore_bankmachine0_level != 5'd16);
assign soc_litedramcore_bankmachine0_syncfifo0_readable = (soc_litedramcore_bankmachine0_level != 1'd0);
assign soc_litedramcore_bankmachine0_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine0_pipe_valid_source_valid) | soc_litedramcore_bankmachine0_pipe_valid_source_ready);
assign soc_litedramcore_bankmachine0_pipe_valid_sink_valid = soc_litedramcore_bankmachine0_sink_sink_valid;
assign soc_litedramcore_bankmachine0_sink_sink_ready = soc_litedramcore_bankmachine0_pipe_valid_sink_ready;
assign soc_litedramcore_bankmachine0_pipe_valid_sink_first = soc_litedramcore_bankmachine0_sink_sink_first;
assign soc_litedramcore_bankmachine0_pipe_valid_sink_last = soc_litedramcore_bankmachine0_sink_sink_last;
assign soc_litedramcore_bankmachine0_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine0_sink_sink_payload_we;
assign soc_litedramcore_bankmachine0_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine0_sink_sink_payload_addr;
assign soc_litedramcore_bankmachine0_source_source_valid = soc_litedramcore_bankmachine0_pipe_valid_source_valid;
assign soc_litedramcore_bankmachine0_pipe_valid_source_ready = soc_litedramcore_bankmachine0_source_source_ready;
assign soc_litedramcore_bankmachine0_source_source_first = soc_litedramcore_bankmachine0_pipe_valid_source_first;
assign soc_litedramcore_bankmachine0_source_source_last = soc_litedramcore_bankmachine0_pipe_valid_source_last;
assign soc_litedramcore_bankmachine0_source_source_payload_we = soc_litedramcore_bankmachine0_pipe_valid_source_payload_we;
assign soc_litedramcore_bankmachine0_source_source_payload_addr = soc_litedramcore_bankmachine0_pipe_valid_source_payload_addr;
always @(*) begin
    bankmachine0_next_state <= 4'd0;
    bankmachine0_next_state <= bankmachine0_state;
    case (bankmachine0_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
                if (soc_litedramcore_bankmachine0_cmd_ready) begin
                    bankmachine0_next_state <= 3'd5;
                end
            end
        end
        2'd2: begin
            if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
                bankmachine0_next_state <= 3'd5;
            end
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine0_trccon_ready) begin
                if (soc_litedramcore_bankmachine0_cmd_ready) begin
                    bankmachine0_next_state <= 3'd7;
                end
            end
        end
        3'd4: begin
            if ((~soc_litedramcore_bankmachine0_refresh_req)) begin
                bankmachine0_next_state <= 1'd0;
            end
        end
        3'd5: begin
            bankmachine0_next_state <= 3'd6;
        end
        3'd6: begin
            bankmachine0_next_state <= 2'd3;
        end
        3'd7: begin
            bankmachine0_next_state <= 4'd8;
        end
        4'd8: begin
            bankmachine0_next_state <= 1'd0;
        end
        default: begin
            if (soc_litedramcore_bankmachine0_refresh_req) begin
                bankmachine0_next_state <= 3'd4;
            end else begin
                if (soc_litedramcore_bankmachine0_source_source_valid) begin
                    if (soc_litedramcore_bankmachine0_row_opened) begin
                        if (soc_litedramcore_bankmachine0_row_hit) begin
                            if ((soc_litedramcore_bankmachine0_cmd_ready & soc_litedramcore_bankmachine0_auto_precharge)) begin
                                bankmachine0_next_state <= 2'd2;
                            end
                        end else begin
                            bankmachine0_next_state <= 1'd1;
                        end
                    end else begin
                        bankmachine0_next_state <= 2'd3;
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
    case (bankmachine0_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine0_trccon_ready) begin
                soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
    case (bankmachine0_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine0_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine0_source_source_valid) begin
                    if (soc_litedramcore_bankmachine0_row_opened) begin
                        if (soc_litedramcore_bankmachine0_row_hit) begin
                            soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
    case (bankmachine0_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
                soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine0_trccon_ready) begin
                soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
    case (bankmachine0_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
                soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine0_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine0_source_source_valid) begin
                    if (soc_litedramcore_bankmachine0_row_opened) begin
                        if (soc_litedramcore_bankmachine0_row_hit) begin
                            if (soc_litedramcore_bankmachine0_source_source_payload_we) begin
                                soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
    case (bankmachine0_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
                soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine0_trccon_ready) begin
                soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
            end
        end
        3'd4: begin
            soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
    case (bankmachine0_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine0_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine0_source_source_valid) begin
                    if (soc_litedramcore_bankmachine0_row_opened) begin
                        if (soc_litedramcore_bankmachine0_row_hit) begin
                            if (soc_litedramcore_bankmachine0_source_source_payload_we) begin
                            end else begin
                                soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
    case (bankmachine0_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine0_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine0_source_source_valid) begin
                    if (soc_litedramcore_bankmachine0_row_opened) begin
                        if (soc_litedramcore_bankmachine0_row_hit) begin
                            if (soc_litedramcore_bankmachine0_source_source_payload_we) begin
                                soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
    case (bankmachine0_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine0_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine0_source_source_valid) begin
                    if (soc_litedramcore_bankmachine0_row_opened) begin
                        if (soc_litedramcore_bankmachine0_row_hit) begin
                            if (soc_litedramcore_bankmachine0_source_source_payload_we) begin
                                soc_litedramcore_bankmachine0_req_wdata_ready <= soc_litedramcore_bankmachine0_cmd_ready;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
    case (bankmachine0_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine0_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine0_source_source_valid) begin
                    if (soc_litedramcore_bankmachine0_row_opened) begin
                        if (soc_litedramcore_bankmachine0_row_hit) begin
                            if (soc_litedramcore_bankmachine0_source_source_payload_we) begin
                            end else begin
                                soc_litedramcore_bankmachine0_req_rdata_valid <= soc_litedramcore_bankmachine0_cmd_ready;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
    case (bankmachine0_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
            if (soc_litedramcore_bankmachine0_twtpcon_ready) begin
                soc_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
            end
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine0_row_open <= 1'd0;
    case (bankmachine0_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine0_trccon_ready) begin
                soc_litedramcore_bankmachine0_row_open <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine0_cmd_valid <= 1'd0;
    case (bankmachine0_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
                soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine0_trccon_ready) begin
                soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine0_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine0_source_source_valid) begin
                    if (soc_litedramcore_bankmachine0_row_opened) begin
                        if (soc_litedramcore_bankmachine0_row_hit) begin
                            soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine0_row_close <= 1'd0;
    case (bankmachine0_state)
        1'd1: begin
            soc_litedramcore_bankmachine0_row_close <= 1'd1;
        end
        2'd2: begin
            soc_litedramcore_bankmachine0_row_close <= 1'd1;
        end
        2'd3: begin
        end
        3'd4: begin
            soc_litedramcore_bankmachine0_row_close <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
assign soc_litedramcore_bankmachine1_sink_valid = soc_litedramcore_bankmachine1_req_valid;
assign soc_litedramcore_bankmachine1_req_ready = soc_litedramcore_bankmachine1_sink_ready;
assign soc_litedramcore_bankmachine1_sink_payload_we = soc_litedramcore_bankmachine1_req_we;
assign soc_litedramcore_bankmachine1_sink_payload_addr = soc_litedramcore_bankmachine1_req_addr;
assign soc_litedramcore_bankmachine1_sink_sink_valid = soc_litedramcore_bankmachine1_source_valid;
assign soc_litedramcore_bankmachine1_source_ready = soc_litedramcore_bankmachine1_sink_sink_ready;
assign soc_litedramcore_bankmachine1_sink_sink_first = soc_litedramcore_bankmachine1_source_first;
assign soc_litedramcore_bankmachine1_sink_sink_last = soc_litedramcore_bankmachine1_source_last;
assign soc_litedramcore_bankmachine1_sink_sink_payload_we = soc_litedramcore_bankmachine1_source_payload_we;
assign soc_litedramcore_bankmachine1_sink_sink_payload_addr = soc_litedramcore_bankmachine1_source_payload_addr;
assign soc_litedramcore_bankmachine1_source_source_ready = (soc_litedramcore_bankmachine1_req_wdata_ready | soc_litedramcore_bankmachine1_req_rdata_valid);
assign soc_litedramcore_bankmachine1_req_lock = (soc_litedramcore_bankmachine1_source_valid | soc_litedramcore_bankmachine1_source_source_valid);
assign soc_litedramcore_bankmachine1_row_hit = (soc_litedramcore_bankmachine1_row == soc_litedramcore_bankmachine1_source_source_payload_addr[20:7]);
assign soc_litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
always @(*) begin
    soc_litedramcore_bankmachine1_cmd_payload_a <= 14'd0;
    if (soc_litedramcore_bankmachine1_row_col_n_addr_sel) begin
        soc_litedramcore_bankmachine1_cmd_payload_a <= soc_litedramcore_bankmachine1_source_source_payload_addr[20:7];
    end else begin
        soc_litedramcore_bankmachine1_cmd_payload_a <= ((soc_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}});
    end
end
assign soc_litedramcore_bankmachine1_twtpcon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_cmd_payload_is_write);
assign soc_litedramcore_bankmachine1_trccon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open);
assign soc_litedramcore_bankmachine1_trascon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open);
always @(*) begin
    soc_litedramcore_bankmachine1_auto_precharge <= 1'd0;
    if ((soc_litedramcore_bankmachine1_source_valid & soc_litedramcore_bankmachine1_source_source_valid)) begin
        if ((soc_litedramcore_bankmachine1_source_payload_addr[20:7] != soc_litedramcore_bankmachine1_source_source_payload_addr[20:7])) begin
            soc_litedramcore_bankmachine1_auto_precharge <= (soc_litedramcore_bankmachine1_row_close == 1'd0);
        end
    end
end
assign soc_litedramcore_bankmachine1_syncfifo1_din = {soc_litedramcore_bankmachine1_fifo_in_last, soc_litedramcore_bankmachine1_fifo_in_first, soc_litedramcore_bankmachine1_fifo_in_payload_addr, soc_litedramcore_bankmachine1_fifo_in_payload_we};
assign {soc_litedramcore_bankmachine1_fifo_out_last, soc_litedramcore_bankmachine1_fifo_out_first, soc_litedramcore_bankmachine1_fifo_out_payload_addr, soc_litedramcore_bankmachine1_fifo_out_payload_we} = soc_litedramcore_bankmachine1_syncfifo1_dout;
assign {soc_litedramcore_bankmachine1_fifo_out_last, soc_litedramcore_bankmachine1_fifo_out_first, soc_litedramcore_bankmachine1_fifo_out_payload_addr, soc_litedramcore_bankmachine1_fifo_out_payload_we} = soc_litedramcore_bankmachine1_syncfifo1_dout;
assign {soc_litedramcore_bankmachine1_fifo_out_last, soc_litedramcore_bankmachine1_fifo_out_first, soc_litedramcore_bankmachine1_fifo_out_payload_addr, soc_litedramcore_bankmachine1_fifo_out_payload_we} = soc_litedramcore_bankmachine1_syncfifo1_dout;
assign {soc_litedramcore_bankmachine1_fifo_out_last, soc_litedramcore_bankmachine1_fifo_out_first, soc_litedramcore_bankmachine1_fifo_out_payload_addr, soc_litedramcore_bankmachine1_fifo_out_payload_we} = soc_litedramcore_bankmachine1_syncfifo1_dout;
assign soc_litedramcore_bankmachine1_sink_ready = soc_litedramcore_bankmachine1_syncfifo1_writable;
assign soc_litedramcore_bankmachine1_syncfifo1_we = soc_litedramcore_bankmachine1_sink_valid;
assign soc_litedramcore_bankmachine1_fifo_in_first = soc_litedramcore_bankmachine1_sink_first;
assign soc_litedramcore_bankmachine1_fifo_in_last = soc_litedramcore_bankmachine1_sink_last;
assign soc_litedramcore_bankmachine1_fifo_in_payload_we = soc_litedramcore_bankmachine1_sink_payload_we;
assign soc_litedramcore_bankmachine1_fifo_in_payload_addr = soc_litedramcore_bankmachine1_sink_payload_addr;
assign soc_litedramcore_bankmachine1_source_valid = soc_litedramcore_bankmachine1_syncfifo1_readable;
assign soc_litedramcore_bankmachine1_source_first = soc_litedramcore_bankmachine1_fifo_out_first;
assign soc_litedramcore_bankmachine1_source_last = soc_litedramcore_bankmachine1_fifo_out_last;
assign soc_litedramcore_bankmachine1_source_payload_we = soc_litedramcore_bankmachine1_fifo_out_payload_we;
assign soc_litedramcore_bankmachine1_source_payload_addr = soc_litedramcore_bankmachine1_fifo_out_payload_addr;
assign soc_litedramcore_bankmachine1_syncfifo1_re = soc_litedramcore_bankmachine1_source_ready;
always @(*) begin
    soc_litedramcore_bankmachine1_wrport_adr <= 4'd0;
    if (soc_litedramcore_bankmachine1_replace) begin
        soc_litedramcore_bankmachine1_wrport_adr <= (soc_litedramcore_bankmachine1_produce - 1'd1);
    end else begin
        soc_litedramcore_bankmachine1_wrport_adr <= soc_litedramcore_bankmachine1_produce;
    end
end
assign soc_litedramcore_bankmachine1_wrport_dat_w = soc_litedramcore_bankmachine1_syncfifo1_din;
assign soc_litedramcore_bankmachine1_wrport_we = (soc_litedramcore_bankmachine1_syncfifo1_we & (soc_litedramcore_bankmachine1_syncfifo1_writable | soc_litedramcore_bankmachine1_replace));
assign soc_litedramcore_bankmachine1_do_read = (soc_litedramcore_bankmachine1_syncfifo1_readable & soc_litedramcore_bankmachine1_syncfifo1_re);
assign soc_litedramcore_bankmachine1_rdport_adr = soc_litedramcore_bankmachine1_consume;
assign soc_litedramcore_bankmachine1_syncfifo1_dout = soc_litedramcore_bankmachine1_rdport_dat_r;
assign soc_litedramcore_bankmachine1_syncfifo1_writable = (soc_litedramcore_bankmachine1_level != 5'd16);
assign soc_litedramcore_bankmachine1_syncfifo1_readable = (soc_litedramcore_bankmachine1_level != 1'd0);
assign soc_litedramcore_bankmachine1_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine1_pipe_valid_source_valid) | soc_litedramcore_bankmachine1_pipe_valid_source_ready);
assign soc_litedramcore_bankmachine1_pipe_valid_sink_valid = soc_litedramcore_bankmachine1_sink_sink_valid;
assign soc_litedramcore_bankmachine1_sink_sink_ready = soc_litedramcore_bankmachine1_pipe_valid_sink_ready;
assign soc_litedramcore_bankmachine1_pipe_valid_sink_first = soc_litedramcore_bankmachine1_sink_sink_first;
assign soc_litedramcore_bankmachine1_pipe_valid_sink_last = soc_litedramcore_bankmachine1_sink_sink_last;
assign soc_litedramcore_bankmachine1_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine1_sink_sink_payload_we;
assign soc_litedramcore_bankmachine1_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine1_sink_sink_payload_addr;
assign soc_litedramcore_bankmachine1_source_source_valid = soc_litedramcore_bankmachine1_pipe_valid_source_valid;
assign soc_litedramcore_bankmachine1_pipe_valid_source_ready = soc_litedramcore_bankmachine1_source_source_ready;
assign soc_litedramcore_bankmachine1_source_source_first = soc_litedramcore_bankmachine1_pipe_valid_source_first;
assign soc_litedramcore_bankmachine1_source_source_last = soc_litedramcore_bankmachine1_pipe_valid_source_last;
assign soc_litedramcore_bankmachine1_source_source_payload_we = soc_litedramcore_bankmachine1_pipe_valid_source_payload_we;
assign soc_litedramcore_bankmachine1_source_source_payload_addr = soc_litedramcore_bankmachine1_pipe_valid_source_payload_addr;
always @(*) begin
    bankmachine1_next_state <= 4'd0;
    bankmachine1_next_state <= bankmachine1_state;
    case (bankmachine1_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
                if (soc_litedramcore_bankmachine1_cmd_ready) begin
                    bankmachine1_next_state <= 3'd5;
                end
            end
        end
        2'd2: begin
            if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
                bankmachine1_next_state <= 3'd5;
            end
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine1_trccon_ready) begin
                if (soc_litedramcore_bankmachine1_cmd_ready) begin
                    bankmachine1_next_state <= 3'd7;
                end
            end
        end
        3'd4: begin
            if ((~soc_litedramcore_bankmachine1_refresh_req)) begin
                bankmachine1_next_state <= 1'd0;
            end
        end
        3'd5: begin
            bankmachine1_next_state <= 3'd6;
        end
        3'd6: begin
            bankmachine1_next_state <= 2'd3;
        end
        3'd7: begin
            bankmachine1_next_state <= 4'd8;
        end
        4'd8: begin
            bankmachine1_next_state <= 1'd0;
        end
        default: begin
            if (soc_litedramcore_bankmachine1_refresh_req) begin
                bankmachine1_next_state <= 3'd4;
            end else begin
                if (soc_litedramcore_bankmachine1_source_source_valid) begin
                    if (soc_litedramcore_bankmachine1_row_opened) begin
                        if (soc_litedramcore_bankmachine1_row_hit) begin
                            if ((soc_litedramcore_bankmachine1_cmd_ready & soc_litedramcore_bankmachine1_auto_precharge)) begin
                                bankmachine1_next_state <= 2'd2;
                            end
                        end else begin
                            bankmachine1_next_state <= 1'd1;
                        end
                    end else begin
                        bankmachine1_next_state <= 2'd3;
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
    case (bankmachine1_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
                soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine1_trccon_ready) begin
                soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
    case (bankmachine1_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
                soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine1_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine1_source_source_valid) begin
                    if (soc_litedramcore_bankmachine1_row_opened) begin
                        if (soc_litedramcore_bankmachine1_row_hit) begin
                            if (soc_litedramcore_bankmachine1_source_source_payload_we) begin
                                soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
    case (bankmachine1_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
                soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine1_trccon_ready) begin
                soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
            end
        end
        3'd4: begin
            soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
    case (bankmachine1_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine1_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine1_source_source_valid) begin
                    if (soc_litedramcore_bankmachine1_row_opened) begin
                        if (soc_litedramcore_bankmachine1_row_hit) begin
                            if (soc_litedramcore_bankmachine1_source_source_payload_we) begin
                            end else begin
                                soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
    case (bankmachine1_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine1_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine1_source_source_valid) begin
                    if (soc_litedramcore_bankmachine1_row_opened) begin
                        if (soc_litedramcore_bankmachine1_row_hit) begin
                            if (soc_litedramcore_bankmachine1_source_source_payload_we) begin
                                soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
    case (bankmachine1_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine1_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine1_source_source_valid) begin
                    if (soc_litedramcore_bankmachine1_row_opened) begin
                        if (soc_litedramcore_bankmachine1_row_hit) begin
                            if (soc_litedramcore_bankmachine1_source_source_payload_we) begin
                                soc_litedramcore_bankmachine1_req_wdata_ready <= soc_litedramcore_bankmachine1_cmd_ready;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
    case (bankmachine1_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine1_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine1_source_source_valid) begin
                    if (soc_litedramcore_bankmachine1_row_opened) begin
                        if (soc_litedramcore_bankmachine1_row_hit) begin
                            if (soc_litedramcore_bankmachine1_source_source_payload_we) begin
                            end else begin
                                soc_litedramcore_bankmachine1_req_rdata_valid <= soc_litedramcore_bankmachine1_cmd_ready;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
    case (bankmachine1_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
            if (soc_litedramcore_bankmachine1_twtpcon_ready) begin
                soc_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
            end
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine1_row_open <= 1'd0;
    case (bankmachine1_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine1_trccon_ready) begin
                soc_litedramcore_bankmachine1_row_open <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine1_cmd_valid <= 1'd0;
    case (bankmachine1_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
                soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine1_trccon_ready) begin
                soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine1_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine1_source_source_valid) begin
                    if (soc_litedramcore_bankmachine1_row_opened) begin
                        if (soc_litedramcore_bankmachine1_row_hit) begin
                            soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine1_row_close <= 1'd0;
    case (bankmachine1_state)
        1'd1: begin
            soc_litedramcore_bankmachine1_row_close <= 1'd1;
        end
        2'd2: begin
            soc_litedramcore_bankmachine1_row_close <= 1'd1;
        end
        2'd3: begin
        end
        3'd4: begin
            soc_litedramcore_bankmachine1_row_close <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
    case (bankmachine1_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine1_trccon_ready) begin
                soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
    case (bankmachine1_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine1_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine1_source_source_valid) begin
                    if (soc_litedramcore_bankmachine1_row_opened) begin
                        if (soc_litedramcore_bankmachine1_row_hit) begin
                            soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
assign soc_litedramcore_bankmachine2_sink_valid = soc_litedramcore_bankmachine2_req_valid;
assign soc_litedramcore_bankmachine2_req_ready = soc_litedramcore_bankmachine2_sink_ready;
assign soc_litedramcore_bankmachine2_sink_payload_we = soc_litedramcore_bankmachine2_req_we;
assign soc_litedramcore_bankmachine2_sink_payload_addr = soc_litedramcore_bankmachine2_req_addr;
assign soc_litedramcore_bankmachine2_sink_sink_valid = soc_litedramcore_bankmachine2_source_valid;
assign soc_litedramcore_bankmachine2_source_ready = soc_litedramcore_bankmachine2_sink_sink_ready;
assign soc_litedramcore_bankmachine2_sink_sink_first = soc_litedramcore_bankmachine2_source_first;
assign soc_litedramcore_bankmachine2_sink_sink_last = soc_litedramcore_bankmachine2_source_last;
assign soc_litedramcore_bankmachine2_sink_sink_payload_we = soc_litedramcore_bankmachine2_source_payload_we;
assign soc_litedramcore_bankmachine2_sink_sink_payload_addr = soc_litedramcore_bankmachine2_source_payload_addr;
assign soc_litedramcore_bankmachine2_source_source_ready = (soc_litedramcore_bankmachine2_req_wdata_ready | soc_litedramcore_bankmachine2_req_rdata_valid);
assign soc_litedramcore_bankmachine2_req_lock = (soc_litedramcore_bankmachine2_source_valid | soc_litedramcore_bankmachine2_source_source_valid);
assign soc_litedramcore_bankmachine2_row_hit = (soc_litedramcore_bankmachine2_row == soc_litedramcore_bankmachine2_source_source_payload_addr[20:7]);
assign soc_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
always @(*) begin
    soc_litedramcore_bankmachine2_cmd_payload_a <= 14'd0;
    if (soc_litedramcore_bankmachine2_row_col_n_addr_sel) begin
        soc_litedramcore_bankmachine2_cmd_payload_a <= soc_litedramcore_bankmachine2_source_source_payload_addr[20:7];
    end else begin
        soc_litedramcore_bankmachine2_cmd_payload_a <= ((soc_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}});
    end
end
assign soc_litedramcore_bankmachine2_twtpcon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_cmd_payload_is_write);
assign soc_litedramcore_bankmachine2_trccon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open);
assign soc_litedramcore_bankmachine2_trascon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open);
always @(*) begin
    soc_litedramcore_bankmachine2_auto_precharge <= 1'd0;
    if ((soc_litedramcore_bankmachine2_source_valid & soc_litedramcore_bankmachine2_source_source_valid)) begin
        if ((soc_litedramcore_bankmachine2_source_payload_addr[20:7] != soc_litedramcore_bankmachine2_source_source_payload_addr[20:7])) begin
            soc_litedramcore_bankmachine2_auto_precharge <= (soc_litedramcore_bankmachine2_row_close == 1'd0);
        end
    end
end
assign soc_litedramcore_bankmachine2_syncfifo2_din = {soc_litedramcore_bankmachine2_fifo_in_last, soc_litedramcore_bankmachine2_fifo_in_first, soc_litedramcore_bankmachine2_fifo_in_payload_addr, soc_litedramcore_bankmachine2_fifo_in_payload_we};
assign {soc_litedramcore_bankmachine2_fifo_out_last, soc_litedramcore_bankmachine2_fifo_out_first, soc_litedramcore_bankmachine2_fifo_out_payload_addr, soc_litedramcore_bankmachine2_fifo_out_payload_we} = soc_litedramcore_bankmachine2_syncfifo2_dout;
assign {soc_litedramcore_bankmachine2_fifo_out_last, soc_litedramcore_bankmachine2_fifo_out_first, soc_litedramcore_bankmachine2_fifo_out_payload_addr, soc_litedramcore_bankmachine2_fifo_out_payload_we} = soc_litedramcore_bankmachine2_syncfifo2_dout;
assign {soc_litedramcore_bankmachine2_fifo_out_last, soc_litedramcore_bankmachine2_fifo_out_first, soc_litedramcore_bankmachine2_fifo_out_payload_addr, soc_litedramcore_bankmachine2_fifo_out_payload_we} = soc_litedramcore_bankmachine2_syncfifo2_dout;
assign {soc_litedramcore_bankmachine2_fifo_out_last, soc_litedramcore_bankmachine2_fifo_out_first, soc_litedramcore_bankmachine2_fifo_out_payload_addr, soc_litedramcore_bankmachine2_fifo_out_payload_we} = soc_litedramcore_bankmachine2_syncfifo2_dout;
assign soc_litedramcore_bankmachine2_sink_ready = soc_litedramcore_bankmachine2_syncfifo2_writable;
assign soc_litedramcore_bankmachine2_syncfifo2_we = soc_litedramcore_bankmachine2_sink_valid;
assign soc_litedramcore_bankmachine2_fifo_in_first = soc_litedramcore_bankmachine2_sink_first;
assign soc_litedramcore_bankmachine2_fifo_in_last = soc_litedramcore_bankmachine2_sink_last;
assign soc_litedramcore_bankmachine2_fifo_in_payload_we = soc_litedramcore_bankmachine2_sink_payload_we;
assign soc_litedramcore_bankmachine2_fifo_in_payload_addr = soc_litedramcore_bankmachine2_sink_payload_addr;
assign soc_litedramcore_bankmachine2_source_valid = soc_litedramcore_bankmachine2_syncfifo2_readable;
assign soc_litedramcore_bankmachine2_source_first = soc_litedramcore_bankmachine2_fifo_out_first;
assign soc_litedramcore_bankmachine2_source_last = soc_litedramcore_bankmachine2_fifo_out_last;
assign soc_litedramcore_bankmachine2_source_payload_we = soc_litedramcore_bankmachine2_fifo_out_payload_we;
assign soc_litedramcore_bankmachine2_source_payload_addr = soc_litedramcore_bankmachine2_fifo_out_payload_addr;
assign soc_litedramcore_bankmachine2_syncfifo2_re = soc_litedramcore_bankmachine2_source_ready;
always @(*) begin
    soc_litedramcore_bankmachine2_wrport_adr <= 4'd0;
    if (soc_litedramcore_bankmachine2_replace) begin
        soc_litedramcore_bankmachine2_wrport_adr <= (soc_litedramcore_bankmachine2_produce - 1'd1);
    end else begin
        soc_litedramcore_bankmachine2_wrport_adr <= soc_litedramcore_bankmachine2_produce;
    end
end
assign soc_litedramcore_bankmachine2_wrport_dat_w = soc_litedramcore_bankmachine2_syncfifo2_din;
assign soc_litedramcore_bankmachine2_wrport_we = (soc_litedramcore_bankmachine2_syncfifo2_we & (soc_litedramcore_bankmachine2_syncfifo2_writable | soc_litedramcore_bankmachine2_replace));
assign soc_litedramcore_bankmachine2_do_read = (soc_litedramcore_bankmachine2_syncfifo2_readable & soc_litedramcore_bankmachine2_syncfifo2_re);
assign soc_litedramcore_bankmachine2_rdport_adr = soc_litedramcore_bankmachine2_consume;
assign soc_litedramcore_bankmachine2_syncfifo2_dout = soc_litedramcore_bankmachine2_rdport_dat_r;
assign soc_litedramcore_bankmachine2_syncfifo2_writable = (soc_litedramcore_bankmachine2_level != 5'd16);
assign soc_litedramcore_bankmachine2_syncfifo2_readable = (soc_litedramcore_bankmachine2_level != 1'd0);
assign soc_litedramcore_bankmachine2_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine2_pipe_valid_source_valid) | soc_litedramcore_bankmachine2_pipe_valid_source_ready);
assign soc_litedramcore_bankmachine2_pipe_valid_sink_valid = soc_litedramcore_bankmachine2_sink_sink_valid;
assign soc_litedramcore_bankmachine2_sink_sink_ready = soc_litedramcore_bankmachine2_pipe_valid_sink_ready;
assign soc_litedramcore_bankmachine2_pipe_valid_sink_first = soc_litedramcore_bankmachine2_sink_sink_first;
assign soc_litedramcore_bankmachine2_pipe_valid_sink_last = soc_litedramcore_bankmachine2_sink_sink_last;
assign soc_litedramcore_bankmachine2_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine2_sink_sink_payload_we;
assign soc_litedramcore_bankmachine2_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine2_sink_sink_payload_addr;
assign soc_litedramcore_bankmachine2_source_source_valid = soc_litedramcore_bankmachine2_pipe_valid_source_valid;
assign soc_litedramcore_bankmachine2_pipe_valid_source_ready = soc_litedramcore_bankmachine2_source_source_ready;
assign soc_litedramcore_bankmachine2_source_source_first = soc_litedramcore_bankmachine2_pipe_valid_source_first;
assign soc_litedramcore_bankmachine2_source_source_last = soc_litedramcore_bankmachine2_pipe_valid_source_last;
assign soc_litedramcore_bankmachine2_source_source_payload_we = soc_litedramcore_bankmachine2_pipe_valid_source_payload_we;
assign soc_litedramcore_bankmachine2_source_source_payload_addr = soc_litedramcore_bankmachine2_pipe_valid_source_payload_addr;
always @(*) begin
    bankmachine2_next_state <= 4'd0;
    bankmachine2_next_state <= bankmachine2_state;
    case (bankmachine2_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
                if (soc_litedramcore_bankmachine2_cmd_ready) begin
                    bankmachine2_next_state <= 3'd5;
                end
            end
        end
        2'd2: begin
            if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
                bankmachine2_next_state <= 3'd5;
            end
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine2_trccon_ready) begin
                if (soc_litedramcore_bankmachine2_cmd_ready) begin
                    bankmachine2_next_state <= 3'd7;
                end
            end
        end
        3'd4: begin
            if ((~soc_litedramcore_bankmachine2_refresh_req)) begin
                bankmachine2_next_state <= 1'd0;
            end
        end
        3'd5: begin
            bankmachine2_next_state <= 3'd6;
        end
        3'd6: begin
            bankmachine2_next_state <= 2'd3;
        end
        3'd7: begin
            bankmachine2_next_state <= 4'd8;
        end
        4'd8: begin
            bankmachine2_next_state <= 1'd0;
        end
        default: begin
            if (soc_litedramcore_bankmachine2_refresh_req) begin
                bankmachine2_next_state <= 3'd4;
            end else begin
                if (soc_litedramcore_bankmachine2_source_source_valid) begin
                    if (soc_litedramcore_bankmachine2_row_opened) begin
                        if (soc_litedramcore_bankmachine2_row_hit) begin
                            if ((soc_litedramcore_bankmachine2_cmd_ready & soc_litedramcore_bankmachine2_auto_precharge)) begin
                                bankmachine2_next_state <= 2'd2;
                            end
                        end else begin
                            bankmachine2_next_state <= 1'd1;
                        end
                    end else begin
                        bankmachine2_next_state <= 2'd3;
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
    case (bankmachine2_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine2_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine2_source_source_valid) begin
                    if (soc_litedramcore_bankmachine2_row_opened) begin
                        if (soc_litedramcore_bankmachine2_row_hit) begin
                            if (soc_litedramcore_bankmachine2_source_source_payload_we) begin
                                soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
    case (bankmachine2_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine2_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine2_source_source_valid) begin
                    if (soc_litedramcore_bankmachine2_row_opened) begin
                        if (soc_litedramcore_bankmachine2_row_hit) begin
                            if (soc_litedramcore_bankmachine2_source_source_payload_we) begin
                                soc_litedramcore_bankmachine2_req_wdata_ready <= soc_litedramcore_bankmachine2_cmd_ready;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
    case (bankmachine2_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine2_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine2_source_source_valid) begin
                    if (soc_litedramcore_bankmachine2_row_opened) begin
                        if (soc_litedramcore_bankmachine2_row_hit) begin
                            if (soc_litedramcore_bankmachine2_source_source_payload_we) begin
                            end else begin
                                soc_litedramcore_bankmachine2_req_rdata_valid <= soc_litedramcore_bankmachine2_cmd_ready;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
    case (bankmachine2_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
            if (soc_litedramcore_bankmachine2_twtpcon_ready) begin
                soc_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
            end
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine2_row_open <= 1'd0;
    case (bankmachine2_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine2_trccon_ready) begin
                soc_litedramcore_bankmachine2_row_open <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine2_cmd_valid <= 1'd0;
    case (bankmachine2_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
                soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine2_trccon_ready) begin
                soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine2_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine2_source_source_valid) begin
                    if (soc_litedramcore_bankmachine2_row_opened) begin
                        if (soc_litedramcore_bankmachine2_row_hit) begin
                            soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine2_row_close <= 1'd0;
    case (bankmachine2_state)
        1'd1: begin
            soc_litedramcore_bankmachine2_row_close <= 1'd1;
        end
        2'd2: begin
            soc_litedramcore_bankmachine2_row_close <= 1'd1;
        end
        2'd3: begin
        end
        3'd4: begin
            soc_litedramcore_bankmachine2_row_close <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
    case (bankmachine2_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine2_trccon_ready) begin
                soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
    case (bankmachine2_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine2_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine2_source_source_valid) begin
                    if (soc_litedramcore_bankmachine2_row_opened) begin
                        if (soc_litedramcore_bankmachine2_row_hit) begin
                            soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
    case (bankmachine2_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
                soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine2_trccon_ready) begin
                soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
    case (bankmachine2_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
                soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine2_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine2_source_source_valid) begin
                    if (soc_litedramcore_bankmachine2_row_opened) begin
                        if (soc_litedramcore_bankmachine2_row_hit) begin
                            if (soc_litedramcore_bankmachine2_source_source_payload_we) begin
                                soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
    case (bankmachine2_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
                soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine2_trccon_ready) begin
                soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
            end
        end
        3'd4: begin
            soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
    case (bankmachine2_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine2_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine2_source_source_valid) begin
                    if (soc_litedramcore_bankmachine2_row_opened) begin
                        if (soc_litedramcore_bankmachine2_row_hit) begin
                            if (soc_litedramcore_bankmachine2_source_source_payload_we) begin
                            end else begin
                                soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
assign soc_litedramcore_bankmachine3_sink_valid = soc_litedramcore_bankmachine3_req_valid;
assign soc_litedramcore_bankmachine3_req_ready = soc_litedramcore_bankmachine3_sink_ready;
assign soc_litedramcore_bankmachine3_sink_payload_we = soc_litedramcore_bankmachine3_req_we;
assign soc_litedramcore_bankmachine3_sink_payload_addr = soc_litedramcore_bankmachine3_req_addr;
assign soc_litedramcore_bankmachine3_sink_sink_valid = soc_litedramcore_bankmachine3_source_valid;
assign soc_litedramcore_bankmachine3_source_ready = soc_litedramcore_bankmachine3_sink_sink_ready;
assign soc_litedramcore_bankmachine3_sink_sink_first = soc_litedramcore_bankmachine3_source_first;
assign soc_litedramcore_bankmachine3_sink_sink_last = soc_litedramcore_bankmachine3_source_last;
assign soc_litedramcore_bankmachine3_sink_sink_payload_we = soc_litedramcore_bankmachine3_source_payload_we;
assign soc_litedramcore_bankmachine3_sink_sink_payload_addr = soc_litedramcore_bankmachine3_source_payload_addr;
assign soc_litedramcore_bankmachine3_source_source_ready = (soc_litedramcore_bankmachine3_req_wdata_ready | soc_litedramcore_bankmachine3_req_rdata_valid);
assign soc_litedramcore_bankmachine3_req_lock = (soc_litedramcore_bankmachine3_source_valid | soc_litedramcore_bankmachine3_source_source_valid);
assign soc_litedramcore_bankmachine3_row_hit = (soc_litedramcore_bankmachine3_row == soc_litedramcore_bankmachine3_source_source_payload_addr[20:7]);
assign soc_litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
always @(*) begin
    soc_litedramcore_bankmachine3_cmd_payload_a <= 14'd0;
    if (soc_litedramcore_bankmachine3_row_col_n_addr_sel) begin
        soc_litedramcore_bankmachine3_cmd_payload_a <= soc_litedramcore_bankmachine3_source_source_payload_addr[20:7];
    end else begin
        soc_litedramcore_bankmachine3_cmd_payload_a <= ((soc_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}});
    end
end
assign soc_litedramcore_bankmachine3_twtpcon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_cmd_payload_is_write);
assign soc_litedramcore_bankmachine3_trccon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open);
assign soc_litedramcore_bankmachine3_trascon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open);
always @(*) begin
    soc_litedramcore_bankmachine3_auto_precharge <= 1'd0;
    if ((soc_litedramcore_bankmachine3_source_valid & soc_litedramcore_bankmachine3_source_source_valid)) begin
        if ((soc_litedramcore_bankmachine3_source_payload_addr[20:7] != soc_litedramcore_bankmachine3_source_source_payload_addr[20:7])) begin
            soc_litedramcore_bankmachine3_auto_precharge <= (soc_litedramcore_bankmachine3_row_close == 1'd0);
        end
    end
end
assign soc_litedramcore_bankmachine3_syncfifo3_din = {soc_litedramcore_bankmachine3_fifo_in_last, soc_litedramcore_bankmachine3_fifo_in_first, soc_litedramcore_bankmachine3_fifo_in_payload_addr, soc_litedramcore_bankmachine3_fifo_in_payload_we};
assign {soc_litedramcore_bankmachine3_fifo_out_last, soc_litedramcore_bankmachine3_fifo_out_first, soc_litedramcore_bankmachine3_fifo_out_payload_addr, soc_litedramcore_bankmachine3_fifo_out_payload_we} = soc_litedramcore_bankmachine3_syncfifo3_dout;
assign {soc_litedramcore_bankmachine3_fifo_out_last, soc_litedramcore_bankmachine3_fifo_out_first, soc_litedramcore_bankmachine3_fifo_out_payload_addr, soc_litedramcore_bankmachine3_fifo_out_payload_we} = soc_litedramcore_bankmachine3_syncfifo3_dout;
assign {soc_litedramcore_bankmachine3_fifo_out_last, soc_litedramcore_bankmachine3_fifo_out_first, soc_litedramcore_bankmachine3_fifo_out_payload_addr, soc_litedramcore_bankmachine3_fifo_out_payload_we} = soc_litedramcore_bankmachine3_syncfifo3_dout;
assign {soc_litedramcore_bankmachine3_fifo_out_last, soc_litedramcore_bankmachine3_fifo_out_first, soc_litedramcore_bankmachine3_fifo_out_payload_addr, soc_litedramcore_bankmachine3_fifo_out_payload_we} = soc_litedramcore_bankmachine3_syncfifo3_dout;
assign soc_litedramcore_bankmachine3_sink_ready = soc_litedramcore_bankmachine3_syncfifo3_writable;
assign soc_litedramcore_bankmachine3_syncfifo3_we = soc_litedramcore_bankmachine3_sink_valid;
assign soc_litedramcore_bankmachine3_fifo_in_first = soc_litedramcore_bankmachine3_sink_first;
assign soc_litedramcore_bankmachine3_fifo_in_last = soc_litedramcore_bankmachine3_sink_last;
assign soc_litedramcore_bankmachine3_fifo_in_payload_we = soc_litedramcore_bankmachine3_sink_payload_we;
assign soc_litedramcore_bankmachine3_fifo_in_payload_addr = soc_litedramcore_bankmachine3_sink_payload_addr;
assign soc_litedramcore_bankmachine3_source_valid = soc_litedramcore_bankmachine3_syncfifo3_readable;
assign soc_litedramcore_bankmachine3_source_first = soc_litedramcore_bankmachine3_fifo_out_first;
assign soc_litedramcore_bankmachine3_source_last = soc_litedramcore_bankmachine3_fifo_out_last;
assign soc_litedramcore_bankmachine3_source_payload_we = soc_litedramcore_bankmachine3_fifo_out_payload_we;
assign soc_litedramcore_bankmachine3_source_payload_addr = soc_litedramcore_bankmachine3_fifo_out_payload_addr;
assign soc_litedramcore_bankmachine3_syncfifo3_re = soc_litedramcore_bankmachine3_source_ready;
always @(*) begin
    soc_litedramcore_bankmachine3_wrport_adr <= 4'd0;
    if (soc_litedramcore_bankmachine3_replace) begin
        soc_litedramcore_bankmachine3_wrport_adr <= (soc_litedramcore_bankmachine3_produce - 1'd1);
    end else begin
        soc_litedramcore_bankmachine3_wrport_adr <= soc_litedramcore_bankmachine3_produce;
    end
end
assign soc_litedramcore_bankmachine3_wrport_dat_w = soc_litedramcore_bankmachine3_syncfifo3_din;
assign soc_litedramcore_bankmachine3_wrport_we = (soc_litedramcore_bankmachine3_syncfifo3_we & (soc_litedramcore_bankmachine3_syncfifo3_writable | soc_litedramcore_bankmachine3_replace));
assign soc_litedramcore_bankmachine3_do_read = (soc_litedramcore_bankmachine3_syncfifo3_readable & soc_litedramcore_bankmachine3_syncfifo3_re);
assign soc_litedramcore_bankmachine3_rdport_adr = soc_litedramcore_bankmachine3_consume;
assign soc_litedramcore_bankmachine3_syncfifo3_dout = soc_litedramcore_bankmachine3_rdport_dat_r;
assign soc_litedramcore_bankmachine3_syncfifo3_writable = (soc_litedramcore_bankmachine3_level != 5'd16);
assign soc_litedramcore_bankmachine3_syncfifo3_readable = (soc_litedramcore_bankmachine3_level != 1'd0);
assign soc_litedramcore_bankmachine3_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine3_pipe_valid_source_valid) | soc_litedramcore_bankmachine3_pipe_valid_source_ready);
assign soc_litedramcore_bankmachine3_pipe_valid_sink_valid = soc_litedramcore_bankmachine3_sink_sink_valid;
assign soc_litedramcore_bankmachine3_sink_sink_ready = soc_litedramcore_bankmachine3_pipe_valid_sink_ready;
assign soc_litedramcore_bankmachine3_pipe_valid_sink_first = soc_litedramcore_bankmachine3_sink_sink_first;
assign soc_litedramcore_bankmachine3_pipe_valid_sink_last = soc_litedramcore_bankmachine3_sink_sink_last;
assign soc_litedramcore_bankmachine3_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine3_sink_sink_payload_we;
assign soc_litedramcore_bankmachine3_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine3_sink_sink_payload_addr;
assign soc_litedramcore_bankmachine3_source_source_valid = soc_litedramcore_bankmachine3_pipe_valid_source_valid;
assign soc_litedramcore_bankmachine3_pipe_valid_source_ready = soc_litedramcore_bankmachine3_source_source_ready;
assign soc_litedramcore_bankmachine3_source_source_first = soc_litedramcore_bankmachine3_pipe_valid_source_first;
assign soc_litedramcore_bankmachine3_source_source_last = soc_litedramcore_bankmachine3_pipe_valid_source_last;
assign soc_litedramcore_bankmachine3_source_source_payload_we = soc_litedramcore_bankmachine3_pipe_valid_source_payload_we;
assign soc_litedramcore_bankmachine3_source_source_payload_addr = soc_litedramcore_bankmachine3_pipe_valid_source_payload_addr;
always @(*) begin
    bankmachine3_next_state <= 4'd0;
    bankmachine3_next_state <= bankmachine3_state;
    case (bankmachine3_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
                if (soc_litedramcore_bankmachine3_cmd_ready) begin
                    bankmachine3_next_state <= 3'd5;
                end
            end
        end
        2'd2: begin
            if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
                bankmachine3_next_state <= 3'd5;
            end
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine3_trccon_ready) begin
                if (soc_litedramcore_bankmachine3_cmd_ready) begin
                    bankmachine3_next_state <= 3'd7;
                end
            end
        end
        3'd4: begin
            if ((~soc_litedramcore_bankmachine3_refresh_req)) begin
                bankmachine3_next_state <= 1'd0;
            end
        end
        3'd5: begin
            bankmachine3_next_state <= 3'd6;
        end
        3'd6: begin
            bankmachine3_next_state <= 2'd3;
        end
        3'd7: begin
            bankmachine3_next_state <= 4'd8;
        end
        4'd8: begin
            bankmachine3_next_state <= 1'd0;
        end
        default: begin
            if (soc_litedramcore_bankmachine3_refresh_req) begin
                bankmachine3_next_state <= 3'd4;
            end else begin
                if (soc_litedramcore_bankmachine3_source_source_valid) begin
                    if (soc_litedramcore_bankmachine3_row_opened) begin
                        if (soc_litedramcore_bankmachine3_row_hit) begin
                            if ((soc_litedramcore_bankmachine3_cmd_ready & soc_litedramcore_bankmachine3_auto_precharge)) begin
                                bankmachine3_next_state <= 2'd2;
                            end
                        end else begin
                            bankmachine3_next_state <= 1'd1;
                        end
                    end else begin
                        bankmachine3_next_state <= 2'd3;
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
    case (bankmachine3_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
            if (soc_litedramcore_bankmachine3_twtpcon_ready) begin
                soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
            end
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine3_row_open <= 1'd0;
    case (bankmachine3_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine3_trccon_ready) begin
                soc_litedramcore_bankmachine3_row_open <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine3_cmd_valid <= 1'd0;
    case (bankmachine3_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
                soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine3_trccon_ready) begin
                soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine3_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine3_source_source_valid) begin
                    if (soc_litedramcore_bankmachine3_row_opened) begin
                        if (soc_litedramcore_bankmachine3_row_hit) begin
                            soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine3_row_close <= 1'd0;
    case (bankmachine3_state)
        1'd1: begin
            soc_litedramcore_bankmachine3_row_close <= 1'd1;
        end
        2'd2: begin
            soc_litedramcore_bankmachine3_row_close <= 1'd1;
        end
        2'd3: begin
        end
        3'd4: begin
            soc_litedramcore_bankmachine3_row_close <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
    case (bankmachine3_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine3_trccon_ready) begin
                soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
    case (bankmachine3_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine3_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine3_source_source_valid) begin
                    if (soc_litedramcore_bankmachine3_row_opened) begin
                        if (soc_litedramcore_bankmachine3_row_hit) begin
                            soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
    case (bankmachine3_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
                soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine3_trccon_ready) begin
                soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
    case (bankmachine3_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
                soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine3_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine3_source_source_valid) begin
                    if (soc_litedramcore_bankmachine3_row_opened) begin
                        if (soc_litedramcore_bankmachine3_row_hit) begin
                            if (soc_litedramcore_bankmachine3_source_source_payload_we) begin
                                soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
    case (bankmachine3_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
                soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine3_trccon_ready) begin
                soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
            end
        end
        3'd4: begin
            soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
    case (bankmachine3_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine3_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine3_source_source_valid) begin
                    if (soc_litedramcore_bankmachine3_row_opened) begin
                        if (soc_litedramcore_bankmachine3_row_hit) begin
                            if (soc_litedramcore_bankmachine3_source_source_payload_we) begin
                            end else begin
                                soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
    case (bankmachine3_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine3_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine3_source_source_valid) begin
                    if (soc_litedramcore_bankmachine3_row_opened) begin
                        if (soc_litedramcore_bankmachine3_row_hit) begin
                            if (soc_litedramcore_bankmachine3_source_source_payload_we) begin
                                soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
    case (bankmachine3_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine3_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine3_source_source_valid) begin
                    if (soc_litedramcore_bankmachine3_row_opened) begin
                        if (soc_litedramcore_bankmachine3_row_hit) begin
                            if (soc_litedramcore_bankmachine3_source_source_payload_we) begin
                                soc_litedramcore_bankmachine3_req_wdata_ready <= soc_litedramcore_bankmachine3_cmd_ready;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
    case (bankmachine3_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine3_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine3_source_source_valid) begin
                    if (soc_litedramcore_bankmachine3_row_opened) begin
                        if (soc_litedramcore_bankmachine3_row_hit) begin
                            if (soc_litedramcore_bankmachine3_source_source_payload_we) begin
                            end else begin
                                soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
assign soc_litedramcore_bankmachine4_sink_valid = soc_litedramcore_bankmachine4_req_valid;
assign soc_litedramcore_bankmachine4_req_ready = soc_litedramcore_bankmachine4_sink_ready;
assign soc_litedramcore_bankmachine4_sink_payload_we = soc_litedramcore_bankmachine4_req_we;
assign soc_litedramcore_bankmachine4_sink_payload_addr = soc_litedramcore_bankmachine4_req_addr;
assign soc_litedramcore_bankmachine4_sink_sink_valid = soc_litedramcore_bankmachine4_source_valid;
assign soc_litedramcore_bankmachine4_source_ready = soc_litedramcore_bankmachine4_sink_sink_ready;
assign soc_litedramcore_bankmachine4_sink_sink_first = soc_litedramcore_bankmachine4_source_first;
assign soc_litedramcore_bankmachine4_sink_sink_last = soc_litedramcore_bankmachine4_source_last;
assign soc_litedramcore_bankmachine4_sink_sink_payload_we = soc_litedramcore_bankmachine4_source_payload_we;
assign soc_litedramcore_bankmachine4_sink_sink_payload_addr = soc_litedramcore_bankmachine4_source_payload_addr;
assign soc_litedramcore_bankmachine4_source_source_ready = (soc_litedramcore_bankmachine4_req_wdata_ready | soc_litedramcore_bankmachine4_req_rdata_valid);
assign soc_litedramcore_bankmachine4_req_lock = (soc_litedramcore_bankmachine4_source_valid | soc_litedramcore_bankmachine4_source_source_valid);
assign soc_litedramcore_bankmachine4_row_hit = (soc_litedramcore_bankmachine4_row == soc_litedramcore_bankmachine4_source_source_payload_addr[20:7]);
assign soc_litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
always @(*) begin
    soc_litedramcore_bankmachine4_cmd_payload_a <= 14'd0;
    if (soc_litedramcore_bankmachine4_row_col_n_addr_sel) begin
        soc_litedramcore_bankmachine4_cmd_payload_a <= soc_litedramcore_bankmachine4_source_source_payload_addr[20:7];
    end else begin
        soc_litedramcore_bankmachine4_cmd_payload_a <= ((soc_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}});
    end
end
assign soc_litedramcore_bankmachine4_twtpcon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_cmd_payload_is_write);
assign soc_litedramcore_bankmachine4_trccon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open);
assign soc_litedramcore_bankmachine4_trascon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open);
always @(*) begin
    soc_litedramcore_bankmachine4_auto_precharge <= 1'd0;
    if ((soc_litedramcore_bankmachine4_source_valid & soc_litedramcore_bankmachine4_source_source_valid)) begin
        if ((soc_litedramcore_bankmachine4_source_payload_addr[20:7] != soc_litedramcore_bankmachine4_source_source_payload_addr[20:7])) begin
            soc_litedramcore_bankmachine4_auto_precharge <= (soc_litedramcore_bankmachine4_row_close == 1'd0);
        end
    end
end
assign soc_litedramcore_bankmachine4_syncfifo4_din = {soc_litedramcore_bankmachine4_fifo_in_last, soc_litedramcore_bankmachine4_fifo_in_first, soc_litedramcore_bankmachine4_fifo_in_payload_addr, soc_litedramcore_bankmachine4_fifo_in_payload_we};
assign {soc_litedramcore_bankmachine4_fifo_out_last, soc_litedramcore_bankmachine4_fifo_out_first, soc_litedramcore_bankmachine4_fifo_out_payload_addr, soc_litedramcore_bankmachine4_fifo_out_payload_we} = soc_litedramcore_bankmachine4_syncfifo4_dout;
assign {soc_litedramcore_bankmachine4_fifo_out_last, soc_litedramcore_bankmachine4_fifo_out_first, soc_litedramcore_bankmachine4_fifo_out_payload_addr, soc_litedramcore_bankmachine4_fifo_out_payload_we} = soc_litedramcore_bankmachine4_syncfifo4_dout;
assign {soc_litedramcore_bankmachine4_fifo_out_last, soc_litedramcore_bankmachine4_fifo_out_first, soc_litedramcore_bankmachine4_fifo_out_payload_addr, soc_litedramcore_bankmachine4_fifo_out_payload_we} = soc_litedramcore_bankmachine4_syncfifo4_dout;
assign {soc_litedramcore_bankmachine4_fifo_out_last, soc_litedramcore_bankmachine4_fifo_out_first, soc_litedramcore_bankmachine4_fifo_out_payload_addr, soc_litedramcore_bankmachine4_fifo_out_payload_we} = soc_litedramcore_bankmachine4_syncfifo4_dout;
assign soc_litedramcore_bankmachine4_sink_ready = soc_litedramcore_bankmachine4_syncfifo4_writable;
assign soc_litedramcore_bankmachine4_syncfifo4_we = soc_litedramcore_bankmachine4_sink_valid;
assign soc_litedramcore_bankmachine4_fifo_in_first = soc_litedramcore_bankmachine4_sink_first;
assign soc_litedramcore_bankmachine4_fifo_in_last = soc_litedramcore_bankmachine4_sink_last;
assign soc_litedramcore_bankmachine4_fifo_in_payload_we = soc_litedramcore_bankmachine4_sink_payload_we;
assign soc_litedramcore_bankmachine4_fifo_in_payload_addr = soc_litedramcore_bankmachine4_sink_payload_addr;
assign soc_litedramcore_bankmachine4_source_valid = soc_litedramcore_bankmachine4_syncfifo4_readable;
assign soc_litedramcore_bankmachine4_source_first = soc_litedramcore_bankmachine4_fifo_out_first;
assign soc_litedramcore_bankmachine4_source_last = soc_litedramcore_bankmachine4_fifo_out_last;
assign soc_litedramcore_bankmachine4_source_payload_we = soc_litedramcore_bankmachine4_fifo_out_payload_we;
assign soc_litedramcore_bankmachine4_source_payload_addr = soc_litedramcore_bankmachine4_fifo_out_payload_addr;
assign soc_litedramcore_bankmachine4_syncfifo4_re = soc_litedramcore_bankmachine4_source_ready;
always @(*) begin
    soc_litedramcore_bankmachine4_wrport_adr <= 4'd0;
    if (soc_litedramcore_bankmachine4_replace) begin
        soc_litedramcore_bankmachine4_wrport_adr <= (soc_litedramcore_bankmachine4_produce - 1'd1);
    end else begin
        soc_litedramcore_bankmachine4_wrport_adr <= soc_litedramcore_bankmachine4_produce;
    end
end
assign soc_litedramcore_bankmachine4_wrport_dat_w = soc_litedramcore_bankmachine4_syncfifo4_din;
assign soc_litedramcore_bankmachine4_wrport_we = (soc_litedramcore_bankmachine4_syncfifo4_we & (soc_litedramcore_bankmachine4_syncfifo4_writable | soc_litedramcore_bankmachine4_replace));
assign soc_litedramcore_bankmachine4_do_read = (soc_litedramcore_bankmachine4_syncfifo4_readable & soc_litedramcore_bankmachine4_syncfifo4_re);
assign soc_litedramcore_bankmachine4_rdport_adr = soc_litedramcore_bankmachine4_consume;
assign soc_litedramcore_bankmachine4_syncfifo4_dout = soc_litedramcore_bankmachine4_rdport_dat_r;
assign soc_litedramcore_bankmachine4_syncfifo4_writable = (soc_litedramcore_bankmachine4_level != 5'd16);
assign soc_litedramcore_bankmachine4_syncfifo4_readable = (soc_litedramcore_bankmachine4_level != 1'd0);
assign soc_litedramcore_bankmachine4_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine4_pipe_valid_source_valid) | soc_litedramcore_bankmachine4_pipe_valid_source_ready);
assign soc_litedramcore_bankmachine4_pipe_valid_sink_valid = soc_litedramcore_bankmachine4_sink_sink_valid;
assign soc_litedramcore_bankmachine4_sink_sink_ready = soc_litedramcore_bankmachine4_pipe_valid_sink_ready;
assign soc_litedramcore_bankmachine4_pipe_valid_sink_first = soc_litedramcore_bankmachine4_sink_sink_first;
assign soc_litedramcore_bankmachine4_pipe_valid_sink_last = soc_litedramcore_bankmachine4_sink_sink_last;
assign soc_litedramcore_bankmachine4_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine4_sink_sink_payload_we;
assign soc_litedramcore_bankmachine4_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine4_sink_sink_payload_addr;
assign soc_litedramcore_bankmachine4_source_source_valid = soc_litedramcore_bankmachine4_pipe_valid_source_valid;
assign soc_litedramcore_bankmachine4_pipe_valid_source_ready = soc_litedramcore_bankmachine4_source_source_ready;
assign soc_litedramcore_bankmachine4_source_source_first = soc_litedramcore_bankmachine4_pipe_valid_source_first;
assign soc_litedramcore_bankmachine4_source_source_last = soc_litedramcore_bankmachine4_pipe_valid_source_last;
assign soc_litedramcore_bankmachine4_source_source_payload_we = soc_litedramcore_bankmachine4_pipe_valid_source_payload_we;
assign soc_litedramcore_bankmachine4_source_source_payload_addr = soc_litedramcore_bankmachine4_pipe_valid_source_payload_addr;
always @(*) begin
    bankmachine4_next_state <= 4'd0;
    bankmachine4_next_state <= bankmachine4_state;
    case (bankmachine4_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
                if (soc_litedramcore_bankmachine4_cmd_ready) begin
                    bankmachine4_next_state <= 3'd5;
                end
            end
        end
        2'd2: begin
            if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
                bankmachine4_next_state <= 3'd5;
            end
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine4_trccon_ready) begin
                if (soc_litedramcore_bankmachine4_cmd_ready) begin
                    bankmachine4_next_state <= 3'd7;
                end
            end
        end
        3'd4: begin
            if ((~soc_litedramcore_bankmachine4_refresh_req)) begin
                bankmachine4_next_state <= 1'd0;
            end
        end
        3'd5: begin
            bankmachine4_next_state <= 3'd6;
        end
        3'd6: begin
            bankmachine4_next_state <= 2'd3;
        end
        3'd7: begin
            bankmachine4_next_state <= 4'd8;
        end
        4'd8: begin
            bankmachine4_next_state <= 1'd0;
        end
        default: begin
            if (soc_litedramcore_bankmachine4_refresh_req) begin
                bankmachine4_next_state <= 3'd4;
            end else begin
                if (soc_litedramcore_bankmachine4_source_source_valid) begin
                    if (soc_litedramcore_bankmachine4_row_opened) begin
                        if (soc_litedramcore_bankmachine4_row_hit) begin
                            if ((soc_litedramcore_bankmachine4_cmd_ready & soc_litedramcore_bankmachine4_auto_precharge)) begin
                                bankmachine4_next_state <= 2'd2;
                            end
                        end else begin
                            bankmachine4_next_state <= 1'd1;
                        end
                    end else begin
                        bankmachine4_next_state <= 2'd3;
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
    case (bankmachine4_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine4_trccon_ready) begin
                soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
    case (bankmachine4_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine4_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine4_source_source_valid) begin
                    if (soc_litedramcore_bankmachine4_row_opened) begin
                        if (soc_litedramcore_bankmachine4_row_hit) begin
                            soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
    case (bankmachine4_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
                soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine4_trccon_ready) begin
                soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
    case (bankmachine4_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
                soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine4_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine4_source_source_valid) begin
                    if (soc_litedramcore_bankmachine4_row_opened) begin
                        if (soc_litedramcore_bankmachine4_row_hit) begin
                            if (soc_litedramcore_bankmachine4_source_source_payload_we) begin
                                soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
    case (bankmachine4_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
                soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine4_trccon_ready) begin
                soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
            end
        end
        3'd4: begin
            soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
    case (bankmachine4_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine4_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine4_source_source_valid) begin
                    if (soc_litedramcore_bankmachine4_row_opened) begin
                        if (soc_litedramcore_bankmachine4_row_hit) begin
                            if (soc_litedramcore_bankmachine4_source_source_payload_we) begin
                            end else begin
                                soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
    case (bankmachine4_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine4_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine4_source_source_valid) begin
                    if (soc_litedramcore_bankmachine4_row_opened) begin
                        if (soc_litedramcore_bankmachine4_row_hit) begin
                            if (soc_litedramcore_bankmachine4_source_source_payload_we) begin
                                soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
    case (bankmachine4_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine4_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine4_source_source_valid) begin
                    if (soc_litedramcore_bankmachine4_row_opened) begin
                        if (soc_litedramcore_bankmachine4_row_hit) begin
                            if (soc_litedramcore_bankmachine4_source_source_payload_we) begin
                                soc_litedramcore_bankmachine4_req_wdata_ready <= soc_litedramcore_bankmachine4_cmd_ready;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
    case (bankmachine4_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine4_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine4_source_source_valid) begin
                    if (soc_litedramcore_bankmachine4_row_opened) begin
                        if (soc_litedramcore_bankmachine4_row_hit) begin
                            if (soc_litedramcore_bankmachine4_source_source_payload_we) begin
                            end else begin
                                soc_litedramcore_bankmachine4_req_rdata_valid <= soc_litedramcore_bankmachine4_cmd_ready;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
    case (bankmachine4_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
            if (soc_litedramcore_bankmachine4_twtpcon_ready) begin
                soc_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
            end
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine4_row_open <= 1'd0;
    case (bankmachine4_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine4_trccon_ready) begin
                soc_litedramcore_bankmachine4_row_open <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine4_cmd_valid <= 1'd0;
    case (bankmachine4_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
                soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine4_trccon_ready) begin
                soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine4_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine4_source_source_valid) begin
                    if (soc_litedramcore_bankmachine4_row_opened) begin
                        if (soc_litedramcore_bankmachine4_row_hit) begin
                            soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine4_row_close <= 1'd0;
    case (bankmachine4_state)
        1'd1: begin
            soc_litedramcore_bankmachine4_row_close <= 1'd1;
        end
        2'd2: begin
            soc_litedramcore_bankmachine4_row_close <= 1'd1;
        end
        2'd3: begin
        end
        3'd4: begin
            soc_litedramcore_bankmachine4_row_close <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
assign soc_litedramcore_bankmachine5_sink_valid = soc_litedramcore_bankmachine5_req_valid;
assign soc_litedramcore_bankmachine5_req_ready = soc_litedramcore_bankmachine5_sink_ready;
assign soc_litedramcore_bankmachine5_sink_payload_we = soc_litedramcore_bankmachine5_req_we;
assign soc_litedramcore_bankmachine5_sink_payload_addr = soc_litedramcore_bankmachine5_req_addr;
assign soc_litedramcore_bankmachine5_sink_sink_valid = soc_litedramcore_bankmachine5_source_valid;
assign soc_litedramcore_bankmachine5_source_ready = soc_litedramcore_bankmachine5_sink_sink_ready;
assign soc_litedramcore_bankmachine5_sink_sink_first = soc_litedramcore_bankmachine5_source_first;
assign soc_litedramcore_bankmachine5_sink_sink_last = soc_litedramcore_bankmachine5_source_last;
assign soc_litedramcore_bankmachine5_sink_sink_payload_we = soc_litedramcore_bankmachine5_source_payload_we;
assign soc_litedramcore_bankmachine5_sink_sink_payload_addr = soc_litedramcore_bankmachine5_source_payload_addr;
assign soc_litedramcore_bankmachine5_source_source_ready = (soc_litedramcore_bankmachine5_req_wdata_ready | soc_litedramcore_bankmachine5_req_rdata_valid);
assign soc_litedramcore_bankmachine5_req_lock = (soc_litedramcore_bankmachine5_source_valid | soc_litedramcore_bankmachine5_source_source_valid);
assign soc_litedramcore_bankmachine5_row_hit = (soc_litedramcore_bankmachine5_row == soc_litedramcore_bankmachine5_source_source_payload_addr[20:7]);
assign soc_litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
always @(*) begin
    soc_litedramcore_bankmachine5_cmd_payload_a <= 14'd0;
    if (soc_litedramcore_bankmachine5_row_col_n_addr_sel) begin
        soc_litedramcore_bankmachine5_cmd_payload_a <= soc_litedramcore_bankmachine5_source_source_payload_addr[20:7];
    end else begin
        soc_litedramcore_bankmachine5_cmd_payload_a <= ((soc_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}});
    end
end
assign soc_litedramcore_bankmachine5_twtpcon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_cmd_payload_is_write);
assign soc_litedramcore_bankmachine5_trccon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open);
assign soc_litedramcore_bankmachine5_trascon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open);
always @(*) begin
    soc_litedramcore_bankmachine5_auto_precharge <= 1'd0;
    if ((soc_litedramcore_bankmachine5_source_valid & soc_litedramcore_bankmachine5_source_source_valid)) begin
        if ((soc_litedramcore_bankmachine5_source_payload_addr[20:7] != soc_litedramcore_bankmachine5_source_source_payload_addr[20:7])) begin
            soc_litedramcore_bankmachine5_auto_precharge <= (soc_litedramcore_bankmachine5_row_close == 1'd0);
        end
    end
end
assign soc_litedramcore_bankmachine5_syncfifo5_din = {soc_litedramcore_bankmachine5_fifo_in_last, soc_litedramcore_bankmachine5_fifo_in_first, soc_litedramcore_bankmachine5_fifo_in_payload_addr, soc_litedramcore_bankmachine5_fifo_in_payload_we};
assign {soc_litedramcore_bankmachine5_fifo_out_last, soc_litedramcore_bankmachine5_fifo_out_first, soc_litedramcore_bankmachine5_fifo_out_payload_addr, soc_litedramcore_bankmachine5_fifo_out_payload_we} = soc_litedramcore_bankmachine5_syncfifo5_dout;
assign {soc_litedramcore_bankmachine5_fifo_out_last, soc_litedramcore_bankmachine5_fifo_out_first, soc_litedramcore_bankmachine5_fifo_out_payload_addr, soc_litedramcore_bankmachine5_fifo_out_payload_we} = soc_litedramcore_bankmachine5_syncfifo5_dout;
assign {soc_litedramcore_bankmachine5_fifo_out_last, soc_litedramcore_bankmachine5_fifo_out_first, soc_litedramcore_bankmachine5_fifo_out_payload_addr, soc_litedramcore_bankmachine5_fifo_out_payload_we} = soc_litedramcore_bankmachine5_syncfifo5_dout;
assign {soc_litedramcore_bankmachine5_fifo_out_last, soc_litedramcore_bankmachine5_fifo_out_first, soc_litedramcore_bankmachine5_fifo_out_payload_addr, soc_litedramcore_bankmachine5_fifo_out_payload_we} = soc_litedramcore_bankmachine5_syncfifo5_dout;
assign soc_litedramcore_bankmachine5_sink_ready = soc_litedramcore_bankmachine5_syncfifo5_writable;
assign soc_litedramcore_bankmachine5_syncfifo5_we = soc_litedramcore_bankmachine5_sink_valid;
assign soc_litedramcore_bankmachine5_fifo_in_first = soc_litedramcore_bankmachine5_sink_first;
assign soc_litedramcore_bankmachine5_fifo_in_last = soc_litedramcore_bankmachine5_sink_last;
assign soc_litedramcore_bankmachine5_fifo_in_payload_we = soc_litedramcore_bankmachine5_sink_payload_we;
assign soc_litedramcore_bankmachine5_fifo_in_payload_addr = soc_litedramcore_bankmachine5_sink_payload_addr;
assign soc_litedramcore_bankmachine5_source_valid = soc_litedramcore_bankmachine5_syncfifo5_readable;
assign soc_litedramcore_bankmachine5_source_first = soc_litedramcore_bankmachine5_fifo_out_first;
assign soc_litedramcore_bankmachine5_source_last = soc_litedramcore_bankmachine5_fifo_out_last;
assign soc_litedramcore_bankmachine5_source_payload_we = soc_litedramcore_bankmachine5_fifo_out_payload_we;
assign soc_litedramcore_bankmachine5_source_payload_addr = soc_litedramcore_bankmachine5_fifo_out_payload_addr;
assign soc_litedramcore_bankmachine5_syncfifo5_re = soc_litedramcore_bankmachine5_source_ready;
always @(*) begin
    soc_litedramcore_bankmachine5_wrport_adr <= 4'd0;
    if (soc_litedramcore_bankmachine5_replace) begin
        soc_litedramcore_bankmachine5_wrport_adr <= (soc_litedramcore_bankmachine5_produce - 1'd1);
    end else begin
        soc_litedramcore_bankmachine5_wrport_adr <= soc_litedramcore_bankmachine5_produce;
    end
end
assign soc_litedramcore_bankmachine5_wrport_dat_w = soc_litedramcore_bankmachine5_syncfifo5_din;
assign soc_litedramcore_bankmachine5_wrport_we = (soc_litedramcore_bankmachine5_syncfifo5_we & (soc_litedramcore_bankmachine5_syncfifo5_writable | soc_litedramcore_bankmachine5_replace));
assign soc_litedramcore_bankmachine5_do_read = (soc_litedramcore_bankmachine5_syncfifo5_readable & soc_litedramcore_bankmachine5_syncfifo5_re);
assign soc_litedramcore_bankmachine5_rdport_adr = soc_litedramcore_bankmachine5_consume;
assign soc_litedramcore_bankmachine5_syncfifo5_dout = soc_litedramcore_bankmachine5_rdport_dat_r;
assign soc_litedramcore_bankmachine5_syncfifo5_writable = (soc_litedramcore_bankmachine5_level != 5'd16);
assign soc_litedramcore_bankmachine5_syncfifo5_readable = (soc_litedramcore_bankmachine5_level != 1'd0);
assign soc_litedramcore_bankmachine5_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine5_pipe_valid_source_valid) | soc_litedramcore_bankmachine5_pipe_valid_source_ready);
assign soc_litedramcore_bankmachine5_pipe_valid_sink_valid = soc_litedramcore_bankmachine5_sink_sink_valid;
assign soc_litedramcore_bankmachine5_sink_sink_ready = soc_litedramcore_bankmachine5_pipe_valid_sink_ready;
assign soc_litedramcore_bankmachine5_pipe_valid_sink_first = soc_litedramcore_bankmachine5_sink_sink_first;
assign soc_litedramcore_bankmachine5_pipe_valid_sink_last = soc_litedramcore_bankmachine5_sink_sink_last;
assign soc_litedramcore_bankmachine5_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine5_sink_sink_payload_we;
assign soc_litedramcore_bankmachine5_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine5_sink_sink_payload_addr;
assign soc_litedramcore_bankmachine5_source_source_valid = soc_litedramcore_bankmachine5_pipe_valid_source_valid;
assign soc_litedramcore_bankmachine5_pipe_valid_source_ready = soc_litedramcore_bankmachine5_source_source_ready;
assign soc_litedramcore_bankmachine5_source_source_first = soc_litedramcore_bankmachine5_pipe_valid_source_first;
assign soc_litedramcore_bankmachine5_source_source_last = soc_litedramcore_bankmachine5_pipe_valid_source_last;
assign soc_litedramcore_bankmachine5_source_source_payload_we = soc_litedramcore_bankmachine5_pipe_valid_source_payload_we;
assign soc_litedramcore_bankmachine5_source_source_payload_addr = soc_litedramcore_bankmachine5_pipe_valid_source_payload_addr;
always @(*) begin
    bankmachine5_next_state <= 4'd0;
    bankmachine5_next_state <= bankmachine5_state;
    case (bankmachine5_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
                if (soc_litedramcore_bankmachine5_cmd_ready) begin
                    bankmachine5_next_state <= 3'd5;
                end
            end
        end
        2'd2: begin
            if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
                bankmachine5_next_state <= 3'd5;
            end
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine5_trccon_ready) begin
                if (soc_litedramcore_bankmachine5_cmd_ready) begin
                    bankmachine5_next_state <= 3'd7;
                end
            end
        end
        3'd4: begin
            if ((~soc_litedramcore_bankmachine5_refresh_req)) begin
                bankmachine5_next_state <= 1'd0;
            end
        end
        3'd5: begin
            bankmachine5_next_state <= 3'd6;
        end
        3'd6: begin
            bankmachine5_next_state <= 2'd3;
        end
        3'd7: begin
            bankmachine5_next_state <= 4'd8;
        end
        4'd8: begin
            bankmachine5_next_state <= 1'd0;
        end
        default: begin
            if (soc_litedramcore_bankmachine5_refresh_req) begin
                bankmachine5_next_state <= 3'd4;
            end else begin
                if (soc_litedramcore_bankmachine5_source_source_valid) begin
                    if (soc_litedramcore_bankmachine5_row_opened) begin
                        if (soc_litedramcore_bankmachine5_row_hit) begin
                            if ((soc_litedramcore_bankmachine5_cmd_ready & soc_litedramcore_bankmachine5_auto_precharge)) begin
                                bankmachine5_next_state <= 2'd2;
                            end
                        end else begin
                            bankmachine5_next_state <= 1'd1;
                        end
                    end else begin
                        bankmachine5_next_state <= 2'd3;
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
    case (bankmachine5_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
                soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine5_trccon_ready) begin
                soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
    case (bankmachine5_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
                soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine5_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine5_source_source_valid) begin
                    if (soc_litedramcore_bankmachine5_row_opened) begin
                        if (soc_litedramcore_bankmachine5_row_hit) begin
                            if (soc_litedramcore_bankmachine5_source_source_payload_we) begin
                                soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
    case (bankmachine5_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
                soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine5_trccon_ready) begin
                soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
            end
        end
        3'd4: begin
            soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
    case (bankmachine5_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine5_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine5_source_source_valid) begin
                    if (soc_litedramcore_bankmachine5_row_opened) begin
                        if (soc_litedramcore_bankmachine5_row_hit) begin
                            if (soc_litedramcore_bankmachine5_source_source_payload_we) begin
                            end else begin
                                soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
    case (bankmachine5_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine5_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine5_source_source_valid) begin
                    if (soc_litedramcore_bankmachine5_row_opened) begin
                        if (soc_litedramcore_bankmachine5_row_hit) begin
                            if (soc_litedramcore_bankmachine5_source_source_payload_we) begin
                                soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
    case (bankmachine5_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine5_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine5_source_source_valid) begin
                    if (soc_litedramcore_bankmachine5_row_opened) begin
                        if (soc_litedramcore_bankmachine5_row_hit) begin
                            if (soc_litedramcore_bankmachine5_source_source_payload_we) begin
                                soc_litedramcore_bankmachine5_req_wdata_ready <= soc_litedramcore_bankmachine5_cmd_ready;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
    case (bankmachine5_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine5_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine5_source_source_valid) begin
                    if (soc_litedramcore_bankmachine5_row_opened) begin
                        if (soc_litedramcore_bankmachine5_row_hit) begin
                            if (soc_litedramcore_bankmachine5_source_source_payload_we) begin
                            end else begin
                                soc_litedramcore_bankmachine5_req_rdata_valid <= soc_litedramcore_bankmachine5_cmd_ready;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
    case (bankmachine5_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
            if (soc_litedramcore_bankmachine5_twtpcon_ready) begin
                soc_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
            end
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine5_row_open <= 1'd0;
    case (bankmachine5_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine5_trccon_ready) begin
                soc_litedramcore_bankmachine5_row_open <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine5_cmd_valid <= 1'd0;
    case (bankmachine5_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
                soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine5_trccon_ready) begin
                soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine5_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine5_source_source_valid) begin
                    if (soc_litedramcore_bankmachine5_row_opened) begin
                        if (soc_litedramcore_bankmachine5_row_hit) begin
                            soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine5_row_close <= 1'd0;
    case (bankmachine5_state)
        1'd1: begin
            soc_litedramcore_bankmachine5_row_close <= 1'd1;
        end
        2'd2: begin
            soc_litedramcore_bankmachine5_row_close <= 1'd1;
        end
        2'd3: begin
        end
        3'd4: begin
            soc_litedramcore_bankmachine5_row_close <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
    case (bankmachine5_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine5_trccon_ready) begin
                soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
    case (bankmachine5_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine5_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine5_source_source_valid) begin
                    if (soc_litedramcore_bankmachine5_row_opened) begin
                        if (soc_litedramcore_bankmachine5_row_hit) begin
                            soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
assign soc_litedramcore_bankmachine6_sink_valid = soc_litedramcore_bankmachine6_req_valid;
assign soc_litedramcore_bankmachine6_req_ready = soc_litedramcore_bankmachine6_sink_ready;
assign soc_litedramcore_bankmachine6_sink_payload_we = soc_litedramcore_bankmachine6_req_we;
assign soc_litedramcore_bankmachine6_sink_payload_addr = soc_litedramcore_bankmachine6_req_addr;
assign soc_litedramcore_bankmachine6_sink_sink_valid = soc_litedramcore_bankmachine6_source_valid;
assign soc_litedramcore_bankmachine6_source_ready = soc_litedramcore_bankmachine6_sink_sink_ready;
assign soc_litedramcore_bankmachine6_sink_sink_first = soc_litedramcore_bankmachine6_source_first;
assign soc_litedramcore_bankmachine6_sink_sink_last = soc_litedramcore_bankmachine6_source_last;
assign soc_litedramcore_bankmachine6_sink_sink_payload_we = soc_litedramcore_bankmachine6_source_payload_we;
assign soc_litedramcore_bankmachine6_sink_sink_payload_addr = soc_litedramcore_bankmachine6_source_payload_addr;
assign soc_litedramcore_bankmachine6_source_source_ready = (soc_litedramcore_bankmachine6_req_wdata_ready | soc_litedramcore_bankmachine6_req_rdata_valid);
assign soc_litedramcore_bankmachine6_req_lock = (soc_litedramcore_bankmachine6_source_valid | soc_litedramcore_bankmachine6_source_source_valid);
assign soc_litedramcore_bankmachine6_row_hit = (soc_litedramcore_bankmachine6_row == soc_litedramcore_bankmachine6_source_source_payload_addr[20:7]);
assign soc_litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
always @(*) begin
    soc_litedramcore_bankmachine6_cmd_payload_a <= 14'd0;
    if (soc_litedramcore_bankmachine6_row_col_n_addr_sel) begin
        soc_litedramcore_bankmachine6_cmd_payload_a <= soc_litedramcore_bankmachine6_source_source_payload_addr[20:7];
    end else begin
        soc_litedramcore_bankmachine6_cmd_payload_a <= ((soc_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}});
    end
end
assign soc_litedramcore_bankmachine6_twtpcon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_cmd_payload_is_write);
assign soc_litedramcore_bankmachine6_trccon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open);
assign soc_litedramcore_bankmachine6_trascon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open);
always @(*) begin
    soc_litedramcore_bankmachine6_auto_precharge <= 1'd0;
    if ((soc_litedramcore_bankmachine6_source_valid & soc_litedramcore_bankmachine6_source_source_valid)) begin
        if ((soc_litedramcore_bankmachine6_source_payload_addr[20:7] != soc_litedramcore_bankmachine6_source_source_payload_addr[20:7])) begin
            soc_litedramcore_bankmachine6_auto_precharge <= (soc_litedramcore_bankmachine6_row_close == 1'd0);
        end
    end
end
assign soc_litedramcore_bankmachine6_syncfifo6_din = {soc_litedramcore_bankmachine6_fifo_in_last, soc_litedramcore_bankmachine6_fifo_in_first, soc_litedramcore_bankmachine6_fifo_in_payload_addr, soc_litedramcore_bankmachine6_fifo_in_payload_we};
assign {soc_litedramcore_bankmachine6_fifo_out_last, soc_litedramcore_bankmachine6_fifo_out_first, soc_litedramcore_bankmachine6_fifo_out_payload_addr, soc_litedramcore_bankmachine6_fifo_out_payload_we} = soc_litedramcore_bankmachine6_syncfifo6_dout;
assign {soc_litedramcore_bankmachine6_fifo_out_last, soc_litedramcore_bankmachine6_fifo_out_first, soc_litedramcore_bankmachine6_fifo_out_payload_addr, soc_litedramcore_bankmachine6_fifo_out_payload_we} = soc_litedramcore_bankmachine6_syncfifo6_dout;
assign {soc_litedramcore_bankmachine6_fifo_out_last, soc_litedramcore_bankmachine6_fifo_out_first, soc_litedramcore_bankmachine6_fifo_out_payload_addr, soc_litedramcore_bankmachine6_fifo_out_payload_we} = soc_litedramcore_bankmachine6_syncfifo6_dout;
assign {soc_litedramcore_bankmachine6_fifo_out_last, soc_litedramcore_bankmachine6_fifo_out_first, soc_litedramcore_bankmachine6_fifo_out_payload_addr, soc_litedramcore_bankmachine6_fifo_out_payload_we} = soc_litedramcore_bankmachine6_syncfifo6_dout;
assign soc_litedramcore_bankmachine6_sink_ready = soc_litedramcore_bankmachine6_syncfifo6_writable;
assign soc_litedramcore_bankmachine6_syncfifo6_we = soc_litedramcore_bankmachine6_sink_valid;
assign soc_litedramcore_bankmachine6_fifo_in_first = soc_litedramcore_bankmachine6_sink_first;
assign soc_litedramcore_bankmachine6_fifo_in_last = soc_litedramcore_bankmachine6_sink_last;
assign soc_litedramcore_bankmachine6_fifo_in_payload_we = soc_litedramcore_bankmachine6_sink_payload_we;
assign soc_litedramcore_bankmachine6_fifo_in_payload_addr = soc_litedramcore_bankmachine6_sink_payload_addr;
assign soc_litedramcore_bankmachine6_source_valid = soc_litedramcore_bankmachine6_syncfifo6_readable;
assign soc_litedramcore_bankmachine6_source_first = soc_litedramcore_bankmachine6_fifo_out_first;
assign soc_litedramcore_bankmachine6_source_last = soc_litedramcore_bankmachine6_fifo_out_last;
assign soc_litedramcore_bankmachine6_source_payload_we = soc_litedramcore_bankmachine6_fifo_out_payload_we;
assign soc_litedramcore_bankmachine6_source_payload_addr = soc_litedramcore_bankmachine6_fifo_out_payload_addr;
assign soc_litedramcore_bankmachine6_syncfifo6_re = soc_litedramcore_bankmachine6_source_ready;
always @(*) begin
    soc_litedramcore_bankmachine6_wrport_adr <= 4'd0;
    if (soc_litedramcore_bankmachine6_replace) begin
        soc_litedramcore_bankmachine6_wrport_adr <= (soc_litedramcore_bankmachine6_produce - 1'd1);
    end else begin
        soc_litedramcore_bankmachine6_wrport_adr <= soc_litedramcore_bankmachine6_produce;
    end
end
assign soc_litedramcore_bankmachine6_wrport_dat_w = soc_litedramcore_bankmachine6_syncfifo6_din;
assign soc_litedramcore_bankmachine6_wrport_we = (soc_litedramcore_bankmachine6_syncfifo6_we & (soc_litedramcore_bankmachine6_syncfifo6_writable | soc_litedramcore_bankmachine6_replace));
assign soc_litedramcore_bankmachine6_do_read = (soc_litedramcore_bankmachine6_syncfifo6_readable & soc_litedramcore_bankmachine6_syncfifo6_re);
assign soc_litedramcore_bankmachine6_rdport_adr = soc_litedramcore_bankmachine6_consume;
assign soc_litedramcore_bankmachine6_syncfifo6_dout = soc_litedramcore_bankmachine6_rdport_dat_r;
assign soc_litedramcore_bankmachine6_syncfifo6_writable = (soc_litedramcore_bankmachine6_level != 5'd16);
assign soc_litedramcore_bankmachine6_syncfifo6_readable = (soc_litedramcore_bankmachine6_level != 1'd0);
assign soc_litedramcore_bankmachine6_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine6_pipe_valid_source_valid) | soc_litedramcore_bankmachine6_pipe_valid_source_ready);
assign soc_litedramcore_bankmachine6_pipe_valid_sink_valid = soc_litedramcore_bankmachine6_sink_sink_valid;
assign soc_litedramcore_bankmachine6_sink_sink_ready = soc_litedramcore_bankmachine6_pipe_valid_sink_ready;
assign soc_litedramcore_bankmachine6_pipe_valid_sink_first = soc_litedramcore_bankmachine6_sink_sink_first;
assign soc_litedramcore_bankmachine6_pipe_valid_sink_last = soc_litedramcore_bankmachine6_sink_sink_last;
assign soc_litedramcore_bankmachine6_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine6_sink_sink_payload_we;
assign soc_litedramcore_bankmachine6_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine6_sink_sink_payload_addr;
assign soc_litedramcore_bankmachine6_source_source_valid = soc_litedramcore_bankmachine6_pipe_valid_source_valid;
assign soc_litedramcore_bankmachine6_pipe_valid_source_ready = soc_litedramcore_bankmachine6_source_source_ready;
assign soc_litedramcore_bankmachine6_source_source_first = soc_litedramcore_bankmachine6_pipe_valid_source_first;
assign soc_litedramcore_bankmachine6_source_source_last = soc_litedramcore_bankmachine6_pipe_valid_source_last;
assign soc_litedramcore_bankmachine6_source_source_payload_we = soc_litedramcore_bankmachine6_pipe_valid_source_payload_we;
assign soc_litedramcore_bankmachine6_source_source_payload_addr = soc_litedramcore_bankmachine6_pipe_valid_source_payload_addr;
always @(*) begin
    bankmachine6_next_state <= 4'd0;
    bankmachine6_next_state <= bankmachine6_state;
    case (bankmachine6_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
                if (soc_litedramcore_bankmachine6_cmd_ready) begin
                    bankmachine6_next_state <= 3'd5;
                end
            end
        end
        2'd2: begin
            if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
                bankmachine6_next_state <= 3'd5;
            end
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine6_trccon_ready) begin
                if (soc_litedramcore_bankmachine6_cmd_ready) begin
                    bankmachine6_next_state <= 3'd7;
                end
            end
        end
        3'd4: begin
            if ((~soc_litedramcore_bankmachine6_refresh_req)) begin
                bankmachine6_next_state <= 1'd0;
            end
        end
        3'd5: begin
            bankmachine6_next_state <= 3'd6;
        end
        3'd6: begin
            bankmachine6_next_state <= 2'd3;
        end
        3'd7: begin
            bankmachine6_next_state <= 4'd8;
        end
        4'd8: begin
            bankmachine6_next_state <= 1'd0;
        end
        default: begin
            if (soc_litedramcore_bankmachine6_refresh_req) begin
                bankmachine6_next_state <= 3'd4;
            end else begin
                if (soc_litedramcore_bankmachine6_source_source_valid) begin
                    if (soc_litedramcore_bankmachine6_row_opened) begin
                        if (soc_litedramcore_bankmachine6_row_hit) begin
                            if ((soc_litedramcore_bankmachine6_cmd_ready & soc_litedramcore_bankmachine6_auto_precharge)) begin
                                bankmachine6_next_state <= 2'd2;
                            end
                        end else begin
                            bankmachine6_next_state <= 1'd1;
                        end
                    end else begin
                        bankmachine6_next_state <= 2'd3;
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
    case (bankmachine6_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine6_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine6_source_source_valid) begin
                    if (soc_litedramcore_bankmachine6_row_opened) begin
                        if (soc_litedramcore_bankmachine6_row_hit) begin
                            if (soc_litedramcore_bankmachine6_source_source_payload_we) begin
                                soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
    case (bankmachine6_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine6_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine6_source_source_valid) begin
                    if (soc_litedramcore_bankmachine6_row_opened) begin
                        if (soc_litedramcore_bankmachine6_row_hit) begin
                            if (soc_litedramcore_bankmachine6_source_source_payload_we) begin
                                soc_litedramcore_bankmachine6_req_wdata_ready <= soc_litedramcore_bankmachine6_cmd_ready;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
    case (bankmachine6_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine6_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine6_source_source_valid) begin
                    if (soc_litedramcore_bankmachine6_row_opened) begin
                        if (soc_litedramcore_bankmachine6_row_hit) begin
                            if (soc_litedramcore_bankmachine6_source_source_payload_we) begin
                            end else begin
                                soc_litedramcore_bankmachine6_req_rdata_valid <= soc_litedramcore_bankmachine6_cmd_ready;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
    case (bankmachine6_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
            if (soc_litedramcore_bankmachine6_twtpcon_ready) begin
                soc_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
            end
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine6_row_open <= 1'd0;
    case (bankmachine6_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine6_trccon_ready) begin
                soc_litedramcore_bankmachine6_row_open <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine6_cmd_valid <= 1'd0;
    case (bankmachine6_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
                soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine6_trccon_ready) begin
                soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine6_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine6_source_source_valid) begin
                    if (soc_litedramcore_bankmachine6_row_opened) begin
                        if (soc_litedramcore_bankmachine6_row_hit) begin
                            soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine6_row_close <= 1'd0;
    case (bankmachine6_state)
        1'd1: begin
            soc_litedramcore_bankmachine6_row_close <= 1'd1;
        end
        2'd2: begin
            soc_litedramcore_bankmachine6_row_close <= 1'd1;
        end
        2'd3: begin
        end
        3'd4: begin
            soc_litedramcore_bankmachine6_row_close <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
    case (bankmachine6_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine6_trccon_ready) begin
                soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
    case (bankmachine6_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine6_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine6_source_source_valid) begin
                    if (soc_litedramcore_bankmachine6_row_opened) begin
                        if (soc_litedramcore_bankmachine6_row_hit) begin
                            soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
    case (bankmachine6_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
                soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine6_trccon_ready) begin
                soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
    case (bankmachine6_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
                soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine6_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine6_source_source_valid) begin
                    if (soc_litedramcore_bankmachine6_row_opened) begin
                        if (soc_litedramcore_bankmachine6_row_hit) begin
                            if (soc_litedramcore_bankmachine6_source_source_payload_we) begin
                                soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
    case (bankmachine6_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
                soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine6_trccon_ready) begin
                soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
            end
        end
        3'd4: begin
            soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
    case (bankmachine6_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine6_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine6_source_source_valid) begin
                    if (soc_litedramcore_bankmachine6_row_opened) begin
                        if (soc_litedramcore_bankmachine6_row_hit) begin
                            if (soc_litedramcore_bankmachine6_source_source_payload_we) begin
                            end else begin
                                soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
assign soc_litedramcore_bankmachine7_sink_valid = soc_litedramcore_bankmachine7_req_valid;
assign soc_litedramcore_bankmachine7_req_ready = soc_litedramcore_bankmachine7_sink_ready;
assign soc_litedramcore_bankmachine7_sink_payload_we = soc_litedramcore_bankmachine7_req_we;
assign soc_litedramcore_bankmachine7_sink_payload_addr = soc_litedramcore_bankmachine7_req_addr;
assign soc_litedramcore_bankmachine7_sink_sink_valid = soc_litedramcore_bankmachine7_source_valid;
assign soc_litedramcore_bankmachine7_source_ready = soc_litedramcore_bankmachine7_sink_sink_ready;
assign soc_litedramcore_bankmachine7_sink_sink_first = soc_litedramcore_bankmachine7_source_first;
assign soc_litedramcore_bankmachine7_sink_sink_last = soc_litedramcore_bankmachine7_source_last;
assign soc_litedramcore_bankmachine7_sink_sink_payload_we = soc_litedramcore_bankmachine7_source_payload_we;
assign soc_litedramcore_bankmachine7_sink_sink_payload_addr = soc_litedramcore_bankmachine7_source_payload_addr;
assign soc_litedramcore_bankmachine7_source_source_ready = (soc_litedramcore_bankmachine7_req_wdata_ready | soc_litedramcore_bankmachine7_req_rdata_valid);
assign soc_litedramcore_bankmachine7_req_lock = (soc_litedramcore_bankmachine7_source_valid | soc_litedramcore_bankmachine7_source_source_valid);
assign soc_litedramcore_bankmachine7_row_hit = (soc_litedramcore_bankmachine7_row == soc_litedramcore_bankmachine7_source_source_payload_addr[20:7]);
assign soc_litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
always @(*) begin
    soc_litedramcore_bankmachine7_cmd_payload_a <= 14'd0;
    if (soc_litedramcore_bankmachine7_row_col_n_addr_sel) begin
        soc_litedramcore_bankmachine7_cmd_payload_a <= soc_litedramcore_bankmachine7_source_source_payload_addr[20:7];
    end else begin
        soc_litedramcore_bankmachine7_cmd_payload_a <= ((soc_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}});
    end
end
assign soc_litedramcore_bankmachine7_twtpcon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_cmd_payload_is_write);
assign soc_litedramcore_bankmachine7_trccon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open);
assign soc_litedramcore_bankmachine7_trascon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open);
always @(*) begin
    soc_litedramcore_bankmachine7_auto_precharge <= 1'd0;
    if ((soc_litedramcore_bankmachine7_source_valid & soc_litedramcore_bankmachine7_source_source_valid)) begin
        if ((soc_litedramcore_bankmachine7_source_payload_addr[20:7] != soc_litedramcore_bankmachine7_source_source_payload_addr[20:7])) begin
            soc_litedramcore_bankmachine7_auto_precharge <= (soc_litedramcore_bankmachine7_row_close == 1'd0);
        end
    end
end
assign soc_litedramcore_bankmachine7_syncfifo7_din = {soc_litedramcore_bankmachine7_fifo_in_last, soc_litedramcore_bankmachine7_fifo_in_first, soc_litedramcore_bankmachine7_fifo_in_payload_addr, soc_litedramcore_bankmachine7_fifo_in_payload_we};
assign {soc_litedramcore_bankmachine7_fifo_out_last, soc_litedramcore_bankmachine7_fifo_out_first, soc_litedramcore_bankmachine7_fifo_out_payload_addr, soc_litedramcore_bankmachine7_fifo_out_payload_we} = soc_litedramcore_bankmachine7_syncfifo7_dout;
assign {soc_litedramcore_bankmachine7_fifo_out_last, soc_litedramcore_bankmachine7_fifo_out_first, soc_litedramcore_bankmachine7_fifo_out_payload_addr, soc_litedramcore_bankmachine7_fifo_out_payload_we} = soc_litedramcore_bankmachine7_syncfifo7_dout;
assign {soc_litedramcore_bankmachine7_fifo_out_last, soc_litedramcore_bankmachine7_fifo_out_first, soc_litedramcore_bankmachine7_fifo_out_payload_addr, soc_litedramcore_bankmachine7_fifo_out_payload_we} = soc_litedramcore_bankmachine7_syncfifo7_dout;
assign {soc_litedramcore_bankmachine7_fifo_out_last, soc_litedramcore_bankmachine7_fifo_out_first, soc_litedramcore_bankmachine7_fifo_out_payload_addr, soc_litedramcore_bankmachine7_fifo_out_payload_we} = soc_litedramcore_bankmachine7_syncfifo7_dout;
assign soc_litedramcore_bankmachine7_sink_ready = soc_litedramcore_bankmachine7_syncfifo7_writable;
assign soc_litedramcore_bankmachine7_syncfifo7_we = soc_litedramcore_bankmachine7_sink_valid;
assign soc_litedramcore_bankmachine7_fifo_in_first = soc_litedramcore_bankmachine7_sink_first;
assign soc_litedramcore_bankmachine7_fifo_in_last = soc_litedramcore_bankmachine7_sink_last;
assign soc_litedramcore_bankmachine7_fifo_in_payload_we = soc_litedramcore_bankmachine7_sink_payload_we;
assign soc_litedramcore_bankmachine7_fifo_in_payload_addr = soc_litedramcore_bankmachine7_sink_payload_addr;
assign soc_litedramcore_bankmachine7_source_valid = soc_litedramcore_bankmachine7_syncfifo7_readable;
assign soc_litedramcore_bankmachine7_source_first = soc_litedramcore_bankmachine7_fifo_out_first;
assign soc_litedramcore_bankmachine7_source_last = soc_litedramcore_bankmachine7_fifo_out_last;
assign soc_litedramcore_bankmachine7_source_payload_we = soc_litedramcore_bankmachine7_fifo_out_payload_we;
assign soc_litedramcore_bankmachine7_source_payload_addr = soc_litedramcore_bankmachine7_fifo_out_payload_addr;
assign soc_litedramcore_bankmachine7_syncfifo7_re = soc_litedramcore_bankmachine7_source_ready;
always @(*) begin
    soc_litedramcore_bankmachine7_wrport_adr <= 4'd0;
    if (soc_litedramcore_bankmachine7_replace) begin
        soc_litedramcore_bankmachine7_wrport_adr <= (soc_litedramcore_bankmachine7_produce - 1'd1);
    end else begin
        soc_litedramcore_bankmachine7_wrport_adr <= soc_litedramcore_bankmachine7_produce;
    end
end
assign soc_litedramcore_bankmachine7_wrport_dat_w = soc_litedramcore_bankmachine7_syncfifo7_din;
assign soc_litedramcore_bankmachine7_wrport_we = (soc_litedramcore_bankmachine7_syncfifo7_we & (soc_litedramcore_bankmachine7_syncfifo7_writable | soc_litedramcore_bankmachine7_replace));
assign soc_litedramcore_bankmachine7_do_read = (soc_litedramcore_bankmachine7_syncfifo7_readable & soc_litedramcore_bankmachine7_syncfifo7_re);
assign soc_litedramcore_bankmachine7_rdport_adr = soc_litedramcore_bankmachine7_consume;
assign soc_litedramcore_bankmachine7_syncfifo7_dout = soc_litedramcore_bankmachine7_rdport_dat_r;
assign soc_litedramcore_bankmachine7_syncfifo7_writable = (soc_litedramcore_bankmachine7_level != 5'd16);
assign soc_litedramcore_bankmachine7_syncfifo7_readable = (soc_litedramcore_bankmachine7_level != 1'd0);
assign soc_litedramcore_bankmachine7_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine7_pipe_valid_source_valid) | soc_litedramcore_bankmachine7_pipe_valid_source_ready);
assign soc_litedramcore_bankmachine7_pipe_valid_sink_valid = soc_litedramcore_bankmachine7_sink_sink_valid;
assign soc_litedramcore_bankmachine7_sink_sink_ready = soc_litedramcore_bankmachine7_pipe_valid_sink_ready;
assign soc_litedramcore_bankmachine7_pipe_valid_sink_first = soc_litedramcore_bankmachine7_sink_sink_first;
assign soc_litedramcore_bankmachine7_pipe_valid_sink_last = soc_litedramcore_bankmachine7_sink_sink_last;
assign soc_litedramcore_bankmachine7_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine7_sink_sink_payload_we;
assign soc_litedramcore_bankmachine7_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine7_sink_sink_payload_addr;
assign soc_litedramcore_bankmachine7_source_source_valid = soc_litedramcore_bankmachine7_pipe_valid_source_valid;
assign soc_litedramcore_bankmachine7_pipe_valid_source_ready = soc_litedramcore_bankmachine7_source_source_ready;
assign soc_litedramcore_bankmachine7_source_source_first = soc_litedramcore_bankmachine7_pipe_valid_source_first;
assign soc_litedramcore_bankmachine7_source_source_last = soc_litedramcore_bankmachine7_pipe_valid_source_last;
assign soc_litedramcore_bankmachine7_source_source_payload_we = soc_litedramcore_bankmachine7_pipe_valid_source_payload_we;
assign soc_litedramcore_bankmachine7_source_source_payload_addr = soc_litedramcore_bankmachine7_pipe_valid_source_payload_addr;
always @(*) begin
    bankmachine7_next_state <= 4'd0;
    bankmachine7_next_state <= bankmachine7_state;
    case (bankmachine7_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
                if (soc_litedramcore_bankmachine7_cmd_ready) begin
                    bankmachine7_next_state <= 3'd5;
                end
            end
        end
        2'd2: begin
            if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
                bankmachine7_next_state <= 3'd5;
            end
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine7_trccon_ready) begin
                if (soc_litedramcore_bankmachine7_cmd_ready) begin
                    bankmachine7_next_state <= 3'd7;
                end
            end
        end
        3'd4: begin
            if ((~soc_litedramcore_bankmachine7_refresh_req)) begin
                bankmachine7_next_state <= 1'd0;
            end
        end
        3'd5: begin
            bankmachine7_next_state <= 3'd6;
        end
        3'd6: begin
            bankmachine7_next_state <= 2'd3;
        end
        3'd7: begin
            bankmachine7_next_state <= 4'd8;
        end
        4'd8: begin
            bankmachine7_next_state <= 1'd0;
        end
        default: begin
            if (soc_litedramcore_bankmachine7_refresh_req) begin
                bankmachine7_next_state <= 3'd4;
            end else begin
                if (soc_litedramcore_bankmachine7_source_source_valid) begin
                    if (soc_litedramcore_bankmachine7_row_opened) begin
                        if (soc_litedramcore_bankmachine7_row_hit) begin
                            if ((soc_litedramcore_bankmachine7_cmd_ready & soc_litedramcore_bankmachine7_auto_precharge)) begin
                                bankmachine7_next_state <= 2'd2;
                            end
                        end else begin
                            bankmachine7_next_state <= 1'd1;
                        end
                    end else begin
                        bankmachine7_next_state <= 2'd3;
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
    case (bankmachine7_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
            if (soc_litedramcore_bankmachine7_twtpcon_ready) begin
                soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
            end
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine7_row_open <= 1'd0;
    case (bankmachine7_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine7_trccon_ready) begin
                soc_litedramcore_bankmachine7_row_open <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine7_cmd_valid <= 1'd0;
    case (bankmachine7_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
                soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine7_trccon_ready) begin
                soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine7_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine7_source_source_valid) begin
                    if (soc_litedramcore_bankmachine7_row_opened) begin
                        if (soc_litedramcore_bankmachine7_row_hit) begin
                            soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine7_row_close <= 1'd0;
    case (bankmachine7_state)
        1'd1: begin
            soc_litedramcore_bankmachine7_row_close <= 1'd1;
        end
        2'd2: begin
            soc_litedramcore_bankmachine7_row_close <= 1'd1;
        end
        2'd3: begin
        end
        3'd4: begin
            soc_litedramcore_bankmachine7_row_close <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
    case (bankmachine7_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine7_trccon_ready) begin
                soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
    case (bankmachine7_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine7_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine7_source_source_valid) begin
                    if (soc_litedramcore_bankmachine7_row_opened) begin
                        if (soc_litedramcore_bankmachine7_row_hit) begin
                            soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
    case (bankmachine7_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
                soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine7_trccon_ready) begin
                soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
    case (bankmachine7_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
                soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine7_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine7_source_source_valid) begin
                    if (soc_litedramcore_bankmachine7_row_opened) begin
                        if (soc_litedramcore_bankmachine7_row_hit) begin
                            if (soc_litedramcore_bankmachine7_source_source_payload_we) begin
                                soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
    case (bankmachine7_state)
        1'd1: begin
            if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
                soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (soc_litedramcore_bankmachine7_trccon_ready) begin
                soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
            end
        end
        3'd4: begin
            soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
    case (bankmachine7_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine7_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine7_source_source_valid) begin
                    if (soc_litedramcore_bankmachine7_row_opened) begin
                        if (soc_litedramcore_bankmachine7_row_hit) begin
                            if (soc_litedramcore_bankmachine7_source_source_payload_we) begin
                            end else begin
                                soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
    case (bankmachine7_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine7_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine7_source_source_valid) begin
                    if (soc_litedramcore_bankmachine7_row_opened) begin
                        if (soc_litedramcore_bankmachine7_row_hit) begin
                            if (soc_litedramcore_bankmachine7_source_source_payload_we) begin
                                soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
    case (bankmachine7_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine7_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine7_source_source_valid) begin
                    if (soc_litedramcore_bankmachine7_row_opened) begin
                        if (soc_litedramcore_bankmachine7_row_hit) begin
                            if (soc_litedramcore_bankmachine7_source_source_payload_we) begin
                                soc_litedramcore_bankmachine7_req_wdata_ready <= soc_litedramcore_bankmachine7_cmd_ready;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
    case (bankmachine7_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        default: begin
            if (soc_litedramcore_bankmachine7_refresh_req) begin
            end else begin
                if (soc_litedramcore_bankmachine7_source_source_valid) begin
                    if (soc_litedramcore_bankmachine7_row_opened) begin
                        if (soc_litedramcore_bankmachine7_row_hit) begin
                            if (soc_litedramcore_bankmachine7_source_source_payload_we) begin
                            end else begin
                                soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
assign soc_litedramcore_trrdcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we)));
assign soc_litedramcore_tfawcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we)));
assign soc_litedramcore_ras_allowed = (soc_litedramcore_trrdcon_ready & soc_litedramcore_tfawcon_ready);
assign soc_litedramcore_tccdcon_valid = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_cmd_payload_is_write | soc_litedramcore_choose_req_cmd_payload_is_read));
assign soc_litedramcore_cas_allowed = soc_litedramcore_tccdcon_ready;
assign soc_litedramcore_twtrcon_valid = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
assign soc_litedramcore_read_available = ((((((((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_payload_is_read) | (soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_payload_is_read)) | (soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_payload_is_read)) | (soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_payload_is_read)) | (soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_payload_is_read)) | (soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_payload_is_read)) | (soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_payload_is_read)) | (soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_payload_is_read));
assign soc_litedramcore_write_available = ((((((((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_payload_is_write) | (soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_payload_is_write)) | (soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_payload_is_write)) | (soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_payload_is_write)) | (soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_payload_is_write)) | (soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_payload_is_write)) | (soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_payload_is_write)) | (soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_payload_is_write));
assign soc_litedramcore_max_time0 = (soc_litedramcore_time0 == 1'd0);
assign soc_litedramcore_max_time1 = (soc_litedramcore_time1 == 1'd0);
assign soc_litedramcore_bankmachine0_refresh_req = soc_litedramcore_cmd_valid;
assign soc_litedramcore_bankmachine1_refresh_req = soc_litedramcore_cmd_valid;
assign soc_litedramcore_bankmachine2_refresh_req = soc_litedramcore_cmd_valid;
assign soc_litedramcore_bankmachine3_refresh_req = soc_litedramcore_cmd_valid;
assign soc_litedramcore_bankmachine4_refresh_req = soc_litedramcore_cmd_valid;
assign soc_litedramcore_bankmachine5_refresh_req = soc_litedramcore_cmd_valid;
assign soc_litedramcore_bankmachine6_refresh_req = soc_litedramcore_cmd_valid;
assign soc_litedramcore_bankmachine7_refresh_req = soc_litedramcore_cmd_valid;
assign soc_litedramcore_go_to_refresh = (((((((soc_litedramcore_bankmachine0_refresh_gnt & soc_litedramcore_bankmachine1_refresh_gnt) & soc_litedramcore_bankmachine2_refresh_gnt) & soc_litedramcore_bankmachine3_refresh_gnt) & soc_litedramcore_bankmachine4_refresh_gnt) & soc_litedramcore_bankmachine5_refresh_gnt) & soc_litedramcore_bankmachine6_refresh_gnt) & soc_litedramcore_bankmachine7_refresh_gnt);
assign soc_litedramcore_interface_rdata = {soc_litedramcore_dfi_p3_rddata, soc_litedramcore_dfi_p2_rddata, soc_litedramcore_dfi_p1_rddata, soc_litedramcore_dfi_p0_rddata};
assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata;
assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata;
assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata;
assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata;
assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we);
assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we);
assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we);
assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we);
always @(*) begin
    soc_litedramcore_choose_cmd_valids <= 8'd0;
    soc_litedramcore_choose_cmd_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
    soc_litedramcore_choose_cmd_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
    soc_litedramcore_choose_cmd_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
    soc_litedramcore_choose_cmd_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
    soc_litedramcore_choose_cmd_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
    soc_litedramcore_choose_cmd_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
    soc_litedramcore_choose_cmd_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
    soc_litedramcore_choose_cmd_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
end
assign soc_litedramcore_choose_cmd_request = soc_litedramcore_choose_cmd_valids;
assign soc_litedramcore_choose_cmd_cmd_valid = rhs_self0;
assign soc_litedramcore_choose_cmd_cmd_payload_a = rhs_self1;
assign soc_litedramcore_choose_cmd_cmd_payload_ba = rhs_self2;
assign soc_litedramcore_choose_cmd_cmd_payload_is_read = rhs_self3;
assign soc_litedramcore_choose_cmd_cmd_payload_is_write = rhs_self4;
assign soc_litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_self5;
always @(*) begin
    soc_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
    if (soc_litedramcore_choose_cmd_cmd_valid) begin
        soc_litedramcore_choose_cmd_cmd_payload_cas <= t_self0;
    end
end
always @(*) begin
    soc_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
    if (soc_litedramcore_choose_cmd_cmd_valid) begin
        soc_litedramcore_choose_cmd_cmd_payload_ras <= t_self1;
    end
end
always @(*) begin
    soc_litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
    if (soc_litedramcore_choose_cmd_cmd_valid) begin
        soc_litedramcore_choose_cmd_cmd_payload_we <= t_self2;
    end
end
always @(*) begin
    soc_litedramcore_bankmachine0_cmd_ready <= 1'd0;
    if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd0))) begin
        soc_litedramcore_bankmachine0_cmd_ready <= 1'd1;
    end
    if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd0))) begin
        soc_litedramcore_bankmachine0_cmd_ready <= 1'd1;
    end
end
always @(*) begin
    soc_litedramcore_bankmachine1_cmd_ready <= 1'd0;
    if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd1))) begin
        soc_litedramcore_bankmachine1_cmd_ready <= 1'd1;
    end
    if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd1))) begin
        soc_litedramcore_bankmachine1_cmd_ready <= 1'd1;
    end
end
always @(*) begin
    soc_litedramcore_bankmachine2_cmd_ready <= 1'd0;
    if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd2))) begin
        soc_litedramcore_bankmachine2_cmd_ready <= 1'd1;
    end
    if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd2))) begin
        soc_litedramcore_bankmachine2_cmd_ready <= 1'd1;
    end
end
always @(*) begin
    soc_litedramcore_bankmachine3_cmd_ready <= 1'd0;
    if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd3))) begin
        soc_litedramcore_bankmachine3_cmd_ready <= 1'd1;
    end
    if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd3))) begin
        soc_litedramcore_bankmachine3_cmd_ready <= 1'd1;
    end
end
always @(*) begin
    soc_litedramcore_bankmachine4_cmd_ready <= 1'd0;
    if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd4))) begin
        soc_litedramcore_bankmachine4_cmd_ready <= 1'd1;
    end
    if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd4))) begin
        soc_litedramcore_bankmachine4_cmd_ready <= 1'd1;
    end
end
always @(*) begin
    soc_litedramcore_bankmachine5_cmd_ready <= 1'd0;
    if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd5))) begin
        soc_litedramcore_bankmachine5_cmd_ready <= 1'd1;
    end
    if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd5))) begin
        soc_litedramcore_bankmachine5_cmd_ready <= 1'd1;
    end
end
always @(*) begin
    soc_litedramcore_bankmachine6_cmd_ready <= 1'd0;
    if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd6))) begin
        soc_litedramcore_bankmachine6_cmd_ready <= 1'd1;
    end
    if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd6))) begin
        soc_litedramcore_bankmachine6_cmd_ready <= 1'd1;
    end
end
always @(*) begin
    soc_litedramcore_bankmachine7_cmd_ready <= 1'd0;
    if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd7))) begin
        soc_litedramcore_bankmachine7_cmd_ready <= 1'd1;
    end
    if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd7))) begin
        soc_litedramcore_bankmachine7_cmd_ready <= 1'd1;
    end
end
assign soc_litedramcore_choose_cmd_ce = (soc_litedramcore_choose_cmd_cmd_ready | (~soc_litedramcore_choose_cmd_cmd_valid));
always @(*) begin
    soc_litedramcore_choose_req_valids <= 8'd0;
    soc_litedramcore_choose_req_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
    soc_litedramcore_choose_req_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
    soc_litedramcore_choose_req_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
    soc_litedramcore_choose_req_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
    soc_litedramcore_choose_req_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
    soc_litedramcore_choose_req_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
    soc_litedramcore_choose_req_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
    soc_litedramcore_choose_req_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
end
assign soc_litedramcore_choose_req_request = soc_litedramcore_choose_req_valids;
assign soc_litedramcore_choose_req_cmd_valid = rhs_self6;
assign soc_litedramcore_choose_req_cmd_payload_a = rhs_self7;
assign soc_litedramcore_choose_req_cmd_payload_ba = rhs_self8;
assign soc_litedramcore_choose_req_cmd_payload_is_read = rhs_self9;
assign soc_litedramcore_choose_req_cmd_payload_is_write = rhs_self10;
assign soc_litedramcore_choose_req_cmd_payload_is_cmd = rhs_self11;
always @(*) begin
    soc_litedramcore_choose_req_cmd_payload_cas <= 1'd0;
    if (soc_litedramcore_choose_req_cmd_valid) begin
        soc_litedramcore_choose_req_cmd_payload_cas <= t_self3;
    end
end
always @(*) begin
    soc_litedramcore_choose_req_cmd_payload_ras <= 1'd0;
    if (soc_litedramcore_choose_req_cmd_valid) begin
        soc_litedramcore_choose_req_cmd_payload_ras <= t_self4;
    end
end
always @(*) begin
    soc_litedramcore_choose_req_cmd_payload_we <= 1'd0;
    if (soc_litedramcore_choose_req_cmd_valid) begin
        soc_litedramcore_choose_req_cmd_payload_we <= t_self5;
    end
end
assign soc_litedramcore_choose_req_ce = (soc_litedramcore_choose_req_cmd_ready | (~soc_litedramcore_choose_req_cmd_valid));
assign soc_litedramcore_dfi_p0_reset_n = 1'd1;
assign soc_litedramcore_dfi_p0_cke = {1{soc_litedramcore_steerer4}};
assign soc_litedramcore_dfi_p0_odt = {1{soc_litedramcore_steerer5}};
assign soc_litedramcore_dfi_p1_reset_n = 1'd1;
assign soc_litedramcore_dfi_p1_cke = {1{soc_litedramcore_steerer6}};
assign soc_litedramcore_dfi_p1_odt = {1{soc_litedramcore_steerer7}};
assign soc_litedramcore_dfi_p2_reset_n = 1'd1;
assign soc_litedramcore_dfi_p2_cke = {1{soc_litedramcore_steerer8}};
assign soc_litedramcore_dfi_p2_odt = {1{soc_litedramcore_steerer9}};
assign soc_litedramcore_dfi_p3_reset_n = 1'd1;
assign soc_litedramcore_dfi_p3_cke = {1{soc_litedramcore_steerer10}};
assign soc_litedramcore_dfi_p3_odt = {1{soc_litedramcore_steerer11}};
assign soc_litedramcore_tfawcon_count = ((((soc_litedramcore_tfawcon_window[0] + soc_litedramcore_tfawcon_window[1]) + soc_litedramcore_tfawcon_window[2]) + soc_litedramcore_tfawcon_window[3]) + soc_litedramcore_tfawcon_window[4]);
always @(*) begin
    multiplexer_next_state <= 4'd0;
    multiplexer_next_state <= multiplexer_state;
    case (multiplexer_state)
        1'd1: begin
            if (soc_litedramcore_read_available) begin
                if (((~soc_litedramcore_write_available) | soc_litedramcore_max_time1)) begin
                    multiplexer_next_state <= 2'd3;
                end
            end
            if (soc_litedramcore_go_to_refresh) begin
                multiplexer_next_state <= 2'd2;
            end
        end
        2'd2: begin
            if (soc_litedramcore_cmd_last) begin
                multiplexer_next_state <= 1'd0;
            end
        end
        2'd3: begin
            if (soc_litedramcore_twtrcon_ready) begin
                multiplexer_next_state <= 1'd0;
            end
        end
        3'd4: begin
            multiplexer_next_state <= 3'd5;
        end
        3'd5: begin
            multiplexer_next_state <= 3'd6;
        end
        3'd6: begin
            multiplexer_next_state <= 3'd7;
        end
        3'd7: begin
            multiplexer_next_state <= 4'd8;
        end
        4'd8: begin
            multiplexer_next_state <= 4'd9;
        end
        4'd9: begin
            multiplexer_next_state <= 4'd10;
        end
        4'd10: begin
            multiplexer_next_state <= 1'd1;
        end
        default: begin
            if (soc_litedramcore_write_available) begin
                if (((~soc_litedramcore_read_available) | soc_litedramcore_max_time0)) begin
                    multiplexer_next_state <= 3'd4;
                end
            end
            if (soc_litedramcore_go_to_refresh) begin
                multiplexer_next_state <= 2'd2;
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_choose_req_cmd_ready <= 1'd0;
    case (multiplexer_state)
        1'd1: begin
            if (1'd0) begin
                soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
            end else begin
                soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (1'd0) begin
                soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
            end else begin
                soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed;
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_en1 <= 1'd0;
    case (multiplexer_state)
        1'd1: begin
            soc_litedramcore_en1 <= 1'd1;
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_steerer0 <= 2'd0;
    case (multiplexer_state)
        1'd1: begin
            soc_litedramcore_steerer0 <= 1'd0;
            if (1'd0) begin
                soc_litedramcore_steerer0 <= 2'd2;
            end
            if (1'd0) begin
                soc_litedramcore_steerer0 <= 1'd1;
            end
        end
        2'd2: begin
            soc_litedramcore_steerer0 <= 2'd3;
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            soc_litedramcore_steerer0 <= 1'd0;
            if (1'd0) begin
                soc_litedramcore_steerer0 <= 2'd2;
            end
            if (1'd0) begin
                soc_litedramcore_steerer0 <= 1'd1;
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_steerer1 <= 2'd0;
    case (multiplexer_state)
        1'd1: begin
            soc_litedramcore_steerer1 <= 1'd0;
            if (1'd0) begin
                soc_litedramcore_steerer1 <= 2'd2;
            end
            if (1'd0) begin
                soc_litedramcore_steerer1 <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            soc_litedramcore_steerer1 <= 1'd0;
            if (1'd0) begin
                soc_litedramcore_steerer1 <= 2'd2;
            end
            if (1'd1) begin
                soc_litedramcore_steerer1 <= 1'd1;
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_steerer2 <= 2'd0;
    case (multiplexer_state)
        1'd1: begin
            soc_litedramcore_steerer2 <= 1'd0;
            if (1'd0) begin
                soc_litedramcore_steerer2 <= 2'd2;
            end
            if (1'd1) begin
                soc_litedramcore_steerer2 <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            soc_litedramcore_steerer2 <= 1'd0;
            if (1'd1) begin
                soc_litedramcore_steerer2 <= 2'd2;
            end
            if (1'd0) begin
                soc_litedramcore_steerer2 <= 1'd1;
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_choose_cmd_want_activates <= 1'd0;
    case (multiplexer_state)
        1'd1: begin
            if (1'd0) begin
            end else begin
                soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (1'd0) begin
            end else begin
                soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed;
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_steerer3 <= 2'd0;
    case (multiplexer_state)
        1'd1: begin
            soc_litedramcore_steerer3 <= 1'd0;
            if (1'd1) begin
                soc_litedramcore_steerer3 <= 2'd2;
            end
            if (1'd0) begin
                soc_litedramcore_steerer3 <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            soc_litedramcore_steerer3 <= 1'd0;
            if (1'd0) begin
                soc_litedramcore_steerer3 <= 2'd2;
            end
            if (1'd0) begin
                soc_litedramcore_steerer3 <= 1'd1;
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_en0 <= 1'd0;
    case (multiplexer_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            soc_litedramcore_en0 <= 1'd1;
        end
    endcase
end
always @(*) begin
    soc_litedramcore_choose_cmd_cmd_ready <= 1'd0;
    case (multiplexer_state)
        1'd1: begin
            if (1'd0) begin
            end else begin
                soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed);
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (1'd0) begin
            end else begin
                soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed);
            end
        end
    endcase
end
always @(*) begin
    soc_litedramcore_choose_req_want_reads <= 1'd0;
    case (multiplexer_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            soc_litedramcore_choose_req_want_reads <= 1'd1;
        end
    endcase
end
always @(*) begin
    soc_litedramcore_cmd_ready <= 1'd0;
    case (multiplexer_state)
        1'd1: begin
        end
        2'd2: begin
            soc_litedramcore_cmd_ready <= 1'd1;
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    soc_litedramcore_choose_req_want_writes <= 1'd0;
    case (multiplexer_state)
        1'd1: begin
            soc_litedramcore_choose_req_want_writes <= 1'd1;
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
assign roundrobin0_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
assign roundrobin0_ce = ((~soc_litedramcore_interface_bank0_valid) & (~soc_litedramcore_interface_bank0_lock));
assign soc_litedramcore_interface_bank0_addr = rhs_self12;
assign soc_litedramcore_interface_bank0_we = rhs_self13;
assign soc_litedramcore_interface_bank0_valid = rhs_self14;
assign roundrobin1_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
assign roundrobin1_ce = ((~soc_litedramcore_interface_bank1_valid) & (~soc_litedramcore_interface_bank1_lock));
assign soc_litedramcore_interface_bank1_addr = rhs_self15;
assign soc_litedramcore_interface_bank1_we = rhs_self16;
assign soc_litedramcore_interface_bank1_valid = rhs_self17;
assign roundrobin2_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
assign roundrobin2_ce = ((~soc_litedramcore_interface_bank2_valid) & (~soc_litedramcore_interface_bank2_lock));
assign soc_litedramcore_interface_bank2_addr = rhs_self18;
assign soc_litedramcore_interface_bank2_we = rhs_self19;
assign soc_litedramcore_interface_bank2_valid = rhs_self20;
assign roundrobin3_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
assign roundrobin3_ce = ((~soc_litedramcore_interface_bank3_valid) & (~soc_litedramcore_interface_bank3_lock));
assign soc_litedramcore_interface_bank3_addr = rhs_self21;
assign soc_litedramcore_interface_bank3_we = rhs_self22;
assign soc_litedramcore_interface_bank3_valid = rhs_self23;
assign roundrobin4_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
assign roundrobin4_ce = ((~soc_litedramcore_interface_bank4_valid) & (~soc_litedramcore_interface_bank4_lock));
assign soc_litedramcore_interface_bank4_addr = rhs_self24;
assign soc_litedramcore_interface_bank4_we = rhs_self25;
assign soc_litedramcore_interface_bank4_valid = rhs_self26;
assign roundrobin5_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
assign roundrobin5_ce = ((~soc_litedramcore_interface_bank5_valid) & (~soc_litedramcore_interface_bank5_lock));
assign soc_litedramcore_interface_bank5_addr = rhs_self27;
assign soc_litedramcore_interface_bank5_we = rhs_self28;
assign soc_litedramcore_interface_bank5_valid = rhs_self29;
assign roundrobin6_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
assign roundrobin6_ce = ((~soc_litedramcore_interface_bank6_valid) & (~soc_litedramcore_interface_bank6_lock));
assign soc_litedramcore_interface_bank6_addr = rhs_self30;
assign soc_litedramcore_interface_bank6_we = rhs_self31;
assign soc_litedramcore_interface_bank6_valid = rhs_self32;
assign roundrobin7_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid)};
assign roundrobin7_ce = ((~soc_litedramcore_interface_bank7_valid) & (~soc_litedramcore_interface_bank7_lock));
assign soc_litedramcore_interface_bank7_addr = rhs_self33;
assign soc_litedramcore_interface_bank7_we = rhs_self34;
assign soc_litedramcore_interface_bank7_valid = rhs_self35;
assign soc_user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank0_ready)) | (((roundrobin1_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank1_ready)) | (((roundrobin2_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank2_ready)) | (((roundrobin3_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank3_ready)) | (((roundrobin4_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank4_ready)) | (((roundrobin5_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank5_ready)) | (((roundrobin6_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank6_ready)) | (((roundrobin7_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0)))))) & soc_litedramcore_interface_bank7_ready));
assign soc_user_port_wdata_ready = new_master_wdata_ready1;
assign soc_user_port_rdata_valid = new_master_rdata_valid8;
always @(*) begin
    soc_litedramcore_interface_wdata <= 128'd0;
    case ({new_master_wdata_ready1})
        1'd1: begin
            soc_litedramcore_interface_wdata <= soc_user_port_wdata_payload_data;
        end
        default: begin
            soc_litedramcore_interface_wdata <= 1'd0;
        end
    endcase
end
always @(*) begin
    soc_litedramcore_interface_wdata_we <= 16'd0;
    case ({new_master_wdata_ready1})
        1'd1: begin
            soc_litedramcore_interface_wdata_we <= soc_user_port_wdata_payload_we;
        end
        default: begin
            soc_litedramcore_interface_wdata_we <= 1'd0;
        end
    endcase
end
assign soc_user_port_rdata_payload_data = soc_litedramcore_interface_rdata;
assign roundrobin0_grant = 1'd0;
assign roundrobin1_grant = 1'd0;
assign roundrobin2_grant = 1'd0;
assign roundrobin3_grant = 1'd0;
assign roundrobin4_grant = 1'd0;
assign roundrobin5_grant = 1'd0;
assign roundrobin6_grant = 1'd0;
assign roundrobin7_grant = 1'd0;
always @(*) begin
    next_state <= 2'd0;
    next_state <= state;
    case (state)
        1'd1: begin
            next_state <= 2'd2;
        end
        2'd2: begin
            next_state <= 1'd0;
        end
        default: begin
            if ((interface0_cyc & interface0_stb)) begin
                next_state <= 1'd1;
            end
        end
    endcase
end
always @(*) begin
    interface1_we_next_value3 <= 1'd0;
    case (state)
        1'd1: begin
            interface1_we_next_value3 <= 1'd0;
        end
        2'd2: begin
        end
        default: begin
            if ((interface0_cyc & interface0_stb)) begin
                interface1_we_next_value3 <= (interface0_we & (interface0_sel != 1'd0));
            end
        end
    endcase
end
always @(*) begin
    interface1_we_next_value_ce3 <= 1'd0;
    case (state)
        1'd1: begin
            interface1_we_next_value_ce3 <= 1'd1;
        end
        2'd2: begin
        end
        default: begin
            if ((interface0_cyc & interface0_stb)) begin
                interface1_we_next_value_ce3 <= 1'd1;
            end
        end
    endcase
end
always @(*) begin
    interface1_dat_w_next_value0 <= 32'd0;
    case (state)
        1'd1: begin
        end
        2'd2: begin
        end
        default: begin
            interface1_dat_w_next_value0 <= interface0_dat_w;
        end
    endcase
end
always @(*) begin
    interface0_ack <= 1'd0;
    case (state)
        1'd1: begin
        end
        2'd2: begin
            interface0_ack <= 1'd1;
        end
        default: begin
        end
    endcase
end
always @(*) begin
    interface1_dat_w_next_value_ce0 <= 1'd0;
    case (state)
        1'd1: begin
        end
        2'd2: begin
        end
        default: begin
            interface1_dat_w_next_value_ce0 <= 1'd1;
        end
    endcase
end
always @(*) begin
    interface0_dat_r <= 32'd0;
    case (state)
        1'd1: begin
        end
        2'd2: begin
            interface0_dat_r <= interface1_dat_r;
        end
        default: begin
        end
    endcase
end
always @(*) begin
    interface1_adr_next_value1 <= 14'd0;
    case (state)
        1'd1: begin
            interface1_adr_next_value1 <= 1'd0;
        end
        2'd2: begin
        end
        default: begin
            if ((interface0_cyc & interface0_stb)) begin
                interface1_adr_next_value1 <= interface0_adr;
            end
        end
    endcase
end
always @(*) begin
    interface1_adr_next_value_ce1 <= 1'd0;
    case (state)
        1'd1: begin
            interface1_adr_next_value_ce1 <= 1'd1;
        end
        2'd2: begin
        end
        default: begin
            if ((interface0_cyc & interface0_stb)) begin
                interface1_adr_next_value_ce1 <= 1'd1;
            end
        end
    endcase
end
always @(*) begin
    interface1_re_next_value2 <= 1'd0;
    case (state)
        1'd1: begin
            interface1_re_next_value2 <= 1'd0;
        end
        2'd2: begin
        end
        default: begin
            if ((interface0_cyc & interface0_stb)) begin
                interface1_re_next_value2 <= ((~interface0_we) & (interface0_sel != 1'd0));
            end
        end
    endcase
end
always @(*) begin
    interface1_re_next_value_ce2 <= 1'd0;
    case (state)
        1'd1: begin
            interface1_re_next_value_ce2 <= 1'd1;
        end
        2'd2: begin
        end
        default: begin
            if ((interface0_cyc & interface0_stb)) begin
                interface1_re_next_value_ce2 <= 1'd1;
            end
        end
    endcase
end
assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
always @(*) begin
    csrbank0_init_done0_re <= 1'd0;
    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
        csrbank0_init_done0_re <= interface0_bank_bus_we;
    end
end
always @(*) begin
    csrbank0_init_done0_we <= 1'd0;
    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
        csrbank0_init_done0_we <= interface0_bank_bus_re;
    end
end
assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
always @(*) begin
    csrbank0_init_error0_we <= 1'd0;
    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
        csrbank0_init_error0_we <= interface0_bank_bus_re;
    end
end
always @(*) begin
    csrbank0_init_error0_re <= 1'd0;
    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
        csrbank0_init_error0_re <= interface0_bank_bus_we;
    end
end
assign csrbank0_init_done0_w = soc_init_done_storage;
assign csrbank0_init_error0_w = soc_init_error_storage;
assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0];
always @(*) begin
    csrbank1_dfii_control0_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
        csrbank1_dfii_control0_we <= interface1_bank_bus_re;
    end
end
always @(*) begin
    csrbank1_dfii_control0_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
        csrbank1_dfii_control0_re <= interface1_bank_bus_we;
    end
end
assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
    csrbank1_dfii_pi0_command0_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
        csrbank1_dfii_pi0_command0_re <= interface1_bank_bus_we;
    end
end
always @(*) begin
    csrbank1_dfii_pi0_command0_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
        csrbank1_dfii_pi0_command0_we <= interface1_bank_bus_re;
    end
end
assign soc_litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0];
always @(*) begin
    soc_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
        soc_litedramcore_phaseinjector0_command_issue_we <= interface1_bank_bus_re;
    end
end
always @(*) begin
    soc_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
        soc_litedramcore_phaseinjector0_command_issue_re <= interface1_bank_bus_we;
    end
end
assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[13:0];
always @(*) begin
    csrbank1_dfii_pi0_address0_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
        csrbank1_dfii_pi0_address0_we <= interface1_bank_bus_re;
    end
end
always @(*) begin
    csrbank1_dfii_pi0_address0_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
        csrbank1_dfii_pi0_address0_re <= interface1_bank_bus_we;
    end
end
assign csrbank1_dfii_pi0_baddress0_r = interface1_bank_bus_dat_w[2:0];
always @(*) begin
    csrbank1_dfii_pi0_baddress0_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
        csrbank1_dfii_pi0_baddress0_we <= interface1_bank_bus_re;
    end
end
always @(*) begin
    csrbank1_dfii_pi0_baddress0_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
        csrbank1_dfii_pi0_baddress0_re <= interface1_bank_bus_we;
    end
end
assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w;
always @(*) begin
    csrbank1_dfii_pi0_wrdata0_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
        csrbank1_dfii_pi0_wrdata0_re <= interface1_bank_bus_we;
    end
end
always @(*) begin
    csrbank1_dfii_pi0_wrdata0_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
        csrbank1_dfii_pi0_wrdata0_we <= interface1_bank_bus_re;
    end
end
assign csrbank1_dfii_pi0_rddata_r = interface1_bank_bus_dat_w;
always @(*) begin
    csrbank1_dfii_pi0_rddata_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
        csrbank1_dfii_pi0_rddata_we <= interface1_bank_bus_re;
    end
end
always @(*) begin
    csrbank1_dfii_pi0_rddata_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
        csrbank1_dfii_pi0_rddata_re <= interface1_bank_bus_we;
    end
end
assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
    csrbank1_dfii_pi1_command0_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
        csrbank1_dfii_pi1_command0_we <= interface1_bank_bus_re;
    end
end
always @(*) begin
    csrbank1_dfii_pi1_command0_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
        csrbank1_dfii_pi1_command0_re <= interface1_bank_bus_we;
    end
end
assign soc_litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0];
always @(*) begin
    soc_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
        soc_litedramcore_phaseinjector1_command_issue_re <= interface1_bank_bus_we;
    end
end
always @(*) begin
    soc_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
        soc_litedramcore_phaseinjector1_command_issue_we <= interface1_bank_bus_re;
    end
end
assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[13:0];
always @(*) begin
    csrbank1_dfii_pi1_address0_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
        csrbank1_dfii_pi1_address0_re <= interface1_bank_bus_we;
    end
end
always @(*) begin
    csrbank1_dfii_pi1_address0_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
        csrbank1_dfii_pi1_address0_we <= interface1_bank_bus_re;
    end
end
assign csrbank1_dfii_pi1_baddress0_r = interface1_bank_bus_dat_w[2:0];
always @(*) begin
    csrbank1_dfii_pi1_baddress0_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
        csrbank1_dfii_pi1_baddress0_we <= interface1_bank_bus_re;
    end
end
always @(*) begin
    csrbank1_dfii_pi1_baddress0_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
        csrbank1_dfii_pi1_baddress0_re <= interface1_bank_bus_we;
    end
end
assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w;
always @(*) begin
    csrbank1_dfii_pi1_wrdata0_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
        csrbank1_dfii_pi1_wrdata0_re <= interface1_bank_bus_we;
    end
end
always @(*) begin
    csrbank1_dfii_pi1_wrdata0_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
        csrbank1_dfii_pi1_wrdata0_we <= interface1_bank_bus_re;
    end
end
assign csrbank1_dfii_pi1_rddata_r = interface1_bank_bus_dat_w;
always @(*) begin
    csrbank1_dfii_pi1_rddata_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
        csrbank1_dfii_pi1_rddata_re <= interface1_bank_bus_we;
    end
end
always @(*) begin
    csrbank1_dfii_pi1_rddata_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
        csrbank1_dfii_pi1_rddata_we <= interface1_bank_bus_re;
    end
end
assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
    csrbank1_dfii_pi2_command0_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin
        csrbank1_dfii_pi2_command0_we <= interface1_bank_bus_re;
    end
end
always @(*) begin
    csrbank1_dfii_pi2_command0_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin
        csrbank1_dfii_pi2_command0_re <= interface1_bank_bus_we;
    end
end
assign soc_litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0];
always @(*) begin
    soc_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
        soc_litedramcore_phaseinjector2_command_issue_we <= interface1_bank_bus_re;
    end
end
always @(*) begin
    soc_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
        soc_litedramcore_phaseinjector2_command_issue_re <= interface1_bank_bus_we;
    end
end
assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[13:0];
always @(*) begin
    csrbank1_dfii_pi2_address0_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin
        csrbank1_dfii_pi2_address0_re <= interface1_bank_bus_we;
    end
end
always @(*) begin
    csrbank1_dfii_pi2_address0_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin
        csrbank1_dfii_pi2_address0_we <= interface1_bank_bus_re;
    end
end
assign csrbank1_dfii_pi2_baddress0_r = interface1_bank_bus_dat_w[2:0];
always @(*) begin
    csrbank1_dfii_pi2_baddress0_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin
        csrbank1_dfii_pi2_baddress0_re <= interface1_bank_bus_we;
    end
end
always @(*) begin
    csrbank1_dfii_pi2_baddress0_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin
        csrbank1_dfii_pi2_baddress0_we <= interface1_bank_bus_re;
    end
end
assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w;
always @(*) begin
    csrbank1_dfii_pi2_wrdata0_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin
        csrbank1_dfii_pi2_wrdata0_we <= interface1_bank_bus_re;
    end
end
always @(*) begin
    csrbank1_dfii_pi2_wrdata0_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin
        csrbank1_dfii_pi2_wrdata0_re <= interface1_bank_bus_we;
    end
end
assign csrbank1_dfii_pi2_rddata_r = interface1_bank_bus_dat_w;
always @(*) begin
    csrbank1_dfii_pi2_rddata_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin
        csrbank1_dfii_pi2_rddata_re <= interface1_bank_bus_we;
    end
end
always @(*) begin
    csrbank1_dfii_pi2_rddata_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin
        csrbank1_dfii_pi2_rddata_we <= interface1_bank_bus_re;
    end
end
assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
    csrbank1_dfii_pi3_command0_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin
        csrbank1_dfii_pi3_command0_re <= interface1_bank_bus_we;
    end
end
always @(*) begin
    csrbank1_dfii_pi3_command0_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin
        csrbank1_dfii_pi3_command0_we <= interface1_bank_bus_re;
    end
end
assign soc_litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0];
always @(*) begin
    soc_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin
        soc_litedramcore_phaseinjector3_command_issue_we <= interface1_bank_bus_re;
    end
end
always @(*) begin
    soc_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin
        soc_litedramcore_phaseinjector3_command_issue_re <= interface1_bank_bus_we;
    end
end
assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[13:0];
always @(*) begin
    csrbank1_dfii_pi3_address0_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin
        csrbank1_dfii_pi3_address0_we <= interface1_bank_bus_re;
    end
end
always @(*) begin
    csrbank1_dfii_pi3_address0_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin
        csrbank1_dfii_pi3_address0_re <= interface1_bank_bus_we;
    end
end
assign csrbank1_dfii_pi3_baddress0_r = interface1_bank_bus_dat_w[2:0];
always @(*) begin
    csrbank1_dfii_pi3_baddress0_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin
        csrbank1_dfii_pi3_baddress0_re <= interface1_bank_bus_we;
    end
end
always @(*) begin
    csrbank1_dfii_pi3_baddress0_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin
        csrbank1_dfii_pi3_baddress0_we <= interface1_bank_bus_re;
    end
end
assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w;
always @(*) begin
    csrbank1_dfii_pi3_wrdata0_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin
        csrbank1_dfii_pi3_wrdata0_we <= interface1_bank_bus_re;
    end
end
always @(*) begin
    csrbank1_dfii_pi3_wrdata0_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin
        csrbank1_dfii_pi3_wrdata0_re <= interface1_bank_bus_we;
    end
end
assign csrbank1_dfii_pi3_rddata_r = interface1_bank_bus_dat_w;
always @(*) begin
    csrbank1_dfii_pi3_rddata_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd24))) begin
        csrbank1_dfii_pi3_rddata_we <= interface1_bank_bus_re;
    end
end
always @(*) begin
    csrbank1_dfii_pi3_rddata_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd24))) begin
        csrbank1_dfii_pi3_rddata_re <= interface1_bank_bus_we;
    end
end
assign soc_litedramcore_sel = soc_litedramcore_storage[0];
assign soc_litedramcore_cke = soc_litedramcore_storage[1];
assign soc_litedramcore_odt = soc_litedramcore_storage[2];
assign soc_litedramcore_reset_n = soc_litedramcore_storage[3];
assign csrbank1_dfii_control0_w = soc_litedramcore_storage;
assign soc_litedramcore_phaseinjector0_csrfield_cs = soc_litedramcore_phaseinjector0_command_storage[0];
assign soc_litedramcore_phaseinjector0_csrfield_we = soc_litedramcore_phaseinjector0_command_storage[1];
assign soc_litedramcore_phaseinjector0_csrfield_cas = soc_litedramcore_phaseinjector0_command_storage[2];
assign soc_litedramcore_phaseinjector0_csrfield_ras = soc_litedramcore_phaseinjector0_command_storage[3];
assign soc_litedramcore_phaseinjector0_csrfield_wren = soc_litedramcore_phaseinjector0_command_storage[4];
assign soc_litedramcore_phaseinjector0_csrfield_rden = soc_litedramcore_phaseinjector0_command_storage[5];
assign soc_litedramcore_phaseinjector0_csrfield_cs_top = soc_litedramcore_phaseinjector0_command_storage[6];
assign soc_litedramcore_phaseinjector0_csrfield_cs_bottom = soc_litedramcore_phaseinjector0_command_storage[7];
assign csrbank1_dfii_pi0_command0_w = soc_litedramcore_phaseinjector0_command_storage;
assign csrbank1_dfii_pi0_address0_w = soc_litedramcore_phaseinjector0_address_storage;
assign csrbank1_dfii_pi0_baddress0_w = soc_litedramcore_phaseinjector0_baddress_storage;
assign csrbank1_dfii_pi0_wrdata0_w = soc_litedramcore_phaseinjector0_wrdata_storage;
assign csrbank1_dfii_pi0_rddata_w = soc_litedramcore_phaseinjector0_rddata_status;
assign soc_litedramcore_phaseinjector0_rddata_we = csrbank1_dfii_pi0_rddata_we;
assign soc_litedramcore_phaseinjector1_csrfield_cs = soc_litedramcore_phaseinjector1_command_storage[0];
assign soc_litedramcore_phaseinjector1_csrfield_we = soc_litedramcore_phaseinjector1_command_storage[1];
assign soc_litedramcore_phaseinjector1_csrfield_cas = soc_litedramcore_phaseinjector1_command_storage[2];
assign soc_litedramcore_phaseinjector1_csrfield_ras = soc_litedramcore_phaseinjector1_command_storage[3];
assign soc_litedramcore_phaseinjector1_csrfield_wren = soc_litedramcore_phaseinjector1_command_storage[4];
assign soc_litedramcore_phaseinjector1_csrfield_rden = soc_litedramcore_phaseinjector1_command_storage[5];
assign soc_litedramcore_phaseinjector1_csrfield_cs_top = soc_litedramcore_phaseinjector1_command_storage[6];
assign soc_litedramcore_phaseinjector1_csrfield_cs_bottom = soc_litedramcore_phaseinjector1_command_storage[7];
assign csrbank1_dfii_pi1_command0_w = soc_litedramcore_phaseinjector1_command_storage;
assign csrbank1_dfii_pi1_address0_w = soc_litedramcore_phaseinjector1_address_storage;
assign csrbank1_dfii_pi1_baddress0_w = soc_litedramcore_phaseinjector1_baddress_storage;
assign csrbank1_dfii_pi1_wrdata0_w = soc_litedramcore_phaseinjector1_wrdata_storage;
assign csrbank1_dfii_pi1_rddata_w = soc_litedramcore_phaseinjector1_rddata_status;
assign soc_litedramcore_phaseinjector1_rddata_we = csrbank1_dfii_pi1_rddata_we;
assign soc_litedramcore_phaseinjector2_csrfield_cs = soc_litedramcore_phaseinjector2_command_storage[0];
assign soc_litedramcore_phaseinjector2_csrfield_we = soc_litedramcore_phaseinjector2_command_storage[1];
assign soc_litedramcore_phaseinjector2_csrfield_cas = soc_litedramcore_phaseinjector2_command_storage[2];
assign soc_litedramcore_phaseinjector2_csrfield_ras = soc_litedramcore_phaseinjector2_command_storage[3];
assign soc_litedramcore_phaseinjector2_csrfield_wren = soc_litedramcore_phaseinjector2_command_storage[4];
assign soc_litedramcore_phaseinjector2_csrfield_rden = soc_litedramcore_phaseinjector2_command_storage[5];
assign soc_litedramcore_phaseinjector2_csrfield_cs_top = soc_litedramcore_phaseinjector2_command_storage[6];
assign soc_litedramcore_phaseinjector2_csrfield_cs_bottom = soc_litedramcore_phaseinjector2_command_storage[7];
assign csrbank1_dfii_pi2_command0_w = soc_litedramcore_phaseinjector2_command_storage;
assign csrbank1_dfii_pi2_address0_w = soc_litedramcore_phaseinjector2_address_storage;
assign csrbank1_dfii_pi2_baddress0_w = soc_litedramcore_phaseinjector2_baddress_storage;
assign csrbank1_dfii_pi2_wrdata0_w = soc_litedramcore_phaseinjector2_wrdata_storage;
assign csrbank1_dfii_pi2_rddata_w = soc_litedramcore_phaseinjector2_rddata_status;
assign soc_litedramcore_phaseinjector2_rddata_we = csrbank1_dfii_pi2_rddata_we;
assign soc_litedramcore_phaseinjector3_csrfield_cs = soc_litedramcore_phaseinjector3_command_storage[0];
assign soc_litedramcore_phaseinjector3_csrfield_we = soc_litedramcore_phaseinjector3_command_storage[1];
assign soc_litedramcore_phaseinjector3_csrfield_cas = soc_litedramcore_phaseinjector3_command_storage[2];
assign soc_litedramcore_phaseinjector3_csrfield_ras = soc_litedramcore_phaseinjector3_command_storage[3];
assign soc_litedramcore_phaseinjector3_csrfield_wren = soc_litedramcore_phaseinjector3_command_storage[4];
assign soc_litedramcore_phaseinjector3_csrfield_rden = soc_litedramcore_phaseinjector3_command_storage[5];
assign soc_litedramcore_phaseinjector3_csrfield_cs_top = soc_litedramcore_phaseinjector3_command_storage[6];
assign soc_litedramcore_phaseinjector3_csrfield_cs_bottom = soc_litedramcore_phaseinjector3_command_storage[7];
assign csrbank1_dfii_pi3_command0_w = soc_litedramcore_phaseinjector3_command_storage;
assign csrbank1_dfii_pi3_address0_w = soc_litedramcore_phaseinjector3_address_storage;
assign csrbank1_dfii_pi3_baddress0_w = soc_litedramcore_phaseinjector3_baddress_storage;
assign csrbank1_dfii_pi3_wrdata0_w = soc_litedramcore_phaseinjector3_wrdata_storage;
assign csrbank1_dfii_pi3_rddata_w = soc_litedramcore_phaseinjector3_rddata_status;
assign soc_litedramcore_phaseinjector3_rddata_we = csrbank1_dfii_pi3_rddata_we;
assign adr = interface1_adr;
assign re = interface1_re;
assign we = interface1_we;
assign dat_w = interface1_dat_w;
assign interface1_dat_r = dat_r;
assign interface0_bank_bus_adr = adr;
assign interface1_bank_bus_adr = adr;
assign interface0_bank_bus_re = re;
assign interface1_bank_bus_re = re;
assign interface0_bank_bus_we = we;
assign interface1_bank_bus_we = we;
assign interface0_bank_bus_dat_w = dat_w;
assign interface1_bank_bus_dat_w = dat_w;
assign dat_r = (interface0_bank_bus_dat_r | interface1_bank_bus_dat_r);
assign slice_proxy0 = ((soc_ddrphy_bankmodel0_row * 11'd1024) | soc_ddrphy_bankmodel0_write_col);
assign slice_proxy1 = ((soc_ddrphy_bankmodel0_row * 11'd1024) | soc_ddrphy_bankmodel0_read_col);
assign slice_proxy2 = ((soc_ddrphy_bankmodel1_row * 11'd1024) | soc_ddrphy_bankmodel1_write_col);
assign slice_proxy3 = ((soc_ddrphy_bankmodel1_row * 11'd1024) | soc_ddrphy_bankmodel1_read_col);
assign slice_proxy4 = ((soc_ddrphy_bankmodel2_row * 11'd1024) | soc_ddrphy_bankmodel2_write_col);
assign slice_proxy5 = ((soc_ddrphy_bankmodel2_row * 11'd1024) | soc_ddrphy_bankmodel2_read_col);
assign slice_proxy6 = ((soc_ddrphy_bankmodel3_row * 11'd1024) | soc_ddrphy_bankmodel3_write_col);
assign slice_proxy7 = ((soc_ddrphy_bankmodel3_row * 11'd1024) | soc_ddrphy_bankmodel3_read_col);
assign slice_proxy8 = ((soc_ddrphy_bankmodel4_row * 11'd1024) | soc_ddrphy_bankmodel4_write_col);
assign slice_proxy9 = ((soc_ddrphy_bankmodel4_row * 11'd1024) | soc_ddrphy_bankmodel4_read_col);
assign slice_proxy10 = ((soc_ddrphy_bankmodel5_row * 11'd1024) | soc_ddrphy_bankmodel5_write_col);
assign slice_proxy11 = ((soc_ddrphy_bankmodel5_row * 11'd1024) | soc_ddrphy_bankmodel5_read_col);
assign slice_proxy12 = ((soc_ddrphy_bankmodel6_row * 11'd1024) | soc_ddrphy_bankmodel6_write_col);
assign slice_proxy13 = ((soc_ddrphy_bankmodel6_row * 11'd1024) | soc_ddrphy_bankmodel6_read_col);
assign slice_proxy14 = ((soc_ddrphy_bankmodel7_row * 11'd1024) | soc_ddrphy_bankmodel7_write_col);
assign slice_proxy15 = ((soc_ddrphy_bankmodel7_row * 11'd1024) | soc_ddrphy_bankmodel7_read_col);
always @(*) begin
    rhs_self0 <= 1'd0;
    case (soc_litedramcore_choose_cmd_grant)
        1'd0: begin
            rhs_self0 <= soc_litedramcore_choose_cmd_valids[0];
        end
        1'd1: begin
            rhs_self0 <= soc_litedramcore_choose_cmd_valids[1];
        end
        2'd2: begin
            rhs_self0 <= soc_litedramcore_choose_cmd_valids[2];
        end
        2'd3: begin
            rhs_self0 <= soc_litedramcore_choose_cmd_valids[3];
        end
        3'd4: begin
            rhs_self0 <= soc_litedramcore_choose_cmd_valids[4];
        end
        3'd5: begin
            rhs_self0 <= soc_litedramcore_choose_cmd_valids[5];
        end
        3'd6: begin
            rhs_self0 <= soc_litedramcore_choose_cmd_valids[6];
        end
        default: begin
            rhs_self0 <= soc_litedramcore_choose_cmd_valids[7];
        end
    endcase
end
always @(*) begin
    rhs_self1 <= 14'd0;
    case (soc_litedramcore_choose_cmd_grant)
        1'd0: begin
            rhs_self1 <= soc_litedramcore_bankmachine0_cmd_payload_a;
        end
        1'd1: begin
            rhs_self1 <= soc_litedramcore_bankmachine1_cmd_payload_a;
        end
        2'd2: begin
            rhs_self1 <= soc_litedramcore_bankmachine2_cmd_payload_a;
        end
        2'd3: begin
            rhs_self1 <= soc_litedramcore_bankmachine3_cmd_payload_a;
        end
        3'd4: begin
            rhs_self1 <= soc_litedramcore_bankmachine4_cmd_payload_a;
        end
        3'd5: begin
            rhs_self1 <= soc_litedramcore_bankmachine5_cmd_payload_a;
        end
        3'd6: begin
            rhs_self1 <= soc_litedramcore_bankmachine6_cmd_payload_a;
        end
        default: begin
            rhs_self1 <= soc_litedramcore_bankmachine7_cmd_payload_a;
        end
    endcase
end
always @(*) begin
    rhs_self2 <= 3'd0;
    case (soc_litedramcore_choose_cmd_grant)
        1'd0: begin
            rhs_self2 <= soc_litedramcore_bankmachine0_cmd_payload_ba;
        end
        1'd1: begin
            rhs_self2 <= soc_litedramcore_bankmachine1_cmd_payload_ba;
        end
        2'd2: begin
            rhs_self2 <= soc_litedramcore_bankmachine2_cmd_payload_ba;
        end
        2'd3: begin
            rhs_self2 <= soc_litedramcore_bankmachine3_cmd_payload_ba;
        end
        3'd4: begin
            rhs_self2 <= soc_litedramcore_bankmachine4_cmd_payload_ba;
        end
        3'd5: begin
            rhs_self2 <= soc_litedramcore_bankmachine5_cmd_payload_ba;
        end
        3'd6: begin
            rhs_self2 <= soc_litedramcore_bankmachine6_cmd_payload_ba;
        end
        default: begin
            rhs_self2 <= soc_litedramcore_bankmachine7_cmd_payload_ba;
        end
    endcase
end
always @(*) begin
    rhs_self3 <= 1'd0;
    case (soc_litedramcore_choose_cmd_grant)
        1'd0: begin
            rhs_self3 <= soc_litedramcore_bankmachine0_cmd_payload_is_read;
        end
        1'd1: begin
            rhs_self3 <= soc_litedramcore_bankmachine1_cmd_payload_is_read;
        end
        2'd2: begin
            rhs_self3 <= soc_litedramcore_bankmachine2_cmd_payload_is_read;
        end
        2'd3: begin
            rhs_self3 <= soc_litedramcore_bankmachine3_cmd_payload_is_read;
        end
        3'd4: begin
            rhs_self3 <= soc_litedramcore_bankmachine4_cmd_payload_is_read;
        end
        3'd5: begin
            rhs_self3 <= soc_litedramcore_bankmachine5_cmd_payload_is_read;
        end
        3'd6: begin
            rhs_self3 <= soc_litedramcore_bankmachine6_cmd_payload_is_read;
        end
        default: begin
            rhs_self3 <= soc_litedramcore_bankmachine7_cmd_payload_is_read;
        end
    endcase
end
always @(*) begin
    rhs_self4 <= 1'd0;
    case (soc_litedramcore_choose_cmd_grant)
        1'd0: begin
            rhs_self4 <= soc_litedramcore_bankmachine0_cmd_payload_is_write;
        end
        1'd1: begin
            rhs_self4 <= soc_litedramcore_bankmachine1_cmd_payload_is_write;
        end
        2'd2: begin
            rhs_self4 <= soc_litedramcore_bankmachine2_cmd_payload_is_write;
        end
        2'd3: begin
            rhs_self4 <= soc_litedramcore_bankmachine3_cmd_payload_is_write;
        end
        3'd4: begin
            rhs_self4 <= soc_litedramcore_bankmachine4_cmd_payload_is_write;
        end
        3'd5: begin
            rhs_self4 <= soc_litedramcore_bankmachine5_cmd_payload_is_write;
        end
        3'd6: begin
            rhs_self4 <= soc_litedramcore_bankmachine6_cmd_payload_is_write;
        end
        default: begin
            rhs_self4 <= soc_litedramcore_bankmachine7_cmd_payload_is_write;
        end
    endcase
end
always @(*) begin
    rhs_self5 <= 1'd0;
    case (soc_litedramcore_choose_cmd_grant)
        1'd0: begin
            rhs_self5 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd;
        end
        1'd1: begin
            rhs_self5 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd;
        end
        2'd2: begin
            rhs_self5 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd;
        end
        2'd3: begin
            rhs_self5 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd;
        end
        3'd4: begin
            rhs_self5 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd;
        end
        3'd5: begin
            rhs_self5 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd;
        end
        3'd6: begin
            rhs_self5 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd;
        end
        default: begin
            rhs_self5 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd;
        end
    endcase
end
always @(*) begin
    t_self0 <= 1'd0;
    case (soc_litedramcore_choose_cmd_grant)
        1'd0: begin
            t_self0 <= soc_litedramcore_bankmachine0_cmd_payload_cas;
        end
        1'd1: begin
            t_self0 <= soc_litedramcore_bankmachine1_cmd_payload_cas;
        end
        2'd2: begin
            t_self0 <= soc_litedramcore_bankmachine2_cmd_payload_cas;
        end
        2'd3: begin
            t_self0 <= soc_litedramcore_bankmachine3_cmd_payload_cas;
        end
        3'd4: begin
            t_self0 <= soc_litedramcore_bankmachine4_cmd_payload_cas;
        end
        3'd5: begin
            t_self0 <= soc_litedramcore_bankmachine5_cmd_payload_cas;
        end
        3'd6: begin
            t_self0 <= soc_litedramcore_bankmachine6_cmd_payload_cas;
        end
        default: begin
            t_self0 <= soc_litedramcore_bankmachine7_cmd_payload_cas;
        end
    endcase
end
always @(*) begin
    t_self1 <= 1'd0;
    case (soc_litedramcore_choose_cmd_grant)
        1'd0: begin
            t_self1 <= soc_litedramcore_bankmachine0_cmd_payload_ras;
        end
        1'd1: begin
            t_self1 <= soc_litedramcore_bankmachine1_cmd_payload_ras;
        end
        2'd2: begin
            t_self1 <= soc_litedramcore_bankmachine2_cmd_payload_ras;
        end
        2'd3: begin
            t_self1 <= soc_litedramcore_bankmachine3_cmd_payload_ras;
        end
        3'd4: begin
            t_self1 <= soc_litedramcore_bankmachine4_cmd_payload_ras;
        end
        3'd5: begin
            t_self1 <= soc_litedramcore_bankmachine5_cmd_payload_ras;
        end
        3'd6: begin
            t_self1 <= soc_litedramcore_bankmachine6_cmd_payload_ras;
        end
        default: begin
            t_self1 <= soc_litedramcore_bankmachine7_cmd_payload_ras;
        end
    endcase
end
always @(*) begin
    t_self2 <= 1'd0;
    case (soc_litedramcore_choose_cmd_grant)
        1'd0: begin
            t_self2 <= soc_litedramcore_bankmachine0_cmd_payload_we;
        end
        1'd1: begin
            t_self2 <= soc_litedramcore_bankmachine1_cmd_payload_we;
        end
        2'd2: begin
            t_self2 <= soc_litedramcore_bankmachine2_cmd_payload_we;
        end
        2'd3: begin
            t_self2 <= soc_litedramcore_bankmachine3_cmd_payload_we;
        end
        3'd4: begin
            t_self2 <= soc_litedramcore_bankmachine4_cmd_payload_we;
        end
        3'd5: begin
            t_self2 <= soc_litedramcore_bankmachine5_cmd_payload_we;
        end
        3'd6: begin
            t_self2 <= soc_litedramcore_bankmachine6_cmd_payload_we;
        end
        default: begin
            t_self2 <= soc_litedramcore_bankmachine7_cmd_payload_we;
        end
    endcase
end
always @(*) begin
    rhs_self6 <= 1'd0;
    case (soc_litedramcore_choose_req_grant)
        1'd0: begin
            rhs_self6 <= soc_litedramcore_choose_req_valids[0];
        end
        1'd1: begin
            rhs_self6 <= soc_litedramcore_choose_req_valids[1];
        end
        2'd2: begin
            rhs_self6 <= soc_litedramcore_choose_req_valids[2];
        end
        2'd3: begin
            rhs_self6 <= soc_litedramcore_choose_req_valids[3];
        end
        3'd4: begin
            rhs_self6 <= soc_litedramcore_choose_req_valids[4];
        end
        3'd5: begin
            rhs_self6 <= soc_litedramcore_choose_req_valids[5];
        end
        3'd6: begin
            rhs_self6 <= soc_litedramcore_choose_req_valids[6];
        end
        default: begin
            rhs_self6 <= soc_litedramcore_choose_req_valids[7];
        end
    endcase
end
always @(*) begin
    rhs_self7 <= 14'd0;
    case (soc_litedramcore_choose_req_grant)
        1'd0: begin
            rhs_self7 <= soc_litedramcore_bankmachine0_cmd_payload_a;
        end
        1'd1: begin
            rhs_self7 <= soc_litedramcore_bankmachine1_cmd_payload_a;
        end
        2'd2: begin
            rhs_self7 <= soc_litedramcore_bankmachine2_cmd_payload_a;
        end
        2'd3: begin
            rhs_self7 <= soc_litedramcore_bankmachine3_cmd_payload_a;
        end
        3'd4: begin
            rhs_self7 <= soc_litedramcore_bankmachine4_cmd_payload_a;
        end
        3'd5: begin
            rhs_self7 <= soc_litedramcore_bankmachine5_cmd_payload_a;
        end
        3'd6: begin
            rhs_self7 <= soc_litedramcore_bankmachine6_cmd_payload_a;
        end
        default: begin
            rhs_self7 <= soc_litedramcore_bankmachine7_cmd_payload_a;
        end
    endcase
end
always @(*) begin
    rhs_self8 <= 3'd0;
    case (soc_litedramcore_choose_req_grant)
        1'd0: begin
            rhs_self8 <= soc_litedramcore_bankmachine0_cmd_payload_ba;
        end
        1'd1: begin
            rhs_self8 <= soc_litedramcore_bankmachine1_cmd_payload_ba;
        end
        2'd2: begin
            rhs_self8 <= soc_litedramcore_bankmachine2_cmd_payload_ba;
        end
        2'd3: begin
            rhs_self8 <= soc_litedramcore_bankmachine3_cmd_payload_ba;
        end
        3'd4: begin
            rhs_self8 <= soc_litedramcore_bankmachine4_cmd_payload_ba;
        end
        3'd5: begin
            rhs_self8 <= soc_litedramcore_bankmachine5_cmd_payload_ba;
        end
        3'd6: begin
            rhs_self8 <= soc_litedramcore_bankmachine6_cmd_payload_ba;
        end
        default: begin
            rhs_self8 <= soc_litedramcore_bankmachine7_cmd_payload_ba;
        end
    endcase
end
always @(*) begin
    rhs_self9 <= 1'd0;
    case (soc_litedramcore_choose_req_grant)
        1'd0: begin
            rhs_self9 <= soc_litedramcore_bankmachine0_cmd_payload_is_read;
        end
        1'd1: begin
            rhs_self9 <= soc_litedramcore_bankmachine1_cmd_payload_is_read;
        end
        2'd2: begin
            rhs_self9 <= soc_litedramcore_bankmachine2_cmd_payload_is_read;
        end
        2'd3: begin
            rhs_self9 <= soc_litedramcore_bankmachine3_cmd_payload_is_read;
        end
        3'd4: begin
            rhs_self9 <= soc_litedramcore_bankmachine4_cmd_payload_is_read;
        end
        3'd5: begin
            rhs_self9 <= soc_litedramcore_bankmachine5_cmd_payload_is_read;
        end
        3'd6: begin
            rhs_self9 <= soc_litedramcore_bankmachine6_cmd_payload_is_read;
        end
        default: begin
            rhs_self9 <= soc_litedramcore_bankmachine7_cmd_payload_is_read;
        end
    endcase
end
always @(*) begin
    rhs_self10 <= 1'd0;
    case (soc_litedramcore_choose_req_grant)
        1'd0: begin
            rhs_self10 <= soc_litedramcore_bankmachine0_cmd_payload_is_write;
        end
        1'd1: begin
            rhs_self10 <= soc_litedramcore_bankmachine1_cmd_payload_is_write;
        end
        2'd2: begin
            rhs_self10 <= soc_litedramcore_bankmachine2_cmd_payload_is_write;
        end
        2'd3: begin
            rhs_self10 <= soc_litedramcore_bankmachine3_cmd_payload_is_write;
        end
        3'd4: begin
            rhs_self10 <= soc_litedramcore_bankmachine4_cmd_payload_is_write;
        end
        3'd5: begin
            rhs_self10 <= soc_litedramcore_bankmachine5_cmd_payload_is_write;
        end
        3'd6: begin
            rhs_self10 <= soc_litedramcore_bankmachine6_cmd_payload_is_write;
        end
        default: begin
            rhs_self10 <= soc_litedramcore_bankmachine7_cmd_payload_is_write;
        end
    endcase
end
always @(*) begin
    rhs_self11 <= 1'd0;
    case (soc_litedramcore_choose_req_grant)
        1'd0: begin
            rhs_self11 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd;
        end
        1'd1: begin
            rhs_self11 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd;
        end
        2'd2: begin
            rhs_self11 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd;
        end
        2'd3: begin
            rhs_self11 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd;
        end
        3'd4: begin
            rhs_self11 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd;
        end
        3'd5: begin
            rhs_self11 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd;
        end
        3'd6: begin
            rhs_self11 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd;
        end
        default: begin
            rhs_self11 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd;
        end
    endcase
end
always @(*) begin
    t_self3 <= 1'd0;
    case (soc_litedramcore_choose_req_grant)
        1'd0: begin
            t_self3 <= soc_litedramcore_bankmachine0_cmd_payload_cas;
        end
        1'd1: begin
            t_self3 <= soc_litedramcore_bankmachine1_cmd_payload_cas;
        end
        2'd2: begin
            t_self3 <= soc_litedramcore_bankmachine2_cmd_payload_cas;
        end
        2'd3: begin
            t_self3 <= soc_litedramcore_bankmachine3_cmd_payload_cas;
        end
        3'd4: begin
            t_self3 <= soc_litedramcore_bankmachine4_cmd_payload_cas;
        end
        3'd5: begin
            t_self3 <= soc_litedramcore_bankmachine5_cmd_payload_cas;
        end
        3'd6: begin
            t_self3 <= soc_litedramcore_bankmachine6_cmd_payload_cas;
        end
        default: begin
            t_self3 <= soc_litedramcore_bankmachine7_cmd_payload_cas;
        end
    endcase
end
always @(*) begin
    t_self4 <= 1'd0;
    case (soc_litedramcore_choose_req_grant)
        1'd0: begin
            t_self4 <= soc_litedramcore_bankmachine0_cmd_payload_ras;
        end
        1'd1: begin
            t_self4 <= soc_litedramcore_bankmachine1_cmd_payload_ras;
        end
        2'd2: begin
            t_self4 <= soc_litedramcore_bankmachine2_cmd_payload_ras;
        end
        2'd3: begin
            t_self4 <= soc_litedramcore_bankmachine3_cmd_payload_ras;
        end
        3'd4: begin
            t_self4 <= soc_litedramcore_bankmachine4_cmd_payload_ras;
        end
        3'd5: begin
            t_self4 <= soc_litedramcore_bankmachine5_cmd_payload_ras;
        end
        3'd6: begin
            t_self4 <= soc_litedramcore_bankmachine6_cmd_payload_ras;
        end
        default: begin
            t_self4 <= soc_litedramcore_bankmachine7_cmd_payload_ras;
        end
    endcase
end
always @(*) begin
    t_self5 <= 1'd0;
    case (soc_litedramcore_choose_req_grant)
        1'd0: begin
            t_self5 <= soc_litedramcore_bankmachine0_cmd_payload_we;
        end
        1'd1: begin
            t_self5 <= soc_litedramcore_bankmachine1_cmd_payload_we;
        end
        2'd2: begin
            t_self5 <= soc_litedramcore_bankmachine2_cmd_payload_we;
        end
        2'd3: begin
            t_self5 <= soc_litedramcore_bankmachine3_cmd_payload_we;
        end
        3'd4: begin
            t_self5 <= soc_litedramcore_bankmachine4_cmd_payload_we;
        end
        3'd5: begin
            t_self5 <= soc_litedramcore_bankmachine5_cmd_payload_we;
        end
        3'd6: begin
            t_self5 <= soc_litedramcore_bankmachine6_cmd_payload_we;
        end
        default: begin
            t_self5 <= soc_litedramcore_bankmachine7_cmd_payload_we;
        end
    endcase
end
always @(*) begin
    rhs_self12 <= 21'd0;
    case (roundrobin0_grant)
        default: begin
            rhs_self12 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
        end
    endcase
end
always @(*) begin
    rhs_self13 <= 1'd0;
    case (roundrobin0_grant)
        default: begin
            rhs_self13 <= soc_user_port_cmd_payload_we;
        end
    endcase
end
always @(*) begin
    rhs_self14 <= 1'd0;
    case (roundrobin0_grant)
        default: begin
            rhs_self14 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
        end
    endcase
end
always @(*) begin
    rhs_self15 <= 21'd0;
    case (roundrobin1_grant)
        default: begin
            rhs_self15 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
        end
    endcase
end
always @(*) begin
    rhs_self16 <= 1'd0;
    case (roundrobin1_grant)
        default: begin
            rhs_self16 <= soc_user_port_cmd_payload_we;
        end
    endcase
end
always @(*) begin
    rhs_self17 <= 1'd0;
    case (roundrobin1_grant)
        default: begin
            rhs_self17 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
        end
    endcase
end
always @(*) begin
    rhs_self18 <= 21'd0;
    case (roundrobin2_grant)
        default: begin
            rhs_self18 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
        end
    endcase
end
always @(*) begin
    rhs_self19 <= 1'd0;
    case (roundrobin2_grant)
        default: begin
            rhs_self19 <= soc_user_port_cmd_payload_we;
        end
    endcase
end
always @(*) begin
    rhs_self20 <= 1'd0;
    case (roundrobin2_grant)
        default: begin
            rhs_self20 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
        end
    endcase
end
always @(*) begin
    rhs_self21 <= 21'd0;
    case (roundrobin3_grant)
        default: begin
            rhs_self21 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
        end
    endcase
end
always @(*) begin
    rhs_self22 <= 1'd0;
    case (roundrobin3_grant)
        default: begin
            rhs_self22 <= soc_user_port_cmd_payload_we;
        end
    endcase
end
always @(*) begin
    rhs_self23 <= 1'd0;
    case (roundrobin3_grant)
        default: begin
            rhs_self23 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
        end
    endcase
end
always @(*) begin
    rhs_self24 <= 21'd0;
    case (roundrobin4_grant)
        default: begin
            rhs_self24 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
        end
    endcase
end
always @(*) begin
    rhs_self25 <= 1'd0;
    case (roundrobin4_grant)
        default: begin
            rhs_self25 <= soc_user_port_cmd_payload_we;
        end
    endcase
end
always @(*) begin
    rhs_self26 <= 1'd0;
    case (roundrobin4_grant)
        default: begin
            rhs_self26 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
        end
    endcase
end
always @(*) begin
    rhs_self27 <= 21'd0;
    case (roundrobin5_grant)
        default: begin
            rhs_self27 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
        end
    endcase
end
always @(*) begin
    rhs_self28 <= 1'd0;
    case (roundrobin5_grant)
        default: begin
            rhs_self28 <= soc_user_port_cmd_payload_we;
        end
    endcase
end
always @(*) begin
    rhs_self29 <= 1'd0;
    case (roundrobin5_grant)
        default: begin
            rhs_self29 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
        end
    endcase
end
always @(*) begin
    rhs_self30 <= 21'd0;
    case (roundrobin6_grant)
        default: begin
            rhs_self30 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
        end
    endcase
end
always @(*) begin
    rhs_self31 <= 1'd0;
    case (roundrobin6_grant)
        default: begin
            rhs_self31 <= soc_user_port_cmd_payload_we;
        end
    endcase
end
always @(*) begin
    rhs_self32 <= 1'd0;
    case (roundrobin6_grant)
        default: begin
            rhs_self32 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
        end
    endcase
end
always @(*) begin
    rhs_self33 <= 21'd0;
    case (roundrobin7_grant)
        default: begin
            rhs_self33 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
        end
    endcase
end
always @(*) begin
    rhs_self34 <= 1'd0;
    case (roundrobin7_grant)
        default: begin
            rhs_self34 <= soc_user_port_cmd_payload_we;
        end
    endcase
end
always @(*) begin
    rhs_self35 <= 1'd0;
    case (roundrobin7_grant)
        default: begin
            rhs_self35 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid);
        end
    endcase
end
always @(*) begin
    self0 <= 3'd0;
    case (soc_litedramcore_steerer0)
        1'd0: begin
            self0 <= soc_litedramcore_nop_ba;
        end
        1'd1: begin
            self0 <= soc_litedramcore_choose_cmd_cmd_payload_ba;
        end
        2'd2: begin
            self0 <= soc_litedramcore_choose_req_cmd_payload_ba;
        end
        default: begin
            self0 <= soc_litedramcore_cmd_payload_ba;
        end
    endcase
end
always @(*) begin
    self1 <= 14'd0;
    case (soc_litedramcore_steerer0)
        1'd0: begin
            self1 <= soc_litedramcore_nop_a;
        end
        1'd1: begin
            self1 <= soc_litedramcore_choose_cmd_cmd_payload_a;
        end
        2'd2: begin
            self1 <= soc_litedramcore_choose_req_cmd_payload_a;
        end
        default: begin
            self1 <= soc_litedramcore_cmd_payload_a;
        end
    endcase
end
always @(*) begin
    self2 <= 1'd0;
    case (soc_litedramcore_steerer0)
        1'd0: begin
            self2 <= 1'd0;
        end
        1'd1: begin
            self2 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
        end
        2'd2: begin
            self2 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
        end
        default: begin
            self2 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
        end
    endcase
end
always @(*) begin
    self3 <= 1'd0;
    case (soc_litedramcore_steerer0)
        1'd0: begin
            self3 <= 1'd0;
        end
        1'd1: begin
            self3 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
        end
        2'd2: begin
            self3 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
        end
        default: begin
            self3 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
        end
    endcase
end
always @(*) begin
    self4 <= 1'd0;
    case (soc_litedramcore_steerer0)
        1'd0: begin
            self4 <= 1'd0;
        end
        1'd1: begin
            self4 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
        end
        2'd2: begin
            self4 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
        end
        default: begin
            self4 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
        end
    endcase
end
always @(*) begin
    self5 <= 1'd0;
    case (soc_litedramcore_steerer0)
        1'd0: begin
            self5 <= 1'd0;
        end
        1'd1: begin
            self5 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
        end
        2'd2: begin
            self5 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
        end
        default: begin
            self5 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
        end
    endcase
end
always @(*) begin
    self6 <= 1'd0;
    case (soc_litedramcore_steerer0)
        1'd0: begin
            self6 <= 1'd0;
        end
        1'd1: begin
            self6 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
        end
        2'd2: begin
            self6 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
        end
        default: begin
            self6 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
        end
    endcase
end
always @(*) begin
    self7 <= 3'd0;
    case (soc_litedramcore_steerer1)
        1'd0: begin
            self7 <= soc_litedramcore_nop_ba;
        end
        1'd1: begin
            self7 <= soc_litedramcore_choose_cmd_cmd_payload_ba;
        end
        2'd2: begin
            self7 <= soc_litedramcore_choose_req_cmd_payload_ba;
        end
        default: begin
            self7 <= soc_litedramcore_cmd_payload_ba;
        end
    endcase
end
always @(*) begin
    self8 <= 14'd0;
    case (soc_litedramcore_steerer1)
        1'd0: begin
            self8 <= soc_litedramcore_nop_a;
        end
        1'd1: begin
            self8 <= soc_litedramcore_choose_cmd_cmd_payload_a;
        end
        2'd2: begin
            self8 <= soc_litedramcore_choose_req_cmd_payload_a;
        end
        default: begin
            self8 <= soc_litedramcore_cmd_payload_a;
        end
    endcase
end
always @(*) begin
    self9 <= 1'd0;
    case (soc_litedramcore_steerer1)
        1'd0: begin
            self9 <= 1'd0;
        end
        1'd1: begin
            self9 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
        end
        2'd2: begin
            self9 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
        end
        default: begin
            self9 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
        end
    endcase
end
always @(*) begin
    self10 <= 1'd0;
    case (soc_litedramcore_steerer1)
        1'd0: begin
            self10 <= 1'd0;
        end
        1'd1: begin
            self10 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
        end
        2'd2: begin
            self10 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
        end
        default: begin
            self10 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
        end
    endcase
end
always @(*) begin
    self11 <= 1'd0;
    case (soc_litedramcore_steerer1)
        1'd0: begin
            self11 <= 1'd0;
        end
        1'd1: begin
            self11 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
        end
        2'd2: begin
            self11 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
        end
        default: begin
            self11 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
        end
    endcase
end
always @(*) begin
    self12 <= 1'd0;
    case (soc_litedramcore_steerer1)
        1'd0: begin
            self12 <= 1'd0;
        end
        1'd1: begin
            self12 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
        end
        2'd2: begin
            self12 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
        end
        default: begin
            self12 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
        end
    endcase
end
always @(*) begin
    self13 <= 1'd0;
    case (soc_litedramcore_steerer1)
        1'd0: begin
            self13 <= 1'd0;
        end
        1'd1: begin
            self13 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
        end
        2'd2: begin
            self13 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
        end
        default: begin
            self13 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
        end
    endcase
end
always @(*) begin
    self14 <= 3'd0;
    case (soc_litedramcore_steerer2)
        1'd0: begin
            self14 <= soc_litedramcore_nop_ba;
        end
        1'd1: begin
            self14 <= soc_litedramcore_choose_cmd_cmd_payload_ba;
        end
        2'd2: begin
            self14 <= soc_litedramcore_choose_req_cmd_payload_ba;
        end
        default: begin
            self14 <= soc_litedramcore_cmd_payload_ba;
        end
    endcase
end
always @(*) begin
    self15 <= 14'd0;
    case (soc_litedramcore_steerer2)
        1'd0: begin
            self15 <= soc_litedramcore_nop_a;
        end
        1'd1: begin
            self15 <= soc_litedramcore_choose_cmd_cmd_payload_a;
        end
        2'd2: begin
            self15 <= soc_litedramcore_choose_req_cmd_payload_a;
        end
        default: begin
            self15 <= soc_litedramcore_cmd_payload_a;
        end
    endcase
end
always @(*) begin
    self16 <= 1'd0;
    case (soc_litedramcore_steerer2)
        1'd0: begin
            self16 <= 1'd0;
        end
        1'd1: begin
            self16 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
        end
        2'd2: begin
            self16 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
        end
        default: begin
            self16 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
        end
    endcase
end
always @(*) begin
    self17 <= 1'd0;
    case (soc_litedramcore_steerer2)
        1'd0: begin
            self17 <= 1'd0;
        end
        1'd1: begin
            self17 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
        end
        2'd2: begin
            self17 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
        end
        default: begin
            self17 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
        end
    endcase
end
always @(*) begin
    self18 <= 1'd0;
    case (soc_litedramcore_steerer2)
        1'd0: begin
            self18 <= 1'd0;
        end
        1'd1: begin
            self18 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
        end
        2'd2: begin
            self18 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
        end
        default: begin
            self18 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
        end
    endcase
end
always @(*) begin
    self19 <= 1'd0;
    case (soc_litedramcore_steerer2)
        1'd0: begin
            self19 <= 1'd0;
        end
        1'd1: begin
            self19 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
        end
        2'd2: begin
            self19 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
        end
        default: begin
            self19 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
        end
    endcase
end
always @(*) begin
    self20 <= 1'd0;
    case (soc_litedramcore_steerer2)
        1'd0: begin
            self20 <= 1'd0;
        end
        1'd1: begin
            self20 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
        end
        2'd2: begin
            self20 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
        end
        default: begin
            self20 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
        end
    endcase
end
always @(*) begin
    self21 <= 3'd0;
    case (soc_litedramcore_steerer3)
        1'd0: begin
            self21 <= soc_litedramcore_nop_ba;
        end
        1'd1: begin
            self21 <= soc_litedramcore_choose_cmd_cmd_payload_ba;
        end
        2'd2: begin
            self21 <= soc_litedramcore_choose_req_cmd_payload_ba;
        end
        default: begin
            self21 <= soc_litedramcore_cmd_payload_ba;
        end
    endcase
end
always @(*) begin
    self22 <= 14'd0;
    case (soc_litedramcore_steerer3)
        1'd0: begin
            self22 <= soc_litedramcore_nop_a;
        end
        1'd1: begin
            self22 <= soc_litedramcore_choose_cmd_cmd_payload_a;
        end
        2'd2: begin
            self22 <= soc_litedramcore_choose_req_cmd_payload_a;
        end
        default: begin
            self22 <= soc_litedramcore_cmd_payload_a;
        end
    endcase
end
always @(*) begin
    self23 <= 1'd0;
    case (soc_litedramcore_steerer3)
        1'd0: begin
            self23 <= 1'd0;
        end
        1'd1: begin
            self23 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
        end
        2'd2: begin
            self23 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
        end
        default: begin
            self23 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
        end
    endcase
end
always @(*) begin
    self24 <= 1'd0;
    case (soc_litedramcore_steerer3)
        1'd0: begin
            self24 <= 1'd0;
        end
        1'd1: begin
            self24 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
        end
        2'd2: begin
            self24 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
        end
        default: begin
            self24 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
        end
    endcase
end
always @(*) begin
    self25 <= 1'd0;
    case (soc_litedramcore_steerer3)
        1'd0: begin
            self25 <= 1'd0;
        end
        1'd1: begin
            self25 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
        end
        2'd2: begin
            self25 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
        end
        default: begin
            self25 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
        end
    endcase
end
always @(*) begin
    self26 <= 1'd0;
    case (soc_litedramcore_steerer3)
        1'd0: begin
            self26 <= 1'd0;
        end
        1'd1: begin
            self26 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
        end
        2'd2: begin
            self26 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
        end
        default: begin
            self26 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
        end
    endcase
end
always @(*) begin
    self27 <= 1'd0;
    case (soc_litedramcore_steerer3)
        1'd0: begin
            self27 <= 1'd0;
        end
        1'd1: begin
            self27 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
        end
        2'd2: begin
            self27 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
        end
        default: begin
            self27 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
        end
    endcase
end


//------------------------------------------------------------------------------
// Synchronous Logic
//------------------------------------------------------------------------------

always @(posedge por_clk) begin
    soc_int_rst <= 1'd0;
end

always @(posedge sys_clk) begin
    soc_ddrphy_new_bank_write0 <= soc_ddrphy_bank_write0;
    soc_ddrphy_new_bank_write_col0 <= soc_ddrphy_bank_write_col0;
    soc_ddrphy_new_bank_write1 <= soc_ddrphy_bank_write1;
    soc_ddrphy_new_bank_write_col1 <= soc_ddrphy_bank_write_col1;
    soc_ddrphy_new_bank_write2 <= soc_ddrphy_bank_write2;
    soc_ddrphy_new_bank_write_col2 <= soc_ddrphy_bank_write_col2;
    soc_ddrphy_new_bank_write3 <= soc_ddrphy_bank_write3;
    soc_ddrphy_new_bank_write_col3 <= soc_ddrphy_bank_write_col3;
    soc_ddrphy_new_bank_write4 <= soc_ddrphy_bank_write4;
    soc_ddrphy_new_bank_write_col4 <= soc_ddrphy_bank_write_col4;
    soc_ddrphy_new_bank_write5 <= soc_ddrphy_bank_write5;
    soc_ddrphy_new_bank_write_col5 <= soc_ddrphy_bank_write_col5;
    soc_ddrphy_new_bank_write6 <= soc_ddrphy_bank_write6;
    soc_ddrphy_new_bank_write_col6 <= soc_ddrphy_bank_write_col6;
    soc_ddrphy_new_bank_write7 <= soc_ddrphy_bank_write7;
    soc_ddrphy_new_bank_write_col7 <= soc_ddrphy_bank_write_col7;
    soc_ddrphy_new_banks_read0 <= soc_ddrphy_banks_read;
    soc_ddrphy_new_banks_read_data0 <= soc_ddrphy_banks_read_data;
    soc_ddrphy_new_banks_read1 <= soc_ddrphy_new_banks_read0;
    soc_ddrphy_new_banks_read_data1 <= soc_ddrphy_new_banks_read_data0;
    soc_ddrphy_new_banks_read2 <= soc_ddrphy_new_banks_read1;
    soc_ddrphy_new_banks_read_data2 <= soc_ddrphy_new_banks_read_data1;
    soc_ddrphy_new_banks_read3 <= soc_ddrphy_new_banks_read2;
    soc_ddrphy_new_banks_read_data3 <= soc_ddrphy_new_banks_read_data2;
    soc_ddrphy_new_banks_read4 <= soc_ddrphy_new_banks_read3;
    soc_ddrphy_new_banks_read_data4 <= soc_ddrphy_new_banks_read_data3;
    soc_ddrphy_new_banks_read5 <= soc_ddrphy_new_banks_read4;
    soc_ddrphy_new_banks_read_data5 <= soc_ddrphy_new_banks_read_data4;
    soc_ddrphy_new_banks_read6 <= soc_ddrphy_new_banks_read5;
    soc_ddrphy_new_banks_read_data6 <= soc_ddrphy_new_banks_read_data5;
    soc_ddrphy_new_banks_read7 <= soc_ddrphy_new_banks_read6;
    soc_ddrphy_new_banks_read_data7 <= soc_ddrphy_new_banks_read_data6;
    if (soc_ddrphy_bankmodel0_precharge) begin
        soc_ddrphy_bankmodel0_active <= 1'd0;
    end else begin
        if (soc_ddrphy_bankmodel0_activate) begin
            soc_ddrphy_bankmodel0_active <= 1'd1;
            soc_ddrphy_bankmodel0_row <= soc_ddrphy_bankmodel0_activate_row;
        end
    end
    if (soc_ddrphy_bankmodel1_precharge) begin
        soc_ddrphy_bankmodel1_active <= 1'd0;
    end else begin
        if (soc_ddrphy_bankmodel1_activate) begin
            soc_ddrphy_bankmodel1_active <= 1'd1;
            soc_ddrphy_bankmodel1_row <= soc_ddrphy_bankmodel1_activate_row;
        end
    end
    if (soc_ddrphy_bankmodel2_precharge) begin
        soc_ddrphy_bankmodel2_active <= 1'd0;
    end else begin
        if (soc_ddrphy_bankmodel2_activate) begin
            soc_ddrphy_bankmodel2_active <= 1'd1;
            soc_ddrphy_bankmodel2_row <= soc_ddrphy_bankmodel2_activate_row;
        end
    end
    if (soc_ddrphy_bankmodel3_precharge) begin
        soc_ddrphy_bankmodel3_active <= 1'd0;
    end else begin
        if (soc_ddrphy_bankmodel3_activate) begin
            soc_ddrphy_bankmodel3_active <= 1'd1;
            soc_ddrphy_bankmodel3_row <= soc_ddrphy_bankmodel3_activate_row;
        end
    end
    if (soc_ddrphy_bankmodel4_precharge) begin
        soc_ddrphy_bankmodel4_active <= 1'd0;
    end else begin
        if (soc_ddrphy_bankmodel4_activate) begin
            soc_ddrphy_bankmodel4_active <= 1'd1;
            soc_ddrphy_bankmodel4_row <= soc_ddrphy_bankmodel4_activate_row;
        end
    end
    if (soc_ddrphy_bankmodel5_precharge) begin
        soc_ddrphy_bankmodel5_active <= 1'd0;
    end else begin
        if (soc_ddrphy_bankmodel5_activate) begin
            soc_ddrphy_bankmodel5_active <= 1'd1;
            soc_ddrphy_bankmodel5_row <= soc_ddrphy_bankmodel5_activate_row;
        end
    end
    if (soc_ddrphy_bankmodel6_precharge) begin
        soc_ddrphy_bankmodel6_active <= 1'd0;
    end else begin
        if (soc_ddrphy_bankmodel6_activate) begin
            soc_ddrphy_bankmodel6_active <= 1'd1;
            soc_ddrphy_bankmodel6_row <= soc_ddrphy_bankmodel6_activate_row;
        end
    end
    if (soc_ddrphy_bankmodel7_precharge) begin
        soc_ddrphy_bankmodel7_active <= 1'd0;
    end else begin
        if (soc_ddrphy_bankmodel7_activate) begin
            soc_ddrphy_bankmodel7_active <= 1'd1;
            soc_ddrphy_bankmodel7_row <= soc_ddrphy_bankmodel7_activate_row;
        end
    end
    if (soc_litedramcore_csr_dfi_p0_rddata_valid) begin
        soc_litedramcore_phaseinjector0_rddata_status <= soc_litedramcore_csr_dfi_p0_rddata;
    end
    if (soc_litedramcore_csr_dfi_p1_rddata_valid) begin
        soc_litedramcore_phaseinjector1_rddata_status <= soc_litedramcore_csr_dfi_p1_rddata;
    end
    if (soc_litedramcore_csr_dfi_p2_rddata_valid) begin
        soc_litedramcore_phaseinjector2_rddata_status <= soc_litedramcore_csr_dfi_p2_rddata;
    end
    if (soc_litedramcore_csr_dfi_p3_rddata_valid) begin
        soc_litedramcore_phaseinjector3_rddata_status <= soc_litedramcore_csr_dfi_p3_rddata;
    end
    if ((soc_litedramcore_timer_wait & (~soc_litedramcore_timer_done0))) begin
        soc_litedramcore_timer_count1 <= (soc_litedramcore_timer_count1 - 1'd1);
    end else begin
        soc_litedramcore_timer_count1 <= 10'd781;
    end
    soc_litedramcore_postponer_req_o <= 1'd0;
    if (soc_litedramcore_postponer_req_i) begin
        soc_litedramcore_postponer_count <= (soc_litedramcore_postponer_count - 1'd1);
        if ((soc_litedramcore_postponer_count == 1'd0)) begin
            soc_litedramcore_postponer_count <= 1'd0;
            soc_litedramcore_postponer_req_o <= 1'd1;
        end
    end
    if (soc_litedramcore_sequencer_start0) begin
        soc_litedramcore_sequencer_count <= 1'd0;
    end else begin
        if (soc_litedramcore_sequencer_done1) begin
            if ((soc_litedramcore_sequencer_count != 1'd0)) begin
                soc_litedramcore_sequencer_count <= (soc_litedramcore_sequencer_count - 1'd1);
            end
        end
    end
    soc_litedramcore_cmd_payload_a <= 1'd0;
    soc_litedramcore_cmd_payload_ba <= 1'd0;
    soc_litedramcore_cmd_payload_cas <= 1'd0;
    soc_litedramcore_cmd_payload_ras <= 1'd0;
    soc_litedramcore_cmd_payload_we <= 1'd0;
    soc_litedramcore_sequencer_done1 <= 1'd0;
    if ((soc_litedramcore_sequencer_start1 & (soc_litedramcore_sequencer_trigger == 1'd0))) begin
        soc_litedramcore_cmd_payload_a <= 11'd1024;
        soc_litedramcore_cmd_payload_ba <= 1'd0;
        soc_litedramcore_cmd_payload_cas <= 1'd0;
        soc_litedramcore_cmd_payload_ras <= 1'd1;
        soc_litedramcore_cmd_payload_we <= 1'd1;
    end
    if ((soc_litedramcore_sequencer_trigger == 2'd3)) begin
        soc_litedramcore_cmd_payload_a <= 11'd1024;
        soc_litedramcore_cmd_payload_ba <= 1'd0;
        soc_litedramcore_cmd_payload_cas <= 1'd1;
        soc_litedramcore_cmd_payload_ras <= 1'd1;
        soc_litedramcore_cmd_payload_we <= 1'd0;
    end
    if ((soc_litedramcore_sequencer_trigger == 6'd35)) begin
        soc_litedramcore_cmd_payload_a <= 1'd0;
        soc_litedramcore_cmd_payload_ba <= 1'd0;
        soc_litedramcore_cmd_payload_cas <= 1'd0;
        soc_litedramcore_cmd_payload_ras <= 1'd0;
        soc_litedramcore_cmd_payload_we <= 1'd0;
        soc_litedramcore_sequencer_done1 <= 1'd1;
    end
    if ((soc_litedramcore_sequencer_trigger == 6'd35)) begin
        soc_litedramcore_sequencer_trigger <= 1'd0;
    end else begin
        if ((soc_litedramcore_sequencer_trigger != 1'd0)) begin
            soc_litedramcore_sequencer_trigger <= (soc_litedramcore_sequencer_trigger + 1'd1);
        end else begin
            if (soc_litedramcore_sequencer_start1) begin
                soc_litedramcore_sequencer_trigger <= 1'd1;
            end
        end
    end
    if ((soc_litedramcore_zqcs_timer_wait & (~soc_litedramcore_zqcs_timer_done0))) begin
        soc_litedramcore_zqcs_timer_count1 <= (soc_litedramcore_zqcs_timer_count1 - 1'd1);
    end else begin
        soc_litedramcore_zqcs_timer_count1 <= 27'd99999999;
    end
    soc_litedramcore_zqcs_executer_done <= 1'd0;
    if ((soc_litedramcore_zqcs_executer_start & (soc_litedramcore_zqcs_executer_trigger == 1'd0))) begin
        soc_litedramcore_cmd_payload_a <= 11'd1024;
        soc_litedramcore_cmd_payload_ba <= 1'd0;
        soc_litedramcore_cmd_payload_cas <= 1'd0;
        soc_litedramcore_cmd_payload_ras <= 1'd1;
        soc_litedramcore_cmd_payload_we <= 1'd1;
    end
    if ((soc_litedramcore_zqcs_executer_trigger == 2'd3)) begin
        soc_litedramcore_cmd_payload_a <= 1'd0;
        soc_litedramcore_cmd_payload_ba <= 1'd0;
        soc_litedramcore_cmd_payload_cas <= 1'd0;
        soc_litedramcore_cmd_payload_ras <= 1'd0;
        soc_litedramcore_cmd_payload_we <= 1'd1;
    end
    if ((soc_litedramcore_zqcs_executer_trigger == 5'd19)) begin
        soc_litedramcore_cmd_payload_a <= 1'd0;
        soc_litedramcore_cmd_payload_ba <= 1'd0;
        soc_litedramcore_cmd_payload_cas <= 1'd0;
        soc_litedramcore_cmd_payload_ras <= 1'd0;
        soc_litedramcore_cmd_payload_we <= 1'd0;
        soc_litedramcore_zqcs_executer_done <= 1'd1;
    end
    if ((soc_litedramcore_zqcs_executer_trigger == 5'd19)) begin
        soc_litedramcore_zqcs_executer_trigger <= 1'd0;
    end else begin
        if ((soc_litedramcore_zqcs_executer_trigger != 1'd0)) begin
            soc_litedramcore_zqcs_executer_trigger <= (soc_litedramcore_zqcs_executer_trigger + 1'd1);
        end else begin
            if (soc_litedramcore_zqcs_executer_start) begin
                soc_litedramcore_zqcs_executer_trigger <= 1'd1;
            end
        end
    end
    refresher_state <= refresher_next_state;
    if (soc_litedramcore_bankmachine0_row_close) begin
        soc_litedramcore_bankmachine0_row_opened <= 1'd0;
    end else begin
        if (soc_litedramcore_bankmachine0_row_open) begin
            soc_litedramcore_bankmachine0_row_opened <= 1'd1;
            soc_litedramcore_bankmachine0_row <= soc_litedramcore_bankmachine0_source_source_payload_addr[20:7];
        end
    end
    if (((soc_litedramcore_bankmachine0_syncfifo0_we & soc_litedramcore_bankmachine0_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_replace))) begin
        soc_litedramcore_bankmachine0_produce <= (soc_litedramcore_bankmachine0_produce + 1'd1);
    end
    if (soc_litedramcore_bankmachine0_do_read) begin
        soc_litedramcore_bankmachine0_consume <= (soc_litedramcore_bankmachine0_consume + 1'd1);
    end
    if (((soc_litedramcore_bankmachine0_syncfifo0_we & soc_litedramcore_bankmachine0_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_replace))) begin
        if ((~soc_litedramcore_bankmachine0_do_read)) begin
            soc_litedramcore_bankmachine0_level <= (soc_litedramcore_bankmachine0_level + 1'd1);
        end
    end else begin
        if (soc_litedramcore_bankmachine0_do_read) begin
            soc_litedramcore_bankmachine0_level <= (soc_litedramcore_bankmachine0_level - 1'd1);
        end
    end
    if (((~soc_litedramcore_bankmachine0_pipe_valid_source_valid) | soc_litedramcore_bankmachine0_pipe_valid_source_ready)) begin
        soc_litedramcore_bankmachine0_pipe_valid_source_valid <= soc_litedramcore_bankmachine0_pipe_valid_sink_valid;
        soc_litedramcore_bankmachine0_pipe_valid_source_first <= soc_litedramcore_bankmachine0_pipe_valid_sink_first;
        soc_litedramcore_bankmachine0_pipe_valid_source_last <= soc_litedramcore_bankmachine0_pipe_valid_sink_last;
        soc_litedramcore_bankmachine0_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine0_pipe_valid_sink_payload_we;
        soc_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
    end
    if (soc_litedramcore_bankmachine0_twtpcon_valid) begin
        soc_litedramcore_bankmachine0_twtpcon_count <= 3'd5;
        if (1'd0) begin
            soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
        end else begin
            soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_bankmachine0_twtpcon_ready)) begin
            soc_litedramcore_bankmachine0_twtpcon_count <= (soc_litedramcore_bankmachine0_twtpcon_count - 1'd1);
            if ((soc_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
                soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
            end
        end
    end
    if (soc_litedramcore_bankmachine0_trccon_valid) begin
        soc_litedramcore_bankmachine0_trccon_count <= 3'd5;
        if (1'd0) begin
            soc_litedramcore_bankmachine0_trccon_ready <= 1'd1;
        end else begin
            soc_litedramcore_bankmachine0_trccon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_bankmachine0_trccon_ready)) begin
            soc_litedramcore_bankmachine0_trccon_count <= (soc_litedramcore_bankmachine0_trccon_count - 1'd1);
            if ((soc_litedramcore_bankmachine0_trccon_count == 1'd1)) begin
                soc_litedramcore_bankmachine0_trccon_ready <= 1'd1;
            end
        end
    end
    if (soc_litedramcore_bankmachine0_trascon_valid) begin
        soc_litedramcore_bankmachine0_trascon_count <= 3'd4;
        if (1'd0) begin
            soc_litedramcore_bankmachine0_trascon_ready <= 1'd1;
        end else begin
            soc_litedramcore_bankmachine0_trascon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_bankmachine0_trascon_ready)) begin
            soc_litedramcore_bankmachine0_trascon_count <= (soc_litedramcore_bankmachine0_trascon_count - 1'd1);
            if ((soc_litedramcore_bankmachine0_trascon_count == 1'd1)) begin
                soc_litedramcore_bankmachine0_trascon_ready <= 1'd1;
            end
        end
    end
    bankmachine0_state <= bankmachine0_next_state;
    if (soc_litedramcore_bankmachine1_row_close) begin
        soc_litedramcore_bankmachine1_row_opened <= 1'd0;
    end else begin
        if (soc_litedramcore_bankmachine1_row_open) begin
            soc_litedramcore_bankmachine1_row_opened <= 1'd1;
            soc_litedramcore_bankmachine1_row <= soc_litedramcore_bankmachine1_source_source_payload_addr[20:7];
        end
    end
    if (((soc_litedramcore_bankmachine1_syncfifo1_we & soc_litedramcore_bankmachine1_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_replace))) begin
        soc_litedramcore_bankmachine1_produce <= (soc_litedramcore_bankmachine1_produce + 1'd1);
    end
    if (soc_litedramcore_bankmachine1_do_read) begin
        soc_litedramcore_bankmachine1_consume <= (soc_litedramcore_bankmachine1_consume + 1'd1);
    end
    if (((soc_litedramcore_bankmachine1_syncfifo1_we & soc_litedramcore_bankmachine1_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_replace))) begin
        if ((~soc_litedramcore_bankmachine1_do_read)) begin
            soc_litedramcore_bankmachine1_level <= (soc_litedramcore_bankmachine1_level + 1'd1);
        end
    end else begin
        if (soc_litedramcore_bankmachine1_do_read) begin
            soc_litedramcore_bankmachine1_level <= (soc_litedramcore_bankmachine1_level - 1'd1);
        end
    end
    if (((~soc_litedramcore_bankmachine1_pipe_valid_source_valid) | soc_litedramcore_bankmachine1_pipe_valid_source_ready)) begin
        soc_litedramcore_bankmachine1_pipe_valid_source_valid <= soc_litedramcore_bankmachine1_pipe_valid_sink_valid;
        soc_litedramcore_bankmachine1_pipe_valid_source_first <= soc_litedramcore_bankmachine1_pipe_valid_sink_first;
        soc_litedramcore_bankmachine1_pipe_valid_source_last <= soc_litedramcore_bankmachine1_pipe_valid_sink_last;
        soc_litedramcore_bankmachine1_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine1_pipe_valid_sink_payload_we;
        soc_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
    end
    if (soc_litedramcore_bankmachine1_twtpcon_valid) begin
        soc_litedramcore_bankmachine1_twtpcon_count <= 3'd5;
        if (1'd0) begin
            soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
        end else begin
            soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_bankmachine1_twtpcon_ready)) begin
            soc_litedramcore_bankmachine1_twtpcon_count <= (soc_litedramcore_bankmachine1_twtpcon_count - 1'd1);
            if ((soc_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
                soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
            end
        end
    end
    if (soc_litedramcore_bankmachine1_trccon_valid) begin
        soc_litedramcore_bankmachine1_trccon_count <= 3'd5;
        if (1'd0) begin
            soc_litedramcore_bankmachine1_trccon_ready <= 1'd1;
        end else begin
            soc_litedramcore_bankmachine1_trccon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_bankmachine1_trccon_ready)) begin
            soc_litedramcore_bankmachine1_trccon_count <= (soc_litedramcore_bankmachine1_trccon_count - 1'd1);
            if ((soc_litedramcore_bankmachine1_trccon_count == 1'd1)) begin
                soc_litedramcore_bankmachine1_trccon_ready <= 1'd1;
            end
        end
    end
    if (soc_litedramcore_bankmachine1_trascon_valid) begin
        soc_litedramcore_bankmachine1_trascon_count <= 3'd4;
        if (1'd0) begin
            soc_litedramcore_bankmachine1_trascon_ready <= 1'd1;
        end else begin
            soc_litedramcore_bankmachine1_trascon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_bankmachine1_trascon_ready)) begin
            soc_litedramcore_bankmachine1_trascon_count <= (soc_litedramcore_bankmachine1_trascon_count - 1'd1);
            if ((soc_litedramcore_bankmachine1_trascon_count == 1'd1)) begin
                soc_litedramcore_bankmachine1_trascon_ready <= 1'd1;
            end
        end
    end
    bankmachine1_state <= bankmachine1_next_state;
    if (soc_litedramcore_bankmachine2_row_close) begin
        soc_litedramcore_bankmachine2_row_opened <= 1'd0;
    end else begin
        if (soc_litedramcore_bankmachine2_row_open) begin
            soc_litedramcore_bankmachine2_row_opened <= 1'd1;
            soc_litedramcore_bankmachine2_row <= soc_litedramcore_bankmachine2_source_source_payload_addr[20:7];
        end
    end
    if (((soc_litedramcore_bankmachine2_syncfifo2_we & soc_litedramcore_bankmachine2_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_replace))) begin
        soc_litedramcore_bankmachine2_produce <= (soc_litedramcore_bankmachine2_produce + 1'd1);
    end
    if (soc_litedramcore_bankmachine2_do_read) begin
        soc_litedramcore_bankmachine2_consume <= (soc_litedramcore_bankmachine2_consume + 1'd1);
    end
    if (((soc_litedramcore_bankmachine2_syncfifo2_we & soc_litedramcore_bankmachine2_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_replace))) begin
        if ((~soc_litedramcore_bankmachine2_do_read)) begin
            soc_litedramcore_bankmachine2_level <= (soc_litedramcore_bankmachine2_level + 1'd1);
        end
    end else begin
        if (soc_litedramcore_bankmachine2_do_read) begin
            soc_litedramcore_bankmachine2_level <= (soc_litedramcore_bankmachine2_level - 1'd1);
        end
    end
    if (((~soc_litedramcore_bankmachine2_pipe_valid_source_valid) | soc_litedramcore_bankmachine2_pipe_valid_source_ready)) begin
        soc_litedramcore_bankmachine2_pipe_valid_source_valid <= soc_litedramcore_bankmachine2_pipe_valid_sink_valid;
        soc_litedramcore_bankmachine2_pipe_valid_source_first <= soc_litedramcore_bankmachine2_pipe_valid_sink_first;
        soc_litedramcore_bankmachine2_pipe_valid_source_last <= soc_litedramcore_bankmachine2_pipe_valid_sink_last;
        soc_litedramcore_bankmachine2_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine2_pipe_valid_sink_payload_we;
        soc_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
    end
    if (soc_litedramcore_bankmachine2_twtpcon_valid) begin
        soc_litedramcore_bankmachine2_twtpcon_count <= 3'd5;
        if (1'd0) begin
            soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
        end else begin
            soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_bankmachine2_twtpcon_ready)) begin
            soc_litedramcore_bankmachine2_twtpcon_count <= (soc_litedramcore_bankmachine2_twtpcon_count - 1'd1);
            if ((soc_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
                soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
            end
        end
    end
    if (soc_litedramcore_bankmachine2_trccon_valid) begin
        soc_litedramcore_bankmachine2_trccon_count <= 3'd5;
        if (1'd0) begin
            soc_litedramcore_bankmachine2_trccon_ready <= 1'd1;
        end else begin
            soc_litedramcore_bankmachine2_trccon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_bankmachine2_trccon_ready)) begin
            soc_litedramcore_bankmachine2_trccon_count <= (soc_litedramcore_bankmachine2_trccon_count - 1'd1);
            if ((soc_litedramcore_bankmachine2_trccon_count == 1'd1)) begin
                soc_litedramcore_bankmachine2_trccon_ready <= 1'd1;
            end
        end
    end
    if (soc_litedramcore_bankmachine2_trascon_valid) begin
        soc_litedramcore_bankmachine2_trascon_count <= 3'd4;
        if (1'd0) begin
            soc_litedramcore_bankmachine2_trascon_ready <= 1'd1;
        end else begin
            soc_litedramcore_bankmachine2_trascon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_bankmachine2_trascon_ready)) begin
            soc_litedramcore_bankmachine2_trascon_count <= (soc_litedramcore_bankmachine2_trascon_count - 1'd1);
            if ((soc_litedramcore_bankmachine2_trascon_count == 1'd1)) begin
                soc_litedramcore_bankmachine2_trascon_ready <= 1'd1;
            end
        end
    end
    bankmachine2_state <= bankmachine2_next_state;
    if (soc_litedramcore_bankmachine3_row_close) begin
        soc_litedramcore_bankmachine3_row_opened <= 1'd0;
    end else begin
        if (soc_litedramcore_bankmachine3_row_open) begin
            soc_litedramcore_bankmachine3_row_opened <= 1'd1;
            soc_litedramcore_bankmachine3_row <= soc_litedramcore_bankmachine3_source_source_payload_addr[20:7];
        end
    end
    if (((soc_litedramcore_bankmachine3_syncfifo3_we & soc_litedramcore_bankmachine3_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_replace))) begin
        soc_litedramcore_bankmachine3_produce <= (soc_litedramcore_bankmachine3_produce + 1'd1);
    end
    if (soc_litedramcore_bankmachine3_do_read) begin
        soc_litedramcore_bankmachine3_consume <= (soc_litedramcore_bankmachine3_consume + 1'd1);
    end
    if (((soc_litedramcore_bankmachine3_syncfifo3_we & soc_litedramcore_bankmachine3_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_replace))) begin
        if ((~soc_litedramcore_bankmachine3_do_read)) begin
            soc_litedramcore_bankmachine3_level <= (soc_litedramcore_bankmachine3_level + 1'd1);
        end
    end else begin
        if (soc_litedramcore_bankmachine3_do_read) begin
            soc_litedramcore_bankmachine3_level <= (soc_litedramcore_bankmachine3_level - 1'd1);
        end
    end
    if (((~soc_litedramcore_bankmachine3_pipe_valid_source_valid) | soc_litedramcore_bankmachine3_pipe_valid_source_ready)) begin
        soc_litedramcore_bankmachine3_pipe_valid_source_valid <= soc_litedramcore_bankmachine3_pipe_valid_sink_valid;
        soc_litedramcore_bankmachine3_pipe_valid_source_first <= soc_litedramcore_bankmachine3_pipe_valid_sink_first;
        soc_litedramcore_bankmachine3_pipe_valid_source_last <= soc_litedramcore_bankmachine3_pipe_valid_sink_last;
        soc_litedramcore_bankmachine3_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine3_pipe_valid_sink_payload_we;
        soc_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
    end
    if (soc_litedramcore_bankmachine3_twtpcon_valid) begin
        soc_litedramcore_bankmachine3_twtpcon_count <= 3'd5;
        if (1'd0) begin
            soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
        end else begin
            soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_bankmachine3_twtpcon_ready)) begin
            soc_litedramcore_bankmachine3_twtpcon_count <= (soc_litedramcore_bankmachine3_twtpcon_count - 1'd1);
            if ((soc_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
                soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
            end
        end
    end
    if (soc_litedramcore_bankmachine3_trccon_valid) begin
        soc_litedramcore_bankmachine3_trccon_count <= 3'd5;
        if (1'd0) begin
            soc_litedramcore_bankmachine3_trccon_ready <= 1'd1;
        end else begin
            soc_litedramcore_bankmachine3_trccon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_bankmachine3_trccon_ready)) begin
            soc_litedramcore_bankmachine3_trccon_count <= (soc_litedramcore_bankmachine3_trccon_count - 1'd1);
            if ((soc_litedramcore_bankmachine3_trccon_count == 1'd1)) begin
                soc_litedramcore_bankmachine3_trccon_ready <= 1'd1;
            end
        end
    end
    if (soc_litedramcore_bankmachine3_trascon_valid) begin
        soc_litedramcore_bankmachine3_trascon_count <= 3'd4;
        if (1'd0) begin
            soc_litedramcore_bankmachine3_trascon_ready <= 1'd1;
        end else begin
            soc_litedramcore_bankmachine3_trascon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_bankmachine3_trascon_ready)) begin
            soc_litedramcore_bankmachine3_trascon_count <= (soc_litedramcore_bankmachine3_trascon_count - 1'd1);
            if ((soc_litedramcore_bankmachine3_trascon_count == 1'd1)) begin
                soc_litedramcore_bankmachine3_trascon_ready <= 1'd1;
            end
        end
    end
    bankmachine3_state <= bankmachine3_next_state;
    if (soc_litedramcore_bankmachine4_row_close) begin
        soc_litedramcore_bankmachine4_row_opened <= 1'd0;
    end else begin
        if (soc_litedramcore_bankmachine4_row_open) begin
            soc_litedramcore_bankmachine4_row_opened <= 1'd1;
            soc_litedramcore_bankmachine4_row <= soc_litedramcore_bankmachine4_source_source_payload_addr[20:7];
        end
    end
    if (((soc_litedramcore_bankmachine4_syncfifo4_we & soc_litedramcore_bankmachine4_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_replace))) begin
        soc_litedramcore_bankmachine4_produce <= (soc_litedramcore_bankmachine4_produce + 1'd1);
    end
    if (soc_litedramcore_bankmachine4_do_read) begin
        soc_litedramcore_bankmachine4_consume <= (soc_litedramcore_bankmachine4_consume + 1'd1);
    end
    if (((soc_litedramcore_bankmachine4_syncfifo4_we & soc_litedramcore_bankmachine4_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_replace))) begin
        if ((~soc_litedramcore_bankmachine4_do_read)) begin
            soc_litedramcore_bankmachine4_level <= (soc_litedramcore_bankmachine4_level + 1'd1);
        end
    end else begin
        if (soc_litedramcore_bankmachine4_do_read) begin
            soc_litedramcore_bankmachine4_level <= (soc_litedramcore_bankmachine4_level - 1'd1);
        end
    end
    if (((~soc_litedramcore_bankmachine4_pipe_valid_source_valid) | soc_litedramcore_bankmachine4_pipe_valid_source_ready)) begin
        soc_litedramcore_bankmachine4_pipe_valid_source_valid <= soc_litedramcore_bankmachine4_pipe_valid_sink_valid;
        soc_litedramcore_bankmachine4_pipe_valid_source_first <= soc_litedramcore_bankmachine4_pipe_valid_sink_first;
        soc_litedramcore_bankmachine4_pipe_valid_source_last <= soc_litedramcore_bankmachine4_pipe_valid_sink_last;
        soc_litedramcore_bankmachine4_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine4_pipe_valid_sink_payload_we;
        soc_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
    end
    if (soc_litedramcore_bankmachine4_twtpcon_valid) begin
        soc_litedramcore_bankmachine4_twtpcon_count <= 3'd5;
        if (1'd0) begin
            soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
        end else begin
            soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_bankmachine4_twtpcon_ready)) begin
            soc_litedramcore_bankmachine4_twtpcon_count <= (soc_litedramcore_bankmachine4_twtpcon_count - 1'd1);
            if ((soc_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
                soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
            end
        end
    end
    if (soc_litedramcore_bankmachine4_trccon_valid) begin
        soc_litedramcore_bankmachine4_trccon_count <= 3'd5;
        if (1'd0) begin
            soc_litedramcore_bankmachine4_trccon_ready <= 1'd1;
        end else begin
            soc_litedramcore_bankmachine4_trccon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_bankmachine4_trccon_ready)) begin
            soc_litedramcore_bankmachine4_trccon_count <= (soc_litedramcore_bankmachine4_trccon_count - 1'd1);
            if ((soc_litedramcore_bankmachine4_trccon_count == 1'd1)) begin
                soc_litedramcore_bankmachine4_trccon_ready <= 1'd1;
            end
        end
    end
    if (soc_litedramcore_bankmachine4_trascon_valid) begin
        soc_litedramcore_bankmachine4_trascon_count <= 3'd4;
        if (1'd0) begin
            soc_litedramcore_bankmachine4_trascon_ready <= 1'd1;
        end else begin
            soc_litedramcore_bankmachine4_trascon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_bankmachine4_trascon_ready)) begin
            soc_litedramcore_bankmachine4_trascon_count <= (soc_litedramcore_bankmachine4_trascon_count - 1'd1);
            if ((soc_litedramcore_bankmachine4_trascon_count == 1'd1)) begin
                soc_litedramcore_bankmachine4_trascon_ready <= 1'd1;
            end
        end
    end
    bankmachine4_state <= bankmachine4_next_state;
    if (soc_litedramcore_bankmachine5_row_close) begin
        soc_litedramcore_bankmachine5_row_opened <= 1'd0;
    end else begin
        if (soc_litedramcore_bankmachine5_row_open) begin
            soc_litedramcore_bankmachine5_row_opened <= 1'd1;
            soc_litedramcore_bankmachine5_row <= soc_litedramcore_bankmachine5_source_source_payload_addr[20:7];
        end
    end
    if (((soc_litedramcore_bankmachine5_syncfifo5_we & soc_litedramcore_bankmachine5_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_replace))) begin
        soc_litedramcore_bankmachine5_produce <= (soc_litedramcore_bankmachine5_produce + 1'd1);
    end
    if (soc_litedramcore_bankmachine5_do_read) begin
        soc_litedramcore_bankmachine5_consume <= (soc_litedramcore_bankmachine5_consume + 1'd1);
    end
    if (((soc_litedramcore_bankmachine5_syncfifo5_we & soc_litedramcore_bankmachine5_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_replace))) begin
        if ((~soc_litedramcore_bankmachine5_do_read)) begin
            soc_litedramcore_bankmachine5_level <= (soc_litedramcore_bankmachine5_level + 1'd1);
        end
    end else begin
        if (soc_litedramcore_bankmachine5_do_read) begin
            soc_litedramcore_bankmachine5_level <= (soc_litedramcore_bankmachine5_level - 1'd1);
        end
    end
    if (((~soc_litedramcore_bankmachine5_pipe_valid_source_valid) | soc_litedramcore_bankmachine5_pipe_valid_source_ready)) begin
        soc_litedramcore_bankmachine5_pipe_valid_source_valid <= soc_litedramcore_bankmachine5_pipe_valid_sink_valid;
        soc_litedramcore_bankmachine5_pipe_valid_source_first <= soc_litedramcore_bankmachine5_pipe_valid_sink_first;
        soc_litedramcore_bankmachine5_pipe_valid_source_last <= soc_litedramcore_bankmachine5_pipe_valid_sink_last;
        soc_litedramcore_bankmachine5_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine5_pipe_valid_sink_payload_we;
        soc_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
    end
    if (soc_litedramcore_bankmachine5_twtpcon_valid) begin
        soc_litedramcore_bankmachine5_twtpcon_count <= 3'd5;
        if (1'd0) begin
            soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
        end else begin
            soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_bankmachine5_twtpcon_ready)) begin
            soc_litedramcore_bankmachine5_twtpcon_count <= (soc_litedramcore_bankmachine5_twtpcon_count - 1'd1);
            if ((soc_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
                soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
            end
        end
    end
    if (soc_litedramcore_bankmachine5_trccon_valid) begin
        soc_litedramcore_bankmachine5_trccon_count <= 3'd5;
        if (1'd0) begin
            soc_litedramcore_bankmachine5_trccon_ready <= 1'd1;
        end else begin
            soc_litedramcore_bankmachine5_trccon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_bankmachine5_trccon_ready)) begin
            soc_litedramcore_bankmachine5_trccon_count <= (soc_litedramcore_bankmachine5_trccon_count - 1'd1);
            if ((soc_litedramcore_bankmachine5_trccon_count == 1'd1)) begin
                soc_litedramcore_bankmachine5_trccon_ready <= 1'd1;
            end
        end
    end
    if (soc_litedramcore_bankmachine5_trascon_valid) begin
        soc_litedramcore_bankmachine5_trascon_count <= 3'd4;
        if (1'd0) begin
            soc_litedramcore_bankmachine5_trascon_ready <= 1'd1;
        end else begin
            soc_litedramcore_bankmachine5_trascon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_bankmachine5_trascon_ready)) begin
            soc_litedramcore_bankmachine5_trascon_count <= (soc_litedramcore_bankmachine5_trascon_count - 1'd1);
            if ((soc_litedramcore_bankmachine5_trascon_count == 1'd1)) begin
                soc_litedramcore_bankmachine5_trascon_ready <= 1'd1;
            end
        end
    end
    bankmachine5_state <= bankmachine5_next_state;
    if (soc_litedramcore_bankmachine6_row_close) begin
        soc_litedramcore_bankmachine6_row_opened <= 1'd0;
    end else begin
        if (soc_litedramcore_bankmachine6_row_open) begin
            soc_litedramcore_bankmachine6_row_opened <= 1'd1;
            soc_litedramcore_bankmachine6_row <= soc_litedramcore_bankmachine6_source_source_payload_addr[20:7];
        end
    end
    if (((soc_litedramcore_bankmachine6_syncfifo6_we & soc_litedramcore_bankmachine6_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_replace))) begin
        soc_litedramcore_bankmachine6_produce <= (soc_litedramcore_bankmachine6_produce + 1'd1);
    end
    if (soc_litedramcore_bankmachine6_do_read) begin
        soc_litedramcore_bankmachine6_consume <= (soc_litedramcore_bankmachine6_consume + 1'd1);
    end
    if (((soc_litedramcore_bankmachine6_syncfifo6_we & soc_litedramcore_bankmachine6_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_replace))) begin
        if ((~soc_litedramcore_bankmachine6_do_read)) begin
            soc_litedramcore_bankmachine6_level <= (soc_litedramcore_bankmachine6_level + 1'd1);
        end
    end else begin
        if (soc_litedramcore_bankmachine6_do_read) begin
            soc_litedramcore_bankmachine6_level <= (soc_litedramcore_bankmachine6_level - 1'd1);
        end
    end
    if (((~soc_litedramcore_bankmachine6_pipe_valid_source_valid) | soc_litedramcore_bankmachine6_pipe_valid_source_ready)) begin
        soc_litedramcore_bankmachine6_pipe_valid_source_valid <= soc_litedramcore_bankmachine6_pipe_valid_sink_valid;
        soc_litedramcore_bankmachine6_pipe_valid_source_first <= soc_litedramcore_bankmachine6_pipe_valid_sink_first;
        soc_litedramcore_bankmachine6_pipe_valid_source_last <= soc_litedramcore_bankmachine6_pipe_valid_sink_last;
        soc_litedramcore_bankmachine6_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine6_pipe_valid_sink_payload_we;
        soc_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
    end
    if (soc_litedramcore_bankmachine6_twtpcon_valid) begin
        soc_litedramcore_bankmachine6_twtpcon_count <= 3'd5;
        if (1'd0) begin
            soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
        end else begin
            soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_bankmachine6_twtpcon_ready)) begin
            soc_litedramcore_bankmachine6_twtpcon_count <= (soc_litedramcore_bankmachine6_twtpcon_count - 1'd1);
            if ((soc_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
                soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
            end
        end
    end
    if (soc_litedramcore_bankmachine6_trccon_valid) begin
        soc_litedramcore_bankmachine6_trccon_count <= 3'd5;
        if (1'd0) begin
            soc_litedramcore_bankmachine6_trccon_ready <= 1'd1;
        end else begin
            soc_litedramcore_bankmachine6_trccon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_bankmachine6_trccon_ready)) begin
            soc_litedramcore_bankmachine6_trccon_count <= (soc_litedramcore_bankmachine6_trccon_count - 1'd1);
            if ((soc_litedramcore_bankmachine6_trccon_count == 1'd1)) begin
                soc_litedramcore_bankmachine6_trccon_ready <= 1'd1;
            end
        end
    end
    if (soc_litedramcore_bankmachine6_trascon_valid) begin
        soc_litedramcore_bankmachine6_trascon_count <= 3'd4;
        if (1'd0) begin
            soc_litedramcore_bankmachine6_trascon_ready <= 1'd1;
        end else begin
            soc_litedramcore_bankmachine6_trascon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_bankmachine6_trascon_ready)) begin
            soc_litedramcore_bankmachine6_trascon_count <= (soc_litedramcore_bankmachine6_trascon_count - 1'd1);
            if ((soc_litedramcore_bankmachine6_trascon_count == 1'd1)) begin
                soc_litedramcore_bankmachine6_trascon_ready <= 1'd1;
            end
        end
    end
    bankmachine6_state <= bankmachine6_next_state;
    if (soc_litedramcore_bankmachine7_row_close) begin
        soc_litedramcore_bankmachine7_row_opened <= 1'd0;
    end else begin
        if (soc_litedramcore_bankmachine7_row_open) begin
            soc_litedramcore_bankmachine7_row_opened <= 1'd1;
            soc_litedramcore_bankmachine7_row <= soc_litedramcore_bankmachine7_source_source_payload_addr[20:7];
        end
    end
    if (((soc_litedramcore_bankmachine7_syncfifo7_we & soc_litedramcore_bankmachine7_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_replace))) begin
        soc_litedramcore_bankmachine7_produce <= (soc_litedramcore_bankmachine7_produce + 1'd1);
    end
    if (soc_litedramcore_bankmachine7_do_read) begin
        soc_litedramcore_bankmachine7_consume <= (soc_litedramcore_bankmachine7_consume + 1'd1);
    end
    if (((soc_litedramcore_bankmachine7_syncfifo7_we & soc_litedramcore_bankmachine7_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_replace))) begin
        if ((~soc_litedramcore_bankmachine7_do_read)) begin
            soc_litedramcore_bankmachine7_level <= (soc_litedramcore_bankmachine7_level + 1'd1);
        end
    end else begin
        if (soc_litedramcore_bankmachine7_do_read) begin
            soc_litedramcore_bankmachine7_level <= (soc_litedramcore_bankmachine7_level - 1'd1);
        end
    end
    if (((~soc_litedramcore_bankmachine7_pipe_valid_source_valid) | soc_litedramcore_bankmachine7_pipe_valid_source_ready)) begin
        soc_litedramcore_bankmachine7_pipe_valid_source_valid <= soc_litedramcore_bankmachine7_pipe_valid_sink_valid;
        soc_litedramcore_bankmachine7_pipe_valid_source_first <= soc_litedramcore_bankmachine7_pipe_valid_sink_first;
        soc_litedramcore_bankmachine7_pipe_valid_source_last <= soc_litedramcore_bankmachine7_pipe_valid_sink_last;
        soc_litedramcore_bankmachine7_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine7_pipe_valid_sink_payload_we;
        soc_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
    end
    if (soc_litedramcore_bankmachine7_twtpcon_valid) begin
        soc_litedramcore_bankmachine7_twtpcon_count <= 3'd5;
        if (1'd0) begin
            soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
        end else begin
            soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_bankmachine7_twtpcon_ready)) begin
            soc_litedramcore_bankmachine7_twtpcon_count <= (soc_litedramcore_bankmachine7_twtpcon_count - 1'd1);
            if ((soc_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
                soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
            end
        end
    end
    if (soc_litedramcore_bankmachine7_trccon_valid) begin
        soc_litedramcore_bankmachine7_trccon_count <= 3'd5;
        if (1'd0) begin
            soc_litedramcore_bankmachine7_trccon_ready <= 1'd1;
        end else begin
            soc_litedramcore_bankmachine7_trccon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_bankmachine7_trccon_ready)) begin
            soc_litedramcore_bankmachine7_trccon_count <= (soc_litedramcore_bankmachine7_trccon_count - 1'd1);
            if ((soc_litedramcore_bankmachine7_trccon_count == 1'd1)) begin
                soc_litedramcore_bankmachine7_trccon_ready <= 1'd1;
            end
        end
    end
    if (soc_litedramcore_bankmachine7_trascon_valid) begin
        soc_litedramcore_bankmachine7_trascon_count <= 3'd4;
        if (1'd0) begin
            soc_litedramcore_bankmachine7_trascon_ready <= 1'd1;
        end else begin
            soc_litedramcore_bankmachine7_trascon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_bankmachine7_trascon_ready)) begin
            soc_litedramcore_bankmachine7_trascon_count <= (soc_litedramcore_bankmachine7_trascon_count - 1'd1);
            if ((soc_litedramcore_bankmachine7_trascon_count == 1'd1)) begin
                soc_litedramcore_bankmachine7_trascon_ready <= 1'd1;
            end
        end
    end
    bankmachine7_state <= bankmachine7_next_state;
    if ((~soc_litedramcore_en0)) begin
        soc_litedramcore_time0 <= 5'd31;
    end else begin
        if ((~soc_litedramcore_max_time0)) begin
            soc_litedramcore_time0 <= (soc_litedramcore_time0 - 1'd1);
        end
    end
    if ((~soc_litedramcore_en1)) begin
        soc_litedramcore_time1 <= 4'd15;
    end else begin
        if ((~soc_litedramcore_max_time1)) begin
            soc_litedramcore_time1 <= (soc_litedramcore_time1 - 1'd1);
        end
    end
    if (soc_litedramcore_choose_cmd_ce) begin
        case (soc_litedramcore_choose_cmd_grant)
            1'd0: begin
                if (soc_litedramcore_choose_cmd_request[1]) begin
                    soc_litedramcore_choose_cmd_grant <= 1'd1;
                end else begin
                    if (soc_litedramcore_choose_cmd_request[2]) begin
                        soc_litedramcore_choose_cmd_grant <= 2'd2;
                    end else begin
                        if (soc_litedramcore_choose_cmd_request[3]) begin
                            soc_litedramcore_choose_cmd_grant <= 2'd3;
                        end else begin
                            if (soc_litedramcore_choose_cmd_request[4]) begin
                                soc_litedramcore_choose_cmd_grant <= 3'd4;
                            end else begin
                                if (soc_litedramcore_choose_cmd_request[5]) begin
                                    soc_litedramcore_choose_cmd_grant <= 3'd5;
                                end else begin
                                    if (soc_litedramcore_choose_cmd_request[6]) begin
                                        soc_litedramcore_choose_cmd_grant <= 3'd6;
                                    end else begin
                                        if (soc_litedramcore_choose_cmd_request[7]) begin
                                            soc_litedramcore_choose_cmd_grant <= 3'd7;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            1'd1: begin
                if (soc_litedramcore_choose_cmd_request[2]) begin
                    soc_litedramcore_choose_cmd_grant <= 2'd2;
                end else begin
                    if (soc_litedramcore_choose_cmd_request[3]) begin
                        soc_litedramcore_choose_cmd_grant <= 2'd3;
                    end else begin
                        if (soc_litedramcore_choose_cmd_request[4]) begin
                            soc_litedramcore_choose_cmd_grant <= 3'd4;
                        end else begin
                            if (soc_litedramcore_choose_cmd_request[5]) begin
                                soc_litedramcore_choose_cmd_grant <= 3'd5;
                            end else begin
                                if (soc_litedramcore_choose_cmd_request[6]) begin
                                    soc_litedramcore_choose_cmd_grant <= 3'd6;
                                end else begin
                                    if (soc_litedramcore_choose_cmd_request[7]) begin
                                        soc_litedramcore_choose_cmd_grant <= 3'd7;
                                    end else begin
                                        if (soc_litedramcore_choose_cmd_request[0]) begin
                                            soc_litedramcore_choose_cmd_grant <= 1'd0;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            2'd2: begin
                if (soc_litedramcore_choose_cmd_request[3]) begin
                    soc_litedramcore_choose_cmd_grant <= 2'd3;
                end else begin
                    if (soc_litedramcore_choose_cmd_request[4]) begin
                        soc_litedramcore_choose_cmd_grant <= 3'd4;
                    end else begin
                        if (soc_litedramcore_choose_cmd_request[5]) begin
                            soc_litedramcore_choose_cmd_grant <= 3'd5;
                        end else begin
                            if (soc_litedramcore_choose_cmd_request[6]) begin
                                soc_litedramcore_choose_cmd_grant <= 3'd6;
                            end else begin
                                if (soc_litedramcore_choose_cmd_request[7]) begin
                                    soc_litedramcore_choose_cmd_grant <= 3'd7;
                                end else begin
                                    if (soc_litedramcore_choose_cmd_request[0]) begin
                                        soc_litedramcore_choose_cmd_grant <= 1'd0;
                                    end else begin
                                        if (soc_litedramcore_choose_cmd_request[1]) begin
                                            soc_litedramcore_choose_cmd_grant <= 1'd1;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            2'd3: begin
                if (soc_litedramcore_choose_cmd_request[4]) begin
                    soc_litedramcore_choose_cmd_grant <= 3'd4;
                end else begin
                    if (soc_litedramcore_choose_cmd_request[5]) begin
                        soc_litedramcore_choose_cmd_grant <= 3'd5;
                    end else begin
                        if (soc_litedramcore_choose_cmd_request[6]) begin
                            soc_litedramcore_choose_cmd_grant <= 3'd6;
                        end else begin
                            if (soc_litedramcore_choose_cmd_request[7]) begin
                                soc_litedramcore_choose_cmd_grant <= 3'd7;
                            end else begin
                                if (soc_litedramcore_choose_cmd_request[0]) begin
                                    soc_litedramcore_choose_cmd_grant <= 1'd0;
                                end else begin
                                    if (soc_litedramcore_choose_cmd_request[1]) begin
                                        soc_litedramcore_choose_cmd_grant <= 1'd1;
                                    end else begin
                                        if (soc_litedramcore_choose_cmd_request[2]) begin
                                            soc_litedramcore_choose_cmd_grant <= 2'd2;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            3'd4: begin
                if (soc_litedramcore_choose_cmd_request[5]) begin
                    soc_litedramcore_choose_cmd_grant <= 3'd5;
                end else begin
                    if (soc_litedramcore_choose_cmd_request[6]) begin
                        soc_litedramcore_choose_cmd_grant <= 3'd6;
                    end else begin
                        if (soc_litedramcore_choose_cmd_request[7]) begin
                            soc_litedramcore_choose_cmd_grant <= 3'd7;
                        end else begin
                            if (soc_litedramcore_choose_cmd_request[0]) begin
                                soc_litedramcore_choose_cmd_grant <= 1'd0;
                            end else begin
                                if (soc_litedramcore_choose_cmd_request[1]) begin
                                    soc_litedramcore_choose_cmd_grant <= 1'd1;
                                end else begin
                                    if (soc_litedramcore_choose_cmd_request[2]) begin
                                        soc_litedramcore_choose_cmd_grant <= 2'd2;
                                    end else begin
                                        if (soc_litedramcore_choose_cmd_request[3]) begin
                                            soc_litedramcore_choose_cmd_grant <= 2'd3;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            3'd5: begin
                if (soc_litedramcore_choose_cmd_request[6]) begin
                    soc_litedramcore_choose_cmd_grant <= 3'd6;
                end else begin
                    if (soc_litedramcore_choose_cmd_request[7]) begin
                        soc_litedramcore_choose_cmd_grant <= 3'd7;
                    end else begin
                        if (soc_litedramcore_choose_cmd_request[0]) begin
                            soc_litedramcore_choose_cmd_grant <= 1'd0;
                        end else begin
                            if (soc_litedramcore_choose_cmd_request[1]) begin
                                soc_litedramcore_choose_cmd_grant <= 1'd1;
                            end else begin
                                if (soc_litedramcore_choose_cmd_request[2]) begin
                                    soc_litedramcore_choose_cmd_grant <= 2'd2;
                                end else begin
                                    if (soc_litedramcore_choose_cmd_request[3]) begin
                                        soc_litedramcore_choose_cmd_grant <= 2'd3;
                                    end else begin
                                        if (soc_litedramcore_choose_cmd_request[4]) begin
                                            soc_litedramcore_choose_cmd_grant <= 3'd4;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            3'd6: begin
                if (soc_litedramcore_choose_cmd_request[7]) begin
                    soc_litedramcore_choose_cmd_grant <= 3'd7;
                end else begin
                    if (soc_litedramcore_choose_cmd_request[0]) begin
                        soc_litedramcore_choose_cmd_grant <= 1'd0;
                    end else begin
                        if (soc_litedramcore_choose_cmd_request[1]) begin
                            soc_litedramcore_choose_cmd_grant <= 1'd1;
                        end else begin
                            if (soc_litedramcore_choose_cmd_request[2]) begin
                                soc_litedramcore_choose_cmd_grant <= 2'd2;
                            end else begin
                                if (soc_litedramcore_choose_cmd_request[3]) begin
                                    soc_litedramcore_choose_cmd_grant <= 2'd3;
                                end else begin
                                    if (soc_litedramcore_choose_cmd_request[4]) begin
                                        soc_litedramcore_choose_cmd_grant <= 3'd4;
                                    end else begin
                                        if (soc_litedramcore_choose_cmd_request[5]) begin
                                            soc_litedramcore_choose_cmd_grant <= 3'd5;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            3'd7: begin
                if (soc_litedramcore_choose_cmd_request[0]) begin
                    soc_litedramcore_choose_cmd_grant <= 1'd0;
                end else begin
                    if (soc_litedramcore_choose_cmd_request[1]) begin
                        soc_litedramcore_choose_cmd_grant <= 1'd1;
                    end else begin
                        if (soc_litedramcore_choose_cmd_request[2]) begin
                            soc_litedramcore_choose_cmd_grant <= 2'd2;
                        end else begin
                            if (soc_litedramcore_choose_cmd_request[3]) begin
                                soc_litedramcore_choose_cmd_grant <= 2'd3;
                            end else begin
                                if (soc_litedramcore_choose_cmd_request[4]) begin
                                    soc_litedramcore_choose_cmd_grant <= 3'd4;
                                end else begin
                                    if (soc_litedramcore_choose_cmd_request[5]) begin
                                        soc_litedramcore_choose_cmd_grant <= 3'd5;
                                    end else begin
                                        if (soc_litedramcore_choose_cmd_request[6]) begin
                                            soc_litedramcore_choose_cmd_grant <= 3'd6;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
        endcase
    end
    if (soc_litedramcore_choose_req_ce) begin
        case (soc_litedramcore_choose_req_grant)
            1'd0: begin
                if (soc_litedramcore_choose_req_request[1]) begin
                    soc_litedramcore_choose_req_grant <= 1'd1;
                end else begin
                    if (soc_litedramcore_choose_req_request[2]) begin
                        soc_litedramcore_choose_req_grant <= 2'd2;
                    end else begin
                        if (soc_litedramcore_choose_req_request[3]) begin
                            soc_litedramcore_choose_req_grant <= 2'd3;
                        end else begin
                            if (soc_litedramcore_choose_req_request[4]) begin
                                soc_litedramcore_choose_req_grant <= 3'd4;
                            end else begin
                                if (soc_litedramcore_choose_req_request[5]) begin
                                    soc_litedramcore_choose_req_grant <= 3'd5;
                                end else begin
                                    if (soc_litedramcore_choose_req_request[6]) begin
                                        soc_litedramcore_choose_req_grant <= 3'd6;
                                    end else begin
                                        if (soc_litedramcore_choose_req_request[7]) begin
                                            soc_litedramcore_choose_req_grant <= 3'd7;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            1'd1: begin
                if (soc_litedramcore_choose_req_request[2]) begin
                    soc_litedramcore_choose_req_grant <= 2'd2;
                end else begin
                    if (soc_litedramcore_choose_req_request[3]) begin
                        soc_litedramcore_choose_req_grant <= 2'd3;
                    end else begin
                        if (soc_litedramcore_choose_req_request[4]) begin
                            soc_litedramcore_choose_req_grant <= 3'd4;
                        end else begin
                            if (soc_litedramcore_choose_req_request[5]) begin
                                soc_litedramcore_choose_req_grant <= 3'd5;
                            end else begin
                                if (soc_litedramcore_choose_req_request[6]) begin
                                    soc_litedramcore_choose_req_grant <= 3'd6;
                                end else begin
                                    if (soc_litedramcore_choose_req_request[7]) begin
                                        soc_litedramcore_choose_req_grant <= 3'd7;
                                    end else begin
                                        if (soc_litedramcore_choose_req_request[0]) begin
                                            soc_litedramcore_choose_req_grant <= 1'd0;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            2'd2: begin
                if (soc_litedramcore_choose_req_request[3]) begin
                    soc_litedramcore_choose_req_grant <= 2'd3;
                end else begin
                    if (soc_litedramcore_choose_req_request[4]) begin
                        soc_litedramcore_choose_req_grant <= 3'd4;
                    end else begin
                        if (soc_litedramcore_choose_req_request[5]) begin
                            soc_litedramcore_choose_req_grant <= 3'd5;
                        end else begin
                            if (soc_litedramcore_choose_req_request[6]) begin
                                soc_litedramcore_choose_req_grant <= 3'd6;
                            end else begin
                                if (soc_litedramcore_choose_req_request[7]) begin
                                    soc_litedramcore_choose_req_grant <= 3'd7;
                                end else begin
                                    if (soc_litedramcore_choose_req_request[0]) begin
                                        soc_litedramcore_choose_req_grant <= 1'd0;
                                    end else begin
                                        if (soc_litedramcore_choose_req_request[1]) begin
                                            soc_litedramcore_choose_req_grant <= 1'd1;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            2'd3: begin
                if (soc_litedramcore_choose_req_request[4]) begin
                    soc_litedramcore_choose_req_grant <= 3'd4;
                end else begin
                    if (soc_litedramcore_choose_req_request[5]) begin
                        soc_litedramcore_choose_req_grant <= 3'd5;
                    end else begin
                        if (soc_litedramcore_choose_req_request[6]) begin
                            soc_litedramcore_choose_req_grant <= 3'd6;
                        end else begin
                            if (soc_litedramcore_choose_req_request[7]) begin
                                soc_litedramcore_choose_req_grant <= 3'd7;
                            end else begin
                                if (soc_litedramcore_choose_req_request[0]) begin
                                    soc_litedramcore_choose_req_grant <= 1'd0;
                                end else begin
                                    if (soc_litedramcore_choose_req_request[1]) begin
                                        soc_litedramcore_choose_req_grant <= 1'd1;
                                    end else begin
                                        if (soc_litedramcore_choose_req_request[2]) begin
                                            soc_litedramcore_choose_req_grant <= 2'd2;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            3'd4: begin
                if (soc_litedramcore_choose_req_request[5]) begin
                    soc_litedramcore_choose_req_grant <= 3'd5;
                end else begin
                    if (soc_litedramcore_choose_req_request[6]) begin
                        soc_litedramcore_choose_req_grant <= 3'd6;
                    end else begin
                        if (soc_litedramcore_choose_req_request[7]) begin
                            soc_litedramcore_choose_req_grant <= 3'd7;
                        end else begin
                            if (soc_litedramcore_choose_req_request[0]) begin
                                soc_litedramcore_choose_req_grant <= 1'd0;
                            end else begin
                                if (soc_litedramcore_choose_req_request[1]) begin
                                    soc_litedramcore_choose_req_grant <= 1'd1;
                                end else begin
                                    if (soc_litedramcore_choose_req_request[2]) begin
                                        soc_litedramcore_choose_req_grant <= 2'd2;
                                    end else begin
                                        if (soc_litedramcore_choose_req_request[3]) begin
                                            soc_litedramcore_choose_req_grant <= 2'd3;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            3'd5: begin
                if (soc_litedramcore_choose_req_request[6]) begin
                    soc_litedramcore_choose_req_grant <= 3'd6;
                end else begin
                    if (soc_litedramcore_choose_req_request[7]) begin
                        soc_litedramcore_choose_req_grant <= 3'd7;
                    end else begin
                        if (soc_litedramcore_choose_req_request[0]) begin
                            soc_litedramcore_choose_req_grant <= 1'd0;
                        end else begin
                            if (soc_litedramcore_choose_req_request[1]) begin
                                soc_litedramcore_choose_req_grant <= 1'd1;
                            end else begin
                                if (soc_litedramcore_choose_req_request[2]) begin
                                    soc_litedramcore_choose_req_grant <= 2'd2;
                                end else begin
                                    if (soc_litedramcore_choose_req_request[3]) begin
                                        soc_litedramcore_choose_req_grant <= 2'd3;
                                    end else begin
                                        if (soc_litedramcore_choose_req_request[4]) begin
                                            soc_litedramcore_choose_req_grant <= 3'd4;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            3'd6: begin
                if (soc_litedramcore_choose_req_request[7]) begin
                    soc_litedramcore_choose_req_grant <= 3'd7;
                end else begin
                    if (soc_litedramcore_choose_req_request[0]) begin
                        soc_litedramcore_choose_req_grant <= 1'd0;
                    end else begin
                        if (soc_litedramcore_choose_req_request[1]) begin
                            soc_litedramcore_choose_req_grant <= 1'd1;
                        end else begin
                            if (soc_litedramcore_choose_req_request[2]) begin
                                soc_litedramcore_choose_req_grant <= 2'd2;
                            end else begin
                                if (soc_litedramcore_choose_req_request[3]) begin
                                    soc_litedramcore_choose_req_grant <= 2'd3;
                                end else begin
                                    if (soc_litedramcore_choose_req_request[4]) begin
                                        soc_litedramcore_choose_req_grant <= 3'd4;
                                    end else begin
                                        if (soc_litedramcore_choose_req_request[5]) begin
                                            soc_litedramcore_choose_req_grant <= 3'd5;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            3'd7: begin
                if (soc_litedramcore_choose_req_request[0]) begin
                    soc_litedramcore_choose_req_grant <= 1'd0;
                end else begin
                    if (soc_litedramcore_choose_req_request[1]) begin
                        soc_litedramcore_choose_req_grant <= 1'd1;
                    end else begin
                        if (soc_litedramcore_choose_req_request[2]) begin
                            soc_litedramcore_choose_req_grant <= 2'd2;
                        end else begin
                            if (soc_litedramcore_choose_req_request[3]) begin
                                soc_litedramcore_choose_req_grant <= 2'd3;
                            end else begin
                                if (soc_litedramcore_choose_req_request[4]) begin
                                    soc_litedramcore_choose_req_grant <= 3'd4;
                                end else begin
                                    if (soc_litedramcore_choose_req_request[5]) begin
                                        soc_litedramcore_choose_req_grant <= 3'd5;
                                    end else begin
                                        if (soc_litedramcore_choose_req_request[6]) begin
                                            soc_litedramcore_choose_req_grant <= 3'd6;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
        endcase
    end
    soc_litedramcore_dfi_p0_cs_n <= 1'd0;
    soc_litedramcore_dfi_p0_bank <= self0;
    soc_litedramcore_dfi_p0_address <= self1;
    soc_litedramcore_dfi_p0_cas_n <= (~self2);
    soc_litedramcore_dfi_p0_ras_n <= (~self3);
    soc_litedramcore_dfi_p0_we_n <= (~self4);
    soc_litedramcore_dfi_p0_rddata_en <= self5;
    soc_litedramcore_dfi_p0_wrdata_en <= self6;
    soc_litedramcore_dfi_p1_cs_n <= 1'd0;
    soc_litedramcore_dfi_p1_bank <= self7;
    soc_litedramcore_dfi_p1_address <= self8;
    soc_litedramcore_dfi_p1_cas_n <= (~self9);
    soc_litedramcore_dfi_p1_ras_n <= (~self10);
    soc_litedramcore_dfi_p1_we_n <= (~self11);
    soc_litedramcore_dfi_p1_rddata_en <= self12;
    soc_litedramcore_dfi_p1_wrdata_en <= self13;
    soc_litedramcore_dfi_p2_cs_n <= 1'd0;
    soc_litedramcore_dfi_p2_bank <= self14;
    soc_litedramcore_dfi_p2_address <= self15;
    soc_litedramcore_dfi_p2_cas_n <= (~self16);
    soc_litedramcore_dfi_p2_ras_n <= (~self17);
    soc_litedramcore_dfi_p2_we_n <= (~self18);
    soc_litedramcore_dfi_p2_rddata_en <= self19;
    soc_litedramcore_dfi_p2_wrdata_en <= self20;
    soc_litedramcore_dfi_p3_cs_n <= 1'd0;
    soc_litedramcore_dfi_p3_bank <= self21;
    soc_litedramcore_dfi_p3_address <= self22;
    soc_litedramcore_dfi_p3_cas_n <= (~self23);
    soc_litedramcore_dfi_p3_ras_n <= (~self24);
    soc_litedramcore_dfi_p3_we_n <= (~self25);
    soc_litedramcore_dfi_p3_rddata_en <= self26;
    soc_litedramcore_dfi_p3_wrdata_en <= self27;
    if (soc_litedramcore_trrdcon_valid) begin
        soc_litedramcore_trrdcon_count <= 1'd1;
        if (1'd0) begin
            soc_litedramcore_trrdcon_ready <= 1'd1;
        end else begin
            soc_litedramcore_trrdcon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_trrdcon_ready)) begin
            soc_litedramcore_trrdcon_count <= (soc_litedramcore_trrdcon_count - 1'd1);
            if ((soc_litedramcore_trrdcon_count == 1'd1)) begin
                soc_litedramcore_trrdcon_ready <= 1'd1;
            end
        end
    end
    soc_litedramcore_tfawcon_window <= {soc_litedramcore_tfawcon_window, soc_litedramcore_tfawcon_valid};
    if ((soc_litedramcore_tfawcon_count < 3'd4)) begin
        if ((soc_litedramcore_tfawcon_count == 2'd3)) begin
            soc_litedramcore_tfawcon_ready <= (~soc_litedramcore_tfawcon_valid);
        end else begin
            soc_litedramcore_tfawcon_ready <= 1'd1;
        end
    end
    if (soc_litedramcore_tccdcon_valid) begin
        soc_litedramcore_tccdcon_count <= 1'd0;
        if (1'd1) begin
            soc_litedramcore_tccdcon_ready <= 1'd1;
        end else begin
            soc_litedramcore_tccdcon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_tccdcon_ready)) begin
            soc_litedramcore_tccdcon_count <= (soc_litedramcore_tccdcon_count - 1'd1);
            if ((soc_litedramcore_tccdcon_count == 1'd1)) begin
                soc_litedramcore_tccdcon_ready <= 1'd1;
            end
        end
    end
    if (soc_litedramcore_twtrcon_valid) begin
        soc_litedramcore_twtrcon_count <= 3'd4;
        if (1'd0) begin
            soc_litedramcore_twtrcon_ready <= 1'd1;
        end else begin
            soc_litedramcore_twtrcon_ready <= 1'd0;
        end
    end else begin
        if ((~soc_litedramcore_twtrcon_ready)) begin
            soc_litedramcore_twtrcon_count <= (soc_litedramcore_twtrcon_count - 1'd1);
            if ((soc_litedramcore_twtrcon_count == 1'd1)) begin
                soc_litedramcore_twtrcon_ready <= 1'd1;
            end
        end
    end
    multiplexer_state <= multiplexer_next_state;
    new_master_wdata_ready0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_wdata_ready)) | ((roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_wdata_ready)) | ((roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_wdata_ready)) | ((roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_wdata_ready)) | ((roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_wdata_ready)) | ((roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_wdata_ready)) | ((roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_wdata_ready)) | ((roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_wdata_ready));
    new_master_wdata_ready1 <= new_master_wdata_ready0;
    new_master_rdata_valid0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_rdata_valid)) | ((roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_rdata_valid)) | ((roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_rdata_valid)) | ((roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_rdata_valid)) | ((roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_rdata_valid)) | ((roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_rdata_valid)) | ((roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_rdata_valid)) | ((roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_rdata_valid));
    new_master_rdata_valid1 <= new_master_rdata_valid0;
    new_master_rdata_valid2 <= new_master_rdata_valid1;
    new_master_rdata_valid3 <= new_master_rdata_valid2;
    new_master_rdata_valid4 <= new_master_rdata_valid3;
    new_master_rdata_valid5 <= new_master_rdata_valid4;
    new_master_rdata_valid6 <= new_master_rdata_valid5;
    new_master_rdata_valid7 <= new_master_rdata_valid6;
    new_master_rdata_valid8 <= new_master_rdata_valid7;
    state <= next_state;
    if (interface1_dat_w_next_value_ce0) begin
        interface1_dat_w <= interface1_dat_w_next_value0;
    end
    if (interface1_adr_next_value_ce1) begin
        interface1_adr <= interface1_adr_next_value1;
    end
    if (interface1_re_next_value_ce2) begin
        interface1_re <= interface1_re_next_value2;
    end
    if (interface1_we_next_value_ce3) begin
        interface1_we <= interface1_we_next_value3;
    end
    interface0_bank_bus_dat_r <= 1'd0;
    if (csrbank0_sel) begin
        case (interface0_bank_bus_adr[8:0])
            1'd0: begin
                interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
            end
            1'd1: begin
                interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
            end
        endcase
    end
    if (csrbank0_init_done0_re) begin
        soc_init_done_storage <= csrbank0_init_done0_r;
    end
    soc_init_done_re <= csrbank0_init_done0_re;
    if (csrbank0_init_error0_re) begin
        soc_init_error_storage <= csrbank0_init_error0_r;
    end
    soc_init_error_re <= csrbank0_init_error0_re;
    interface1_bank_bus_dat_r <= 1'd0;
    if (csrbank1_sel) begin
        case (interface1_bank_bus_adr[8:0])
            1'd0: begin
                interface1_bank_bus_dat_r <= csrbank1_dfii_control0_w;
            end
            1'd1: begin
                interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_command0_w;
            end
            2'd2: begin
                interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector0_command_issue_w;
            end
            2'd3: begin
                interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w;
            end
            3'd4: begin
                interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w;
            end
            3'd5: begin
                interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w;
            end
            3'd6: begin
                interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata_w;
            end
            3'd7: begin
                interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w;
            end
            4'd8: begin
                interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector1_command_issue_w;
            end
            4'd9: begin
                interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w;
            end
            4'd10: begin
                interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w;
            end
            4'd11: begin
                interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w;
            end
            4'd12: begin
                interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata_w;
            end
            4'd13: begin
                interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w;
            end
            4'd14: begin
                interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector2_command_issue_w;
            end
            4'd15: begin
                interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w;
            end
            5'd16: begin
                interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w;
            end
            5'd17: begin
                interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w;
            end
            5'd18: begin
                interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata_w;
            end
            5'd19: begin
                interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_command0_w;
            end
            5'd20: begin
                interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector3_command_issue_w;
            end
            5'd21: begin
                interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address0_w;
            end
            5'd22: begin
                interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_baddress0_w;
            end
            5'd23: begin
                interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata0_w;
            end
            5'd24: begin
                interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata_w;
            end
        endcase
    end
    if (csrbank1_dfii_control0_re) begin
        soc_litedramcore_storage <= csrbank1_dfii_control0_r;
    end
    soc_litedramcore_re <= csrbank1_dfii_control0_re;
    if (csrbank1_dfii_pi0_command0_re) begin
        soc_litedramcore_phaseinjector0_command_storage <= csrbank1_dfii_pi0_command0_r;
    end
    soc_litedramcore_phaseinjector0_command_re <= csrbank1_dfii_pi0_command0_re;
    if (csrbank1_dfii_pi0_address0_re) begin
        soc_litedramcore_phaseinjector0_address_storage <= csrbank1_dfii_pi0_address0_r;
    end
    soc_litedramcore_phaseinjector0_address_re <= csrbank1_dfii_pi0_address0_re;
    if (csrbank1_dfii_pi0_baddress0_re) begin
        soc_litedramcore_phaseinjector0_baddress_storage <= csrbank1_dfii_pi0_baddress0_r;
    end
    soc_litedramcore_phaseinjector0_baddress_re <= csrbank1_dfii_pi0_baddress0_re;
    if (csrbank1_dfii_pi0_wrdata0_re) begin
        soc_litedramcore_phaseinjector0_wrdata_storage <= csrbank1_dfii_pi0_wrdata0_r;
    end
    soc_litedramcore_phaseinjector0_wrdata_re <= csrbank1_dfii_pi0_wrdata0_re;
    soc_litedramcore_phaseinjector0_rddata_re <= csrbank1_dfii_pi0_rddata_re;
    if (csrbank1_dfii_pi1_command0_re) begin
        soc_litedramcore_phaseinjector1_command_storage <= csrbank1_dfii_pi1_command0_r;
    end
    soc_litedramcore_phaseinjector1_command_re <= csrbank1_dfii_pi1_command0_re;
    if (csrbank1_dfii_pi1_address0_re) begin
        soc_litedramcore_phaseinjector1_address_storage <= csrbank1_dfii_pi1_address0_r;
    end
    soc_litedramcore_phaseinjector1_address_re <= csrbank1_dfii_pi1_address0_re;
    if (csrbank1_dfii_pi1_baddress0_re) begin
        soc_litedramcore_phaseinjector1_baddress_storage <= csrbank1_dfii_pi1_baddress0_r;
    end
    soc_litedramcore_phaseinjector1_baddress_re <= csrbank1_dfii_pi1_baddress0_re;
    if (csrbank1_dfii_pi1_wrdata0_re) begin
        soc_litedramcore_phaseinjector1_wrdata_storage <= csrbank1_dfii_pi1_wrdata0_r;
    end
    soc_litedramcore_phaseinjector1_wrdata_re <= csrbank1_dfii_pi1_wrdata0_re;
    soc_litedramcore_phaseinjector1_rddata_re <= csrbank1_dfii_pi1_rddata_re;
    if (csrbank1_dfii_pi2_command0_re) begin
        soc_litedramcore_phaseinjector2_command_storage <= csrbank1_dfii_pi2_command0_r;
    end
    soc_litedramcore_phaseinjector2_command_re <= csrbank1_dfii_pi2_command0_re;
    if (csrbank1_dfii_pi2_address0_re) begin
        soc_litedramcore_phaseinjector2_address_storage <= csrbank1_dfii_pi2_address0_r;
    end
    soc_litedramcore_phaseinjector2_address_re <= csrbank1_dfii_pi2_address0_re;
    if (csrbank1_dfii_pi2_baddress0_re) begin
        soc_litedramcore_phaseinjector2_baddress_storage <= csrbank1_dfii_pi2_baddress0_r;
    end
    soc_litedramcore_phaseinjector2_baddress_re <= csrbank1_dfii_pi2_baddress0_re;
    if (csrbank1_dfii_pi2_wrdata0_re) begin
        soc_litedramcore_phaseinjector2_wrdata_storage <= csrbank1_dfii_pi2_wrdata0_r;
    end
    soc_litedramcore_phaseinjector2_wrdata_re <= csrbank1_dfii_pi2_wrdata0_re;
    soc_litedramcore_phaseinjector2_rddata_re <= csrbank1_dfii_pi2_rddata_re;
    if (csrbank1_dfii_pi3_command0_re) begin
        soc_litedramcore_phaseinjector3_command_storage <= csrbank1_dfii_pi3_command0_r;
    end
    soc_litedramcore_phaseinjector3_command_re <= csrbank1_dfii_pi3_command0_re;
    if (csrbank1_dfii_pi3_address0_re) begin
        soc_litedramcore_phaseinjector3_address_storage <= csrbank1_dfii_pi3_address0_r;
    end
    soc_litedramcore_phaseinjector3_address_re <= csrbank1_dfii_pi3_address0_re;
    if (csrbank1_dfii_pi3_baddress0_re) begin
        soc_litedramcore_phaseinjector3_baddress_storage <= csrbank1_dfii_pi3_baddress0_r;
    end
    soc_litedramcore_phaseinjector3_baddress_re <= csrbank1_dfii_pi3_baddress0_re;
    if (csrbank1_dfii_pi3_wrdata0_re) begin
        soc_litedramcore_phaseinjector3_wrdata_storage <= csrbank1_dfii_pi3_wrdata0_r;
    end
    soc_litedramcore_phaseinjector3_wrdata_re <= csrbank1_dfii_pi3_wrdata0_re;
    soc_litedramcore_phaseinjector3_rddata_re <= csrbank1_dfii_pi3_rddata_re;
    if (sys_rst) begin
        soc_ddrphy_bankmodel0_active <= 1'd0;
        soc_ddrphy_bankmodel0_row <= 14'd0;
        soc_ddrphy_bankmodel1_active <= 1'd0;
        soc_ddrphy_bankmodel1_row <= 14'd0;
        soc_ddrphy_bankmodel2_active <= 1'd0;
        soc_ddrphy_bankmodel2_row <= 14'd0;
        soc_ddrphy_bankmodel3_active <= 1'd0;
        soc_ddrphy_bankmodel3_row <= 14'd0;
        soc_ddrphy_bankmodel4_active <= 1'd0;
        soc_ddrphy_bankmodel4_row <= 14'd0;
        soc_ddrphy_bankmodel5_active <= 1'd0;
        soc_ddrphy_bankmodel5_row <= 14'd0;
        soc_ddrphy_bankmodel6_active <= 1'd0;
        soc_ddrphy_bankmodel6_row <= 14'd0;
        soc_ddrphy_bankmodel7_active <= 1'd0;
        soc_ddrphy_bankmodel7_row <= 14'd0;
        soc_ddrphy_new_bank_write0 <= 1'd0;
        soc_ddrphy_new_bank_write_col0 <= 10'd0;
        soc_ddrphy_new_bank_write1 <= 1'd0;
        soc_ddrphy_new_bank_write_col1 <= 10'd0;
        soc_ddrphy_new_bank_write2 <= 1'd0;
        soc_ddrphy_new_bank_write_col2 <= 10'd0;
        soc_ddrphy_new_bank_write3 <= 1'd0;
        soc_ddrphy_new_bank_write_col3 <= 10'd0;
        soc_ddrphy_new_bank_write4 <= 1'd0;
        soc_ddrphy_new_bank_write_col4 <= 10'd0;
        soc_ddrphy_new_bank_write5 <= 1'd0;
        soc_ddrphy_new_bank_write_col5 <= 10'd0;
        soc_ddrphy_new_bank_write6 <= 1'd0;
        soc_ddrphy_new_bank_write_col6 <= 10'd0;
        soc_ddrphy_new_bank_write7 <= 1'd0;
        soc_ddrphy_new_bank_write_col7 <= 10'd0;
        soc_ddrphy_new_banks_read0 <= 1'd0;
        soc_ddrphy_new_banks_read_data0 <= 128'd0;
        soc_ddrphy_new_banks_read1 <= 1'd0;
        soc_ddrphy_new_banks_read_data1 <= 128'd0;
        soc_ddrphy_new_banks_read2 <= 1'd0;
        soc_ddrphy_new_banks_read_data2 <= 128'd0;
        soc_ddrphy_new_banks_read3 <= 1'd0;
        soc_ddrphy_new_banks_read_data3 <= 128'd0;
        soc_ddrphy_new_banks_read4 <= 1'd0;
        soc_ddrphy_new_banks_read_data4 <= 128'd0;
        soc_ddrphy_new_banks_read5 <= 1'd0;
        soc_ddrphy_new_banks_read_data5 <= 128'd0;
        soc_ddrphy_new_banks_read6 <= 1'd0;
        soc_ddrphy_new_banks_read_data6 <= 128'd0;
        soc_ddrphy_new_banks_read7 <= 1'd0;
        soc_ddrphy_new_banks_read_data7 <= 128'd0;
        soc_litedramcore_storage <= 4'd1;
        soc_litedramcore_re <= 1'd0;
        soc_litedramcore_phaseinjector0_command_storage <= 8'd0;
        soc_litedramcore_phaseinjector0_command_re <= 1'd0;
        soc_litedramcore_phaseinjector0_address_re <= 1'd0;
        soc_litedramcore_phaseinjector0_baddress_re <= 1'd0;
        soc_litedramcore_phaseinjector0_wrdata_re <= 1'd0;
        soc_litedramcore_phaseinjector0_rddata_status <= 32'd0;
        soc_litedramcore_phaseinjector0_rddata_re <= 1'd0;
        soc_litedramcore_phaseinjector1_command_storage <= 8'd0;
        soc_litedramcore_phaseinjector1_command_re <= 1'd0;
        soc_litedramcore_phaseinjector1_address_re <= 1'd0;
        soc_litedramcore_phaseinjector1_baddress_re <= 1'd0;
        soc_litedramcore_phaseinjector1_wrdata_re <= 1'd0;
        soc_litedramcore_phaseinjector1_rddata_status <= 32'd0;
        soc_litedramcore_phaseinjector1_rddata_re <= 1'd0;
        soc_litedramcore_phaseinjector2_command_storage <= 8'd0;
        soc_litedramcore_phaseinjector2_command_re <= 1'd0;
        soc_litedramcore_phaseinjector2_address_re <= 1'd0;
        soc_litedramcore_phaseinjector2_baddress_re <= 1'd0;
        soc_litedramcore_phaseinjector2_wrdata_re <= 1'd0;
        soc_litedramcore_phaseinjector2_rddata_status <= 32'd0;
        soc_litedramcore_phaseinjector2_rddata_re <= 1'd0;
        soc_litedramcore_phaseinjector3_command_storage <= 8'd0;
        soc_litedramcore_phaseinjector3_command_re <= 1'd0;
        soc_litedramcore_phaseinjector3_address_re <= 1'd0;
        soc_litedramcore_phaseinjector3_baddress_re <= 1'd0;
        soc_litedramcore_phaseinjector3_wrdata_re <= 1'd0;
        soc_litedramcore_phaseinjector3_rddata_status <= 32'd0;
        soc_litedramcore_phaseinjector3_rddata_re <= 1'd0;
        soc_litedramcore_dfi_p0_address <= 14'd0;
        soc_litedramcore_dfi_p0_bank <= 3'd0;
        soc_litedramcore_dfi_p0_cas_n <= 1'd1;
        soc_litedramcore_dfi_p0_cs_n <= 1'd1;
        soc_litedramcore_dfi_p0_ras_n <= 1'd1;
        soc_litedramcore_dfi_p0_we_n <= 1'd1;
        soc_litedramcore_dfi_p0_wrdata_en <= 1'd0;
        soc_litedramcore_dfi_p0_rddata_en <= 1'd0;
        soc_litedramcore_dfi_p1_address <= 14'd0;
        soc_litedramcore_dfi_p1_bank <= 3'd0;
        soc_litedramcore_dfi_p1_cas_n <= 1'd1;
        soc_litedramcore_dfi_p1_cs_n <= 1'd1;
        soc_litedramcore_dfi_p1_ras_n <= 1'd1;
        soc_litedramcore_dfi_p1_we_n <= 1'd1;
        soc_litedramcore_dfi_p1_wrdata_en <= 1'd0;
        soc_litedramcore_dfi_p1_rddata_en <= 1'd0;
        soc_litedramcore_dfi_p2_address <= 14'd0;
        soc_litedramcore_dfi_p2_bank <= 3'd0;
        soc_litedramcore_dfi_p2_cas_n <= 1'd1;
        soc_litedramcore_dfi_p2_cs_n <= 1'd1;
        soc_litedramcore_dfi_p2_ras_n <= 1'd1;
        soc_litedramcore_dfi_p2_we_n <= 1'd1;
        soc_litedramcore_dfi_p2_wrdata_en <= 1'd0;
        soc_litedramcore_dfi_p2_rddata_en <= 1'd0;
        soc_litedramcore_dfi_p3_address <= 14'd0;
        soc_litedramcore_dfi_p3_bank <= 3'd0;
        soc_litedramcore_dfi_p3_cas_n <= 1'd1;
        soc_litedramcore_dfi_p3_cs_n <= 1'd1;
        soc_litedramcore_dfi_p3_ras_n <= 1'd1;
        soc_litedramcore_dfi_p3_we_n <= 1'd1;
        soc_litedramcore_dfi_p3_wrdata_en <= 1'd0;
        soc_litedramcore_dfi_p3_rddata_en <= 1'd0;
        soc_litedramcore_cmd_payload_a <= 14'd0;
        soc_litedramcore_cmd_payload_ba <= 3'd0;
        soc_litedramcore_cmd_payload_cas <= 1'd0;
        soc_litedramcore_cmd_payload_ras <= 1'd0;
        soc_litedramcore_cmd_payload_we <= 1'd0;
        soc_litedramcore_timer_count1 <= 10'd781;
        soc_litedramcore_postponer_req_o <= 1'd0;
        soc_litedramcore_postponer_count <= 1'd0;
        soc_litedramcore_sequencer_done1 <= 1'd0;
        soc_litedramcore_sequencer_trigger <= 6'd0;
        soc_litedramcore_sequencer_count <= 1'd0;
        soc_litedramcore_zqcs_timer_count1 <= 27'd99999999;
        soc_litedramcore_zqcs_executer_done <= 1'd0;
        soc_litedramcore_zqcs_executer_trigger <= 5'd0;
        soc_litedramcore_bankmachine0_level <= 5'd0;
        soc_litedramcore_bankmachine0_produce <= 4'd0;
        soc_litedramcore_bankmachine0_consume <= 4'd0;
        soc_litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0;
        soc_litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0;
        soc_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 21'd0;
        soc_litedramcore_bankmachine0_row <= 14'd0;
        soc_litedramcore_bankmachine0_row_opened <= 1'd0;
        soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
        soc_litedramcore_bankmachine0_twtpcon_count <= 3'd0;
        soc_litedramcore_bankmachine0_trccon_ready <= 1'd0;
        soc_litedramcore_bankmachine0_trccon_count <= 3'd0;
        soc_litedramcore_bankmachine0_trascon_ready <= 1'd0;
        soc_litedramcore_bankmachine0_trascon_count <= 3'd0;
        soc_litedramcore_bankmachine1_level <= 5'd0;
        soc_litedramcore_bankmachine1_produce <= 4'd0;
        soc_litedramcore_bankmachine1_consume <= 4'd0;
        soc_litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0;
        soc_litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0;
        soc_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 21'd0;
        soc_litedramcore_bankmachine1_row <= 14'd0;
        soc_litedramcore_bankmachine1_row_opened <= 1'd0;
        soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
        soc_litedramcore_bankmachine1_twtpcon_count <= 3'd0;
        soc_litedramcore_bankmachine1_trccon_ready <= 1'd0;
        soc_litedramcore_bankmachine1_trccon_count <= 3'd0;
        soc_litedramcore_bankmachine1_trascon_ready <= 1'd0;
        soc_litedramcore_bankmachine1_trascon_count <= 3'd0;
        soc_litedramcore_bankmachine2_level <= 5'd0;
        soc_litedramcore_bankmachine2_produce <= 4'd0;
        soc_litedramcore_bankmachine2_consume <= 4'd0;
        soc_litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0;
        soc_litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0;
        soc_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 21'd0;
        soc_litedramcore_bankmachine2_row <= 14'd0;
        soc_litedramcore_bankmachine2_row_opened <= 1'd0;
        soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
        soc_litedramcore_bankmachine2_twtpcon_count <= 3'd0;
        soc_litedramcore_bankmachine2_trccon_ready <= 1'd0;
        soc_litedramcore_bankmachine2_trccon_count <= 3'd0;
        soc_litedramcore_bankmachine2_trascon_ready <= 1'd0;
        soc_litedramcore_bankmachine2_trascon_count <= 3'd0;
        soc_litedramcore_bankmachine3_level <= 5'd0;
        soc_litedramcore_bankmachine3_produce <= 4'd0;
        soc_litedramcore_bankmachine3_consume <= 4'd0;
        soc_litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0;
        soc_litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0;
        soc_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 21'd0;
        soc_litedramcore_bankmachine3_row <= 14'd0;
        soc_litedramcore_bankmachine3_row_opened <= 1'd0;
        soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
        soc_litedramcore_bankmachine3_twtpcon_count <= 3'd0;
        soc_litedramcore_bankmachine3_trccon_ready <= 1'd0;
        soc_litedramcore_bankmachine3_trccon_count <= 3'd0;
        soc_litedramcore_bankmachine3_trascon_ready <= 1'd0;
        soc_litedramcore_bankmachine3_trascon_count <= 3'd0;
        soc_litedramcore_bankmachine4_level <= 5'd0;
        soc_litedramcore_bankmachine4_produce <= 4'd0;
        soc_litedramcore_bankmachine4_consume <= 4'd0;
        soc_litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0;
        soc_litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0;
        soc_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 21'd0;
        soc_litedramcore_bankmachine4_row <= 14'd0;
        soc_litedramcore_bankmachine4_row_opened <= 1'd0;
        soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
        soc_litedramcore_bankmachine4_twtpcon_count <= 3'd0;
        soc_litedramcore_bankmachine4_trccon_ready <= 1'd0;
        soc_litedramcore_bankmachine4_trccon_count <= 3'd0;
        soc_litedramcore_bankmachine4_trascon_ready <= 1'd0;
        soc_litedramcore_bankmachine4_trascon_count <= 3'd0;
        soc_litedramcore_bankmachine5_level <= 5'd0;
        soc_litedramcore_bankmachine5_produce <= 4'd0;
        soc_litedramcore_bankmachine5_consume <= 4'd0;
        soc_litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0;
        soc_litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0;
        soc_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 21'd0;
        soc_litedramcore_bankmachine5_row <= 14'd0;
        soc_litedramcore_bankmachine5_row_opened <= 1'd0;
        soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
        soc_litedramcore_bankmachine5_twtpcon_count <= 3'd0;
        soc_litedramcore_bankmachine5_trccon_ready <= 1'd0;
        soc_litedramcore_bankmachine5_trccon_count <= 3'd0;
        soc_litedramcore_bankmachine5_trascon_ready <= 1'd0;
        soc_litedramcore_bankmachine5_trascon_count <= 3'd0;
        soc_litedramcore_bankmachine6_level <= 5'd0;
        soc_litedramcore_bankmachine6_produce <= 4'd0;
        soc_litedramcore_bankmachine6_consume <= 4'd0;
        soc_litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0;
        soc_litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0;
        soc_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 21'd0;
        soc_litedramcore_bankmachine6_row <= 14'd0;
        soc_litedramcore_bankmachine6_row_opened <= 1'd0;
        soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
        soc_litedramcore_bankmachine6_twtpcon_count <= 3'd0;
        soc_litedramcore_bankmachine6_trccon_ready <= 1'd0;
        soc_litedramcore_bankmachine6_trccon_count <= 3'd0;
        soc_litedramcore_bankmachine6_trascon_ready <= 1'd0;
        soc_litedramcore_bankmachine6_trascon_count <= 3'd0;
        soc_litedramcore_bankmachine7_level <= 5'd0;
        soc_litedramcore_bankmachine7_produce <= 4'd0;
        soc_litedramcore_bankmachine7_consume <= 4'd0;
        soc_litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0;
        soc_litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0;
        soc_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 21'd0;
        soc_litedramcore_bankmachine7_row <= 14'd0;
        soc_litedramcore_bankmachine7_row_opened <= 1'd0;
        soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
        soc_litedramcore_bankmachine7_twtpcon_count <= 3'd0;
        soc_litedramcore_bankmachine7_trccon_ready <= 1'd0;
        soc_litedramcore_bankmachine7_trccon_count <= 3'd0;
        soc_litedramcore_bankmachine7_trascon_ready <= 1'd0;
        soc_litedramcore_bankmachine7_trascon_count <= 3'd0;
        soc_litedramcore_choose_cmd_grant <= 3'd0;
        soc_litedramcore_choose_req_grant <= 3'd0;
        soc_litedramcore_trrdcon_ready <= 1'd0;
        soc_litedramcore_trrdcon_count <= 1'd0;
        soc_litedramcore_tfawcon_ready <= 1'd1;
        soc_litedramcore_tfawcon_window <= 5'd0;
        soc_litedramcore_tccdcon_ready <= 1'd0;
        soc_litedramcore_tccdcon_count <= 1'd0;
        soc_litedramcore_twtrcon_ready <= 1'd0;
        soc_litedramcore_twtrcon_count <= 3'd0;
        soc_litedramcore_time0 <= 5'd0;
        soc_litedramcore_time1 <= 4'd0;
        soc_init_done_storage <= 1'd0;
        soc_init_done_re <= 1'd0;
        soc_init_error_storage <= 1'd0;
        soc_init_error_re <= 1'd0;
        interface1_re <= 1'd0;
        interface1_we <= 1'd0;
        refresher_state <= 2'd0;
        bankmachine0_state <= 4'd0;
        bankmachine1_state <= 4'd0;
        bankmachine2_state <= 4'd0;
        bankmachine3_state <= 4'd0;
        bankmachine4_state <= 4'd0;
        bankmachine5_state <= 4'd0;
        bankmachine6_state <= 4'd0;
        bankmachine7_state <= 4'd0;
        multiplexer_state <= 4'd0;
        new_master_wdata_ready0 <= 1'd0;
        new_master_wdata_ready1 <= 1'd0;
        new_master_rdata_valid0 <= 1'd0;
        new_master_rdata_valid1 <= 1'd0;
        new_master_rdata_valid2 <= 1'd0;
        new_master_rdata_valid3 <= 1'd0;
        new_master_rdata_valid4 <= 1'd0;
        new_master_rdata_valid5 <= 1'd0;
        new_master_rdata_valid6 <= 1'd0;
        new_master_rdata_valid7 <= 1'd0;
        new_master_rdata_valid8 <= 1'd0;
        state <= 2'd0;
    end
end


//------------------------------------------------------------------------------
// Specialized Logic
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
// Memory mem: 2097152-words x 128-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
// Port 1 | Read: Async | Write: ---- | 
reg [127:0] mem[0:2097151];
reg [20:0] mem_adr0;
always @(posedge sys_clk) begin
	if (soc_ddrphy_bankmodel0_write_port_we[0])
		mem[soc_ddrphy_bankmodel0_write_port_adr][7:0] <= soc_ddrphy_bankmodel0_write_port_dat_w[7:0];
	if (soc_ddrphy_bankmodel0_write_port_we[1])
		mem[soc_ddrphy_bankmodel0_write_port_adr][15:8] <= soc_ddrphy_bankmodel0_write_port_dat_w[15:8];
	if (soc_ddrphy_bankmodel0_write_port_we[2])
		mem[soc_ddrphy_bankmodel0_write_port_adr][23:16] <= soc_ddrphy_bankmodel0_write_port_dat_w[23:16];
	if (soc_ddrphy_bankmodel0_write_port_we[3])
		mem[soc_ddrphy_bankmodel0_write_port_adr][31:24] <= soc_ddrphy_bankmodel0_write_port_dat_w[31:24];
	if (soc_ddrphy_bankmodel0_write_port_we[4])
		mem[soc_ddrphy_bankmodel0_write_port_adr][39:32] <= soc_ddrphy_bankmodel0_write_port_dat_w[39:32];
	if (soc_ddrphy_bankmodel0_write_port_we[5])
		mem[soc_ddrphy_bankmodel0_write_port_adr][47:40] <= soc_ddrphy_bankmodel0_write_port_dat_w[47:40];
	if (soc_ddrphy_bankmodel0_write_port_we[6])
		mem[soc_ddrphy_bankmodel0_write_port_adr][55:48] <= soc_ddrphy_bankmodel0_write_port_dat_w[55:48];
	if (soc_ddrphy_bankmodel0_write_port_we[7])
		mem[soc_ddrphy_bankmodel0_write_port_adr][63:56] <= soc_ddrphy_bankmodel0_write_port_dat_w[63:56];
	if (soc_ddrphy_bankmodel0_write_port_we[8])
		mem[soc_ddrphy_bankmodel0_write_port_adr][71:64] <= soc_ddrphy_bankmodel0_write_port_dat_w[71:64];
	if (soc_ddrphy_bankmodel0_write_port_we[9])
		mem[soc_ddrphy_bankmodel0_write_port_adr][79:72] <= soc_ddrphy_bankmodel0_write_port_dat_w[79:72];
	if (soc_ddrphy_bankmodel0_write_port_we[10])
		mem[soc_ddrphy_bankmodel0_write_port_adr][87:80] <= soc_ddrphy_bankmodel0_write_port_dat_w[87:80];
	if (soc_ddrphy_bankmodel0_write_port_we[11])
		mem[soc_ddrphy_bankmodel0_write_port_adr][95:88] <= soc_ddrphy_bankmodel0_write_port_dat_w[95:88];
	if (soc_ddrphy_bankmodel0_write_port_we[12])
		mem[soc_ddrphy_bankmodel0_write_port_adr][103:96] <= soc_ddrphy_bankmodel0_write_port_dat_w[103:96];
	if (soc_ddrphy_bankmodel0_write_port_we[13])
		mem[soc_ddrphy_bankmodel0_write_port_adr][111:104] <= soc_ddrphy_bankmodel0_write_port_dat_w[111:104];
	if (soc_ddrphy_bankmodel0_write_port_we[14])
		mem[soc_ddrphy_bankmodel0_write_port_adr][119:112] <= soc_ddrphy_bankmodel0_write_port_dat_w[119:112];
	if (soc_ddrphy_bankmodel0_write_port_we[15])
		mem[soc_ddrphy_bankmodel0_write_port_adr][127:120] <= soc_ddrphy_bankmodel0_write_port_dat_w[127:120];
	mem_adr0 <= soc_ddrphy_bankmodel0_write_port_adr;
end
always @(posedge sys_clk) begin
end
assign soc_ddrphy_bankmodel0_write_port_dat_r = mem[mem_adr0];
assign soc_ddrphy_bankmodel0_read_port_dat_r = mem[soc_ddrphy_bankmodel0_read_port_adr];


//------------------------------------------------------------------------------
// Memory mem_1: 2097152-words x 128-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
// Port 1 | Read: Async | Write: ---- | 
reg [127:0] mem_1[0:2097151];
reg [20:0] mem_1_adr0;
always @(posedge sys_clk) begin
	if (soc_ddrphy_bankmodel1_write_port_we[0])
		mem_1[soc_ddrphy_bankmodel1_write_port_adr][7:0] <= soc_ddrphy_bankmodel1_write_port_dat_w[7:0];
	if (soc_ddrphy_bankmodel1_write_port_we[1])
		mem_1[soc_ddrphy_bankmodel1_write_port_adr][15:8] <= soc_ddrphy_bankmodel1_write_port_dat_w[15:8];
	if (soc_ddrphy_bankmodel1_write_port_we[2])
		mem_1[soc_ddrphy_bankmodel1_write_port_adr][23:16] <= soc_ddrphy_bankmodel1_write_port_dat_w[23:16];
	if (soc_ddrphy_bankmodel1_write_port_we[3])
		mem_1[soc_ddrphy_bankmodel1_write_port_adr][31:24] <= soc_ddrphy_bankmodel1_write_port_dat_w[31:24];
	if (soc_ddrphy_bankmodel1_write_port_we[4])
		mem_1[soc_ddrphy_bankmodel1_write_port_adr][39:32] <= soc_ddrphy_bankmodel1_write_port_dat_w[39:32];
	if (soc_ddrphy_bankmodel1_write_port_we[5])
		mem_1[soc_ddrphy_bankmodel1_write_port_adr][47:40] <= soc_ddrphy_bankmodel1_write_port_dat_w[47:40];
	if (soc_ddrphy_bankmodel1_write_port_we[6])
		mem_1[soc_ddrphy_bankmodel1_write_port_adr][55:48] <= soc_ddrphy_bankmodel1_write_port_dat_w[55:48];
	if (soc_ddrphy_bankmodel1_write_port_we[7])
		mem_1[soc_ddrphy_bankmodel1_write_port_adr][63:56] <= soc_ddrphy_bankmodel1_write_port_dat_w[63:56];
	if (soc_ddrphy_bankmodel1_write_port_we[8])
		mem_1[soc_ddrphy_bankmodel1_write_port_adr][71:64] <= soc_ddrphy_bankmodel1_write_port_dat_w[71:64];
	if (soc_ddrphy_bankmodel1_write_port_we[9])
		mem_1[soc_ddrphy_bankmodel1_write_port_adr][79:72] <= soc_ddrphy_bankmodel1_write_port_dat_w[79:72];
	if (soc_ddrphy_bankmodel1_write_port_we[10])
		mem_1[soc_ddrphy_bankmodel1_write_port_adr][87:80] <= soc_ddrphy_bankmodel1_write_port_dat_w[87:80];
	if (soc_ddrphy_bankmodel1_write_port_we[11])
		mem_1[soc_ddrphy_bankmodel1_write_port_adr][95:88] <= soc_ddrphy_bankmodel1_write_port_dat_w[95:88];
	if (soc_ddrphy_bankmodel1_write_port_we[12])
		mem_1[soc_ddrphy_bankmodel1_write_port_adr][103:96] <= soc_ddrphy_bankmodel1_write_port_dat_w[103:96];
	if (soc_ddrphy_bankmodel1_write_port_we[13])
		mem_1[soc_ddrphy_bankmodel1_write_port_adr][111:104] <= soc_ddrphy_bankmodel1_write_port_dat_w[111:104];
	if (soc_ddrphy_bankmodel1_write_port_we[14])
		mem_1[soc_ddrphy_bankmodel1_write_port_adr][119:112] <= soc_ddrphy_bankmodel1_write_port_dat_w[119:112];
	if (soc_ddrphy_bankmodel1_write_port_we[15])
		mem_1[soc_ddrphy_bankmodel1_write_port_adr][127:120] <= soc_ddrphy_bankmodel1_write_port_dat_w[127:120];
	mem_1_adr0 <= soc_ddrphy_bankmodel1_write_port_adr;
end
always @(posedge sys_clk) begin
end
assign soc_ddrphy_bankmodel1_write_port_dat_r = mem_1[mem_1_adr0];
assign soc_ddrphy_bankmodel1_read_port_dat_r = mem_1[soc_ddrphy_bankmodel1_read_port_adr];


//------------------------------------------------------------------------------
// Memory mem_2: 2097152-words x 128-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
// Port 1 | Read: Async | Write: ---- | 
reg [127:0] mem_2[0:2097151];
reg [20:0] mem_2_adr0;
always @(posedge sys_clk) begin
	if (soc_ddrphy_bankmodel2_write_port_we[0])
		mem_2[soc_ddrphy_bankmodel2_write_port_adr][7:0] <= soc_ddrphy_bankmodel2_write_port_dat_w[7:0];
	if (soc_ddrphy_bankmodel2_write_port_we[1])
		mem_2[soc_ddrphy_bankmodel2_write_port_adr][15:8] <= soc_ddrphy_bankmodel2_write_port_dat_w[15:8];
	if (soc_ddrphy_bankmodel2_write_port_we[2])
		mem_2[soc_ddrphy_bankmodel2_write_port_adr][23:16] <= soc_ddrphy_bankmodel2_write_port_dat_w[23:16];
	if (soc_ddrphy_bankmodel2_write_port_we[3])
		mem_2[soc_ddrphy_bankmodel2_write_port_adr][31:24] <= soc_ddrphy_bankmodel2_write_port_dat_w[31:24];
	if (soc_ddrphy_bankmodel2_write_port_we[4])
		mem_2[soc_ddrphy_bankmodel2_write_port_adr][39:32] <= soc_ddrphy_bankmodel2_write_port_dat_w[39:32];
	if (soc_ddrphy_bankmodel2_write_port_we[5])
		mem_2[soc_ddrphy_bankmodel2_write_port_adr][47:40] <= soc_ddrphy_bankmodel2_write_port_dat_w[47:40];
	if (soc_ddrphy_bankmodel2_write_port_we[6])
		mem_2[soc_ddrphy_bankmodel2_write_port_adr][55:48] <= soc_ddrphy_bankmodel2_write_port_dat_w[55:48];
	if (soc_ddrphy_bankmodel2_write_port_we[7])
		mem_2[soc_ddrphy_bankmodel2_write_port_adr][63:56] <= soc_ddrphy_bankmodel2_write_port_dat_w[63:56];
	if (soc_ddrphy_bankmodel2_write_port_we[8])
		mem_2[soc_ddrphy_bankmodel2_write_port_adr][71:64] <= soc_ddrphy_bankmodel2_write_port_dat_w[71:64];
	if (soc_ddrphy_bankmodel2_write_port_we[9])
		mem_2[soc_ddrphy_bankmodel2_write_port_adr][79:72] <= soc_ddrphy_bankmodel2_write_port_dat_w[79:72];
	if (soc_ddrphy_bankmodel2_write_port_we[10])
		mem_2[soc_ddrphy_bankmodel2_write_port_adr][87:80] <= soc_ddrphy_bankmodel2_write_port_dat_w[87:80];
	if (soc_ddrphy_bankmodel2_write_port_we[11])
		mem_2[soc_ddrphy_bankmodel2_write_port_adr][95:88] <= soc_ddrphy_bankmodel2_write_port_dat_w[95:88];
	if (soc_ddrphy_bankmodel2_write_port_we[12])
		mem_2[soc_ddrphy_bankmodel2_write_port_adr][103:96] <= soc_ddrphy_bankmodel2_write_port_dat_w[103:96];
	if (soc_ddrphy_bankmodel2_write_port_we[13])
		mem_2[soc_ddrphy_bankmodel2_write_port_adr][111:104] <= soc_ddrphy_bankmodel2_write_port_dat_w[111:104];
	if (soc_ddrphy_bankmodel2_write_port_we[14])
		mem_2[soc_ddrphy_bankmodel2_write_port_adr][119:112] <= soc_ddrphy_bankmodel2_write_port_dat_w[119:112];
	if (soc_ddrphy_bankmodel2_write_port_we[15])
		mem_2[soc_ddrphy_bankmodel2_write_port_adr][127:120] <= soc_ddrphy_bankmodel2_write_port_dat_w[127:120];
	mem_2_adr0 <= soc_ddrphy_bankmodel2_write_port_adr;
end
always @(posedge sys_clk) begin
end
assign soc_ddrphy_bankmodel2_write_port_dat_r = mem_2[mem_2_adr0];
assign soc_ddrphy_bankmodel2_read_port_dat_r = mem_2[soc_ddrphy_bankmodel2_read_port_adr];


//------------------------------------------------------------------------------
// Memory mem_3: 2097152-words x 128-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
// Port 1 | Read: Async | Write: ---- | 
reg [127:0] mem_3[0:2097151];
reg [20:0] mem_3_adr0;
always @(posedge sys_clk) begin
	if (soc_ddrphy_bankmodel3_write_port_we[0])
		mem_3[soc_ddrphy_bankmodel3_write_port_adr][7:0] <= soc_ddrphy_bankmodel3_write_port_dat_w[7:0];
	if (soc_ddrphy_bankmodel3_write_port_we[1])
		mem_3[soc_ddrphy_bankmodel3_write_port_adr][15:8] <= soc_ddrphy_bankmodel3_write_port_dat_w[15:8];
	if (soc_ddrphy_bankmodel3_write_port_we[2])
		mem_3[soc_ddrphy_bankmodel3_write_port_adr][23:16] <= soc_ddrphy_bankmodel3_write_port_dat_w[23:16];
	if (soc_ddrphy_bankmodel3_write_port_we[3])
		mem_3[soc_ddrphy_bankmodel3_write_port_adr][31:24] <= soc_ddrphy_bankmodel3_write_port_dat_w[31:24];
	if (soc_ddrphy_bankmodel3_write_port_we[4])
		mem_3[soc_ddrphy_bankmodel3_write_port_adr][39:32] <= soc_ddrphy_bankmodel3_write_port_dat_w[39:32];
	if (soc_ddrphy_bankmodel3_write_port_we[5])
		mem_3[soc_ddrphy_bankmodel3_write_port_adr][47:40] <= soc_ddrphy_bankmodel3_write_port_dat_w[47:40];
	if (soc_ddrphy_bankmodel3_write_port_we[6])
		mem_3[soc_ddrphy_bankmodel3_write_port_adr][55:48] <= soc_ddrphy_bankmodel3_write_port_dat_w[55:48];
	if (soc_ddrphy_bankmodel3_write_port_we[7])
		mem_3[soc_ddrphy_bankmodel3_write_port_adr][63:56] <= soc_ddrphy_bankmodel3_write_port_dat_w[63:56];
	if (soc_ddrphy_bankmodel3_write_port_we[8])
		mem_3[soc_ddrphy_bankmodel3_write_port_adr][71:64] <= soc_ddrphy_bankmodel3_write_port_dat_w[71:64];
	if (soc_ddrphy_bankmodel3_write_port_we[9])
		mem_3[soc_ddrphy_bankmodel3_write_port_adr][79:72] <= soc_ddrphy_bankmodel3_write_port_dat_w[79:72];
	if (soc_ddrphy_bankmodel3_write_port_we[10])
		mem_3[soc_ddrphy_bankmodel3_write_port_adr][87:80] <= soc_ddrphy_bankmodel3_write_port_dat_w[87:80];
	if (soc_ddrphy_bankmodel3_write_port_we[11])
		mem_3[soc_ddrphy_bankmodel3_write_port_adr][95:88] <= soc_ddrphy_bankmodel3_write_port_dat_w[95:88];
	if (soc_ddrphy_bankmodel3_write_port_we[12])
		mem_3[soc_ddrphy_bankmodel3_write_port_adr][103:96] <= soc_ddrphy_bankmodel3_write_port_dat_w[103:96];
	if (soc_ddrphy_bankmodel3_write_port_we[13])
		mem_3[soc_ddrphy_bankmodel3_write_port_adr][111:104] <= soc_ddrphy_bankmodel3_write_port_dat_w[111:104];
	if (soc_ddrphy_bankmodel3_write_port_we[14])
		mem_3[soc_ddrphy_bankmodel3_write_port_adr][119:112] <= soc_ddrphy_bankmodel3_write_port_dat_w[119:112];
	if (soc_ddrphy_bankmodel3_write_port_we[15])
		mem_3[soc_ddrphy_bankmodel3_write_port_adr][127:120] <= soc_ddrphy_bankmodel3_write_port_dat_w[127:120];
	mem_3_adr0 <= soc_ddrphy_bankmodel3_write_port_adr;
end
always @(posedge sys_clk) begin
end
assign soc_ddrphy_bankmodel3_write_port_dat_r = mem_3[mem_3_adr0];
assign soc_ddrphy_bankmodel3_read_port_dat_r = mem_3[soc_ddrphy_bankmodel3_read_port_adr];


//------------------------------------------------------------------------------
// Memory mem_4: 2097152-words x 128-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
// Port 1 | Read: Async | Write: ---- | 
reg [127:0] mem_4[0:2097151];
reg [20:0] mem_4_adr0;
always @(posedge sys_clk) begin
	if (soc_ddrphy_bankmodel4_write_port_we[0])
		mem_4[soc_ddrphy_bankmodel4_write_port_adr][7:0] <= soc_ddrphy_bankmodel4_write_port_dat_w[7:0];
	if (soc_ddrphy_bankmodel4_write_port_we[1])
		mem_4[soc_ddrphy_bankmodel4_write_port_adr][15:8] <= soc_ddrphy_bankmodel4_write_port_dat_w[15:8];
	if (soc_ddrphy_bankmodel4_write_port_we[2])
		mem_4[soc_ddrphy_bankmodel4_write_port_adr][23:16] <= soc_ddrphy_bankmodel4_write_port_dat_w[23:16];
	if (soc_ddrphy_bankmodel4_write_port_we[3])
		mem_4[soc_ddrphy_bankmodel4_write_port_adr][31:24] <= soc_ddrphy_bankmodel4_write_port_dat_w[31:24];
	if (soc_ddrphy_bankmodel4_write_port_we[4])
		mem_4[soc_ddrphy_bankmodel4_write_port_adr][39:32] <= soc_ddrphy_bankmodel4_write_port_dat_w[39:32];
	if (soc_ddrphy_bankmodel4_write_port_we[5])
		mem_4[soc_ddrphy_bankmodel4_write_port_adr][47:40] <= soc_ddrphy_bankmodel4_write_port_dat_w[47:40];
	if (soc_ddrphy_bankmodel4_write_port_we[6])
		mem_4[soc_ddrphy_bankmodel4_write_port_adr][55:48] <= soc_ddrphy_bankmodel4_write_port_dat_w[55:48];
	if (soc_ddrphy_bankmodel4_write_port_we[7])
		mem_4[soc_ddrphy_bankmodel4_write_port_adr][63:56] <= soc_ddrphy_bankmodel4_write_port_dat_w[63:56];
	if (soc_ddrphy_bankmodel4_write_port_we[8])
		mem_4[soc_ddrphy_bankmodel4_write_port_adr][71:64] <= soc_ddrphy_bankmodel4_write_port_dat_w[71:64];
	if (soc_ddrphy_bankmodel4_write_port_we[9])
		mem_4[soc_ddrphy_bankmodel4_write_port_adr][79:72] <= soc_ddrphy_bankmodel4_write_port_dat_w[79:72];
	if (soc_ddrphy_bankmodel4_write_port_we[10])
		mem_4[soc_ddrphy_bankmodel4_write_port_adr][87:80] <= soc_ddrphy_bankmodel4_write_port_dat_w[87:80];
	if (soc_ddrphy_bankmodel4_write_port_we[11])
		mem_4[soc_ddrphy_bankmodel4_write_port_adr][95:88] <= soc_ddrphy_bankmodel4_write_port_dat_w[95:88];
	if (soc_ddrphy_bankmodel4_write_port_we[12])
		mem_4[soc_ddrphy_bankmodel4_write_port_adr][103:96] <= soc_ddrphy_bankmodel4_write_port_dat_w[103:96];
	if (soc_ddrphy_bankmodel4_write_port_we[13])
		mem_4[soc_ddrphy_bankmodel4_write_port_adr][111:104] <= soc_ddrphy_bankmodel4_write_port_dat_w[111:104];
	if (soc_ddrphy_bankmodel4_write_port_we[14])
		mem_4[soc_ddrphy_bankmodel4_write_port_adr][119:112] <= soc_ddrphy_bankmodel4_write_port_dat_w[119:112];
	if (soc_ddrphy_bankmodel4_write_port_we[15])
		mem_4[soc_ddrphy_bankmodel4_write_port_adr][127:120] <= soc_ddrphy_bankmodel4_write_port_dat_w[127:120];
	mem_4_adr0 <= soc_ddrphy_bankmodel4_write_port_adr;
end
always @(posedge sys_clk) begin
end
assign soc_ddrphy_bankmodel4_write_port_dat_r = mem_4[mem_4_adr0];
assign soc_ddrphy_bankmodel4_read_port_dat_r = mem_4[soc_ddrphy_bankmodel4_read_port_adr];


//------------------------------------------------------------------------------
// Memory mem_5: 2097152-words x 128-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
// Port 1 | Read: Async | Write: ---- | 
reg [127:0] mem_5[0:2097151];
reg [20:0] mem_5_adr0;
always @(posedge sys_clk) begin
	if (soc_ddrphy_bankmodel5_write_port_we[0])
		mem_5[soc_ddrphy_bankmodel5_write_port_adr][7:0] <= soc_ddrphy_bankmodel5_write_port_dat_w[7:0];
	if (soc_ddrphy_bankmodel5_write_port_we[1])
		mem_5[soc_ddrphy_bankmodel5_write_port_adr][15:8] <= soc_ddrphy_bankmodel5_write_port_dat_w[15:8];
	if (soc_ddrphy_bankmodel5_write_port_we[2])
		mem_5[soc_ddrphy_bankmodel5_write_port_adr][23:16] <= soc_ddrphy_bankmodel5_write_port_dat_w[23:16];
	if (soc_ddrphy_bankmodel5_write_port_we[3])
		mem_5[soc_ddrphy_bankmodel5_write_port_adr][31:24] <= soc_ddrphy_bankmodel5_write_port_dat_w[31:24];
	if (soc_ddrphy_bankmodel5_write_port_we[4])
		mem_5[soc_ddrphy_bankmodel5_write_port_adr][39:32] <= soc_ddrphy_bankmodel5_write_port_dat_w[39:32];
	if (soc_ddrphy_bankmodel5_write_port_we[5])
		mem_5[soc_ddrphy_bankmodel5_write_port_adr][47:40] <= soc_ddrphy_bankmodel5_write_port_dat_w[47:40];
	if (soc_ddrphy_bankmodel5_write_port_we[6])
		mem_5[soc_ddrphy_bankmodel5_write_port_adr][55:48] <= soc_ddrphy_bankmodel5_write_port_dat_w[55:48];
	if (soc_ddrphy_bankmodel5_write_port_we[7])
		mem_5[soc_ddrphy_bankmodel5_write_port_adr][63:56] <= soc_ddrphy_bankmodel5_write_port_dat_w[63:56];
	if (soc_ddrphy_bankmodel5_write_port_we[8])
		mem_5[soc_ddrphy_bankmodel5_write_port_adr][71:64] <= soc_ddrphy_bankmodel5_write_port_dat_w[71:64];
	if (soc_ddrphy_bankmodel5_write_port_we[9])
		mem_5[soc_ddrphy_bankmodel5_write_port_adr][79:72] <= soc_ddrphy_bankmodel5_write_port_dat_w[79:72];
	if (soc_ddrphy_bankmodel5_write_port_we[10])
		mem_5[soc_ddrphy_bankmodel5_write_port_adr][87:80] <= soc_ddrphy_bankmodel5_write_port_dat_w[87:80];
	if (soc_ddrphy_bankmodel5_write_port_we[11])
		mem_5[soc_ddrphy_bankmodel5_write_port_adr][95:88] <= soc_ddrphy_bankmodel5_write_port_dat_w[95:88];
	if (soc_ddrphy_bankmodel5_write_port_we[12])
		mem_5[soc_ddrphy_bankmodel5_write_port_adr][103:96] <= soc_ddrphy_bankmodel5_write_port_dat_w[103:96];
	if (soc_ddrphy_bankmodel5_write_port_we[13])
		mem_5[soc_ddrphy_bankmodel5_write_port_adr][111:104] <= soc_ddrphy_bankmodel5_write_port_dat_w[111:104];
	if (soc_ddrphy_bankmodel5_write_port_we[14])
		mem_5[soc_ddrphy_bankmodel5_write_port_adr][119:112] <= soc_ddrphy_bankmodel5_write_port_dat_w[119:112];
	if (soc_ddrphy_bankmodel5_write_port_we[15])
		mem_5[soc_ddrphy_bankmodel5_write_port_adr][127:120] <= soc_ddrphy_bankmodel5_write_port_dat_w[127:120];
	mem_5_adr0 <= soc_ddrphy_bankmodel5_write_port_adr;
end
always @(posedge sys_clk) begin
end
assign soc_ddrphy_bankmodel5_write_port_dat_r = mem_5[mem_5_adr0];
assign soc_ddrphy_bankmodel5_read_port_dat_r = mem_5[soc_ddrphy_bankmodel5_read_port_adr];


//------------------------------------------------------------------------------
// Memory mem_6: 2097152-words x 128-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
// Port 1 | Read: Async | Write: ---- | 
reg [127:0] mem_6[0:2097151];
reg [20:0] mem_6_adr0;
always @(posedge sys_clk) begin
	if (soc_ddrphy_bankmodel6_write_port_we[0])
		mem_6[soc_ddrphy_bankmodel6_write_port_adr][7:0] <= soc_ddrphy_bankmodel6_write_port_dat_w[7:0];
	if (soc_ddrphy_bankmodel6_write_port_we[1])
		mem_6[soc_ddrphy_bankmodel6_write_port_adr][15:8] <= soc_ddrphy_bankmodel6_write_port_dat_w[15:8];
	if (soc_ddrphy_bankmodel6_write_port_we[2])
		mem_6[soc_ddrphy_bankmodel6_write_port_adr][23:16] <= soc_ddrphy_bankmodel6_write_port_dat_w[23:16];
	if (soc_ddrphy_bankmodel6_write_port_we[3])
		mem_6[soc_ddrphy_bankmodel6_write_port_adr][31:24] <= soc_ddrphy_bankmodel6_write_port_dat_w[31:24];
	if (soc_ddrphy_bankmodel6_write_port_we[4])
		mem_6[soc_ddrphy_bankmodel6_write_port_adr][39:32] <= soc_ddrphy_bankmodel6_write_port_dat_w[39:32];
	if (soc_ddrphy_bankmodel6_write_port_we[5])
		mem_6[soc_ddrphy_bankmodel6_write_port_adr][47:40] <= soc_ddrphy_bankmodel6_write_port_dat_w[47:40];
	if (soc_ddrphy_bankmodel6_write_port_we[6])
		mem_6[soc_ddrphy_bankmodel6_write_port_adr][55:48] <= soc_ddrphy_bankmodel6_write_port_dat_w[55:48];
	if (soc_ddrphy_bankmodel6_write_port_we[7])
		mem_6[soc_ddrphy_bankmodel6_write_port_adr][63:56] <= soc_ddrphy_bankmodel6_write_port_dat_w[63:56];
	if (soc_ddrphy_bankmodel6_write_port_we[8])
		mem_6[soc_ddrphy_bankmodel6_write_port_adr][71:64] <= soc_ddrphy_bankmodel6_write_port_dat_w[71:64];
	if (soc_ddrphy_bankmodel6_write_port_we[9])
		mem_6[soc_ddrphy_bankmodel6_write_port_adr][79:72] <= soc_ddrphy_bankmodel6_write_port_dat_w[79:72];
	if (soc_ddrphy_bankmodel6_write_port_we[10])
		mem_6[soc_ddrphy_bankmodel6_write_port_adr][87:80] <= soc_ddrphy_bankmodel6_write_port_dat_w[87:80];
	if (soc_ddrphy_bankmodel6_write_port_we[11])
		mem_6[soc_ddrphy_bankmodel6_write_port_adr][95:88] <= soc_ddrphy_bankmodel6_write_port_dat_w[95:88];
	if (soc_ddrphy_bankmodel6_write_port_we[12])
		mem_6[soc_ddrphy_bankmodel6_write_port_adr][103:96] <= soc_ddrphy_bankmodel6_write_port_dat_w[103:96];
	if (soc_ddrphy_bankmodel6_write_port_we[13])
		mem_6[soc_ddrphy_bankmodel6_write_port_adr][111:104] <= soc_ddrphy_bankmodel6_write_port_dat_w[111:104];
	if (soc_ddrphy_bankmodel6_write_port_we[14])
		mem_6[soc_ddrphy_bankmodel6_write_port_adr][119:112] <= soc_ddrphy_bankmodel6_write_port_dat_w[119:112];
	if (soc_ddrphy_bankmodel6_write_port_we[15])
		mem_6[soc_ddrphy_bankmodel6_write_port_adr][127:120] <= soc_ddrphy_bankmodel6_write_port_dat_w[127:120];
	mem_6_adr0 <= soc_ddrphy_bankmodel6_write_port_adr;
end
always @(posedge sys_clk) begin
end
assign soc_ddrphy_bankmodel6_write_port_dat_r = mem_6[mem_6_adr0];
assign soc_ddrphy_bankmodel6_read_port_dat_r = mem_6[soc_ddrphy_bankmodel6_read_port_adr];


//------------------------------------------------------------------------------
// Memory mem_7: 2097152-words x 128-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
// Port 1 | Read: Async | Write: ---- | 
reg [127:0] mem_7[0:2097151];
reg [20:0] mem_7_adr0;
always @(posedge sys_clk) begin
	if (soc_ddrphy_bankmodel7_write_port_we[0])
		mem_7[soc_ddrphy_bankmodel7_write_port_adr][7:0] <= soc_ddrphy_bankmodel7_write_port_dat_w[7:0];
	if (soc_ddrphy_bankmodel7_write_port_we[1])
		mem_7[soc_ddrphy_bankmodel7_write_port_adr][15:8] <= soc_ddrphy_bankmodel7_write_port_dat_w[15:8];
	if (soc_ddrphy_bankmodel7_write_port_we[2])
		mem_7[soc_ddrphy_bankmodel7_write_port_adr][23:16] <= soc_ddrphy_bankmodel7_write_port_dat_w[23:16];
	if (soc_ddrphy_bankmodel7_write_port_we[3])
		mem_7[soc_ddrphy_bankmodel7_write_port_adr][31:24] <= soc_ddrphy_bankmodel7_write_port_dat_w[31:24];
	if (soc_ddrphy_bankmodel7_write_port_we[4])
		mem_7[soc_ddrphy_bankmodel7_write_port_adr][39:32] <= soc_ddrphy_bankmodel7_write_port_dat_w[39:32];
	if (soc_ddrphy_bankmodel7_write_port_we[5])
		mem_7[soc_ddrphy_bankmodel7_write_port_adr][47:40] <= soc_ddrphy_bankmodel7_write_port_dat_w[47:40];
	if (soc_ddrphy_bankmodel7_write_port_we[6])
		mem_7[soc_ddrphy_bankmodel7_write_port_adr][55:48] <= soc_ddrphy_bankmodel7_write_port_dat_w[55:48];
	if (soc_ddrphy_bankmodel7_write_port_we[7])
		mem_7[soc_ddrphy_bankmodel7_write_port_adr][63:56] <= soc_ddrphy_bankmodel7_write_port_dat_w[63:56];
	if (soc_ddrphy_bankmodel7_write_port_we[8])
		mem_7[soc_ddrphy_bankmodel7_write_port_adr][71:64] <= soc_ddrphy_bankmodel7_write_port_dat_w[71:64];
	if (soc_ddrphy_bankmodel7_write_port_we[9])
		mem_7[soc_ddrphy_bankmodel7_write_port_adr][79:72] <= soc_ddrphy_bankmodel7_write_port_dat_w[79:72];
	if (soc_ddrphy_bankmodel7_write_port_we[10])
		mem_7[soc_ddrphy_bankmodel7_write_port_adr][87:80] <= soc_ddrphy_bankmodel7_write_port_dat_w[87:80];
	if (soc_ddrphy_bankmodel7_write_port_we[11])
		mem_7[soc_ddrphy_bankmodel7_write_port_adr][95:88] <= soc_ddrphy_bankmodel7_write_port_dat_w[95:88];
	if (soc_ddrphy_bankmodel7_write_port_we[12])
		mem_7[soc_ddrphy_bankmodel7_write_port_adr][103:96] <= soc_ddrphy_bankmodel7_write_port_dat_w[103:96];
	if (soc_ddrphy_bankmodel7_write_port_we[13])
		mem_7[soc_ddrphy_bankmodel7_write_port_adr][111:104] <= soc_ddrphy_bankmodel7_write_port_dat_w[111:104];
	if (soc_ddrphy_bankmodel7_write_port_we[14])
		mem_7[soc_ddrphy_bankmodel7_write_port_adr][119:112] <= soc_ddrphy_bankmodel7_write_port_dat_w[119:112];
	if (soc_ddrphy_bankmodel7_write_port_we[15])
		mem_7[soc_ddrphy_bankmodel7_write_port_adr][127:120] <= soc_ddrphy_bankmodel7_write_port_dat_w[127:120];
	mem_7_adr0 <= soc_ddrphy_bankmodel7_write_port_adr;
end
always @(posedge sys_clk) begin
end
assign soc_ddrphy_bankmodel7_write_port_dat_r = mem_7[mem_7_adr0];
assign soc_ddrphy_bankmodel7_read_port_dat_r = mem_7[soc_ddrphy_bankmodel7_read_port_adr];


//------------------------------------------------------------------------------
// Memory storage: 16-words x 24-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
// Port 1 | Read: Async | Write: ---- | 
reg [23:0] storage[0:15];
reg [23:0] storage_dat0;
always @(posedge sys_clk) begin
	if (soc_litedramcore_bankmachine0_wrport_we)
		storage[soc_litedramcore_bankmachine0_wrport_adr] <= soc_litedramcore_bankmachine0_wrport_dat_w;
	storage_dat0 <= storage[soc_litedramcore_bankmachine0_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_litedramcore_bankmachine0_wrport_dat_r = storage_dat0;
assign soc_litedramcore_bankmachine0_rdport_dat_r = storage[soc_litedramcore_bankmachine0_rdport_adr];


//------------------------------------------------------------------------------
// Memory storage_1: 16-words x 24-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
// Port 1 | Read: Async | Write: ---- | 
reg [23:0] storage_1[0:15];
reg [23:0] storage_1_dat0;
always @(posedge sys_clk) begin
	if (soc_litedramcore_bankmachine1_wrport_we)
		storage_1[soc_litedramcore_bankmachine1_wrport_adr] <= soc_litedramcore_bankmachine1_wrport_dat_w;
	storage_1_dat0 <= storage_1[soc_litedramcore_bankmachine1_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0;
assign soc_litedramcore_bankmachine1_rdport_dat_r = storage_1[soc_litedramcore_bankmachine1_rdport_adr];


//------------------------------------------------------------------------------
// Memory storage_2: 16-words x 24-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
// Port 1 | Read: Async | Write: ---- | 
reg [23:0] storage_2[0:15];
reg [23:0] storage_2_dat0;
always @(posedge sys_clk) begin
	if (soc_litedramcore_bankmachine2_wrport_we)
		storage_2[soc_litedramcore_bankmachine2_wrport_adr] <= soc_litedramcore_bankmachine2_wrport_dat_w;
	storage_2_dat0 <= storage_2[soc_litedramcore_bankmachine2_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0;
assign soc_litedramcore_bankmachine2_rdport_dat_r = storage_2[soc_litedramcore_bankmachine2_rdport_adr];


//------------------------------------------------------------------------------
// Memory storage_3: 16-words x 24-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
// Port 1 | Read: Async | Write: ---- | 
reg [23:0] storage_3[0:15];
reg [23:0] storage_3_dat0;
always @(posedge sys_clk) begin
	if (soc_litedramcore_bankmachine3_wrport_we)
		storage_3[soc_litedramcore_bankmachine3_wrport_adr] <= soc_litedramcore_bankmachine3_wrport_dat_w;
	storage_3_dat0 <= storage_3[soc_litedramcore_bankmachine3_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0;
assign soc_litedramcore_bankmachine3_rdport_dat_r = storage_3[soc_litedramcore_bankmachine3_rdport_adr];


//------------------------------------------------------------------------------
// Memory storage_4: 16-words x 24-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
// Port 1 | Read: Async | Write: ---- | 
reg [23:0] storage_4[0:15];
reg [23:0] storage_4_dat0;
always @(posedge sys_clk) begin
	if (soc_litedramcore_bankmachine4_wrport_we)
		storage_4[soc_litedramcore_bankmachine4_wrport_adr] <= soc_litedramcore_bankmachine4_wrport_dat_w;
	storage_4_dat0 <= storage_4[soc_litedramcore_bankmachine4_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0;
assign soc_litedramcore_bankmachine4_rdport_dat_r = storage_4[soc_litedramcore_bankmachine4_rdport_adr];


//------------------------------------------------------------------------------
// Memory storage_5: 16-words x 24-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
// Port 1 | Read: Async | Write: ---- | 
reg [23:0] storage_5[0:15];
reg [23:0] storage_5_dat0;
always @(posedge sys_clk) begin
	if (soc_litedramcore_bankmachine5_wrport_we)
		storage_5[soc_litedramcore_bankmachine5_wrport_adr] <= soc_litedramcore_bankmachine5_wrport_dat_w;
	storage_5_dat0 <= storage_5[soc_litedramcore_bankmachine5_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0;
assign soc_litedramcore_bankmachine5_rdport_dat_r = storage_5[soc_litedramcore_bankmachine5_rdport_adr];


//------------------------------------------------------------------------------
// Memory storage_6: 16-words x 24-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
// Port 1 | Read: Async | Write: ---- | 
reg [23:0] storage_6[0:15];
reg [23:0] storage_6_dat0;
always @(posedge sys_clk) begin
	if (soc_litedramcore_bankmachine6_wrport_we)
		storage_6[soc_litedramcore_bankmachine6_wrport_adr] <= soc_litedramcore_bankmachine6_wrport_dat_w;
	storage_6_dat0 <= storage_6[soc_litedramcore_bankmachine6_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0;
assign soc_litedramcore_bankmachine6_rdport_dat_r = storage_6[soc_litedramcore_bankmachine6_rdport_adr];


//------------------------------------------------------------------------------
// Memory storage_7: 16-words x 24-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 24 
// Port 1 | Read: Async | Write: ---- | 
reg [23:0] storage_7[0:15];
reg [23:0] storage_7_dat0;
always @(posedge sys_clk) begin
	if (soc_litedramcore_bankmachine7_wrport_we)
		storage_7[soc_litedramcore_bankmachine7_wrport_adr] <= soc_litedramcore_bankmachine7_wrport_dat_w;
	storage_7_dat0 <= storage_7[soc_litedramcore_bankmachine7_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0;
assign soc_litedramcore_bankmachine7_rdport_dat_r = storage_7[soc_litedramcore_bankmachine7_rdport_adr];


endmodule

// -----------------------------------------------------------------------------
//  Auto-Generated by LiteX on 2025-02-15 19:54:54.
//------------------------------------------------------------------------------
