From 066e38b8ea9208ff0a643cf816efb76c36a2a9c4 Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Sat, 6 Dec 2025 16:26:52 +1100 Subject: [PATCH] FPU: Do proper over/underflow handling for single-precision [fm]add The ADD_3 state incorporated some of the logic of the FINISH state, but in some cases assumed the result couldn't overflow or underflow - which is not true for single precision operations, if the input operands are outside the single precision range. Fix this, and simplify things, by having ADD_3 always go to FINISH state, which does the full overflow and underflow checking. Signed-off-by: Paul Mackerras --- fpu.vhdl | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/fpu.vhdl b/fpu.vhdl index 06596bb..e37ceb3 100644 --- a/fpu.vhdl +++ b/fpu.vhdl @@ -1866,25 +1866,14 @@ begin -- result is opposite sign to expected rsgn_op := RSGN_INV; set_r := '1'; - v.state := FINISH; elsif r.r(UNIT_BIT + 1) = '1' then -- sum overflowed, shift right opsel_r <= RES_SHIFT; set_r := '1'; re_set_result <= '1'; set_x := '1'; - if exp_huge = '1' then - v.state := ROUND_OFLOW; - else - v.state := ROUNDING; - end if; - elsif r.r(UNIT_BIT) = '1' then - set_x := '1'; - v.state := ROUNDING; - else - rs_norm <= '1'; - v.state := NORMALIZE; end if; + v.state := FINISH; when CMP_1 => opsel_a <= AIN_A;