diff --git a/fpga/top-acorn-cle-215.vhdl b/fpga/top-acorn-cle-215.vhdl
index 7f03506..693f700 100644
--- a/fpga/top-acorn-cle-215.vhdl
+++ b/fpga/top-acorn-cle-215.vhdl
@@ -10,6 +10,7 @@ use work.wishbone_types.all;
 
 entity toplevel is
     generic (
+        CPUS          : natural := 1;
 	MEMORY_SIZE   : integer := 16384;
 	RAM_INIT_FILE : string   := "firmware.hex";
 	CLK_FREQUENCY : positive := 100000000;
@@ -66,6 +67,9 @@ architecture behaviour of toplevel is
     -- Internal clock
     signal ext_clk : std_ulogic;
 
+    -- Status
+    signal run_outs : std_ulogic_vector(CPUS-1 downto 0);
+
     -- Reset signals:
     signal soc_rst : std_ulogic;
     signal pll_rst : std_ulogic;
@@ -124,6 +128,7 @@ begin
 	    MEMORY_SIZE   => BRAM_SIZE,
 	    RAM_INIT_FILE => RAM_INIT_FILE,
 	    SIM           => false,
+            NCPUS         => CPUS,
 	    CLK_FREQ      => CLK_FREQUENCY,
 	    HAS_DRAM      => USE_LITEDRAM,
 	    DRAM_SIZE     => 1024 * 1024 * 1024,
@@ -141,6 +146,7 @@ begin
             -- System signals
 	    system_clk        => system_clk,
 	    rst               => soc_rst,
+            run_outs          => run_outs,
 
             -- UART signals
             uart0_txd         => uart_tx,
@@ -223,10 +229,10 @@ begin
 		pll_locked_out => system_clk_locked
 		);
 
-	led0 <= soc_rst;
-	led1 <= pll_rst;
-        led2 <= not system_clk_locked;
-	led3 <= '0';
+	led0 <= run_outs(0);
+	led1 <= run_outs(1) when CPUS > 1 else pll_rst;
+        led2 <= run_outs(2) when CPUS > 2 else not system_clk_locked;
+	led3 <= run_outs(3) when CPUS > 3 else '0';
 
         -- Vivado barfs on those differential signals if left
         -- unconnected. So instanciate a diff. buffer and feed
diff --git a/microwatt.core b/microwatt.core
index ed2aa01..a1e9e5d 100644
--- a/microwatt.core
+++ b/microwatt.core
@@ -197,6 +197,7 @@ targets:
     default_tool: vivado
     filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
     parameters :
+      - cpus
       - memory_size
       - ram_init_file
       - use_litedram=true
@@ -205,6 +206,8 @@ targets:
       - spi_flash_offset=10485760
       - log_length=2048
       - uart_is_16550
+      - has_fpu
+      - has_btc
     generate: [litedram_acorn_cle_215, git_hash]
     tools:
       vivado: {part : xc7a200tsbg484-2}