From 102fbcfe9a3d8e054fdb0ad050512944051e4844 Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Mon, 4 May 2020 15:17:04 +1000 Subject: [PATCH] execute1: Fix interrupt delivery during slow instructions During slow instructions such as multiply or divide, if a decrementer (or other asynchronous) interrupt becomes pending, it disrupts the logic that keeps stall asserted until the end of the slow instruction, and the interrupt logic starts trying to deliver the interrupt before the slow instruction has finished. To fix that, make the interrupt logic wait until it sees e_in.valid set before setting exception to 1. Signed-off-by: Paul Mackerras --- execute1.vhdl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/execute1.vhdl b/execute1.vhdl index 1846488..8286d30 100644 --- a/execute1.vhdl +++ b/execute1.vhdl @@ -454,12 +454,12 @@ begin v.e.valid := e_in.valid; report "Writing SRR1: " & to_hstring(ctrl.srr1); - elsif irq_valid = '1' then + elsif irq_valid = '1' and e_in.valid = '1' then -- we need two cycles to write srr0 and 1 -- will need more when we have to write DSISR, DAR and HIER -- Don't deliver the interrupt until we have a valid instruction -- coming in, so we have a valid NIA to put in SRR0. - exception := e_in.valid; + exception := '1'; ctrl_tmp.srr1 <= msr_copy(ctrl.msr); elsif e_in.valid = '1' and ctrl.msr(MSR_PR) = '1' and