diff --git a/litedram/gen-src/sdram_init/Makefile b/litedram/gen-src/sdram_init/Makefile
index 6f50dae..1744f3b 100644
--- a/litedram/gen-src/sdram_init/Makefile
+++ b/litedram/gen-src/sdram_init/Makefile
@@ -5,7 +5,8 @@ OBJ = $(BUILD_DIR)/obj
 LXINC_DIR=$(LXSRC_DIR)/include
 
 PROGRAM = sdram_init
-OBJECTS = $(OBJ)/head.o $(OBJ)/main.o $(OBJ)/sdram.o $(OBJ)/memtest.o $(OBJ)/console.o
+OBJECTS = $(OBJ)/head.o $(OBJ)/main.o $(OBJ)/sdram.o $(OBJ)/accessors.o \
+          $(OBJ)/memtest.o $(OBJ)/console.o
 
 #### Compiler
 
@@ -58,6 +59,8 @@ all: objdir $(OBJ)/$(PROGRAM).hex
 
 $(OBJ)/sdram.o: $(LXSRC_DIR)/liblitedram/sdram.c
 	$(call Q,CC, $(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@, $@)
+$(OBJ)/accessors.o: $(LXSRC_DIR)/liblitedram/accessors.c
+	$(call Q,CC, $(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@, $@)
 $(OBJ)/memtest.o: $(LXSRC_DIR)/libbase/memtest.c
 	$(call Q,CC, $(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@, $@)
 $(OBJ)/console.o: $(SRC_DIR)/../../../lib/console.c
diff --git a/litedram/generated/acorn-cle-215/litedram_core.init b/litedram/generated/acorn-cle-215/litedram_core.init
index 61e54f3..0573632 100644
--- a/litedram/generated/acorn-cle-215/litedram_core.init
+++ b/litedram/generated/acorn-cle-215/litedram_core.init
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@@ -1944,6 +1928,8 @@ ebe1fff8e8010010
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 0000000000004269
diff --git a/litedram/generated/acorn-cle-215/litedram_core.v b/litedram/generated/acorn-cle-215/litedram_core.v
index 22c0e22..6125302 100644
--- a/litedram/generated/acorn-cle-215/litedram_core.v
+++ b/litedram/generated/acorn-cle-215/litedram_core.v
@@ -8,10 +8,11 @@
 //
 // Filename   : litedram_core.v
 // Device     : 
-// LiteX sha1 : --------
-// Date       : 2022-10-28 19:01:23
+// LiteX sha1 : 87137c30
+// Date       : 2024-04-01 10:12:09
 //------------------------------------------------------------------------------
 
+`timescale 1ns / 1ps
 
 //------------------------------------------------------------------------------
 // Module
@@ -19,4868 +20,5328 @@
 
 module litedram_core (
     input  wire          clk,
-    input  wire          rst,
-    output wire          pll_locked,
     output wire   [15:0] ddram_a,
     output wire    [2:0] ddram_ba,
-    output wire          ddram_ras_n,
     output wire          ddram_cas_n,
-    output wire          ddram_we_n,
+    output wire          ddram_cke,
+    output wire          ddram_clk_n,
+    output wire          ddram_clk_p,
     output wire          ddram_cs_n,
     output wire    [1:0] ddram_dm,
     inout  wire   [15:0] ddram_dq,
-    inout  wire    [1:0] ddram_dqs_p,
     inout  wire    [1:0] ddram_dqs_n,
-    output wire          ddram_clk_p,
-    output wire          ddram_clk_n,
-    output wire          ddram_cke,
+    inout  wire    [1:0] ddram_dqs_p,
     output wire          ddram_odt,
+    output wire          ddram_ras_n,
     output wire          ddram_reset_n,
+    output wire          ddram_we_n,
     output wire          init_done,
     output wire          init_error,
-    input  wire   [29:0] wb_ctrl_adr,
-    input  wire   [31:0] wb_ctrl_dat_w,
-    output wire   [31:0] wb_ctrl_dat_r,
-    input  wire    [3:0] wb_ctrl_sel,
-    input  wire          wb_ctrl_cyc,
-    input  wire          wb_ctrl_stb,
-    output wire          wb_ctrl_ack,
-    input  wire          wb_ctrl_we,
-    input  wire    [2:0] wb_ctrl_cti,
-    input  wire    [1:0] wb_ctrl_bte,
-    output wire          wb_ctrl_err,
+    output wire          pll_locked,
+    input  wire          rst,
     output wire          user_clk,
-    output wire          user_rst,
-    input  wire          user_port_native_0_cmd_valid,
+    input  wire   [25:0] user_port_native_0_cmd_addr,
     output wire          user_port_native_0_cmd_ready,
+    input  wire          user_port_native_0_cmd_valid,
     input  wire          user_port_native_0_cmd_we,
-    input  wire   [25:0] user_port_native_0_cmd_addr,
-    input  wire          user_port_native_0_wdata_valid,
+    output wire  [127:0] user_port_native_0_rdata_data,
+    input  wire          user_port_native_0_rdata_ready,
+    output wire          user_port_native_0_rdata_valid,
+    input  wire  [127:0] user_port_native_0_wdata_data,
     output wire          user_port_native_0_wdata_ready,
+    input  wire          user_port_native_0_wdata_valid,
     input  wire   [15:0] user_port_native_0_wdata_we,
-    input  wire  [127:0] user_port_native_0_wdata_data,
-    output wire          user_port_native_0_rdata_valid,
-    input  wire          user_port_native_0_rdata_ready,
-    output wire  [127:0] user_port_native_0_rdata_data
+    output wire          user_rst,
+    output wire          wb_ctrl_ack,
+    input  wire   [29:0] wb_ctrl_adr,
+    input  wire    [1:0] wb_ctrl_bte,
+    input  wire    [2:0] wb_ctrl_cti,
+    input  wire          wb_ctrl_cyc,
+    output wire   [31:0] wb_ctrl_dat_r,
+    input  wire   [31:0] wb_ctrl_dat_w,
+    output wire          wb_ctrl_err,
+    input  wire    [3:0] wb_ctrl_sel,
+    input  wire          wb_ctrl_stb,
+    input  wire          wb_ctrl_we
 );
 
 
+//------------------------------------------------------------------------------
+// Hierarchy
+//------------------------------------------------------------------------------
+
+/*
+LiteDRAMCore
+└─── bus (SoCBusHandler)
+│    └─── _interconnect (InterconnectPointToPoint)
+└─── csr (SoCCSRHandler)
+└─── irq (SoCIRQHandler)
+└─── cpu (CPUNone)
+└─── crg (LiteDRAMS7DDRPHYCRG)
+│    └─── pll (S7PLL)
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [BUFG]
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [BUFG]
+│    │    └─── [BUFG]
+│    │    └─── [BUFG]
+│    │    └─── [PLLE2_ADV]
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    └─── idelayctrl (S7IDELAYCTRL)
+│    │    └─── [IDELAYCTRL]
+└─── ddrphy (A7DDRPHY)
+│    └─── tappeddelayline_0* (TappedDelayLine)
+│    └─── dqspattern_0* (DQSPattern)
+│    └─── bitslip_0* (BitSlip)
+│    └─── bitslip_1* (BitSlip)
+│    └─── bitslip_2* (BitSlip)
+│    └─── bitslip_3* (BitSlip)
+│    └─── tappeddelayline_1* (TappedDelayLine)
+│    └─── bitslip_4* (BitSlip)
+│    └─── bitslip_5* (BitSlip)
+│    └─── bitslip_6* (BitSlip)
+│    └─── bitslip_7* (BitSlip)
+│    └─── bitslip_8* (BitSlip)
+│    └─── bitslip_9* (BitSlip)
+│    └─── bitslip_10* (BitSlip)
+│    └─── bitslip_11* (BitSlip)
+│    └─── bitslip_12* (BitSlip)
+│    └─── bitslip_13* (BitSlip)
+│    └─── bitslip_14* (BitSlip)
+│    └─── bitslip_15* (BitSlip)
+│    └─── bitslip_16* (BitSlip)
+│    └─── bitslip_17* (BitSlip)
+│    └─── bitslip_18* (BitSlip)
+│    └─── bitslip_19* (BitSlip)
+│    └─── bitslip_20* (BitSlip)
+│    └─── bitslip_21* (BitSlip)
+│    └─── bitslip_22* (BitSlip)
+│    └─── bitslip_23* (BitSlip)
+│    └─── bitslip_24* (BitSlip)
+│    └─── bitslip_25* (BitSlip)
+│    └─── bitslip_26* (BitSlip)
+│    └─── bitslip_27* (BitSlip)
+│    └─── bitslip_28* (BitSlip)
+│    └─── bitslip_29* (BitSlip)
+│    └─── bitslip_30* (BitSlip)
+│    └─── bitslip_31* (BitSlip)
+│    └─── bitslip_32* (BitSlip)
+│    └─── bitslip_33* (BitSlip)
+│    └─── bitslip_34* (BitSlip)
+│    └─── bitslip_35* (BitSlip)
+│    └─── tappeddelayline_2* (TappedDelayLine)
+│    └─── tappeddelayline_3* (TappedDelayLine)
+│    └─── [IDELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OBUFDS]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [ISERDESE2]
+│    └─── [IOBUFDS]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [IOBUFDS]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+└─── sdram (LiteDRAMCore)
+│    └─── dfii (DFIInjector)
+│    │    └─── pi0 (PhaseInjector)
+│    │    └─── pi1 (PhaseInjector)
+│    │    └─── pi2 (PhaseInjector)
+│    │    └─── pi3 (PhaseInjector)
+│    └─── controller (LiteDRAMController)
+│    │    └─── refresher (Refresher)
+│    │    │    └─── timer (RefreshTimer)
+│    │    │    └─── postponer (RefreshPostponer)
+│    │    │    └─── sequencer (RefreshSequencer)
+│    │    │    │    └─── refreshexecuter_0* (RefreshExecuter)
+│    │    │    └─── zqcs_timer (RefreshTimer)
+│    │    │    └─── zqs_executer (ZQCSExecuter)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_0* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_1* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_2* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_3* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_4* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_5* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_6* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_7* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── multiplexer (Multiplexer)
+│    │    │    └─── choose_cmd (_CommandChooser)
+│    │    │    │    └─── roundrobin_0* (RoundRobin)
+│    │    │    └─── choose_req (_CommandChooser)
+│    │    │    │    └─── roundrobin_0* (RoundRobin)
+│    │    │    └─── _steerer_0* (_Steerer)
+│    │    │    └─── trrdcon (tXXDController)
+│    │    │    └─── tfawcon (tFAWController)
+│    │    │    └─── tccdcon (tXXDController)
+│    │    │    └─── twtrcon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    └─── crossbar (LiteDRAMCrossbar)
+│    │    └─── roundrobin_0* (RoundRobin)
+│    │    └─── roundrobin_1* (RoundRobin)
+│    │    └─── roundrobin_2* (RoundRobin)
+│    │    └─── roundrobin_3* (RoundRobin)
+│    │    └─── roundrobin_4* (RoundRobin)
+│    │    └─── roundrobin_5* (RoundRobin)
+│    │    └─── roundrobin_6* (RoundRobin)
+│    │    └─── roundrobin_7* (RoundRobin)
+└─── ddrctrl (LiteDRAMCoreControl)
+└─── csr_bridge (Wishbone2CSR)
+│    └─── fsm (FSM)
+└─── csr_bankarray (CSRBankArray)
+│    └─── csrbank_0* (CSRBank)
+│    │    └─── csrstorage_0* (CSRStorage)
+│    │    └─── csrstorage_1* (CSRStorage)
+│    └─── csrbank_1* (CSRBank)
+│    │    └─── csrstorage_0* (CSRStorage)
+│    │    └─── csrstorage_1* (CSRStorage)
+│    │    └─── csrstorage_2* (CSRStorage)
+│    │    └─── csrstorage_3* (CSRStorage)
+│    │    └─── csrstorage_4* (CSRStorage)
+│    │    └─── csrstorage_5* (CSRStorage)
+│    └─── csrbank_2* (CSRBank)
+│    │    └─── csrstorage_0* (CSRStorage)
+│    │    └─── csrstorage_1* (CSRStorage)
+│    │    └─── csrstorage_2* (CSRStorage)
+│    │    └─── csrstorage_3* (CSRStorage)
+│    │    └─── csrstorage_4* (CSRStorage)
+│    │    └─── csrstatus_0* (CSRStatus)
+│    │    └─── csrstorage_5* (CSRStorage)
+│    │    └─── csrstorage_6* (CSRStorage)
+│    │    └─── csrstorage_7* (CSRStorage)
+│    │    └─── csrstorage_8* (CSRStorage)
+│    │    └─── csrstatus_1* (CSRStatus)
+│    │    └─── csrstorage_9* (CSRStorage)
+│    │    └─── csrstorage_10* (CSRStorage)
+│    │    └─── csrstorage_11* (CSRStorage)
+│    │    └─── csrstorage_12* (CSRStorage)
+│    │    └─── csrstatus_2* (CSRStatus)
+│    │    └─── csrstorage_13* (CSRStorage)
+│    │    └─── csrstorage_14* (CSRStorage)
+│    │    └─── csrstorage_15* (CSRStorage)
+│    │    └─── csrstorage_16* (CSRStorage)
+│    │    └─── csrstatus_3* (CSRStatus)
+└─── csr_interconnect (InterconnectShared)
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+* : Generated name.
+[]: BlackBox.
+*/
+
 //------------------------------------------------------------------------------
 // Signals
 //------------------------------------------------------------------------------
 
-reg           rst_1 = 1'd0;
-wire          sys_clk;
-wire          sys_rst;
-wire          sys4x_clk;
-wire          sys4x_dqs_clk;
+wire   [13:0] builder_adr;
+reg     [3:0] builder_bankmachine0_next_state = 4'd0;
+reg     [3:0] builder_bankmachine0_state = 4'd0;
+reg     [3:0] builder_bankmachine1_next_state = 4'd0;
+reg     [3:0] builder_bankmachine1_state = 4'd0;
+reg     [3:0] builder_bankmachine2_next_state = 4'd0;
+reg     [3:0] builder_bankmachine2_state = 4'd0;
+reg     [3:0] builder_bankmachine3_next_state = 4'd0;
+reg     [3:0] builder_bankmachine3_state = 4'd0;
+reg     [3:0] builder_bankmachine4_next_state = 4'd0;
+reg     [3:0] builder_bankmachine4_state = 4'd0;
+reg     [3:0] builder_bankmachine5_next_state = 4'd0;
+reg     [3:0] builder_bankmachine5_state = 4'd0;
+reg     [3:0] builder_bankmachine6_next_state = 4'd0;
+reg     [3:0] builder_bankmachine6_state = 4'd0;
+reg     [3:0] builder_bankmachine7_next_state = 4'd0;
+reg     [3:0] builder_bankmachine7_state = 4'd0;
+wire          builder_csrbank0_init_done0_r;
+reg           builder_csrbank0_init_done0_re = 1'd0;
+wire          builder_csrbank0_init_done0_w;
+reg           builder_csrbank0_init_done0_we = 1'd0;
+wire          builder_csrbank0_init_error0_r;
+reg           builder_csrbank0_init_error0_re = 1'd0;
+wire          builder_csrbank0_init_error0_w;
+reg           builder_csrbank0_init_error0_we = 1'd0;
+wire          builder_csrbank0_sel;
+wire    [1:0] builder_csrbank1_dly_sel0_r;
+reg           builder_csrbank1_dly_sel0_re = 1'd0;
+wire    [1:0] builder_csrbank1_dly_sel0_w;
+reg           builder_csrbank1_dly_sel0_we = 1'd0;
+wire    [4:0] builder_csrbank1_half_sys8x_taps0_r;
+reg           builder_csrbank1_half_sys8x_taps0_re = 1'd0;
+wire    [4:0] builder_csrbank1_half_sys8x_taps0_w;
+reg           builder_csrbank1_half_sys8x_taps0_we = 1'd0;
+wire    [1:0] builder_csrbank1_rdphase0_r;
+reg           builder_csrbank1_rdphase0_re = 1'd0;
+wire    [1:0] builder_csrbank1_rdphase0_w;
+reg           builder_csrbank1_rdphase0_we = 1'd0;
+wire          builder_csrbank1_rst0_r;
+reg           builder_csrbank1_rst0_re = 1'd0;
+wire          builder_csrbank1_rst0_w;
+reg           builder_csrbank1_rst0_we = 1'd0;
+wire          builder_csrbank1_sel;
+wire          builder_csrbank1_wlevel_en0_r;
+reg           builder_csrbank1_wlevel_en0_re = 1'd0;
+wire          builder_csrbank1_wlevel_en0_w;
+reg           builder_csrbank1_wlevel_en0_we = 1'd0;
+wire    [1:0] builder_csrbank1_wrphase0_r;
+reg           builder_csrbank1_wrphase0_re = 1'd0;
+wire    [1:0] builder_csrbank1_wrphase0_w;
+reg           builder_csrbank1_wrphase0_we = 1'd0;
+wire    [3:0] builder_csrbank2_dfii_control0_r;
+reg           builder_csrbank2_dfii_control0_re = 1'd0;
+wire    [3:0] builder_csrbank2_dfii_control0_w;
+reg           builder_csrbank2_dfii_control0_we = 1'd0;
+wire   [15:0] builder_csrbank2_dfii_pi0_address0_r;
+reg           builder_csrbank2_dfii_pi0_address0_re = 1'd0;
+wire   [15:0] builder_csrbank2_dfii_pi0_address0_w;
+reg           builder_csrbank2_dfii_pi0_address0_we = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi0_baddress0_r;
+reg           builder_csrbank2_dfii_pi0_baddress0_re = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi0_baddress0_w;
+reg           builder_csrbank2_dfii_pi0_baddress0_we = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi0_command0_r;
+reg           builder_csrbank2_dfii_pi0_command0_re = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi0_command0_w;
+reg           builder_csrbank2_dfii_pi0_command0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi0_rddata_r;
+reg           builder_csrbank2_dfii_pi0_rddata_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi0_rddata_w;
+reg           builder_csrbank2_dfii_pi0_rddata_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi0_wrdata0_r;
+reg           builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi0_wrdata0_w;
+reg           builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0;
+wire   [15:0] builder_csrbank2_dfii_pi1_address0_r;
+reg           builder_csrbank2_dfii_pi1_address0_re = 1'd0;
+wire   [15:0] builder_csrbank2_dfii_pi1_address0_w;
+reg           builder_csrbank2_dfii_pi1_address0_we = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi1_baddress0_r;
+reg           builder_csrbank2_dfii_pi1_baddress0_re = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi1_baddress0_w;
+reg           builder_csrbank2_dfii_pi1_baddress0_we = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi1_command0_r;
+reg           builder_csrbank2_dfii_pi1_command0_re = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi1_command0_w;
+reg           builder_csrbank2_dfii_pi1_command0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi1_rddata_r;
+reg           builder_csrbank2_dfii_pi1_rddata_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi1_rddata_w;
+reg           builder_csrbank2_dfii_pi1_rddata_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi1_wrdata0_r;
+reg           builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi1_wrdata0_w;
+reg           builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0;
+wire   [15:0] builder_csrbank2_dfii_pi2_address0_r;
+reg           builder_csrbank2_dfii_pi2_address0_re = 1'd0;
+wire   [15:0] builder_csrbank2_dfii_pi2_address0_w;
+reg           builder_csrbank2_dfii_pi2_address0_we = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi2_baddress0_r;
+reg           builder_csrbank2_dfii_pi2_baddress0_re = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi2_baddress0_w;
+reg           builder_csrbank2_dfii_pi2_baddress0_we = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi2_command0_r;
+reg           builder_csrbank2_dfii_pi2_command0_re = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi2_command0_w;
+reg           builder_csrbank2_dfii_pi2_command0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi2_rddata_r;
+reg           builder_csrbank2_dfii_pi2_rddata_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi2_rddata_w;
+reg           builder_csrbank2_dfii_pi2_rddata_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi2_wrdata0_r;
+reg           builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi2_wrdata0_w;
+reg           builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0;
+wire   [15:0] builder_csrbank2_dfii_pi3_address0_r;
+reg           builder_csrbank2_dfii_pi3_address0_re = 1'd0;
+wire   [15:0] builder_csrbank2_dfii_pi3_address0_w;
+reg           builder_csrbank2_dfii_pi3_address0_we = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi3_baddress0_r;
+reg           builder_csrbank2_dfii_pi3_baddress0_re = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi3_baddress0_w;
+reg           builder_csrbank2_dfii_pi3_baddress0_we = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi3_command0_r;
+reg           builder_csrbank2_dfii_pi3_command0_re = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi3_command0_w;
+reg           builder_csrbank2_dfii_pi3_command0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi3_rddata_r;
+reg           builder_csrbank2_dfii_pi3_rddata_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi3_rddata_w;
+reg           builder_csrbank2_dfii_pi3_rddata_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi3_wrdata0_r;
+reg           builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi3_wrdata0_w;
+reg           builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0;
+wire          builder_csrbank2_sel;
+wire   [31:0] builder_dat_r;
+wire   [31:0] builder_dat_w;
+reg           builder_interface0_ack = 1'd0;
+wire   [29:0] builder_interface0_adr;
+wire   [13:0] builder_interface0_bank_bus_adr;
+reg    [31:0] builder_interface0_bank_bus_dat_r = 32'd0;
+wire   [31:0] builder_interface0_bank_bus_dat_w;
+wire          builder_interface0_bank_bus_we;
+wire    [1:0] builder_interface0_bte;
+wire    [2:0] builder_interface0_cti;
+wire          builder_interface0_cyc;
+reg    [31:0] builder_interface0_dat_r = 32'd0;
+wire   [31:0] builder_interface0_dat_w;
+reg           builder_interface0_err = 1'd0;
+wire    [3:0] builder_interface0_sel;
+wire          builder_interface0_stb;
+wire          builder_interface0_we;
+reg    [13:0] builder_interface1_adr = 14'd0;
+reg    [13:0] builder_interface1_adr_next_value1 = 14'd0;
+reg           builder_interface1_adr_next_value_ce1 = 1'd0;
+wire   [13:0] builder_interface1_bank_bus_adr;
+reg    [31:0] builder_interface1_bank_bus_dat_r = 32'd0;
+wire   [31:0] builder_interface1_bank_bus_dat_w;
+wire          builder_interface1_bank_bus_we;
+wire   [31:0] builder_interface1_dat_r;
+reg    [31:0] builder_interface1_dat_w = 32'd0;
+reg    [31:0] builder_interface1_dat_w_next_value0 = 32'd0;
+reg           builder_interface1_dat_w_next_value_ce0 = 1'd0;
+reg           builder_interface1_we = 1'd0;
+reg           builder_interface1_we_next_value2 = 1'd0;
+reg           builder_interface1_we_next_value_ce2 = 1'd0;
+wire   [13:0] builder_interface2_bank_bus_adr;
+reg    [31:0] builder_interface2_bank_bus_dat_r = 32'd0;
+wire   [31:0] builder_interface2_bank_bus_dat_w;
+wire          builder_interface2_bank_bus_we;
+reg           builder_locked0 = 1'd0;
+reg           builder_locked1 = 1'd0;
+reg           builder_locked2 = 1'd0;
+reg           builder_locked3 = 1'd0;
+reg           builder_locked4 = 1'd0;
+reg           builder_locked5 = 1'd0;
+reg           builder_locked6 = 1'd0;
+reg           builder_locked7 = 1'd0;
+reg     [3:0] builder_multiplexer_next_state = 4'd0;
+reg     [3:0] builder_multiplexer_state = 4'd0;
+reg           builder_new_master_rdata_valid0 = 1'd0;
+reg           builder_new_master_rdata_valid1 = 1'd0;
+reg           builder_new_master_rdata_valid2 = 1'd0;
+reg           builder_new_master_rdata_valid3 = 1'd0;
+reg           builder_new_master_rdata_valid4 = 1'd0;
+reg           builder_new_master_rdata_valid5 = 1'd0;
+reg           builder_new_master_rdata_valid6 = 1'd0;
+reg           builder_new_master_rdata_valid7 = 1'd0;
+reg           builder_new_master_rdata_valid8 = 1'd0;
+reg           builder_new_master_wdata_ready0 = 1'd0;
+reg           builder_new_master_wdata_ready1 = 1'd0;
+reg     [1:0] builder_next_state = 2'd0;
+wire          builder_pll_fb;
+reg     [1:0] builder_refresher_next_state = 2'd0;
+reg     [1:0] builder_refresher_state = 2'd0;
+wire          builder_reset0;
+wire          builder_reset1;
+wire          builder_reset2;
+wire          builder_reset3;
+wire          builder_reset4;
+wire          builder_reset5;
+wire          builder_reset6;
+wire          builder_reset7;
+reg           builder_rhs_self0 = 1'd0;
+reg    [15:0] builder_rhs_self1 = 16'd0;
+reg           builder_rhs_self10 = 1'd0;
+reg           builder_rhs_self11 = 1'd0;
+reg    [22:0] builder_rhs_self12 = 23'd0;
+reg           builder_rhs_self13 = 1'd0;
+reg           builder_rhs_self14 = 1'd0;
+reg    [22:0] builder_rhs_self15 = 23'd0;
+reg           builder_rhs_self16 = 1'd0;
+reg           builder_rhs_self17 = 1'd0;
+reg    [22:0] builder_rhs_self18 = 23'd0;
+reg           builder_rhs_self19 = 1'd0;
+reg     [2:0] builder_rhs_self2 = 3'd0;
+reg           builder_rhs_self20 = 1'd0;
+reg    [22:0] builder_rhs_self21 = 23'd0;
+reg           builder_rhs_self22 = 1'd0;
+reg           builder_rhs_self23 = 1'd0;
+reg    [22:0] builder_rhs_self24 = 23'd0;
+reg           builder_rhs_self25 = 1'd0;
+reg           builder_rhs_self26 = 1'd0;
+reg    [22:0] builder_rhs_self27 = 23'd0;
+reg           builder_rhs_self28 = 1'd0;
+reg           builder_rhs_self29 = 1'd0;
+reg           builder_rhs_self3 = 1'd0;
+reg    [22:0] builder_rhs_self30 = 23'd0;
+reg           builder_rhs_self31 = 1'd0;
+reg           builder_rhs_self32 = 1'd0;
+reg    [22:0] builder_rhs_self33 = 23'd0;
+reg           builder_rhs_self34 = 1'd0;
+reg           builder_rhs_self35 = 1'd0;
+reg           builder_rhs_self4 = 1'd0;
+reg           builder_rhs_self5 = 1'd0;
+reg           builder_rhs_self6 = 1'd0;
+reg    [15:0] builder_rhs_self7 = 16'd0;
+reg     [2:0] builder_rhs_self8 = 3'd0;
+reg           builder_rhs_self9 = 1'd0;
+wire          builder_roundrobin0_ce;
+wire          builder_roundrobin0_grant;
+wire          builder_roundrobin0_request;
+wire          builder_roundrobin1_ce;
+wire          builder_roundrobin1_grant;
+wire          builder_roundrobin1_request;
+wire          builder_roundrobin2_ce;
+wire          builder_roundrobin2_grant;
+wire          builder_roundrobin2_request;
+wire          builder_roundrobin3_ce;
+wire          builder_roundrobin3_grant;
+wire          builder_roundrobin3_request;
+wire          builder_roundrobin4_ce;
+wire          builder_roundrobin4_grant;
+wire          builder_roundrobin4_request;
+wire          builder_roundrobin5_ce;
+wire          builder_roundrobin5_grant;
+wire          builder_roundrobin5_request;
+wire          builder_roundrobin6_ce;
+wire          builder_roundrobin6_grant;
+wire          builder_roundrobin6_request;
+wire          builder_roundrobin7_ce;
+wire          builder_roundrobin7_grant;
+wire          builder_roundrobin7_request;
+reg     [2:0] builder_self0 = 3'd0;
+reg    [15:0] builder_self1 = 16'd0;
+reg           builder_self10 = 1'd0;
+reg           builder_self11 = 1'd0;
+reg           builder_self12 = 1'd0;
+reg           builder_self13 = 1'd0;
+reg     [2:0] builder_self14 = 3'd0;
+reg    [15:0] builder_self15 = 16'd0;
+reg           builder_self16 = 1'd0;
+reg           builder_self17 = 1'd0;
+reg           builder_self18 = 1'd0;
+reg           builder_self19 = 1'd0;
+reg           builder_self2 = 1'd0;
+reg           builder_self20 = 1'd0;
+reg     [2:0] builder_self21 = 3'd0;
+reg    [15:0] builder_self22 = 16'd0;
+reg           builder_self23 = 1'd0;
+reg           builder_self24 = 1'd0;
+reg           builder_self25 = 1'd0;
+reg           builder_self26 = 1'd0;
+reg           builder_self27 = 1'd0;
+reg           builder_self3 = 1'd0;
+reg           builder_self4 = 1'd0;
+reg           builder_self5 = 1'd0;
+reg           builder_self6 = 1'd0;
+reg     [2:0] builder_self7 = 3'd0;
+reg    [15:0] builder_self8 = 16'd0;
+reg           builder_self9 = 1'd0;
+reg     [1:0] builder_state = 2'd0;
+reg           builder_t_self0 = 1'd0;
+reg           builder_t_self1 = 1'd0;
+reg           builder_t_self2 = 1'd0;
+reg           builder_t_self3 = 1'd0;
+reg           builder_t_self4 = 1'd0;
+reg           builder_t_self5 = 1'd0;
+wire          builder_we;
+wire          builder_xilinxasyncresetsynchronizerimpl0_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl0_rst_meta;
+wire          builder_xilinxasyncresetsynchronizerimpl1_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl1_rst_meta;
+wire          builder_xilinxasyncresetsynchronizerimpl2_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl2_expr;
+wire          builder_xilinxasyncresetsynchronizerimpl2_rst_meta;
+wire          builder_xilinxasyncresetsynchronizerimpl3_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl3_expr;
+wire          builder_xilinxasyncresetsynchronizerimpl3_rst_meta;
 wire          iodelay_clk;
 wire          iodelay_rst;
-wire          reset;
-reg           power_down = 1'd0;
-wire          locked;
-wire          clkin;
-wire          clkout0;
-wire          clkout_buf0;
-wire          clkout1;
-wire          clkout_buf1;
-wire          clkout2;
-wire          clkout_buf2;
-wire          clkout3;
-wire          clkout_buf3;
-reg     [3:0] reset_counter = 4'd15;
-reg           ic_reset = 1'd1;
-reg           a7ddrphy_rst_storage = 1'd0;
-reg           a7ddrphy_rst_re = 1'd0;
-reg     [1:0] a7ddrphy_dly_sel_storage = 2'd0;
-reg           a7ddrphy_dly_sel_re = 1'd0;
-reg     [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8;
-reg           a7ddrphy_half_sys8x_taps_re = 1'd0;
-reg           a7ddrphy_wlevel_en_storage = 1'd0;
-reg           a7ddrphy_wlevel_en_re = 1'd0;
-reg           a7ddrphy_wlevel_strobe_re = 1'd0;
-wire          a7ddrphy_wlevel_strobe_r;
-reg           a7ddrphy_wlevel_strobe_we = 1'd0;
-reg           a7ddrphy_wlevel_strobe_w = 1'd0;
-reg           a7ddrphy_rdly_dq_rst_re = 1'd0;
-wire          a7ddrphy_rdly_dq_rst_r;
-reg           a7ddrphy_rdly_dq_rst_we = 1'd0;
-reg           a7ddrphy_rdly_dq_rst_w = 1'd0;
-reg           a7ddrphy_rdly_dq_inc_re = 1'd0;
-wire          a7ddrphy_rdly_dq_inc_r;
-reg           a7ddrphy_rdly_dq_inc_we = 1'd0;
-reg           a7ddrphy_rdly_dq_inc_w = 1'd0;
-reg           a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
-wire          a7ddrphy_rdly_dq_bitslip_rst_r;
-reg           a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
-reg           a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-reg           a7ddrphy_rdly_dq_bitslip_re = 1'd0;
-wire          a7ddrphy_rdly_dq_bitslip_r;
-reg           a7ddrphy_rdly_dq_bitslip_we = 1'd0;
-reg           a7ddrphy_rdly_dq_bitslip_w = 1'd0;
-reg           a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
-wire          a7ddrphy_wdly_dq_bitslip_rst_r;
-reg           a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
-reg           a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
-reg           a7ddrphy_wdly_dq_bitslip_re = 1'd0;
-wire          a7ddrphy_wdly_dq_bitslip_r;
-reg           a7ddrphy_wdly_dq_bitslip_we = 1'd0;
-reg           a7ddrphy_wdly_dq_bitslip_w = 1'd0;
-reg     [1:0] a7ddrphy_rdphase_storage = 2'd2;
-reg           a7ddrphy_rdphase_re = 1'd0;
-reg     [1:0] a7ddrphy_wrphase_storage = 2'd3;
-reg           a7ddrphy_wrphase_re = 1'd0;
-wire   [15:0] a7ddrphy_dfi_p0_address;
-wire    [2:0] a7ddrphy_dfi_p0_bank;
-wire          a7ddrphy_dfi_p0_cas_n;
-wire          a7ddrphy_dfi_p0_cs_n;
-wire          a7ddrphy_dfi_p0_ras_n;
-wire          a7ddrphy_dfi_p0_we_n;
-wire          a7ddrphy_dfi_p0_cke;
-wire          a7ddrphy_dfi_p0_odt;
-wire          a7ddrphy_dfi_p0_reset_n;
-wire          a7ddrphy_dfi_p0_act_n;
-wire   [31:0] a7ddrphy_dfi_p0_wrdata;
-wire          a7ddrphy_dfi_p0_wrdata_en;
-wire    [3:0] a7ddrphy_dfi_p0_wrdata_mask;
-wire          a7ddrphy_dfi_p0_rddata_en;
-reg    [31:0] a7ddrphy_dfi_p0_rddata = 32'd0;
-wire          a7ddrphy_dfi_p0_rddata_valid;
-wire   [15:0] a7ddrphy_dfi_p1_address;
-wire    [2:0] a7ddrphy_dfi_p1_bank;
-wire          a7ddrphy_dfi_p1_cas_n;
-wire          a7ddrphy_dfi_p1_cs_n;
-wire          a7ddrphy_dfi_p1_ras_n;
-wire          a7ddrphy_dfi_p1_we_n;
-wire          a7ddrphy_dfi_p1_cke;
-wire          a7ddrphy_dfi_p1_odt;
-wire          a7ddrphy_dfi_p1_reset_n;
-wire          a7ddrphy_dfi_p1_act_n;
-wire   [31:0] a7ddrphy_dfi_p1_wrdata;
-wire          a7ddrphy_dfi_p1_wrdata_en;
-wire    [3:0] a7ddrphy_dfi_p1_wrdata_mask;
-wire          a7ddrphy_dfi_p1_rddata_en;
-reg    [31:0] a7ddrphy_dfi_p1_rddata = 32'd0;
-wire          a7ddrphy_dfi_p1_rddata_valid;
-wire   [15:0] a7ddrphy_dfi_p2_address;
-wire    [2:0] a7ddrphy_dfi_p2_bank;
-wire          a7ddrphy_dfi_p2_cas_n;
-wire          a7ddrphy_dfi_p2_cs_n;
-wire          a7ddrphy_dfi_p2_ras_n;
-wire          a7ddrphy_dfi_p2_we_n;
-wire          a7ddrphy_dfi_p2_cke;
-wire          a7ddrphy_dfi_p2_odt;
-wire          a7ddrphy_dfi_p2_reset_n;
-wire          a7ddrphy_dfi_p2_act_n;
-wire   [31:0] a7ddrphy_dfi_p2_wrdata;
-wire          a7ddrphy_dfi_p2_wrdata_en;
-wire    [3:0] a7ddrphy_dfi_p2_wrdata_mask;
-wire          a7ddrphy_dfi_p2_rddata_en;
-reg    [31:0] a7ddrphy_dfi_p2_rddata = 32'd0;
-wire          a7ddrphy_dfi_p2_rddata_valid;
-wire   [15:0] a7ddrphy_dfi_p3_address;
-wire    [2:0] a7ddrphy_dfi_p3_bank;
-wire          a7ddrphy_dfi_p3_cas_n;
-wire          a7ddrphy_dfi_p3_cs_n;
-wire          a7ddrphy_dfi_p3_ras_n;
-wire          a7ddrphy_dfi_p3_we_n;
-wire          a7ddrphy_dfi_p3_cke;
-wire          a7ddrphy_dfi_p3_odt;
-wire          a7ddrphy_dfi_p3_reset_n;
-wire          a7ddrphy_dfi_p3_act_n;
-wire   [31:0] a7ddrphy_dfi_p3_wrdata;
-wire          a7ddrphy_dfi_p3_wrdata_en;
-wire    [3:0] a7ddrphy_dfi_p3_wrdata_mask;
-wire          a7ddrphy_dfi_p3_rddata_en;
-reg    [31:0] a7ddrphy_dfi_p3_rddata = 32'd0;
-wire          a7ddrphy_dfi_p3_rddata_valid;
-wire          a7ddrphy_sd_clk_se_nodelay;
-wire    [2:0] a7ddrphy_pads_ba;
-reg           a7ddrphy_dqs_oe = 1'd0;
-wire          a7ddrphy_dqs_preamble;
-wire          a7ddrphy_dqs_postamble;
-wire          a7ddrphy_dqs_oe_delay_tappeddelayline;
-reg           a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg           a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-reg           a7ddrphy_dqspattern0 = 1'd0;
-reg           a7ddrphy_dqspattern1 = 1'd0;
-reg     [7:0] a7ddrphy_dqspattern_o0 = 8'd0;
-reg     [7:0] a7ddrphy_dqspattern_o1 = 8'd0;
-wire          a7ddrphy_dqs_o_no_delay0;
-wire          a7ddrphy_dqs_t0;
-reg     [7:0] a7ddrphy_bitslip00 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip0_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip0_r0 = 16'd0;
-wire          a7ddrphy0;
-wire          a7ddrphy_dqs_o_no_delay1;
-wire          a7ddrphy_dqs_t1;
-reg     [7:0] a7ddrphy_bitslip10 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip1_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip1_r0 = 16'd0;
-wire          a7ddrphy1;
-reg     [7:0] a7ddrphy_bitslip01 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip0_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip0_r1 = 16'd0;
-reg     [7:0] a7ddrphy_bitslip11 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip1_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip1_r1 = 16'd0;
-wire          a7ddrphy_dq_oe;
-wire          a7ddrphy_dq_oe_delay_tappeddelayline;
-reg           a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg           a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-wire          a7ddrphy_dq_o_nodelay0;
-wire          a7ddrphy_dq_i_nodelay0;
-wire          a7ddrphy_dq_i_delayed0;
-wire          a7ddrphy_dq_t0;
-reg     [7:0] a7ddrphy_bitslip02 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip0_value2 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip0_r2 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip03;
-reg     [7:0] a7ddrphy_bitslip04 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip0_value3 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip0_r3 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay1;
-wire          a7ddrphy_dq_i_nodelay1;
-wire          a7ddrphy_dq_i_delayed1;
-wire          a7ddrphy_dq_t1;
-reg     [7:0] a7ddrphy_bitslip12 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip1_value2 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip1_r2 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip13;
-reg     [7:0] a7ddrphy_bitslip14 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip1_value3 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip1_r3 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay2;
-wire          a7ddrphy_dq_i_nodelay2;
-wire          a7ddrphy_dq_i_delayed2;
-wire          a7ddrphy_dq_t2;
-reg     [7:0] a7ddrphy_bitslip20 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip2_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip2_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip21;
-reg     [7:0] a7ddrphy_bitslip22 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip2_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip2_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay3;
-wire          a7ddrphy_dq_i_nodelay3;
-wire          a7ddrphy_dq_i_delayed3;
-wire          a7ddrphy_dq_t3;
-reg     [7:0] a7ddrphy_bitslip30 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip3_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip3_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip31;
-reg     [7:0] a7ddrphy_bitslip32 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip3_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip3_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay4;
-wire          a7ddrphy_dq_i_nodelay4;
-wire          a7ddrphy_dq_i_delayed4;
-wire          a7ddrphy_dq_t4;
-reg     [7:0] a7ddrphy_bitslip40 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip4_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip4_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip41;
-reg     [7:0] a7ddrphy_bitslip42 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip4_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip4_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay5;
-wire          a7ddrphy_dq_i_nodelay5;
-wire          a7ddrphy_dq_i_delayed5;
-wire          a7ddrphy_dq_t5;
-reg     [7:0] a7ddrphy_bitslip50 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip5_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip5_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip51;
-reg     [7:0] a7ddrphy_bitslip52 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip5_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip5_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay6;
-wire          a7ddrphy_dq_i_nodelay6;
-wire          a7ddrphy_dq_i_delayed6;
-wire          a7ddrphy_dq_t6;
-reg     [7:0] a7ddrphy_bitslip60 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip6_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip6_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip61;
-reg     [7:0] a7ddrphy_bitslip62 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip6_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip6_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay7;
-wire          a7ddrphy_dq_i_nodelay7;
-wire          a7ddrphy_dq_i_delayed7;
-wire          a7ddrphy_dq_t7;
-reg     [7:0] a7ddrphy_bitslip70 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip7_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip7_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip71;
-reg     [7:0] a7ddrphy_bitslip72 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip7_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip7_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay8;
-wire          a7ddrphy_dq_i_nodelay8;
-wire          a7ddrphy_dq_i_delayed8;
-wire          a7ddrphy_dq_t8;
-reg     [7:0] a7ddrphy_bitslip80 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip8_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip8_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip81;
-reg     [7:0] a7ddrphy_bitslip82 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip8_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip8_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay9;
-wire          a7ddrphy_dq_i_nodelay9;
-wire          a7ddrphy_dq_i_delayed9;
-wire          a7ddrphy_dq_t9;
-reg     [7:0] a7ddrphy_bitslip90 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip9_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip9_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip91;
-reg     [7:0] a7ddrphy_bitslip92 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip9_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip9_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay10;
-wire          a7ddrphy_dq_i_nodelay10;
-wire          a7ddrphy_dq_i_delayed10;
-wire          a7ddrphy_dq_t10;
-reg     [7:0] a7ddrphy_bitslip100 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip10_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip10_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip101;
-reg     [7:0] a7ddrphy_bitslip102 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip10_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip10_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay11;
-wire          a7ddrphy_dq_i_nodelay11;
-wire          a7ddrphy_dq_i_delayed11;
-wire          a7ddrphy_dq_t11;
-reg     [7:0] a7ddrphy_bitslip110 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip11_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip11_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip111;
-reg     [7:0] a7ddrphy_bitslip112 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip11_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip11_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay12;
-wire          a7ddrphy_dq_i_nodelay12;
-wire          a7ddrphy_dq_i_delayed12;
-wire          a7ddrphy_dq_t12;
-reg     [7:0] a7ddrphy_bitslip120 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip12_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip12_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip121;
-reg     [7:0] a7ddrphy_bitslip122 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip12_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip12_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay13;
-wire          a7ddrphy_dq_i_nodelay13;
-wire          a7ddrphy_dq_i_delayed13;
-wire          a7ddrphy_dq_t13;
-reg     [7:0] a7ddrphy_bitslip130 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip13_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip13_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip131;
-reg     [7:0] a7ddrphy_bitslip132 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip13_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip13_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay14;
-wire          a7ddrphy_dq_i_nodelay14;
-wire          a7ddrphy_dq_i_delayed14;
-wire          a7ddrphy_dq_t14;
-reg     [7:0] a7ddrphy_bitslip140 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip14_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip14_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip141;
-reg     [7:0] a7ddrphy_bitslip142 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip14_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip14_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay15;
-wire          a7ddrphy_dq_i_nodelay15;
-wire          a7ddrphy_dq_i_delayed15;
-wire          a7ddrphy_dq_t15;
-reg     [7:0] a7ddrphy_bitslip150 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip15_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip15_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip151;
-reg     [7:0] a7ddrphy_bitslip152 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip15_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip15_r1 = 16'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
-reg           a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
-reg           a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
-reg           a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
-wire   [15:0] litedramcore_slave_p0_address;
-wire    [2:0] litedramcore_slave_p0_bank;
-wire          litedramcore_slave_p0_cas_n;
-wire          litedramcore_slave_p0_cs_n;
-wire          litedramcore_slave_p0_ras_n;
-wire          litedramcore_slave_p0_we_n;
-wire          litedramcore_slave_p0_cke;
-wire          litedramcore_slave_p0_odt;
-wire          litedramcore_slave_p0_reset_n;
-wire          litedramcore_slave_p0_act_n;
-wire   [31:0] litedramcore_slave_p0_wrdata;
-wire          litedramcore_slave_p0_wrdata_en;
-wire    [3:0] litedramcore_slave_p0_wrdata_mask;
-wire          litedramcore_slave_p0_rddata_en;
-reg    [31:0] litedramcore_slave_p0_rddata = 32'd0;
-reg           litedramcore_slave_p0_rddata_valid = 1'd0;
-wire   [15:0] litedramcore_slave_p1_address;
-wire    [2:0] litedramcore_slave_p1_bank;
-wire          litedramcore_slave_p1_cas_n;
-wire          litedramcore_slave_p1_cs_n;
-wire          litedramcore_slave_p1_ras_n;
-wire          litedramcore_slave_p1_we_n;
-wire          litedramcore_slave_p1_cke;
-wire          litedramcore_slave_p1_odt;
-wire          litedramcore_slave_p1_reset_n;
-wire          litedramcore_slave_p1_act_n;
-wire   [31:0] litedramcore_slave_p1_wrdata;
-wire          litedramcore_slave_p1_wrdata_en;
-wire    [3:0] litedramcore_slave_p1_wrdata_mask;
-wire          litedramcore_slave_p1_rddata_en;
-reg    [31:0] litedramcore_slave_p1_rddata = 32'd0;
-reg           litedramcore_slave_p1_rddata_valid = 1'd0;
-wire   [15:0] litedramcore_slave_p2_address;
-wire    [2:0] litedramcore_slave_p2_bank;
-wire          litedramcore_slave_p2_cas_n;
-wire          litedramcore_slave_p2_cs_n;
-wire          litedramcore_slave_p2_ras_n;
-wire          litedramcore_slave_p2_we_n;
-wire          litedramcore_slave_p2_cke;
-wire          litedramcore_slave_p2_odt;
-wire          litedramcore_slave_p2_reset_n;
-wire          litedramcore_slave_p2_act_n;
-wire   [31:0] litedramcore_slave_p2_wrdata;
-wire          litedramcore_slave_p2_wrdata_en;
-wire    [3:0] litedramcore_slave_p2_wrdata_mask;
-wire          litedramcore_slave_p2_rddata_en;
-reg    [31:0] litedramcore_slave_p2_rddata = 32'd0;
-reg           litedramcore_slave_p2_rddata_valid = 1'd0;
-wire   [15:0] litedramcore_slave_p3_address;
-wire    [2:0] litedramcore_slave_p3_bank;
-wire          litedramcore_slave_p3_cas_n;
-wire          litedramcore_slave_p3_cs_n;
-wire          litedramcore_slave_p3_ras_n;
-wire          litedramcore_slave_p3_we_n;
-wire          litedramcore_slave_p3_cke;
-wire          litedramcore_slave_p3_odt;
-wire          litedramcore_slave_p3_reset_n;
-wire          litedramcore_slave_p3_act_n;
-wire   [31:0] litedramcore_slave_p3_wrdata;
-wire          litedramcore_slave_p3_wrdata_en;
-wire    [3:0] litedramcore_slave_p3_wrdata_mask;
-wire          litedramcore_slave_p3_rddata_en;
-reg    [31:0] litedramcore_slave_p3_rddata = 32'd0;
-reg           litedramcore_slave_p3_rddata_valid = 1'd0;
-reg    [15:0] litedramcore_master_p0_address = 16'd0;
-reg     [2:0] litedramcore_master_p0_bank = 3'd0;
-reg           litedramcore_master_p0_cas_n = 1'd1;
-reg           litedramcore_master_p0_cs_n = 1'd1;
-reg           litedramcore_master_p0_ras_n = 1'd1;
-reg           litedramcore_master_p0_we_n = 1'd1;
-reg           litedramcore_master_p0_cke = 1'd0;
-reg           litedramcore_master_p0_odt = 1'd0;
-reg           litedramcore_master_p0_reset_n = 1'd0;
-reg           litedramcore_master_p0_act_n = 1'd1;
-reg    [31:0] litedramcore_master_p0_wrdata = 32'd0;
-reg           litedramcore_master_p0_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_master_p0_wrdata_mask = 4'd0;
-reg           litedramcore_master_p0_rddata_en = 1'd0;
-wire   [31:0] litedramcore_master_p0_rddata;
-wire          litedramcore_master_p0_rddata_valid;
-reg    [15:0] litedramcore_master_p1_address = 16'd0;
-reg     [2:0] litedramcore_master_p1_bank = 3'd0;
-reg           litedramcore_master_p1_cas_n = 1'd1;
-reg           litedramcore_master_p1_cs_n = 1'd1;
-reg           litedramcore_master_p1_ras_n = 1'd1;
-reg           litedramcore_master_p1_we_n = 1'd1;
-reg           litedramcore_master_p1_cke = 1'd0;
-reg           litedramcore_master_p1_odt = 1'd0;
-reg           litedramcore_master_p1_reset_n = 1'd0;
-reg           litedramcore_master_p1_act_n = 1'd1;
-reg    [31:0] litedramcore_master_p1_wrdata = 32'd0;
-reg           litedramcore_master_p1_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_master_p1_wrdata_mask = 4'd0;
-reg           litedramcore_master_p1_rddata_en = 1'd0;
-wire   [31:0] litedramcore_master_p1_rddata;
-wire          litedramcore_master_p1_rddata_valid;
-reg    [15:0] litedramcore_master_p2_address = 16'd0;
-reg     [2:0] litedramcore_master_p2_bank = 3'd0;
-reg           litedramcore_master_p2_cas_n = 1'd1;
-reg           litedramcore_master_p2_cs_n = 1'd1;
-reg           litedramcore_master_p2_ras_n = 1'd1;
-reg           litedramcore_master_p2_we_n = 1'd1;
-reg           litedramcore_master_p2_cke = 1'd0;
-reg           litedramcore_master_p2_odt = 1'd0;
-reg           litedramcore_master_p2_reset_n = 1'd0;
-reg           litedramcore_master_p2_act_n = 1'd1;
-reg    [31:0] litedramcore_master_p2_wrdata = 32'd0;
-reg           litedramcore_master_p2_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_master_p2_wrdata_mask = 4'd0;
-reg           litedramcore_master_p2_rddata_en = 1'd0;
-wire   [31:0] litedramcore_master_p2_rddata;
-wire          litedramcore_master_p2_rddata_valid;
-reg    [15:0] litedramcore_master_p3_address = 16'd0;
-reg     [2:0] litedramcore_master_p3_bank = 3'd0;
-reg           litedramcore_master_p3_cas_n = 1'd1;
-reg           litedramcore_master_p3_cs_n = 1'd1;
-reg           litedramcore_master_p3_ras_n = 1'd1;
-reg           litedramcore_master_p3_we_n = 1'd1;
-reg           litedramcore_master_p3_cke = 1'd0;
-reg           litedramcore_master_p3_odt = 1'd0;
-reg           litedramcore_master_p3_reset_n = 1'd0;
-reg           litedramcore_master_p3_act_n = 1'd1;
-reg    [31:0] litedramcore_master_p3_wrdata = 32'd0;
-reg           litedramcore_master_p3_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_master_p3_wrdata_mask = 4'd0;
-reg           litedramcore_master_p3_rddata_en = 1'd0;
-wire   [31:0] litedramcore_master_p3_rddata;
-wire          litedramcore_master_p3_rddata_valid;
-wire   [15:0] litedramcore_csr_dfi_p0_address;
-wire    [2:0] litedramcore_csr_dfi_p0_bank;
-reg           litedramcore_csr_dfi_p0_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p0_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p0_ras_n = 1'd1;
-reg           litedramcore_csr_dfi_p0_we_n = 1'd1;
-wire          litedramcore_csr_dfi_p0_cke;
-wire          litedramcore_csr_dfi_p0_odt;
-wire          litedramcore_csr_dfi_p0_reset_n;
-reg           litedramcore_csr_dfi_p0_act_n = 1'd1;
-wire   [31:0] litedramcore_csr_dfi_p0_wrdata;
-wire          litedramcore_csr_dfi_p0_wrdata_en;
-wire    [3:0] litedramcore_csr_dfi_p0_wrdata_mask;
-wire          litedramcore_csr_dfi_p0_rddata_en;
-reg    [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0;
-reg           litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
-wire   [15:0] litedramcore_csr_dfi_p1_address;
-wire    [2:0] litedramcore_csr_dfi_p1_bank;
-reg           litedramcore_csr_dfi_p1_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p1_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p1_ras_n = 1'd1;
-reg           litedramcore_csr_dfi_p1_we_n = 1'd1;
-wire          litedramcore_csr_dfi_p1_cke;
-wire          litedramcore_csr_dfi_p1_odt;
-wire          litedramcore_csr_dfi_p1_reset_n;
-reg           litedramcore_csr_dfi_p1_act_n = 1'd1;
-wire   [31:0] litedramcore_csr_dfi_p1_wrdata;
-wire          litedramcore_csr_dfi_p1_wrdata_en;
-wire    [3:0] litedramcore_csr_dfi_p1_wrdata_mask;
-wire          litedramcore_csr_dfi_p1_rddata_en;
-reg    [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0;
-reg           litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
-wire   [15:0] litedramcore_csr_dfi_p2_address;
-wire    [2:0] litedramcore_csr_dfi_p2_bank;
-reg           litedramcore_csr_dfi_p2_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p2_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p2_ras_n = 1'd1;
-reg           litedramcore_csr_dfi_p2_we_n = 1'd1;
-wire          litedramcore_csr_dfi_p2_cke;
-wire          litedramcore_csr_dfi_p2_odt;
-wire          litedramcore_csr_dfi_p2_reset_n;
-reg           litedramcore_csr_dfi_p2_act_n = 1'd1;
-wire   [31:0] litedramcore_csr_dfi_p2_wrdata;
-wire          litedramcore_csr_dfi_p2_wrdata_en;
-wire    [3:0] litedramcore_csr_dfi_p2_wrdata_mask;
-wire          litedramcore_csr_dfi_p2_rddata_en;
-reg    [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0;
-reg           litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
-wire   [15:0] litedramcore_csr_dfi_p3_address;
-wire    [2:0] litedramcore_csr_dfi_p3_bank;
-reg           litedramcore_csr_dfi_p3_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p3_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p3_ras_n = 1'd1;
-reg           litedramcore_csr_dfi_p3_we_n = 1'd1;
-wire          litedramcore_csr_dfi_p3_cke;
-wire          litedramcore_csr_dfi_p3_odt;
-wire          litedramcore_csr_dfi_p3_reset_n;
-reg           litedramcore_csr_dfi_p3_act_n = 1'd1;
-wire   [31:0] litedramcore_csr_dfi_p3_wrdata;
-wire          litedramcore_csr_dfi_p3_wrdata_en;
-wire    [3:0] litedramcore_csr_dfi_p3_wrdata_mask;
-wire          litedramcore_csr_dfi_p3_rddata_en;
-reg    [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0;
-reg           litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
-reg    [15:0] litedramcore_ext_dfi_p0_address = 16'd0;
-reg     [2:0] litedramcore_ext_dfi_p0_bank = 3'd0;
-reg           litedramcore_ext_dfi_p0_cas_n = 1'd1;
-reg           litedramcore_ext_dfi_p0_cs_n = 1'd1;
-reg           litedramcore_ext_dfi_p0_ras_n = 1'd1;
-reg           litedramcore_ext_dfi_p0_we_n = 1'd1;
-reg           litedramcore_ext_dfi_p0_cke = 1'd0;
-reg           litedramcore_ext_dfi_p0_odt = 1'd0;
-reg           litedramcore_ext_dfi_p0_reset_n = 1'd0;
-reg           litedramcore_ext_dfi_p0_act_n = 1'd1;
-reg    [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0;
-reg           litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
-reg           litedramcore_ext_dfi_p0_rddata_en = 1'd0;
-reg    [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0;
-reg           litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
-reg    [15:0] litedramcore_ext_dfi_p1_address = 16'd0;
-reg     [2:0] litedramcore_ext_dfi_p1_bank = 3'd0;
-reg           litedramcore_ext_dfi_p1_cas_n = 1'd1;
-reg           litedramcore_ext_dfi_p1_cs_n = 1'd1;
-reg           litedramcore_ext_dfi_p1_ras_n = 1'd1;
-reg           litedramcore_ext_dfi_p1_we_n = 1'd1;
-reg           litedramcore_ext_dfi_p1_cke = 1'd0;
-reg           litedramcore_ext_dfi_p1_odt = 1'd0;
-reg           litedramcore_ext_dfi_p1_reset_n = 1'd0;
-reg           litedramcore_ext_dfi_p1_act_n = 1'd1;
-reg    [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0;
-reg           litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
-reg           litedramcore_ext_dfi_p1_rddata_en = 1'd0;
-reg    [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0;
-reg           litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
-reg    [15:0] litedramcore_ext_dfi_p2_address = 16'd0;
-reg     [2:0] litedramcore_ext_dfi_p2_bank = 3'd0;
-reg           litedramcore_ext_dfi_p2_cas_n = 1'd1;
-reg           litedramcore_ext_dfi_p2_cs_n = 1'd1;
-reg           litedramcore_ext_dfi_p2_ras_n = 1'd1;
-reg           litedramcore_ext_dfi_p2_we_n = 1'd1;
-reg           litedramcore_ext_dfi_p2_cke = 1'd0;
-reg           litedramcore_ext_dfi_p2_odt = 1'd0;
-reg           litedramcore_ext_dfi_p2_reset_n = 1'd0;
-reg           litedramcore_ext_dfi_p2_act_n = 1'd1;
-reg    [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0;
-reg           litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
-reg           litedramcore_ext_dfi_p2_rddata_en = 1'd0;
-reg    [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0;
-reg           litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
-reg    [15:0] litedramcore_ext_dfi_p3_address = 16'd0;
-reg     [2:0] litedramcore_ext_dfi_p3_bank = 3'd0;
-reg           litedramcore_ext_dfi_p3_cas_n = 1'd1;
-reg           litedramcore_ext_dfi_p3_cs_n = 1'd1;
-reg           litedramcore_ext_dfi_p3_ras_n = 1'd1;
-reg           litedramcore_ext_dfi_p3_we_n = 1'd1;
-reg           litedramcore_ext_dfi_p3_cke = 1'd0;
-reg           litedramcore_ext_dfi_p3_odt = 1'd0;
-reg           litedramcore_ext_dfi_p3_reset_n = 1'd0;
-reg           litedramcore_ext_dfi_p3_act_n = 1'd1;
-reg    [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0;
-reg           litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
-reg           litedramcore_ext_dfi_p3_rddata_en = 1'd0;
-reg    [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0;
-reg           litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
-reg           litedramcore_ext_dfi_sel = 1'd0;
-wire          litedramcore_sel;
-wire          litedramcore_cke;
-wire          litedramcore_odt;
-wire          litedramcore_reset_n;
-reg     [3:0] litedramcore_storage = 4'd1;
-reg           litedramcore_re = 1'd0;
-wire          litedramcore_phaseinjector0_csrfield_cs;
-wire          litedramcore_phaseinjector0_csrfield_we;
-wire          litedramcore_phaseinjector0_csrfield_cas;
-wire          litedramcore_phaseinjector0_csrfield_ras;
-wire          litedramcore_phaseinjector0_csrfield_wren;
-wire          litedramcore_phaseinjector0_csrfield_rden;
-reg     [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
-reg           litedramcore_phaseinjector0_command_re = 1'd0;
-reg           litedramcore_phaseinjector0_command_issue_re = 1'd0;
-wire          litedramcore_phaseinjector0_command_issue_r;
-reg           litedramcore_phaseinjector0_command_issue_we = 1'd0;
-reg           litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg    [15:0] litedramcore_phaseinjector0_address_storage = 16'd0;
-reg           litedramcore_phaseinjector0_address_re = 1'd0;
-reg     [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg           litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0;
-reg           litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0;
-wire          litedramcore_phaseinjector0_rddata_we;
-reg           litedramcore_phaseinjector0_rddata_re = 1'd0;
-wire          litedramcore_phaseinjector1_csrfield_cs;
-wire          litedramcore_phaseinjector1_csrfield_we;
-wire          litedramcore_phaseinjector1_csrfield_cas;
-wire          litedramcore_phaseinjector1_csrfield_ras;
-wire          litedramcore_phaseinjector1_csrfield_wren;
-wire          litedramcore_phaseinjector1_csrfield_rden;
-reg     [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
-reg           litedramcore_phaseinjector1_command_re = 1'd0;
-reg           litedramcore_phaseinjector1_command_issue_re = 1'd0;
-wire          litedramcore_phaseinjector1_command_issue_r;
-reg           litedramcore_phaseinjector1_command_issue_we = 1'd0;
-reg           litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg    [15:0] litedramcore_phaseinjector1_address_storage = 16'd0;
-reg           litedramcore_phaseinjector1_address_re = 1'd0;
-reg     [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg           litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0;
-reg           litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0;
-wire          litedramcore_phaseinjector1_rddata_we;
-reg           litedramcore_phaseinjector1_rddata_re = 1'd0;
-wire          litedramcore_phaseinjector2_csrfield_cs;
-wire          litedramcore_phaseinjector2_csrfield_we;
-wire          litedramcore_phaseinjector2_csrfield_cas;
-wire          litedramcore_phaseinjector2_csrfield_ras;
-wire          litedramcore_phaseinjector2_csrfield_wren;
-wire          litedramcore_phaseinjector2_csrfield_rden;
-reg     [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
-reg           litedramcore_phaseinjector2_command_re = 1'd0;
-reg           litedramcore_phaseinjector2_command_issue_re = 1'd0;
-wire          litedramcore_phaseinjector2_command_issue_r;
-reg           litedramcore_phaseinjector2_command_issue_we = 1'd0;
-reg           litedramcore_phaseinjector2_command_issue_w = 1'd0;
-reg    [15:0] litedramcore_phaseinjector2_address_storage = 16'd0;
-reg           litedramcore_phaseinjector2_address_re = 1'd0;
-reg     [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
-reg           litedramcore_phaseinjector2_baddress_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0;
-reg           litedramcore_phaseinjector2_wrdata_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0;
-wire          litedramcore_phaseinjector2_rddata_we;
-reg           litedramcore_phaseinjector2_rddata_re = 1'd0;
-wire          litedramcore_phaseinjector3_csrfield_cs;
-wire          litedramcore_phaseinjector3_csrfield_we;
-wire          litedramcore_phaseinjector3_csrfield_cas;
-wire          litedramcore_phaseinjector3_csrfield_ras;
-wire          litedramcore_phaseinjector3_csrfield_wren;
-wire          litedramcore_phaseinjector3_csrfield_rden;
-reg     [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
-reg           litedramcore_phaseinjector3_command_re = 1'd0;
-reg           litedramcore_phaseinjector3_command_issue_re = 1'd0;
-wire          litedramcore_phaseinjector3_command_issue_r;
-reg           litedramcore_phaseinjector3_command_issue_we = 1'd0;
-reg           litedramcore_phaseinjector3_command_issue_w = 1'd0;
-reg    [15:0] litedramcore_phaseinjector3_address_storage = 16'd0;
-reg           litedramcore_phaseinjector3_address_re = 1'd0;
-reg     [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
-reg           litedramcore_phaseinjector3_baddress_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0;
-reg           litedramcore_phaseinjector3_wrdata_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0;
-wire          litedramcore_phaseinjector3_rddata_we;
-reg           litedramcore_phaseinjector3_rddata_re = 1'd0;
-wire          litedramcore_interface_bank0_valid;
-wire          litedramcore_interface_bank0_ready;
-wire          litedramcore_interface_bank0_we;
-wire   [22:0] litedramcore_interface_bank0_addr;
-wire          litedramcore_interface_bank0_lock;
-wire          litedramcore_interface_bank0_wdata_ready;
-wire          litedramcore_interface_bank0_rdata_valid;
-wire          litedramcore_interface_bank1_valid;
-wire          litedramcore_interface_bank1_ready;
-wire          litedramcore_interface_bank1_we;
-wire   [22:0] litedramcore_interface_bank1_addr;
-wire          litedramcore_interface_bank1_lock;
-wire          litedramcore_interface_bank1_wdata_ready;
-wire          litedramcore_interface_bank1_rdata_valid;
-wire          litedramcore_interface_bank2_valid;
-wire          litedramcore_interface_bank2_ready;
-wire          litedramcore_interface_bank2_we;
-wire   [22:0] litedramcore_interface_bank2_addr;
-wire          litedramcore_interface_bank2_lock;
-wire          litedramcore_interface_bank2_wdata_ready;
-wire          litedramcore_interface_bank2_rdata_valid;
-wire          litedramcore_interface_bank3_valid;
-wire          litedramcore_interface_bank3_ready;
-wire          litedramcore_interface_bank3_we;
-wire   [22:0] litedramcore_interface_bank3_addr;
-wire          litedramcore_interface_bank3_lock;
-wire          litedramcore_interface_bank3_wdata_ready;
-wire          litedramcore_interface_bank3_rdata_valid;
-wire          litedramcore_interface_bank4_valid;
-wire          litedramcore_interface_bank4_ready;
-wire          litedramcore_interface_bank4_we;
-wire   [22:0] litedramcore_interface_bank4_addr;
-wire          litedramcore_interface_bank4_lock;
-wire          litedramcore_interface_bank4_wdata_ready;
-wire          litedramcore_interface_bank4_rdata_valid;
-wire          litedramcore_interface_bank5_valid;
-wire          litedramcore_interface_bank5_ready;
-wire          litedramcore_interface_bank5_we;
-wire   [22:0] litedramcore_interface_bank5_addr;
-wire          litedramcore_interface_bank5_lock;
-wire          litedramcore_interface_bank5_wdata_ready;
-wire          litedramcore_interface_bank5_rdata_valid;
-wire          litedramcore_interface_bank6_valid;
-wire          litedramcore_interface_bank6_ready;
-wire          litedramcore_interface_bank6_we;
-wire   [22:0] litedramcore_interface_bank6_addr;
-wire          litedramcore_interface_bank6_lock;
-wire          litedramcore_interface_bank6_wdata_ready;
-wire          litedramcore_interface_bank6_rdata_valid;
-wire          litedramcore_interface_bank7_valid;
-wire          litedramcore_interface_bank7_ready;
-wire          litedramcore_interface_bank7_we;
-wire   [22:0] litedramcore_interface_bank7_addr;
-wire          litedramcore_interface_bank7_lock;
-wire          litedramcore_interface_bank7_wdata_ready;
-wire          litedramcore_interface_bank7_rdata_valid;
-reg   [127:0] litedramcore_interface_wdata = 128'd0;
-reg    [15:0] litedramcore_interface_wdata_we = 16'd0;
-wire  [127:0] litedramcore_interface_rdata;
-reg    [15:0] litedramcore_dfi_p0_address = 16'd0;
-reg     [2:0] litedramcore_dfi_p0_bank = 3'd0;
-reg           litedramcore_dfi_p0_cas_n = 1'd1;
-reg           litedramcore_dfi_p0_cs_n = 1'd1;
-reg           litedramcore_dfi_p0_ras_n = 1'd1;
-reg           litedramcore_dfi_p0_we_n = 1'd1;
-wire          litedramcore_dfi_p0_cke;
-wire          litedramcore_dfi_p0_odt;
-wire          litedramcore_dfi_p0_reset_n;
-reg           litedramcore_dfi_p0_act_n = 1'd1;
-wire   [31:0] litedramcore_dfi_p0_wrdata;
-reg           litedramcore_dfi_p0_wrdata_en = 1'd0;
-wire    [3:0] litedramcore_dfi_p0_wrdata_mask;
-reg           litedramcore_dfi_p0_rddata_en = 1'd0;
-wire   [31:0] litedramcore_dfi_p0_rddata;
-wire          litedramcore_dfi_p0_rddata_valid;
-reg    [15:0] litedramcore_dfi_p1_address = 16'd0;
-reg     [2:0] litedramcore_dfi_p1_bank = 3'd0;
-reg           litedramcore_dfi_p1_cas_n = 1'd1;
-reg           litedramcore_dfi_p1_cs_n = 1'd1;
-reg           litedramcore_dfi_p1_ras_n = 1'd1;
-reg           litedramcore_dfi_p1_we_n = 1'd1;
-wire          litedramcore_dfi_p1_cke;
-wire          litedramcore_dfi_p1_odt;
-wire          litedramcore_dfi_p1_reset_n;
-reg           litedramcore_dfi_p1_act_n = 1'd1;
-wire   [31:0] litedramcore_dfi_p1_wrdata;
-reg           litedramcore_dfi_p1_wrdata_en = 1'd0;
-wire    [3:0] litedramcore_dfi_p1_wrdata_mask;
-reg           litedramcore_dfi_p1_rddata_en = 1'd0;
-wire   [31:0] litedramcore_dfi_p1_rddata;
-wire          litedramcore_dfi_p1_rddata_valid;
-reg    [15:0] litedramcore_dfi_p2_address = 16'd0;
-reg     [2:0] litedramcore_dfi_p2_bank = 3'd0;
-reg           litedramcore_dfi_p2_cas_n = 1'd1;
-reg           litedramcore_dfi_p2_cs_n = 1'd1;
-reg           litedramcore_dfi_p2_ras_n = 1'd1;
-reg           litedramcore_dfi_p2_we_n = 1'd1;
-wire          litedramcore_dfi_p2_cke;
-wire          litedramcore_dfi_p2_odt;
-wire          litedramcore_dfi_p2_reset_n;
-reg           litedramcore_dfi_p2_act_n = 1'd1;
-wire   [31:0] litedramcore_dfi_p2_wrdata;
-reg           litedramcore_dfi_p2_wrdata_en = 1'd0;
-wire    [3:0] litedramcore_dfi_p2_wrdata_mask;
-reg           litedramcore_dfi_p2_rddata_en = 1'd0;
-wire   [31:0] litedramcore_dfi_p2_rddata;
-wire          litedramcore_dfi_p2_rddata_valid;
-reg    [15:0] litedramcore_dfi_p3_address = 16'd0;
-reg     [2:0] litedramcore_dfi_p3_bank = 3'd0;
-reg           litedramcore_dfi_p3_cas_n = 1'd1;
-reg           litedramcore_dfi_p3_cs_n = 1'd1;
-reg           litedramcore_dfi_p3_ras_n = 1'd1;
-reg           litedramcore_dfi_p3_we_n = 1'd1;
-wire          litedramcore_dfi_p3_cke;
-wire          litedramcore_dfi_p3_odt;
-wire          litedramcore_dfi_p3_reset_n;
-reg           litedramcore_dfi_p3_act_n = 1'd1;
-wire   [31:0] litedramcore_dfi_p3_wrdata;
-reg           litedramcore_dfi_p3_wrdata_en = 1'd0;
-wire    [3:0] litedramcore_dfi_p3_wrdata_mask;
-reg           litedramcore_dfi_p3_rddata_en = 1'd0;
-wire   [31:0] litedramcore_dfi_p3_rddata;
-wire          litedramcore_dfi_p3_rddata_valid;
-reg           litedramcore_cmd_valid = 1'd0;
-reg           litedramcore_cmd_ready = 1'd0;
-reg           litedramcore_cmd_last = 1'd0;
-reg    [15:0] litedramcore_cmd_payload_a = 16'd0;
-reg     [2:0] litedramcore_cmd_payload_ba = 3'd0;
-reg           litedramcore_cmd_payload_cas = 1'd0;
-reg           litedramcore_cmd_payload_ras = 1'd0;
-reg           litedramcore_cmd_payload_we = 1'd0;
-reg           litedramcore_cmd_payload_is_read = 1'd0;
-reg           litedramcore_cmd_payload_is_write = 1'd0;
-wire          litedramcore_wants_refresh;
-wire          litedramcore_wants_zqcs;
-wire          litedramcore_timer_wait;
-wire          litedramcore_timer_done0;
-wire    [9:0] litedramcore_timer_count0;
-wire          litedramcore_timer_done1;
-reg     [9:0] litedramcore_timer_count1 = 10'd781;
-wire          litedramcore_postponer_req_i;
-reg           litedramcore_postponer_req_o = 1'd0;
-reg           litedramcore_postponer_count = 1'd0;
-reg           litedramcore_sequencer_start0 = 1'd0;
-wire          litedramcore_sequencer_done0;
-wire          litedramcore_sequencer_start1;
-reg           litedramcore_sequencer_done1 = 1'd0;
-reg     [6:0] litedramcore_sequencer_counter = 7'd0;
-reg           litedramcore_sequencer_count = 1'd0;
-wire          litedramcore_zqcs_timer_wait;
-wire          litedramcore_zqcs_timer_done0;
-wire   [26:0] litedramcore_zqcs_timer_count0;
-wire          litedramcore_zqcs_timer_done1;
-reg    [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
-reg           litedramcore_zqcs_executer_start = 1'd0;
-reg           litedramcore_zqcs_executer_done = 1'd0;
-reg     [4:0] litedramcore_zqcs_executer_counter = 5'd0;
-wire          litedramcore_bankmachine0_req_valid;
-wire          litedramcore_bankmachine0_req_ready;
-wire          litedramcore_bankmachine0_req_we;
-wire   [22:0] litedramcore_bankmachine0_req_addr;
-wire          litedramcore_bankmachine0_req_lock;
-reg           litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine0_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine0_refresh_req;
-reg           litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg    [15:0] litedramcore_bankmachine0_cmd_payload_a = 16'd0;
-wire    [2:0] litedramcore_bankmachine0_cmd_payload_ba;
-reg           litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine0_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine0_sink_valid;
-wire          litedramcore_bankmachine0_sink_ready;
-reg           litedramcore_bankmachine0_sink_first = 1'd0;
-reg           litedramcore_bankmachine0_sink_last = 1'd0;
-wire          litedramcore_bankmachine0_sink_payload_we;
-wire   [22:0] litedramcore_bankmachine0_sink_payload_addr;
-wire          litedramcore_bankmachine0_source_valid;
-wire          litedramcore_bankmachine0_source_ready;
-wire          litedramcore_bankmachine0_source_first;
-wire          litedramcore_bankmachine0_source_last;
-wire          litedramcore_bankmachine0_source_payload_we;
-wire   [22:0] litedramcore_bankmachine0_source_payload_addr;
-wire          litedramcore_bankmachine0_syncfifo0_we;
-wire          litedramcore_bankmachine0_syncfifo0_writable;
-wire          litedramcore_bankmachine0_syncfifo0_re;
-wire          litedramcore_bankmachine0_syncfifo0_readable;
-wire   [25:0] litedramcore_bankmachine0_syncfifo0_din;
-wire   [25:0] litedramcore_bankmachine0_syncfifo0_dout;
-reg     [4:0] litedramcore_bankmachine0_level = 5'd0;
-reg           litedramcore_bankmachine0_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine0_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine0_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0;
-wire   [25:0] litedramcore_bankmachine0_wrport_dat_r;
-wire          litedramcore_bankmachine0_wrport_we;
-wire   [25:0] litedramcore_bankmachine0_wrport_dat_w;
-wire          litedramcore_bankmachine0_do_read;
-wire    [3:0] litedramcore_bankmachine0_rdport_adr;
-wire   [25:0] litedramcore_bankmachine0_rdport_dat_r;
-wire          litedramcore_bankmachine0_fifo_in_payload_we;
-wire   [22:0] litedramcore_bankmachine0_fifo_in_payload_addr;
-wire          litedramcore_bankmachine0_fifo_in_first;
-wire          litedramcore_bankmachine0_fifo_in_last;
-wire          litedramcore_bankmachine0_fifo_out_payload_we;
-wire   [22:0] litedramcore_bankmachine0_fifo_out_payload_addr;
-wire          litedramcore_bankmachine0_fifo_out_first;
-wire          litedramcore_bankmachine0_fifo_out_last;
-wire          litedramcore_bankmachine0_sink_sink_valid;
-wire          litedramcore_bankmachine0_sink_sink_ready;
-wire          litedramcore_bankmachine0_sink_sink_first;
-wire          litedramcore_bankmachine0_sink_sink_last;
-wire          litedramcore_bankmachine0_sink_sink_payload_we;
-wire   [22:0] litedramcore_bankmachine0_sink_sink_payload_addr;
-wire          litedramcore_bankmachine0_source_source_valid;
-wire          litedramcore_bankmachine0_source_source_ready;
-wire          litedramcore_bankmachine0_source_source_first;
-wire          litedramcore_bankmachine0_source_source_last;
-wire          litedramcore_bankmachine0_source_source_payload_we;
-wire   [22:0] litedramcore_bankmachine0_source_source_payload_addr;
-wire          litedramcore_bankmachine0_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine0_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine0_pipe_valid_sink_first;
-wire          litedramcore_bankmachine0_pipe_valid_sink_last;
-wire          litedramcore_bankmachine0_pipe_valid_sink_payload_we;
-wire   [22:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine0_pipe_valid_source_ready;
-reg           litedramcore_bankmachine0_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine0_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0;
-reg    [22:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 23'd0;
-reg    [15:0] litedramcore_bankmachine0_row = 16'd0;
-reg           litedramcore_bankmachine0_row_opened = 1'd0;
-wire          litedramcore_bankmachine0_row_hit;
-reg           litedramcore_bankmachine0_row_open = 1'd0;
-reg           litedramcore_bankmachine0_row_close = 1'd0;
-reg           litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine0_twtpcon_valid;
+wire          main_a7ddrphy0;
+wire          main_a7ddrphy1;
+reg     [7:0] main_a7ddrphy_bitslip00 = 8'd0;
+reg     [7:0] main_a7ddrphy_bitslip01 = 8'd0;
+reg     [7:0] main_a7ddrphy_bitslip02 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip03;
+reg     [7:0] main_a7ddrphy_bitslip04 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip10 = 8'd0;
+reg     [7:0] main_a7ddrphy_bitslip100 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip101;
+reg     [7:0] main_a7ddrphy_bitslip102 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip11 = 8'd0;
+reg     [7:0] main_a7ddrphy_bitslip110 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip111;
+reg     [7:0] main_a7ddrphy_bitslip112 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip12 = 8'd0;
+reg     [7:0] main_a7ddrphy_bitslip120 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip121;
+reg     [7:0] main_a7ddrphy_bitslip122 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7;
+wire    [7:0] main_a7ddrphy_bitslip13;
+reg     [7:0] main_a7ddrphy_bitslip130 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip131;
+reg     [7:0] main_a7ddrphy_bitslip132 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip14 = 8'd0;
+reg     [7:0] main_a7ddrphy_bitslip140 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip141;
+reg     [7:0] main_a7ddrphy_bitslip142 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip150 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip151;
+reg     [7:0] main_a7ddrphy_bitslip152 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7;
+reg    [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip20 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip21;
+reg     [7:0] main_a7ddrphy_bitslip22 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip30 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip31;
+reg     [7:0] main_a7ddrphy_bitslip32 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip40 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip41;
+reg     [7:0] main_a7ddrphy_bitslip42 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip50 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip51;
+reg     [7:0] main_a7ddrphy_bitslip52 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip60 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip61;
+reg     [7:0] main_a7ddrphy_bitslip62 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip70 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip71;
+reg     [7:0] main_a7ddrphy_bitslip72 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip80 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip81;
+reg     [7:0] main_a7ddrphy_bitslip82 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip90 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip91;
+reg     [7:0] main_a7ddrphy_bitslip92 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7;
+wire          main_a7ddrphy_dfi_p0_act_n;
+wire   [15:0] main_a7ddrphy_dfi_p0_address;
+wire    [2:0] main_a7ddrphy_dfi_p0_bank;
+wire          main_a7ddrphy_dfi_p0_cas_n;
+wire          main_a7ddrphy_dfi_p0_cke;
+wire          main_a7ddrphy_dfi_p0_cs_n;
+wire          main_a7ddrphy_dfi_p0_odt;
+wire          main_a7ddrphy_dfi_p0_ras_n;
+reg    [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0;
+wire          main_a7ddrphy_dfi_p0_rddata_en;
+wire          main_a7ddrphy_dfi_p0_rddata_valid;
+wire          main_a7ddrphy_dfi_p0_reset_n;
+wire          main_a7ddrphy_dfi_p0_we_n;
+wire   [31:0] main_a7ddrphy_dfi_p0_wrdata;
+wire          main_a7ddrphy_dfi_p0_wrdata_en;
+wire    [3:0] main_a7ddrphy_dfi_p0_wrdata_mask;
+wire          main_a7ddrphy_dfi_p1_act_n;
+wire   [15:0] main_a7ddrphy_dfi_p1_address;
+wire    [2:0] main_a7ddrphy_dfi_p1_bank;
+wire          main_a7ddrphy_dfi_p1_cas_n;
+wire          main_a7ddrphy_dfi_p1_cke;
+wire          main_a7ddrphy_dfi_p1_cs_n;
+wire          main_a7ddrphy_dfi_p1_odt;
+wire          main_a7ddrphy_dfi_p1_ras_n;
+reg    [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0;
+wire          main_a7ddrphy_dfi_p1_rddata_en;
+wire          main_a7ddrphy_dfi_p1_rddata_valid;
+wire          main_a7ddrphy_dfi_p1_reset_n;
+wire          main_a7ddrphy_dfi_p1_we_n;
+wire   [31:0] main_a7ddrphy_dfi_p1_wrdata;
+wire          main_a7ddrphy_dfi_p1_wrdata_en;
+wire    [3:0] main_a7ddrphy_dfi_p1_wrdata_mask;
+wire          main_a7ddrphy_dfi_p2_act_n;
+wire   [15:0] main_a7ddrphy_dfi_p2_address;
+wire    [2:0] main_a7ddrphy_dfi_p2_bank;
+wire          main_a7ddrphy_dfi_p2_cas_n;
+wire          main_a7ddrphy_dfi_p2_cke;
+wire          main_a7ddrphy_dfi_p2_cs_n;
+wire          main_a7ddrphy_dfi_p2_odt;
+wire          main_a7ddrphy_dfi_p2_ras_n;
+reg    [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0;
+wire          main_a7ddrphy_dfi_p2_rddata_en;
+wire          main_a7ddrphy_dfi_p2_rddata_valid;
+wire          main_a7ddrphy_dfi_p2_reset_n;
+wire          main_a7ddrphy_dfi_p2_we_n;
+wire   [31:0] main_a7ddrphy_dfi_p2_wrdata;
+wire          main_a7ddrphy_dfi_p2_wrdata_en;
+wire    [3:0] main_a7ddrphy_dfi_p2_wrdata_mask;
+wire          main_a7ddrphy_dfi_p3_act_n;
+wire   [15:0] main_a7ddrphy_dfi_p3_address;
+wire    [2:0] main_a7ddrphy_dfi_p3_bank;
+wire          main_a7ddrphy_dfi_p3_cas_n;
+wire          main_a7ddrphy_dfi_p3_cke;
+wire          main_a7ddrphy_dfi_p3_cs_n;
+wire          main_a7ddrphy_dfi_p3_odt;
+wire          main_a7ddrphy_dfi_p3_ras_n;
+reg    [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0;
+wire          main_a7ddrphy_dfi_p3_rddata_en;
+wire          main_a7ddrphy_dfi_p3_rddata_valid;
+wire          main_a7ddrphy_dfi_p3_reset_n;
+wire          main_a7ddrphy_dfi_p3_we_n;
+wire   [31:0] main_a7ddrphy_dfi_p3_wrdata;
+wire          main_a7ddrphy_dfi_p3_wrdata_en;
+wire    [3:0] main_a7ddrphy_dfi_p3_wrdata_mask;
+reg           main_a7ddrphy_dly_sel_re = 1'd0;
+reg     [1:0] main_a7ddrphy_dly_sel_storage = 2'd0;
+wire          main_a7ddrphy_dq_i_delayed0;
+wire          main_a7ddrphy_dq_i_delayed1;
+wire          main_a7ddrphy_dq_i_delayed10;
+wire          main_a7ddrphy_dq_i_delayed11;
+wire          main_a7ddrphy_dq_i_delayed12;
+wire          main_a7ddrphy_dq_i_delayed13;
+wire          main_a7ddrphy_dq_i_delayed14;
+wire          main_a7ddrphy_dq_i_delayed15;
+wire          main_a7ddrphy_dq_i_delayed2;
+wire          main_a7ddrphy_dq_i_delayed3;
+wire          main_a7ddrphy_dq_i_delayed4;
+wire          main_a7ddrphy_dq_i_delayed5;
+wire          main_a7ddrphy_dq_i_delayed6;
+wire          main_a7ddrphy_dq_i_delayed7;
+wire          main_a7ddrphy_dq_i_delayed8;
+wire          main_a7ddrphy_dq_i_delayed9;
+wire          main_a7ddrphy_dq_i_nodelay0;
+wire          main_a7ddrphy_dq_i_nodelay1;
+wire          main_a7ddrphy_dq_i_nodelay10;
+wire          main_a7ddrphy_dq_i_nodelay11;
+wire          main_a7ddrphy_dq_i_nodelay12;
+wire          main_a7ddrphy_dq_i_nodelay13;
+wire          main_a7ddrphy_dq_i_nodelay14;
+wire          main_a7ddrphy_dq_i_nodelay15;
+wire          main_a7ddrphy_dq_i_nodelay2;
+wire          main_a7ddrphy_dq_i_nodelay3;
+wire          main_a7ddrphy_dq_i_nodelay4;
+wire          main_a7ddrphy_dq_i_nodelay5;
+wire          main_a7ddrphy_dq_i_nodelay6;
+wire          main_a7ddrphy_dq_i_nodelay7;
+wire          main_a7ddrphy_dq_i_nodelay8;
+wire          main_a7ddrphy_dq_i_nodelay9;
+wire          main_a7ddrphy_dq_o_nodelay0;
+wire          main_a7ddrphy_dq_o_nodelay1;
+wire          main_a7ddrphy_dq_o_nodelay10;
+wire          main_a7ddrphy_dq_o_nodelay11;
+wire          main_a7ddrphy_dq_o_nodelay12;
+wire          main_a7ddrphy_dq_o_nodelay13;
+wire          main_a7ddrphy_dq_o_nodelay14;
+wire          main_a7ddrphy_dq_o_nodelay15;
+wire          main_a7ddrphy_dq_o_nodelay2;
+wire          main_a7ddrphy_dq_o_nodelay3;
+wire          main_a7ddrphy_dq_o_nodelay4;
+wire          main_a7ddrphy_dq_o_nodelay5;
+wire          main_a7ddrphy_dq_o_nodelay6;
+wire          main_a7ddrphy_dq_o_nodelay7;
+wire          main_a7ddrphy_dq_o_nodelay8;
+wire          main_a7ddrphy_dq_o_nodelay9;
+wire          main_a7ddrphy_dq_oe;
+wire          main_a7ddrphy_dq_oe_delay_tappeddelayline;
+reg           main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg           main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+wire          main_a7ddrphy_dq_t0;
+wire          main_a7ddrphy_dq_t1;
+wire          main_a7ddrphy_dq_t10;
+wire          main_a7ddrphy_dq_t11;
+wire          main_a7ddrphy_dq_t12;
+wire          main_a7ddrphy_dq_t13;
+wire          main_a7ddrphy_dq_t14;
+wire          main_a7ddrphy_dq_t15;
+wire          main_a7ddrphy_dq_t2;
+wire          main_a7ddrphy_dq_t3;
+wire          main_a7ddrphy_dq_t4;
+wire          main_a7ddrphy_dq_t5;
+wire          main_a7ddrphy_dq_t6;
+wire          main_a7ddrphy_dq_t7;
+wire          main_a7ddrphy_dq_t8;
+wire          main_a7ddrphy_dq_t9;
+wire          main_a7ddrphy_dqs_o_no_delay0;
+wire          main_a7ddrphy_dqs_o_no_delay1;
+reg           main_a7ddrphy_dqs_oe = 1'd0;
+wire          main_a7ddrphy_dqs_oe_delay_tappeddelayline;
+reg           main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg           main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+wire          main_a7ddrphy_dqs_postamble;
+wire          main_a7ddrphy_dqs_preamble;
+wire          main_a7ddrphy_dqs_t0;
+wire          main_a7ddrphy_dqs_t1;
+reg           main_a7ddrphy_dqspattern0 = 1'd0;
+reg           main_a7ddrphy_dqspattern1 = 1'd0;
+reg     [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0;
+reg     [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0;
+reg           main_a7ddrphy_half_sys8x_taps_re = 1'd0;
+reg     [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8;
+wire    [2:0] main_a7ddrphy_pads_ba;
+reg           main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
+wire          main_a7ddrphy_rdly_dq_bitslip_r;
+reg           main_a7ddrphy_rdly_dq_bitslip_re = 1'd0;
+wire          main_a7ddrphy_rdly_dq_bitslip_rst_r;
+reg           main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
+reg           main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+reg           main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
+reg           main_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
+reg           main_a7ddrphy_rdly_dq_bitslip_we = 1'd0;
+wire          main_a7ddrphy_rdly_dq_inc_r;
+reg           main_a7ddrphy_rdly_dq_inc_re = 1'd0;
+reg           main_a7ddrphy_rdly_dq_inc_w = 1'd0;
+reg           main_a7ddrphy_rdly_dq_inc_we = 1'd0;
+wire          main_a7ddrphy_rdly_dq_rst_r;
+reg           main_a7ddrphy_rdly_dq_rst_re = 1'd0;
+reg           main_a7ddrphy_rdly_dq_rst_w = 1'd0;
+reg           main_a7ddrphy_rdly_dq_rst_we = 1'd0;
+reg           main_a7ddrphy_rdphase_re = 1'd0;
+reg     [1:0] main_a7ddrphy_rdphase_storage = 2'd2;
+reg           main_a7ddrphy_rst_re = 1'd0;
+reg           main_a7ddrphy_rst_storage = 1'd0;
+wire          main_a7ddrphy_sd_clk_se_nodelay;
+wire          main_a7ddrphy_wdly_dq_bitslip_r;
+reg           main_a7ddrphy_wdly_dq_bitslip_re = 1'd0;
+wire          main_a7ddrphy_wdly_dq_bitslip_rst_r;
+reg           main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
+reg           main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
+reg           main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
+reg           main_a7ddrphy_wdly_dq_bitslip_w = 1'd0;
+reg           main_a7ddrphy_wdly_dq_bitslip_we = 1'd0;
+reg           main_a7ddrphy_wlevel_en_re = 1'd0;
+reg           main_a7ddrphy_wlevel_en_storage = 1'd0;
+wire          main_a7ddrphy_wlevel_strobe_r;
+reg           main_a7ddrphy_wlevel_strobe_re = 1'd0;
+reg           main_a7ddrphy_wlevel_strobe_w = 1'd0;
+reg           main_a7ddrphy_wlevel_strobe_we = 1'd0;
+reg           main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
+reg           main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
+reg           main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
+reg           main_a7ddrphy_wrphase_re = 1'd0;
+reg     [1:0] main_a7ddrphy_wrphase_storage = 2'd3;
+wire          main_clkin;
+wire          main_clkout0;
+wire          main_clkout1;
+wire          main_clkout2;
+wire          main_clkout3;
+wire          main_clkout_buf0;
+wire          main_clkout_buf1;
+wire          main_clkout_buf2;
+wire          main_clkout_buf3;
+reg           main_ic_reset = 1'd1;
+reg           main_init_done_re = 1'd0;
+reg           main_init_done_storage = 1'd0;
+reg           main_init_error_re = 1'd0;
+reg           main_init_error_storage = 1'd0;
+reg           main_litedramcore_bankmachine0_auto_precharge = 1'd0;
+reg    [15:0] main_litedramcore_bankmachine0_cmd_payload_a = 16'd0;
+wire    [2:0] main_litedramcore_bankmachine0_cmd_payload_ba;
+reg           main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine0_consume = 4'd0;
+wire          main_litedramcore_bankmachine0_do_read;
+wire          main_litedramcore_bankmachine0_fifo_in_first;
+wire          main_litedramcore_bankmachine0_fifo_in_last;
+wire   [22:0] main_litedramcore_bankmachine0_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine0_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine0_fifo_out_first;
+wire          main_litedramcore_bankmachine0_fifo_out_last;
+wire   [22:0] main_litedramcore_bankmachine0_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine0_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine0_level = 5'd0;
+wire          main_litedramcore_bankmachine0_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine0_pipe_valid_sink_last;
+wire   [22:0] main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine0_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine0_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine0_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine0_pipe_valid_source_last = 1'd0;
+reg    [22:0] main_litedramcore_bankmachine0_pipe_valid_source_payload_addr = 23'd0;
+reg           main_litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine0_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine0_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine0_rdport_adr;
+wire   [25:0] main_litedramcore_bankmachine0_rdport_dat_r;
+reg           main_litedramcore_bankmachine0_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine0_refresh_req;
+reg           main_litedramcore_bankmachine0_replace = 1'd0;
+wire   [22:0] main_litedramcore_bankmachine0_req_addr;
+wire          main_litedramcore_bankmachine0_req_lock;
+reg           main_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine0_req_ready;
+wire          main_litedramcore_bankmachine0_req_valid;
+reg           main_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine0_req_we;
+reg    [15:0] main_litedramcore_bankmachine0_row = 16'd0;
+reg           main_litedramcore_bankmachine0_row_close = 1'd0;
+reg           main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine0_row_hit;
+reg           main_litedramcore_bankmachine0_row_open = 1'd0;
+reg           main_litedramcore_bankmachine0_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine0_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine0_sink_last = 1'd0;
+wire   [22:0] main_litedramcore_bankmachine0_sink_payload_addr;
+wire          main_litedramcore_bankmachine0_sink_payload_we;
+wire          main_litedramcore_bankmachine0_sink_ready;
+wire          main_litedramcore_bankmachine0_sink_sink_first;
+wire          main_litedramcore_bankmachine0_sink_sink_last;
+wire   [22:0] main_litedramcore_bankmachine0_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine0_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine0_sink_sink_ready;
+wire          main_litedramcore_bankmachine0_sink_sink_valid;
+wire          main_litedramcore_bankmachine0_sink_valid;
+wire          main_litedramcore_bankmachine0_source_first;
+wire          main_litedramcore_bankmachine0_source_last;
+wire   [22:0] main_litedramcore_bankmachine0_source_payload_addr;
+wire          main_litedramcore_bankmachine0_source_payload_we;
+wire          main_litedramcore_bankmachine0_source_ready;
+wire          main_litedramcore_bankmachine0_source_source_first;
+wire          main_litedramcore_bankmachine0_source_source_last;
+wire   [22:0] main_litedramcore_bankmachine0_source_source_payload_addr;
+wire          main_litedramcore_bankmachine0_source_source_payload_we;
+wire          main_litedramcore_bankmachine0_source_source_ready;
+wire          main_litedramcore_bankmachine0_source_source_valid;
+wire          main_litedramcore_bankmachine0_source_valid;
+wire   [25:0] main_litedramcore_bankmachine0_syncfifo0_din;
+wire   [25:0] main_litedramcore_bankmachine0_syncfifo0_dout;
+wire          main_litedramcore_bankmachine0_syncfifo0_re;
+wire          main_litedramcore_bankmachine0_syncfifo0_readable;
+wire          main_litedramcore_bankmachine0_syncfifo0_we;
+wire          main_litedramcore_bankmachine0_syncfifo0_writable;
+reg     [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine0_trccon_valid;
+reg           main_litedramcore_bankmachine0_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine0_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
-wire          litedramcore_bankmachine0_trascon_valid;
+reg           main_litedramcore_bankmachine0_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine0_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine0_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
-wire          litedramcore_bankmachine1_req_valid;
-wire          litedramcore_bankmachine1_req_ready;
-wire          litedramcore_bankmachine1_req_we;
-wire   [22:0] litedramcore_bankmachine1_req_addr;
-wire          litedramcore_bankmachine1_req_lock;
-reg           litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine1_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine1_refresh_req;
-reg           litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine1_cmd_ready = 1'd0;
-reg    [15:0] litedramcore_bankmachine1_cmd_payload_a = 16'd0;
-wire    [2:0] litedramcore_bankmachine1_cmd_payload_ba;
-reg           litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine1_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine1_sink_valid;
-wire          litedramcore_bankmachine1_sink_ready;
-reg           litedramcore_bankmachine1_sink_first = 1'd0;
-reg           litedramcore_bankmachine1_sink_last = 1'd0;
-wire          litedramcore_bankmachine1_sink_payload_we;
-wire   [22:0] litedramcore_bankmachine1_sink_payload_addr;
-wire          litedramcore_bankmachine1_source_valid;
-wire          litedramcore_bankmachine1_source_ready;
-wire          litedramcore_bankmachine1_source_first;
-wire          litedramcore_bankmachine1_source_last;
-wire          litedramcore_bankmachine1_source_payload_we;
-wire   [22:0] litedramcore_bankmachine1_source_payload_addr;
-wire          litedramcore_bankmachine1_syncfifo1_we;
-wire          litedramcore_bankmachine1_syncfifo1_writable;
-wire          litedramcore_bankmachine1_syncfifo1_re;
-wire          litedramcore_bankmachine1_syncfifo1_readable;
-wire   [25:0] litedramcore_bankmachine1_syncfifo1_din;
-wire   [25:0] litedramcore_bankmachine1_syncfifo1_dout;
-reg     [4:0] litedramcore_bankmachine1_level = 5'd0;
-reg           litedramcore_bankmachine1_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine1_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine1_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0;
-wire   [25:0] litedramcore_bankmachine1_wrport_dat_r;
-wire          litedramcore_bankmachine1_wrport_we;
-wire   [25:0] litedramcore_bankmachine1_wrport_dat_w;
-wire          litedramcore_bankmachine1_do_read;
-wire    [3:0] litedramcore_bankmachine1_rdport_adr;
-wire   [25:0] litedramcore_bankmachine1_rdport_dat_r;
-wire          litedramcore_bankmachine1_fifo_in_payload_we;
-wire   [22:0] litedramcore_bankmachine1_fifo_in_payload_addr;
-wire          litedramcore_bankmachine1_fifo_in_first;
-wire          litedramcore_bankmachine1_fifo_in_last;
-wire          litedramcore_bankmachine1_fifo_out_payload_we;
-wire   [22:0] litedramcore_bankmachine1_fifo_out_payload_addr;
-wire          litedramcore_bankmachine1_fifo_out_first;
-wire          litedramcore_bankmachine1_fifo_out_last;
-wire          litedramcore_bankmachine1_sink_sink_valid;
-wire          litedramcore_bankmachine1_sink_sink_ready;
-wire          litedramcore_bankmachine1_sink_sink_first;
-wire          litedramcore_bankmachine1_sink_sink_last;
-wire          litedramcore_bankmachine1_sink_sink_payload_we;
-wire   [22:0] litedramcore_bankmachine1_sink_sink_payload_addr;
-wire          litedramcore_bankmachine1_source_source_valid;
-wire          litedramcore_bankmachine1_source_source_ready;
-wire          litedramcore_bankmachine1_source_source_first;
-wire          litedramcore_bankmachine1_source_source_last;
-wire          litedramcore_bankmachine1_source_source_payload_we;
-wire   [22:0] litedramcore_bankmachine1_source_source_payload_addr;
-wire          litedramcore_bankmachine1_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine1_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine1_pipe_valid_sink_first;
-wire          litedramcore_bankmachine1_pipe_valid_sink_last;
-wire          litedramcore_bankmachine1_pipe_valid_sink_payload_we;
-wire   [22:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine1_pipe_valid_source_ready;
-reg           litedramcore_bankmachine1_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine1_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0;
-reg    [22:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 23'd0;
-reg    [15:0] litedramcore_bankmachine1_row = 16'd0;
-reg           litedramcore_bankmachine1_row_opened = 1'd0;
-wire          litedramcore_bankmachine1_row_hit;
-reg           litedramcore_bankmachine1_row_open = 1'd0;
-reg           litedramcore_bankmachine1_row_close = 1'd0;
-reg           litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine1_twtpcon_valid;
+reg           main_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine0_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine0_wrport_adr = 4'd0;
+wire   [25:0] main_litedramcore_bankmachine0_wrport_dat_r;
+wire   [25:0] main_litedramcore_bankmachine0_wrport_dat_w;
+wire          main_litedramcore_bankmachine0_wrport_we;
+reg           main_litedramcore_bankmachine1_auto_precharge = 1'd0;
+reg    [15:0] main_litedramcore_bankmachine1_cmd_payload_a = 16'd0;
+wire    [2:0] main_litedramcore_bankmachine1_cmd_payload_ba;
+reg           main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine1_consume = 4'd0;
+wire          main_litedramcore_bankmachine1_do_read;
+wire          main_litedramcore_bankmachine1_fifo_in_first;
+wire          main_litedramcore_bankmachine1_fifo_in_last;
+wire   [22:0] main_litedramcore_bankmachine1_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine1_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine1_fifo_out_first;
+wire          main_litedramcore_bankmachine1_fifo_out_last;
+wire   [22:0] main_litedramcore_bankmachine1_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine1_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine1_level = 5'd0;
+wire          main_litedramcore_bankmachine1_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine1_pipe_valid_sink_last;
+wire   [22:0] main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine1_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine1_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine1_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine1_pipe_valid_source_last = 1'd0;
+reg    [22:0] main_litedramcore_bankmachine1_pipe_valid_source_payload_addr = 23'd0;
+reg           main_litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine1_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine1_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine1_rdport_adr;
+wire   [25:0] main_litedramcore_bankmachine1_rdport_dat_r;
+reg           main_litedramcore_bankmachine1_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine1_refresh_req;
+reg           main_litedramcore_bankmachine1_replace = 1'd0;
+wire   [22:0] main_litedramcore_bankmachine1_req_addr;
+wire          main_litedramcore_bankmachine1_req_lock;
+reg           main_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine1_req_ready;
+wire          main_litedramcore_bankmachine1_req_valid;
+reg           main_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine1_req_we;
+reg    [15:0] main_litedramcore_bankmachine1_row = 16'd0;
+reg           main_litedramcore_bankmachine1_row_close = 1'd0;
+reg           main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine1_row_hit;
+reg           main_litedramcore_bankmachine1_row_open = 1'd0;
+reg           main_litedramcore_bankmachine1_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine1_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine1_sink_last = 1'd0;
+wire   [22:0] main_litedramcore_bankmachine1_sink_payload_addr;
+wire          main_litedramcore_bankmachine1_sink_payload_we;
+wire          main_litedramcore_bankmachine1_sink_ready;
+wire          main_litedramcore_bankmachine1_sink_sink_first;
+wire          main_litedramcore_bankmachine1_sink_sink_last;
+wire   [22:0] main_litedramcore_bankmachine1_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine1_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine1_sink_sink_ready;
+wire          main_litedramcore_bankmachine1_sink_sink_valid;
+wire          main_litedramcore_bankmachine1_sink_valid;
+wire          main_litedramcore_bankmachine1_source_first;
+wire          main_litedramcore_bankmachine1_source_last;
+wire   [22:0] main_litedramcore_bankmachine1_source_payload_addr;
+wire          main_litedramcore_bankmachine1_source_payload_we;
+wire          main_litedramcore_bankmachine1_source_ready;
+wire          main_litedramcore_bankmachine1_source_source_first;
+wire          main_litedramcore_bankmachine1_source_source_last;
+wire   [22:0] main_litedramcore_bankmachine1_source_source_payload_addr;
+wire          main_litedramcore_bankmachine1_source_source_payload_we;
+wire          main_litedramcore_bankmachine1_source_source_ready;
+wire          main_litedramcore_bankmachine1_source_source_valid;
+wire          main_litedramcore_bankmachine1_source_valid;
+wire   [25:0] main_litedramcore_bankmachine1_syncfifo1_din;
+wire   [25:0] main_litedramcore_bankmachine1_syncfifo1_dout;
+wire          main_litedramcore_bankmachine1_syncfifo1_re;
+wire          main_litedramcore_bankmachine1_syncfifo1_readable;
+wire          main_litedramcore_bankmachine1_syncfifo1_we;
+wire          main_litedramcore_bankmachine1_syncfifo1_writable;
+reg     [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine1_trccon_valid;
+reg           main_litedramcore_bankmachine1_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine1_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
-wire          litedramcore_bankmachine1_trascon_valid;
+reg           main_litedramcore_bankmachine1_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine1_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine1_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
-wire          litedramcore_bankmachine2_req_valid;
-wire          litedramcore_bankmachine2_req_ready;
-wire          litedramcore_bankmachine2_req_we;
-wire   [22:0] litedramcore_bankmachine2_req_addr;
-wire          litedramcore_bankmachine2_req_lock;
-reg           litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine2_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine2_refresh_req;
-reg           litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine2_cmd_ready = 1'd0;
-reg    [15:0] litedramcore_bankmachine2_cmd_payload_a = 16'd0;
-wire    [2:0] litedramcore_bankmachine2_cmd_payload_ba;
-reg           litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine2_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine2_sink_valid;
-wire          litedramcore_bankmachine2_sink_ready;
-reg           litedramcore_bankmachine2_sink_first = 1'd0;
-reg           litedramcore_bankmachine2_sink_last = 1'd0;
-wire          litedramcore_bankmachine2_sink_payload_we;
-wire   [22:0] litedramcore_bankmachine2_sink_payload_addr;
-wire          litedramcore_bankmachine2_source_valid;
-wire          litedramcore_bankmachine2_source_ready;
-wire          litedramcore_bankmachine2_source_first;
-wire          litedramcore_bankmachine2_source_last;
-wire          litedramcore_bankmachine2_source_payload_we;
-wire   [22:0] litedramcore_bankmachine2_source_payload_addr;
-wire          litedramcore_bankmachine2_syncfifo2_we;
-wire          litedramcore_bankmachine2_syncfifo2_writable;
-wire          litedramcore_bankmachine2_syncfifo2_re;
-wire          litedramcore_bankmachine2_syncfifo2_readable;
-wire   [25:0] litedramcore_bankmachine2_syncfifo2_din;
-wire   [25:0] litedramcore_bankmachine2_syncfifo2_dout;
-reg     [4:0] litedramcore_bankmachine2_level = 5'd0;
-reg           litedramcore_bankmachine2_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine2_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine2_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0;
-wire   [25:0] litedramcore_bankmachine2_wrport_dat_r;
-wire          litedramcore_bankmachine2_wrport_we;
-wire   [25:0] litedramcore_bankmachine2_wrport_dat_w;
-wire          litedramcore_bankmachine2_do_read;
-wire    [3:0] litedramcore_bankmachine2_rdport_adr;
-wire   [25:0] litedramcore_bankmachine2_rdport_dat_r;
-wire          litedramcore_bankmachine2_fifo_in_payload_we;
-wire   [22:0] litedramcore_bankmachine2_fifo_in_payload_addr;
-wire          litedramcore_bankmachine2_fifo_in_first;
-wire          litedramcore_bankmachine2_fifo_in_last;
-wire          litedramcore_bankmachine2_fifo_out_payload_we;
-wire   [22:0] litedramcore_bankmachine2_fifo_out_payload_addr;
-wire          litedramcore_bankmachine2_fifo_out_first;
-wire          litedramcore_bankmachine2_fifo_out_last;
-wire          litedramcore_bankmachine2_sink_sink_valid;
-wire          litedramcore_bankmachine2_sink_sink_ready;
-wire          litedramcore_bankmachine2_sink_sink_first;
-wire          litedramcore_bankmachine2_sink_sink_last;
-wire          litedramcore_bankmachine2_sink_sink_payload_we;
-wire   [22:0] litedramcore_bankmachine2_sink_sink_payload_addr;
-wire          litedramcore_bankmachine2_source_source_valid;
-wire          litedramcore_bankmachine2_source_source_ready;
-wire          litedramcore_bankmachine2_source_source_first;
-wire          litedramcore_bankmachine2_source_source_last;
-wire          litedramcore_bankmachine2_source_source_payload_we;
-wire   [22:0] litedramcore_bankmachine2_source_source_payload_addr;
-wire          litedramcore_bankmachine2_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine2_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine2_pipe_valid_sink_first;
-wire          litedramcore_bankmachine2_pipe_valid_sink_last;
-wire          litedramcore_bankmachine2_pipe_valid_sink_payload_we;
-wire   [22:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine2_pipe_valid_source_ready;
-reg           litedramcore_bankmachine2_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine2_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0;
-reg    [22:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 23'd0;
-reg    [15:0] litedramcore_bankmachine2_row = 16'd0;
-reg           litedramcore_bankmachine2_row_opened = 1'd0;
-wire          litedramcore_bankmachine2_row_hit;
-reg           litedramcore_bankmachine2_row_open = 1'd0;
-reg           litedramcore_bankmachine2_row_close = 1'd0;
-reg           litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine2_twtpcon_valid;
+reg           main_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine1_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine1_wrport_adr = 4'd0;
+wire   [25:0] main_litedramcore_bankmachine1_wrport_dat_r;
+wire   [25:0] main_litedramcore_bankmachine1_wrport_dat_w;
+wire          main_litedramcore_bankmachine1_wrport_we;
+reg           main_litedramcore_bankmachine2_auto_precharge = 1'd0;
+reg    [15:0] main_litedramcore_bankmachine2_cmd_payload_a = 16'd0;
+wire    [2:0] main_litedramcore_bankmachine2_cmd_payload_ba;
+reg           main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine2_consume = 4'd0;
+wire          main_litedramcore_bankmachine2_do_read;
+wire          main_litedramcore_bankmachine2_fifo_in_first;
+wire          main_litedramcore_bankmachine2_fifo_in_last;
+wire   [22:0] main_litedramcore_bankmachine2_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine2_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine2_fifo_out_first;
+wire          main_litedramcore_bankmachine2_fifo_out_last;
+wire   [22:0] main_litedramcore_bankmachine2_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine2_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine2_level = 5'd0;
+wire          main_litedramcore_bankmachine2_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine2_pipe_valid_sink_last;
+wire   [22:0] main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine2_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine2_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine2_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine2_pipe_valid_source_last = 1'd0;
+reg    [22:0] main_litedramcore_bankmachine2_pipe_valid_source_payload_addr = 23'd0;
+reg           main_litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine2_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine2_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine2_rdport_adr;
+wire   [25:0] main_litedramcore_bankmachine2_rdport_dat_r;
+reg           main_litedramcore_bankmachine2_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine2_refresh_req;
+reg           main_litedramcore_bankmachine2_replace = 1'd0;
+wire   [22:0] main_litedramcore_bankmachine2_req_addr;
+wire          main_litedramcore_bankmachine2_req_lock;
+reg           main_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine2_req_ready;
+wire          main_litedramcore_bankmachine2_req_valid;
+reg           main_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine2_req_we;
+reg    [15:0] main_litedramcore_bankmachine2_row = 16'd0;
+reg           main_litedramcore_bankmachine2_row_close = 1'd0;
+reg           main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine2_row_hit;
+reg           main_litedramcore_bankmachine2_row_open = 1'd0;
+reg           main_litedramcore_bankmachine2_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine2_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine2_sink_last = 1'd0;
+wire   [22:0] main_litedramcore_bankmachine2_sink_payload_addr;
+wire          main_litedramcore_bankmachine2_sink_payload_we;
+wire          main_litedramcore_bankmachine2_sink_ready;
+wire          main_litedramcore_bankmachine2_sink_sink_first;
+wire          main_litedramcore_bankmachine2_sink_sink_last;
+wire   [22:0] main_litedramcore_bankmachine2_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine2_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine2_sink_sink_ready;
+wire          main_litedramcore_bankmachine2_sink_sink_valid;
+wire          main_litedramcore_bankmachine2_sink_valid;
+wire          main_litedramcore_bankmachine2_source_first;
+wire          main_litedramcore_bankmachine2_source_last;
+wire   [22:0] main_litedramcore_bankmachine2_source_payload_addr;
+wire          main_litedramcore_bankmachine2_source_payload_we;
+wire          main_litedramcore_bankmachine2_source_ready;
+wire          main_litedramcore_bankmachine2_source_source_first;
+wire          main_litedramcore_bankmachine2_source_source_last;
+wire   [22:0] main_litedramcore_bankmachine2_source_source_payload_addr;
+wire          main_litedramcore_bankmachine2_source_source_payload_we;
+wire          main_litedramcore_bankmachine2_source_source_ready;
+wire          main_litedramcore_bankmachine2_source_source_valid;
+wire          main_litedramcore_bankmachine2_source_valid;
+wire   [25:0] main_litedramcore_bankmachine2_syncfifo2_din;
+wire   [25:0] main_litedramcore_bankmachine2_syncfifo2_dout;
+wire          main_litedramcore_bankmachine2_syncfifo2_re;
+wire          main_litedramcore_bankmachine2_syncfifo2_readable;
+wire          main_litedramcore_bankmachine2_syncfifo2_we;
+wire          main_litedramcore_bankmachine2_syncfifo2_writable;
+reg     [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine2_trccon_valid;
+reg           main_litedramcore_bankmachine2_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine2_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
-wire          litedramcore_bankmachine2_trascon_valid;
+reg           main_litedramcore_bankmachine2_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine2_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine2_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
-wire          litedramcore_bankmachine3_req_valid;
-wire          litedramcore_bankmachine3_req_ready;
-wire          litedramcore_bankmachine3_req_we;
-wire   [22:0] litedramcore_bankmachine3_req_addr;
-wire          litedramcore_bankmachine3_req_lock;
-reg           litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine3_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine3_refresh_req;
-reg           litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine3_cmd_ready = 1'd0;
-reg    [15:0] litedramcore_bankmachine3_cmd_payload_a = 16'd0;
-wire    [2:0] litedramcore_bankmachine3_cmd_payload_ba;
-reg           litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine3_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine3_sink_valid;
-wire          litedramcore_bankmachine3_sink_ready;
-reg           litedramcore_bankmachine3_sink_first = 1'd0;
-reg           litedramcore_bankmachine3_sink_last = 1'd0;
-wire          litedramcore_bankmachine3_sink_payload_we;
-wire   [22:0] litedramcore_bankmachine3_sink_payload_addr;
-wire          litedramcore_bankmachine3_source_valid;
-wire          litedramcore_bankmachine3_source_ready;
-wire          litedramcore_bankmachine3_source_first;
-wire          litedramcore_bankmachine3_source_last;
-wire          litedramcore_bankmachine3_source_payload_we;
-wire   [22:0] litedramcore_bankmachine3_source_payload_addr;
-wire          litedramcore_bankmachine3_syncfifo3_we;
-wire          litedramcore_bankmachine3_syncfifo3_writable;
-wire          litedramcore_bankmachine3_syncfifo3_re;
-wire          litedramcore_bankmachine3_syncfifo3_readable;
-wire   [25:0] litedramcore_bankmachine3_syncfifo3_din;
-wire   [25:0] litedramcore_bankmachine3_syncfifo3_dout;
-reg     [4:0] litedramcore_bankmachine3_level = 5'd0;
-reg           litedramcore_bankmachine3_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine3_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine3_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0;
-wire   [25:0] litedramcore_bankmachine3_wrport_dat_r;
-wire          litedramcore_bankmachine3_wrport_we;
-wire   [25:0] litedramcore_bankmachine3_wrport_dat_w;
-wire          litedramcore_bankmachine3_do_read;
-wire    [3:0] litedramcore_bankmachine3_rdport_adr;
-wire   [25:0] litedramcore_bankmachine3_rdport_dat_r;
-wire          litedramcore_bankmachine3_fifo_in_payload_we;
-wire   [22:0] litedramcore_bankmachine3_fifo_in_payload_addr;
-wire          litedramcore_bankmachine3_fifo_in_first;
-wire          litedramcore_bankmachine3_fifo_in_last;
-wire          litedramcore_bankmachine3_fifo_out_payload_we;
-wire   [22:0] litedramcore_bankmachine3_fifo_out_payload_addr;
-wire          litedramcore_bankmachine3_fifo_out_first;
-wire          litedramcore_bankmachine3_fifo_out_last;
-wire          litedramcore_bankmachine3_sink_sink_valid;
-wire          litedramcore_bankmachine3_sink_sink_ready;
-wire          litedramcore_bankmachine3_sink_sink_first;
-wire          litedramcore_bankmachine3_sink_sink_last;
-wire          litedramcore_bankmachine3_sink_sink_payload_we;
-wire   [22:0] litedramcore_bankmachine3_sink_sink_payload_addr;
-wire          litedramcore_bankmachine3_source_source_valid;
-wire          litedramcore_bankmachine3_source_source_ready;
-wire          litedramcore_bankmachine3_source_source_first;
-wire          litedramcore_bankmachine3_source_source_last;
-wire          litedramcore_bankmachine3_source_source_payload_we;
-wire   [22:0] litedramcore_bankmachine3_source_source_payload_addr;
-wire          litedramcore_bankmachine3_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine3_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine3_pipe_valid_sink_first;
-wire          litedramcore_bankmachine3_pipe_valid_sink_last;
-wire          litedramcore_bankmachine3_pipe_valid_sink_payload_we;
-wire   [22:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine3_pipe_valid_source_ready;
-reg           litedramcore_bankmachine3_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine3_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0;
-reg    [22:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 23'd0;
-reg    [15:0] litedramcore_bankmachine3_row = 16'd0;
-reg           litedramcore_bankmachine3_row_opened = 1'd0;
-wire          litedramcore_bankmachine3_row_hit;
-reg           litedramcore_bankmachine3_row_open = 1'd0;
-reg           litedramcore_bankmachine3_row_close = 1'd0;
-reg           litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine3_twtpcon_valid;
+reg           main_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine2_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine2_wrport_adr = 4'd0;
+wire   [25:0] main_litedramcore_bankmachine2_wrport_dat_r;
+wire   [25:0] main_litedramcore_bankmachine2_wrport_dat_w;
+wire          main_litedramcore_bankmachine2_wrport_we;
+reg           main_litedramcore_bankmachine3_auto_precharge = 1'd0;
+reg    [15:0] main_litedramcore_bankmachine3_cmd_payload_a = 16'd0;
+wire    [2:0] main_litedramcore_bankmachine3_cmd_payload_ba;
+reg           main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine3_consume = 4'd0;
+wire          main_litedramcore_bankmachine3_do_read;
+wire          main_litedramcore_bankmachine3_fifo_in_first;
+wire          main_litedramcore_bankmachine3_fifo_in_last;
+wire   [22:0] main_litedramcore_bankmachine3_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine3_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine3_fifo_out_first;
+wire          main_litedramcore_bankmachine3_fifo_out_last;
+wire   [22:0] main_litedramcore_bankmachine3_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine3_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine3_level = 5'd0;
+wire          main_litedramcore_bankmachine3_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine3_pipe_valid_sink_last;
+wire   [22:0] main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine3_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine3_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine3_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine3_pipe_valid_source_last = 1'd0;
+reg    [22:0] main_litedramcore_bankmachine3_pipe_valid_source_payload_addr = 23'd0;
+reg           main_litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine3_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine3_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine3_rdport_adr;
+wire   [25:0] main_litedramcore_bankmachine3_rdport_dat_r;
+reg           main_litedramcore_bankmachine3_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine3_refresh_req;
+reg           main_litedramcore_bankmachine3_replace = 1'd0;
+wire   [22:0] main_litedramcore_bankmachine3_req_addr;
+wire          main_litedramcore_bankmachine3_req_lock;
+reg           main_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine3_req_ready;
+wire          main_litedramcore_bankmachine3_req_valid;
+reg           main_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine3_req_we;
+reg    [15:0] main_litedramcore_bankmachine3_row = 16'd0;
+reg           main_litedramcore_bankmachine3_row_close = 1'd0;
+reg           main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine3_row_hit;
+reg           main_litedramcore_bankmachine3_row_open = 1'd0;
+reg           main_litedramcore_bankmachine3_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine3_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine3_sink_last = 1'd0;
+wire   [22:0] main_litedramcore_bankmachine3_sink_payload_addr;
+wire          main_litedramcore_bankmachine3_sink_payload_we;
+wire          main_litedramcore_bankmachine3_sink_ready;
+wire          main_litedramcore_bankmachine3_sink_sink_first;
+wire          main_litedramcore_bankmachine3_sink_sink_last;
+wire   [22:0] main_litedramcore_bankmachine3_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine3_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine3_sink_sink_ready;
+wire          main_litedramcore_bankmachine3_sink_sink_valid;
+wire          main_litedramcore_bankmachine3_sink_valid;
+wire          main_litedramcore_bankmachine3_source_first;
+wire          main_litedramcore_bankmachine3_source_last;
+wire   [22:0] main_litedramcore_bankmachine3_source_payload_addr;
+wire          main_litedramcore_bankmachine3_source_payload_we;
+wire          main_litedramcore_bankmachine3_source_ready;
+wire          main_litedramcore_bankmachine3_source_source_first;
+wire          main_litedramcore_bankmachine3_source_source_last;
+wire   [22:0] main_litedramcore_bankmachine3_source_source_payload_addr;
+wire          main_litedramcore_bankmachine3_source_source_payload_we;
+wire          main_litedramcore_bankmachine3_source_source_ready;
+wire          main_litedramcore_bankmachine3_source_source_valid;
+wire          main_litedramcore_bankmachine3_source_valid;
+wire   [25:0] main_litedramcore_bankmachine3_syncfifo3_din;
+wire   [25:0] main_litedramcore_bankmachine3_syncfifo3_dout;
+wire          main_litedramcore_bankmachine3_syncfifo3_re;
+wire          main_litedramcore_bankmachine3_syncfifo3_readable;
+wire          main_litedramcore_bankmachine3_syncfifo3_we;
+wire          main_litedramcore_bankmachine3_syncfifo3_writable;
+reg     [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine3_trccon_valid;
+reg           main_litedramcore_bankmachine3_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine3_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
-wire          litedramcore_bankmachine3_trascon_valid;
+reg           main_litedramcore_bankmachine3_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine3_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine3_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
-wire          litedramcore_bankmachine4_req_valid;
-wire          litedramcore_bankmachine4_req_ready;
-wire          litedramcore_bankmachine4_req_we;
-wire   [22:0] litedramcore_bankmachine4_req_addr;
-wire          litedramcore_bankmachine4_req_lock;
-reg           litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine4_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine4_refresh_req;
-reg           litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine4_cmd_ready = 1'd0;
-reg    [15:0] litedramcore_bankmachine4_cmd_payload_a = 16'd0;
-wire    [2:0] litedramcore_bankmachine4_cmd_payload_ba;
-reg           litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine4_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine4_sink_valid;
-wire          litedramcore_bankmachine4_sink_ready;
-reg           litedramcore_bankmachine4_sink_first = 1'd0;
-reg           litedramcore_bankmachine4_sink_last = 1'd0;
-wire          litedramcore_bankmachine4_sink_payload_we;
-wire   [22:0] litedramcore_bankmachine4_sink_payload_addr;
-wire          litedramcore_bankmachine4_source_valid;
-wire          litedramcore_bankmachine4_source_ready;
-wire          litedramcore_bankmachine4_source_first;
-wire          litedramcore_bankmachine4_source_last;
-wire          litedramcore_bankmachine4_source_payload_we;
-wire   [22:0] litedramcore_bankmachine4_source_payload_addr;
-wire          litedramcore_bankmachine4_syncfifo4_we;
-wire          litedramcore_bankmachine4_syncfifo4_writable;
-wire          litedramcore_bankmachine4_syncfifo4_re;
-wire          litedramcore_bankmachine4_syncfifo4_readable;
-wire   [25:0] litedramcore_bankmachine4_syncfifo4_din;
-wire   [25:0] litedramcore_bankmachine4_syncfifo4_dout;
-reg     [4:0] litedramcore_bankmachine4_level = 5'd0;
-reg           litedramcore_bankmachine4_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine4_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine4_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0;
-wire   [25:0] litedramcore_bankmachine4_wrport_dat_r;
-wire          litedramcore_bankmachine4_wrport_we;
-wire   [25:0] litedramcore_bankmachine4_wrport_dat_w;
-wire          litedramcore_bankmachine4_do_read;
-wire    [3:0] litedramcore_bankmachine4_rdport_adr;
-wire   [25:0] litedramcore_bankmachine4_rdport_dat_r;
-wire          litedramcore_bankmachine4_fifo_in_payload_we;
-wire   [22:0] litedramcore_bankmachine4_fifo_in_payload_addr;
-wire          litedramcore_bankmachine4_fifo_in_first;
-wire          litedramcore_bankmachine4_fifo_in_last;
-wire          litedramcore_bankmachine4_fifo_out_payload_we;
-wire   [22:0] litedramcore_bankmachine4_fifo_out_payload_addr;
-wire          litedramcore_bankmachine4_fifo_out_first;
-wire          litedramcore_bankmachine4_fifo_out_last;
-wire          litedramcore_bankmachine4_sink_sink_valid;
-wire          litedramcore_bankmachine4_sink_sink_ready;
-wire          litedramcore_bankmachine4_sink_sink_first;
-wire          litedramcore_bankmachine4_sink_sink_last;
-wire          litedramcore_bankmachine4_sink_sink_payload_we;
-wire   [22:0] litedramcore_bankmachine4_sink_sink_payload_addr;
-wire          litedramcore_bankmachine4_source_source_valid;
-wire          litedramcore_bankmachine4_source_source_ready;
-wire          litedramcore_bankmachine4_source_source_first;
-wire          litedramcore_bankmachine4_source_source_last;
-wire          litedramcore_bankmachine4_source_source_payload_we;
-wire   [22:0] litedramcore_bankmachine4_source_source_payload_addr;
-wire          litedramcore_bankmachine4_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine4_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine4_pipe_valid_sink_first;
-wire          litedramcore_bankmachine4_pipe_valid_sink_last;
-wire          litedramcore_bankmachine4_pipe_valid_sink_payload_we;
-wire   [22:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine4_pipe_valid_source_ready;
-reg           litedramcore_bankmachine4_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine4_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0;
-reg    [22:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 23'd0;
-reg    [15:0] litedramcore_bankmachine4_row = 16'd0;
-reg           litedramcore_bankmachine4_row_opened = 1'd0;
-wire          litedramcore_bankmachine4_row_hit;
-reg           litedramcore_bankmachine4_row_open = 1'd0;
-reg           litedramcore_bankmachine4_row_close = 1'd0;
-reg           litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine4_twtpcon_valid;
+reg           main_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine3_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine3_wrport_adr = 4'd0;
+wire   [25:0] main_litedramcore_bankmachine3_wrport_dat_r;
+wire   [25:0] main_litedramcore_bankmachine3_wrport_dat_w;
+wire          main_litedramcore_bankmachine3_wrport_we;
+reg           main_litedramcore_bankmachine4_auto_precharge = 1'd0;
+reg    [15:0] main_litedramcore_bankmachine4_cmd_payload_a = 16'd0;
+wire    [2:0] main_litedramcore_bankmachine4_cmd_payload_ba;
+reg           main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine4_consume = 4'd0;
+wire          main_litedramcore_bankmachine4_do_read;
+wire          main_litedramcore_bankmachine4_fifo_in_first;
+wire          main_litedramcore_bankmachine4_fifo_in_last;
+wire   [22:0] main_litedramcore_bankmachine4_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine4_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine4_fifo_out_first;
+wire          main_litedramcore_bankmachine4_fifo_out_last;
+wire   [22:0] main_litedramcore_bankmachine4_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine4_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine4_level = 5'd0;
+wire          main_litedramcore_bankmachine4_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine4_pipe_valid_sink_last;
+wire   [22:0] main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine4_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine4_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine4_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine4_pipe_valid_source_last = 1'd0;
+reg    [22:0] main_litedramcore_bankmachine4_pipe_valid_source_payload_addr = 23'd0;
+reg           main_litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine4_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine4_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine4_rdport_adr;
+wire   [25:0] main_litedramcore_bankmachine4_rdport_dat_r;
+reg           main_litedramcore_bankmachine4_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine4_refresh_req;
+reg           main_litedramcore_bankmachine4_replace = 1'd0;
+wire   [22:0] main_litedramcore_bankmachine4_req_addr;
+wire          main_litedramcore_bankmachine4_req_lock;
+reg           main_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine4_req_ready;
+wire          main_litedramcore_bankmachine4_req_valid;
+reg           main_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine4_req_we;
+reg    [15:0] main_litedramcore_bankmachine4_row = 16'd0;
+reg           main_litedramcore_bankmachine4_row_close = 1'd0;
+reg           main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine4_row_hit;
+reg           main_litedramcore_bankmachine4_row_open = 1'd0;
+reg           main_litedramcore_bankmachine4_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine4_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine4_sink_last = 1'd0;
+wire   [22:0] main_litedramcore_bankmachine4_sink_payload_addr;
+wire          main_litedramcore_bankmachine4_sink_payload_we;
+wire          main_litedramcore_bankmachine4_sink_ready;
+wire          main_litedramcore_bankmachine4_sink_sink_first;
+wire          main_litedramcore_bankmachine4_sink_sink_last;
+wire   [22:0] main_litedramcore_bankmachine4_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine4_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine4_sink_sink_ready;
+wire          main_litedramcore_bankmachine4_sink_sink_valid;
+wire          main_litedramcore_bankmachine4_sink_valid;
+wire          main_litedramcore_bankmachine4_source_first;
+wire          main_litedramcore_bankmachine4_source_last;
+wire   [22:0] main_litedramcore_bankmachine4_source_payload_addr;
+wire          main_litedramcore_bankmachine4_source_payload_we;
+wire          main_litedramcore_bankmachine4_source_ready;
+wire          main_litedramcore_bankmachine4_source_source_first;
+wire          main_litedramcore_bankmachine4_source_source_last;
+wire   [22:0] main_litedramcore_bankmachine4_source_source_payload_addr;
+wire          main_litedramcore_bankmachine4_source_source_payload_we;
+wire          main_litedramcore_bankmachine4_source_source_ready;
+wire          main_litedramcore_bankmachine4_source_source_valid;
+wire          main_litedramcore_bankmachine4_source_valid;
+wire   [25:0] main_litedramcore_bankmachine4_syncfifo4_din;
+wire   [25:0] main_litedramcore_bankmachine4_syncfifo4_dout;
+wire          main_litedramcore_bankmachine4_syncfifo4_re;
+wire          main_litedramcore_bankmachine4_syncfifo4_readable;
+wire          main_litedramcore_bankmachine4_syncfifo4_we;
+wire          main_litedramcore_bankmachine4_syncfifo4_writable;
+reg     [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine4_trccon_valid;
+reg           main_litedramcore_bankmachine4_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine4_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
-wire          litedramcore_bankmachine4_trascon_valid;
+reg           main_litedramcore_bankmachine4_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine4_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine4_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
-wire          litedramcore_bankmachine5_req_valid;
-wire          litedramcore_bankmachine5_req_ready;
-wire          litedramcore_bankmachine5_req_we;
-wire   [22:0] litedramcore_bankmachine5_req_addr;
-wire          litedramcore_bankmachine5_req_lock;
-reg           litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine5_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine5_refresh_req;
-reg           litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine5_cmd_ready = 1'd0;
-reg    [15:0] litedramcore_bankmachine5_cmd_payload_a = 16'd0;
-wire    [2:0] litedramcore_bankmachine5_cmd_payload_ba;
-reg           litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine5_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine5_sink_valid;
-wire          litedramcore_bankmachine5_sink_ready;
-reg           litedramcore_bankmachine5_sink_first = 1'd0;
-reg           litedramcore_bankmachine5_sink_last = 1'd0;
-wire          litedramcore_bankmachine5_sink_payload_we;
-wire   [22:0] litedramcore_bankmachine5_sink_payload_addr;
-wire          litedramcore_bankmachine5_source_valid;
-wire          litedramcore_bankmachine5_source_ready;
-wire          litedramcore_bankmachine5_source_first;
-wire          litedramcore_bankmachine5_source_last;
-wire          litedramcore_bankmachine5_source_payload_we;
-wire   [22:0] litedramcore_bankmachine5_source_payload_addr;
-wire          litedramcore_bankmachine5_syncfifo5_we;
-wire          litedramcore_bankmachine5_syncfifo5_writable;
-wire          litedramcore_bankmachine5_syncfifo5_re;
-wire          litedramcore_bankmachine5_syncfifo5_readable;
-wire   [25:0] litedramcore_bankmachine5_syncfifo5_din;
-wire   [25:0] litedramcore_bankmachine5_syncfifo5_dout;
-reg     [4:0] litedramcore_bankmachine5_level = 5'd0;
-reg           litedramcore_bankmachine5_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine5_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine5_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0;
-wire   [25:0] litedramcore_bankmachine5_wrport_dat_r;
-wire          litedramcore_bankmachine5_wrport_we;
-wire   [25:0] litedramcore_bankmachine5_wrport_dat_w;
-wire          litedramcore_bankmachine5_do_read;
-wire    [3:0] litedramcore_bankmachine5_rdport_adr;
-wire   [25:0] litedramcore_bankmachine5_rdport_dat_r;
-wire          litedramcore_bankmachine5_fifo_in_payload_we;
-wire   [22:0] litedramcore_bankmachine5_fifo_in_payload_addr;
-wire          litedramcore_bankmachine5_fifo_in_first;
-wire          litedramcore_bankmachine5_fifo_in_last;
-wire          litedramcore_bankmachine5_fifo_out_payload_we;
-wire   [22:0] litedramcore_bankmachine5_fifo_out_payload_addr;
-wire          litedramcore_bankmachine5_fifo_out_first;
-wire          litedramcore_bankmachine5_fifo_out_last;
-wire          litedramcore_bankmachine5_sink_sink_valid;
-wire          litedramcore_bankmachine5_sink_sink_ready;
-wire          litedramcore_bankmachine5_sink_sink_first;
-wire          litedramcore_bankmachine5_sink_sink_last;
-wire          litedramcore_bankmachine5_sink_sink_payload_we;
-wire   [22:0] litedramcore_bankmachine5_sink_sink_payload_addr;
-wire          litedramcore_bankmachine5_source_source_valid;
-wire          litedramcore_bankmachine5_source_source_ready;
-wire          litedramcore_bankmachine5_source_source_first;
-wire          litedramcore_bankmachine5_source_source_last;
-wire          litedramcore_bankmachine5_source_source_payload_we;
-wire   [22:0] litedramcore_bankmachine5_source_source_payload_addr;
-wire          litedramcore_bankmachine5_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine5_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine5_pipe_valid_sink_first;
-wire          litedramcore_bankmachine5_pipe_valid_sink_last;
-wire          litedramcore_bankmachine5_pipe_valid_sink_payload_we;
-wire   [22:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine5_pipe_valid_source_ready;
-reg           litedramcore_bankmachine5_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine5_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0;
-reg    [22:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 23'd0;
-reg    [15:0] litedramcore_bankmachine5_row = 16'd0;
-reg           litedramcore_bankmachine5_row_opened = 1'd0;
-wire          litedramcore_bankmachine5_row_hit;
-reg           litedramcore_bankmachine5_row_open = 1'd0;
-reg           litedramcore_bankmachine5_row_close = 1'd0;
-reg           litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine5_twtpcon_valid;
+reg           main_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine4_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine4_wrport_adr = 4'd0;
+wire   [25:0] main_litedramcore_bankmachine4_wrport_dat_r;
+wire   [25:0] main_litedramcore_bankmachine4_wrport_dat_w;
+wire          main_litedramcore_bankmachine4_wrport_we;
+reg           main_litedramcore_bankmachine5_auto_precharge = 1'd0;
+reg    [15:0] main_litedramcore_bankmachine5_cmd_payload_a = 16'd0;
+wire    [2:0] main_litedramcore_bankmachine5_cmd_payload_ba;
+reg           main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine5_consume = 4'd0;
+wire          main_litedramcore_bankmachine5_do_read;
+wire          main_litedramcore_bankmachine5_fifo_in_first;
+wire          main_litedramcore_bankmachine5_fifo_in_last;
+wire   [22:0] main_litedramcore_bankmachine5_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine5_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine5_fifo_out_first;
+wire          main_litedramcore_bankmachine5_fifo_out_last;
+wire   [22:0] main_litedramcore_bankmachine5_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine5_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine5_level = 5'd0;
+wire          main_litedramcore_bankmachine5_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine5_pipe_valid_sink_last;
+wire   [22:0] main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine5_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine5_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine5_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine5_pipe_valid_source_last = 1'd0;
+reg    [22:0] main_litedramcore_bankmachine5_pipe_valid_source_payload_addr = 23'd0;
+reg           main_litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine5_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine5_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine5_rdport_adr;
+wire   [25:0] main_litedramcore_bankmachine5_rdport_dat_r;
+reg           main_litedramcore_bankmachine5_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine5_refresh_req;
+reg           main_litedramcore_bankmachine5_replace = 1'd0;
+wire   [22:0] main_litedramcore_bankmachine5_req_addr;
+wire          main_litedramcore_bankmachine5_req_lock;
+reg           main_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine5_req_ready;
+wire          main_litedramcore_bankmachine5_req_valid;
+reg           main_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine5_req_we;
+reg    [15:0] main_litedramcore_bankmachine5_row = 16'd0;
+reg           main_litedramcore_bankmachine5_row_close = 1'd0;
+reg           main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine5_row_hit;
+reg           main_litedramcore_bankmachine5_row_open = 1'd0;
+reg           main_litedramcore_bankmachine5_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine5_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine5_sink_last = 1'd0;
+wire   [22:0] main_litedramcore_bankmachine5_sink_payload_addr;
+wire          main_litedramcore_bankmachine5_sink_payload_we;
+wire          main_litedramcore_bankmachine5_sink_ready;
+wire          main_litedramcore_bankmachine5_sink_sink_first;
+wire          main_litedramcore_bankmachine5_sink_sink_last;
+wire   [22:0] main_litedramcore_bankmachine5_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine5_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine5_sink_sink_ready;
+wire          main_litedramcore_bankmachine5_sink_sink_valid;
+wire          main_litedramcore_bankmachine5_sink_valid;
+wire          main_litedramcore_bankmachine5_source_first;
+wire          main_litedramcore_bankmachine5_source_last;
+wire   [22:0] main_litedramcore_bankmachine5_source_payload_addr;
+wire          main_litedramcore_bankmachine5_source_payload_we;
+wire          main_litedramcore_bankmachine5_source_ready;
+wire          main_litedramcore_bankmachine5_source_source_first;
+wire          main_litedramcore_bankmachine5_source_source_last;
+wire   [22:0] main_litedramcore_bankmachine5_source_source_payload_addr;
+wire          main_litedramcore_bankmachine5_source_source_payload_we;
+wire          main_litedramcore_bankmachine5_source_source_ready;
+wire          main_litedramcore_bankmachine5_source_source_valid;
+wire          main_litedramcore_bankmachine5_source_valid;
+wire   [25:0] main_litedramcore_bankmachine5_syncfifo5_din;
+wire   [25:0] main_litedramcore_bankmachine5_syncfifo5_dout;
+wire          main_litedramcore_bankmachine5_syncfifo5_re;
+wire          main_litedramcore_bankmachine5_syncfifo5_readable;
+wire          main_litedramcore_bankmachine5_syncfifo5_we;
+wire          main_litedramcore_bankmachine5_syncfifo5_writable;
+reg     [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine5_trccon_valid;
+reg           main_litedramcore_bankmachine5_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine5_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
-wire          litedramcore_bankmachine5_trascon_valid;
+reg           main_litedramcore_bankmachine5_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine5_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine5_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
-wire          litedramcore_bankmachine6_req_valid;
-wire          litedramcore_bankmachine6_req_ready;
-wire          litedramcore_bankmachine6_req_we;
-wire   [22:0] litedramcore_bankmachine6_req_addr;
-wire          litedramcore_bankmachine6_req_lock;
-reg           litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine6_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine6_refresh_req;
-reg           litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine6_cmd_ready = 1'd0;
-reg    [15:0] litedramcore_bankmachine6_cmd_payload_a = 16'd0;
-wire    [2:0] litedramcore_bankmachine6_cmd_payload_ba;
-reg           litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine6_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine6_sink_valid;
-wire          litedramcore_bankmachine6_sink_ready;
-reg           litedramcore_bankmachine6_sink_first = 1'd0;
-reg           litedramcore_bankmachine6_sink_last = 1'd0;
-wire          litedramcore_bankmachine6_sink_payload_we;
-wire   [22:0] litedramcore_bankmachine6_sink_payload_addr;
-wire          litedramcore_bankmachine6_source_valid;
-wire          litedramcore_bankmachine6_source_ready;
-wire          litedramcore_bankmachine6_source_first;
-wire          litedramcore_bankmachine6_source_last;
-wire          litedramcore_bankmachine6_source_payload_we;
-wire   [22:0] litedramcore_bankmachine6_source_payload_addr;
-wire          litedramcore_bankmachine6_syncfifo6_we;
-wire          litedramcore_bankmachine6_syncfifo6_writable;
-wire          litedramcore_bankmachine6_syncfifo6_re;
-wire          litedramcore_bankmachine6_syncfifo6_readable;
-wire   [25:0] litedramcore_bankmachine6_syncfifo6_din;
-wire   [25:0] litedramcore_bankmachine6_syncfifo6_dout;
-reg     [4:0] litedramcore_bankmachine6_level = 5'd0;
-reg           litedramcore_bankmachine6_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine6_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine6_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0;
-wire   [25:0] litedramcore_bankmachine6_wrport_dat_r;
-wire          litedramcore_bankmachine6_wrport_we;
-wire   [25:0] litedramcore_bankmachine6_wrport_dat_w;
-wire          litedramcore_bankmachine6_do_read;
-wire    [3:0] litedramcore_bankmachine6_rdport_adr;
-wire   [25:0] litedramcore_bankmachine6_rdport_dat_r;
-wire          litedramcore_bankmachine6_fifo_in_payload_we;
-wire   [22:0] litedramcore_bankmachine6_fifo_in_payload_addr;
-wire          litedramcore_bankmachine6_fifo_in_first;
-wire          litedramcore_bankmachine6_fifo_in_last;
-wire          litedramcore_bankmachine6_fifo_out_payload_we;
-wire   [22:0] litedramcore_bankmachine6_fifo_out_payload_addr;
-wire          litedramcore_bankmachine6_fifo_out_first;
-wire          litedramcore_bankmachine6_fifo_out_last;
-wire          litedramcore_bankmachine6_sink_sink_valid;
-wire          litedramcore_bankmachine6_sink_sink_ready;
-wire          litedramcore_bankmachine6_sink_sink_first;
-wire          litedramcore_bankmachine6_sink_sink_last;
-wire          litedramcore_bankmachine6_sink_sink_payload_we;
-wire   [22:0] litedramcore_bankmachine6_sink_sink_payload_addr;
-wire          litedramcore_bankmachine6_source_source_valid;
-wire          litedramcore_bankmachine6_source_source_ready;
-wire          litedramcore_bankmachine6_source_source_first;
-wire          litedramcore_bankmachine6_source_source_last;
-wire          litedramcore_bankmachine6_source_source_payload_we;
-wire   [22:0] litedramcore_bankmachine6_source_source_payload_addr;
-wire          litedramcore_bankmachine6_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine6_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine6_pipe_valid_sink_first;
-wire          litedramcore_bankmachine6_pipe_valid_sink_last;
-wire          litedramcore_bankmachine6_pipe_valid_sink_payload_we;
-wire   [22:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine6_pipe_valid_source_ready;
-reg           litedramcore_bankmachine6_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine6_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0;
-reg    [22:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 23'd0;
-reg    [15:0] litedramcore_bankmachine6_row = 16'd0;
-reg           litedramcore_bankmachine6_row_opened = 1'd0;
-wire          litedramcore_bankmachine6_row_hit;
-reg           litedramcore_bankmachine6_row_open = 1'd0;
-reg           litedramcore_bankmachine6_row_close = 1'd0;
-reg           litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine6_twtpcon_valid;
+reg           main_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine5_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine5_wrport_adr = 4'd0;
+wire   [25:0] main_litedramcore_bankmachine5_wrport_dat_r;
+wire   [25:0] main_litedramcore_bankmachine5_wrport_dat_w;
+wire          main_litedramcore_bankmachine5_wrport_we;
+reg           main_litedramcore_bankmachine6_auto_precharge = 1'd0;
+reg    [15:0] main_litedramcore_bankmachine6_cmd_payload_a = 16'd0;
+wire    [2:0] main_litedramcore_bankmachine6_cmd_payload_ba;
+reg           main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine6_consume = 4'd0;
+wire          main_litedramcore_bankmachine6_do_read;
+wire          main_litedramcore_bankmachine6_fifo_in_first;
+wire          main_litedramcore_bankmachine6_fifo_in_last;
+wire   [22:0] main_litedramcore_bankmachine6_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine6_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine6_fifo_out_first;
+wire          main_litedramcore_bankmachine6_fifo_out_last;
+wire   [22:0] main_litedramcore_bankmachine6_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine6_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine6_level = 5'd0;
+wire          main_litedramcore_bankmachine6_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine6_pipe_valid_sink_last;
+wire   [22:0] main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine6_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine6_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine6_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine6_pipe_valid_source_last = 1'd0;
+reg    [22:0] main_litedramcore_bankmachine6_pipe_valid_source_payload_addr = 23'd0;
+reg           main_litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine6_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine6_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine6_rdport_adr;
+wire   [25:0] main_litedramcore_bankmachine6_rdport_dat_r;
+reg           main_litedramcore_bankmachine6_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine6_refresh_req;
+reg           main_litedramcore_bankmachine6_replace = 1'd0;
+wire   [22:0] main_litedramcore_bankmachine6_req_addr;
+wire          main_litedramcore_bankmachine6_req_lock;
+reg           main_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine6_req_ready;
+wire          main_litedramcore_bankmachine6_req_valid;
+reg           main_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine6_req_we;
+reg    [15:0] main_litedramcore_bankmachine6_row = 16'd0;
+reg           main_litedramcore_bankmachine6_row_close = 1'd0;
+reg           main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine6_row_hit;
+reg           main_litedramcore_bankmachine6_row_open = 1'd0;
+reg           main_litedramcore_bankmachine6_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine6_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine6_sink_last = 1'd0;
+wire   [22:0] main_litedramcore_bankmachine6_sink_payload_addr;
+wire          main_litedramcore_bankmachine6_sink_payload_we;
+wire          main_litedramcore_bankmachine6_sink_ready;
+wire          main_litedramcore_bankmachine6_sink_sink_first;
+wire          main_litedramcore_bankmachine6_sink_sink_last;
+wire   [22:0] main_litedramcore_bankmachine6_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine6_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine6_sink_sink_ready;
+wire          main_litedramcore_bankmachine6_sink_sink_valid;
+wire          main_litedramcore_bankmachine6_sink_valid;
+wire          main_litedramcore_bankmachine6_source_first;
+wire          main_litedramcore_bankmachine6_source_last;
+wire   [22:0] main_litedramcore_bankmachine6_source_payload_addr;
+wire          main_litedramcore_bankmachine6_source_payload_we;
+wire          main_litedramcore_bankmachine6_source_ready;
+wire          main_litedramcore_bankmachine6_source_source_first;
+wire          main_litedramcore_bankmachine6_source_source_last;
+wire   [22:0] main_litedramcore_bankmachine6_source_source_payload_addr;
+wire          main_litedramcore_bankmachine6_source_source_payload_we;
+wire          main_litedramcore_bankmachine6_source_source_ready;
+wire          main_litedramcore_bankmachine6_source_source_valid;
+wire          main_litedramcore_bankmachine6_source_valid;
+wire   [25:0] main_litedramcore_bankmachine6_syncfifo6_din;
+wire   [25:0] main_litedramcore_bankmachine6_syncfifo6_dout;
+wire          main_litedramcore_bankmachine6_syncfifo6_re;
+wire          main_litedramcore_bankmachine6_syncfifo6_readable;
+wire          main_litedramcore_bankmachine6_syncfifo6_we;
+wire          main_litedramcore_bankmachine6_syncfifo6_writable;
+reg     [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine6_trccon_valid;
+reg           main_litedramcore_bankmachine6_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine6_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
-wire          litedramcore_bankmachine6_trascon_valid;
+reg           main_litedramcore_bankmachine6_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine6_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine6_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
-wire          litedramcore_bankmachine7_req_valid;
-wire          litedramcore_bankmachine7_req_ready;
-wire          litedramcore_bankmachine7_req_we;
-wire   [22:0] litedramcore_bankmachine7_req_addr;
-wire          litedramcore_bankmachine7_req_lock;
-reg           litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine7_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine7_refresh_req;
-reg           litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine7_cmd_ready = 1'd0;
-reg    [15:0] litedramcore_bankmachine7_cmd_payload_a = 16'd0;
-wire    [2:0] litedramcore_bankmachine7_cmd_payload_ba;
-reg           litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine7_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine7_sink_valid;
-wire          litedramcore_bankmachine7_sink_ready;
-reg           litedramcore_bankmachine7_sink_first = 1'd0;
-reg           litedramcore_bankmachine7_sink_last = 1'd0;
-wire          litedramcore_bankmachine7_sink_payload_we;
-wire   [22:0] litedramcore_bankmachine7_sink_payload_addr;
-wire          litedramcore_bankmachine7_source_valid;
-wire          litedramcore_bankmachine7_source_ready;
-wire          litedramcore_bankmachine7_source_first;
-wire          litedramcore_bankmachine7_source_last;
-wire          litedramcore_bankmachine7_source_payload_we;
-wire   [22:0] litedramcore_bankmachine7_source_payload_addr;
-wire          litedramcore_bankmachine7_syncfifo7_we;
-wire          litedramcore_bankmachine7_syncfifo7_writable;
-wire          litedramcore_bankmachine7_syncfifo7_re;
-wire          litedramcore_bankmachine7_syncfifo7_readable;
-wire   [25:0] litedramcore_bankmachine7_syncfifo7_din;
-wire   [25:0] litedramcore_bankmachine7_syncfifo7_dout;
-reg     [4:0] litedramcore_bankmachine7_level = 5'd0;
-reg           litedramcore_bankmachine7_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine7_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine7_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0;
-wire   [25:0] litedramcore_bankmachine7_wrport_dat_r;
-wire          litedramcore_bankmachine7_wrport_we;
-wire   [25:0] litedramcore_bankmachine7_wrport_dat_w;
-wire          litedramcore_bankmachine7_do_read;
-wire    [3:0] litedramcore_bankmachine7_rdport_adr;
-wire   [25:0] litedramcore_bankmachine7_rdport_dat_r;
-wire          litedramcore_bankmachine7_fifo_in_payload_we;
-wire   [22:0] litedramcore_bankmachine7_fifo_in_payload_addr;
-wire          litedramcore_bankmachine7_fifo_in_first;
-wire          litedramcore_bankmachine7_fifo_in_last;
-wire          litedramcore_bankmachine7_fifo_out_payload_we;
-wire   [22:0] litedramcore_bankmachine7_fifo_out_payload_addr;
-wire          litedramcore_bankmachine7_fifo_out_first;
-wire          litedramcore_bankmachine7_fifo_out_last;
-wire          litedramcore_bankmachine7_sink_sink_valid;
-wire          litedramcore_bankmachine7_sink_sink_ready;
-wire          litedramcore_bankmachine7_sink_sink_first;
-wire          litedramcore_bankmachine7_sink_sink_last;
-wire          litedramcore_bankmachine7_sink_sink_payload_we;
-wire   [22:0] litedramcore_bankmachine7_sink_sink_payload_addr;
-wire          litedramcore_bankmachine7_source_source_valid;
-wire          litedramcore_bankmachine7_source_source_ready;
-wire          litedramcore_bankmachine7_source_source_first;
-wire          litedramcore_bankmachine7_source_source_last;
-wire          litedramcore_bankmachine7_source_source_payload_we;
-wire   [22:0] litedramcore_bankmachine7_source_source_payload_addr;
-wire          litedramcore_bankmachine7_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine7_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine7_pipe_valid_sink_first;
-wire          litedramcore_bankmachine7_pipe_valid_sink_last;
-wire          litedramcore_bankmachine7_pipe_valid_sink_payload_we;
-wire   [22:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine7_pipe_valid_source_ready;
-reg           litedramcore_bankmachine7_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine7_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0;
-reg    [22:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 23'd0;
-reg    [15:0] litedramcore_bankmachine7_row = 16'd0;
-reg           litedramcore_bankmachine7_row_opened = 1'd0;
-wire          litedramcore_bankmachine7_row_hit;
-reg           litedramcore_bankmachine7_row_open = 1'd0;
-reg           litedramcore_bankmachine7_row_close = 1'd0;
-reg           litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine7_twtpcon_valid;
+reg           main_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine6_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine6_wrport_adr = 4'd0;
+wire   [25:0] main_litedramcore_bankmachine6_wrport_dat_r;
+wire   [25:0] main_litedramcore_bankmachine6_wrport_dat_w;
+wire          main_litedramcore_bankmachine6_wrport_we;
+reg           main_litedramcore_bankmachine7_auto_precharge = 1'd0;
+reg    [15:0] main_litedramcore_bankmachine7_cmd_payload_a = 16'd0;
+wire    [2:0] main_litedramcore_bankmachine7_cmd_payload_ba;
+reg           main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine7_consume = 4'd0;
+wire          main_litedramcore_bankmachine7_do_read;
+wire          main_litedramcore_bankmachine7_fifo_in_first;
+wire          main_litedramcore_bankmachine7_fifo_in_last;
+wire   [22:0] main_litedramcore_bankmachine7_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine7_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine7_fifo_out_first;
+wire          main_litedramcore_bankmachine7_fifo_out_last;
+wire   [22:0] main_litedramcore_bankmachine7_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine7_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine7_level = 5'd0;
+wire          main_litedramcore_bankmachine7_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine7_pipe_valid_sink_last;
+wire   [22:0] main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine7_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine7_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine7_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine7_pipe_valid_source_last = 1'd0;
+reg    [22:0] main_litedramcore_bankmachine7_pipe_valid_source_payload_addr = 23'd0;
+reg           main_litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine7_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine7_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine7_rdport_adr;
+wire   [25:0] main_litedramcore_bankmachine7_rdport_dat_r;
+reg           main_litedramcore_bankmachine7_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine7_refresh_req;
+reg           main_litedramcore_bankmachine7_replace = 1'd0;
+wire   [22:0] main_litedramcore_bankmachine7_req_addr;
+wire          main_litedramcore_bankmachine7_req_lock;
+reg           main_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine7_req_ready;
+wire          main_litedramcore_bankmachine7_req_valid;
+reg           main_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine7_req_we;
+reg    [15:0] main_litedramcore_bankmachine7_row = 16'd0;
+reg           main_litedramcore_bankmachine7_row_close = 1'd0;
+reg           main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine7_row_hit;
+reg           main_litedramcore_bankmachine7_row_open = 1'd0;
+reg           main_litedramcore_bankmachine7_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine7_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine7_sink_last = 1'd0;
+wire   [22:0] main_litedramcore_bankmachine7_sink_payload_addr;
+wire          main_litedramcore_bankmachine7_sink_payload_we;
+wire          main_litedramcore_bankmachine7_sink_ready;
+wire          main_litedramcore_bankmachine7_sink_sink_first;
+wire          main_litedramcore_bankmachine7_sink_sink_last;
+wire   [22:0] main_litedramcore_bankmachine7_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine7_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine7_sink_sink_ready;
+wire          main_litedramcore_bankmachine7_sink_sink_valid;
+wire          main_litedramcore_bankmachine7_sink_valid;
+wire          main_litedramcore_bankmachine7_source_first;
+wire          main_litedramcore_bankmachine7_source_last;
+wire   [22:0] main_litedramcore_bankmachine7_source_payload_addr;
+wire          main_litedramcore_bankmachine7_source_payload_we;
+wire          main_litedramcore_bankmachine7_source_ready;
+wire          main_litedramcore_bankmachine7_source_source_first;
+wire          main_litedramcore_bankmachine7_source_source_last;
+wire   [22:0] main_litedramcore_bankmachine7_source_source_payload_addr;
+wire          main_litedramcore_bankmachine7_source_source_payload_we;
+wire          main_litedramcore_bankmachine7_source_source_ready;
+wire          main_litedramcore_bankmachine7_source_source_valid;
+wire          main_litedramcore_bankmachine7_source_valid;
+wire   [25:0] main_litedramcore_bankmachine7_syncfifo7_din;
+wire   [25:0] main_litedramcore_bankmachine7_syncfifo7_dout;
+wire          main_litedramcore_bankmachine7_syncfifo7_re;
+wire          main_litedramcore_bankmachine7_syncfifo7_readable;
+wire          main_litedramcore_bankmachine7_syncfifo7_we;
+wire          main_litedramcore_bankmachine7_syncfifo7_writable;
+reg     [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine7_trccon_valid;
+reg           main_litedramcore_bankmachine7_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine7_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
-wire          litedramcore_bankmachine7_trascon_valid;
+reg           main_litedramcore_bankmachine7_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine7_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine7_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
-wire          litedramcore_ras_allowed;
-wire          litedramcore_cas_allowed;
-wire    [1:0] litedramcore_rdcmdphase;
-wire    [1:0] litedramcore_wrcmdphase;
-reg           litedramcore_choose_cmd_want_reads = 1'd0;
-reg           litedramcore_choose_cmd_want_writes = 1'd0;
-reg           litedramcore_choose_cmd_want_cmds = 1'd0;
-reg           litedramcore_choose_cmd_want_activates = 1'd0;
-wire          litedramcore_choose_cmd_cmd_valid;
-reg           litedramcore_choose_cmd_cmd_ready = 1'd0;
-wire   [15:0] litedramcore_choose_cmd_cmd_payload_a;
-wire    [2:0] litedramcore_choose_cmd_cmd_payload_ba;
-reg           litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg           litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg           litedramcore_choose_cmd_cmd_payload_we = 1'd0;
-wire          litedramcore_choose_cmd_cmd_payload_is_cmd;
-wire          litedramcore_choose_cmd_cmd_payload_is_read;
-wire          litedramcore_choose_cmd_cmd_payload_is_write;
-reg     [7:0] litedramcore_choose_cmd_valids = 8'd0;
-wire    [7:0] litedramcore_choose_cmd_request;
-reg     [2:0] litedramcore_choose_cmd_grant = 3'd0;
-wire          litedramcore_choose_cmd_ce;
-reg           litedramcore_choose_req_want_reads = 1'd0;
-reg           litedramcore_choose_req_want_writes = 1'd0;
-reg           litedramcore_choose_req_want_cmds = 1'd0;
-reg           litedramcore_choose_req_want_activates = 1'd0;
-wire          litedramcore_choose_req_cmd_valid;
-reg           litedramcore_choose_req_cmd_ready = 1'd0;
-wire   [15:0] litedramcore_choose_req_cmd_payload_a;
-wire    [2:0] litedramcore_choose_req_cmd_payload_ba;
-reg           litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg           litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg           litedramcore_choose_req_cmd_payload_we = 1'd0;
-wire          litedramcore_choose_req_cmd_payload_is_cmd;
-wire          litedramcore_choose_req_cmd_payload_is_read;
-wire          litedramcore_choose_req_cmd_payload_is_write;
-reg     [7:0] litedramcore_choose_req_valids = 8'd0;
-wire    [7:0] litedramcore_choose_req_request;
-reg     [2:0] litedramcore_choose_req_grant = 3'd0;
-wire          litedramcore_choose_req_ce;
-reg    [15:0] litedramcore_nop_a = 16'd0;
-reg     [2:0] litedramcore_nop_ba = 3'd0;
-reg     [1:0] litedramcore_steerer_sel0 = 2'd0;
-reg     [1:0] litedramcore_steerer_sel1 = 2'd0;
-reg     [1:0] litedramcore_steerer_sel2 = 2'd0;
-reg     [1:0] litedramcore_steerer_sel3 = 2'd0;
-reg           litedramcore_steerer0 = 1'd1;
-reg           litedramcore_steerer1 = 1'd1;
-reg           litedramcore_steerer2 = 1'd1;
-reg           litedramcore_steerer3 = 1'd1;
-reg           litedramcore_steerer4 = 1'd1;
-reg           litedramcore_steerer5 = 1'd1;
-reg           litedramcore_steerer6 = 1'd1;
-reg           litedramcore_steerer7 = 1'd1;
-wire          litedramcore_trrdcon_valid;
+reg           main_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine7_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine7_wrport_adr = 4'd0;
+wire   [25:0] main_litedramcore_bankmachine7_wrport_dat_r;
+wire   [25:0] main_litedramcore_bankmachine7_wrport_dat_w;
+wire          main_litedramcore_bankmachine7_wrport_we;
+wire          main_litedramcore_cas_allowed;
+wire          main_litedramcore_choose_cmd_ce;
+wire   [15:0] main_litedramcore_choose_cmd_cmd_payload_a;
+wire    [2:0] main_litedramcore_choose_cmd_cmd_payload_ba;
+reg           main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+wire          main_litedramcore_choose_cmd_cmd_payload_is_cmd;
+wire          main_litedramcore_choose_cmd_cmd_payload_is_read;
+wire          main_litedramcore_choose_cmd_cmd_payload_is_write;
+reg           main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+reg           main_litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire          main_litedramcore_choose_cmd_cmd_valid;
+reg     [2:0] main_litedramcore_choose_cmd_grant = 3'd0;
+wire    [7:0] main_litedramcore_choose_cmd_request;
+reg     [7:0] main_litedramcore_choose_cmd_valids = 8'd0;
+reg           main_litedramcore_choose_cmd_want_activates = 1'd0;
+reg           main_litedramcore_choose_cmd_want_cmds = 1'd0;
+reg           main_litedramcore_choose_cmd_want_reads = 1'd0;
+reg           main_litedramcore_choose_cmd_want_writes = 1'd0;
+wire          main_litedramcore_choose_req_ce;
+wire   [15:0] main_litedramcore_choose_req_cmd_payload_a;
+wire    [2:0] main_litedramcore_choose_req_cmd_payload_ba;
+reg           main_litedramcore_choose_req_cmd_payload_cas = 1'd0;
+wire          main_litedramcore_choose_req_cmd_payload_is_cmd;
+wire          main_litedramcore_choose_req_cmd_payload_is_read;
+wire          main_litedramcore_choose_req_cmd_payload_is_write;
+reg           main_litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_choose_req_cmd_payload_we = 1'd0;
+reg           main_litedramcore_choose_req_cmd_ready = 1'd0;
+wire          main_litedramcore_choose_req_cmd_valid;
+reg     [2:0] main_litedramcore_choose_req_grant = 3'd0;
+wire    [7:0] main_litedramcore_choose_req_request;
+reg     [7:0] main_litedramcore_choose_req_valids = 8'd0;
+reg           main_litedramcore_choose_req_want_activates = 1'd0;
+reg           main_litedramcore_choose_req_want_cmds = 1'd0;
+reg           main_litedramcore_choose_req_want_reads = 1'd0;
+reg           main_litedramcore_choose_req_want_writes = 1'd0;
+wire          main_litedramcore_cke;
+reg           main_litedramcore_cmd_last = 1'd0;
+reg    [15:0] main_litedramcore_cmd_payload_a = 16'd0;
+reg     [2:0] main_litedramcore_cmd_payload_ba = 3'd0;
+reg           main_litedramcore_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_cmd_payload_we = 1'd0;
+reg           main_litedramcore_cmd_ready = 1'd0;
+reg           main_litedramcore_cmd_valid = 1'd0;
+reg           main_litedramcore_csr_dfi_p0_act_n = 1'd1;
+wire   [15:0] main_litedramcore_csr_dfi_p0_address;
+wire    [2:0] main_litedramcore_csr_dfi_p0_bank;
+reg           main_litedramcore_csr_dfi_p0_cas_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p0_cke = 1'd0;
+reg           main_litedramcore_csr_dfi_p0_cs_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p0_odt = 1'd0;
+reg           main_litedramcore_csr_dfi_p0_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_csr_dfi_p0_rddata = 32'd0;
+wire          main_litedramcore_csr_dfi_p0_rddata_en;
+reg           main_litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
+wire          main_litedramcore_csr_dfi_p0_reset_n;
+reg           main_litedramcore_csr_dfi_p0_we_n = 1'd1;
+wire   [31:0] main_litedramcore_csr_dfi_p0_wrdata;
+wire          main_litedramcore_csr_dfi_p0_wrdata_en;
+wire    [3:0] main_litedramcore_csr_dfi_p0_wrdata_mask;
+reg           main_litedramcore_csr_dfi_p1_act_n = 1'd1;
+wire   [15:0] main_litedramcore_csr_dfi_p1_address;
+wire    [2:0] main_litedramcore_csr_dfi_p1_bank;
+reg           main_litedramcore_csr_dfi_p1_cas_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p1_cke = 1'd0;
+reg           main_litedramcore_csr_dfi_p1_cs_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p1_odt = 1'd0;
+reg           main_litedramcore_csr_dfi_p1_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_csr_dfi_p1_rddata = 32'd0;
+wire          main_litedramcore_csr_dfi_p1_rddata_en;
+reg           main_litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
+wire          main_litedramcore_csr_dfi_p1_reset_n;
+reg           main_litedramcore_csr_dfi_p1_we_n = 1'd1;
+wire   [31:0] main_litedramcore_csr_dfi_p1_wrdata;
+wire          main_litedramcore_csr_dfi_p1_wrdata_en;
+wire    [3:0] main_litedramcore_csr_dfi_p1_wrdata_mask;
+reg           main_litedramcore_csr_dfi_p2_act_n = 1'd1;
+wire   [15:0] main_litedramcore_csr_dfi_p2_address;
+wire    [2:0] main_litedramcore_csr_dfi_p2_bank;
+reg           main_litedramcore_csr_dfi_p2_cas_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p2_cke = 1'd0;
+reg           main_litedramcore_csr_dfi_p2_cs_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p2_odt = 1'd0;
+reg           main_litedramcore_csr_dfi_p2_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_csr_dfi_p2_rddata = 32'd0;
+wire          main_litedramcore_csr_dfi_p2_rddata_en;
+reg           main_litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
+wire          main_litedramcore_csr_dfi_p2_reset_n;
+reg           main_litedramcore_csr_dfi_p2_we_n = 1'd1;
+wire   [31:0] main_litedramcore_csr_dfi_p2_wrdata;
+wire          main_litedramcore_csr_dfi_p2_wrdata_en;
+wire    [3:0] main_litedramcore_csr_dfi_p2_wrdata_mask;
+reg           main_litedramcore_csr_dfi_p3_act_n = 1'd1;
+wire   [15:0] main_litedramcore_csr_dfi_p3_address;
+wire    [2:0] main_litedramcore_csr_dfi_p3_bank;
+reg           main_litedramcore_csr_dfi_p3_cas_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p3_cke = 1'd0;
+reg           main_litedramcore_csr_dfi_p3_cs_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p3_odt = 1'd0;
+reg           main_litedramcore_csr_dfi_p3_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_csr_dfi_p3_rddata = 32'd0;
+wire          main_litedramcore_csr_dfi_p3_rddata_en;
+reg           main_litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
+wire          main_litedramcore_csr_dfi_p3_reset_n;
+reg           main_litedramcore_csr_dfi_p3_we_n = 1'd1;
+wire   [31:0] main_litedramcore_csr_dfi_p3_wrdata;
+wire          main_litedramcore_csr_dfi_p3_wrdata_en;
+wire    [3:0] main_litedramcore_csr_dfi_p3_wrdata_mask;
+reg           main_litedramcore_dfi_p0_act_n = 1'd1;
+reg    [15:0] main_litedramcore_dfi_p0_address = 16'd0;
+reg     [2:0] main_litedramcore_dfi_p0_bank = 3'd0;
+reg           main_litedramcore_dfi_p0_cas_n = 1'd1;
+wire          main_litedramcore_dfi_p0_cke;
+reg           main_litedramcore_dfi_p0_cs_n = 1'd1;
+wire          main_litedramcore_dfi_p0_odt;
+reg           main_litedramcore_dfi_p0_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p0_rddata;
+reg           main_litedramcore_dfi_p0_rddata_en = 1'd0;
+wire          main_litedramcore_dfi_p0_rddata_valid;
+wire          main_litedramcore_dfi_p0_reset_n;
+reg           main_litedramcore_dfi_p0_we_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p0_wrdata;
+reg           main_litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire    [3:0] main_litedramcore_dfi_p0_wrdata_mask;
+reg           main_litedramcore_dfi_p1_act_n = 1'd1;
+reg    [15:0] main_litedramcore_dfi_p1_address = 16'd0;
+reg     [2:0] main_litedramcore_dfi_p1_bank = 3'd0;
+reg           main_litedramcore_dfi_p1_cas_n = 1'd1;
+wire          main_litedramcore_dfi_p1_cke;
+reg           main_litedramcore_dfi_p1_cs_n = 1'd1;
+wire          main_litedramcore_dfi_p1_odt;
+reg           main_litedramcore_dfi_p1_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p1_rddata;
+reg           main_litedramcore_dfi_p1_rddata_en = 1'd0;
+wire          main_litedramcore_dfi_p1_rddata_valid;
+wire          main_litedramcore_dfi_p1_reset_n;
+reg           main_litedramcore_dfi_p1_we_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p1_wrdata;
+reg           main_litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire    [3:0] main_litedramcore_dfi_p1_wrdata_mask;
+reg           main_litedramcore_dfi_p2_act_n = 1'd1;
+reg    [15:0] main_litedramcore_dfi_p2_address = 16'd0;
+reg     [2:0] main_litedramcore_dfi_p2_bank = 3'd0;
+reg           main_litedramcore_dfi_p2_cas_n = 1'd1;
+wire          main_litedramcore_dfi_p2_cke;
+reg           main_litedramcore_dfi_p2_cs_n = 1'd1;
+wire          main_litedramcore_dfi_p2_odt;
+reg           main_litedramcore_dfi_p2_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p2_rddata;
+reg           main_litedramcore_dfi_p2_rddata_en = 1'd0;
+wire          main_litedramcore_dfi_p2_rddata_valid;
+wire          main_litedramcore_dfi_p2_reset_n;
+reg           main_litedramcore_dfi_p2_we_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p2_wrdata;
+reg           main_litedramcore_dfi_p2_wrdata_en = 1'd0;
+wire    [3:0] main_litedramcore_dfi_p2_wrdata_mask;
+reg           main_litedramcore_dfi_p3_act_n = 1'd1;
+reg    [15:0] main_litedramcore_dfi_p3_address = 16'd0;
+reg     [2:0] main_litedramcore_dfi_p3_bank = 3'd0;
+reg           main_litedramcore_dfi_p3_cas_n = 1'd1;
+wire          main_litedramcore_dfi_p3_cke;
+reg           main_litedramcore_dfi_p3_cs_n = 1'd1;
+wire          main_litedramcore_dfi_p3_odt;
+reg           main_litedramcore_dfi_p3_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p3_rddata;
+reg           main_litedramcore_dfi_p3_rddata_en = 1'd0;
+wire          main_litedramcore_dfi_p3_rddata_valid;
+wire          main_litedramcore_dfi_p3_reset_n;
+reg           main_litedramcore_dfi_p3_we_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p3_wrdata;
+reg           main_litedramcore_dfi_p3_wrdata_en = 1'd0;
+wire    [3:0] main_litedramcore_dfi_p3_wrdata_mask;
+reg           main_litedramcore_en0 = 1'd0;
+reg           main_litedramcore_en1 = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_act_n = 1'd1;
+reg    [15:0] main_litedramcore_ext_dfi_p0_address = 16'd0;
+reg     [2:0] main_litedramcore_ext_dfi_p0_bank = 3'd0;
+reg           main_litedramcore_ext_dfi_p0_cas_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p0_cke = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_cs_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p0_odt = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p0_rddata = 32'd0;
+reg           main_litedramcore_ext_dfi_p0_rddata_en = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_reset_n = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_we_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p0_wrdata = 32'd0;
+reg           main_litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
+reg           main_litedramcore_ext_dfi_p1_act_n = 1'd1;
+reg    [15:0] main_litedramcore_ext_dfi_p1_address = 16'd0;
+reg     [2:0] main_litedramcore_ext_dfi_p1_bank = 3'd0;
+reg           main_litedramcore_ext_dfi_p1_cas_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p1_cke = 1'd0;
+reg           main_litedramcore_ext_dfi_p1_cs_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p1_odt = 1'd0;
+reg           main_litedramcore_ext_dfi_p1_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p1_rddata = 32'd0;
+reg           main_litedramcore_ext_dfi_p1_rddata_en = 1'd0;
+reg           main_litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
+reg           main_litedramcore_ext_dfi_p1_reset_n = 1'd0;
+reg           main_litedramcore_ext_dfi_p1_we_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p1_wrdata = 32'd0;
+reg           main_litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
+reg           main_litedramcore_ext_dfi_p2_act_n = 1'd1;
+reg    [15:0] main_litedramcore_ext_dfi_p2_address = 16'd0;
+reg     [2:0] main_litedramcore_ext_dfi_p2_bank = 3'd0;
+reg           main_litedramcore_ext_dfi_p2_cas_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p2_cke = 1'd0;
+reg           main_litedramcore_ext_dfi_p2_cs_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p2_odt = 1'd0;
+reg           main_litedramcore_ext_dfi_p2_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p2_rddata = 32'd0;
+reg           main_litedramcore_ext_dfi_p2_rddata_en = 1'd0;
+reg           main_litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
+reg           main_litedramcore_ext_dfi_p2_reset_n = 1'd0;
+reg           main_litedramcore_ext_dfi_p2_we_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p2_wrdata = 32'd0;
+reg           main_litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
+reg           main_litedramcore_ext_dfi_p3_act_n = 1'd1;
+reg    [15:0] main_litedramcore_ext_dfi_p3_address = 16'd0;
+reg     [2:0] main_litedramcore_ext_dfi_p3_bank = 3'd0;
+reg           main_litedramcore_ext_dfi_p3_cas_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p3_cke = 1'd0;
+reg           main_litedramcore_ext_dfi_p3_cs_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p3_odt = 1'd0;
+reg           main_litedramcore_ext_dfi_p3_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p3_rddata = 32'd0;
+reg           main_litedramcore_ext_dfi_p3_rddata_en = 1'd0;
+reg           main_litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
+reg           main_litedramcore_ext_dfi_p3_reset_n = 1'd0;
+reg           main_litedramcore_ext_dfi_p3_we_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p3_wrdata = 32'd0;
+reg           main_litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
+reg           main_litedramcore_ext_dfi_sel = 1'd0;
+wire          main_litedramcore_go_to_refresh;
+wire   [22:0] main_litedramcore_interface_bank0_addr;
+wire          main_litedramcore_interface_bank0_lock;
+wire          main_litedramcore_interface_bank0_rdata_valid;
+wire          main_litedramcore_interface_bank0_ready;
+wire          main_litedramcore_interface_bank0_valid;
+wire          main_litedramcore_interface_bank0_wdata_ready;
+wire          main_litedramcore_interface_bank0_we;
+wire   [22:0] main_litedramcore_interface_bank1_addr;
+wire          main_litedramcore_interface_bank1_lock;
+wire          main_litedramcore_interface_bank1_rdata_valid;
+wire          main_litedramcore_interface_bank1_ready;
+wire          main_litedramcore_interface_bank1_valid;
+wire          main_litedramcore_interface_bank1_wdata_ready;
+wire          main_litedramcore_interface_bank1_we;
+wire   [22:0] main_litedramcore_interface_bank2_addr;
+wire          main_litedramcore_interface_bank2_lock;
+wire          main_litedramcore_interface_bank2_rdata_valid;
+wire          main_litedramcore_interface_bank2_ready;
+wire          main_litedramcore_interface_bank2_valid;
+wire          main_litedramcore_interface_bank2_wdata_ready;
+wire          main_litedramcore_interface_bank2_we;
+wire   [22:0] main_litedramcore_interface_bank3_addr;
+wire          main_litedramcore_interface_bank3_lock;
+wire          main_litedramcore_interface_bank3_rdata_valid;
+wire          main_litedramcore_interface_bank3_ready;
+wire          main_litedramcore_interface_bank3_valid;
+wire          main_litedramcore_interface_bank3_wdata_ready;
+wire          main_litedramcore_interface_bank3_we;
+wire   [22:0] main_litedramcore_interface_bank4_addr;
+wire          main_litedramcore_interface_bank4_lock;
+wire          main_litedramcore_interface_bank4_rdata_valid;
+wire          main_litedramcore_interface_bank4_ready;
+wire          main_litedramcore_interface_bank4_valid;
+wire          main_litedramcore_interface_bank4_wdata_ready;
+wire          main_litedramcore_interface_bank4_we;
+wire   [22:0] main_litedramcore_interface_bank5_addr;
+wire          main_litedramcore_interface_bank5_lock;
+wire          main_litedramcore_interface_bank5_rdata_valid;
+wire          main_litedramcore_interface_bank5_ready;
+wire          main_litedramcore_interface_bank5_valid;
+wire          main_litedramcore_interface_bank5_wdata_ready;
+wire          main_litedramcore_interface_bank5_we;
+wire   [22:0] main_litedramcore_interface_bank6_addr;
+wire          main_litedramcore_interface_bank6_lock;
+wire          main_litedramcore_interface_bank6_rdata_valid;
+wire          main_litedramcore_interface_bank6_ready;
+wire          main_litedramcore_interface_bank6_valid;
+wire          main_litedramcore_interface_bank6_wdata_ready;
+wire          main_litedramcore_interface_bank6_we;
+wire   [22:0] main_litedramcore_interface_bank7_addr;
+wire          main_litedramcore_interface_bank7_lock;
+wire          main_litedramcore_interface_bank7_rdata_valid;
+wire          main_litedramcore_interface_bank7_ready;
+wire          main_litedramcore_interface_bank7_valid;
+wire          main_litedramcore_interface_bank7_wdata_ready;
+wire          main_litedramcore_interface_bank7_we;
+wire  [127:0] main_litedramcore_interface_rdata;
+reg   [127:0] main_litedramcore_interface_wdata = 128'd0;
+reg    [15:0] main_litedramcore_interface_wdata_we = 16'd0;
+reg           main_litedramcore_master_p0_act_n = 1'd1;
+reg    [15:0] main_litedramcore_master_p0_address = 16'd0;
+reg     [2:0] main_litedramcore_master_p0_bank = 3'd0;
+reg           main_litedramcore_master_p0_cas_n = 1'd1;
+reg           main_litedramcore_master_p0_cke = 1'd0;
+reg           main_litedramcore_master_p0_cs_n = 1'd1;
+reg           main_litedramcore_master_p0_odt = 1'd0;
+reg           main_litedramcore_master_p0_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_master_p0_rddata;
+reg           main_litedramcore_master_p0_rddata_en = 1'd0;
+wire          main_litedramcore_master_p0_rddata_valid;
+reg           main_litedramcore_master_p0_reset_n = 1'd0;
+reg           main_litedramcore_master_p0_we_n = 1'd1;
+reg    [31:0] main_litedramcore_master_p0_wrdata = 32'd0;
+reg           main_litedramcore_master_p0_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0;
+reg           main_litedramcore_master_p1_act_n = 1'd1;
+reg    [15:0] main_litedramcore_master_p1_address = 16'd0;
+reg     [2:0] main_litedramcore_master_p1_bank = 3'd0;
+reg           main_litedramcore_master_p1_cas_n = 1'd1;
+reg           main_litedramcore_master_p1_cke = 1'd0;
+reg           main_litedramcore_master_p1_cs_n = 1'd1;
+reg           main_litedramcore_master_p1_odt = 1'd0;
+reg           main_litedramcore_master_p1_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_master_p1_rddata;
+reg           main_litedramcore_master_p1_rddata_en = 1'd0;
+wire          main_litedramcore_master_p1_rddata_valid;
+reg           main_litedramcore_master_p1_reset_n = 1'd0;
+reg           main_litedramcore_master_p1_we_n = 1'd1;
+reg    [31:0] main_litedramcore_master_p1_wrdata = 32'd0;
+reg           main_litedramcore_master_p1_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0;
+reg           main_litedramcore_master_p2_act_n = 1'd1;
+reg    [15:0] main_litedramcore_master_p2_address = 16'd0;
+reg     [2:0] main_litedramcore_master_p2_bank = 3'd0;
+reg           main_litedramcore_master_p2_cas_n = 1'd1;
+reg           main_litedramcore_master_p2_cke = 1'd0;
+reg           main_litedramcore_master_p2_cs_n = 1'd1;
+reg           main_litedramcore_master_p2_odt = 1'd0;
+reg           main_litedramcore_master_p2_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_master_p2_rddata;
+reg           main_litedramcore_master_p2_rddata_en = 1'd0;
+wire          main_litedramcore_master_p2_rddata_valid;
+reg           main_litedramcore_master_p2_reset_n = 1'd0;
+reg           main_litedramcore_master_p2_we_n = 1'd1;
+reg    [31:0] main_litedramcore_master_p2_wrdata = 32'd0;
+reg           main_litedramcore_master_p2_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0;
+reg           main_litedramcore_master_p3_act_n = 1'd1;
+reg    [15:0] main_litedramcore_master_p3_address = 16'd0;
+reg     [2:0] main_litedramcore_master_p3_bank = 3'd0;
+reg           main_litedramcore_master_p3_cas_n = 1'd1;
+reg           main_litedramcore_master_p3_cke = 1'd0;
+reg           main_litedramcore_master_p3_cs_n = 1'd1;
+reg           main_litedramcore_master_p3_odt = 1'd0;
+reg           main_litedramcore_master_p3_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_master_p3_rddata;
+reg           main_litedramcore_master_p3_rddata_en = 1'd0;
+wire          main_litedramcore_master_p3_rddata_valid;
+reg           main_litedramcore_master_p3_reset_n = 1'd0;
+reg           main_litedramcore_master_p3_we_n = 1'd1;
+reg    [31:0] main_litedramcore_master_p3_wrdata = 32'd0;
+reg           main_litedramcore_master_p3_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0;
+wire          main_litedramcore_max_time0;
+wire          main_litedramcore_max_time1;
+reg    [15:0] main_litedramcore_nop_a = 16'd0;
+reg     [2:0] main_litedramcore_nop_ba = 3'd0;
+wire    [1:0] main_litedramcore_nphases;
+wire          main_litedramcore_odt;
+reg           main_litedramcore_phaseinjector0_address_re = 1'd0;
+reg    [15:0] main_litedramcore_phaseinjector0_address_storage = 16'd0;
+reg           main_litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg     [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0;
+wire          main_litedramcore_phaseinjector0_command_issue_r;
+reg           main_litedramcore_phaseinjector0_command_issue_re = 1'd0;
+reg           main_litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg           main_litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg           main_litedramcore_phaseinjector0_command_re = 1'd0;
+reg     [7:0] main_litedramcore_phaseinjector0_command_storage = 8'd0;
+wire          main_litedramcore_phaseinjector0_csrfield_cas;
+wire          main_litedramcore_phaseinjector0_csrfield_cs;
+wire          main_litedramcore_phaseinjector0_csrfield_cs_bottom;
+wire          main_litedramcore_phaseinjector0_csrfield_cs_top;
+wire          main_litedramcore_phaseinjector0_csrfield_ras;
+wire          main_litedramcore_phaseinjector0_csrfield_rden;
+wire          main_litedramcore_phaseinjector0_csrfield_we;
+wire          main_litedramcore_phaseinjector0_csrfield_wren;
+reg           main_litedramcore_phaseinjector0_rddata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0;
+wire          main_litedramcore_phaseinjector0_rddata_we;
+reg           main_litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
+reg           main_litedramcore_phaseinjector1_address_re = 1'd0;
+reg    [15:0] main_litedramcore_phaseinjector1_address_storage = 16'd0;
+reg           main_litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg     [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0;
+wire          main_litedramcore_phaseinjector1_command_issue_r;
+reg           main_litedramcore_phaseinjector1_command_issue_re = 1'd0;
+reg           main_litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg           main_litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg           main_litedramcore_phaseinjector1_command_re = 1'd0;
+reg     [7:0] main_litedramcore_phaseinjector1_command_storage = 8'd0;
+wire          main_litedramcore_phaseinjector1_csrfield_cas;
+wire          main_litedramcore_phaseinjector1_csrfield_cs;
+wire          main_litedramcore_phaseinjector1_csrfield_cs_bottom;
+wire          main_litedramcore_phaseinjector1_csrfield_cs_top;
+wire          main_litedramcore_phaseinjector1_csrfield_ras;
+wire          main_litedramcore_phaseinjector1_csrfield_rden;
+wire          main_litedramcore_phaseinjector1_csrfield_we;
+wire          main_litedramcore_phaseinjector1_csrfield_wren;
+reg           main_litedramcore_phaseinjector1_rddata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0;
+wire          main_litedramcore_phaseinjector1_rddata_we;
+reg           main_litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
+reg           main_litedramcore_phaseinjector2_address_re = 1'd0;
+reg    [15:0] main_litedramcore_phaseinjector2_address_storage = 16'd0;
+reg           main_litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg     [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0;
+wire          main_litedramcore_phaseinjector2_command_issue_r;
+reg           main_litedramcore_phaseinjector2_command_issue_re = 1'd0;
+reg           main_litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg           main_litedramcore_phaseinjector2_command_issue_we = 1'd0;
+reg           main_litedramcore_phaseinjector2_command_re = 1'd0;
+reg     [7:0] main_litedramcore_phaseinjector2_command_storage = 8'd0;
+wire          main_litedramcore_phaseinjector2_csrfield_cas;
+wire          main_litedramcore_phaseinjector2_csrfield_cs;
+wire          main_litedramcore_phaseinjector2_csrfield_cs_bottom;
+wire          main_litedramcore_phaseinjector2_csrfield_cs_top;
+wire          main_litedramcore_phaseinjector2_csrfield_ras;
+wire          main_litedramcore_phaseinjector2_csrfield_rden;
+wire          main_litedramcore_phaseinjector2_csrfield_we;
+wire          main_litedramcore_phaseinjector2_csrfield_wren;
+reg           main_litedramcore_phaseinjector2_rddata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0;
+wire          main_litedramcore_phaseinjector2_rddata_we;
+reg           main_litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
+reg           main_litedramcore_phaseinjector3_address_re = 1'd0;
+reg    [15:0] main_litedramcore_phaseinjector3_address_storage = 16'd0;
+reg           main_litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg     [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0;
+wire          main_litedramcore_phaseinjector3_command_issue_r;
+reg           main_litedramcore_phaseinjector3_command_issue_re = 1'd0;
+reg           main_litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg           main_litedramcore_phaseinjector3_command_issue_we = 1'd0;
+reg           main_litedramcore_phaseinjector3_command_re = 1'd0;
+reg     [7:0] main_litedramcore_phaseinjector3_command_storage = 8'd0;
+wire          main_litedramcore_phaseinjector3_csrfield_cas;
+wire          main_litedramcore_phaseinjector3_csrfield_cs;
+wire          main_litedramcore_phaseinjector3_csrfield_cs_bottom;
+wire          main_litedramcore_phaseinjector3_csrfield_cs_top;
+wire          main_litedramcore_phaseinjector3_csrfield_ras;
+wire          main_litedramcore_phaseinjector3_csrfield_rden;
+wire          main_litedramcore_phaseinjector3_csrfield_we;
+wire          main_litedramcore_phaseinjector3_csrfield_wren;
+reg           main_litedramcore_phaseinjector3_rddata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0;
+wire          main_litedramcore_phaseinjector3_rddata_we;
+reg           main_litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
+reg           main_litedramcore_postponer_count = 1'd0;
+wire          main_litedramcore_postponer_req_i;
+reg           main_litedramcore_postponer_req_o = 1'd0;
+wire          main_litedramcore_ras_allowed;
+wire    [1:0] main_litedramcore_rdphase;
+reg           main_litedramcore_re = 1'd0;
+wire          main_litedramcore_read_available;
+wire          main_litedramcore_reset_n;
+wire          main_litedramcore_sel;
+reg           main_litedramcore_sequencer_count = 1'd0;
+wire          main_litedramcore_sequencer_done0;
+reg           main_litedramcore_sequencer_done1 = 1'd0;
+reg           main_litedramcore_sequencer_start0 = 1'd0;
+wire          main_litedramcore_sequencer_start1;
+reg     [6:0] main_litedramcore_sequencer_trigger = 7'd0;
+wire          main_litedramcore_slave_p0_act_n;
+wire   [15:0] main_litedramcore_slave_p0_address;
+wire    [2:0] main_litedramcore_slave_p0_bank;
+wire          main_litedramcore_slave_p0_cas_n;
+wire          main_litedramcore_slave_p0_cke;
+wire          main_litedramcore_slave_p0_cs_n;
+wire          main_litedramcore_slave_p0_odt;
+wire          main_litedramcore_slave_p0_ras_n;
+reg    [31:0] main_litedramcore_slave_p0_rddata = 32'd0;
+wire          main_litedramcore_slave_p0_rddata_en;
+reg           main_litedramcore_slave_p0_rddata_valid = 1'd0;
+wire          main_litedramcore_slave_p0_reset_n;
+wire          main_litedramcore_slave_p0_we_n;
+wire   [31:0] main_litedramcore_slave_p0_wrdata;
+wire          main_litedramcore_slave_p0_wrdata_en;
+wire    [3:0] main_litedramcore_slave_p0_wrdata_mask;
+wire          main_litedramcore_slave_p1_act_n;
+wire   [15:0] main_litedramcore_slave_p1_address;
+wire    [2:0] main_litedramcore_slave_p1_bank;
+wire          main_litedramcore_slave_p1_cas_n;
+wire          main_litedramcore_slave_p1_cke;
+wire          main_litedramcore_slave_p1_cs_n;
+wire          main_litedramcore_slave_p1_odt;
+wire          main_litedramcore_slave_p1_ras_n;
+reg    [31:0] main_litedramcore_slave_p1_rddata = 32'd0;
+wire          main_litedramcore_slave_p1_rddata_en;
+reg           main_litedramcore_slave_p1_rddata_valid = 1'd0;
+wire          main_litedramcore_slave_p1_reset_n;
+wire          main_litedramcore_slave_p1_we_n;
+wire   [31:0] main_litedramcore_slave_p1_wrdata;
+wire          main_litedramcore_slave_p1_wrdata_en;
+wire    [3:0] main_litedramcore_slave_p1_wrdata_mask;
+wire          main_litedramcore_slave_p2_act_n;
+wire   [15:0] main_litedramcore_slave_p2_address;
+wire    [2:0] main_litedramcore_slave_p2_bank;
+wire          main_litedramcore_slave_p2_cas_n;
+wire          main_litedramcore_slave_p2_cke;
+wire          main_litedramcore_slave_p2_cs_n;
+wire          main_litedramcore_slave_p2_odt;
+wire          main_litedramcore_slave_p2_ras_n;
+reg    [31:0] main_litedramcore_slave_p2_rddata = 32'd0;
+wire          main_litedramcore_slave_p2_rddata_en;
+reg           main_litedramcore_slave_p2_rddata_valid = 1'd0;
+wire          main_litedramcore_slave_p2_reset_n;
+wire          main_litedramcore_slave_p2_we_n;
+wire   [31:0] main_litedramcore_slave_p2_wrdata;
+wire          main_litedramcore_slave_p2_wrdata_en;
+wire    [3:0] main_litedramcore_slave_p2_wrdata_mask;
+wire          main_litedramcore_slave_p3_act_n;
+wire   [15:0] main_litedramcore_slave_p3_address;
+wire    [2:0] main_litedramcore_slave_p3_bank;
+wire          main_litedramcore_slave_p3_cas_n;
+wire          main_litedramcore_slave_p3_cke;
+wire          main_litedramcore_slave_p3_cs_n;
+wire          main_litedramcore_slave_p3_odt;
+wire          main_litedramcore_slave_p3_ras_n;
+reg    [31:0] main_litedramcore_slave_p3_rddata = 32'd0;
+wire          main_litedramcore_slave_p3_rddata_en;
+reg           main_litedramcore_slave_p3_rddata_valid = 1'd0;
+wire          main_litedramcore_slave_p3_reset_n;
+wire          main_litedramcore_slave_p3_we_n;
+wire   [31:0] main_litedramcore_slave_p3_wrdata;
+wire          main_litedramcore_slave_p3_wrdata_en;
+wire    [3:0] main_litedramcore_slave_p3_wrdata_mask;
+reg     [1:0] main_litedramcore_steerer0 = 2'd0;
+reg     [1:0] main_litedramcore_steerer1 = 2'd0;
+reg           main_litedramcore_steerer10 = 1'd1;
+reg           main_litedramcore_steerer11 = 1'd1;
+reg     [1:0] main_litedramcore_steerer2 = 2'd0;
+reg     [1:0] main_litedramcore_steerer3 = 2'd0;
+reg           main_litedramcore_steerer4 = 1'd1;
+reg           main_litedramcore_steerer5 = 1'd1;
+reg           main_litedramcore_steerer6 = 1'd1;
+reg           main_litedramcore_steerer7 = 1'd1;
+reg           main_litedramcore_steerer8 = 1'd1;
+reg           main_litedramcore_steerer9 = 1'd1;
+reg     [3:0] main_litedramcore_storage = 4'd1;
+reg           main_litedramcore_tccdcon_count = 1'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_trrdcon_ready = 1'd0;
-reg           litedramcore_trrdcon_count = 1'd0;
-wire          litedramcore_tfawcon_valid;
+reg           main_litedramcore_tccdcon_ready = 1'd0;
+wire          main_litedramcore_tccdcon_valid;
+wire    [2:0] main_litedramcore_tfawcon_count;
 (* dont_touch = "true" *)
-reg           litedramcore_tfawcon_ready = 1'd1;
-wire    [2:0] litedramcore_tfawcon_count;
-reg     [4:0] litedramcore_tfawcon_window = 5'd0;
-wire          litedramcore_tccdcon_valid;
+reg           main_litedramcore_tfawcon_ready = 1'd1;
+wire          main_litedramcore_tfawcon_valid;
+reg     [4:0] main_litedramcore_tfawcon_window = 5'd0;
+reg     [4:0] main_litedramcore_time0 = 5'd0;
+reg     [3:0] main_litedramcore_time1 = 4'd0;
+wire    [9:0] main_litedramcore_timer_count0;
+reg     [9:0] main_litedramcore_timer_count1 = 10'd781;
+wire          main_litedramcore_timer_done0;
+wire          main_litedramcore_timer_done1;
+wire          main_litedramcore_timer_wait;
+reg           main_litedramcore_trrdcon_count = 1'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_tccdcon_ready = 1'd0;
-reg           litedramcore_tccdcon_count = 1'd0;
-wire          litedramcore_twtrcon_valid;
+reg           main_litedramcore_trrdcon_ready = 1'd0;
+wire          main_litedramcore_trrdcon_valid;
+reg     [2:0] main_litedramcore_twtrcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_twtrcon_ready = 1'd0;
-reg     [2:0] litedramcore_twtrcon_count = 3'd0;
-wire          litedramcore_read_available;
-wire          litedramcore_write_available;
-reg           litedramcore_en0 = 1'd0;
-wire          litedramcore_max_time0;
-reg     [4:0] litedramcore_time0 = 5'd0;
-reg           litedramcore_en1 = 1'd0;
-wire          litedramcore_max_time1;
-reg     [3:0] litedramcore_time1 = 4'd0;
-wire          litedramcore_go_to_refresh;
-reg           init_done_storage = 1'd0;
-reg           init_done_re = 1'd0;
-reg           init_error_storage = 1'd0;
-reg           init_error_re = 1'd0;
-wire   [29:0] wb_bus_adr;
-wire   [31:0] wb_bus_dat_w;
-wire   [31:0] wb_bus_dat_r;
-wire    [3:0] wb_bus_sel;
-wire          wb_bus_cyc;
-wire          wb_bus_stb;
-wire          wb_bus_ack;
-wire          wb_bus_we;
-wire    [2:0] wb_bus_cti;
-wire    [1:0] wb_bus_bte;
-wire          wb_bus_err;
-wire          user_enable;
-wire          user_port_cmd_valid;
-wire          user_port_cmd_ready;
-wire          user_port_cmd_payload_we;
-wire   [25:0] user_port_cmd_payload_addr;
-wire          user_port_wdata_valid;
-wire          user_port_wdata_ready;
-wire  [127:0] user_port_wdata_payload_data;
-wire   [15:0] user_port_wdata_payload_we;
-wire          user_port_rdata_valid;
-wire          user_port_rdata_ready;
-wire  [127:0] user_port_rdata_payload_data;
-reg    [13:0] litedramcore_adr = 14'd0;
-reg           litedramcore_we = 1'd0;
-reg    [31:0] litedramcore_dat_w = 32'd0;
-wire   [31:0] litedramcore_dat_r;
-wire   [29:0] litedramcore_wishbone_adr;
-wire   [31:0] litedramcore_wishbone_dat_w;
-reg    [31:0] litedramcore_wishbone_dat_r = 32'd0;
-wire    [3:0] litedramcore_wishbone_sel;
-wire          litedramcore_wishbone_cyc;
-wire          litedramcore_wishbone_stb;
-reg           litedramcore_wishbone_ack = 1'd0;
-wire          litedramcore_wishbone_we;
-wire    [2:0] litedramcore_wishbone_cti;
-wire    [1:0] litedramcore_wishbone_bte;
-reg           litedramcore_wishbone_err = 1'd0;
-wire   [13:0] interface0_bank_bus_adr;
-wire          interface0_bank_bus_we;
-wire   [31:0] interface0_bank_bus_dat_w;
-reg    [31:0] interface0_bank_bus_dat_r = 32'd0;
-reg           csrbank0_init_done0_re = 1'd0;
-wire          csrbank0_init_done0_r;
-reg           csrbank0_init_done0_we = 1'd0;
-wire          csrbank0_init_done0_w;
-reg           csrbank0_init_error0_re = 1'd0;
-wire          csrbank0_init_error0_r;
-reg           csrbank0_init_error0_we = 1'd0;
-wire          csrbank0_init_error0_w;
-wire          csrbank0_sel;
-wire   [13:0] interface1_bank_bus_adr;
-wire          interface1_bank_bus_we;
-wire   [31:0] interface1_bank_bus_dat_w;
-reg    [31:0] interface1_bank_bus_dat_r = 32'd0;
-reg           csrbank1_rst0_re = 1'd0;
-wire          csrbank1_rst0_r;
-reg           csrbank1_rst0_we = 1'd0;
-wire          csrbank1_rst0_w;
-reg           csrbank1_dly_sel0_re = 1'd0;
-wire    [1:0] csrbank1_dly_sel0_r;
-reg           csrbank1_dly_sel0_we = 1'd0;
-wire    [1:0] csrbank1_dly_sel0_w;
-reg           csrbank1_half_sys8x_taps0_re = 1'd0;
-wire    [4:0] csrbank1_half_sys8x_taps0_r;
-reg           csrbank1_half_sys8x_taps0_we = 1'd0;
-wire    [4:0] csrbank1_half_sys8x_taps0_w;
-reg           csrbank1_wlevel_en0_re = 1'd0;
-wire          csrbank1_wlevel_en0_r;
-reg           csrbank1_wlevel_en0_we = 1'd0;
-wire          csrbank1_wlevel_en0_w;
-reg           csrbank1_rdphase0_re = 1'd0;
-wire    [1:0] csrbank1_rdphase0_r;
-reg           csrbank1_rdphase0_we = 1'd0;
-wire    [1:0] csrbank1_rdphase0_w;
-reg           csrbank1_wrphase0_re = 1'd0;
-wire    [1:0] csrbank1_wrphase0_r;
-reg           csrbank1_wrphase0_we = 1'd0;
-wire    [1:0] csrbank1_wrphase0_w;
-wire          csrbank1_sel;
-wire   [13:0] interface2_bank_bus_adr;
-wire          interface2_bank_bus_we;
-wire   [31:0] interface2_bank_bus_dat_w;
-reg    [31:0] interface2_bank_bus_dat_r = 32'd0;
-reg           csrbank2_dfii_control0_re = 1'd0;
-wire    [3:0] csrbank2_dfii_control0_r;
-reg           csrbank2_dfii_control0_we = 1'd0;
-wire    [3:0] csrbank2_dfii_control0_w;
-reg           csrbank2_dfii_pi0_command0_re = 1'd0;
-wire    [5:0] csrbank2_dfii_pi0_command0_r;
-reg           csrbank2_dfii_pi0_command0_we = 1'd0;
-wire    [5:0] csrbank2_dfii_pi0_command0_w;
-reg           csrbank2_dfii_pi0_address0_re = 1'd0;
-wire   [15:0] csrbank2_dfii_pi0_address0_r;
-reg           csrbank2_dfii_pi0_address0_we = 1'd0;
-wire   [15:0] csrbank2_dfii_pi0_address0_w;
-reg           csrbank2_dfii_pi0_baddress0_re = 1'd0;
-wire    [2:0] csrbank2_dfii_pi0_baddress0_r;
-reg           csrbank2_dfii_pi0_baddress0_we = 1'd0;
-wire    [2:0] csrbank2_dfii_pi0_baddress0_w;
-reg           csrbank2_dfii_pi0_wrdata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_wrdata0_r;
-reg           csrbank2_dfii_pi0_wrdata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_wrdata0_w;
-reg           csrbank2_dfii_pi0_rddata_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_rddata_r;
-reg           csrbank2_dfii_pi0_rddata_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_rddata_w;
-reg           csrbank2_dfii_pi1_command0_re = 1'd0;
-wire    [5:0] csrbank2_dfii_pi1_command0_r;
-reg           csrbank2_dfii_pi1_command0_we = 1'd0;
-wire    [5:0] csrbank2_dfii_pi1_command0_w;
-reg           csrbank2_dfii_pi1_address0_re = 1'd0;
-wire   [15:0] csrbank2_dfii_pi1_address0_r;
-reg           csrbank2_dfii_pi1_address0_we = 1'd0;
-wire   [15:0] csrbank2_dfii_pi1_address0_w;
-reg           csrbank2_dfii_pi1_baddress0_re = 1'd0;
-wire    [2:0] csrbank2_dfii_pi1_baddress0_r;
-reg           csrbank2_dfii_pi1_baddress0_we = 1'd0;
-wire    [2:0] csrbank2_dfii_pi1_baddress0_w;
-reg           csrbank2_dfii_pi1_wrdata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_wrdata0_r;
-reg           csrbank2_dfii_pi1_wrdata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_wrdata0_w;
-reg           csrbank2_dfii_pi1_rddata_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_rddata_r;
-reg           csrbank2_dfii_pi1_rddata_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_rddata_w;
-reg           csrbank2_dfii_pi2_command0_re = 1'd0;
-wire    [5:0] csrbank2_dfii_pi2_command0_r;
-reg           csrbank2_dfii_pi2_command0_we = 1'd0;
-wire    [5:0] csrbank2_dfii_pi2_command0_w;
-reg           csrbank2_dfii_pi2_address0_re = 1'd0;
-wire   [15:0] csrbank2_dfii_pi2_address0_r;
-reg           csrbank2_dfii_pi2_address0_we = 1'd0;
-wire   [15:0] csrbank2_dfii_pi2_address0_w;
-reg           csrbank2_dfii_pi2_baddress0_re = 1'd0;
-wire    [2:0] csrbank2_dfii_pi2_baddress0_r;
-reg           csrbank2_dfii_pi2_baddress0_we = 1'd0;
-wire    [2:0] csrbank2_dfii_pi2_baddress0_w;
-reg           csrbank2_dfii_pi2_wrdata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi2_wrdata0_r;
-reg           csrbank2_dfii_pi2_wrdata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi2_wrdata0_w;
-reg           csrbank2_dfii_pi2_rddata_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi2_rddata_r;
-reg           csrbank2_dfii_pi2_rddata_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi2_rddata_w;
-reg           csrbank2_dfii_pi3_command0_re = 1'd0;
-wire    [5:0] csrbank2_dfii_pi3_command0_r;
-reg           csrbank2_dfii_pi3_command0_we = 1'd0;
-wire    [5:0] csrbank2_dfii_pi3_command0_w;
-reg           csrbank2_dfii_pi3_address0_re = 1'd0;
-wire   [15:0] csrbank2_dfii_pi3_address0_r;
-reg           csrbank2_dfii_pi3_address0_we = 1'd0;
-wire   [15:0] csrbank2_dfii_pi3_address0_w;
-reg           csrbank2_dfii_pi3_baddress0_re = 1'd0;
-wire    [2:0] csrbank2_dfii_pi3_baddress0_r;
-reg           csrbank2_dfii_pi3_baddress0_we = 1'd0;
-wire    [2:0] csrbank2_dfii_pi3_baddress0_w;
-reg           csrbank2_dfii_pi3_wrdata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi3_wrdata0_r;
-reg           csrbank2_dfii_pi3_wrdata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi3_wrdata0_w;
-reg           csrbank2_dfii_pi3_rddata_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi3_rddata_r;
-reg           csrbank2_dfii_pi3_rddata_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi3_rddata_w;
-wire          csrbank2_sel;
-wire   [13:0] csr_interconnect_adr;
-wire          csr_interconnect_we;
-wire   [31:0] csr_interconnect_dat_w;
-wire   [31:0] csr_interconnect_dat_r;
-wire          litedramcore_reset0;
-wire          litedramcore_reset1;
-wire          litedramcore_reset2;
-wire          litedramcore_reset3;
-wire          litedramcore_reset4;
-wire          litedramcore_reset5;
-wire          litedramcore_reset6;
-wire          litedramcore_reset7;
-wire          litedramcore_pll_fb;
-reg     [1:0] litedramcore_refresher_state = 2'd0;
-reg     [1:0] litedramcore_refresher_next_state = 2'd0;
-reg     [3:0] litedramcore_bankmachine0_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine0_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine1_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine1_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine2_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine2_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine3_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine3_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine4_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine4_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine5_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine5_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine6_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine6_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine7_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine7_next_state = 4'd0;
-reg     [3:0] litedramcore_multiplexer_state = 4'd0;
-reg     [3:0] litedramcore_multiplexer_next_state = 4'd0;
-wire          litedramcore_roundrobin0_request;
-wire          litedramcore_roundrobin0_grant;
-wire          litedramcore_roundrobin0_ce;
-wire          litedramcore_roundrobin1_request;
-wire          litedramcore_roundrobin1_grant;
-wire          litedramcore_roundrobin1_ce;
-wire          litedramcore_roundrobin2_request;
-wire          litedramcore_roundrobin2_grant;
-wire          litedramcore_roundrobin2_ce;
-wire          litedramcore_roundrobin3_request;
-wire          litedramcore_roundrobin3_grant;
-wire          litedramcore_roundrobin3_ce;
-wire          litedramcore_roundrobin4_request;
-wire          litedramcore_roundrobin4_grant;
-wire          litedramcore_roundrobin4_ce;
-wire          litedramcore_roundrobin5_request;
-wire          litedramcore_roundrobin5_grant;
-wire          litedramcore_roundrobin5_ce;
-wire          litedramcore_roundrobin6_request;
-wire          litedramcore_roundrobin6_grant;
-wire          litedramcore_roundrobin6_ce;
-wire          litedramcore_roundrobin7_request;
-wire          litedramcore_roundrobin7_grant;
-wire          litedramcore_roundrobin7_ce;
-reg           litedramcore_locked0 = 1'd0;
-reg           litedramcore_locked1 = 1'd0;
-reg           litedramcore_locked2 = 1'd0;
-reg           litedramcore_locked3 = 1'd0;
-reg           litedramcore_locked4 = 1'd0;
-reg           litedramcore_locked5 = 1'd0;
-reg           litedramcore_locked6 = 1'd0;
-reg           litedramcore_locked7 = 1'd0;
-reg           litedramcore_new_master_wdata_ready0 = 1'd0;
-reg           litedramcore_new_master_wdata_ready1 = 1'd0;
-reg           litedramcore_new_master_rdata_valid0 = 1'd0;
-reg           litedramcore_new_master_rdata_valid1 = 1'd0;
-reg           litedramcore_new_master_rdata_valid2 = 1'd0;
-reg           litedramcore_new_master_rdata_valid3 = 1'd0;
-reg           litedramcore_new_master_rdata_valid4 = 1'd0;
-reg           litedramcore_new_master_rdata_valid5 = 1'd0;
-reg           litedramcore_new_master_rdata_valid6 = 1'd0;
-reg           litedramcore_new_master_rdata_valid7 = 1'd0;
-reg           litedramcore_new_master_rdata_valid8 = 1'd0;
-reg     [1:0] litedramcore_state = 2'd0;
-reg     [1:0] litedramcore_next_state = 2'd0;
-reg    [31:0] litedramcore_dat_w_next_value0 = 32'd0;
-reg           litedramcore_dat_w_next_value_ce0 = 1'd0;
-reg    [13:0] litedramcore_adr_next_value1 = 14'd0;
-reg           litedramcore_adr_next_value_ce1 = 1'd0;
-reg           litedramcore_we_next_value2 = 1'd0;
-reg           litedramcore_we_next_value_ce2 = 1'd0;
-reg           rhs_array_muxed0 = 1'd0;
-reg    [15:0] rhs_array_muxed1 = 16'd0;
-reg     [2:0] rhs_array_muxed2 = 3'd0;
-reg           rhs_array_muxed3 = 1'd0;
-reg           rhs_array_muxed4 = 1'd0;
-reg           rhs_array_muxed5 = 1'd0;
-reg           t_array_muxed0 = 1'd0;
-reg           t_array_muxed1 = 1'd0;
-reg           t_array_muxed2 = 1'd0;
-reg           rhs_array_muxed6 = 1'd0;
-reg    [15:0] rhs_array_muxed7 = 16'd0;
-reg     [2:0] rhs_array_muxed8 = 3'd0;
-reg           rhs_array_muxed9 = 1'd0;
-reg           rhs_array_muxed10 = 1'd0;
-reg           rhs_array_muxed11 = 1'd0;
-reg           t_array_muxed3 = 1'd0;
-reg           t_array_muxed4 = 1'd0;
-reg           t_array_muxed5 = 1'd0;
-reg    [22:0] rhs_array_muxed12 = 23'd0;
-reg           rhs_array_muxed13 = 1'd0;
-reg           rhs_array_muxed14 = 1'd0;
-reg    [22:0] rhs_array_muxed15 = 23'd0;
-reg           rhs_array_muxed16 = 1'd0;
-reg           rhs_array_muxed17 = 1'd0;
-reg    [22:0] rhs_array_muxed18 = 23'd0;
-reg           rhs_array_muxed19 = 1'd0;
-reg           rhs_array_muxed20 = 1'd0;
-reg    [22:0] rhs_array_muxed21 = 23'd0;
-reg           rhs_array_muxed22 = 1'd0;
-reg           rhs_array_muxed23 = 1'd0;
-reg    [22:0] rhs_array_muxed24 = 23'd0;
-reg           rhs_array_muxed25 = 1'd0;
-reg           rhs_array_muxed26 = 1'd0;
-reg    [22:0] rhs_array_muxed27 = 23'd0;
-reg           rhs_array_muxed28 = 1'd0;
-reg           rhs_array_muxed29 = 1'd0;
-reg    [22:0] rhs_array_muxed30 = 23'd0;
-reg           rhs_array_muxed31 = 1'd0;
-reg           rhs_array_muxed32 = 1'd0;
-reg    [22:0] rhs_array_muxed33 = 23'd0;
-reg           rhs_array_muxed34 = 1'd0;
-reg           rhs_array_muxed35 = 1'd0;
-reg     [2:0] array_muxed0 = 3'd0;
-reg    [15:0] array_muxed1 = 16'd0;
-reg           array_muxed2 = 1'd0;
-reg           array_muxed3 = 1'd0;
-reg           array_muxed4 = 1'd0;
-reg           array_muxed5 = 1'd0;
-reg           array_muxed6 = 1'd0;
-reg     [2:0] array_muxed7 = 3'd0;
-reg    [15:0] array_muxed8 = 16'd0;
-reg           array_muxed9 = 1'd0;
-reg           array_muxed10 = 1'd0;
-reg           array_muxed11 = 1'd0;
-reg           array_muxed12 = 1'd0;
-reg           array_muxed13 = 1'd0;
-reg     [2:0] array_muxed14 = 3'd0;
-reg    [15:0] array_muxed15 = 16'd0;
-reg           array_muxed16 = 1'd0;
-reg           array_muxed17 = 1'd0;
-reg           array_muxed18 = 1'd0;
-reg           array_muxed19 = 1'd0;
-reg           array_muxed20 = 1'd0;
-reg     [2:0] array_muxed21 = 3'd0;
-reg    [15:0] array_muxed22 = 16'd0;
-reg           array_muxed23 = 1'd0;
-reg           array_muxed24 = 1'd0;
-reg           array_muxed25 = 1'd0;
-reg           array_muxed26 = 1'd0;
-reg           array_muxed27 = 1'd0;
-wire          xilinxasyncresetsynchronizerimpl0;
-wire          xilinxasyncresetsynchronizerimpl0_rst_meta;
-wire          xilinxasyncresetsynchronizerimpl1;
-wire          xilinxasyncresetsynchronizerimpl1_rst_meta;
-wire          xilinxasyncresetsynchronizerimpl2;
-wire          xilinxasyncresetsynchronizerimpl2_rst_meta;
-wire          xilinxasyncresetsynchronizerimpl2_expr;
-wire          xilinxasyncresetsynchronizerimpl3;
-wire          xilinxasyncresetsynchronizerimpl3_rst_meta;
-wire          xilinxasyncresetsynchronizerimpl3_expr;
+reg           main_litedramcore_twtrcon_ready = 1'd0;
+wire          main_litedramcore_twtrcon_valid;
+wire          main_litedramcore_wants_refresh;
+wire          main_litedramcore_wants_zqcs;
+wire          main_litedramcore_write_available;
+reg           main_litedramcore_zqcs_executer_done = 1'd0;
+reg           main_litedramcore_zqcs_executer_start = 1'd0;
+reg     [4:0] main_litedramcore_zqcs_executer_trigger = 5'd0;
+wire   [26:0] main_litedramcore_zqcs_timer_count0;
+reg    [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999;
+wire          main_litedramcore_zqcs_timer_done0;
+wire          main_litedramcore_zqcs_timer_done1;
+wire          main_litedramcore_zqcs_timer_wait;
+wire          main_locked;
+reg           main_power_down = 1'd0;
+wire          main_reset;
+reg     [3:0] main_reset_counter = 4'd15;
+reg           main_rst = 1'd0;
+wire          main_user_enable;
+wire   [25:0] main_user_port_cmd_payload_addr;
+wire          main_user_port_cmd_payload_we;
+wire          main_user_port_cmd_ready;
+wire          main_user_port_cmd_valid;
+wire  [127:0] main_user_port_rdata_payload_data;
+wire          main_user_port_rdata_ready;
+wire          main_user_port_rdata_valid;
+wire  [127:0] main_user_port_wdata_payload_data;
+wire   [15:0] main_user_port_wdata_payload_we;
+wire          main_user_port_wdata_ready;
+wire          main_user_port_wdata_valid;
+wire          main_wb_bus_ack;
+wire   [29:0] main_wb_bus_adr;
+wire    [1:0] main_wb_bus_bte;
+wire    [2:0] main_wb_bus_cti;
+wire          main_wb_bus_cyc;
+wire   [31:0] main_wb_bus_dat_r;
+wire   [31:0] main_wb_bus_dat_w;
+wire          main_wb_bus_err;
+wire    [3:0] main_wb_bus_sel;
+wire          main_wb_bus_stb;
+wire          main_wb_bus_we;
+wire          sys4x_clk;
+wire          sys4x_dqs_clk;
+wire          sys_clk;
+wire          sys_rst;
 
 //------------------------------------------------------------------------------
 // Combinatorial Logic
 //------------------------------------------------------------------------------
 
-assign init_done = init_done_storage;
-assign init_error = init_error_storage;
-assign wb_bus_adr = wb_ctrl_adr;
-assign wb_bus_dat_w = wb_ctrl_dat_w;
-assign wb_ctrl_dat_r = wb_bus_dat_r;
-assign wb_bus_sel = wb_ctrl_sel;
-assign wb_bus_cyc = wb_ctrl_cyc;
-assign wb_bus_stb = wb_ctrl_stb;
-assign wb_ctrl_ack = wb_bus_ack;
-assign wb_bus_we = wb_ctrl_we;
-assign wb_bus_cti = wb_ctrl_cti;
-assign wb_bus_bte = wb_ctrl_bte;
-assign wb_ctrl_err = wb_bus_err;
+assign init_done = main_init_done_storage;
+assign init_error = main_init_error_storage;
+assign main_wb_bus_adr = wb_ctrl_adr;
+assign main_wb_bus_dat_w = wb_ctrl_dat_w;
+assign wb_ctrl_dat_r = main_wb_bus_dat_r;
+assign main_wb_bus_sel = wb_ctrl_sel;
+assign main_wb_bus_cyc = wb_ctrl_cyc;
+assign main_wb_bus_stb = wb_ctrl_stb;
+assign wb_ctrl_ack = main_wb_bus_ack;
+assign main_wb_bus_we = wb_ctrl_we;
+assign main_wb_bus_cti = wb_ctrl_cti;
+assign main_wb_bus_bte = wb_ctrl_bte;
+assign wb_ctrl_err = main_wb_bus_err;
 assign user_clk = sys_clk;
 assign user_rst = sys_rst;
-assign user_enable = 1'd1;
-assign user_port_cmd_valid = (user_port_native_0_cmd_valid & user_enable);
-assign user_port_native_0_cmd_ready = (user_port_cmd_ready & user_enable);
-assign user_port_cmd_payload_we = user_port_native_0_cmd_we;
-assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
-assign user_port_wdata_valid = (user_port_native_0_wdata_valid & user_enable);
-assign user_port_native_0_wdata_ready = (user_port_wdata_ready & user_enable);
-assign user_port_wdata_payload_we = user_port_native_0_wdata_we;
-assign user_port_wdata_payload_data = user_port_native_0_wdata_data;
-assign user_port_native_0_rdata_valid = (user_port_rdata_valid & user_enable);
-assign user_port_rdata_ready = (user_port_native_0_rdata_ready & user_enable);
-assign user_port_native_0_rdata_data = user_port_rdata_payload_data;
-assign reset = (rst | rst_1);
-assign pll_locked = locked;
-assign clkin = clk;
-assign iodelay_clk = clkout_buf0;
-assign sys_clk = clkout_buf1;
-assign sys4x_clk = clkout_buf2;
-assign sys4x_dqs_clk = clkout_buf3;
-assign ddram_ba = a7ddrphy_pads_ba;
-assign a7ddrphy_dqs_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dqs_oe) | a7ddrphy_dqs_postamble);
-assign a7ddrphy_dq_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dq_oe) | a7ddrphy_dqs_postamble);
-always @(*) begin
-    a7ddrphy_dfi_p0_rddata <= 32'd0;
-    a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0];
-    a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1];
-    a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0];
-    a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1];
-    a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0];
-    a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1];
-    a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0];
-    a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1];
-    a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0];
-    a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1];
-    a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0];
-    a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1];
-    a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0];
-    a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1];
-    a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0];
-    a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1];
-    a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0];
-    a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1];
-    a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0];
-    a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1];
-    a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0];
-    a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1];
-    a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0];
-    a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1];
-    a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0];
-    a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1];
-    a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0];
-    a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1];
-    a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0];
-    a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1];
-    a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0];
-    a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1];
-end
-always @(*) begin
-    a7ddrphy_dfi_p1_rddata <= 32'd0;
-    a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2];
-    a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3];
-    a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2];
-    a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3];
-    a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2];
-    a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3];
-    a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2];
-    a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3];
-    a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2];
-    a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3];
-    a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2];
-    a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3];
-    a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2];
-    a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3];
-    a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2];
-    a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3];
-    a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2];
-    a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3];
-    a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2];
-    a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3];
-    a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2];
-    a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3];
-    a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2];
-    a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3];
-    a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2];
-    a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3];
-    a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2];
-    a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3];
-    a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2];
-    a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3];
-    a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2];
-    a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3];
-end
-always @(*) begin
-    a7ddrphy_dfi_p2_rddata <= 32'd0;
-    a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4];
-    a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5];
-    a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4];
-    a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5];
-    a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4];
-    a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5];
-    a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4];
-    a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5];
-    a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4];
-    a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5];
-    a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4];
-    a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5];
-    a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4];
-    a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5];
-    a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4];
-    a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5];
-    a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4];
-    a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5];
-    a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4];
-    a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5];
-    a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4];
-    a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5];
-    a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4];
-    a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5];
-    a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4];
-    a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5];
-    a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4];
-    a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5];
-    a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4];
-    a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5];
-    a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4];
-    a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5];
-end
-always @(*) begin
-    a7ddrphy_dfi_p3_rddata <= 32'd0;
-    a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6];
-    a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7];
-    a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6];
-    a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7];
-    a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6];
-    a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7];
-    a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6];
-    a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7];
-    a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6];
-    a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7];
-    a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6];
-    a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7];
-    a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6];
-    a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7];
-    a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6];
-    a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7];
-    a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6];
-    a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7];
-    a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6];
-    a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7];
-    a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6];
-    a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7];
-    a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6];
-    a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7];
-    a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6];
-    a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7];
-    a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6];
-    a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7];
-    a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6];
-    a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7];
-    a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6];
-    a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7];
-end
-assign a7ddrphy_dfi_p0_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
-assign a7ddrphy_dfi_p1_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
-assign a7ddrphy_dfi_p2_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
-assign a7ddrphy_dfi_p3_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
-assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en_tappeddelayline1;
-always @(*) begin
-    a7ddrphy_dqs_oe <= 1'd0;
-    if (a7ddrphy_wlevel_en_storage) begin
-        a7ddrphy_dqs_oe <= 1'd1;
+assign main_user_enable = 1'd1;
+assign main_user_port_cmd_valid = (user_port_native_0_cmd_valid & main_user_enable);
+assign user_port_native_0_cmd_ready = (main_user_port_cmd_ready & main_user_enable);
+assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we;
+assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
+assign main_user_port_wdata_valid = (user_port_native_0_wdata_valid & main_user_enable);
+assign user_port_native_0_wdata_ready = (main_user_port_wdata_ready & main_user_enable);
+assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we;
+assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data;
+assign user_port_native_0_rdata_valid = (main_user_port_rdata_valid & main_user_enable);
+assign main_user_port_rdata_ready = (user_port_native_0_rdata_ready & main_user_enable);
+assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data;
+assign builder_interface0_adr = main_wb_bus_adr;
+assign builder_interface0_dat_w = main_wb_bus_dat_w;
+assign main_wb_bus_dat_r = builder_interface0_dat_r;
+assign builder_interface0_sel = main_wb_bus_sel;
+assign builder_interface0_cyc = main_wb_bus_cyc;
+assign builder_interface0_stb = main_wb_bus_stb;
+assign main_wb_bus_ack = builder_interface0_ack;
+assign builder_interface0_we = main_wb_bus_we;
+assign builder_interface0_cti = main_wb_bus_cti;
+assign builder_interface0_bte = main_wb_bus_bte;
+assign main_wb_bus_err = builder_interface0_err;
+assign main_reset = (rst | main_rst);
+assign pll_locked = main_locked;
+assign main_clkin = clk;
+assign iodelay_clk = main_clkout_buf0;
+assign sys_clk = main_clkout_buf1;
+assign sys4x_clk = main_clkout_buf2;
+assign sys4x_dqs_clk = main_clkout_buf3;
+assign ddram_ba = main_a7ddrphy_pads_ba;
+assign main_a7ddrphy_dqs_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_oe) | main_a7ddrphy_dqs_postamble);
+assign main_a7ddrphy_dq_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dq_oe) | main_a7ddrphy_dqs_postamble);
+always @(*) begin
+    main_a7ddrphy_dfi_p0_rddata <= 32'd0;
+    main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip04[0];
+    main_a7ddrphy_dfi_p0_rddata[16] <= main_a7ddrphy_bitslip04[1];
+    main_a7ddrphy_dfi_p0_rddata[1] <= main_a7ddrphy_bitslip14[0];
+    main_a7ddrphy_dfi_p0_rddata[17] <= main_a7ddrphy_bitslip14[1];
+    main_a7ddrphy_dfi_p0_rddata[2] <= main_a7ddrphy_bitslip22[0];
+    main_a7ddrphy_dfi_p0_rddata[18] <= main_a7ddrphy_bitslip22[1];
+    main_a7ddrphy_dfi_p0_rddata[3] <= main_a7ddrphy_bitslip32[0];
+    main_a7ddrphy_dfi_p0_rddata[19] <= main_a7ddrphy_bitslip32[1];
+    main_a7ddrphy_dfi_p0_rddata[4] <= main_a7ddrphy_bitslip42[0];
+    main_a7ddrphy_dfi_p0_rddata[20] <= main_a7ddrphy_bitslip42[1];
+    main_a7ddrphy_dfi_p0_rddata[5] <= main_a7ddrphy_bitslip52[0];
+    main_a7ddrphy_dfi_p0_rddata[21] <= main_a7ddrphy_bitslip52[1];
+    main_a7ddrphy_dfi_p0_rddata[6] <= main_a7ddrphy_bitslip62[0];
+    main_a7ddrphy_dfi_p0_rddata[22] <= main_a7ddrphy_bitslip62[1];
+    main_a7ddrphy_dfi_p0_rddata[7] <= main_a7ddrphy_bitslip72[0];
+    main_a7ddrphy_dfi_p0_rddata[23] <= main_a7ddrphy_bitslip72[1];
+    main_a7ddrphy_dfi_p0_rddata[8] <= main_a7ddrphy_bitslip82[0];
+    main_a7ddrphy_dfi_p0_rddata[24] <= main_a7ddrphy_bitslip82[1];
+    main_a7ddrphy_dfi_p0_rddata[9] <= main_a7ddrphy_bitslip92[0];
+    main_a7ddrphy_dfi_p0_rddata[25] <= main_a7ddrphy_bitslip92[1];
+    main_a7ddrphy_dfi_p0_rddata[10] <= main_a7ddrphy_bitslip102[0];
+    main_a7ddrphy_dfi_p0_rddata[26] <= main_a7ddrphy_bitslip102[1];
+    main_a7ddrphy_dfi_p0_rddata[11] <= main_a7ddrphy_bitslip112[0];
+    main_a7ddrphy_dfi_p0_rddata[27] <= main_a7ddrphy_bitslip112[1];
+    main_a7ddrphy_dfi_p0_rddata[12] <= main_a7ddrphy_bitslip122[0];
+    main_a7ddrphy_dfi_p0_rddata[28] <= main_a7ddrphy_bitslip122[1];
+    main_a7ddrphy_dfi_p0_rddata[13] <= main_a7ddrphy_bitslip132[0];
+    main_a7ddrphy_dfi_p0_rddata[29] <= main_a7ddrphy_bitslip132[1];
+    main_a7ddrphy_dfi_p0_rddata[14] <= main_a7ddrphy_bitslip142[0];
+    main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip142[1];
+    main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip152[0];
+    main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip152[1];
+end
+always @(*) begin
+    main_a7ddrphy_dfi_p1_rddata <= 32'd0;
+    main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip04[2];
+    main_a7ddrphy_dfi_p1_rddata[16] <= main_a7ddrphy_bitslip04[3];
+    main_a7ddrphy_dfi_p1_rddata[1] <= main_a7ddrphy_bitslip14[2];
+    main_a7ddrphy_dfi_p1_rddata[17] <= main_a7ddrphy_bitslip14[3];
+    main_a7ddrphy_dfi_p1_rddata[2] <= main_a7ddrphy_bitslip22[2];
+    main_a7ddrphy_dfi_p1_rddata[18] <= main_a7ddrphy_bitslip22[3];
+    main_a7ddrphy_dfi_p1_rddata[3] <= main_a7ddrphy_bitslip32[2];
+    main_a7ddrphy_dfi_p1_rddata[19] <= main_a7ddrphy_bitslip32[3];
+    main_a7ddrphy_dfi_p1_rddata[4] <= main_a7ddrphy_bitslip42[2];
+    main_a7ddrphy_dfi_p1_rddata[20] <= main_a7ddrphy_bitslip42[3];
+    main_a7ddrphy_dfi_p1_rddata[5] <= main_a7ddrphy_bitslip52[2];
+    main_a7ddrphy_dfi_p1_rddata[21] <= main_a7ddrphy_bitslip52[3];
+    main_a7ddrphy_dfi_p1_rddata[6] <= main_a7ddrphy_bitslip62[2];
+    main_a7ddrphy_dfi_p1_rddata[22] <= main_a7ddrphy_bitslip62[3];
+    main_a7ddrphy_dfi_p1_rddata[7] <= main_a7ddrphy_bitslip72[2];
+    main_a7ddrphy_dfi_p1_rddata[23] <= main_a7ddrphy_bitslip72[3];
+    main_a7ddrphy_dfi_p1_rddata[8] <= main_a7ddrphy_bitslip82[2];
+    main_a7ddrphy_dfi_p1_rddata[24] <= main_a7ddrphy_bitslip82[3];
+    main_a7ddrphy_dfi_p1_rddata[9] <= main_a7ddrphy_bitslip92[2];
+    main_a7ddrphy_dfi_p1_rddata[25] <= main_a7ddrphy_bitslip92[3];
+    main_a7ddrphy_dfi_p1_rddata[10] <= main_a7ddrphy_bitslip102[2];
+    main_a7ddrphy_dfi_p1_rddata[26] <= main_a7ddrphy_bitslip102[3];
+    main_a7ddrphy_dfi_p1_rddata[11] <= main_a7ddrphy_bitslip112[2];
+    main_a7ddrphy_dfi_p1_rddata[27] <= main_a7ddrphy_bitslip112[3];
+    main_a7ddrphy_dfi_p1_rddata[12] <= main_a7ddrphy_bitslip122[2];
+    main_a7ddrphy_dfi_p1_rddata[28] <= main_a7ddrphy_bitslip122[3];
+    main_a7ddrphy_dfi_p1_rddata[13] <= main_a7ddrphy_bitslip132[2];
+    main_a7ddrphy_dfi_p1_rddata[29] <= main_a7ddrphy_bitslip132[3];
+    main_a7ddrphy_dfi_p1_rddata[14] <= main_a7ddrphy_bitslip142[2];
+    main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip142[3];
+    main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip152[2];
+    main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip152[3];
+end
+always @(*) begin
+    main_a7ddrphy_dfi_p2_rddata <= 32'd0;
+    main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip04[4];
+    main_a7ddrphy_dfi_p2_rddata[16] <= main_a7ddrphy_bitslip04[5];
+    main_a7ddrphy_dfi_p2_rddata[1] <= main_a7ddrphy_bitslip14[4];
+    main_a7ddrphy_dfi_p2_rddata[17] <= main_a7ddrphy_bitslip14[5];
+    main_a7ddrphy_dfi_p2_rddata[2] <= main_a7ddrphy_bitslip22[4];
+    main_a7ddrphy_dfi_p2_rddata[18] <= main_a7ddrphy_bitslip22[5];
+    main_a7ddrphy_dfi_p2_rddata[3] <= main_a7ddrphy_bitslip32[4];
+    main_a7ddrphy_dfi_p2_rddata[19] <= main_a7ddrphy_bitslip32[5];
+    main_a7ddrphy_dfi_p2_rddata[4] <= main_a7ddrphy_bitslip42[4];
+    main_a7ddrphy_dfi_p2_rddata[20] <= main_a7ddrphy_bitslip42[5];
+    main_a7ddrphy_dfi_p2_rddata[5] <= main_a7ddrphy_bitslip52[4];
+    main_a7ddrphy_dfi_p2_rddata[21] <= main_a7ddrphy_bitslip52[5];
+    main_a7ddrphy_dfi_p2_rddata[6] <= main_a7ddrphy_bitslip62[4];
+    main_a7ddrphy_dfi_p2_rddata[22] <= main_a7ddrphy_bitslip62[5];
+    main_a7ddrphy_dfi_p2_rddata[7] <= main_a7ddrphy_bitslip72[4];
+    main_a7ddrphy_dfi_p2_rddata[23] <= main_a7ddrphy_bitslip72[5];
+    main_a7ddrphy_dfi_p2_rddata[8] <= main_a7ddrphy_bitslip82[4];
+    main_a7ddrphy_dfi_p2_rddata[24] <= main_a7ddrphy_bitslip82[5];
+    main_a7ddrphy_dfi_p2_rddata[9] <= main_a7ddrphy_bitslip92[4];
+    main_a7ddrphy_dfi_p2_rddata[25] <= main_a7ddrphy_bitslip92[5];
+    main_a7ddrphy_dfi_p2_rddata[10] <= main_a7ddrphy_bitslip102[4];
+    main_a7ddrphy_dfi_p2_rddata[26] <= main_a7ddrphy_bitslip102[5];
+    main_a7ddrphy_dfi_p2_rddata[11] <= main_a7ddrphy_bitslip112[4];
+    main_a7ddrphy_dfi_p2_rddata[27] <= main_a7ddrphy_bitslip112[5];
+    main_a7ddrphy_dfi_p2_rddata[12] <= main_a7ddrphy_bitslip122[4];
+    main_a7ddrphy_dfi_p2_rddata[28] <= main_a7ddrphy_bitslip122[5];
+    main_a7ddrphy_dfi_p2_rddata[13] <= main_a7ddrphy_bitslip132[4];
+    main_a7ddrphy_dfi_p2_rddata[29] <= main_a7ddrphy_bitslip132[5];
+    main_a7ddrphy_dfi_p2_rddata[14] <= main_a7ddrphy_bitslip142[4];
+    main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip142[5];
+    main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip152[4];
+    main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip152[5];
+end
+always @(*) begin
+    main_a7ddrphy_dfi_p3_rddata <= 32'd0;
+    main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip04[6];
+    main_a7ddrphy_dfi_p3_rddata[16] <= main_a7ddrphy_bitslip04[7];
+    main_a7ddrphy_dfi_p3_rddata[1] <= main_a7ddrphy_bitslip14[6];
+    main_a7ddrphy_dfi_p3_rddata[17] <= main_a7ddrphy_bitslip14[7];
+    main_a7ddrphy_dfi_p3_rddata[2] <= main_a7ddrphy_bitslip22[6];
+    main_a7ddrphy_dfi_p3_rddata[18] <= main_a7ddrphy_bitslip22[7];
+    main_a7ddrphy_dfi_p3_rddata[3] <= main_a7ddrphy_bitslip32[6];
+    main_a7ddrphy_dfi_p3_rddata[19] <= main_a7ddrphy_bitslip32[7];
+    main_a7ddrphy_dfi_p3_rddata[4] <= main_a7ddrphy_bitslip42[6];
+    main_a7ddrphy_dfi_p3_rddata[20] <= main_a7ddrphy_bitslip42[7];
+    main_a7ddrphy_dfi_p3_rddata[5] <= main_a7ddrphy_bitslip52[6];
+    main_a7ddrphy_dfi_p3_rddata[21] <= main_a7ddrphy_bitslip52[7];
+    main_a7ddrphy_dfi_p3_rddata[6] <= main_a7ddrphy_bitslip62[6];
+    main_a7ddrphy_dfi_p3_rddata[22] <= main_a7ddrphy_bitslip62[7];
+    main_a7ddrphy_dfi_p3_rddata[7] <= main_a7ddrphy_bitslip72[6];
+    main_a7ddrphy_dfi_p3_rddata[23] <= main_a7ddrphy_bitslip72[7];
+    main_a7ddrphy_dfi_p3_rddata[8] <= main_a7ddrphy_bitslip82[6];
+    main_a7ddrphy_dfi_p3_rddata[24] <= main_a7ddrphy_bitslip82[7];
+    main_a7ddrphy_dfi_p3_rddata[9] <= main_a7ddrphy_bitslip92[6];
+    main_a7ddrphy_dfi_p3_rddata[25] <= main_a7ddrphy_bitslip92[7];
+    main_a7ddrphy_dfi_p3_rddata[10] <= main_a7ddrphy_bitslip102[6];
+    main_a7ddrphy_dfi_p3_rddata[26] <= main_a7ddrphy_bitslip102[7];
+    main_a7ddrphy_dfi_p3_rddata[11] <= main_a7ddrphy_bitslip112[6];
+    main_a7ddrphy_dfi_p3_rddata[27] <= main_a7ddrphy_bitslip112[7];
+    main_a7ddrphy_dfi_p3_rddata[12] <= main_a7ddrphy_bitslip122[6];
+    main_a7ddrphy_dfi_p3_rddata[28] <= main_a7ddrphy_bitslip122[7];
+    main_a7ddrphy_dfi_p3_rddata[13] <= main_a7ddrphy_bitslip132[6];
+    main_a7ddrphy_dfi_p3_rddata[29] <= main_a7ddrphy_bitslip132[7];
+    main_a7ddrphy_dfi_p3_rddata[14] <= main_a7ddrphy_bitslip142[6];
+    main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip142[7];
+    main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip152[6];
+    main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip152[7];
+end
+assign main_a7ddrphy_dfi_p0_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
+assign main_a7ddrphy_dfi_p1_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
+assign main_a7ddrphy_dfi_p2_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
+assign main_a7ddrphy_dfi_p3_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
+assign main_a7ddrphy_dq_oe = main_a7ddrphy_wrdata_en_tappeddelayline1;
+always @(*) begin
+    main_a7ddrphy_dqs_oe <= 1'd0;
+    if (main_a7ddrphy_wlevel_en_storage) begin
+        main_a7ddrphy_dqs_oe <= 1'd1;
     end else begin
-        a7ddrphy_dqs_oe <= a7ddrphy_dq_oe;
+        main_a7ddrphy_dqs_oe <= main_a7ddrphy_dq_oe;
     end
 end
-assign a7ddrphy_dqs_preamble = (a7ddrphy_wrdata_en_tappeddelayline0 & (~a7ddrphy_wrdata_en_tappeddelayline1));
-assign a7ddrphy_dqs_postamble = (a7ddrphy_wrdata_en_tappeddelayline2 & (~a7ddrphy_wrdata_en_tappeddelayline1));
+assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_wrdata_en_tappeddelayline0 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
+assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_wrdata_en_tappeddelayline2 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
 always @(*) begin
-    a7ddrphy_dqspattern_o0 <= 8'd0;
-    a7ddrphy_dqspattern_o0 <= 7'd85;
-    if (a7ddrphy_dqspattern0) begin
-        a7ddrphy_dqspattern_o0 <= 5'd21;
+    main_a7ddrphy_dqspattern_o0 <= 8'd0;
+    main_a7ddrphy_dqspattern_o0 <= 7'd85;
+    if (main_a7ddrphy_dqspattern0) begin
+        main_a7ddrphy_dqspattern_o0 <= 5'd21;
     end
-    if (a7ddrphy_dqspattern1) begin
-        a7ddrphy_dqspattern_o0 <= 7'd84;
+    if (main_a7ddrphy_dqspattern1) begin
+        main_a7ddrphy_dqspattern_o0 <= 7'd84;
     end
-    if (a7ddrphy_wlevel_en_storage) begin
-        a7ddrphy_dqspattern_o0 <= 1'd0;
-        if (a7ddrphy_wlevel_strobe_re) begin
-            a7ddrphy_dqspattern_o0 <= 1'd1;
+    if (main_a7ddrphy_wlevel_en_storage) begin
+        main_a7ddrphy_dqspattern_o0 <= 1'd0;
+        if (main_a7ddrphy_wlevel_strobe_re) begin
+            main_a7ddrphy_dqspattern_o0 <= 1'd1;
         end
     end
 end
 always @(*) begin
-    a7ddrphy_bitslip00 <= 8'd0;
-    case (a7ddrphy_bitslip0_value0)
+    main_a7ddrphy_bitslip00 <= 8'd0;
+    case (main_a7ddrphy_bitslip0_value0)
         1'd0: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip10 <= 8'd0;
-    case (a7ddrphy_bitslip1_value0)
+    main_a7ddrphy_bitslip10 <= 8'd0;
+    case (main_a7ddrphy_bitslip1_value0)
         1'd0: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip01 <= 8'd0;
-    case (a7ddrphy_bitslip0_value1)
+    main_a7ddrphy_bitslip01 <= 8'd0;
+    case (main_a7ddrphy_bitslip0_value1)
         1'd0: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip11 <= 8'd0;
-    case (a7ddrphy_bitslip1_value1)
+    main_a7ddrphy_bitslip11 <= 8'd0;
+    case (main_a7ddrphy_bitslip1_value1)
         1'd0: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip02 <= 8'd0;
-    case (a7ddrphy_bitslip0_value2)
+    main_a7ddrphy_bitslip02 <= 8'd0;
+    case (main_a7ddrphy_bitslip0_value2)
         1'd0: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip04 <= 8'd0;
-    case (a7ddrphy_bitslip0_value3)
+    main_a7ddrphy_bitslip04 <= 8'd0;
+    case (main_a7ddrphy_bitslip0_value3)
         1'd0: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip12 <= 8'd0;
-    case (a7ddrphy_bitslip1_value2)
+    main_a7ddrphy_bitslip12 <= 8'd0;
+    case (main_a7ddrphy_bitslip1_value2)
         1'd0: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip14 <= 8'd0;
-    case (a7ddrphy_bitslip1_value3)
+    main_a7ddrphy_bitslip14 <= 8'd0;
+    case (main_a7ddrphy_bitslip1_value3)
         1'd0: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip20 <= 8'd0;
-    case (a7ddrphy_bitslip2_value0)
+    main_a7ddrphy_bitslip20 <= 8'd0;
+    case (main_a7ddrphy_bitslip2_value0)
         1'd0: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip22 <= 8'd0;
-    case (a7ddrphy_bitslip2_value1)
+    main_a7ddrphy_bitslip22 <= 8'd0;
+    case (main_a7ddrphy_bitslip2_value1)
         1'd0: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip30 <= 8'd0;
-    case (a7ddrphy_bitslip3_value0)
+    main_a7ddrphy_bitslip30 <= 8'd0;
+    case (main_a7ddrphy_bitslip3_value0)
         1'd0: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip32 <= 8'd0;
-    case (a7ddrphy_bitslip3_value1)
+    main_a7ddrphy_bitslip32 <= 8'd0;
+    case (main_a7ddrphy_bitslip3_value1)
         1'd0: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip40 <= 8'd0;
-    case (a7ddrphy_bitslip4_value0)
+    main_a7ddrphy_bitslip40 <= 8'd0;
+    case (main_a7ddrphy_bitslip4_value0)
         1'd0: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip42 <= 8'd0;
-    case (a7ddrphy_bitslip4_value1)
+    main_a7ddrphy_bitslip42 <= 8'd0;
+    case (main_a7ddrphy_bitslip4_value1)
         1'd0: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip50 <= 8'd0;
-    case (a7ddrphy_bitslip5_value0)
+    main_a7ddrphy_bitslip50 <= 8'd0;
+    case (main_a7ddrphy_bitslip5_value0)
         1'd0: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip52 <= 8'd0;
-    case (a7ddrphy_bitslip5_value1)
+    main_a7ddrphy_bitslip52 <= 8'd0;
+    case (main_a7ddrphy_bitslip5_value1)
         1'd0: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip60 <= 8'd0;
-    case (a7ddrphy_bitslip6_value0)
+    main_a7ddrphy_bitslip60 <= 8'd0;
+    case (main_a7ddrphy_bitslip6_value0)
         1'd0: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip62 <= 8'd0;
-    case (a7ddrphy_bitslip6_value1)
+    main_a7ddrphy_bitslip62 <= 8'd0;
+    case (main_a7ddrphy_bitslip6_value1)
         1'd0: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip70 <= 8'd0;
-    case (a7ddrphy_bitslip7_value0)
+    main_a7ddrphy_bitslip70 <= 8'd0;
+    case (main_a7ddrphy_bitslip7_value0)
         1'd0: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip72 <= 8'd0;
-    case (a7ddrphy_bitslip7_value1)
+    main_a7ddrphy_bitslip72 <= 8'd0;
+    case (main_a7ddrphy_bitslip7_value1)
         1'd0: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip80 <= 8'd0;
-    case (a7ddrphy_bitslip8_value0)
+    main_a7ddrphy_bitslip80 <= 8'd0;
+    case (main_a7ddrphy_bitslip8_value0)
         1'd0: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip82 <= 8'd0;
-    case (a7ddrphy_bitslip8_value1)
+    main_a7ddrphy_bitslip82 <= 8'd0;
+    case (main_a7ddrphy_bitslip8_value1)
         1'd0: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip90 <= 8'd0;
-    case (a7ddrphy_bitslip9_value0)
+    main_a7ddrphy_bitslip90 <= 8'd0;
+    case (main_a7ddrphy_bitslip9_value0)
         1'd0: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip92 <= 8'd0;
-    case (a7ddrphy_bitslip9_value1)
+    main_a7ddrphy_bitslip92 <= 8'd0;
+    case (main_a7ddrphy_bitslip9_value1)
         1'd0: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip100 <= 8'd0;
-    case (a7ddrphy_bitslip10_value0)
+    main_a7ddrphy_bitslip100 <= 8'd0;
+    case (main_a7ddrphy_bitslip10_value0)
         1'd0: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip102 <= 8'd0;
-    case (a7ddrphy_bitslip10_value1)
+    main_a7ddrphy_bitslip102 <= 8'd0;
+    case (main_a7ddrphy_bitslip10_value1)
         1'd0: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip110 <= 8'd0;
-    case (a7ddrphy_bitslip11_value0)
+    main_a7ddrphy_bitslip110 <= 8'd0;
+    case (main_a7ddrphy_bitslip11_value0)
         1'd0: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip112 <= 8'd0;
-    case (a7ddrphy_bitslip11_value1)
+    main_a7ddrphy_bitslip112 <= 8'd0;
+    case (main_a7ddrphy_bitslip11_value1)
         1'd0: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip120 <= 8'd0;
-    case (a7ddrphy_bitslip12_value0)
+    main_a7ddrphy_bitslip120 <= 8'd0;
+    case (main_a7ddrphy_bitslip12_value0)
         1'd0: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip122 <= 8'd0;
-    case (a7ddrphy_bitslip12_value1)
+    main_a7ddrphy_bitslip122 <= 8'd0;
+    case (main_a7ddrphy_bitslip12_value1)
         1'd0: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip130 <= 8'd0;
-    case (a7ddrphy_bitslip13_value0)
+    main_a7ddrphy_bitslip130 <= 8'd0;
+    case (main_a7ddrphy_bitslip13_value0)
         1'd0: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip132 <= 8'd0;
-    case (a7ddrphy_bitslip13_value1)
+    main_a7ddrphy_bitslip132 <= 8'd0;
+    case (main_a7ddrphy_bitslip13_value1)
         1'd0: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip140 <= 8'd0;
-    case (a7ddrphy_bitslip14_value0)
+    main_a7ddrphy_bitslip140 <= 8'd0;
+    case (main_a7ddrphy_bitslip14_value0)
         1'd0: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip142 <= 8'd0;
-    case (a7ddrphy_bitslip14_value1)
+    main_a7ddrphy_bitslip142 <= 8'd0;
+    case (main_a7ddrphy_bitslip14_value1)
         1'd0: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip150 <= 8'd0;
-    case (a7ddrphy_bitslip15_value0)
+    main_a7ddrphy_bitslip150 <= 8'd0;
+    case (main_a7ddrphy_bitslip15_value0)
         1'd0: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip152 <= 8'd0;
-    case (a7ddrphy_bitslip15_value1)
+    main_a7ddrphy_bitslip152 <= 8'd0;
+    case (main_a7ddrphy_bitslip15_value1)
         1'd0: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1];
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2];
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3];
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4];
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5];
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6];
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7];
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8];
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[15:8];
         end
     endcase
 end
-assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address;
-assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
-assign a7ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n;
-assign a7ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n;
-assign a7ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n;
-assign a7ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n;
-assign a7ddrphy_dfi_p0_cke = litedramcore_master_p0_cke;
-assign a7ddrphy_dfi_p0_odt = litedramcore_master_p0_odt;
-assign a7ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n;
-assign a7ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n;
-assign a7ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata;
-assign a7ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en;
-assign a7ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask;
-assign a7ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en;
-assign litedramcore_master_p0_rddata = a7ddrphy_dfi_p0_rddata;
-assign litedramcore_master_p0_rddata_valid = a7ddrphy_dfi_p0_rddata_valid;
-assign a7ddrphy_dfi_p1_address = litedramcore_master_p1_address;
-assign a7ddrphy_dfi_p1_bank = litedramcore_master_p1_bank;
-assign a7ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n;
-assign a7ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n;
-assign a7ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n;
-assign a7ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n;
-assign a7ddrphy_dfi_p1_cke = litedramcore_master_p1_cke;
-assign a7ddrphy_dfi_p1_odt = litedramcore_master_p1_odt;
-assign a7ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n;
-assign a7ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n;
-assign a7ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata;
-assign a7ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en;
-assign a7ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask;
-assign a7ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en;
-assign litedramcore_master_p1_rddata = a7ddrphy_dfi_p1_rddata;
-assign litedramcore_master_p1_rddata_valid = a7ddrphy_dfi_p1_rddata_valid;
-assign a7ddrphy_dfi_p2_address = litedramcore_master_p2_address;
-assign a7ddrphy_dfi_p2_bank = litedramcore_master_p2_bank;
-assign a7ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n;
-assign a7ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n;
-assign a7ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n;
-assign a7ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n;
-assign a7ddrphy_dfi_p2_cke = litedramcore_master_p2_cke;
-assign a7ddrphy_dfi_p2_odt = litedramcore_master_p2_odt;
-assign a7ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n;
-assign a7ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n;
-assign a7ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata;
-assign a7ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en;
-assign a7ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask;
-assign a7ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en;
-assign litedramcore_master_p2_rddata = a7ddrphy_dfi_p2_rddata;
-assign litedramcore_master_p2_rddata_valid = a7ddrphy_dfi_p2_rddata_valid;
-assign a7ddrphy_dfi_p3_address = litedramcore_master_p3_address;
-assign a7ddrphy_dfi_p3_bank = litedramcore_master_p3_bank;
-assign a7ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n;
-assign a7ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n;
-assign a7ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n;
-assign a7ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n;
-assign a7ddrphy_dfi_p3_cke = litedramcore_master_p3_cke;
-assign a7ddrphy_dfi_p3_odt = litedramcore_master_p3_odt;
-assign a7ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n;
-assign a7ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n;
-assign a7ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata;
-assign a7ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en;
-assign a7ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask;
-assign a7ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en;
-assign litedramcore_master_p3_rddata = a7ddrphy_dfi_p3_rddata;
-assign litedramcore_master_p3_rddata_valid = a7ddrphy_dfi_p3_rddata_valid;
-assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address;
-assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank;
-assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n;
-assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n;
-assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n;
-assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n;
-assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke;
-assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt;
-assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n;
-assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n;
-assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata;
-assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en;
-assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask;
-assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en;
-assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata;
-assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid;
-assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address;
-assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank;
-assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n;
-assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n;
-assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n;
-assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n;
-assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke;
-assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt;
-assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n;
-assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n;
-assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata;
-assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en;
-assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask;
-assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en;
-assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata;
-assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid;
-assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address;
-assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank;
-assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n;
-assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n;
-assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n;
-assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n;
-assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke;
-assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt;
-assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n;
-assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n;
-assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata;
-assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en;
-assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask;
-assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en;
-assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata;
-assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid;
-assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address;
-assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank;
-assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n;
-assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n;
-assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n;
-assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n;
-assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke;
-assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt;
-assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n;
-assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n;
-assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata;
-assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en;
-assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask;
-assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en;
-assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
-assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;
-always @(*) begin
-    litedramcore_master_p3_ras_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n;
+assign main_a7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address;
+assign main_a7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank;
+assign main_a7ddrphy_dfi_p0_cas_n = main_litedramcore_master_p0_cas_n;
+assign main_a7ddrphy_dfi_p0_cs_n = main_litedramcore_master_p0_cs_n;
+assign main_a7ddrphy_dfi_p0_ras_n = main_litedramcore_master_p0_ras_n;
+assign main_a7ddrphy_dfi_p0_we_n = main_litedramcore_master_p0_we_n;
+assign main_a7ddrphy_dfi_p0_cke = main_litedramcore_master_p0_cke;
+assign main_a7ddrphy_dfi_p0_odt = main_litedramcore_master_p0_odt;
+assign main_a7ddrphy_dfi_p0_reset_n = main_litedramcore_master_p0_reset_n;
+assign main_a7ddrphy_dfi_p0_act_n = main_litedramcore_master_p0_act_n;
+assign main_a7ddrphy_dfi_p0_wrdata = main_litedramcore_master_p0_wrdata;
+assign main_a7ddrphy_dfi_p0_wrdata_en = main_litedramcore_master_p0_wrdata_en;
+assign main_a7ddrphy_dfi_p0_wrdata_mask = main_litedramcore_master_p0_wrdata_mask;
+assign main_a7ddrphy_dfi_p0_rddata_en = main_litedramcore_master_p0_rddata_en;
+assign main_litedramcore_master_p0_rddata = main_a7ddrphy_dfi_p0_rddata;
+assign main_litedramcore_master_p0_rddata_valid = main_a7ddrphy_dfi_p0_rddata_valid;
+assign main_a7ddrphy_dfi_p1_address = main_litedramcore_master_p1_address;
+assign main_a7ddrphy_dfi_p1_bank = main_litedramcore_master_p1_bank;
+assign main_a7ddrphy_dfi_p1_cas_n = main_litedramcore_master_p1_cas_n;
+assign main_a7ddrphy_dfi_p1_cs_n = main_litedramcore_master_p1_cs_n;
+assign main_a7ddrphy_dfi_p1_ras_n = main_litedramcore_master_p1_ras_n;
+assign main_a7ddrphy_dfi_p1_we_n = main_litedramcore_master_p1_we_n;
+assign main_a7ddrphy_dfi_p1_cke = main_litedramcore_master_p1_cke;
+assign main_a7ddrphy_dfi_p1_odt = main_litedramcore_master_p1_odt;
+assign main_a7ddrphy_dfi_p1_reset_n = main_litedramcore_master_p1_reset_n;
+assign main_a7ddrphy_dfi_p1_act_n = main_litedramcore_master_p1_act_n;
+assign main_a7ddrphy_dfi_p1_wrdata = main_litedramcore_master_p1_wrdata;
+assign main_a7ddrphy_dfi_p1_wrdata_en = main_litedramcore_master_p1_wrdata_en;
+assign main_a7ddrphy_dfi_p1_wrdata_mask = main_litedramcore_master_p1_wrdata_mask;
+assign main_a7ddrphy_dfi_p1_rddata_en = main_litedramcore_master_p1_rddata_en;
+assign main_litedramcore_master_p1_rddata = main_a7ddrphy_dfi_p1_rddata;
+assign main_litedramcore_master_p1_rddata_valid = main_a7ddrphy_dfi_p1_rddata_valid;
+assign main_a7ddrphy_dfi_p2_address = main_litedramcore_master_p2_address;
+assign main_a7ddrphy_dfi_p2_bank = main_litedramcore_master_p2_bank;
+assign main_a7ddrphy_dfi_p2_cas_n = main_litedramcore_master_p2_cas_n;
+assign main_a7ddrphy_dfi_p2_cs_n = main_litedramcore_master_p2_cs_n;
+assign main_a7ddrphy_dfi_p2_ras_n = main_litedramcore_master_p2_ras_n;
+assign main_a7ddrphy_dfi_p2_we_n = main_litedramcore_master_p2_we_n;
+assign main_a7ddrphy_dfi_p2_cke = main_litedramcore_master_p2_cke;
+assign main_a7ddrphy_dfi_p2_odt = main_litedramcore_master_p2_odt;
+assign main_a7ddrphy_dfi_p2_reset_n = main_litedramcore_master_p2_reset_n;
+assign main_a7ddrphy_dfi_p2_act_n = main_litedramcore_master_p2_act_n;
+assign main_a7ddrphy_dfi_p2_wrdata = main_litedramcore_master_p2_wrdata;
+assign main_a7ddrphy_dfi_p2_wrdata_en = main_litedramcore_master_p2_wrdata_en;
+assign main_a7ddrphy_dfi_p2_wrdata_mask = main_litedramcore_master_p2_wrdata_mask;
+assign main_a7ddrphy_dfi_p2_rddata_en = main_litedramcore_master_p2_rddata_en;
+assign main_litedramcore_master_p2_rddata = main_a7ddrphy_dfi_p2_rddata;
+assign main_litedramcore_master_p2_rddata_valid = main_a7ddrphy_dfi_p2_rddata_valid;
+assign main_a7ddrphy_dfi_p3_address = main_litedramcore_master_p3_address;
+assign main_a7ddrphy_dfi_p3_bank = main_litedramcore_master_p3_bank;
+assign main_a7ddrphy_dfi_p3_cas_n = main_litedramcore_master_p3_cas_n;
+assign main_a7ddrphy_dfi_p3_cs_n = main_litedramcore_master_p3_cs_n;
+assign main_a7ddrphy_dfi_p3_ras_n = main_litedramcore_master_p3_ras_n;
+assign main_a7ddrphy_dfi_p3_we_n = main_litedramcore_master_p3_we_n;
+assign main_a7ddrphy_dfi_p3_cke = main_litedramcore_master_p3_cke;
+assign main_a7ddrphy_dfi_p3_odt = main_litedramcore_master_p3_odt;
+assign main_a7ddrphy_dfi_p3_reset_n = main_litedramcore_master_p3_reset_n;
+assign main_a7ddrphy_dfi_p3_act_n = main_litedramcore_master_p3_act_n;
+assign main_a7ddrphy_dfi_p3_wrdata = main_litedramcore_master_p3_wrdata;
+assign main_a7ddrphy_dfi_p3_wrdata_en = main_litedramcore_master_p3_wrdata_en;
+assign main_a7ddrphy_dfi_p3_wrdata_mask = main_litedramcore_master_p3_wrdata_mask;
+assign main_a7ddrphy_dfi_p3_rddata_en = main_litedramcore_master_p3_rddata_en;
+assign main_litedramcore_master_p3_rddata = main_a7ddrphy_dfi_p3_rddata;
+assign main_litedramcore_master_p3_rddata_valid = main_a7ddrphy_dfi_p3_rddata_valid;
+assign main_litedramcore_slave_p0_address = main_litedramcore_dfi_p0_address;
+assign main_litedramcore_slave_p0_bank = main_litedramcore_dfi_p0_bank;
+assign main_litedramcore_slave_p0_cas_n = main_litedramcore_dfi_p0_cas_n;
+assign main_litedramcore_slave_p0_cs_n = main_litedramcore_dfi_p0_cs_n;
+assign main_litedramcore_slave_p0_ras_n = main_litedramcore_dfi_p0_ras_n;
+assign main_litedramcore_slave_p0_we_n = main_litedramcore_dfi_p0_we_n;
+assign main_litedramcore_slave_p0_cke = main_litedramcore_dfi_p0_cke;
+assign main_litedramcore_slave_p0_odt = main_litedramcore_dfi_p0_odt;
+assign main_litedramcore_slave_p0_reset_n = main_litedramcore_dfi_p0_reset_n;
+assign main_litedramcore_slave_p0_act_n = main_litedramcore_dfi_p0_act_n;
+assign main_litedramcore_slave_p0_wrdata = main_litedramcore_dfi_p0_wrdata;
+assign main_litedramcore_slave_p0_wrdata_en = main_litedramcore_dfi_p0_wrdata_en;
+assign main_litedramcore_slave_p0_wrdata_mask = main_litedramcore_dfi_p0_wrdata_mask;
+assign main_litedramcore_slave_p0_rddata_en = main_litedramcore_dfi_p0_rddata_en;
+assign main_litedramcore_dfi_p0_rddata = main_litedramcore_slave_p0_rddata;
+assign main_litedramcore_dfi_p0_rddata_valid = main_litedramcore_slave_p0_rddata_valid;
+assign main_litedramcore_slave_p1_address = main_litedramcore_dfi_p1_address;
+assign main_litedramcore_slave_p1_bank = main_litedramcore_dfi_p1_bank;
+assign main_litedramcore_slave_p1_cas_n = main_litedramcore_dfi_p1_cas_n;
+assign main_litedramcore_slave_p1_cs_n = main_litedramcore_dfi_p1_cs_n;
+assign main_litedramcore_slave_p1_ras_n = main_litedramcore_dfi_p1_ras_n;
+assign main_litedramcore_slave_p1_we_n = main_litedramcore_dfi_p1_we_n;
+assign main_litedramcore_slave_p1_cke = main_litedramcore_dfi_p1_cke;
+assign main_litedramcore_slave_p1_odt = main_litedramcore_dfi_p1_odt;
+assign main_litedramcore_slave_p1_reset_n = main_litedramcore_dfi_p1_reset_n;
+assign main_litedramcore_slave_p1_act_n = main_litedramcore_dfi_p1_act_n;
+assign main_litedramcore_slave_p1_wrdata = main_litedramcore_dfi_p1_wrdata;
+assign main_litedramcore_slave_p1_wrdata_en = main_litedramcore_dfi_p1_wrdata_en;
+assign main_litedramcore_slave_p1_wrdata_mask = main_litedramcore_dfi_p1_wrdata_mask;
+assign main_litedramcore_slave_p1_rddata_en = main_litedramcore_dfi_p1_rddata_en;
+assign main_litedramcore_dfi_p1_rddata = main_litedramcore_slave_p1_rddata;
+assign main_litedramcore_dfi_p1_rddata_valid = main_litedramcore_slave_p1_rddata_valid;
+assign main_litedramcore_slave_p2_address = main_litedramcore_dfi_p2_address;
+assign main_litedramcore_slave_p2_bank = main_litedramcore_dfi_p2_bank;
+assign main_litedramcore_slave_p2_cas_n = main_litedramcore_dfi_p2_cas_n;
+assign main_litedramcore_slave_p2_cs_n = main_litedramcore_dfi_p2_cs_n;
+assign main_litedramcore_slave_p2_ras_n = main_litedramcore_dfi_p2_ras_n;
+assign main_litedramcore_slave_p2_we_n = main_litedramcore_dfi_p2_we_n;
+assign main_litedramcore_slave_p2_cke = main_litedramcore_dfi_p2_cke;
+assign main_litedramcore_slave_p2_odt = main_litedramcore_dfi_p2_odt;
+assign main_litedramcore_slave_p2_reset_n = main_litedramcore_dfi_p2_reset_n;
+assign main_litedramcore_slave_p2_act_n = main_litedramcore_dfi_p2_act_n;
+assign main_litedramcore_slave_p2_wrdata = main_litedramcore_dfi_p2_wrdata;
+assign main_litedramcore_slave_p2_wrdata_en = main_litedramcore_dfi_p2_wrdata_en;
+assign main_litedramcore_slave_p2_wrdata_mask = main_litedramcore_dfi_p2_wrdata_mask;
+assign main_litedramcore_slave_p2_rddata_en = main_litedramcore_dfi_p2_rddata_en;
+assign main_litedramcore_dfi_p2_rddata = main_litedramcore_slave_p2_rddata;
+assign main_litedramcore_dfi_p2_rddata_valid = main_litedramcore_slave_p2_rddata_valid;
+assign main_litedramcore_slave_p3_address = main_litedramcore_dfi_p3_address;
+assign main_litedramcore_slave_p3_bank = main_litedramcore_dfi_p3_bank;
+assign main_litedramcore_slave_p3_cas_n = main_litedramcore_dfi_p3_cas_n;
+assign main_litedramcore_slave_p3_cs_n = main_litedramcore_dfi_p3_cs_n;
+assign main_litedramcore_slave_p3_ras_n = main_litedramcore_dfi_p3_ras_n;
+assign main_litedramcore_slave_p3_we_n = main_litedramcore_dfi_p3_we_n;
+assign main_litedramcore_slave_p3_cke = main_litedramcore_dfi_p3_cke;
+assign main_litedramcore_slave_p3_odt = main_litedramcore_dfi_p3_odt;
+assign main_litedramcore_slave_p3_reset_n = main_litedramcore_dfi_p3_reset_n;
+assign main_litedramcore_slave_p3_act_n = main_litedramcore_dfi_p3_act_n;
+assign main_litedramcore_slave_p3_wrdata = main_litedramcore_dfi_p3_wrdata;
+assign main_litedramcore_slave_p3_wrdata_en = main_litedramcore_dfi_p3_wrdata_en;
+assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_mask;
+assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en;
+assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata;
+assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid;
+always @(*) begin
+    main_litedramcore_master_p3_ras_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_ras_n <= main_litedramcore_ext_dfi_p3_ras_n;
         end else begin
-            litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
+            main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n;
         end
     end else begin
-        litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n;
+        main_litedramcore_master_p3_ras_n <= main_litedramcore_csr_dfi_p3_ras_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_we_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n;
+    main_litedramcore_master_p3_we_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_we_n <= main_litedramcore_ext_dfi_p3_we_n;
         end else begin
-            litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
+            main_litedramcore_master_p3_we_n <= main_litedramcore_slave_p3_we_n;
         end
     end else begin
-        litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n;
+        main_litedramcore_master_p3_we_n <= main_litedramcore_csr_dfi_p3_we_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_cke <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke;
+    main_litedramcore_master_p3_cke <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_cke <= main_litedramcore_ext_dfi_p3_cke;
         end else begin
-            litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
+            main_litedramcore_master_p3_cke <= main_litedramcore_slave_p3_cke;
         end
     end else begin
-        litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke;
+        main_litedramcore_master_p3_cke <= main_litedramcore_csr_dfi_p3_cke;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_odt <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt;
+    main_litedramcore_master_p3_odt <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_odt <= main_litedramcore_ext_dfi_p3_odt;
         end else begin
-            litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
+            main_litedramcore_master_p3_odt <= main_litedramcore_slave_p3_odt;
         end
     end else begin
-        litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt;
+        main_litedramcore_master_p3_odt <= main_litedramcore_csr_dfi_p3_odt;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_reset_n <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n;
+    main_litedramcore_master_p3_reset_n <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_reset_n <= main_litedramcore_ext_dfi_p3_reset_n;
         end else begin
-            litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
+            main_litedramcore_master_p3_reset_n <= main_litedramcore_slave_p3_reset_n;
         end
     end else begin
-        litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n;
+        main_litedramcore_master_p3_reset_n <= main_litedramcore_csr_dfi_p3_reset_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_act_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n;
+    main_litedramcore_master_p3_act_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_act_n <= main_litedramcore_ext_dfi_p3_act_n;
         end else begin
-            litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
+            main_litedramcore_master_p3_act_n <= main_litedramcore_slave_p3_act_n;
         end
     end else begin
-        litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n;
+        main_litedramcore_master_p3_act_n <= main_litedramcore_csr_dfi_p3_act_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_wrdata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata;
+    main_litedramcore_master_p3_wrdata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_wrdata <= main_litedramcore_ext_dfi_p3_wrdata;
         end else begin
-            litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
+            main_litedramcore_master_p3_wrdata <= main_litedramcore_slave_p3_wrdata;
         end
     end else begin
-        litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata;
+        main_litedramcore_master_p3_wrdata <= main_litedramcore_csr_dfi_p3_wrdata;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_wrdata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en;
+    main_litedramcore_master_p3_wrdata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_wrdata_en <= main_litedramcore_ext_dfi_p3_wrdata_en;
         end else begin
-            litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
+            main_litedramcore_master_p3_wrdata_en <= main_litedramcore_slave_p3_wrdata_en;
         end
     end else begin
-        litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en;
+        main_litedramcore_master_p3_wrdata_en <= main_litedramcore_csr_dfi_p3_wrdata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_wrdata_mask <= 4'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask;
+    main_litedramcore_master_p3_wrdata_mask <= 4'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_ext_dfi_p3_wrdata_mask;
         end else begin
-            litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
+            main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_slave_p3_wrdata_mask;
         end
     end else begin
-        litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask;
+        main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_csr_dfi_p3_wrdata_mask;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_rddata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en;
+    main_litedramcore_master_p3_rddata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_rddata_en <= main_litedramcore_ext_dfi_p3_rddata_en;
         end else begin
-            litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
+            main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en;
         end
     end else begin
-        litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en;
+        main_litedramcore_master_p3_rddata_en <= main_litedramcore_csr_dfi_p3_rddata_en;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p0_rddata <= 32'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p0_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata;
+        main_litedramcore_csr_dfi_p0_rddata <= main_litedramcore_master_p0_rddata;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+        main_litedramcore_csr_dfi_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p1_rddata <= 32'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p1_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+        main_litedramcore_csr_dfi_p1_rddata <= main_litedramcore_master_p1_rddata;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+        main_litedramcore_csr_dfi_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p2_rddata <= 32'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p2_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata;
+        main_litedramcore_csr_dfi_p2_rddata <= main_litedramcore_master_p2_rddata;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+        main_litedramcore_csr_dfi_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p3_rddata <= 32'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p3_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata;
+        main_litedramcore_csr_dfi_p3_rddata <= main_litedramcore_master_p3_rddata;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+        main_litedramcore_csr_dfi_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p0_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata;
+    main_litedramcore_ext_dfi_p0_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p0_rddata <= main_litedramcore_master_p0_rddata;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+    main_litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p1_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+    main_litedramcore_ext_dfi_p1_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p1_rddata <= main_litedramcore_master_p1_rddata;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+    main_litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p2_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata;
+    main_litedramcore_ext_dfi_p2_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p2_rddata <= main_litedramcore_master_p2_rddata;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+    main_litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p0_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p0_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
+            main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p0_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p0_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+            main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p3_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata;
+    main_litedramcore_ext_dfi_p3_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p3_rddata <= main_litedramcore_master_p3_rddata;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+    main_litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p1_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p1_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
+            main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p1_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p1_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+            main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p2_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p2_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
+            main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p2_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p2_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+            main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p3_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p3_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
+            main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p3_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p3_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+            main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_master_p0_address <= 16'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address;
+    main_litedramcore_master_p0_address <= 16'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_address <= main_litedramcore_ext_dfi_p0_address;
         end else begin
-            litedramcore_master_p0_address <= litedramcore_slave_p0_address;
+            main_litedramcore_master_p0_address <= main_litedramcore_slave_p0_address;
         end
     end else begin
-        litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address;
+        main_litedramcore_master_p0_address <= main_litedramcore_csr_dfi_p0_address;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_bank <= 3'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank;
+    main_litedramcore_master_p0_bank <= 3'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_bank <= main_litedramcore_ext_dfi_p0_bank;
         end else begin
-            litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
+            main_litedramcore_master_p0_bank <= main_litedramcore_slave_p0_bank;
         end
     end else begin
-        litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank;
+        main_litedramcore_master_p0_bank <= main_litedramcore_csr_dfi_p0_bank;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_cas_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n;
+    main_litedramcore_master_p0_cas_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_cas_n <= main_litedramcore_ext_dfi_p0_cas_n;
         end else begin
-            litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
+            main_litedramcore_master_p0_cas_n <= main_litedramcore_slave_p0_cas_n;
         end
     end else begin
-        litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n;
+        main_litedramcore_master_p0_cas_n <= main_litedramcore_csr_dfi_p0_cas_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_cs_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
+    main_litedramcore_master_p0_cs_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_cs_n <= main_litedramcore_ext_dfi_p0_cs_n;
         end else begin
-            litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+            main_litedramcore_master_p0_cs_n <= main_litedramcore_slave_p0_cs_n;
+            if (1'd0) begin
+                main_litedramcore_master_p0_cs_n <= {2{main_litedramcore_slave_p0_cs_n}};
+            end
         end
     end else begin
-        litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
+        main_litedramcore_master_p0_cs_n <= main_litedramcore_csr_dfi_p0_cs_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_ras_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
+    main_litedramcore_master_p0_ras_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_ras_n <= main_litedramcore_ext_dfi_p0_ras_n;
         end else begin
-            litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+            main_litedramcore_master_p0_ras_n <= main_litedramcore_slave_p0_ras_n;
         end
     end else begin
-        litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
+        main_litedramcore_master_p0_ras_n <= main_litedramcore_csr_dfi_p0_ras_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_we_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
+    main_litedramcore_master_p0_we_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_we_n <= main_litedramcore_ext_dfi_p0_we_n;
         end else begin
-            litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+            main_litedramcore_master_p0_we_n <= main_litedramcore_slave_p0_we_n;
         end
     end else begin
-        litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
+        main_litedramcore_master_p0_we_n <= main_litedramcore_csr_dfi_p0_we_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_cke <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke;
+    main_litedramcore_master_p0_cke <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_cke <= main_litedramcore_ext_dfi_p0_cke;
         end else begin
-            litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
+            main_litedramcore_master_p0_cke <= main_litedramcore_slave_p0_cke;
         end
     end else begin
-        litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke;
+        main_litedramcore_master_p0_cke <= main_litedramcore_csr_dfi_p0_cke;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_odt <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt;
+    main_litedramcore_master_p0_odt <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_odt <= main_litedramcore_ext_dfi_p0_odt;
         end else begin
-            litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
+            main_litedramcore_master_p0_odt <= main_litedramcore_slave_p0_odt;
         end
     end else begin
-        litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt;
+        main_litedramcore_master_p0_odt <= main_litedramcore_csr_dfi_p0_odt;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_reset_n <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n;
+    main_litedramcore_master_p0_reset_n <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_reset_n <= main_litedramcore_ext_dfi_p0_reset_n;
         end else begin
-            litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
+            main_litedramcore_master_p0_reset_n <= main_litedramcore_slave_p0_reset_n;
         end
     end else begin
-        litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n;
+        main_litedramcore_master_p0_reset_n <= main_litedramcore_csr_dfi_p0_reset_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_act_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n;
+    main_litedramcore_master_p0_act_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_act_n <= main_litedramcore_ext_dfi_p0_act_n;
         end else begin
-            litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
+            main_litedramcore_master_p0_act_n <= main_litedramcore_slave_p0_act_n;
         end
     end else begin
-        litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n;
+        main_litedramcore_master_p0_act_n <= main_litedramcore_csr_dfi_p0_act_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_wrdata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata;
+    main_litedramcore_master_p0_wrdata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_wrdata <= main_litedramcore_ext_dfi_p0_wrdata;
         end else begin
-            litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
+            main_litedramcore_master_p0_wrdata <= main_litedramcore_slave_p0_wrdata;
         end
     end else begin
-        litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata;
+        main_litedramcore_master_p0_wrdata <= main_litedramcore_csr_dfi_p0_wrdata;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_wrdata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en;
+    main_litedramcore_master_p0_wrdata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_wrdata_en <= main_litedramcore_ext_dfi_p0_wrdata_en;
         end else begin
-            litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
+            main_litedramcore_master_p0_wrdata_en <= main_litedramcore_slave_p0_wrdata_en;
         end
     end else begin
-        litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en;
+        main_litedramcore_master_p0_wrdata_en <= main_litedramcore_csr_dfi_p0_wrdata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_wrdata_mask <= 4'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask;
+    main_litedramcore_master_p0_wrdata_mask <= 4'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_ext_dfi_p0_wrdata_mask;
         end else begin
-            litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
+            main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_slave_p0_wrdata_mask;
         end
     end else begin
-        litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask;
+        main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_csr_dfi_p0_wrdata_mask;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_rddata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en;
+    main_litedramcore_master_p0_rddata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_rddata_en <= main_litedramcore_ext_dfi_p0_rddata_en;
         end else begin
-            litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
+            main_litedramcore_master_p0_rddata_en <= main_litedramcore_slave_p0_rddata_en;
         end
     end else begin
-        litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en;
+        main_litedramcore_master_p0_rddata_en <= main_litedramcore_csr_dfi_p0_rddata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_address <= 16'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address;
+    main_litedramcore_master_p1_address <= 16'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_address <= main_litedramcore_ext_dfi_p1_address;
         end else begin
-            litedramcore_master_p1_address <= litedramcore_slave_p1_address;
+            main_litedramcore_master_p1_address <= main_litedramcore_slave_p1_address;
         end
     end else begin
-        litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address;
+        main_litedramcore_master_p1_address <= main_litedramcore_csr_dfi_p1_address;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_bank <= 3'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank;
+    main_litedramcore_master_p1_bank <= 3'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_bank <= main_litedramcore_ext_dfi_p1_bank;
         end else begin
-            litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
+            main_litedramcore_master_p1_bank <= main_litedramcore_slave_p1_bank;
         end
     end else begin
-        litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank;
+        main_litedramcore_master_p1_bank <= main_litedramcore_csr_dfi_p1_bank;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_cas_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n;
+    main_litedramcore_master_p1_cas_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_cas_n <= main_litedramcore_ext_dfi_p1_cas_n;
         end else begin
-            litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
+            main_litedramcore_master_p1_cas_n <= main_litedramcore_slave_p1_cas_n;
         end
     end else begin
-        litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n;
+        main_litedramcore_master_p1_cas_n <= main_litedramcore_csr_dfi_p1_cas_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_cs_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n;
+    main_litedramcore_master_p1_cs_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_cs_n <= main_litedramcore_ext_dfi_p1_cs_n;
         end else begin
-            litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
+            main_litedramcore_master_p1_cs_n <= main_litedramcore_slave_p1_cs_n;
+            if (1'd0) begin
+                main_litedramcore_master_p1_cs_n <= {2{main_litedramcore_slave_p1_cs_n}};
+            end
         end
     end else begin
-        litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n;
+        main_litedramcore_master_p1_cs_n <= main_litedramcore_csr_dfi_p1_cs_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_ras_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n;
+    main_litedramcore_master_p1_ras_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_ras_n <= main_litedramcore_ext_dfi_p1_ras_n;
         end else begin
-            litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
+            main_litedramcore_master_p1_ras_n <= main_litedramcore_slave_p1_ras_n;
         end
     end else begin
-        litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n;
+        main_litedramcore_master_p1_ras_n <= main_litedramcore_csr_dfi_p1_ras_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_we_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n;
+    main_litedramcore_master_p1_we_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_we_n <= main_litedramcore_ext_dfi_p1_we_n;
         end else begin
-            litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
+            main_litedramcore_master_p1_we_n <= main_litedramcore_slave_p1_we_n;
         end
     end else begin
-        litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n;
+        main_litedramcore_master_p1_we_n <= main_litedramcore_csr_dfi_p1_we_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_cke <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke;
+    main_litedramcore_master_p1_cke <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_cke <= main_litedramcore_ext_dfi_p1_cke;
         end else begin
-            litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
+            main_litedramcore_master_p1_cke <= main_litedramcore_slave_p1_cke;
         end
     end else begin
-        litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke;
+        main_litedramcore_master_p1_cke <= main_litedramcore_csr_dfi_p1_cke;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_odt <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt;
+    main_litedramcore_master_p1_odt <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_odt <= main_litedramcore_ext_dfi_p1_odt;
         end else begin
-            litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
+            main_litedramcore_master_p1_odt <= main_litedramcore_slave_p1_odt;
         end
     end else begin
-        litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt;
+        main_litedramcore_master_p1_odt <= main_litedramcore_csr_dfi_p1_odt;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_reset_n <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n;
+    main_litedramcore_master_p1_reset_n <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_reset_n <= main_litedramcore_ext_dfi_p1_reset_n;
         end else begin
-            litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+            main_litedramcore_master_p1_reset_n <= main_litedramcore_slave_p1_reset_n;
         end
     end else begin
-        litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n;
+        main_litedramcore_master_p1_reset_n <= main_litedramcore_csr_dfi_p1_reset_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_act_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n;
+    main_litedramcore_master_p1_act_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_act_n <= main_litedramcore_ext_dfi_p1_act_n;
         end else begin
-            litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
+            main_litedramcore_master_p1_act_n <= main_litedramcore_slave_p1_act_n;
         end
     end else begin
-        litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n;
+        main_litedramcore_master_p1_act_n <= main_litedramcore_csr_dfi_p1_act_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_wrdata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata;
+    main_litedramcore_master_p1_wrdata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_wrdata <= main_litedramcore_ext_dfi_p1_wrdata;
         end else begin
-            litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
+            main_litedramcore_master_p1_wrdata <= main_litedramcore_slave_p1_wrdata;
         end
     end else begin
-        litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata;
+        main_litedramcore_master_p1_wrdata <= main_litedramcore_csr_dfi_p1_wrdata;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_wrdata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en;
+    main_litedramcore_master_p1_wrdata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_wrdata_en <= main_litedramcore_ext_dfi_p1_wrdata_en;
         end else begin
-            litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
+            main_litedramcore_master_p1_wrdata_en <= main_litedramcore_slave_p1_wrdata_en;
         end
     end else begin
-        litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en;
+        main_litedramcore_master_p1_wrdata_en <= main_litedramcore_csr_dfi_p1_wrdata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_wrdata_mask <= 4'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask;
+    main_litedramcore_master_p1_wrdata_mask <= 4'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_ext_dfi_p1_wrdata_mask;
         end else begin
-            litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
+            main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_slave_p1_wrdata_mask;
         end
     end else begin
-        litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask;
+        main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_csr_dfi_p1_wrdata_mask;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_rddata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en;
+    main_litedramcore_master_p1_rddata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_rddata_en <= main_litedramcore_ext_dfi_p1_rddata_en;
         end else begin
-            litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
+            main_litedramcore_master_p1_rddata_en <= main_litedramcore_slave_p1_rddata_en;
         end
     end else begin
-        litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en;
+        main_litedramcore_master_p1_rddata_en <= main_litedramcore_csr_dfi_p1_rddata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_address <= 16'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address;
+    main_litedramcore_master_p2_address <= 16'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_address <= main_litedramcore_ext_dfi_p2_address;
         end else begin
-            litedramcore_master_p2_address <= litedramcore_slave_p2_address;
+            main_litedramcore_master_p2_address <= main_litedramcore_slave_p2_address;
         end
     end else begin
-        litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address;
+        main_litedramcore_master_p2_address <= main_litedramcore_csr_dfi_p2_address;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_bank <= 3'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank;
+    main_litedramcore_master_p2_bank <= 3'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_bank <= main_litedramcore_ext_dfi_p2_bank;
         end else begin
-            litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
+            main_litedramcore_master_p2_bank <= main_litedramcore_slave_p2_bank;
         end
     end else begin
-        litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank;
+        main_litedramcore_master_p2_bank <= main_litedramcore_csr_dfi_p2_bank;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_cas_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n;
+    main_litedramcore_master_p2_cas_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_cas_n <= main_litedramcore_ext_dfi_p2_cas_n;
         end else begin
-            litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
+            main_litedramcore_master_p2_cas_n <= main_litedramcore_slave_p2_cas_n;
         end
     end else begin
-        litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n;
+        main_litedramcore_master_p2_cas_n <= main_litedramcore_csr_dfi_p2_cas_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_cs_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n;
+    main_litedramcore_master_p2_cs_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_cs_n <= main_litedramcore_ext_dfi_p2_cs_n;
         end else begin
-            litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
+            main_litedramcore_master_p2_cs_n <= main_litedramcore_slave_p2_cs_n;
+            if (1'd0) begin
+                main_litedramcore_master_p2_cs_n <= {2{main_litedramcore_slave_p2_cs_n}};
+            end
         end
     end else begin
-        litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n;
+        main_litedramcore_master_p2_cs_n <= main_litedramcore_csr_dfi_p2_cs_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_ras_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n;
+    main_litedramcore_master_p2_ras_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_ras_n <= main_litedramcore_ext_dfi_p2_ras_n;
         end else begin
-            litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
+            main_litedramcore_master_p2_ras_n <= main_litedramcore_slave_p2_ras_n;
         end
     end else begin
-        litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n;
+        main_litedramcore_master_p2_ras_n <= main_litedramcore_csr_dfi_p2_ras_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_we_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n;
+    main_litedramcore_master_p2_we_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_we_n <= main_litedramcore_ext_dfi_p2_we_n;
         end else begin
-            litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
+            main_litedramcore_master_p2_we_n <= main_litedramcore_slave_p2_we_n;
         end
     end else begin
-        litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n;
+        main_litedramcore_master_p2_we_n <= main_litedramcore_csr_dfi_p2_we_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_cke <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke;
+    main_litedramcore_master_p2_cke <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_cke <= main_litedramcore_ext_dfi_p2_cke;
         end else begin
-            litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
+            main_litedramcore_master_p2_cke <= main_litedramcore_slave_p2_cke;
         end
     end else begin
-        litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke;
+        main_litedramcore_master_p2_cke <= main_litedramcore_csr_dfi_p2_cke;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_odt <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt;
+    main_litedramcore_master_p2_odt <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_odt <= main_litedramcore_ext_dfi_p2_odt;
         end else begin
-            litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
+            main_litedramcore_master_p2_odt <= main_litedramcore_slave_p2_odt;
         end
     end else begin
-        litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt;
+        main_litedramcore_master_p2_odt <= main_litedramcore_csr_dfi_p2_odt;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_reset_n <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n;
+    main_litedramcore_master_p2_reset_n <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_reset_n <= main_litedramcore_ext_dfi_p2_reset_n;
         end else begin
-            litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
+            main_litedramcore_master_p2_reset_n <= main_litedramcore_slave_p2_reset_n;
         end
     end else begin
-        litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n;
+        main_litedramcore_master_p2_reset_n <= main_litedramcore_csr_dfi_p2_reset_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_act_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n;
+    main_litedramcore_master_p2_act_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_act_n <= main_litedramcore_ext_dfi_p2_act_n;
         end else begin
-            litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
+            main_litedramcore_master_p2_act_n <= main_litedramcore_slave_p2_act_n;
         end
     end else begin
-        litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n;
+        main_litedramcore_master_p2_act_n <= main_litedramcore_csr_dfi_p2_act_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_wrdata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata;
+    main_litedramcore_master_p2_wrdata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_wrdata <= main_litedramcore_ext_dfi_p2_wrdata;
         end else begin
-            litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
+            main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata;
         end
     end else begin
-        litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata;
+        main_litedramcore_master_p2_wrdata <= main_litedramcore_csr_dfi_p2_wrdata;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_wrdata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en;
+    main_litedramcore_master_p2_wrdata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_wrdata_en <= main_litedramcore_ext_dfi_p2_wrdata_en;
         end else begin
-            litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
+            main_litedramcore_master_p2_wrdata_en <= main_litedramcore_slave_p2_wrdata_en;
         end
     end else begin
-        litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en;
+        main_litedramcore_master_p2_wrdata_en <= main_litedramcore_csr_dfi_p2_wrdata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_wrdata_mask <= 4'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask;
+    main_litedramcore_master_p2_wrdata_mask <= 4'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_ext_dfi_p2_wrdata_mask;
         end else begin
-            litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
+            main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_slave_p2_wrdata_mask;
         end
     end else begin
-        litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask;
+        main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_csr_dfi_p2_wrdata_mask;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_rddata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en;
+    main_litedramcore_master_p2_rddata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_rddata_en <= main_litedramcore_ext_dfi_p2_rddata_en;
         end else begin
-            litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
+            main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en;
         end
     end else begin
-        litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en;
+        main_litedramcore_master_p2_rddata_en <= main_litedramcore_csr_dfi_p2_rddata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_address <= 16'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address;
+    main_litedramcore_master_p3_address <= 16'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_address <= main_litedramcore_ext_dfi_p3_address;
         end else begin
-            litedramcore_master_p3_address <= litedramcore_slave_p3_address;
+            main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address;
         end
     end else begin
-        litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address;
+        main_litedramcore_master_p3_address <= main_litedramcore_csr_dfi_p3_address;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_bank <= 3'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank;
+    main_litedramcore_master_p3_bank <= 3'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_bank <= main_litedramcore_ext_dfi_p3_bank;
         end else begin
-            litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
+            main_litedramcore_master_p3_bank <= main_litedramcore_slave_p3_bank;
         end
     end else begin
-        litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank;
+        main_litedramcore_master_p3_bank <= main_litedramcore_csr_dfi_p3_bank;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_cas_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n;
+    main_litedramcore_master_p3_cas_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_cas_n <= main_litedramcore_ext_dfi_p3_cas_n;
         end else begin
-            litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
+            main_litedramcore_master_p3_cas_n <= main_litedramcore_slave_p3_cas_n;
         end
     end else begin
-        litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n;
+        main_litedramcore_master_p3_cas_n <= main_litedramcore_csr_dfi_p3_cas_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_cs_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n;
+    main_litedramcore_master_p3_cs_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_cs_n <= main_litedramcore_ext_dfi_p3_cs_n;
         end else begin
-            litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
+            main_litedramcore_master_p3_cs_n <= main_litedramcore_slave_p3_cs_n;
+            if (1'd0) begin
+                main_litedramcore_master_p3_cs_n <= {2{main_litedramcore_slave_p3_cs_n}};
+            end
         end
     end else begin
-        litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n;
-    end
-end
-assign litedramcore_csr_dfi_p0_cke = litedramcore_cke;
-assign litedramcore_csr_dfi_p1_cke = litedramcore_cke;
-assign litedramcore_csr_dfi_p2_cke = litedramcore_cke;
-assign litedramcore_csr_dfi_p3_cke = litedramcore_cke;
-assign litedramcore_csr_dfi_p0_odt = litedramcore_odt;
-assign litedramcore_csr_dfi_p1_odt = litedramcore_odt;
-assign litedramcore_csr_dfi_p2_odt = litedramcore_odt;
-assign litedramcore_csr_dfi_p3_odt = litedramcore_odt;
-assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n;
-assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n;
-assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n;
-assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n;
-always @(*) begin
-    litedramcore_csr_dfi_p0_cas_n <= 1'd1;
-    if (litedramcore_phaseinjector0_command_issue_re) begin
-        litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas);
+        main_litedramcore_master_p3_cs_n <= main_litedramcore_csr_dfi_p3_cs_n;
+    end
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p0_cke <= 1'd0;
+    main_litedramcore_csr_dfi_p0_cke <= main_litedramcore_cke;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p1_cke <= 1'd0;
+    main_litedramcore_csr_dfi_p1_cke <= main_litedramcore_cke;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p2_cke <= 1'd0;
+    main_litedramcore_csr_dfi_p2_cke <= main_litedramcore_cke;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p3_cke <= 1'd0;
+    main_litedramcore_csr_dfi_p3_cke <= main_litedramcore_cke;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p0_odt <= 1'd0;
+    main_litedramcore_csr_dfi_p0_odt <= main_litedramcore_odt;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p1_odt <= 1'd0;
+    main_litedramcore_csr_dfi_p1_odt <= main_litedramcore_odt;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p2_odt <= 1'd0;
+    main_litedramcore_csr_dfi_p2_odt <= main_litedramcore_odt;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p3_odt <= 1'd0;
+    main_litedramcore_csr_dfi_p3_odt <= main_litedramcore_odt;
+end
+assign main_litedramcore_csr_dfi_p0_reset_n = main_litedramcore_reset_n;
+assign main_litedramcore_csr_dfi_p1_reset_n = main_litedramcore_reset_n;
+assign main_litedramcore_csr_dfi_p2_reset_n = main_litedramcore_reset_n;
+assign main_litedramcore_csr_dfi_p3_reset_n = main_litedramcore_reset_n;
+always @(*) begin
+    main_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        main_litedramcore_csr_dfi_p0_cas_n <= (~main_litedramcore_phaseinjector0_csrfield_cas);
     end else begin
-        litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+        main_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p0_cs_n <= 1'd1;
-    if (litedramcore_phaseinjector0_command_issue_re) begin
-        litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}};
+    main_litedramcore_csr_dfi_p0_cs_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        if (main_litedramcore_phaseinjector0_csrfield_cs_top) begin
+            main_litedramcore_csr_dfi_p0_cs_n <= 2'd2;
+        end else begin
+            if (main_litedramcore_phaseinjector0_csrfield_cs_bottom) begin
+                main_litedramcore_csr_dfi_p0_cs_n <= 1'd1;
+            end else begin
+                main_litedramcore_csr_dfi_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_csrfield_cs)}};
+            end
+        end
     end else begin
-        litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
+        main_litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p0_ras_n <= 1'd1;
-    if (litedramcore_phaseinjector0_command_issue_re) begin
-        litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras);
+    main_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        main_litedramcore_csr_dfi_p0_ras_n <= (~main_litedramcore_phaseinjector0_csrfield_ras);
     end else begin
-        litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+        main_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p0_we_n <= 1'd1;
-    if (litedramcore_phaseinjector0_command_issue_re) begin
-        litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
+    main_litedramcore_csr_dfi_p0_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        main_litedramcore_csr_dfi_p0_we_n <= (~main_litedramcore_phaseinjector0_csrfield_we);
     end else begin
-        litedramcore_csr_dfi_p0_we_n <= 1'd1;
+        main_litedramcore_csr_dfi_p0_we_n <= 1'd1;
     end
 end
-assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage;
-assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage;
-assign litedramcore_csr_dfi_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_wren);
-assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_rden);
-assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
-assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
+assign main_litedramcore_csr_dfi_p0_address = main_litedramcore_phaseinjector0_address_storage;
+assign main_litedramcore_csr_dfi_p0_bank = main_litedramcore_phaseinjector0_baddress_storage;
+assign main_litedramcore_csr_dfi_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_wren);
+assign main_litedramcore_csr_dfi_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_rden);
+assign main_litedramcore_csr_dfi_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage;
+assign main_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
 always @(*) begin
-    litedramcore_csr_dfi_p1_cas_n <= 1'd1;
-    if (litedramcore_phaseinjector1_command_issue_re) begin
-        litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas);
+    main_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        main_litedramcore_csr_dfi_p1_cas_n <= (~main_litedramcore_phaseinjector1_csrfield_cas);
     end else begin
-        litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+        main_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p1_cs_n <= 1'd1;
-    if (litedramcore_phaseinjector1_command_issue_re) begin
-        litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}};
+    main_litedramcore_csr_dfi_p1_cs_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        if (main_litedramcore_phaseinjector1_csrfield_cs_top) begin
+            main_litedramcore_csr_dfi_p1_cs_n <= 2'd2;
+        end else begin
+            if (main_litedramcore_phaseinjector1_csrfield_cs_bottom) begin
+                main_litedramcore_csr_dfi_p1_cs_n <= 1'd1;
+            end else begin
+                main_litedramcore_csr_dfi_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_csrfield_cs)}};
+            end
+        end
     end else begin
-        litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
+        main_litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p1_ras_n <= 1'd1;
-    if (litedramcore_phaseinjector1_command_issue_re) begin
-        litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras);
+    main_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        main_litedramcore_csr_dfi_p1_ras_n <= (~main_litedramcore_phaseinjector1_csrfield_ras);
     end else begin
-        litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+        main_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p1_we_n <= 1'd1;
-    if (litedramcore_phaseinjector1_command_issue_re) begin
-        litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
+    main_litedramcore_csr_dfi_p1_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        main_litedramcore_csr_dfi_p1_we_n <= (~main_litedramcore_phaseinjector1_csrfield_we);
     end else begin
-        litedramcore_csr_dfi_p1_we_n <= 1'd1;
+        main_litedramcore_csr_dfi_p1_we_n <= 1'd1;
     end
 end
-assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage;
-assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage;
-assign litedramcore_csr_dfi_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_wren);
-assign litedramcore_csr_dfi_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_rden);
-assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
-assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
+assign main_litedramcore_csr_dfi_p1_address = main_litedramcore_phaseinjector1_address_storage;
+assign main_litedramcore_csr_dfi_p1_bank = main_litedramcore_phaseinjector1_baddress_storage;
+assign main_litedramcore_csr_dfi_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_wren);
+assign main_litedramcore_csr_dfi_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_rden);
+assign main_litedramcore_csr_dfi_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage;
+assign main_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
 always @(*) begin
-    litedramcore_csr_dfi_p2_cas_n <= 1'd1;
-    if (litedramcore_phaseinjector2_command_issue_re) begin
-        litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas);
+    main_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        main_litedramcore_csr_dfi_p2_cas_n <= (~main_litedramcore_phaseinjector2_csrfield_cas);
     end else begin
-        litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+        main_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p2_cs_n <= 1'd1;
-    if (litedramcore_phaseinjector2_command_issue_re) begin
-        litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}};
+    main_litedramcore_csr_dfi_p2_cs_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        if (main_litedramcore_phaseinjector2_csrfield_cs_top) begin
+            main_litedramcore_csr_dfi_p2_cs_n <= 2'd2;
+        end else begin
+            if (main_litedramcore_phaseinjector2_csrfield_cs_bottom) begin
+                main_litedramcore_csr_dfi_p2_cs_n <= 1'd1;
+            end else begin
+                main_litedramcore_csr_dfi_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_csrfield_cs)}};
+            end
+        end
     end else begin
-        litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
+        main_litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p2_ras_n <= 1'd1;
-    if (litedramcore_phaseinjector2_command_issue_re) begin
-        litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras);
+    main_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        main_litedramcore_csr_dfi_p2_ras_n <= (~main_litedramcore_phaseinjector2_csrfield_ras);
     end else begin
-        litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+        main_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p2_we_n <= 1'd1;
-    if (litedramcore_phaseinjector2_command_issue_re) begin
-        litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we);
+    main_litedramcore_csr_dfi_p2_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        main_litedramcore_csr_dfi_p2_we_n <= (~main_litedramcore_phaseinjector2_csrfield_we);
     end else begin
-        litedramcore_csr_dfi_p2_we_n <= 1'd1;
+        main_litedramcore_csr_dfi_p2_we_n <= 1'd1;
     end
 end
-assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage;
-assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage;
-assign litedramcore_csr_dfi_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_wren);
-assign litedramcore_csr_dfi_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_rden);
-assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
-assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
+assign main_litedramcore_csr_dfi_p2_address = main_litedramcore_phaseinjector2_address_storage;
+assign main_litedramcore_csr_dfi_p2_bank = main_litedramcore_phaseinjector2_baddress_storage;
+assign main_litedramcore_csr_dfi_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_wren);
+assign main_litedramcore_csr_dfi_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_rden);
+assign main_litedramcore_csr_dfi_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage;
+assign main_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
 always @(*) begin
-    litedramcore_csr_dfi_p3_cas_n <= 1'd1;
-    if (litedramcore_phaseinjector3_command_issue_re) begin
-        litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas);
+    main_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        main_litedramcore_csr_dfi_p3_cas_n <= (~main_litedramcore_phaseinjector3_csrfield_cas);
     end else begin
-        litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+        main_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p3_cs_n <= 1'd1;
-    if (litedramcore_phaseinjector3_command_issue_re) begin
-        litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}};
+    main_litedramcore_csr_dfi_p3_cs_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        if (main_litedramcore_phaseinjector3_csrfield_cs_top) begin
+            main_litedramcore_csr_dfi_p3_cs_n <= 2'd2;
+        end else begin
+            if (main_litedramcore_phaseinjector3_csrfield_cs_bottom) begin
+                main_litedramcore_csr_dfi_p3_cs_n <= 1'd1;
+            end else begin
+                main_litedramcore_csr_dfi_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_csrfield_cs)}};
+            end
+        end
     end else begin
-        litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
+        main_litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p3_ras_n <= 1'd1;
-    if (litedramcore_phaseinjector3_command_issue_re) begin
-        litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras);
+    main_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        main_litedramcore_csr_dfi_p3_ras_n <= (~main_litedramcore_phaseinjector3_csrfield_ras);
     end else begin
-        litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+        main_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p3_we_n <= 1'd1;
-    if (litedramcore_phaseinjector3_command_issue_re) begin
-        litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we);
+    main_litedramcore_csr_dfi_p3_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        main_litedramcore_csr_dfi_p3_we_n <= (~main_litedramcore_phaseinjector3_csrfield_we);
     end else begin
-        litedramcore_csr_dfi_p3_we_n <= 1'd1;
-    end
-end
-assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage;
-assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage;
-assign litedramcore_csr_dfi_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_wren);
-assign litedramcore_csr_dfi_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_rden);
-assign litedramcore_csr_dfi_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage;
-assign litedramcore_csr_dfi_p3_wrdata_mask = 1'd0;
-assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid;
-assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready;
-assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we;
-assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr;
-assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock;
-assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready;
-assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid;
-assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid;
-assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready;
-assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we;
-assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr;
-assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock;
-assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready;
-assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid;
-assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid;
-assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready;
-assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we;
-assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr;
-assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock;
-assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready;
-assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid;
-assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid;
-assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready;
-assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we;
-assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr;
-assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock;
-assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready;
-assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid;
-assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid;
-assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready;
-assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we;
-assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr;
-assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock;
-assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready;
-assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid;
-assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid;
-assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready;
-assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we;
-assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr;
-assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock;
-assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready;
-assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid;
-assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid;
-assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready;
-assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we;
-assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr;
-assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock;
-assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready;
-assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid;
-assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid;
-assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready;
-assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we;
-assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr;
-assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock;
-assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready;
-assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid;
-assign litedramcore_timer_wait = (~litedramcore_timer_done0);
-assign litedramcore_postponer_req_i = litedramcore_timer_done0;
-assign litedramcore_wants_refresh = litedramcore_postponer_req_o;
-assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0;
-assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done);
-assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0);
-assign litedramcore_timer_done0 = litedramcore_timer_done1;
-assign litedramcore_timer_count0 = litedramcore_timer_count1;
-assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0));
-assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0));
-assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0);
-assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
-assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
-always @(*) begin
-    litedramcore_refresher_next_state <= 2'd0;
-    litedramcore_refresher_next_state <= litedramcore_refresher_state;
-    case (litedramcore_refresher_state)
+        main_litedramcore_csr_dfi_p3_we_n <= 1'd1;
+    end
+end
+assign main_litedramcore_csr_dfi_p3_address = main_litedramcore_phaseinjector3_address_storage;
+assign main_litedramcore_csr_dfi_p3_bank = main_litedramcore_phaseinjector3_baddress_storage;
+assign main_litedramcore_csr_dfi_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_wren);
+assign main_litedramcore_csr_dfi_p3_rddata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_rden);
+assign main_litedramcore_csr_dfi_p3_wrdata = main_litedramcore_phaseinjector3_wrdata_storage;
+assign main_litedramcore_csr_dfi_p3_wrdata_mask = 1'd0;
+assign main_litedramcore_bankmachine0_req_valid = main_litedramcore_interface_bank0_valid;
+assign main_litedramcore_interface_bank0_ready = main_litedramcore_bankmachine0_req_ready;
+assign main_litedramcore_bankmachine0_req_we = main_litedramcore_interface_bank0_we;
+assign main_litedramcore_bankmachine0_req_addr = main_litedramcore_interface_bank0_addr;
+assign main_litedramcore_interface_bank0_lock = main_litedramcore_bankmachine0_req_lock;
+assign main_litedramcore_interface_bank0_wdata_ready = main_litedramcore_bankmachine0_req_wdata_ready;
+assign main_litedramcore_interface_bank0_rdata_valid = main_litedramcore_bankmachine0_req_rdata_valid;
+assign main_litedramcore_bankmachine1_req_valid = main_litedramcore_interface_bank1_valid;
+assign main_litedramcore_interface_bank1_ready = main_litedramcore_bankmachine1_req_ready;
+assign main_litedramcore_bankmachine1_req_we = main_litedramcore_interface_bank1_we;
+assign main_litedramcore_bankmachine1_req_addr = main_litedramcore_interface_bank1_addr;
+assign main_litedramcore_interface_bank1_lock = main_litedramcore_bankmachine1_req_lock;
+assign main_litedramcore_interface_bank1_wdata_ready = main_litedramcore_bankmachine1_req_wdata_ready;
+assign main_litedramcore_interface_bank1_rdata_valid = main_litedramcore_bankmachine1_req_rdata_valid;
+assign main_litedramcore_bankmachine2_req_valid = main_litedramcore_interface_bank2_valid;
+assign main_litedramcore_interface_bank2_ready = main_litedramcore_bankmachine2_req_ready;
+assign main_litedramcore_bankmachine2_req_we = main_litedramcore_interface_bank2_we;
+assign main_litedramcore_bankmachine2_req_addr = main_litedramcore_interface_bank2_addr;
+assign main_litedramcore_interface_bank2_lock = main_litedramcore_bankmachine2_req_lock;
+assign main_litedramcore_interface_bank2_wdata_ready = main_litedramcore_bankmachine2_req_wdata_ready;
+assign main_litedramcore_interface_bank2_rdata_valid = main_litedramcore_bankmachine2_req_rdata_valid;
+assign main_litedramcore_bankmachine3_req_valid = main_litedramcore_interface_bank3_valid;
+assign main_litedramcore_interface_bank3_ready = main_litedramcore_bankmachine3_req_ready;
+assign main_litedramcore_bankmachine3_req_we = main_litedramcore_interface_bank3_we;
+assign main_litedramcore_bankmachine3_req_addr = main_litedramcore_interface_bank3_addr;
+assign main_litedramcore_interface_bank3_lock = main_litedramcore_bankmachine3_req_lock;
+assign main_litedramcore_interface_bank3_wdata_ready = main_litedramcore_bankmachine3_req_wdata_ready;
+assign main_litedramcore_interface_bank3_rdata_valid = main_litedramcore_bankmachine3_req_rdata_valid;
+assign main_litedramcore_bankmachine4_req_valid = main_litedramcore_interface_bank4_valid;
+assign main_litedramcore_interface_bank4_ready = main_litedramcore_bankmachine4_req_ready;
+assign main_litedramcore_bankmachine4_req_we = main_litedramcore_interface_bank4_we;
+assign main_litedramcore_bankmachine4_req_addr = main_litedramcore_interface_bank4_addr;
+assign main_litedramcore_interface_bank4_lock = main_litedramcore_bankmachine4_req_lock;
+assign main_litedramcore_interface_bank4_wdata_ready = main_litedramcore_bankmachine4_req_wdata_ready;
+assign main_litedramcore_interface_bank4_rdata_valid = main_litedramcore_bankmachine4_req_rdata_valid;
+assign main_litedramcore_bankmachine5_req_valid = main_litedramcore_interface_bank5_valid;
+assign main_litedramcore_interface_bank5_ready = main_litedramcore_bankmachine5_req_ready;
+assign main_litedramcore_bankmachine5_req_we = main_litedramcore_interface_bank5_we;
+assign main_litedramcore_bankmachine5_req_addr = main_litedramcore_interface_bank5_addr;
+assign main_litedramcore_interface_bank5_lock = main_litedramcore_bankmachine5_req_lock;
+assign main_litedramcore_interface_bank5_wdata_ready = main_litedramcore_bankmachine5_req_wdata_ready;
+assign main_litedramcore_interface_bank5_rdata_valid = main_litedramcore_bankmachine5_req_rdata_valid;
+assign main_litedramcore_bankmachine6_req_valid = main_litedramcore_interface_bank6_valid;
+assign main_litedramcore_interface_bank6_ready = main_litedramcore_bankmachine6_req_ready;
+assign main_litedramcore_bankmachine6_req_we = main_litedramcore_interface_bank6_we;
+assign main_litedramcore_bankmachine6_req_addr = main_litedramcore_interface_bank6_addr;
+assign main_litedramcore_interface_bank6_lock = main_litedramcore_bankmachine6_req_lock;
+assign main_litedramcore_interface_bank6_wdata_ready = main_litedramcore_bankmachine6_req_wdata_ready;
+assign main_litedramcore_interface_bank6_rdata_valid = main_litedramcore_bankmachine6_req_rdata_valid;
+assign main_litedramcore_bankmachine7_req_valid = main_litedramcore_interface_bank7_valid;
+assign main_litedramcore_interface_bank7_ready = main_litedramcore_bankmachine7_req_ready;
+assign main_litedramcore_bankmachine7_req_we = main_litedramcore_interface_bank7_we;
+assign main_litedramcore_bankmachine7_req_addr = main_litedramcore_interface_bank7_addr;
+assign main_litedramcore_interface_bank7_lock = main_litedramcore_bankmachine7_req_lock;
+assign main_litedramcore_interface_bank7_wdata_ready = main_litedramcore_bankmachine7_req_wdata_ready;
+assign main_litedramcore_interface_bank7_rdata_valid = main_litedramcore_bankmachine7_req_rdata_valid;
+assign main_litedramcore_timer_wait = (~main_litedramcore_timer_done0);
+assign main_litedramcore_postponer_req_i = main_litedramcore_timer_done0;
+assign main_litedramcore_wants_refresh = main_litedramcore_postponer_req_o;
+assign main_litedramcore_wants_zqcs = main_litedramcore_zqcs_timer_done0;
+assign main_litedramcore_zqcs_timer_wait = (~main_litedramcore_zqcs_executer_done);
+assign main_litedramcore_timer_done1 = (main_litedramcore_timer_count1 == 1'd0);
+assign main_litedramcore_timer_done0 = main_litedramcore_timer_done1;
+assign main_litedramcore_timer_count0 = main_litedramcore_timer_count1;
+assign main_litedramcore_sequencer_start1 = (main_litedramcore_sequencer_start0 | (main_litedramcore_sequencer_count != 1'd0));
+assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 & (main_litedramcore_sequencer_count == 1'd0));
+assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0);
+assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1;
+assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1;
+always @(*) begin
+    builder_refresher_next_state <= 2'd0;
+    builder_refresher_next_state <= builder_refresher_state;
+    case (builder_refresher_state)
         1'd1: begin
-            if (litedramcore_cmd_ready) begin
-                litedramcore_refresher_next_state <= 2'd2;
+            if (main_litedramcore_cmd_ready) begin
+                builder_refresher_next_state <= 2'd2;
             end
         end
         2'd2: begin
-            if (litedramcore_sequencer_done0) begin
-                if (litedramcore_wants_zqcs) begin
-                    litedramcore_refresher_next_state <= 2'd3;
+            if (main_litedramcore_sequencer_done0) begin
+                if (main_litedramcore_wants_zqcs) begin
+                    builder_refresher_next_state <= 2'd3;
                 end else begin
-                    litedramcore_refresher_next_state <= 1'd0;
+                    builder_refresher_next_state <= 1'd0;
                 end
             end
         end
         2'd3: begin
-            if (litedramcore_zqcs_executer_done) begin
-                litedramcore_refresher_next_state <= 1'd0;
+            if (main_litedramcore_zqcs_executer_done) begin
+                builder_refresher_next_state <= 1'd0;
             end
         end
         default: begin
             if (1'd1) begin
-                if (litedramcore_wants_refresh) begin
-                    litedramcore_refresher_next_state <= 1'd1;
+                if (main_litedramcore_wants_refresh) begin
+                    builder_refresher_next_state <= 1'd1;
                 end
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_cmd_valid <= 1'd0;
-    case (litedramcore_refresher_state)
+    main_litedramcore_sequencer_start0 <= 1'd0;
+    case (builder_refresher_state)
         1'd1: begin
-            litedramcore_cmd_valid <= 1'd1;
+            if (main_litedramcore_cmd_ready) begin
+                main_litedramcore_sequencer_start0 <= 1'd1;
+            end
         end
         2'd2: begin
-            litedramcore_cmd_valid <= 1'd1;
-            if (litedramcore_sequencer_done0) begin
-                if (litedramcore_wants_zqcs) begin
-                end else begin
-                    litedramcore_cmd_valid <= 1'd0;
-                end
-            end
         end
         2'd3: begin
-            litedramcore_cmd_valid <= 1'd1;
-            if (litedramcore_zqcs_executer_done) begin
-                litedramcore_cmd_valid <= 1'd0;
-            end
         end
         default: begin
         end
     endcase
 end
 always @(*) begin
-    litedramcore_zqcs_executer_start <= 1'd0;
-    case (litedramcore_refresher_state)
+    main_litedramcore_cmd_valid <= 1'd0;
+    case (builder_refresher_state)
         1'd1: begin
+            main_litedramcore_cmd_valid <= 1'd1;
         end
         2'd2: begin
-            if (litedramcore_sequencer_done0) begin
-                if (litedramcore_wants_zqcs) begin
-                    litedramcore_zqcs_executer_start <= 1'd1;
+            main_litedramcore_cmd_valid <= 1'd1;
+            if (main_litedramcore_sequencer_done0) begin
+                if (main_litedramcore_wants_zqcs) begin
                 end else begin
+                    main_litedramcore_cmd_valid <= 1'd0;
                 end
             end
         end
         2'd3: begin
+            main_litedramcore_cmd_valid <= 1'd1;
+            if (main_litedramcore_zqcs_executer_done) begin
+                main_litedramcore_cmd_valid <= 1'd0;
+            end
         end
         default: begin
         end
     endcase
 end
 always @(*) begin
-    litedramcore_cmd_last <= 1'd0;
-    case (litedramcore_refresher_state)
+    main_litedramcore_zqcs_executer_start <= 1'd0;
+    case (builder_refresher_state)
         1'd1: begin
         end
         2'd2: begin
-            if (litedramcore_sequencer_done0) begin
-                if (litedramcore_wants_zqcs) begin
+            if (main_litedramcore_sequencer_done0) begin
+                if (main_litedramcore_wants_zqcs) begin
+                    main_litedramcore_zqcs_executer_start <= 1'd1;
                 end else begin
-                    litedramcore_cmd_last <= 1'd1;
                 end
             end
         end
         2'd3: begin
-            if (litedramcore_zqcs_executer_done) begin
-                litedramcore_cmd_last <= 1'd1;
-            end
         end
         default: begin
         end
     endcase
 end
 always @(*) begin
-    litedramcore_sequencer_start0 <= 1'd0;
-    case (litedramcore_refresher_state)
+    main_litedramcore_cmd_last <= 1'd0;
+    case (builder_refresher_state)
         1'd1: begin
-            if (litedramcore_cmd_ready) begin
-                litedramcore_sequencer_start0 <= 1'd1;
-            end
         end
         2'd2: begin
+            if (main_litedramcore_sequencer_done0) begin
+                if (main_litedramcore_wants_zqcs) begin
+                end else begin
+                    main_litedramcore_cmd_last <= 1'd1;
+                end
+            end
         end
         2'd3: begin
+            if (main_litedramcore_zqcs_executer_done) begin
+                main_litedramcore_cmd_last <= 1'd1;
+            end
         end
         default: begin
         end
     endcase
 end
-assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid;
-assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready;
-assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we;
-assign litedramcore_bankmachine0_sink_payload_addr = litedramcore_bankmachine0_req_addr;
-assign litedramcore_bankmachine0_sink_sink_valid = litedramcore_bankmachine0_source_valid;
-assign litedramcore_bankmachine0_source_ready = litedramcore_bankmachine0_sink_sink_ready;
-assign litedramcore_bankmachine0_sink_sink_first = litedramcore_bankmachine0_source_first;
-assign litedramcore_bankmachine0_sink_sink_last = litedramcore_bankmachine0_source_last;
-assign litedramcore_bankmachine0_sink_sink_payload_we = litedramcore_bankmachine0_source_payload_we;
-assign litedramcore_bankmachine0_sink_sink_payload_addr = litedramcore_bankmachine0_source_payload_addr;
-assign litedramcore_bankmachine0_source_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
-assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_source_valid | litedramcore_bankmachine0_source_source_valid);
-assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_source_source_payload_addr[22:7]);
-assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
-always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_a <= 16'd0;
-    if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
-        litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_source_source_payload_addr[22:7];
+assign main_litedramcore_bankmachine0_sink_valid = main_litedramcore_bankmachine0_req_valid;
+assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_sink_ready;
+assign main_litedramcore_bankmachine0_sink_payload_we = main_litedramcore_bankmachine0_req_we;
+assign main_litedramcore_bankmachine0_sink_payload_addr = main_litedramcore_bankmachine0_req_addr;
+assign main_litedramcore_bankmachine0_sink_sink_valid = main_litedramcore_bankmachine0_source_valid;
+assign main_litedramcore_bankmachine0_source_ready = main_litedramcore_bankmachine0_sink_sink_ready;
+assign main_litedramcore_bankmachine0_sink_sink_first = main_litedramcore_bankmachine0_source_first;
+assign main_litedramcore_bankmachine0_sink_sink_last = main_litedramcore_bankmachine0_source_last;
+assign main_litedramcore_bankmachine0_sink_sink_payload_we = main_litedramcore_bankmachine0_source_payload_we;
+assign main_litedramcore_bankmachine0_sink_sink_payload_addr = main_litedramcore_bankmachine0_source_payload_addr;
+assign main_litedramcore_bankmachine0_source_source_ready = (main_litedramcore_bankmachine0_req_wdata_ready | main_litedramcore_bankmachine0_req_rdata_valid);
+assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_source_valid | main_litedramcore_bankmachine0_source_source_valid);
+assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_source_source_payload_addr[22:7]);
+assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
+always @(*) begin
+    main_litedramcore_bankmachine0_cmd_payload_a <= 16'd0;
+    if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine0_cmd_payload_a <= main_litedramcore_bankmachine0_source_source_payload_addr[22:7];
     end else begin
-        litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
-assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
-assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
-always @(*) begin
-    litedramcore_bankmachine0_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine0_source_valid & litedramcore_bankmachine0_source_source_valid)) begin
-        if ((litedramcore_bankmachine0_source_payload_addr[22:7] != litedramcore_bankmachine0_source_source_payload_addr[22:7])) begin
-            litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine0_syncfifo0_din = {litedramcore_bankmachine0_fifo_in_last, litedramcore_bankmachine0_fifo_in_first, litedramcore_bankmachine0_fifo_in_payload_addr, litedramcore_bankmachine0_fifo_in_payload_we};
-assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
-assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
-assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
-assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
-assign litedramcore_bankmachine0_sink_ready = litedramcore_bankmachine0_syncfifo0_writable;
-assign litedramcore_bankmachine0_syncfifo0_we = litedramcore_bankmachine0_sink_valid;
-assign litedramcore_bankmachine0_fifo_in_first = litedramcore_bankmachine0_sink_first;
-assign litedramcore_bankmachine0_fifo_in_last = litedramcore_bankmachine0_sink_last;
-assign litedramcore_bankmachine0_fifo_in_payload_we = litedramcore_bankmachine0_sink_payload_we;
-assign litedramcore_bankmachine0_fifo_in_payload_addr = litedramcore_bankmachine0_sink_payload_addr;
-assign litedramcore_bankmachine0_source_valid = litedramcore_bankmachine0_syncfifo0_readable;
-assign litedramcore_bankmachine0_source_first = litedramcore_bankmachine0_fifo_out_first;
-assign litedramcore_bankmachine0_source_last = litedramcore_bankmachine0_fifo_out_last;
-assign litedramcore_bankmachine0_source_payload_we = litedramcore_bankmachine0_fifo_out_payload_we;
-assign litedramcore_bankmachine0_source_payload_addr = litedramcore_bankmachine0_fifo_out_payload_addr;
-assign litedramcore_bankmachine0_syncfifo0_re = litedramcore_bankmachine0_source_ready;
-always @(*) begin
-    litedramcore_bankmachine0_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine0_replace) begin
-        litedramcore_bankmachine0_wrport_adr <= (litedramcore_bankmachine0_produce - 1'd1);
+        main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write);
+assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
+assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine0_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine0_source_valid & main_litedramcore_bankmachine0_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine0_source_payload_addr[22:7] != main_litedramcore_bankmachine0_source_source_payload_addr[22:7])) begin
+            main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine0_syncfifo0_din = {main_litedramcore_bankmachine0_fifo_in_last, main_litedramcore_bankmachine0_fifo_in_first, main_litedramcore_bankmachine0_fifo_in_payload_addr, main_litedramcore_bankmachine0_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout;
+assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout;
+assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout;
+assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout;
+assign main_litedramcore_bankmachine0_sink_ready = main_litedramcore_bankmachine0_syncfifo0_writable;
+assign main_litedramcore_bankmachine0_syncfifo0_we = main_litedramcore_bankmachine0_sink_valid;
+assign main_litedramcore_bankmachine0_fifo_in_first = main_litedramcore_bankmachine0_sink_first;
+assign main_litedramcore_bankmachine0_fifo_in_last = main_litedramcore_bankmachine0_sink_last;
+assign main_litedramcore_bankmachine0_fifo_in_payload_we = main_litedramcore_bankmachine0_sink_payload_we;
+assign main_litedramcore_bankmachine0_fifo_in_payload_addr = main_litedramcore_bankmachine0_sink_payload_addr;
+assign main_litedramcore_bankmachine0_source_valid = main_litedramcore_bankmachine0_syncfifo0_readable;
+assign main_litedramcore_bankmachine0_source_first = main_litedramcore_bankmachine0_fifo_out_first;
+assign main_litedramcore_bankmachine0_source_last = main_litedramcore_bankmachine0_fifo_out_last;
+assign main_litedramcore_bankmachine0_source_payload_we = main_litedramcore_bankmachine0_fifo_out_payload_we;
+assign main_litedramcore_bankmachine0_source_payload_addr = main_litedramcore_bankmachine0_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine0_syncfifo0_re = main_litedramcore_bankmachine0_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine0_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine0_replace) begin
+        main_litedramcore_bankmachine0_wrport_adr <= (main_litedramcore_bankmachine0_produce - 1'd1);
     end else begin
-        litedramcore_bankmachine0_wrport_adr <= litedramcore_bankmachine0_produce;
-    end
-end
-assign litedramcore_bankmachine0_wrport_dat_w = litedramcore_bankmachine0_syncfifo0_din;
-assign litedramcore_bankmachine0_wrport_we = (litedramcore_bankmachine0_syncfifo0_we & (litedramcore_bankmachine0_syncfifo0_writable | litedramcore_bankmachine0_replace));
-assign litedramcore_bankmachine0_do_read = (litedramcore_bankmachine0_syncfifo0_readable & litedramcore_bankmachine0_syncfifo0_re);
-assign litedramcore_bankmachine0_rdport_adr = litedramcore_bankmachine0_consume;
-assign litedramcore_bankmachine0_syncfifo0_dout = litedramcore_bankmachine0_rdport_dat_r;
-assign litedramcore_bankmachine0_syncfifo0_writable = (litedramcore_bankmachine0_level != 5'd16);
-assign litedramcore_bankmachine0_syncfifo0_readable = (litedramcore_bankmachine0_level != 1'd0);
-assign litedramcore_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready);
-assign litedramcore_bankmachine0_pipe_valid_sink_valid = litedramcore_bankmachine0_sink_sink_valid;
-assign litedramcore_bankmachine0_sink_sink_ready = litedramcore_bankmachine0_pipe_valid_sink_ready;
-assign litedramcore_bankmachine0_pipe_valid_sink_first = litedramcore_bankmachine0_sink_sink_first;
-assign litedramcore_bankmachine0_pipe_valid_sink_last = litedramcore_bankmachine0_sink_sink_last;
-assign litedramcore_bankmachine0_pipe_valid_sink_payload_we = litedramcore_bankmachine0_sink_sink_payload_we;
-assign litedramcore_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_bankmachine0_sink_sink_payload_addr;
-assign litedramcore_bankmachine0_source_source_valid = litedramcore_bankmachine0_pipe_valid_source_valid;
-assign litedramcore_bankmachine0_pipe_valid_source_ready = litedramcore_bankmachine0_source_source_ready;
-assign litedramcore_bankmachine0_source_source_first = litedramcore_bankmachine0_pipe_valid_source_first;
-assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_pipe_valid_source_last;
-assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine0_next_state <= 4'd0;
-    litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
-    case (litedramcore_bankmachine0_state)
+        main_litedramcore_bankmachine0_wrport_adr <= main_litedramcore_bankmachine0_produce;
+    end
+end
+assign main_litedramcore_bankmachine0_wrport_dat_w = main_litedramcore_bankmachine0_syncfifo0_din;
+assign main_litedramcore_bankmachine0_wrport_we = (main_litedramcore_bankmachine0_syncfifo0_we & (main_litedramcore_bankmachine0_syncfifo0_writable | main_litedramcore_bankmachine0_replace));
+assign main_litedramcore_bankmachine0_do_read = (main_litedramcore_bankmachine0_syncfifo0_readable & main_litedramcore_bankmachine0_syncfifo0_re);
+assign main_litedramcore_bankmachine0_rdport_adr = main_litedramcore_bankmachine0_consume;
+assign main_litedramcore_bankmachine0_syncfifo0_dout = main_litedramcore_bankmachine0_rdport_dat_r;
+assign main_litedramcore_bankmachine0_syncfifo0_writable = (main_litedramcore_bankmachine0_level != 5'd16);
+assign main_litedramcore_bankmachine0_syncfifo0_readable = (main_litedramcore_bankmachine0_level != 1'd0);
+assign main_litedramcore_bankmachine0_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine0_pipe_valid_source_valid) | main_litedramcore_bankmachine0_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine0_pipe_valid_sink_valid = main_litedramcore_bankmachine0_sink_sink_valid;
+assign main_litedramcore_bankmachine0_sink_sink_ready = main_litedramcore_bankmachine0_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine0_pipe_valid_sink_first = main_litedramcore_bankmachine0_sink_sink_first;
+assign main_litedramcore_bankmachine0_pipe_valid_sink_last = main_litedramcore_bankmachine0_sink_sink_last;
+assign main_litedramcore_bankmachine0_pipe_valid_sink_payload_we = main_litedramcore_bankmachine0_sink_sink_payload_we;
+assign main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine0_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine0_source_source_valid = main_litedramcore_bankmachine0_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine0_pipe_valid_source_ready = main_litedramcore_bankmachine0_source_source_ready;
+assign main_litedramcore_bankmachine0_source_source_first = main_litedramcore_bankmachine0_pipe_valid_source_first;
+assign main_litedramcore_bankmachine0_source_source_last = main_litedramcore_bankmachine0_pipe_valid_source_last;
+assign main_litedramcore_bankmachine0_source_source_payload_we = main_litedramcore_bankmachine0_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine0_source_source_payload_addr = main_litedramcore_bankmachine0_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine0_next_state <= 4'd0;
+    builder_bankmachine0_next_state <= builder_bankmachine0_state;
+    case (builder_bankmachine0_state)
         1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                if (litedramcore_bankmachine0_cmd_ready) begin
-                    litedramcore_bankmachine0_next_state <= 3'd5;
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                if (main_litedramcore_bankmachine0_cmd_ready) begin
+                    builder_bankmachine0_next_state <= 3'd5;
                 end
             end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_next_state <= 3'd5;
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                builder_bankmachine0_next_state <= 3'd5;
             end
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                if (litedramcore_bankmachine0_cmd_ready) begin
-                    litedramcore_bankmachine0_next_state <= 3'd7;
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                if (main_litedramcore_bankmachine0_cmd_ready) begin
+                    builder_bankmachine0_next_state <= 3'd7;
                 end
             end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine0_refresh_req)) begin
-                litedramcore_bankmachine0_next_state <= 1'd0;
+            if ((~main_litedramcore_bankmachine0_refresh_req)) begin
+                builder_bankmachine0_next_state <= 1'd0;
+            end
+        end
+        3'd5: begin
+            builder_bankmachine0_next_state <= 3'd6;
+        end
+        3'd6: begin
+            builder_bankmachine0_next_state <= 2'd3;
+        end
+        3'd7: begin
+            builder_bankmachine0_next_state <= 4'd8;
+        end
+        4'd8: begin
+            builder_bankmachine0_next_state <= 1'd0;
+        end
+        default: begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
+                builder_bankmachine0_next_state <= 3'd4;
+            end else begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if ((main_litedramcore_bankmachine0_cmd_ready & main_litedramcore_bankmachine0_auto_precharge)) begin
+                                builder_bankmachine0_next_state <= 2'd2;
+                            end
+                        end else begin
+                            builder_bankmachine0_next_state <= 1'd1;
+                        end
+                    end else begin
+                        builder_bankmachine0_next_state <= 2'd3;
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine0_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
             end
         end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
         3'd5: begin
-            litedramcore_bankmachine0_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine0_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine0_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine0_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
-                litedramcore_bankmachine0_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine0_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
-                                litedramcore_bankmachine0_next_state <= 2'd2;
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
+                                main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+                            end else begin
                             end
                         end else begin
-                            litedramcore_bankmachine0_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine0_next_state <= 2'd3;
                     end
                 end
             end
@@ -4888,8 +5349,38 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine0_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+            end
+        end
+        3'd4: begin
+            main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -4907,14 +5398,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -4926,8 +5417,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -4945,13 +5436,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
-                                litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
+                                main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -4964,8 +5455,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -4983,13 +5474,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
-                                litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
+                                main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -5002,8 +5493,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5021,14 +5512,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
+                                main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
                             end
                         end else begin
                         end
@@ -5040,8 +5531,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5049,8 +5540,8 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine0_twtpcon_ready) begin
-                litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+            if (main_litedramcore_bankmachine0_twtpcon_ready) begin
+                main_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
             end
         end
         3'd5: begin
@@ -5066,15 +5557,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_row_open <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_row_open <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -5092,18 +5583,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_valid <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -5117,12 +5608,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            litedramcore_bankmachine0_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -5133,18 +5624,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_row_close <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_row_close <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
-            litedramcore_bankmachine0_row_close <= 1'd1;
+            main_litedramcore_bankmachine0_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine0_row_close <= 1'd1;
+            main_litedramcore_bankmachine0_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine0_row_close <= 1'd1;
+            main_litedramcore_bankmachine0_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -5159,15 +5650,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -5185,8 +5676,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5204,12 +5695,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -5220,18 +5711,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -5248,41 +5739,139 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+assign main_litedramcore_bankmachine1_sink_valid = main_litedramcore_bankmachine1_req_valid;
+assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_sink_ready;
+assign main_litedramcore_bankmachine1_sink_payload_we = main_litedramcore_bankmachine1_req_we;
+assign main_litedramcore_bankmachine1_sink_payload_addr = main_litedramcore_bankmachine1_req_addr;
+assign main_litedramcore_bankmachine1_sink_sink_valid = main_litedramcore_bankmachine1_source_valid;
+assign main_litedramcore_bankmachine1_source_ready = main_litedramcore_bankmachine1_sink_sink_ready;
+assign main_litedramcore_bankmachine1_sink_sink_first = main_litedramcore_bankmachine1_source_first;
+assign main_litedramcore_bankmachine1_sink_sink_last = main_litedramcore_bankmachine1_source_last;
+assign main_litedramcore_bankmachine1_sink_sink_payload_we = main_litedramcore_bankmachine1_source_payload_we;
+assign main_litedramcore_bankmachine1_sink_sink_payload_addr = main_litedramcore_bankmachine1_source_payload_addr;
+assign main_litedramcore_bankmachine1_source_source_ready = (main_litedramcore_bankmachine1_req_wdata_ready | main_litedramcore_bankmachine1_req_rdata_valid);
+assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_source_valid | main_litedramcore_bankmachine1_source_source_valid);
+assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_source_source_payload_addr[22:7]);
+assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
+always @(*) begin
+    main_litedramcore_bankmachine1_cmd_payload_a <= 16'd0;
+    if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine1_cmd_payload_a <= main_litedramcore_bankmachine1_source_source_payload_addr[22:7];
+    end else begin
+        main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write);
+assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
+assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine1_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine1_source_valid & main_litedramcore_bankmachine1_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine1_source_payload_addr[22:7] != main_litedramcore_bankmachine1_source_source_payload_addr[22:7])) begin
+            main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine1_syncfifo1_din = {main_litedramcore_bankmachine1_fifo_in_last, main_litedramcore_bankmachine1_fifo_in_first, main_litedramcore_bankmachine1_fifo_in_payload_addr, main_litedramcore_bankmachine1_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout;
+assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout;
+assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout;
+assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout;
+assign main_litedramcore_bankmachine1_sink_ready = main_litedramcore_bankmachine1_syncfifo1_writable;
+assign main_litedramcore_bankmachine1_syncfifo1_we = main_litedramcore_bankmachine1_sink_valid;
+assign main_litedramcore_bankmachine1_fifo_in_first = main_litedramcore_bankmachine1_sink_first;
+assign main_litedramcore_bankmachine1_fifo_in_last = main_litedramcore_bankmachine1_sink_last;
+assign main_litedramcore_bankmachine1_fifo_in_payload_we = main_litedramcore_bankmachine1_sink_payload_we;
+assign main_litedramcore_bankmachine1_fifo_in_payload_addr = main_litedramcore_bankmachine1_sink_payload_addr;
+assign main_litedramcore_bankmachine1_source_valid = main_litedramcore_bankmachine1_syncfifo1_readable;
+assign main_litedramcore_bankmachine1_source_first = main_litedramcore_bankmachine1_fifo_out_first;
+assign main_litedramcore_bankmachine1_source_last = main_litedramcore_bankmachine1_fifo_out_last;
+assign main_litedramcore_bankmachine1_source_payload_we = main_litedramcore_bankmachine1_fifo_out_payload_we;
+assign main_litedramcore_bankmachine1_source_payload_addr = main_litedramcore_bankmachine1_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine1_syncfifo1_re = main_litedramcore_bankmachine1_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine1_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine1_replace) begin
+        main_litedramcore_bankmachine1_wrport_adr <= (main_litedramcore_bankmachine1_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine1_wrport_adr <= main_litedramcore_bankmachine1_produce;
+    end
+end
+assign main_litedramcore_bankmachine1_wrport_dat_w = main_litedramcore_bankmachine1_syncfifo1_din;
+assign main_litedramcore_bankmachine1_wrport_we = (main_litedramcore_bankmachine1_syncfifo1_we & (main_litedramcore_bankmachine1_syncfifo1_writable | main_litedramcore_bankmachine1_replace));
+assign main_litedramcore_bankmachine1_do_read = (main_litedramcore_bankmachine1_syncfifo1_readable & main_litedramcore_bankmachine1_syncfifo1_re);
+assign main_litedramcore_bankmachine1_rdport_adr = main_litedramcore_bankmachine1_consume;
+assign main_litedramcore_bankmachine1_syncfifo1_dout = main_litedramcore_bankmachine1_rdport_dat_r;
+assign main_litedramcore_bankmachine1_syncfifo1_writable = (main_litedramcore_bankmachine1_level != 5'd16);
+assign main_litedramcore_bankmachine1_syncfifo1_readable = (main_litedramcore_bankmachine1_level != 1'd0);
+assign main_litedramcore_bankmachine1_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine1_pipe_valid_source_valid) | main_litedramcore_bankmachine1_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine1_pipe_valid_sink_valid = main_litedramcore_bankmachine1_sink_sink_valid;
+assign main_litedramcore_bankmachine1_sink_sink_ready = main_litedramcore_bankmachine1_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine1_pipe_valid_sink_first = main_litedramcore_bankmachine1_sink_sink_first;
+assign main_litedramcore_bankmachine1_pipe_valid_sink_last = main_litedramcore_bankmachine1_sink_sink_last;
+assign main_litedramcore_bankmachine1_pipe_valid_sink_payload_we = main_litedramcore_bankmachine1_sink_sink_payload_we;
+assign main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine1_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine1_source_source_valid = main_litedramcore_bankmachine1_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine1_pipe_valid_source_ready = main_litedramcore_bankmachine1_source_source_ready;
+assign main_litedramcore_bankmachine1_source_source_first = main_litedramcore_bankmachine1_pipe_valid_source_first;
+assign main_litedramcore_bankmachine1_source_source_last = main_litedramcore_bankmachine1_pipe_valid_source_last;
+assign main_litedramcore_bankmachine1_source_source_payload_we = main_litedramcore_bankmachine1_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine1_source_source_payload_addr = main_litedramcore_bankmachine1_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine1_next_state <= 4'd0;
+    builder_bankmachine1_next_state <= builder_bankmachine1_state;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                if (main_litedramcore_bankmachine1_cmd_ready) begin
+                    builder_bankmachine1_next_state <= 3'd5;
+                end
             end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                builder_bankmachine1_next_state <= 3'd5;
+            end
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                if (main_litedramcore_bankmachine1_cmd_ready) begin
+                    builder_bankmachine1_next_state <= 3'd7;
+                end
+            end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine1_refresh_req)) begin
+                builder_bankmachine1_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine1_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine1_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine1_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine1_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
+                builder_bankmachine1_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
-                                litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
-                            end else begin
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if ((main_litedramcore_bankmachine1_cmd_ready & main_litedramcore_bankmachine1_auto_precharge)) begin
+                                builder_bankmachine1_next_state <= 2'd2;
                             end
                         end else begin
+                            builder_bankmachine1_next_state <= 1'd1;
                         end
                     end else begin
+                        builder_bankmachine1_next_state <= 2'd3;
                     end
                 end
             end
@@ -5290,22 +5879,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         3'd4: begin
-            litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -5316,142 +5898,56 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
+                                main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
-assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid;
-assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready;
-assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we;
-assign litedramcore_bankmachine1_sink_payload_addr = litedramcore_bankmachine1_req_addr;
-assign litedramcore_bankmachine1_sink_sink_valid = litedramcore_bankmachine1_source_valid;
-assign litedramcore_bankmachine1_source_ready = litedramcore_bankmachine1_sink_sink_ready;
-assign litedramcore_bankmachine1_sink_sink_first = litedramcore_bankmachine1_source_first;
-assign litedramcore_bankmachine1_sink_sink_last = litedramcore_bankmachine1_source_last;
-assign litedramcore_bankmachine1_sink_sink_payload_we = litedramcore_bankmachine1_source_payload_we;
-assign litedramcore_bankmachine1_sink_sink_payload_addr = litedramcore_bankmachine1_source_payload_addr;
-assign litedramcore_bankmachine1_source_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
-assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_source_valid | litedramcore_bankmachine1_source_source_valid);
-assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_source_source_payload_addr[22:7]);
-assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
-always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_a <= 16'd0;
-    if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
-        litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_source_source_payload_addr[22:7];
-    end else begin
-        litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
-assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
-assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
-always @(*) begin
-    litedramcore_bankmachine1_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine1_source_valid & litedramcore_bankmachine1_source_source_valid)) begin
-        if ((litedramcore_bankmachine1_source_payload_addr[22:7] != litedramcore_bankmachine1_source_source_payload_addr[22:7])) begin
-            litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine1_syncfifo1_din = {litedramcore_bankmachine1_fifo_in_last, litedramcore_bankmachine1_fifo_in_first, litedramcore_bankmachine1_fifo_in_payload_addr, litedramcore_bankmachine1_fifo_in_payload_we};
-assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
-assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
-assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
-assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
-assign litedramcore_bankmachine1_sink_ready = litedramcore_bankmachine1_syncfifo1_writable;
-assign litedramcore_bankmachine1_syncfifo1_we = litedramcore_bankmachine1_sink_valid;
-assign litedramcore_bankmachine1_fifo_in_first = litedramcore_bankmachine1_sink_first;
-assign litedramcore_bankmachine1_fifo_in_last = litedramcore_bankmachine1_sink_last;
-assign litedramcore_bankmachine1_fifo_in_payload_we = litedramcore_bankmachine1_sink_payload_we;
-assign litedramcore_bankmachine1_fifo_in_payload_addr = litedramcore_bankmachine1_sink_payload_addr;
-assign litedramcore_bankmachine1_source_valid = litedramcore_bankmachine1_syncfifo1_readable;
-assign litedramcore_bankmachine1_source_first = litedramcore_bankmachine1_fifo_out_first;
-assign litedramcore_bankmachine1_source_last = litedramcore_bankmachine1_fifo_out_last;
-assign litedramcore_bankmachine1_source_payload_we = litedramcore_bankmachine1_fifo_out_payload_we;
-assign litedramcore_bankmachine1_source_payload_addr = litedramcore_bankmachine1_fifo_out_payload_addr;
-assign litedramcore_bankmachine1_syncfifo1_re = litedramcore_bankmachine1_source_ready;
-always @(*) begin
-    litedramcore_bankmachine1_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine1_replace) begin
-        litedramcore_bankmachine1_wrport_adr <= (litedramcore_bankmachine1_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine1_wrport_adr <= litedramcore_bankmachine1_produce;
-    end
-end
-assign litedramcore_bankmachine1_wrport_dat_w = litedramcore_bankmachine1_syncfifo1_din;
-assign litedramcore_bankmachine1_wrport_we = (litedramcore_bankmachine1_syncfifo1_we & (litedramcore_bankmachine1_syncfifo1_writable | litedramcore_bankmachine1_replace));
-assign litedramcore_bankmachine1_do_read = (litedramcore_bankmachine1_syncfifo1_readable & litedramcore_bankmachine1_syncfifo1_re);
-assign litedramcore_bankmachine1_rdport_adr = litedramcore_bankmachine1_consume;
-assign litedramcore_bankmachine1_syncfifo1_dout = litedramcore_bankmachine1_rdport_dat_r;
-assign litedramcore_bankmachine1_syncfifo1_writable = (litedramcore_bankmachine1_level != 5'd16);
-assign litedramcore_bankmachine1_syncfifo1_readable = (litedramcore_bankmachine1_level != 1'd0);
-assign litedramcore_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready);
-assign litedramcore_bankmachine1_pipe_valid_sink_valid = litedramcore_bankmachine1_sink_sink_valid;
-assign litedramcore_bankmachine1_sink_sink_ready = litedramcore_bankmachine1_pipe_valid_sink_ready;
-assign litedramcore_bankmachine1_pipe_valid_sink_first = litedramcore_bankmachine1_sink_sink_first;
-assign litedramcore_bankmachine1_pipe_valid_sink_last = litedramcore_bankmachine1_sink_sink_last;
-assign litedramcore_bankmachine1_pipe_valid_sink_payload_we = litedramcore_bankmachine1_sink_sink_payload_we;
-assign litedramcore_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_bankmachine1_sink_sink_payload_addr;
-assign litedramcore_bankmachine1_source_source_valid = litedramcore_bankmachine1_pipe_valid_source_valid;
-assign litedramcore_bankmachine1_pipe_valid_source_ready = litedramcore_bankmachine1_source_source_ready;
-assign litedramcore_bankmachine1_source_source_first = litedramcore_bankmachine1_pipe_valid_source_first;
-assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_pipe_valid_source_last;
-assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine1_next_state <= 4'd0;
-    litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
-    case (litedramcore_bankmachine1_state)
+always @(*) begin
+    main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                if (litedramcore_bankmachine1_cmd_ready) begin
-                    litedramcore_bankmachine1_next_state <= 3'd5;
-                end
-            end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                if (litedramcore_bankmachine1_cmd_ready) begin
-                    litedramcore_bankmachine1_next_state <= 3'd7;
-                end
-            end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine1_refresh_req)) begin
-                litedramcore_bankmachine1_next_state <= 1'd0;
-            end
         end
         3'd5: begin
-            litedramcore_bankmachine1_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine1_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine1_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine1_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
-                litedramcore_bankmachine1_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine1_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
-                                litedramcore_bankmachine1_next_state <= 2'd2;
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
+                            end else begin
+                                main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
                             end
                         end else begin
-                            litedramcore_bankmachine1_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine1_next_state <= 2'd3;
                     end
                 end
             end
@@ -5459,8 +5955,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5468,8 +5964,8 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine1_twtpcon_ready) begin
-                litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+            if (main_litedramcore_bankmachine1_twtpcon_ready) begin
+                main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
             end
         end
         3'd5: begin
@@ -5485,15 +5981,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_row_open <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_row_open <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -5511,18 +6007,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -5536,12 +6032,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            litedramcore_bankmachine1_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -5552,18 +6048,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_row_close <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_row_close <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            litedramcore_bankmachine1_row_close <= 1'd1;
+            main_litedramcore_bankmachine1_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine1_row_close <= 1'd1;
+            main_litedramcore_bankmachine1_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine1_row_close <= 1'd1;
+            main_litedramcore_bankmachine1_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -5578,15 +6074,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -5604,8 +6100,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5623,12 +6119,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -5639,18 +6135,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -5668,11 +6164,11 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
@@ -5690,13 +6186,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                                litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
+                                main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -5709,22 +6205,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -5739,8 +6235,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5758,14 +6254,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -5777,8 +6273,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5796,13 +6292,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                                litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
+                                main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -5814,38 +6310,139 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid;
+assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready;
+assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we;
+assign main_litedramcore_bankmachine2_sink_payload_addr = main_litedramcore_bankmachine2_req_addr;
+assign main_litedramcore_bankmachine2_sink_sink_valid = main_litedramcore_bankmachine2_source_valid;
+assign main_litedramcore_bankmachine2_source_ready = main_litedramcore_bankmachine2_sink_sink_ready;
+assign main_litedramcore_bankmachine2_sink_sink_first = main_litedramcore_bankmachine2_source_first;
+assign main_litedramcore_bankmachine2_sink_sink_last = main_litedramcore_bankmachine2_source_last;
+assign main_litedramcore_bankmachine2_sink_sink_payload_we = main_litedramcore_bankmachine2_source_payload_we;
+assign main_litedramcore_bankmachine2_sink_sink_payload_addr = main_litedramcore_bankmachine2_source_payload_addr;
+assign main_litedramcore_bankmachine2_source_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid);
+assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_source_valid | main_litedramcore_bankmachine2_source_source_valid);
+assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_source_source_payload_addr[22:7]);
+assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
+always @(*) begin
+    main_litedramcore_bankmachine2_cmd_payload_a <= 16'd0;
+    if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine2_cmd_payload_a <= main_litedramcore_bankmachine2_source_source_payload_addr[22:7];
+    end else begin
+        main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write);
+assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
+assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine2_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine2_source_valid & main_litedramcore_bankmachine2_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine2_source_payload_addr[22:7] != main_litedramcore_bankmachine2_source_source_payload_addr[22:7])) begin
+            main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine2_syncfifo2_din = {main_litedramcore_bankmachine2_fifo_in_last, main_litedramcore_bankmachine2_fifo_in_first, main_litedramcore_bankmachine2_fifo_in_payload_addr, main_litedramcore_bankmachine2_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
+assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
+assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
+assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
+assign main_litedramcore_bankmachine2_sink_ready = main_litedramcore_bankmachine2_syncfifo2_writable;
+assign main_litedramcore_bankmachine2_syncfifo2_we = main_litedramcore_bankmachine2_sink_valid;
+assign main_litedramcore_bankmachine2_fifo_in_first = main_litedramcore_bankmachine2_sink_first;
+assign main_litedramcore_bankmachine2_fifo_in_last = main_litedramcore_bankmachine2_sink_last;
+assign main_litedramcore_bankmachine2_fifo_in_payload_we = main_litedramcore_bankmachine2_sink_payload_we;
+assign main_litedramcore_bankmachine2_fifo_in_payload_addr = main_litedramcore_bankmachine2_sink_payload_addr;
+assign main_litedramcore_bankmachine2_source_valid = main_litedramcore_bankmachine2_syncfifo2_readable;
+assign main_litedramcore_bankmachine2_source_first = main_litedramcore_bankmachine2_fifo_out_first;
+assign main_litedramcore_bankmachine2_source_last = main_litedramcore_bankmachine2_fifo_out_last;
+assign main_litedramcore_bankmachine2_source_payload_we = main_litedramcore_bankmachine2_fifo_out_payload_we;
+assign main_litedramcore_bankmachine2_source_payload_addr = main_litedramcore_bankmachine2_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine2_syncfifo2_re = main_litedramcore_bankmachine2_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine2_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine2_replace) begin
+        main_litedramcore_bankmachine2_wrport_adr <= (main_litedramcore_bankmachine2_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine2_wrport_adr <= main_litedramcore_bankmachine2_produce;
+    end
+end
+assign main_litedramcore_bankmachine2_wrport_dat_w = main_litedramcore_bankmachine2_syncfifo2_din;
+assign main_litedramcore_bankmachine2_wrport_we = (main_litedramcore_bankmachine2_syncfifo2_we & (main_litedramcore_bankmachine2_syncfifo2_writable | main_litedramcore_bankmachine2_replace));
+assign main_litedramcore_bankmachine2_do_read = (main_litedramcore_bankmachine2_syncfifo2_readable & main_litedramcore_bankmachine2_syncfifo2_re);
+assign main_litedramcore_bankmachine2_rdport_adr = main_litedramcore_bankmachine2_consume;
+assign main_litedramcore_bankmachine2_syncfifo2_dout = main_litedramcore_bankmachine2_rdport_dat_r;
+assign main_litedramcore_bankmachine2_syncfifo2_writable = (main_litedramcore_bankmachine2_level != 5'd16);
+assign main_litedramcore_bankmachine2_syncfifo2_readable = (main_litedramcore_bankmachine2_level != 1'd0);
+assign main_litedramcore_bankmachine2_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine2_pipe_valid_source_valid) | main_litedramcore_bankmachine2_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine2_pipe_valid_sink_valid = main_litedramcore_bankmachine2_sink_sink_valid;
+assign main_litedramcore_bankmachine2_sink_sink_ready = main_litedramcore_bankmachine2_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine2_pipe_valid_sink_first = main_litedramcore_bankmachine2_sink_sink_first;
+assign main_litedramcore_bankmachine2_pipe_valid_sink_last = main_litedramcore_bankmachine2_sink_sink_last;
+assign main_litedramcore_bankmachine2_pipe_valid_sink_payload_we = main_litedramcore_bankmachine2_sink_sink_payload_we;
+assign main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine2_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine2_source_source_valid = main_litedramcore_bankmachine2_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine2_pipe_valid_source_ready = main_litedramcore_bankmachine2_source_source_ready;
+assign main_litedramcore_bankmachine2_source_source_first = main_litedramcore_bankmachine2_pipe_valid_source_first;
+assign main_litedramcore_bankmachine2_source_source_last = main_litedramcore_bankmachine2_pipe_valid_source_last;
+assign main_litedramcore_bankmachine2_source_source_payload_we = main_litedramcore_bankmachine2_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine2_source_source_payload_addr = main_litedramcore_bankmachine2_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine2_next_state <= 4'd0;
+    builder_bankmachine2_next_state <= builder_bankmachine2_state;
+    case (builder_bankmachine2_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                if (main_litedramcore_bankmachine2_cmd_ready) begin
+                    builder_bankmachine2_next_state <= 3'd5;
+                end
+            end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                builder_bankmachine2_next_state <= 3'd5;
+            end
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                if (main_litedramcore_bankmachine2_cmd_ready) begin
+                    builder_bankmachine2_next_state <= 3'd7;
+                end
+            end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine2_refresh_req)) begin
+                builder_bankmachine2_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine2_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine2_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine2_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine2_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
+                builder_bankmachine2_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                                litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
-                            end else begin
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if ((main_litedramcore_bankmachine2_cmd_ready & main_litedramcore_bankmachine2_auto_precharge)) begin
+                                builder_bankmachine2_next_state <= 2'd2;
                             end
                         end else begin
+                            builder_bankmachine2_next_state <= 1'd1;
                         end
                     end else begin
+                        builder_bankmachine2_next_state <= 2'd3;
                     end
                 end
             end
@@ -5853,13 +6450,16 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine2_row_open <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_row_open <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -5872,157 +6472,44 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
-assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid;
-assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready;
-assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we;
-assign litedramcore_bankmachine2_sink_payload_addr = litedramcore_bankmachine2_req_addr;
-assign litedramcore_bankmachine2_sink_sink_valid = litedramcore_bankmachine2_source_valid;
-assign litedramcore_bankmachine2_source_ready = litedramcore_bankmachine2_sink_sink_ready;
-assign litedramcore_bankmachine2_sink_sink_first = litedramcore_bankmachine2_source_first;
-assign litedramcore_bankmachine2_sink_sink_last = litedramcore_bankmachine2_source_last;
-assign litedramcore_bankmachine2_sink_sink_payload_we = litedramcore_bankmachine2_source_payload_we;
-assign litedramcore_bankmachine2_sink_sink_payload_addr = litedramcore_bankmachine2_source_payload_addr;
-assign litedramcore_bankmachine2_source_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
-assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_source_valid | litedramcore_bankmachine2_source_source_valid);
-assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_source_source_payload_addr[22:7]);
-assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
-always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_a <= 16'd0;
-    if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
-        litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_source_source_payload_addr[22:7];
-    end else begin
-        litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
-assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
-assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
-always @(*) begin
-    litedramcore_bankmachine2_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine2_source_valid & litedramcore_bankmachine2_source_source_valid)) begin
-        if ((litedramcore_bankmachine2_source_payload_addr[22:7] != litedramcore_bankmachine2_source_source_payload_addr[22:7])) begin
-            litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine2_syncfifo2_din = {litedramcore_bankmachine2_fifo_in_last, litedramcore_bankmachine2_fifo_in_first, litedramcore_bankmachine2_fifo_in_payload_addr, litedramcore_bankmachine2_fifo_in_payload_we};
-assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
-assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
-assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
-assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
-assign litedramcore_bankmachine2_sink_ready = litedramcore_bankmachine2_syncfifo2_writable;
-assign litedramcore_bankmachine2_syncfifo2_we = litedramcore_bankmachine2_sink_valid;
-assign litedramcore_bankmachine2_fifo_in_first = litedramcore_bankmachine2_sink_first;
-assign litedramcore_bankmachine2_fifo_in_last = litedramcore_bankmachine2_sink_last;
-assign litedramcore_bankmachine2_fifo_in_payload_we = litedramcore_bankmachine2_sink_payload_we;
-assign litedramcore_bankmachine2_fifo_in_payload_addr = litedramcore_bankmachine2_sink_payload_addr;
-assign litedramcore_bankmachine2_source_valid = litedramcore_bankmachine2_syncfifo2_readable;
-assign litedramcore_bankmachine2_source_first = litedramcore_bankmachine2_fifo_out_first;
-assign litedramcore_bankmachine2_source_last = litedramcore_bankmachine2_fifo_out_last;
-assign litedramcore_bankmachine2_source_payload_we = litedramcore_bankmachine2_fifo_out_payload_we;
-assign litedramcore_bankmachine2_source_payload_addr = litedramcore_bankmachine2_fifo_out_payload_addr;
-assign litedramcore_bankmachine2_syncfifo2_re = litedramcore_bankmachine2_source_ready;
-always @(*) begin
-    litedramcore_bankmachine2_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine2_replace) begin
-        litedramcore_bankmachine2_wrport_adr <= (litedramcore_bankmachine2_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine2_wrport_adr <= litedramcore_bankmachine2_produce;
-    end
-end
-assign litedramcore_bankmachine2_wrport_dat_w = litedramcore_bankmachine2_syncfifo2_din;
-assign litedramcore_bankmachine2_wrport_we = (litedramcore_bankmachine2_syncfifo2_we & (litedramcore_bankmachine2_syncfifo2_writable | litedramcore_bankmachine2_replace));
-assign litedramcore_bankmachine2_do_read = (litedramcore_bankmachine2_syncfifo2_readable & litedramcore_bankmachine2_syncfifo2_re);
-assign litedramcore_bankmachine2_rdport_adr = litedramcore_bankmachine2_consume;
-assign litedramcore_bankmachine2_syncfifo2_dout = litedramcore_bankmachine2_rdport_dat_r;
-assign litedramcore_bankmachine2_syncfifo2_writable = (litedramcore_bankmachine2_level != 5'd16);
-assign litedramcore_bankmachine2_syncfifo2_readable = (litedramcore_bankmachine2_level != 1'd0);
-assign litedramcore_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready);
-assign litedramcore_bankmachine2_pipe_valid_sink_valid = litedramcore_bankmachine2_sink_sink_valid;
-assign litedramcore_bankmachine2_sink_sink_ready = litedramcore_bankmachine2_pipe_valid_sink_ready;
-assign litedramcore_bankmachine2_pipe_valid_sink_first = litedramcore_bankmachine2_sink_sink_first;
-assign litedramcore_bankmachine2_pipe_valid_sink_last = litedramcore_bankmachine2_sink_sink_last;
-assign litedramcore_bankmachine2_pipe_valid_sink_payload_we = litedramcore_bankmachine2_sink_sink_payload_we;
-assign litedramcore_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_bankmachine2_sink_sink_payload_addr;
-assign litedramcore_bankmachine2_source_source_valid = litedramcore_bankmachine2_pipe_valid_source_valid;
-assign litedramcore_bankmachine2_pipe_valid_source_ready = litedramcore_bankmachine2_source_source_ready;
-assign litedramcore_bankmachine2_source_source_first = litedramcore_bankmachine2_pipe_valid_source_first;
-assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_pipe_valid_source_last;
-assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine2_next_state <= 4'd0;
-    litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
-    case (litedramcore_bankmachine2_state)
+always @(*) begin
+    main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                if (litedramcore_bankmachine2_cmd_ready) begin
-                    litedramcore_bankmachine2_next_state <= 3'd5;
-                end
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                if (litedramcore_bankmachine2_cmd_ready) begin
-                    litedramcore_bankmachine2_next_state <= 3'd7;
-                end
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine2_refresh_req)) begin
-                litedramcore_bankmachine2_next_state <= 1'd0;
-            end
         end
         3'd5: begin
-            litedramcore_bankmachine2_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine2_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine2_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine2_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
-                litedramcore_bankmachine2_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
-                                litedramcore_bankmachine2_next_state <= 2'd2;
-                            end
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
                         end else begin
-                            litedramcore_bankmachine2_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine2_next_state <= 2'd3;
                     end
                 end
             end
@@ -6030,15 +6517,41 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_row_close <= 1'd0;
+    case (builder_bankmachine2_state)
+        1'd1: begin
+            main_litedramcore_bankmachine2_row_close <= 1'd1;
+        end
+        2'd2: begin
+            main_litedramcore_bankmachine2_row_close <= 1'd1;
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            main_litedramcore_bankmachine2_row_close <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -6056,8 +6569,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6075,12 +6588,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -6091,18 +6604,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -6120,11 +6633,11 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
@@ -6142,13 +6655,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
-                                litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
+                                main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -6161,22 +6674,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -6191,8 +6704,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6210,14 +6723,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -6229,8 +6742,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6248,13 +6761,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
-                                litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
+                                main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -6267,8 +6780,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6286,13 +6799,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
-                                litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
+                                main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -6305,8 +6818,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6324,14 +6837,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
+                                main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
                             end
                         end else begin
                         end
@@ -6343,8 +6856,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6352,8 +6865,8 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine2_twtpcon_ready) begin
-                litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+            if (main_litedramcore_bankmachine2_twtpcon_ready) begin
+                main_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
             end
         end
         3'd5: begin
@@ -6368,67 +6881,139 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine2_row_open <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+assign main_litedramcore_bankmachine3_sink_valid = main_litedramcore_bankmachine3_req_valid;
+assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_sink_ready;
+assign main_litedramcore_bankmachine3_sink_payload_we = main_litedramcore_bankmachine3_req_we;
+assign main_litedramcore_bankmachine3_sink_payload_addr = main_litedramcore_bankmachine3_req_addr;
+assign main_litedramcore_bankmachine3_sink_sink_valid = main_litedramcore_bankmachine3_source_valid;
+assign main_litedramcore_bankmachine3_source_ready = main_litedramcore_bankmachine3_sink_sink_ready;
+assign main_litedramcore_bankmachine3_sink_sink_first = main_litedramcore_bankmachine3_source_first;
+assign main_litedramcore_bankmachine3_sink_sink_last = main_litedramcore_bankmachine3_source_last;
+assign main_litedramcore_bankmachine3_sink_sink_payload_we = main_litedramcore_bankmachine3_source_payload_we;
+assign main_litedramcore_bankmachine3_sink_sink_payload_addr = main_litedramcore_bankmachine3_source_payload_addr;
+assign main_litedramcore_bankmachine3_source_source_ready = (main_litedramcore_bankmachine3_req_wdata_ready | main_litedramcore_bankmachine3_req_rdata_valid);
+assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_source_valid | main_litedramcore_bankmachine3_source_source_valid);
+assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_source_source_payload_addr[22:7]);
+assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
+always @(*) begin
+    main_litedramcore_bankmachine3_cmd_payload_a <= 16'd0;
+    if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine3_cmd_payload_a <= main_litedramcore_bankmachine3_source_source_payload_addr[22:7];
+    end else begin
+        main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write);
+assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
+assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine3_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine3_source_valid & main_litedramcore_bankmachine3_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine3_source_payload_addr[22:7] != main_litedramcore_bankmachine3_source_source_payload_addr[22:7])) begin
+            main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine3_syncfifo3_din = {main_litedramcore_bankmachine3_fifo_in_last, main_litedramcore_bankmachine3_fifo_in_first, main_litedramcore_bankmachine3_fifo_in_payload_addr, main_litedramcore_bankmachine3_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout;
+assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout;
+assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout;
+assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout;
+assign main_litedramcore_bankmachine3_sink_ready = main_litedramcore_bankmachine3_syncfifo3_writable;
+assign main_litedramcore_bankmachine3_syncfifo3_we = main_litedramcore_bankmachine3_sink_valid;
+assign main_litedramcore_bankmachine3_fifo_in_first = main_litedramcore_bankmachine3_sink_first;
+assign main_litedramcore_bankmachine3_fifo_in_last = main_litedramcore_bankmachine3_sink_last;
+assign main_litedramcore_bankmachine3_fifo_in_payload_we = main_litedramcore_bankmachine3_sink_payload_we;
+assign main_litedramcore_bankmachine3_fifo_in_payload_addr = main_litedramcore_bankmachine3_sink_payload_addr;
+assign main_litedramcore_bankmachine3_source_valid = main_litedramcore_bankmachine3_syncfifo3_readable;
+assign main_litedramcore_bankmachine3_source_first = main_litedramcore_bankmachine3_fifo_out_first;
+assign main_litedramcore_bankmachine3_source_last = main_litedramcore_bankmachine3_fifo_out_last;
+assign main_litedramcore_bankmachine3_source_payload_we = main_litedramcore_bankmachine3_fifo_out_payload_we;
+assign main_litedramcore_bankmachine3_source_payload_addr = main_litedramcore_bankmachine3_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine3_syncfifo3_re = main_litedramcore_bankmachine3_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine3_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine3_replace) begin
+        main_litedramcore_bankmachine3_wrport_adr <= (main_litedramcore_bankmachine3_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine3_wrport_adr <= main_litedramcore_bankmachine3_produce;
+    end
+end
+assign main_litedramcore_bankmachine3_wrport_dat_w = main_litedramcore_bankmachine3_syncfifo3_din;
+assign main_litedramcore_bankmachine3_wrport_we = (main_litedramcore_bankmachine3_syncfifo3_we & (main_litedramcore_bankmachine3_syncfifo3_writable | main_litedramcore_bankmachine3_replace));
+assign main_litedramcore_bankmachine3_do_read = (main_litedramcore_bankmachine3_syncfifo3_readable & main_litedramcore_bankmachine3_syncfifo3_re);
+assign main_litedramcore_bankmachine3_rdport_adr = main_litedramcore_bankmachine3_consume;
+assign main_litedramcore_bankmachine3_syncfifo3_dout = main_litedramcore_bankmachine3_rdport_dat_r;
+assign main_litedramcore_bankmachine3_syncfifo3_writable = (main_litedramcore_bankmachine3_level != 5'd16);
+assign main_litedramcore_bankmachine3_syncfifo3_readable = (main_litedramcore_bankmachine3_level != 1'd0);
+assign main_litedramcore_bankmachine3_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine3_pipe_valid_source_valid) | main_litedramcore_bankmachine3_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine3_pipe_valid_sink_valid = main_litedramcore_bankmachine3_sink_sink_valid;
+assign main_litedramcore_bankmachine3_sink_sink_ready = main_litedramcore_bankmachine3_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine3_pipe_valid_sink_first = main_litedramcore_bankmachine3_sink_sink_first;
+assign main_litedramcore_bankmachine3_pipe_valid_sink_last = main_litedramcore_bankmachine3_sink_sink_last;
+assign main_litedramcore_bankmachine3_pipe_valid_sink_payload_we = main_litedramcore_bankmachine3_sink_sink_payload_we;
+assign main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine3_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine3_source_source_valid = main_litedramcore_bankmachine3_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine3_pipe_valid_source_ready = main_litedramcore_bankmachine3_source_source_ready;
+assign main_litedramcore_bankmachine3_source_source_first = main_litedramcore_bankmachine3_pipe_valid_source_first;
+assign main_litedramcore_bankmachine3_source_source_last = main_litedramcore_bankmachine3_pipe_valid_source_last;
+assign main_litedramcore_bankmachine3_source_source_payload_we = main_litedramcore_bankmachine3_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine3_source_source_payload_addr = main_litedramcore_bankmachine3_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine3_next_state <= 4'd0;
+    builder_bankmachine3_next_state <= builder_bankmachine3_state;
+    case (builder_bankmachine3_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                if (main_litedramcore_bankmachine3_cmd_ready) begin
+                    builder_bankmachine3_next_state <= 3'd5;
+                end
+            end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                builder_bankmachine3_next_state <= 3'd5;
+            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                if (main_litedramcore_bankmachine3_cmd_ready) begin
+                    builder_bankmachine3_next_state <= 3'd7;
+                end
             end
         end
         3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine2_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine2_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_cmd_valid <= 1'd1;
+            if ((~main_litedramcore_bankmachine3_refresh_req)) begin
+                builder_bankmachine3_next_state <= 1'd0;
             end
         end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_cmd_valid <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
         3'd5: begin
+            builder_bankmachine3_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine3_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine3_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine3_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
+                builder_bankmachine3_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            litedramcore_bankmachine2_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin
+                                builder_bankmachine3_next_state <= 2'd2;
+                            end
                         end else begin
+                            builder_bankmachine3_next_state <= 1'd1;
                         end
                     end else begin
+                        builder_bankmachine3_next_state <= 2'd3;
                     end
                 end
             end
@@ -6436,173 +7021,34 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_row_close <= 1'd0;
-    case (litedramcore_bankmachine2_state)
-        1'd1: begin
-            litedramcore_bankmachine2_row_close <= 1'd1;
-        end
-        2'd2: begin
-            litedramcore_bankmachine2_row_close <= 1'd1;
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            litedramcore_bankmachine2_row_close <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid;
-assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready;
-assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we;
-assign litedramcore_bankmachine3_sink_payload_addr = litedramcore_bankmachine3_req_addr;
-assign litedramcore_bankmachine3_sink_sink_valid = litedramcore_bankmachine3_source_valid;
-assign litedramcore_bankmachine3_source_ready = litedramcore_bankmachine3_sink_sink_ready;
-assign litedramcore_bankmachine3_sink_sink_first = litedramcore_bankmachine3_source_first;
-assign litedramcore_bankmachine3_sink_sink_last = litedramcore_bankmachine3_source_last;
-assign litedramcore_bankmachine3_sink_sink_payload_we = litedramcore_bankmachine3_source_payload_we;
-assign litedramcore_bankmachine3_sink_sink_payload_addr = litedramcore_bankmachine3_source_payload_addr;
-assign litedramcore_bankmachine3_source_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
-assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_source_valid | litedramcore_bankmachine3_source_source_valid);
-assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_source_source_payload_addr[22:7]);
-assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
-always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_a <= 16'd0;
-    if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
-        litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_source_source_payload_addr[22:7];
-    end else begin
-        litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
-assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
-assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
-always @(*) begin
-    litedramcore_bankmachine3_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine3_source_valid & litedramcore_bankmachine3_source_source_valid)) begin
-        if ((litedramcore_bankmachine3_source_payload_addr[22:7] != litedramcore_bankmachine3_source_source_payload_addr[22:7])) begin
-            litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine3_syncfifo3_din = {litedramcore_bankmachine3_fifo_in_last, litedramcore_bankmachine3_fifo_in_first, litedramcore_bankmachine3_fifo_in_payload_addr, litedramcore_bankmachine3_fifo_in_payload_we};
-assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
-assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
-assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
-assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
-assign litedramcore_bankmachine3_sink_ready = litedramcore_bankmachine3_syncfifo3_writable;
-assign litedramcore_bankmachine3_syncfifo3_we = litedramcore_bankmachine3_sink_valid;
-assign litedramcore_bankmachine3_fifo_in_first = litedramcore_bankmachine3_sink_first;
-assign litedramcore_bankmachine3_fifo_in_last = litedramcore_bankmachine3_sink_last;
-assign litedramcore_bankmachine3_fifo_in_payload_we = litedramcore_bankmachine3_sink_payload_we;
-assign litedramcore_bankmachine3_fifo_in_payload_addr = litedramcore_bankmachine3_sink_payload_addr;
-assign litedramcore_bankmachine3_source_valid = litedramcore_bankmachine3_syncfifo3_readable;
-assign litedramcore_bankmachine3_source_first = litedramcore_bankmachine3_fifo_out_first;
-assign litedramcore_bankmachine3_source_last = litedramcore_bankmachine3_fifo_out_last;
-assign litedramcore_bankmachine3_source_payload_we = litedramcore_bankmachine3_fifo_out_payload_we;
-assign litedramcore_bankmachine3_source_payload_addr = litedramcore_bankmachine3_fifo_out_payload_addr;
-assign litedramcore_bankmachine3_syncfifo3_re = litedramcore_bankmachine3_source_ready;
-always @(*) begin
-    litedramcore_bankmachine3_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine3_replace) begin
-        litedramcore_bankmachine3_wrport_adr <= (litedramcore_bankmachine3_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine3_wrport_adr <= litedramcore_bankmachine3_produce;
-    end
-end
-assign litedramcore_bankmachine3_wrport_dat_w = litedramcore_bankmachine3_syncfifo3_din;
-assign litedramcore_bankmachine3_wrport_we = (litedramcore_bankmachine3_syncfifo3_we & (litedramcore_bankmachine3_syncfifo3_writable | litedramcore_bankmachine3_replace));
-assign litedramcore_bankmachine3_do_read = (litedramcore_bankmachine3_syncfifo3_readable & litedramcore_bankmachine3_syncfifo3_re);
-assign litedramcore_bankmachine3_rdport_adr = litedramcore_bankmachine3_consume;
-assign litedramcore_bankmachine3_syncfifo3_dout = litedramcore_bankmachine3_rdport_dat_r;
-assign litedramcore_bankmachine3_syncfifo3_writable = (litedramcore_bankmachine3_level != 5'd16);
-assign litedramcore_bankmachine3_syncfifo3_readable = (litedramcore_bankmachine3_level != 1'd0);
-assign litedramcore_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready);
-assign litedramcore_bankmachine3_pipe_valid_sink_valid = litedramcore_bankmachine3_sink_sink_valid;
-assign litedramcore_bankmachine3_sink_sink_ready = litedramcore_bankmachine3_pipe_valid_sink_ready;
-assign litedramcore_bankmachine3_pipe_valid_sink_first = litedramcore_bankmachine3_sink_sink_first;
-assign litedramcore_bankmachine3_pipe_valid_sink_last = litedramcore_bankmachine3_sink_sink_last;
-assign litedramcore_bankmachine3_pipe_valid_sink_payload_we = litedramcore_bankmachine3_sink_sink_payload_we;
-assign litedramcore_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_bankmachine3_sink_sink_payload_addr;
-assign litedramcore_bankmachine3_source_source_valid = litedramcore_bankmachine3_pipe_valid_source_valid;
-assign litedramcore_bankmachine3_pipe_valid_source_ready = litedramcore_bankmachine3_source_source_ready;
-assign litedramcore_bankmachine3_source_source_first = litedramcore_bankmachine3_pipe_valid_source_first;
-assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_pipe_valid_source_last;
-assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine3_next_state <= 4'd0;
-    litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                if (litedramcore_bankmachine3_cmd_ready) begin
-                    litedramcore_bankmachine3_next_state <= 3'd5;
-                end
-            end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                if (litedramcore_bankmachine3_cmd_ready) begin
-                    litedramcore_bankmachine3_next_state <= 3'd7;
-                end
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine3_refresh_req)) begin
-                litedramcore_bankmachine3_next_state <= 1'd0;
-            end
         end
         3'd5: begin
-            litedramcore_bankmachine3_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine3_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine3_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine3_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
-                litedramcore_bankmachine3_next_state <= 3'd4;
-            end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
-                                litedramcore_bankmachine3_next_state <= 2'd2;
-                            end
-                        end else begin
-                            litedramcore_bankmachine3_next_state <= 1'd1;
-                        end
-                    end else begin
-                        litedramcore_bankmachine3_next_state <= 2'd3;
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6620,12 +7066,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -6636,18 +7082,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -6665,11 +7111,11 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
@@ -6687,13 +7133,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
-                                litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
+                                main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -6706,22 +7152,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -6736,8 +7182,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6755,14 +7201,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -6774,8 +7220,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6793,13 +7239,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
-                                litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
+                                main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -6812,8 +7258,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6831,13 +7277,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
-                                litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
+                                main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -6850,8 +7296,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6869,14 +7315,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
+                                main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
                             end
                         end else begin
                         end
@@ -6888,8 +7334,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6897,8 +7343,8 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine3_twtpcon_ready) begin
-                litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+            if (main_litedramcore_bankmachine3_twtpcon_ready) begin
+                main_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
             end
         end
         3'd5: begin
@@ -6914,15 +7360,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_row_open <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_row_open <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -6940,18 +7386,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -6965,12 +7411,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            litedramcore_bankmachine3_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -6981,18 +7427,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_row_close <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_row_close <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
-            litedramcore_bankmachine3_row_close <= 1'd1;
+            main_litedramcore_bankmachine3_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine3_row_close <= 1'd1;
+            main_litedramcore_bankmachine3_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine3_row_close <= 1'd1;
+            main_litedramcore_bankmachine3_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -7006,165 +7452,180 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+assign main_litedramcore_bankmachine4_sink_valid = main_litedramcore_bankmachine4_req_valid;
+assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_sink_ready;
+assign main_litedramcore_bankmachine4_sink_payload_we = main_litedramcore_bankmachine4_req_we;
+assign main_litedramcore_bankmachine4_sink_payload_addr = main_litedramcore_bankmachine4_req_addr;
+assign main_litedramcore_bankmachine4_sink_sink_valid = main_litedramcore_bankmachine4_source_valid;
+assign main_litedramcore_bankmachine4_source_ready = main_litedramcore_bankmachine4_sink_sink_ready;
+assign main_litedramcore_bankmachine4_sink_sink_first = main_litedramcore_bankmachine4_source_first;
+assign main_litedramcore_bankmachine4_sink_sink_last = main_litedramcore_bankmachine4_source_last;
+assign main_litedramcore_bankmachine4_sink_sink_payload_we = main_litedramcore_bankmachine4_source_payload_we;
+assign main_litedramcore_bankmachine4_sink_sink_payload_addr = main_litedramcore_bankmachine4_source_payload_addr;
+assign main_litedramcore_bankmachine4_source_source_ready = (main_litedramcore_bankmachine4_req_wdata_ready | main_litedramcore_bankmachine4_req_rdata_valid);
+assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_source_valid | main_litedramcore_bankmachine4_source_source_valid);
+assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_source_source_payload_addr[22:7]);
+assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
+always @(*) begin
+    main_litedramcore_bankmachine4_cmd_payload_a <= 16'd0;
+    if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine4_cmd_payload_a <= main_litedramcore_bankmachine4_source_source_payload_addr[22:7];
+    end else begin
+        main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write);
+assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
+assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine4_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine4_source_valid & main_litedramcore_bankmachine4_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine4_source_payload_addr[22:7] != main_litedramcore_bankmachine4_source_source_payload_addr[22:7])) begin
+            main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine4_syncfifo4_din = {main_litedramcore_bankmachine4_fifo_in_last, main_litedramcore_bankmachine4_fifo_in_first, main_litedramcore_bankmachine4_fifo_in_payload_addr, main_litedramcore_bankmachine4_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout;
+assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout;
+assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout;
+assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout;
+assign main_litedramcore_bankmachine4_sink_ready = main_litedramcore_bankmachine4_syncfifo4_writable;
+assign main_litedramcore_bankmachine4_syncfifo4_we = main_litedramcore_bankmachine4_sink_valid;
+assign main_litedramcore_bankmachine4_fifo_in_first = main_litedramcore_bankmachine4_sink_first;
+assign main_litedramcore_bankmachine4_fifo_in_last = main_litedramcore_bankmachine4_sink_last;
+assign main_litedramcore_bankmachine4_fifo_in_payload_we = main_litedramcore_bankmachine4_sink_payload_we;
+assign main_litedramcore_bankmachine4_fifo_in_payload_addr = main_litedramcore_bankmachine4_sink_payload_addr;
+assign main_litedramcore_bankmachine4_source_valid = main_litedramcore_bankmachine4_syncfifo4_readable;
+assign main_litedramcore_bankmachine4_source_first = main_litedramcore_bankmachine4_fifo_out_first;
+assign main_litedramcore_bankmachine4_source_last = main_litedramcore_bankmachine4_fifo_out_last;
+assign main_litedramcore_bankmachine4_source_payload_we = main_litedramcore_bankmachine4_fifo_out_payload_we;
+assign main_litedramcore_bankmachine4_source_payload_addr = main_litedramcore_bankmachine4_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine4_syncfifo4_re = main_litedramcore_bankmachine4_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine4_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine4_replace) begin
+        main_litedramcore_bankmachine4_wrport_adr <= (main_litedramcore_bankmachine4_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine4_wrport_adr <= main_litedramcore_bankmachine4_produce;
+    end
+end
+assign main_litedramcore_bankmachine4_wrport_dat_w = main_litedramcore_bankmachine4_syncfifo4_din;
+assign main_litedramcore_bankmachine4_wrport_we = (main_litedramcore_bankmachine4_syncfifo4_we & (main_litedramcore_bankmachine4_syncfifo4_writable | main_litedramcore_bankmachine4_replace));
+assign main_litedramcore_bankmachine4_do_read = (main_litedramcore_bankmachine4_syncfifo4_readable & main_litedramcore_bankmachine4_syncfifo4_re);
+assign main_litedramcore_bankmachine4_rdport_adr = main_litedramcore_bankmachine4_consume;
+assign main_litedramcore_bankmachine4_syncfifo4_dout = main_litedramcore_bankmachine4_rdport_dat_r;
+assign main_litedramcore_bankmachine4_syncfifo4_writable = (main_litedramcore_bankmachine4_level != 5'd16);
+assign main_litedramcore_bankmachine4_syncfifo4_readable = (main_litedramcore_bankmachine4_level != 1'd0);
+assign main_litedramcore_bankmachine4_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine4_pipe_valid_source_valid) | main_litedramcore_bankmachine4_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine4_pipe_valid_sink_valid = main_litedramcore_bankmachine4_sink_sink_valid;
+assign main_litedramcore_bankmachine4_sink_sink_ready = main_litedramcore_bankmachine4_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine4_pipe_valid_sink_first = main_litedramcore_bankmachine4_sink_sink_first;
+assign main_litedramcore_bankmachine4_pipe_valid_sink_last = main_litedramcore_bankmachine4_sink_sink_last;
+assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_we = main_litedramcore_bankmachine4_sink_sink_payload_we;
+assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine4_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine4_source_source_valid = main_litedramcore_bankmachine4_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine4_pipe_valid_source_ready = main_litedramcore_bankmachine4_source_source_ready;
+assign main_litedramcore_bankmachine4_source_source_first = main_litedramcore_bankmachine4_pipe_valid_source_first;
+assign main_litedramcore_bankmachine4_source_source_last = main_litedramcore_bankmachine4_pipe_valid_source_last;
+assign main_litedramcore_bankmachine4_source_source_payload_we = main_litedramcore_bankmachine4_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine4_source_source_payload_addr = main_litedramcore_bankmachine4_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine4_next_state <= 4'd0;
+    builder_bankmachine4_next_state <= builder_bankmachine4_state;
+    case (builder_bankmachine4_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                if (main_litedramcore_bankmachine4_cmd_ready) begin
+                    builder_bankmachine4_next_state <= 3'd5;
+                end
+            end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                builder_bankmachine4_next_state <= 3'd5;
+            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                if (main_litedramcore_bankmachine4_cmd_ready) begin
+                    builder_bankmachine4_next_state <= 3'd7;
+                end
             end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine4_refresh_req)) begin
+                builder_bankmachine4_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine4_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine4_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine4_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine4_next_state <= 1'd0;
         end
         default: begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
+                builder_bankmachine4_next_state <= 3'd4;
+            end else begin
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if ((main_litedramcore_bankmachine4_cmd_ready & main_litedramcore_bankmachine4_auto_precharge)) begin
+                                builder_bankmachine4_next_state <= 2'd2;
+                            end
+                        end else begin
+                            builder_bankmachine4_next_state <= 1'd1;
+                        end
+                    end else begin
+                        builder_bankmachine4_next_state <= 2'd3;
+                    end
+                end
+            end
         end
     endcase
 end
-assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid;
-assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready;
-assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we;
-assign litedramcore_bankmachine4_sink_payload_addr = litedramcore_bankmachine4_req_addr;
-assign litedramcore_bankmachine4_sink_sink_valid = litedramcore_bankmachine4_source_valid;
-assign litedramcore_bankmachine4_source_ready = litedramcore_bankmachine4_sink_sink_ready;
-assign litedramcore_bankmachine4_sink_sink_first = litedramcore_bankmachine4_source_first;
-assign litedramcore_bankmachine4_sink_sink_last = litedramcore_bankmachine4_source_last;
-assign litedramcore_bankmachine4_sink_sink_payload_we = litedramcore_bankmachine4_source_payload_we;
-assign litedramcore_bankmachine4_sink_sink_payload_addr = litedramcore_bankmachine4_source_payload_addr;
-assign litedramcore_bankmachine4_source_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
-assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_source_valid | litedramcore_bankmachine4_source_source_valid);
-assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_source_source_payload_addr[22:7]);
-assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
-always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_a <= 16'd0;
-    if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
-        litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_source_source_payload_addr[22:7];
-    end else begin
-        litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
-assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
-assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
-always @(*) begin
-    litedramcore_bankmachine4_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine4_source_valid & litedramcore_bankmachine4_source_source_valid)) begin
-        if ((litedramcore_bankmachine4_source_payload_addr[22:7] != litedramcore_bankmachine4_source_source_payload_addr[22:7])) begin
-            litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine4_syncfifo4_din = {litedramcore_bankmachine4_fifo_in_last, litedramcore_bankmachine4_fifo_in_first, litedramcore_bankmachine4_fifo_in_payload_addr, litedramcore_bankmachine4_fifo_in_payload_we};
-assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
-assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
-assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
-assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
-assign litedramcore_bankmachine4_sink_ready = litedramcore_bankmachine4_syncfifo4_writable;
-assign litedramcore_bankmachine4_syncfifo4_we = litedramcore_bankmachine4_sink_valid;
-assign litedramcore_bankmachine4_fifo_in_first = litedramcore_bankmachine4_sink_first;
-assign litedramcore_bankmachine4_fifo_in_last = litedramcore_bankmachine4_sink_last;
-assign litedramcore_bankmachine4_fifo_in_payload_we = litedramcore_bankmachine4_sink_payload_we;
-assign litedramcore_bankmachine4_fifo_in_payload_addr = litedramcore_bankmachine4_sink_payload_addr;
-assign litedramcore_bankmachine4_source_valid = litedramcore_bankmachine4_syncfifo4_readable;
-assign litedramcore_bankmachine4_source_first = litedramcore_bankmachine4_fifo_out_first;
-assign litedramcore_bankmachine4_source_last = litedramcore_bankmachine4_fifo_out_last;
-assign litedramcore_bankmachine4_source_payload_we = litedramcore_bankmachine4_fifo_out_payload_we;
-assign litedramcore_bankmachine4_source_payload_addr = litedramcore_bankmachine4_fifo_out_payload_addr;
-assign litedramcore_bankmachine4_syncfifo4_re = litedramcore_bankmachine4_source_ready;
-always @(*) begin
-    litedramcore_bankmachine4_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine4_replace) begin
-        litedramcore_bankmachine4_wrport_adr <= (litedramcore_bankmachine4_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine4_wrport_adr <= litedramcore_bankmachine4_produce;
-    end
-end
-assign litedramcore_bankmachine4_wrport_dat_w = litedramcore_bankmachine4_syncfifo4_din;
-assign litedramcore_bankmachine4_wrport_we = (litedramcore_bankmachine4_syncfifo4_we & (litedramcore_bankmachine4_syncfifo4_writable | litedramcore_bankmachine4_replace));
-assign litedramcore_bankmachine4_do_read = (litedramcore_bankmachine4_syncfifo4_readable & litedramcore_bankmachine4_syncfifo4_re);
-assign litedramcore_bankmachine4_rdport_adr = litedramcore_bankmachine4_consume;
-assign litedramcore_bankmachine4_syncfifo4_dout = litedramcore_bankmachine4_rdport_dat_r;
-assign litedramcore_bankmachine4_syncfifo4_writable = (litedramcore_bankmachine4_level != 5'd16);
-assign litedramcore_bankmachine4_syncfifo4_readable = (litedramcore_bankmachine4_level != 1'd0);
-assign litedramcore_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready);
-assign litedramcore_bankmachine4_pipe_valid_sink_valid = litedramcore_bankmachine4_sink_sink_valid;
-assign litedramcore_bankmachine4_sink_sink_ready = litedramcore_bankmachine4_pipe_valid_sink_ready;
-assign litedramcore_bankmachine4_pipe_valid_sink_first = litedramcore_bankmachine4_sink_sink_first;
-assign litedramcore_bankmachine4_pipe_valid_sink_last = litedramcore_bankmachine4_sink_sink_last;
-assign litedramcore_bankmachine4_pipe_valid_sink_payload_we = litedramcore_bankmachine4_sink_sink_payload_we;
-assign litedramcore_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_bankmachine4_sink_sink_payload_addr;
-assign litedramcore_bankmachine4_source_source_valid = litedramcore_bankmachine4_pipe_valid_source_valid;
-assign litedramcore_bankmachine4_pipe_valid_source_ready = litedramcore_bankmachine4_source_source_ready;
-assign litedramcore_bankmachine4_source_source_first = litedramcore_bankmachine4_pipe_valid_source_first;
-assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_pipe_valid_source_last;
-assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine4_next_state <= 4'd0;
-    litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
-    case (litedramcore_bankmachine4_state)
+always @(*) begin
+    main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                if (litedramcore_bankmachine4_cmd_ready) begin
-                    litedramcore_bankmachine4_next_state <= 3'd5;
-                end
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                if (litedramcore_bankmachine4_cmd_ready) begin
-                    litedramcore_bankmachine4_next_state <= 3'd7;
-                end
-            end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine4_refresh_req)) begin
-                litedramcore_bankmachine4_next_state <= 1'd0;
-            end
         end
         3'd5: begin
-            litedramcore_bankmachine4_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine4_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine4_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine4_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
-                litedramcore_bankmachine4_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
-                                litedramcore_bankmachine4_next_state <= 2'd2;
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
+                                main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+                            end else begin
                             end
                         end else begin
-                            litedramcore_bankmachine4_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine4_next_state <= 2'd3;
                     end
                 end
             end
@@ -7172,8 +7633,38 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine4_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+            end
+        end
+        3'd4: begin
+            main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7191,14 +7682,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -7210,8 +7701,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7229,13 +7720,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
-                                litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
+                                main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -7248,8 +7739,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7267,13 +7758,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
-                                litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
+                                main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -7286,8 +7777,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7305,14 +7796,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
+                                main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready;
                             end
                         end else begin
                         end
@@ -7324,8 +7815,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7333,8 +7824,8 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine4_twtpcon_ready) begin
-                litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+            if (main_litedramcore_bankmachine4_twtpcon_ready) begin
+                main_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
             end
         end
         3'd5: begin
@@ -7350,15 +7841,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_row_open <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_row_open <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -7376,18 +7867,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_valid <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -7401,12 +7892,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            litedramcore_bankmachine4_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -7417,18 +7908,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_row_close <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_row_close <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            litedramcore_bankmachine4_row_close <= 1'd1;
+            main_litedramcore_bankmachine4_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine4_row_close <= 1'd1;
+            main_litedramcore_bankmachine4_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine4_row_close <= 1'd1;
+            main_litedramcore_bankmachine4_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -7443,15 +7934,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -7469,8 +7960,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7488,12 +7979,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -7504,18 +7995,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -7532,41 +8023,139 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+assign main_litedramcore_bankmachine5_sink_valid = main_litedramcore_bankmachine5_req_valid;
+assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_sink_ready;
+assign main_litedramcore_bankmachine5_sink_payload_we = main_litedramcore_bankmachine5_req_we;
+assign main_litedramcore_bankmachine5_sink_payload_addr = main_litedramcore_bankmachine5_req_addr;
+assign main_litedramcore_bankmachine5_sink_sink_valid = main_litedramcore_bankmachine5_source_valid;
+assign main_litedramcore_bankmachine5_source_ready = main_litedramcore_bankmachine5_sink_sink_ready;
+assign main_litedramcore_bankmachine5_sink_sink_first = main_litedramcore_bankmachine5_source_first;
+assign main_litedramcore_bankmachine5_sink_sink_last = main_litedramcore_bankmachine5_source_last;
+assign main_litedramcore_bankmachine5_sink_sink_payload_we = main_litedramcore_bankmachine5_source_payload_we;
+assign main_litedramcore_bankmachine5_sink_sink_payload_addr = main_litedramcore_bankmachine5_source_payload_addr;
+assign main_litedramcore_bankmachine5_source_source_ready = (main_litedramcore_bankmachine5_req_wdata_ready | main_litedramcore_bankmachine5_req_rdata_valid);
+assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_source_valid | main_litedramcore_bankmachine5_source_source_valid);
+assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_source_source_payload_addr[22:7]);
+assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
+always @(*) begin
+    main_litedramcore_bankmachine5_cmd_payload_a <= 16'd0;
+    if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine5_cmd_payload_a <= main_litedramcore_bankmachine5_source_source_payload_addr[22:7];
+    end else begin
+        main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write);
+assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
+assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine5_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine5_source_valid & main_litedramcore_bankmachine5_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine5_source_payload_addr[22:7] != main_litedramcore_bankmachine5_source_source_payload_addr[22:7])) begin
+            main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine5_syncfifo5_din = {main_litedramcore_bankmachine5_fifo_in_last, main_litedramcore_bankmachine5_fifo_in_first, main_litedramcore_bankmachine5_fifo_in_payload_addr, main_litedramcore_bankmachine5_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout;
+assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout;
+assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout;
+assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout;
+assign main_litedramcore_bankmachine5_sink_ready = main_litedramcore_bankmachine5_syncfifo5_writable;
+assign main_litedramcore_bankmachine5_syncfifo5_we = main_litedramcore_bankmachine5_sink_valid;
+assign main_litedramcore_bankmachine5_fifo_in_first = main_litedramcore_bankmachine5_sink_first;
+assign main_litedramcore_bankmachine5_fifo_in_last = main_litedramcore_bankmachine5_sink_last;
+assign main_litedramcore_bankmachine5_fifo_in_payload_we = main_litedramcore_bankmachine5_sink_payload_we;
+assign main_litedramcore_bankmachine5_fifo_in_payload_addr = main_litedramcore_bankmachine5_sink_payload_addr;
+assign main_litedramcore_bankmachine5_source_valid = main_litedramcore_bankmachine5_syncfifo5_readable;
+assign main_litedramcore_bankmachine5_source_first = main_litedramcore_bankmachine5_fifo_out_first;
+assign main_litedramcore_bankmachine5_source_last = main_litedramcore_bankmachine5_fifo_out_last;
+assign main_litedramcore_bankmachine5_source_payload_we = main_litedramcore_bankmachine5_fifo_out_payload_we;
+assign main_litedramcore_bankmachine5_source_payload_addr = main_litedramcore_bankmachine5_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine5_syncfifo5_re = main_litedramcore_bankmachine5_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine5_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine5_replace) begin
+        main_litedramcore_bankmachine5_wrport_adr <= (main_litedramcore_bankmachine5_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine5_wrport_adr <= main_litedramcore_bankmachine5_produce;
+    end
+end
+assign main_litedramcore_bankmachine5_wrport_dat_w = main_litedramcore_bankmachine5_syncfifo5_din;
+assign main_litedramcore_bankmachine5_wrport_we = (main_litedramcore_bankmachine5_syncfifo5_we & (main_litedramcore_bankmachine5_syncfifo5_writable | main_litedramcore_bankmachine5_replace));
+assign main_litedramcore_bankmachine5_do_read = (main_litedramcore_bankmachine5_syncfifo5_readable & main_litedramcore_bankmachine5_syncfifo5_re);
+assign main_litedramcore_bankmachine5_rdport_adr = main_litedramcore_bankmachine5_consume;
+assign main_litedramcore_bankmachine5_syncfifo5_dout = main_litedramcore_bankmachine5_rdport_dat_r;
+assign main_litedramcore_bankmachine5_syncfifo5_writable = (main_litedramcore_bankmachine5_level != 5'd16);
+assign main_litedramcore_bankmachine5_syncfifo5_readable = (main_litedramcore_bankmachine5_level != 1'd0);
+assign main_litedramcore_bankmachine5_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine5_pipe_valid_source_valid) | main_litedramcore_bankmachine5_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine5_pipe_valid_sink_valid = main_litedramcore_bankmachine5_sink_sink_valid;
+assign main_litedramcore_bankmachine5_sink_sink_ready = main_litedramcore_bankmachine5_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine5_pipe_valid_sink_first = main_litedramcore_bankmachine5_sink_sink_first;
+assign main_litedramcore_bankmachine5_pipe_valid_sink_last = main_litedramcore_bankmachine5_sink_sink_last;
+assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_we = main_litedramcore_bankmachine5_sink_sink_payload_we;
+assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine5_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine5_source_source_valid = main_litedramcore_bankmachine5_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine5_pipe_valid_source_ready = main_litedramcore_bankmachine5_source_source_ready;
+assign main_litedramcore_bankmachine5_source_source_first = main_litedramcore_bankmachine5_pipe_valid_source_first;
+assign main_litedramcore_bankmachine5_source_source_last = main_litedramcore_bankmachine5_pipe_valid_source_last;
+assign main_litedramcore_bankmachine5_source_source_payload_we = main_litedramcore_bankmachine5_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine5_source_source_payload_addr = main_litedramcore_bankmachine5_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine5_next_state <= 4'd0;
+    builder_bankmachine5_next_state <= builder_bankmachine5_state;
+    case (builder_bankmachine5_state)
         1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                if (main_litedramcore_bankmachine5_cmd_ready) begin
+                    builder_bankmachine5_next_state <= 3'd5;
+                end
             end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                builder_bankmachine5_next_state <= 3'd5;
+            end
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                if (main_litedramcore_bankmachine5_cmd_ready) begin
+                    builder_bankmachine5_next_state <= 3'd7;
+                end
+            end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine5_refresh_req)) begin
+                builder_bankmachine5_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine5_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine5_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine5_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine5_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
+                builder_bankmachine5_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
-                                litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
-                            end else begin
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin
+                                builder_bankmachine5_next_state <= 2'd2;
                             end
                         end else begin
+                            builder_bankmachine5_next_state <= 1'd1;
                         end
                     end else begin
+                        builder_bankmachine5_next_state <= 2'd3;
                     end
                 end
             end
@@ -7574,22 +8163,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         3'd4: begin
-            litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -7600,142 +8182,56 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
+                                main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
-assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid;
-assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready;
-assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we;
-assign litedramcore_bankmachine5_sink_payload_addr = litedramcore_bankmachine5_req_addr;
-assign litedramcore_bankmachine5_sink_sink_valid = litedramcore_bankmachine5_source_valid;
-assign litedramcore_bankmachine5_source_ready = litedramcore_bankmachine5_sink_sink_ready;
-assign litedramcore_bankmachine5_sink_sink_first = litedramcore_bankmachine5_source_first;
-assign litedramcore_bankmachine5_sink_sink_last = litedramcore_bankmachine5_source_last;
-assign litedramcore_bankmachine5_sink_sink_payload_we = litedramcore_bankmachine5_source_payload_we;
-assign litedramcore_bankmachine5_sink_sink_payload_addr = litedramcore_bankmachine5_source_payload_addr;
-assign litedramcore_bankmachine5_source_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
-assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_source_valid | litedramcore_bankmachine5_source_source_valid);
-assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_source_source_payload_addr[22:7]);
-assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
-always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_a <= 16'd0;
-    if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
-        litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_source_source_payload_addr[22:7];
-    end else begin
-        litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
-assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
-assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
-always @(*) begin
-    litedramcore_bankmachine5_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine5_source_valid & litedramcore_bankmachine5_source_source_valid)) begin
-        if ((litedramcore_bankmachine5_source_payload_addr[22:7] != litedramcore_bankmachine5_source_source_payload_addr[22:7])) begin
-            litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine5_syncfifo5_din = {litedramcore_bankmachine5_fifo_in_last, litedramcore_bankmachine5_fifo_in_first, litedramcore_bankmachine5_fifo_in_payload_addr, litedramcore_bankmachine5_fifo_in_payload_we};
-assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
-assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
-assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
-assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
-assign litedramcore_bankmachine5_sink_ready = litedramcore_bankmachine5_syncfifo5_writable;
-assign litedramcore_bankmachine5_syncfifo5_we = litedramcore_bankmachine5_sink_valid;
-assign litedramcore_bankmachine5_fifo_in_first = litedramcore_bankmachine5_sink_first;
-assign litedramcore_bankmachine5_fifo_in_last = litedramcore_bankmachine5_sink_last;
-assign litedramcore_bankmachine5_fifo_in_payload_we = litedramcore_bankmachine5_sink_payload_we;
-assign litedramcore_bankmachine5_fifo_in_payload_addr = litedramcore_bankmachine5_sink_payload_addr;
-assign litedramcore_bankmachine5_source_valid = litedramcore_bankmachine5_syncfifo5_readable;
-assign litedramcore_bankmachine5_source_first = litedramcore_bankmachine5_fifo_out_first;
-assign litedramcore_bankmachine5_source_last = litedramcore_bankmachine5_fifo_out_last;
-assign litedramcore_bankmachine5_source_payload_we = litedramcore_bankmachine5_fifo_out_payload_we;
-assign litedramcore_bankmachine5_source_payload_addr = litedramcore_bankmachine5_fifo_out_payload_addr;
-assign litedramcore_bankmachine5_syncfifo5_re = litedramcore_bankmachine5_source_ready;
-always @(*) begin
-    litedramcore_bankmachine5_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine5_replace) begin
-        litedramcore_bankmachine5_wrport_adr <= (litedramcore_bankmachine5_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine5_wrport_adr <= litedramcore_bankmachine5_produce;
-    end
-end
-assign litedramcore_bankmachine5_wrport_dat_w = litedramcore_bankmachine5_syncfifo5_din;
-assign litedramcore_bankmachine5_wrport_we = (litedramcore_bankmachine5_syncfifo5_we & (litedramcore_bankmachine5_syncfifo5_writable | litedramcore_bankmachine5_replace));
-assign litedramcore_bankmachine5_do_read = (litedramcore_bankmachine5_syncfifo5_readable & litedramcore_bankmachine5_syncfifo5_re);
-assign litedramcore_bankmachine5_rdport_adr = litedramcore_bankmachine5_consume;
-assign litedramcore_bankmachine5_syncfifo5_dout = litedramcore_bankmachine5_rdport_dat_r;
-assign litedramcore_bankmachine5_syncfifo5_writable = (litedramcore_bankmachine5_level != 5'd16);
-assign litedramcore_bankmachine5_syncfifo5_readable = (litedramcore_bankmachine5_level != 1'd0);
-assign litedramcore_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready);
-assign litedramcore_bankmachine5_pipe_valid_sink_valid = litedramcore_bankmachine5_sink_sink_valid;
-assign litedramcore_bankmachine5_sink_sink_ready = litedramcore_bankmachine5_pipe_valid_sink_ready;
-assign litedramcore_bankmachine5_pipe_valid_sink_first = litedramcore_bankmachine5_sink_sink_first;
-assign litedramcore_bankmachine5_pipe_valid_sink_last = litedramcore_bankmachine5_sink_sink_last;
-assign litedramcore_bankmachine5_pipe_valid_sink_payload_we = litedramcore_bankmachine5_sink_sink_payload_we;
-assign litedramcore_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_bankmachine5_sink_sink_payload_addr;
-assign litedramcore_bankmachine5_source_source_valid = litedramcore_bankmachine5_pipe_valid_source_valid;
-assign litedramcore_bankmachine5_pipe_valid_source_ready = litedramcore_bankmachine5_source_source_ready;
-assign litedramcore_bankmachine5_source_source_first = litedramcore_bankmachine5_pipe_valid_source_first;
-assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_pipe_valid_source_last;
-assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine5_next_state <= 4'd0;
-    litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
-    case (litedramcore_bankmachine5_state)
+always @(*) begin
+    main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                if (litedramcore_bankmachine5_cmd_ready) begin
-                    litedramcore_bankmachine5_next_state <= 3'd5;
-                end
-            end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                if (litedramcore_bankmachine5_cmd_ready) begin
-                    litedramcore_bankmachine5_next_state <= 3'd7;
-                end
-            end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine5_refresh_req)) begin
-                litedramcore_bankmachine5_next_state <= 1'd0;
-            end
         end
         3'd5: begin
-            litedramcore_bankmachine5_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine5_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine5_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine5_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
-                litedramcore_bankmachine5_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
-                                litedramcore_bankmachine5_next_state <= 2'd2;
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
+                            end else begin
+                                main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
                             end
                         end else begin
-                            litedramcore_bankmachine5_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine5_next_state <= 2'd3;
                     end
                 end
             end
@@ -7743,8 +8239,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7752,8 +8248,8 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine5_twtpcon_ready) begin
-                litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+            if (main_litedramcore_bankmachine5_twtpcon_ready) begin
+                main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
             end
         end
         3'd5: begin
@@ -7769,15 +8265,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_row_open <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_row_open <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -7795,18 +8291,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_valid <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -7820,12 +8316,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            litedramcore_bankmachine5_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -7836,18 +8332,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_row_close <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_row_close <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
-            litedramcore_bankmachine5_row_close <= 1'd1;
+            main_litedramcore_bankmachine5_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine5_row_close <= 1'd1;
+            main_litedramcore_bankmachine5_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine5_row_close <= 1'd1;
+            main_litedramcore_bankmachine5_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -7862,15 +8358,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -7888,8 +8384,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7907,12 +8403,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -7923,18 +8419,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -7952,11 +8448,11 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
@@ -7974,13 +8470,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
-                                litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
+                                main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -7993,22 +8489,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -8023,8 +8519,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8042,14 +8538,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -8061,8 +8557,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8080,13 +8576,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
-                                litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
+                                main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -8098,38 +8594,139 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+assign main_litedramcore_bankmachine6_sink_valid = main_litedramcore_bankmachine6_req_valid;
+assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_sink_ready;
+assign main_litedramcore_bankmachine6_sink_payload_we = main_litedramcore_bankmachine6_req_we;
+assign main_litedramcore_bankmachine6_sink_payload_addr = main_litedramcore_bankmachine6_req_addr;
+assign main_litedramcore_bankmachine6_sink_sink_valid = main_litedramcore_bankmachine6_source_valid;
+assign main_litedramcore_bankmachine6_source_ready = main_litedramcore_bankmachine6_sink_sink_ready;
+assign main_litedramcore_bankmachine6_sink_sink_first = main_litedramcore_bankmachine6_source_first;
+assign main_litedramcore_bankmachine6_sink_sink_last = main_litedramcore_bankmachine6_source_last;
+assign main_litedramcore_bankmachine6_sink_sink_payload_we = main_litedramcore_bankmachine6_source_payload_we;
+assign main_litedramcore_bankmachine6_sink_sink_payload_addr = main_litedramcore_bankmachine6_source_payload_addr;
+assign main_litedramcore_bankmachine6_source_source_ready = (main_litedramcore_bankmachine6_req_wdata_ready | main_litedramcore_bankmachine6_req_rdata_valid);
+assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_source_valid | main_litedramcore_bankmachine6_source_source_valid);
+assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_source_source_payload_addr[22:7]);
+assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
+always @(*) begin
+    main_litedramcore_bankmachine6_cmd_payload_a <= 16'd0;
+    if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine6_cmd_payload_a <= main_litedramcore_bankmachine6_source_source_payload_addr[22:7];
+    end else begin
+        main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write);
+assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
+assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine6_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine6_source_valid & main_litedramcore_bankmachine6_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine6_source_payload_addr[22:7] != main_litedramcore_bankmachine6_source_source_payload_addr[22:7])) begin
+            main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine6_syncfifo6_din = {main_litedramcore_bankmachine6_fifo_in_last, main_litedramcore_bankmachine6_fifo_in_first, main_litedramcore_bankmachine6_fifo_in_payload_addr, main_litedramcore_bankmachine6_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout;
+assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout;
+assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout;
+assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout;
+assign main_litedramcore_bankmachine6_sink_ready = main_litedramcore_bankmachine6_syncfifo6_writable;
+assign main_litedramcore_bankmachine6_syncfifo6_we = main_litedramcore_bankmachine6_sink_valid;
+assign main_litedramcore_bankmachine6_fifo_in_first = main_litedramcore_bankmachine6_sink_first;
+assign main_litedramcore_bankmachine6_fifo_in_last = main_litedramcore_bankmachine6_sink_last;
+assign main_litedramcore_bankmachine6_fifo_in_payload_we = main_litedramcore_bankmachine6_sink_payload_we;
+assign main_litedramcore_bankmachine6_fifo_in_payload_addr = main_litedramcore_bankmachine6_sink_payload_addr;
+assign main_litedramcore_bankmachine6_source_valid = main_litedramcore_bankmachine6_syncfifo6_readable;
+assign main_litedramcore_bankmachine6_source_first = main_litedramcore_bankmachine6_fifo_out_first;
+assign main_litedramcore_bankmachine6_source_last = main_litedramcore_bankmachine6_fifo_out_last;
+assign main_litedramcore_bankmachine6_source_payload_we = main_litedramcore_bankmachine6_fifo_out_payload_we;
+assign main_litedramcore_bankmachine6_source_payload_addr = main_litedramcore_bankmachine6_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine6_syncfifo6_re = main_litedramcore_bankmachine6_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine6_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine6_replace) begin
+        main_litedramcore_bankmachine6_wrport_adr <= (main_litedramcore_bankmachine6_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine6_wrport_adr <= main_litedramcore_bankmachine6_produce;
+    end
+end
+assign main_litedramcore_bankmachine6_wrport_dat_w = main_litedramcore_bankmachine6_syncfifo6_din;
+assign main_litedramcore_bankmachine6_wrport_we = (main_litedramcore_bankmachine6_syncfifo6_we & (main_litedramcore_bankmachine6_syncfifo6_writable | main_litedramcore_bankmachine6_replace));
+assign main_litedramcore_bankmachine6_do_read = (main_litedramcore_bankmachine6_syncfifo6_readable & main_litedramcore_bankmachine6_syncfifo6_re);
+assign main_litedramcore_bankmachine6_rdport_adr = main_litedramcore_bankmachine6_consume;
+assign main_litedramcore_bankmachine6_syncfifo6_dout = main_litedramcore_bankmachine6_rdport_dat_r;
+assign main_litedramcore_bankmachine6_syncfifo6_writable = (main_litedramcore_bankmachine6_level != 5'd16);
+assign main_litedramcore_bankmachine6_syncfifo6_readable = (main_litedramcore_bankmachine6_level != 1'd0);
+assign main_litedramcore_bankmachine6_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine6_pipe_valid_source_valid) | main_litedramcore_bankmachine6_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine6_pipe_valid_sink_valid = main_litedramcore_bankmachine6_sink_sink_valid;
+assign main_litedramcore_bankmachine6_sink_sink_ready = main_litedramcore_bankmachine6_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine6_pipe_valid_sink_first = main_litedramcore_bankmachine6_sink_sink_first;
+assign main_litedramcore_bankmachine6_pipe_valid_sink_last = main_litedramcore_bankmachine6_sink_sink_last;
+assign main_litedramcore_bankmachine6_pipe_valid_sink_payload_we = main_litedramcore_bankmachine6_sink_sink_payload_we;
+assign main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine6_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine6_source_source_valid = main_litedramcore_bankmachine6_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine6_pipe_valid_source_ready = main_litedramcore_bankmachine6_source_source_ready;
+assign main_litedramcore_bankmachine6_source_source_first = main_litedramcore_bankmachine6_pipe_valid_source_first;
+assign main_litedramcore_bankmachine6_source_source_last = main_litedramcore_bankmachine6_pipe_valid_source_last;
+assign main_litedramcore_bankmachine6_source_source_payload_we = main_litedramcore_bankmachine6_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine6_source_source_payload_addr = main_litedramcore_bankmachine6_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine6_next_state <= 4'd0;
+    builder_bankmachine6_next_state <= builder_bankmachine6_state;
+    case (builder_bankmachine6_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                if (main_litedramcore_bankmachine6_cmd_ready) begin
+                    builder_bankmachine6_next_state <= 3'd5;
+                end
+            end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                builder_bankmachine6_next_state <= 3'd5;
+            end
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                if (main_litedramcore_bankmachine6_cmd_ready) begin
+                    builder_bankmachine6_next_state <= 3'd7;
+                end
+            end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine6_refresh_req)) begin
+                builder_bankmachine6_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine6_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine6_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine6_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine6_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
+                builder_bankmachine6_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
-                                litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
-                            end else begin
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if ((main_litedramcore_bankmachine6_cmd_ready & main_litedramcore_bankmachine6_auto_precharge)) begin
+                                builder_bankmachine6_next_state <= 2'd2;
                             end
                         end else begin
+                            builder_bankmachine6_next_state <= 1'd1;
                         end
                     end else begin
+                        builder_bankmachine6_next_state <= 2'd3;
                     end
                 end
             end
@@ -8137,13 +8734,16 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine6_row_open <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_row_open <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -8156,157 +8756,44 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
-assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid;
-assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready;
-assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we;
-assign litedramcore_bankmachine6_sink_payload_addr = litedramcore_bankmachine6_req_addr;
-assign litedramcore_bankmachine6_sink_sink_valid = litedramcore_bankmachine6_source_valid;
-assign litedramcore_bankmachine6_source_ready = litedramcore_bankmachine6_sink_sink_ready;
-assign litedramcore_bankmachine6_sink_sink_first = litedramcore_bankmachine6_source_first;
-assign litedramcore_bankmachine6_sink_sink_last = litedramcore_bankmachine6_source_last;
-assign litedramcore_bankmachine6_sink_sink_payload_we = litedramcore_bankmachine6_source_payload_we;
-assign litedramcore_bankmachine6_sink_sink_payload_addr = litedramcore_bankmachine6_source_payload_addr;
-assign litedramcore_bankmachine6_source_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
-assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_source_valid | litedramcore_bankmachine6_source_source_valid);
-assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_source_source_payload_addr[22:7]);
-assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
-always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_a <= 16'd0;
-    if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
-        litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_source_source_payload_addr[22:7];
-    end else begin
-        litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
-assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
-assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
-always @(*) begin
-    litedramcore_bankmachine6_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine6_source_valid & litedramcore_bankmachine6_source_source_valid)) begin
-        if ((litedramcore_bankmachine6_source_payload_addr[22:7] != litedramcore_bankmachine6_source_source_payload_addr[22:7])) begin
-            litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine6_syncfifo6_din = {litedramcore_bankmachine6_fifo_in_last, litedramcore_bankmachine6_fifo_in_first, litedramcore_bankmachine6_fifo_in_payload_addr, litedramcore_bankmachine6_fifo_in_payload_we};
-assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
-assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
-assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
-assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
-assign litedramcore_bankmachine6_sink_ready = litedramcore_bankmachine6_syncfifo6_writable;
-assign litedramcore_bankmachine6_syncfifo6_we = litedramcore_bankmachine6_sink_valid;
-assign litedramcore_bankmachine6_fifo_in_first = litedramcore_bankmachine6_sink_first;
-assign litedramcore_bankmachine6_fifo_in_last = litedramcore_bankmachine6_sink_last;
-assign litedramcore_bankmachine6_fifo_in_payload_we = litedramcore_bankmachine6_sink_payload_we;
-assign litedramcore_bankmachine6_fifo_in_payload_addr = litedramcore_bankmachine6_sink_payload_addr;
-assign litedramcore_bankmachine6_source_valid = litedramcore_bankmachine6_syncfifo6_readable;
-assign litedramcore_bankmachine6_source_first = litedramcore_bankmachine6_fifo_out_first;
-assign litedramcore_bankmachine6_source_last = litedramcore_bankmachine6_fifo_out_last;
-assign litedramcore_bankmachine6_source_payload_we = litedramcore_bankmachine6_fifo_out_payload_we;
-assign litedramcore_bankmachine6_source_payload_addr = litedramcore_bankmachine6_fifo_out_payload_addr;
-assign litedramcore_bankmachine6_syncfifo6_re = litedramcore_bankmachine6_source_ready;
-always @(*) begin
-    litedramcore_bankmachine6_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine6_replace) begin
-        litedramcore_bankmachine6_wrport_adr <= (litedramcore_bankmachine6_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine6_wrport_adr <= litedramcore_bankmachine6_produce;
-    end
-end
-assign litedramcore_bankmachine6_wrport_dat_w = litedramcore_bankmachine6_syncfifo6_din;
-assign litedramcore_bankmachine6_wrport_we = (litedramcore_bankmachine6_syncfifo6_we & (litedramcore_bankmachine6_syncfifo6_writable | litedramcore_bankmachine6_replace));
-assign litedramcore_bankmachine6_do_read = (litedramcore_bankmachine6_syncfifo6_readable & litedramcore_bankmachine6_syncfifo6_re);
-assign litedramcore_bankmachine6_rdport_adr = litedramcore_bankmachine6_consume;
-assign litedramcore_bankmachine6_syncfifo6_dout = litedramcore_bankmachine6_rdport_dat_r;
-assign litedramcore_bankmachine6_syncfifo6_writable = (litedramcore_bankmachine6_level != 5'd16);
-assign litedramcore_bankmachine6_syncfifo6_readable = (litedramcore_bankmachine6_level != 1'd0);
-assign litedramcore_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready);
-assign litedramcore_bankmachine6_pipe_valid_sink_valid = litedramcore_bankmachine6_sink_sink_valid;
-assign litedramcore_bankmachine6_sink_sink_ready = litedramcore_bankmachine6_pipe_valid_sink_ready;
-assign litedramcore_bankmachine6_pipe_valid_sink_first = litedramcore_bankmachine6_sink_sink_first;
-assign litedramcore_bankmachine6_pipe_valid_sink_last = litedramcore_bankmachine6_sink_sink_last;
-assign litedramcore_bankmachine6_pipe_valid_sink_payload_we = litedramcore_bankmachine6_sink_sink_payload_we;
-assign litedramcore_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_bankmachine6_sink_sink_payload_addr;
-assign litedramcore_bankmachine6_source_source_valid = litedramcore_bankmachine6_pipe_valid_source_valid;
-assign litedramcore_bankmachine6_pipe_valid_source_ready = litedramcore_bankmachine6_source_source_ready;
-assign litedramcore_bankmachine6_source_source_first = litedramcore_bankmachine6_pipe_valid_source_first;
-assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_pipe_valid_source_last;
-assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine6_next_state <= 4'd0;
-    litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
-    case (litedramcore_bankmachine6_state)
+always @(*) begin
+    main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                if (litedramcore_bankmachine6_cmd_ready) begin
-                    litedramcore_bankmachine6_next_state <= 3'd5;
-                end
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                if (litedramcore_bankmachine6_cmd_ready) begin
-                    litedramcore_bankmachine6_next_state <= 3'd7;
-                end
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine6_refresh_req)) begin
-                litedramcore_bankmachine6_next_state <= 1'd0;
-            end
         end
         3'd5: begin
-            litedramcore_bankmachine6_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine6_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine6_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine6_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
-                litedramcore_bankmachine6_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
-                                litedramcore_bankmachine6_next_state <= 2'd2;
-                            end
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
                         end else begin
-                            litedramcore_bankmachine6_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine6_next_state <= 2'd3;
                     end
                 end
             end
@@ -8314,15 +8801,41 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_row_close <= 1'd0;
+    case (builder_bankmachine6_state)
+        1'd1: begin
+            main_litedramcore_bankmachine6_row_close <= 1'd1;
+        end
+        2'd2: begin
+            main_litedramcore_bankmachine6_row_close <= 1'd1;
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            main_litedramcore_bankmachine6_row_close <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -8340,8 +8853,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8359,12 +8872,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -8375,18 +8888,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -8404,11 +8917,11 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
@@ -8426,13 +8939,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
-                                litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
+                                main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -8445,22 +8958,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -8475,8 +8988,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8494,14 +9007,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -8513,8 +9026,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8532,13 +9045,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
-                                litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
+                                main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -8551,8 +9064,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8570,13 +9083,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
-                                litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
+                                main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -8589,8 +9102,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8608,14 +9121,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
+                                main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
                             end
                         end else begin
                         end
@@ -8627,8 +9140,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8636,36 +9149,10 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine6_twtpcon_ready) begin
-                litedramcore_bankmachine6_refresh_gnt <= 1'd1;
-            end
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine6_row_open <= 1'd0;
-    case (litedramcore_bankmachine6_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine6_twtpcon_ready) begin
+                main_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
             end
         end
-        3'd4: begin
-        end
         3'd5: begin
         end
         3'd6: begin
@@ -8678,41 +9165,139 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine6_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+assign main_litedramcore_bankmachine7_sink_valid = main_litedramcore_bankmachine7_req_valid;
+assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_sink_ready;
+assign main_litedramcore_bankmachine7_sink_payload_we = main_litedramcore_bankmachine7_req_we;
+assign main_litedramcore_bankmachine7_sink_payload_addr = main_litedramcore_bankmachine7_req_addr;
+assign main_litedramcore_bankmachine7_sink_sink_valid = main_litedramcore_bankmachine7_source_valid;
+assign main_litedramcore_bankmachine7_source_ready = main_litedramcore_bankmachine7_sink_sink_ready;
+assign main_litedramcore_bankmachine7_sink_sink_first = main_litedramcore_bankmachine7_source_first;
+assign main_litedramcore_bankmachine7_sink_sink_last = main_litedramcore_bankmachine7_source_last;
+assign main_litedramcore_bankmachine7_sink_sink_payload_we = main_litedramcore_bankmachine7_source_payload_we;
+assign main_litedramcore_bankmachine7_sink_sink_payload_addr = main_litedramcore_bankmachine7_source_payload_addr;
+assign main_litedramcore_bankmachine7_source_source_ready = (main_litedramcore_bankmachine7_req_wdata_ready | main_litedramcore_bankmachine7_req_rdata_valid);
+assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_source_valid | main_litedramcore_bankmachine7_source_source_valid);
+assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_source_source_payload_addr[22:7]);
+assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
+always @(*) begin
+    main_litedramcore_bankmachine7_cmd_payload_a <= 16'd0;
+    if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine7_cmd_payload_a <= main_litedramcore_bankmachine7_source_source_payload_addr[22:7];
+    end else begin
+        main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write);
+assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
+assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine7_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine7_source_valid & main_litedramcore_bankmachine7_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine7_source_payload_addr[22:7] != main_litedramcore_bankmachine7_source_source_payload_addr[22:7])) begin
+            main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine7_syncfifo7_din = {main_litedramcore_bankmachine7_fifo_in_last, main_litedramcore_bankmachine7_fifo_in_first, main_litedramcore_bankmachine7_fifo_in_payload_addr, main_litedramcore_bankmachine7_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout;
+assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout;
+assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout;
+assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout;
+assign main_litedramcore_bankmachine7_sink_ready = main_litedramcore_bankmachine7_syncfifo7_writable;
+assign main_litedramcore_bankmachine7_syncfifo7_we = main_litedramcore_bankmachine7_sink_valid;
+assign main_litedramcore_bankmachine7_fifo_in_first = main_litedramcore_bankmachine7_sink_first;
+assign main_litedramcore_bankmachine7_fifo_in_last = main_litedramcore_bankmachine7_sink_last;
+assign main_litedramcore_bankmachine7_fifo_in_payload_we = main_litedramcore_bankmachine7_sink_payload_we;
+assign main_litedramcore_bankmachine7_fifo_in_payload_addr = main_litedramcore_bankmachine7_sink_payload_addr;
+assign main_litedramcore_bankmachine7_source_valid = main_litedramcore_bankmachine7_syncfifo7_readable;
+assign main_litedramcore_bankmachine7_source_first = main_litedramcore_bankmachine7_fifo_out_first;
+assign main_litedramcore_bankmachine7_source_last = main_litedramcore_bankmachine7_fifo_out_last;
+assign main_litedramcore_bankmachine7_source_payload_we = main_litedramcore_bankmachine7_fifo_out_payload_we;
+assign main_litedramcore_bankmachine7_source_payload_addr = main_litedramcore_bankmachine7_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine7_syncfifo7_re = main_litedramcore_bankmachine7_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine7_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine7_replace) begin
+        main_litedramcore_bankmachine7_wrport_adr <= (main_litedramcore_bankmachine7_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine7_wrport_adr <= main_litedramcore_bankmachine7_produce;
+    end
+end
+assign main_litedramcore_bankmachine7_wrport_dat_w = main_litedramcore_bankmachine7_syncfifo7_din;
+assign main_litedramcore_bankmachine7_wrport_we = (main_litedramcore_bankmachine7_syncfifo7_we & (main_litedramcore_bankmachine7_syncfifo7_writable | main_litedramcore_bankmachine7_replace));
+assign main_litedramcore_bankmachine7_do_read = (main_litedramcore_bankmachine7_syncfifo7_readable & main_litedramcore_bankmachine7_syncfifo7_re);
+assign main_litedramcore_bankmachine7_rdport_adr = main_litedramcore_bankmachine7_consume;
+assign main_litedramcore_bankmachine7_syncfifo7_dout = main_litedramcore_bankmachine7_rdport_dat_r;
+assign main_litedramcore_bankmachine7_syncfifo7_writable = (main_litedramcore_bankmachine7_level != 5'd16);
+assign main_litedramcore_bankmachine7_syncfifo7_readable = (main_litedramcore_bankmachine7_level != 1'd0);
+assign main_litedramcore_bankmachine7_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine7_pipe_valid_source_valid) | main_litedramcore_bankmachine7_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine7_pipe_valid_sink_valid = main_litedramcore_bankmachine7_sink_sink_valid;
+assign main_litedramcore_bankmachine7_sink_sink_ready = main_litedramcore_bankmachine7_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine7_pipe_valid_sink_first = main_litedramcore_bankmachine7_sink_sink_first;
+assign main_litedramcore_bankmachine7_pipe_valid_sink_last = main_litedramcore_bankmachine7_sink_sink_last;
+assign main_litedramcore_bankmachine7_pipe_valid_sink_payload_we = main_litedramcore_bankmachine7_sink_sink_payload_we;
+assign main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine7_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine7_source_source_valid = main_litedramcore_bankmachine7_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine7_pipe_valid_source_ready = main_litedramcore_bankmachine7_source_source_ready;
+assign main_litedramcore_bankmachine7_source_source_first = main_litedramcore_bankmachine7_pipe_valid_source_first;
+assign main_litedramcore_bankmachine7_source_source_last = main_litedramcore_bankmachine7_pipe_valid_source_last;
+assign main_litedramcore_bankmachine7_source_source_payload_we = main_litedramcore_bankmachine7_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine7_source_source_payload_addr = main_litedramcore_bankmachine7_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine7_next_state <= 4'd0;
+    builder_bankmachine7_next_state <= builder_bankmachine7_state;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                if (main_litedramcore_bankmachine7_cmd_ready) begin
+                    builder_bankmachine7_next_state <= 3'd5;
+                end
             end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                builder_bankmachine7_next_state <= 3'd5;
+            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                if (main_litedramcore_bankmachine7_cmd_ready) begin
+                    builder_bankmachine7_next_state <= 3'd7;
+                end
             end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine7_refresh_req)) begin
+                builder_bankmachine7_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine7_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine7_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine7_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine7_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
+                builder_bankmachine7_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            litedramcore_bankmachine6_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if ((main_litedramcore_bankmachine7_cmd_ready & main_litedramcore_bankmachine7_auto_precharge)) begin
+                                builder_bankmachine7_next_state <= 2'd2;
+                            end
                         end else begin
+                            builder_bankmachine7_next_state <= 1'd1;
                         end
                     end else begin
+                        builder_bankmachine7_next_state <= 2'd3;
                     end
                 end
             end
@@ -8720,173 +9305,34 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_row_close <= 1'd0;
-    case (litedramcore_bankmachine6_state)
-        1'd1: begin
-            litedramcore_bankmachine6_row_close <= 1'd1;
-        end
-        2'd2: begin
-            litedramcore_bankmachine6_row_close <= 1'd1;
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            litedramcore_bankmachine6_row_close <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid;
-assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready;
-assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we;
-assign litedramcore_bankmachine7_sink_payload_addr = litedramcore_bankmachine7_req_addr;
-assign litedramcore_bankmachine7_sink_sink_valid = litedramcore_bankmachine7_source_valid;
-assign litedramcore_bankmachine7_source_ready = litedramcore_bankmachine7_sink_sink_ready;
-assign litedramcore_bankmachine7_sink_sink_first = litedramcore_bankmachine7_source_first;
-assign litedramcore_bankmachine7_sink_sink_last = litedramcore_bankmachine7_source_last;
-assign litedramcore_bankmachine7_sink_sink_payload_we = litedramcore_bankmachine7_source_payload_we;
-assign litedramcore_bankmachine7_sink_sink_payload_addr = litedramcore_bankmachine7_source_payload_addr;
-assign litedramcore_bankmachine7_source_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
-assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_source_valid | litedramcore_bankmachine7_source_source_valid);
-assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_source_source_payload_addr[22:7]);
-assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
-always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_a <= 16'd0;
-    if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
-        litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_source_source_payload_addr[22:7];
-    end else begin
-        litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
-assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
-assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
-always @(*) begin
-    litedramcore_bankmachine7_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine7_source_valid & litedramcore_bankmachine7_source_source_valid)) begin
-        if ((litedramcore_bankmachine7_source_payload_addr[22:7] != litedramcore_bankmachine7_source_source_payload_addr[22:7])) begin
-            litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine7_syncfifo7_din = {litedramcore_bankmachine7_fifo_in_last, litedramcore_bankmachine7_fifo_in_first, litedramcore_bankmachine7_fifo_in_payload_addr, litedramcore_bankmachine7_fifo_in_payload_we};
-assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
-assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
-assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
-assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
-assign litedramcore_bankmachine7_sink_ready = litedramcore_bankmachine7_syncfifo7_writable;
-assign litedramcore_bankmachine7_syncfifo7_we = litedramcore_bankmachine7_sink_valid;
-assign litedramcore_bankmachine7_fifo_in_first = litedramcore_bankmachine7_sink_first;
-assign litedramcore_bankmachine7_fifo_in_last = litedramcore_bankmachine7_sink_last;
-assign litedramcore_bankmachine7_fifo_in_payload_we = litedramcore_bankmachine7_sink_payload_we;
-assign litedramcore_bankmachine7_fifo_in_payload_addr = litedramcore_bankmachine7_sink_payload_addr;
-assign litedramcore_bankmachine7_source_valid = litedramcore_bankmachine7_syncfifo7_readable;
-assign litedramcore_bankmachine7_source_first = litedramcore_bankmachine7_fifo_out_first;
-assign litedramcore_bankmachine7_source_last = litedramcore_bankmachine7_fifo_out_last;
-assign litedramcore_bankmachine7_source_payload_we = litedramcore_bankmachine7_fifo_out_payload_we;
-assign litedramcore_bankmachine7_source_payload_addr = litedramcore_bankmachine7_fifo_out_payload_addr;
-assign litedramcore_bankmachine7_syncfifo7_re = litedramcore_bankmachine7_source_ready;
-always @(*) begin
-    litedramcore_bankmachine7_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine7_replace) begin
-        litedramcore_bankmachine7_wrport_adr <= (litedramcore_bankmachine7_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine7_wrport_adr <= litedramcore_bankmachine7_produce;
-    end
-end
-assign litedramcore_bankmachine7_wrport_dat_w = litedramcore_bankmachine7_syncfifo7_din;
-assign litedramcore_bankmachine7_wrport_we = (litedramcore_bankmachine7_syncfifo7_we & (litedramcore_bankmachine7_syncfifo7_writable | litedramcore_bankmachine7_replace));
-assign litedramcore_bankmachine7_do_read = (litedramcore_bankmachine7_syncfifo7_readable & litedramcore_bankmachine7_syncfifo7_re);
-assign litedramcore_bankmachine7_rdport_adr = litedramcore_bankmachine7_consume;
-assign litedramcore_bankmachine7_syncfifo7_dout = litedramcore_bankmachine7_rdport_dat_r;
-assign litedramcore_bankmachine7_syncfifo7_writable = (litedramcore_bankmachine7_level != 5'd16);
-assign litedramcore_bankmachine7_syncfifo7_readable = (litedramcore_bankmachine7_level != 1'd0);
-assign litedramcore_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready);
-assign litedramcore_bankmachine7_pipe_valid_sink_valid = litedramcore_bankmachine7_sink_sink_valid;
-assign litedramcore_bankmachine7_sink_sink_ready = litedramcore_bankmachine7_pipe_valid_sink_ready;
-assign litedramcore_bankmachine7_pipe_valid_sink_first = litedramcore_bankmachine7_sink_sink_first;
-assign litedramcore_bankmachine7_pipe_valid_sink_last = litedramcore_bankmachine7_sink_sink_last;
-assign litedramcore_bankmachine7_pipe_valid_sink_payload_we = litedramcore_bankmachine7_sink_sink_payload_we;
-assign litedramcore_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_bankmachine7_sink_sink_payload_addr;
-assign litedramcore_bankmachine7_source_source_valid = litedramcore_bankmachine7_pipe_valid_source_valid;
-assign litedramcore_bankmachine7_pipe_valid_source_ready = litedramcore_bankmachine7_source_source_ready;
-assign litedramcore_bankmachine7_source_source_first = litedramcore_bankmachine7_pipe_valid_source_first;
-assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_pipe_valid_source_last;
-assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine7_next_state <= 4'd0;
-    litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                if (litedramcore_bankmachine7_cmd_ready) begin
-                    litedramcore_bankmachine7_next_state <= 3'd5;
-                end
-            end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                if (litedramcore_bankmachine7_cmd_ready) begin
-                    litedramcore_bankmachine7_next_state <= 3'd7;
-                end
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine7_refresh_req)) begin
-                litedramcore_bankmachine7_next_state <= 1'd0;
-            end
         end
         3'd5: begin
-            litedramcore_bankmachine7_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine7_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine7_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine7_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
-                litedramcore_bankmachine7_next_state <= 3'd4;
-            end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
-                                litedramcore_bankmachine7_next_state <= 2'd2;
-                            end
-                        end else begin
-                            litedramcore_bankmachine7_next_state <= 1'd1;
-                        end
-                    end else begin
-                        litedramcore_bankmachine7_next_state <= 2'd3;
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8904,12 +9350,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -8920,18 +9366,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -8949,11 +9395,11 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
@@ -8971,13 +9417,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
-                                litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
+                                main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -8990,22 +9436,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -9020,8 +9466,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9039,14 +9485,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -9058,8 +9504,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9077,13 +9523,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
-                                litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
+                                main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -9096,8 +9542,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9115,13 +9561,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
-                                litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
+                                main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -9134,8 +9580,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9153,14 +9599,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
+                                main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
                             end
                         end else begin
                         end
@@ -9172,8 +9618,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9181,8 +9627,8 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine7_twtpcon_ready) begin
-                litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+            if (main_litedramcore_bankmachine7_twtpcon_ready) begin
+                main_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
             end
         end
         3'd5: begin
@@ -9198,15 +9644,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_row_open <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_row_open <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -9224,18 +9670,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -9249,12 +9695,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            litedramcore_bankmachine7_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -9265,18 +9711,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_row_close <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_row_close <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            litedramcore_bankmachine7_row_close <= 1'd1;
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine7_row_close <= 1'd1;
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine7_row_close <= 1'd1;
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -9290,292 +9736,263 @@ always @(*) begin
         end
     endcase
 end
+assign main_litedramcore_nphases = (main_a7ddrphy_rdphase_storage - 1'd1);
+assign main_litedramcore_rdphase = (main_a7ddrphy_wrphase_storage - 1'd1);
+assign main_litedramcore_trrdcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we)));
+assign main_litedramcore_tfawcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we)));
+assign main_litedramcore_ras_allowed = (main_litedramcore_trrdcon_ready & main_litedramcore_tfawcon_ready);
+assign main_litedramcore_tccdcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_cmd_payload_is_write | main_litedramcore_choose_req_cmd_payload_is_read));
+assign main_litedramcore_cas_allowed = main_litedramcore_tccdcon_ready;
+assign main_litedramcore_twtrcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+assign main_litedramcore_read_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_read) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_read)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_read)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_read)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_read)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_read)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_read)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_read));
+assign main_litedramcore_write_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_write) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_write)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_write)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_write)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_write)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_write)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_write)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_write));
+assign main_litedramcore_max_time0 = (main_litedramcore_time0 == 1'd0);
+assign main_litedramcore_max_time1 = (main_litedramcore_time1 == 1'd0);
+assign main_litedramcore_bankmachine0_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine1_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine2_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine3_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine4_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine5_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine6_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine7_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_go_to_refresh = (((((((main_litedramcore_bankmachine0_refresh_gnt & main_litedramcore_bankmachine1_refresh_gnt) & main_litedramcore_bankmachine2_refresh_gnt) & main_litedramcore_bankmachine3_refresh_gnt) & main_litedramcore_bankmachine4_refresh_gnt) & main_litedramcore_bankmachine5_refresh_gnt) & main_litedramcore_bankmachine6_refresh_gnt) & main_litedramcore_bankmachine7_refresh_gnt);
+assign main_litedramcore_interface_rdata = {main_litedramcore_dfi_p3_rddata, main_litedramcore_dfi_p2_rddata, main_litedramcore_dfi_p1_rddata, main_litedramcore_dfi_p0_rddata};
+assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
+assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
+assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
+assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
+assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
+assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
+assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
+assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
 always @(*) begin
-    litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine7_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-assign litedramcore_rdcmdphase = (a7ddrphy_rdphase_storage - 1'd1);
-assign litedramcore_wrcmdphase = (a7ddrphy_wrphase_storage - 1'd1);
-assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
-assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
-assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready);
-assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read));
-assign litedramcore_cas_allowed = litedramcore_tccdcon_ready;
-assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
-assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read));
-assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write));
-assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0);
-assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0);
-assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt);
-assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata};
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
-always @(*) begin
-    litedramcore_choose_cmd_valids <= 8'd0;
-    litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids <= 8'd0;
+    main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
 end
-assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
-assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
-assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1;
-assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
-assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
-assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
-assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
+assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids;
+assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_self0;
+assign main_litedramcore_choose_cmd_cmd_payload_a = builder_rhs_self1;
+assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_self2;
+assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_self3;
+assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_self4;
+assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_self5;
 always @(*) begin
-    litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
-    if (litedramcore_choose_cmd_cmd_valid) begin
-        litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
+    main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
+    if (main_litedramcore_choose_cmd_cmd_valid) begin
+        main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_self0;
     end
 end
 always @(*) begin
-    litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
-    if (litedramcore_choose_cmd_cmd_valid) begin
-        litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
+    main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
+    if (main_litedramcore_choose_cmd_cmd_valid) begin
+        main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_self1;
     end
 end
 always @(*) begin
-    litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
-    if (litedramcore_choose_cmd_cmd_valid) begin
-        litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
+    main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
+    if (main_litedramcore_choose_cmd_cmd_valid) begin
+        main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_self2;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
-        litedramcore_bankmachine0_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine0_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin
+        main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
-        litedramcore_bankmachine0_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin
+        main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
-        litedramcore_bankmachine1_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine1_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin
+        main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
-        litedramcore_bankmachine1_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin
+        main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
-        litedramcore_bankmachine2_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine2_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin
+        main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
-        litedramcore_bankmachine2_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin
+        main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
-        litedramcore_bankmachine3_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine3_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin
+        main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
-        litedramcore_bankmachine3_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin
+        main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
-        litedramcore_bankmachine4_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine4_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin
+        main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
-        litedramcore_bankmachine4_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin
+        main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
-        litedramcore_bankmachine5_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine5_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin
+        main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
-        litedramcore_bankmachine5_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin
+        main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
-        litedramcore_bankmachine6_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine6_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin
+        main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
-        litedramcore_bankmachine6_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin
+        main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
-        litedramcore_bankmachine7_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine7_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin
+        main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
-        litedramcore_bankmachine7_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin
+        main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
     end
 end
-assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
+assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid));
 always @(*) begin
-    litedramcore_choose_req_valids <= 8'd0;
-    litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids <= 8'd0;
+    main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
 end
-assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
-assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
-assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7;
-assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8;
-assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9;
-assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
-assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
+assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids;
+assign main_litedramcore_choose_req_cmd_valid = builder_rhs_self6;
+assign main_litedramcore_choose_req_cmd_payload_a = builder_rhs_self7;
+assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_self8;
+assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_self9;
+assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_self10;
+assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_self11;
 always @(*) begin
-    litedramcore_choose_req_cmd_payload_cas <= 1'd0;
-    if (litedramcore_choose_req_cmd_valid) begin
-        litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
+    main_litedramcore_choose_req_cmd_payload_cas <= 1'd0;
+    if (main_litedramcore_choose_req_cmd_valid) begin
+        main_litedramcore_choose_req_cmd_payload_cas <= builder_t_self3;
     end
 end
 always @(*) begin
-    litedramcore_choose_req_cmd_payload_ras <= 1'd0;
-    if (litedramcore_choose_req_cmd_valid) begin
-        litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
+    main_litedramcore_choose_req_cmd_payload_ras <= 1'd0;
+    if (main_litedramcore_choose_req_cmd_valid) begin
+        main_litedramcore_choose_req_cmd_payload_ras <= builder_t_self4;
     end
 end
 always @(*) begin
-    litedramcore_choose_req_cmd_payload_we <= 1'd0;
-    if (litedramcore_choose_req_cmd_valid) begin
-        litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
+    main_litedramcore_choose_req_cmd_payload_we <= 1'd0;
+    if (main_litedramcore_choose_req_cmd_valid) begin
+        main_litedramcore_choose_req_cmd_payload_we <= builder_t_self5;
     end
 end
-assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
-assign litedramcore_dfi_p0_reset_n = 1'd1;
-assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}};
-assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}};
-assign litedramcore_dfi_p1_reset_n = 1'd1;
-assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}};
-assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}};
-assign litedramcore_dfi_p2_reset_n = 1'd1;
-assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}};
-assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}};
-assign litedramcore_dfi_p3_reset_n = 1'd1;
-assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}};
-assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}};
-assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]);
+assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid));
+assign main_litedramcore_dfi_p0_reset_n = 1'd1;
+assign main_litedramcore_dfi_p0_cke = {1{main_litedramcore_steerer4}};
+assign main_litedramcore_dfi_p0_odt = {1{main_litedramcore_steerer5}};
+assign main_litedramcore_dfi_p1_reset_n = 1'd1;
+assign main_litedramcore_dfi_p1_cke = {1{main_litedramcore_steerer6}};
+assign main_litedramcore_dfi_p1_odt = {1{main_litedramcore_steerer7}};
+assign main_litedramcore_dfi_p2_reset_n = 1'd1;
+assign main_litedramcore_dfi_p2_cke = {1{main_litedramcore_steerer8}};
+assign main_litedramcore_dfi_p2_odt = {1{main_litedramcore_steerer9}};
+assign main_litedramcore_dfi_p3_reset_n = 1'd1;
+assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer10}};
+assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer11}};
+assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]);
 always @(*) begin
-    litedramcore_multiplexer_next_state <= 4'd0;
-    litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
-    case (litedramcore_multiplexer_state)
+    builder_multiplexer_next_state <= 4'd0;
+    builder_multiplexer_next_state <= builder_multiplexer_state;
+    case (builder_multiplexer_state)
         1'd1: begin
-            if (litedramcore_read_available) begin
-                if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
-                    litedramcore_multiplexer_next_state <= 2'd3;
+            if (main_litedramcore_read_available) begin
+                if (((~main_litedramcore_write_available) | main_litedramcore_max_time1)) begin
+                    builder_multiplexer_next_state <= 2'd3;
                 end
             end
-            if (litedramcore_go_to_refresh) begin
-                litedramcore_multiplexer_next_state <= 2'd2;
+            if (main_litedramcore_go_to_refresh) begin
+                builder_multiplexer_next_state <= 2'd2;
             end
         end
         2'd2: begin
-            if (litedramcore_cmd_last) begin
-                litedramcore_multiplexer_next_state <= 1'd0;
+            if (main_litedramcore_cmd_last) begin
+                builder_multiplexer_next_state <= 1'd0;
             end
         end
         2'd3: begin
-            if (litedramcore_twtrcon_ready) begin
-                litedramcore_multiplexer_next_state <= 1'd0;
+            if (main_litedramcore_twtrcon_ready) begin
+                builder_multiplexer_next_state <= 1'd0;
             end
         end
         3'd4: begin
-            litedramcore_multiplexer_next_state <= 3'd5;
+            builder_multiplexer_next_state <= 3'd5;
         end
         3'd5: begin
-            litedramcore_multiplexer_next_state <= 3'd6;
+            builder_multiplexer_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_multiplexer_next_state <= 3'd7;
+            builder_multiplexer_next_state <= 3'd7;
         end
         3'd7: begin
-            litedramcore_multiplexer_next_state <= 4'd8;
+            builder_multiplexer_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_multiplexer_next_state <= 4'd9;
+            builder_multiplexer_next_state <= 4'd9;
         end
         4'd9: begin
-            litedramcore_multiplexer_next_state <= 4'd10;
+            builder_multiplexer_next_state <= 4'd10;
         end
         4'd10: begin
-            litedramcore_multiplexer_next_state <= 1'd1;
+            builder_multiplexer_next_state <= 1'd1;
         end
         default: begin
-            if (litedramcore_write_available) begin
-                if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
-                    litedramcore_multiplexer_next_state <= 3'd4;
+            if (main_litedramcore_write_available) begin
+                if (((~main_litedramcore_read_available) | main_litedramcore_max_time0)) begin
+                    builder_multiplexer_next_state <= 3'd4;
                 end
             end
-            if (litedramcore_go_to_refresh) begin
-                litedramcore_multiplexer_next_state <= 2'd2;
+            if (main_litedramcore_go_to_refresh) begin
+                builder_multiplexer_next_state <= 2'd2;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_steerer_sel0 <= 2'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_choose_req_cmd_ready <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer_sel0 <= 1'd0;
-            if ((a7ddrphy_wrphase_storage == 1'd0)) begin
-                litedramcore_steerer_sel0 <= 2'd2;
-            end
-            if ((litedramcore_wrcmdphase == 1'd0)) begin
-                litedramcore_steerer_sel0 <= 1'd1;
+            if (1'd0) begin
+                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+            end else begin
+                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
             end
         end
         2'd2: begin
-            litedramcore_steerer_sel0 <= 2'd3;
         end
         2'd3: begin
         end
@@ -9594,23 +10011,21 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_steerer_sel0 <= 1'd0;
-            if ((a7ddrphy_rdphase_storage == 1'd0)) begin
-                litedramcore_steerer_sel0 <= 2'd2;
-            end
-            if ((litedramcore_rdcmdphase == 1'd0)) begin
-                litedramcore_steerer_sel0 <= 1'd1;
+            if (1'd0) begin
+                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+            end else begin
+                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_cmd_ready <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_en1 <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
+            main_litedramcore_en1 <= 1'd1;
         end
         2'd2: begin
-            litedramcore_cmd_ready <= 1'd1;
         end
         2'd3: begin
         end
@@ -9633,18 +10048,19 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_steerer_sel1 <= 2'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_steerer0 <= 2'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer_sel1 <= 1'd0;
-            if ((a7ddrphy_wrphase_storage == 1'd1)) begin
-                litedramcore_steerer_sel1 <= 2'd2;
+            main_litedramcore_steerer0 <= 1'd0;
+            if ((main_a7ddrphy_wrphase_storage == 1'd0)) begin
+                main_litedramcore_steerer0 <= 2'd2;
             end
-            if ((litedramcore_wrcmdphase == 1'd1)) begin
-                litedramcore_steerer_sel1 <= 1'd1;
+            if ((main_litedramcore_rdphase == 1'd0)) begin
+                main_litedramcore_steerer0 <= 1'd1;
             end
         end
         2'd2: begin
+            main_litedramcore_steerer0 <= 2'd3;
         end
         2'd3: begin
         end
@@ -9663,29 +10079,23 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_steerer_sel1 <= 1'd0;
-            if ((a7ddrphy_rdphase_storage == 1'd1)) begin
-                litedramcore_steerer_sel1 <= 2'd2;
+            main_litedramcore_steerer0 <= 1'd0;
+            if ((main_a7ddrphy_rdphase_storage == 1'd0)) begin
+                main_litedramcore_steerer0 <= 2'd2;
             end
-            if ((litedramcore_rdcmdphase == 1'd1)) begin
-                litedramcore_steerer_sel1 <= 1'd1;
+            if ((main_litedramcore_nphases == 1'd0)) begin
+                main_litedramcore_steerer0 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_steerer_sel2 <= 2'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_cmd_ready <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer_sel2 <= 1'd0;
-            if ((a7ddrphy_wrphase_storage == 2'd2)) begin
-                litedramcore_steerer_sel2 <= 2'd2;
-            end
-            if ((litedramcore_wrcmdphase == 2'd2)) begin
-                litedramcore_steerer_sel2 <= 1'd1;
-            end
         end
         2'd2: begin
+            main_litedramcore_cmd_ready <= 1'd1;
         end
         2'd3: begin
         end
@@ -9704,23 +10114,19 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_steerer_sel2 <= 1'd0;
-            if ((a7ddrphy_rdphase_storage == 2'd2)) begin
-                litedramcore_steerer_sel2 <= 2'd2;
-            end
-            if ((litedramcore_rdcmdphase == 2'd2)) begin
-                litedramcore_steerer_sel2 <= 1'd1;
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_cmd_want_activates <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_steerer1 <= 2'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            if (1'd0) begin
-            end else begin
-                litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+            main_litedramcore_steerer1 <= 1'd0;
+            if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin
+                main_litedramcore_steerer1 <= 2'd2;
+            end
+            if ((main_litedramcore_rdphase == 1'd1)) begin
+                main_litedramcore_steerer1 <= 1'd1;
             end
         end
         2'd2: begin
@@ -9742,23 +10148,26 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            if (1'd0) begin
-            end else begin
-                litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+            main_litedramcore_steerer1 <= 1'd0;
+            if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin
+                main_litedramcore_steerer1 <= 2'd2;
+            end
+            if ((main_litedramcore_nphases == 1'd1)) begin
+                main_litedramcore_steerer1 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_steerer_sel3 <= 2'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_steerer2 <= 2'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer_sel3 <= 1'd0;
-            if ((a7ddrphy_wrphase_storage == 2'd3)) begin
-                litedramcore_steerer_sel3 <= 2'd2;
+            main_litedramcore_steerer2 <= 1'd0;
+            if ((main_a7ddrphy_wrphase_storage == 2'd2)) begin
+                main_litedramcore_steerer2 <= 2'd2;
             end
-            if ((litedramcore_wrcmdphase == 2'd3)) begin
-                litedramcore_steerer_sel3 <= 1'd1;
+            if ((main_litedramcore_rdphase == 2'd2)) begin
+                main_litedramcore_steerer2 <= 1'd1;
             end
         end
         2'd2: begin
@@ -9780,20 +10189,24 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_steerer_sel3 <= 1'd0;
-            if ((a7ddrphy_rdphase_storage == 2'd3)) begin
-                litedramcore_steerer_sel3 <= 2'd2;
+            main_litedramcore_steerer2 <= 1'd0;
+            if ((main_a7ddrphy_rdphase_storage == 2'd2)) begin
+                main_litedramcore_steerer2 <= 2'd2;
             end
-            if ((litedramcore_rdcmdphase == 2'd3)) begin
-                litedramcore_steerer_sel3 <= 1'd1;
+            if ((main_litedramcore_nphases == 2'd2)) begin
+                main_litedramcore_steerer2 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_en0 <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_choose_cmd_want_activates <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
+            if (1'd0) begin
+            end else begin
+                main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
+            end
         end
         2'd2: begin
         end
@@ -9814,17 +10227,23 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_en0 <= 1'd1;
+            if (1'd0) begin
+            end else begin
+                main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_cmd_cmd_ready <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_steerer3 <= 2'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            if (1'd0) begin
-            end else begin
-                litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+            main_litedramcore_steerer3 <= 1'd0;
+            if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin
+                main_litedramcore_steerer3 <= 2'd2;
+            end
+            if ((main_litedramcore_rdphase == 2'd3)) begin
+                main_litedramcore_steerer3 <= 1'd1;
             end
         end
         2'd2: begin
@@ -9846,16 +10265,19 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            if (1'd0) begin
-            end else begin
-                litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+            main_litedramcore_steerer3 <= 1'd0;
+            if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin
+                main_litedramcore_steerer3 <= 2'd2;
+            end
+            if ((main_litedramcore_nphases == 2'd3)) begin
+                main_litedramcore_steerer3 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_req_want_reads <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_en0 <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9877,15 +10299,18 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_choose_req_want_reads <= 1'd1;
+            main_litedramcore_en0 <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_req_want_writes <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_choose_req_want_writes <= 1'd1;
+            if (1'd0) begin
+            end else begin
+                main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+            end
         end
         2'd2: begin
         end
@@ -9906,14 +10331,17 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
+            if (1'd0) begin
+            end else begin
+                main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_en1 <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_choose_req_want_reads <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_en1 <= 1'd1;
         end
         2'd2: begin
         end
@@ -9934,18 +10362,15 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
+            main_litedramcore_choose_req_want_reads <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_req_cmd_ready <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_choose_req_want_writes <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            if (1'd0) begin
-                litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
-            end else begin
-                litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
-            end
+            main_litedramcore_choose_req_want_writes <= 1'd1;
         end
         2'd2: begin
         end
@@ -9966,2016 +10391,2008 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            if (1'd0) begin
-                litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
-            end else begin
-                litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
-            end
         end
     endcase
 end
-assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
-assign litedramcore_interface_bank0_addr = rhs_array_muxed12;
-assign litedramcore_interface_bank0_we = rhs_array_muxed13;
-assign litedramcore_interface_bank0_valid = rhs_array_muxed14;
-assign litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock));
-assign litedramcore_interface_bank1_addr = rhs_array_muxed15;
-assign litedramcore_interface_bank1_we = rhs_array_muxed16;
-assign litedramcore_interface_bank1_valid = rhs_array_muxed17;
-assign litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock));
-assign litedramcore_interface_bank2_addr = rhs_array_muxed18;
-assign litedramcore_interface_bank2_we = rhs_array_muxed19;
-assign litedramcore_interface_bank2_valid = rhs_array_muxed20;
-assign litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock));
-assign litedramcore_interface_bank3_addr = rhs_array_muxed21;
-assign litedramcore_interface_bank3_we = rhs_array_muxed22;
-assign litedramcore_interface_bank3_valid = rhs_array_muxed23;
-assign litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock));
-assign litedramcore_interface_bank4_addr = rhs_array_muxed24;
-assign litedramcore_interface_bank4_we = rhs_array_muxed25;
-assign litedramcore_interface_bank4_valid = rhs_array_muxed26;
-assign litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock));
-assign litedramcore_interface_bank5_addr = rhs_array_muxed27;
-assign litedramcore_interface_bank5_we = rhs_array_muxed28;
-assign litedramcore_interface_bank5_valid = rhs_array_muxed29;
-assign litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock));
-assign litedramcore_interface_bank6_addr = rhs_array_muxed30;
-assign litedramcore_interface_bank6_we = rhs_array_muxed31;
-assign litedramcore_interface_bank6_valid = rhs_array_muxed32;
-assign litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock));
-assign litedramcore_interface_bank7_addr = rhs_array_muxed33;
-assign litedramcore_interface_bank7_we = rhs_array_muxed34;
-assign litedramcore_interface_bank7_valid = rhs_array_muxed35;
-assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready));
-assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1;
-assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8;
-always @(*) begin
-    litedramcore_interface_wdata <= 128'd0;
-    case ({litedramcore_new_master_wdata_ready1})
+assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock));
+assign main_litedramcore_interface_bank0_addr = builder_rhs_self12;
+assign main_litedramcore_interface_bank0_we = builder_rhs_self13;
+assign main_litedramcore_interface_bank0_valid = builder_rhs_self14;
+assign builder_roundrobin1_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin1_ce = ((~main_litedramcore_interface_bank1_valid) & (~main_litedramcore_interface_bank1_lock));
+assign main_litedramcore_interface_bank1_addr = builder_rhs_self15;
+assign main_litedramcore_interface_bank1_we = builder_rhs_self16;
+assign main_litedramcore_interface_bank1_valid = builder_rhs_self17;
+assign builder_roundrobin2_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin2_ce = ((~main_litedramcore_interface_bank2_valid) & (~main_litedramcore_interface_bank2_lock));
+assign main_litedramcore_interface_bank2_addr = builder_rhs_self18;
+assign main_litedramcore_interface_bank2_we = builder_rhs_self19;
+assign main_litedramcore_interface_bank2_valid = builder_rhs_self20;
+assign builder_roundrobin3_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin3_ce = ((~main_litedramcore_interface_bank3_valid) & (~main_litedramcore_interface_bank3_lock));
+assign main_litedramcore_interface_bank3_addr = builder_rhs_self21;
+assign main_litedramcore_interface_bank3_we = builder_rhs_self22;
+assign main_litedramcore_interface_bank3_valid = builder_rhs_self23;
+assign builder_roundrobin4_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin4_ce = ((~main_litedramcore_interface_bank4_valid) & (~main_litedramcore_interface_bank4_lock));
+assign main_litedramcore_interface_bank4_addr = builder_rhs_self24;
+assign main_litedramcore_interface_bank4_we = builder_rhs_self25;
+assign main_litedramcore_interface_bank4_valid = builder_rhs_self26;
+assign builder_roundrobin5_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin5_ce = ((~main_litedramcore_interface_bank5_valid) & (~main_litedramcore_interface_bank5_lock));
+assign main_litedramcore_interface_bank5_addr = builder_rhs_self27;
+assign main_litedramcore_interface_bank5_we = builder_rhs_self28;
+assign main_litedramcore_interface_bank5_valid = builder_rhs_self29;
+assign builder_roundrobin6_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin6_ce = ((~main_litedramcore_interface_bank6_valid) & (~main_litedramcore_interface_bank6_lock));
+assign main_litedramcore_interface_bank6_addr = builder_rhs_self30;
+assign main_litedramcore_interface_bank6_we = builder_rhs_self31;
+assign main_litedramcore_interface_bank6_valid = builder_rhs_self32;
+assign builder_roundrobin7_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin7_ce = ((~main_litedramcore_interface_bank7_valid) & (~main_litedramcore_interface_bank7_lock));
+assign main_litedramcore_interface_bank7_addr = builder_rhs_self33;
+assign main_litedramcore_interface_bank7_we = builder_rhs_self34;
+assign main_litedramcore_interface_bank7_valid = builder_rhs_self35;
+assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready));
+assign main_user_port_wdata_ready = builder_new_master_wdata_ready1;
+assign main_user_port_rdata_valid = builder_new_master_rdata_valid8;
+always @(*) begin
+    main_litedramcore_interface_wdata <= 128'd0;
+    case ({builder_new_master_wdata_ready1})
         1'd1: begin
-            litedramcore_interface_wdata <= user_port_wdata_payload_data;
+            main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data;
         end
         default: begin
-            litedramcore_interface_wdata <= 1'd0;
+            main_litedramcore_interface_wdata <= 1'd0;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_interface_wdata_we <= 16'd0;
-    case ({litedramcore_new_master_wdata_ready1})
+    main_litedramcore_interface_wdata_we <= 16'd0;
+    case ({builder_new_master_wdata_ready1})
         1'd1: begin
-            litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
+            main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we;
         end
         default: begin
-            litedramcore_interface_wdata_we <= 1'd0;
+            main_litedramcore_interface_wdata_we <= 1'd0;
         end
     endcase
 end
-assign user_port_rdata_payload_data = litedramcore_interface_rdata;
-assign litedramcore_roundrobin0_grant = 1'd0;
-assign litedramcore_roundrobin1_grant = 1'd0;
-assign litedramcore_roundrobin2_grant = 1'd0;
-assign litedramcore_roundrobin3_grant = 1'd0;
-assign litedramcore_roundrobin4_grant = 1'd0;
-assign litedramcore_roundrobin5_grant = 1'd0;
-assign litedramcore_roundrobin6_grant = 1'd0;
-assign litedramcore_roundrobin7_grant = 1'd0;
-always @(*) begin
-    litedramcore_next_state <= 2'd0;
-    litedramcore_next_state <= litedramcore_state;
-    case (litedramcore_state)
+assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata;
+assign builder_roundrobin0_grant = 1'd0;
+assign builder_roundrobin1_grant = 1'd0;
+assign builder_roundrobin2_grant = 1'd0;
+assign builder_roundrobin3_grant = 1'd0;
+assign builder_roundrobin4_grant = 1'd0;
+assign builder_roundrobin5_grant = 1'd0;
+assign builder_roundrobin6_grant = 1'd0;
+assign builder_roundrobin7_grant = 1'd0;
+always @(*) begin
+    builder_next_state <= 2'd0;
+    builder_next_state <= builder_state;
+    case (builder_state)
         1'd1: begin
-            litedramcore_next_state <= 2'd2;
+            builder_next_state <= 2'd2;
         end
         2'd2: begin
-            litedramcore_next_state <= 1'd0;
+            builder_next_state <= 1'd0;
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_next_state <= 1'd1;
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_next_state <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_adr_next_value1 <= 14'd0;
-    case (litedramcore_state)
+    builder_interface0_dat_r <= 32'd0;
+    case (builder_state)
         1'd1: begin
-            litedramcore_adr_next_value1 <= 1'd0;
         end
         2'd2: begin
+            builder_interface0_dat_r <= builder_interface1_dat_r;
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_adr_next_value_ce1 <= 1'd0;
-    case (litedramcore_state)
+    builder_interface1_dat_w_next_value0 <= 32'd0;
+    case (builder_state)
         1'd1: begin
-            litedramcore_adr_next_value_ce1 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_adr_next_value_ce1 <= 1'd1;
-            end
+            builder_interface1_dat_w_next_value0 <= builder_interface0_dat_w;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_wishbone_dat_r <= 32'd0;
-    case (litedramcore_state)
+    builder_interface1_dat_w_next_value_ce0 <= 1'd0;
+    case (builder_state)
         1'd1: begin
         end
         2'd2: begin
-            litedramcore_wishbone_dat_r <= litedramcore_dat_r;
         end
         default: begin
+            builder_interface1_dat_w_next_value_ce0 <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_we_next_value2 <= 1'd0;
-    case (litedramcore_state)
+    builder_interface1_adr_next_value1 <= 14'd0;
+    case (builder_state)
         1'd1: begin
-            litedramcore_we_next_value2 <= 1'd0;
+            builder_interface1_adr_next_value1 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_adr_next_value1 <= builder_interface0_adr[29:0];
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_we_next_value_ce2 <= 1'd0;
-    case (litedramcore_state)
+    builder_interface0_ack <= 1'd0;
+    case (builder_state)
         1'd1: begin
-            litedramcore_we_next_value_ce2 <= 1'd1;
         end
         2'd2: begin
+            builder_interface0_ack <= 1'd1;
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_we_next_value_ce2 <= 1'd1;
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_wishbone_ack <= 1'd0;
-    case (litedramcore_state)
+    builder_interface1_adr_next_value_ce1 <= 1'd0;
+    case (builder_state)
         1'd1: begin
+            builder_interface1_adr_next_value_ce1 <= 1'd1;
         end
         2'd2: begin
-            litedramcore_wishbone_ack <= 1'd1;
         end
         default: begin
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_adr_next_value_ce1 <= 1'd1;
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_dat_w_next_value0 <= 32'd0;
-    case (litedramcore_state)
+    builder_interface1_we_next_value2 <= 1'd0;
+    case (builder_state)
         1'd1: begin
+            builder_interface1_we_next_value2 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
-            litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_we_next_value2 <= (builder_interface0_we & (builder_interface0_sel != 1'd0));
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_dat_w_next_value_ce0 <= 1'd0;
-    case (litedramcore_state)
+    builder_interface1_we_next_value_ce2 <= 1'd0;
+    case (builder_state)
         1'd1: begin
+            builder_interface1_we_next_value_ce2 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
-            litedramcore_dat_w_next_value_ce0 <= 1'd1;
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_we_next_value_ce2 <= 1'd1;
+            end
         end
     endcase
 end
-assign litedramcore_wishbone_adr = wb_bus_adr;
-assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
-assign wb_bus_dat_r = litedramcore_wishbone_dat_r;
-assign litedramcore_wishbone_sel = wb_bus_sel;
-assign litedramcore_wishbone_cyc = wb_bus_cyc;
-assign litedramcore_wishbone_stb = wb_bus_stb;
-assign wb_bus_ack = litedramcore_wishbone_ack;
-assign litedramcore_wishbone_we = wb_bus_we;
-assign litedramcore_wishbone_cti = wb_bus_cti;
-assign litedramcore_wishbone_bte = wb_bus_bte;
-assign wb_bus_err = litedramcore_wishbone_err;
-assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
-assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
+assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0);
+assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank0_init_done0_we <= 1'd0;
-    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank0_init_done0_we <= (~interface0_bank_bus_we);
+    builder_csrbank0_init_done0_re <= 1'd0;
+    if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank0_init_done0_re <= 1'd0;
-    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank0_init_done0_re <= interface0_bank_bus_we;
+    builder_csrbank0_init_done0_we <= 1'd0;
+    if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
     end
 end
-assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
+assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank0_init_error0_we <= 1'd0;
-    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank0_init_error0_we <= (~interface0_bank_bus_we);
+    builder_csrbank0_init_error0_we <= 1'd0;
+    if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank0_init_error0_re <= 1'd0;
-    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank0_init_error0_re <= interface0_bank_bus_we;
+    builder_csrbank0_init_error0_re <= 1'd0;
+    if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
     end
 end
-assign csrbank0_init_done0_w = init_done_storage;
-assign csrbank0_init_error0_w = init_error_storage;
-assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
-assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0];
+assign builder_csrbank0_init_done0_w = main_init_done_storage;
+assign builder_csrbank0_init_error0_w = main_init_error_storage;
+assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
+assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank1_rst0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank1_rst0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_rst0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank1_rst0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank1_rst0_re <= interface1_bank_bus_we;
+    builder_csrbank1_rst0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
     end
 end
-assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
+assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    csrbank1_dly_sel0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank1_dly_sel0_re <= interface1_bank_bus_we;
+    builder_csrbank1_dly_sel0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_dly_sel0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_dly_sel0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
+assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0];
 always @(*) begin
-    csrbank1_half_sys8x_taps0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
+        builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_half_sys8x_taps0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we;
+    builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
+        builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0];
+assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank1_wlevel_en0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank1_wlevel_en0_re <= interface1_bank_bus_we;
+    builder_csrbank1_wlevel_en0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
+        builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank1_wlevel_en0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_wlevel_en0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
+        builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
     end
 end
-assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_wlevel_strobe_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
-        a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we;
+    main_a7ddrphy_wlevel_strobe_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
+        main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    a7ddrphy_wlevel_strobe_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
-        a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_wlevel_strobe_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
+        main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_rdly_dq_rst_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
+    main_a7ddrphy_rdly_dq_rst_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
+        main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    a7ddrphy_rdly_dq_rst_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_rdly_dq_rst_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
+        main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_rdly_dq_inc_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
+    main_a7ddrphy_rdly_dq_inc_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
+        main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    a7ddrphy_rdly_dq_inc_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_rdly_dq_inc_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
+        main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
-        a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
+        main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
-        a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
+    main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
+        main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
     end
 end
-assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
-        a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
+        main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
-        a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we;
+    main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
+        main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
     end
 end
-assign a7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
-        a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
+        main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
-        a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
+    main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
+        main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
     end
 end
-assign a7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
-        a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
+        main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
-        a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we;
+    main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
+        main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
     end
 end
-assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0];
+assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    csrbank1_rdphase0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
-        csrbank1_rdphase0_re <= interface1_bank_bus_we;
+    builder_csrbank1_rdphase0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
+        builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_rdphase0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
-        csrbank1_rdphase0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_rdphase0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
+        builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0];
+assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    csrbank1_wrphase0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
-        csrbank1_wrphase0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_wrphase0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
+        builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank1_wrphase0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
-        csrbank1_wrphase0_re <= interface1_bank_bus_we;
+    builder_csrbank1_wrphase0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
+        builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
     end
 end
-assign csrbank1_rst0_w = a7ddrphy_rst_storage;
-assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0];
-assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0];
-assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage;
-assign csrbank1_rdphase0_w = a7ddrphy_rdphase_storage[1:0];
-assign csrbank1_wrphase0_w = a7ddrphy_wrphase_storage[1:0];
-assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2);
-assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
+assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage;
+assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0];
+assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0];
+assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage;
+assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0];
+assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0];
+assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
+assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
 always @(*) begin
-    csrbank2_dfii_control0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank2_dfii_control0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_control0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_control0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_control0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
+assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi0_command0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_command0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_command0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
+assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    litedramcore_phaseinjector0_command_issue_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
-        litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
+    main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
+        main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    litedramcore_phaseinjector0_command_issue_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
-        litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
+    main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
+        main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[15:0];
+assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[15:0];
 always @(*) begin
-    csrbank2_dfii_pi0_address0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
+        builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_address0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_address0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
+        builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank2_dfii_pi0_baddress0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
-        csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
+        builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_baddress0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
-        csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
+        builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
-        csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
+        builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
-        csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
+        builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi0_rddata_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
-        csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_rddata_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
+        builder_csrbank2_dfii_pi0_rddata_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_rddata_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
-        csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_rddata_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
+        builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
+assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi1_command0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
-        csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_command0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
+        builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_command0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
-        csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
+        builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
+assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    litedramcore_phaseinjector1_command_issue_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
-        litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we;
+    main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
+        main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    litedramcore_phaseinjector1_command_issue_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
-        litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
+    main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
+        main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[15:0];
+assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[15:0];
 always @(*) begin
-    csrbank2_dfii_pi1_address0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
-        csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
+        builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_address0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
-        csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_address0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
+        builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank2_dfii_pi1_baddress0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
-        csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
+        builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_baddress0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
-        csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
+        builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
-        csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
+        builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
-        csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
+        builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi1_rddata_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
-        csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_rddata_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
+        builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_rddata_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
-        csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_rddata_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
+        builder_csrbank2_dfii_pi1_rddata_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0];
+assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi2_command0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
-        csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_command0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
+        builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_command0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
-        csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_command0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
+        builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0];
+assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    litedramcore_phaseinjector2_command_issue_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
-        litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we);
+    main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
+        main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    litedramcore_phaseinjector2_command_issue_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
-        litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we;
+    main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
+        main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[15:0];
+assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[15:0];
 always @(*) begin
-    csrbank2_dfii_pi2_address0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
-        csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_address0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
+        builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_address0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
-        csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
+        builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank2_dfii_pi2_baddress0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
-        csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
+        builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_baddress0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
-        csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
+        builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
-        csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+        builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
-        csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+        builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi2_rddata_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
-        csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_rddata_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+        builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_rddata_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
-        csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_rddata_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+        builder_csrbank2_dfii_pi2_rddata_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0];
+assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi3_command0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
-        csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
+        builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_command0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
-        csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_command0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
+        builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0];
+assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    litedramcore_phaseinjector3_command_issue_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
-        litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we;
+    main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
+        main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    litedramcore_phaseinjector3_command_issue_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
-        litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we);
+    main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
+        main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[15:0];
+assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[15:0];
 always @(*) begin
-    csrbank2_dfii_pi3_address0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
-        csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_address0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
+        builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_address0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
-        csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
+        builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank2_dfii_pi3_baddress0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
-        csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+        builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_baddress0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
-        csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+        builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
-        csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
+        builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
-        csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
+        builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi3_rddata_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
-        csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_rddata_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
+        builder_csrbank2_dfii_pi3_rddata_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_rddata_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
-        csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_rddata_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
+        builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign litedramcore_sel = litedramcore_storage[0];
-assign litedramcore_cke = litedramcore_storage[1];
-assign litedramcore_odt = litedramcore_storage[2];
-assign litedramcore_reset_n = litedramcore_storage[3];
-assign csrbank2_dfii_control0_w = litedramcore_storage[3:0];
-assign litedramcore_phaseinjector0_csrfield_cs = litedramcore_phaseinjector0_command_storage[0];
-assign litedramcore_phaseinjector0_csrfield_we = litedramcore_phaseinjector0_command_storage[1];
-assign litedramcore_phaseinjector0_csrfield_cas = litedramcore_phaseinjector0_command_storage[2];
-assign litedramcore_phaseinjector0_csrfield_ras = litedramcore_phaseinjector0_command_storage[3];
-assign litedramcore_phaseinjector0_csrfield_wren = litedramcore_phaseinjector0_command_storage[4];
-assign litedramcore_phaseinjector0_csrfield_rden = litedramcore_phaseinjector0_command_storage[5];
-assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
-assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[15:0];
-assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
-assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
-assign csrbank2_dfii_pi0_rddata_w = litedramcore_phaseinjector0_rddata_status[31:0];
-assign litedramcore_phaseinjector0_rddata_we = csrbank2_dfii_pi0_rddata_we;
-assign litedramcore_phaseinjector1_csrfield_cs = litedramcore_phaseinjector1_command_storage[0];
-assign litedramcore_phaseinjector1_csrfield_we = litedramcore_phaseinjector1_command_storage[1];
-assign litedramcore_phaseinjector1_csrfield_cas = litedramcore_phaseinjector1_command_storage[2];
-assign litedramcore_phaseinjector1_csrfield_ras = litedramcore_phaseinjector1_command_storage[3];
-assign litedramcore_phaseinjector1_csrfield_wren = litedramcore_phaseinjector1_command_storage[4];
-assign litedramcore_phaseinjector1_csrfield_rden = litedramcore_phaseinjector1_command_storage[5];
-assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
-assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[15:0];
-assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
-assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
-assign csrbank2_dfii_pi1_rddata_w = litedramcore_phaseinjector1_rddata_status[31:0];
-assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata_we;
-assign litedramcore_phaseinjector2_csrfield_cs = litedramcore_phaseinjector2_command_storage[0];
-assign litedramcore_phaseinjector2_csrfield_we = litedramcore_phaseinjector2_command_storage[1];
-assign litedramcore_phaseinjector2_csrfield_cas = litedramcore_phaseinjector2_command_storage[2];
-assign litedramcore_phaseinjector2_csrfield_ras = litedramcore_phaseinjector2_command_storage[3];
-assign litedramcore_phaseinjector2_csrfield_wren = litedramcore_phaseinjector2_command_storage[4];
-assign litedramcore_phaseinjector2_csrfield_rden = litedramcore_phaseinjector2_command_storage[5];
-assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
-assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[15:0];
-assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
-assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0];
-assign csrbank2_dfii_pi2_rddata_w = litedramcore_phaseinjector2_rddata_status[31:0];
-assign litedramcore_phaseinjector2_rddata_we = csrbank2_dfii_pi2_rddata_we;
-assign litedramcore_phaseinjector3_csrfield_cs = litedramcore_phaseinjector3_command_storage[0];
-assign litedramcore_phaseinjector3_csrfield_we = litedramcore_phaseinjector3_command_storage[1];
-assign litedramcore_phaseinjector3_csrfield_cas = litedramcore_phaseinjector3_command_storage[2];
-assign litedramcore_phaseinjector3_csrfield_ras = litedramcore_phaseinjector3_command_storage[3];
-assign litedramcore_phaseinjector3_csrfield_wren = litedramcore_phaseinjector3_command_storage[4];
-assign litedramcore_phaseinjector3_csrfield_rden = litedramcore_phaseinjector3_command_storage[5];
-assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
-assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[15:0];
-assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
-assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0];
-assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_rddata_status[31:0];
-assign litedramcore_phaseinjector3_rddata_we = csrbank2_dfii_pi3_rddata_we;
-assign csr_interconnect_adr = litedramcore_adr;
-assign csr_interconnect_we = litedramcore_we;
-assign csr_interconnect_dat_w = litedramcore_dat_w;
-assign litedramcore_dat_r = csr_interconnect_dat_r;
-assign interface0_bank_bus_adr = csr_interconnect_adr;
-assign interface1_bank_bus_adr = csr_interconnect_adr;
-assign interface2_bank_bus_adr = csr_interconnect_adr;
-assign interface0_bank_bus_we = csr_interconnect_we;
-assign interface1_bank_bus_we = csr_interconnect_we;
-assign interface2_bank_bus_we = csr_interconnect_we;
-assign interface0_bank_bus_dat_w = csr_interconnect_dat_w;
-assign interface1_bank_bus_dat_w = csr_interconnect_dat_w;
-assign interface2_bank_bus_dat_w = csr_interconnect_dat_w;
-assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
-always @(*) begin
-    rhs_array_muxed0 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+assign main_litedramcore_sel = main_litedramcore_storage[0];
+assign main_litedramcore_cke = main_litedramcore_storage[1];
+assign main_litedramcore_odt = main_litedramcore_storage[2];
+assign main_litedramcore_reset_n = main_litedramcore_storage[3];
+assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0];
+assign main_litedramcore_phaseinjector0_csrfield_cs = main_litedramcore_phaseinjector0_command_storage[0];
+assign main_litedramcore_phaseinjector0_csrfield_we = main_litedramcore_phaseinjector0_command_storage[1];
+assign main_litedramcore_phaseinjector0_csrfield_cas = main_litedramcore_phaseinjector0_command_storage[2];
+assign main_litedramcore_phaseinjector0_csrfield_ras = main_litedramcore_phaseinjector0_command_storage[3];
+assign main_litedramcore_phaseinjector0_csrfield_wren = main_litedramcore_phaseinjector0_command_storage[4];
+assign main_litedramcore_phaseinjector0_csrfield_rden = main_litedramcore_phaseinjector0_command_storage[5];
+assign main_litedramcore_phaseinjector0_csrfield_cs_top = main_litedramcore_phaseinjector0_command_storage[6];
+assign main_litedramcore_phaseinjector0_csrfield_cs_bottom = main_litedramcore_phaseinjector0_command_storage[7];
+assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[7:0];
+assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[15:0];
+assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0];
+assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we;
+assign main_litedramcore_phaseinjector1_csrfield_cs = main_litedramcore_phaseinjector1_command_storage[0];
+assign main_litedramcore_phaseinjector1_csrfield_we = main_litedramcore_phaseinjector1_command_storage[1];
+assign main_litedramcore_phaseinjector1_csrfield_cas = main_litedramcore_phaseinjector1_command_storage[2];
+assign main_litedramcore_phaseinjector1_csrfield_ras = main_litedramcore_phaseinjector1_command_storage[3];
+assign main_litedramcore_phaseinjector1_csrfield_wren = main_litedramcore_phaseinjector1_command_storage[4];
+assign main_litedramcore_phaseinjector1_csrfield_rden = main_litedramcore_phaseinjector1_command_storage[5];
+assign main_litedramcore_phaseinjector1_csrfield_cs_top = main_litedramcore_phaseinjector1_command_storage[6];
+assign main_litedramcore_phaseinjector1_csrfield_cs_bottom = main_litedramcore_phaseinjector1_command_storage[7];
+assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[7:0];
+assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[15:0];
+assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0];
+assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we;
+assign main_litedramcore_phaseinjector2_csrfield_cs = main_litedramcore_phaseinjector2_command_storage[0];
+assign main_litedramcore_phaseinjector2_csrfield_we = main_litedramcore_phaseinjector2_command_storage[1];
+assign main_litedramcore_phaseinjector2_csrfield_cas = main_litedramcore_phaseinjector2_command_storage[2];
+assign main_litedramcore_phaseinjector2_csrfield_ras = main_litedramcore_phaseinjector2_command_storage[3];
+assign main_litedramcore_phaseinjector2_csrfield_wren = main_litedramcore_phaseinjector2_command_storage[4];
+assign main_litedramcore_phaseinjector2_csrfield_rden = main_litedramcore_phaseinjector2_command_storage[5];
+assign main_litedramcore_phaseinjector2_csrfield_cs_top = main_litedramcore_phaseinjector2_command_storage[6];
+assign main_litedramcore_phaseinjector2_csrfield_cs_bottom = main_litedramcore_phaseinjector2_command_storage[7];
+assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[7:0];
+assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[15:0];
+assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0];
+assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we;
+assign main_litedramcore_phaseinjector3_csrfield_cs = main_litedramcore_phaseinjector3_command_storage[0];
+assign main_litedramcore_phaseinjector3_csrfield_we = main_litedramcore_phaseinjector3_command_storage[1];
+assign main_litedramcore_phaseinjector3_csrfield_cas = main_litedramcore_phaseinjector3_command_storage[2];
+assign main_litedramcore_phaseinjector3_csrfield_ras = main_litedramcore_phaseinjector3_command_storage[3];
+assign main_litedramcore_phaseinjector3_csrfield_wren = main_litedramcore_phaseinjector3_command_storage[4];
+assign main_litedramcore_phaseinjector3_csrfield_rden = main_litedramcore_phaseinjector3_command_storage[5];
+assign main_litedramcore_phaseinjector3_csrfield_cs_top = main_litedramcore_phaseinjector3_command_storage[6];
+assign main_litedramcore_phaseinjector3_csrfield_cs_bottom = main_litedramcore_phaseinjector3_command_storage[7];
+assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[7:0];
+assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[15:0];
+assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0];
+assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we;
+assign builder_adr = builder_interface1_adr;
+assign builder_we = builder_interface1_we;
+assign builder_dat_w = builder_interface1_dat_w;
+assign builder_interface1_dat_r = builder_dat_r;
+assign builder_interface0_bank_bus_adr = builder_adr;
+assign builder_interface1_bank_bus_adr = builder_adr;
+assign builder_interface2_bank_bus_adr = builder_adr;
+assign builder_interface0_bank_bus_we = builder_we;
+assign builder_interface1_bank_bus_we = builder_we;
+assign builder_interface2_bank_bus_we = builder_we;
+assign builder_interface0_bank_bus_dat_w = builder_dat_w;
+assign builder_interface1_bank_bus_dat_w = builder_dat_w;
+assign builder_interface2_bank_bus_dat_w = builder_dat_w;
+assign builder_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r);
+always @(*) begin
+    builder_rhs_self0 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[0];
         end
         1'd1: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[1];
         end
         2'd2: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[2];
         end
         2'd3: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[3];
         end
         3'd4: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[4];
         end
         3'd5: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[5];
         end
         3'd6: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[6];
         end
         default: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[7];
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed1 <= 16'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_rhs_self1 <= 16'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine0_cmd_payload_a;
         end
         1'd1: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine1_cmd_payload_a;
         end
         2'd2: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine2_cmd_payload_a;
         end
         2'd3: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine3_cmd_payload_a;
         end
         3'd4: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine4_cmd_payload_a;
         end
         3'd5: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine5_cmd_payload_a;
         end
         3'd6: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine6_cmd_payload_a;
         end
         default: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine7_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed2 <= 3'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_rhs_self2 <= 3'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine0_cmd_payload_ba;
         end
         1'd1: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine1_cmd_payload_ba;
         end
         2'd2: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine2_cmd_payload_ba;
         end
         2'd3: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine3_cmd_payload_ba;
         end
         3'd4: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine4_cmd_payload_ba;
         end
         3'd5: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine5_cmd_payload_ba;
         end
         3'd6: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine6_cmd_payload_ba;
         end
         default: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine7_cmd_payload_ba;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed3 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_rhs_self3 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine0_cmd_payload_is_read;
         end
         1'd1: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine1_cmd_payload_is_read;
         end
         2'd2: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine2_cmd_payload_is_read;
         end
         2'd3: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine3_cmd_payload_is_read;
         end
         3'd4: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine4_cmd_payload_is_read;
         end
         3'd5: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine5_cmd_payload_is_read;
         end
         3'd6: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine6_cmd_payload_is_read;
         end
         default: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed4 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_rhs_self4 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine0_cmd_payload_is_write;
         end
         1'd1: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine1_cmd_payload_is_write;
         end
         2'd2: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine2_cmd_payload_is_write;
         end
         2'd3: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine3_cmd_payload_is_write;
         end
         3'd4: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine4_cmd_payload_is_write;
         end
         3'd5: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine5_cmd_payload_is_write;
         end
         3'd6: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine6_cmd_payload_is_write;
         end
         default: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed5 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_rhs_self5 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd;
         end
         1'd1: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd;
         end
         2'd2: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd;
         end
         2'd3: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd;
         end
         3'd4: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd;
         end
         3'd5: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd;
         end
         3'd6: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd;
         end
         default: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed0 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_t_self0 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine0_cmd_payload_cas;
         end
         1'd1: begin
-            t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine1_cmd_payload_cas;
         end
         2'd2: begin
-            t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine2_cmd_payload_cas;
         end
         2'd3: begin
-            t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine3_cmd_payload_cas;
         end
         3'd4: begin
-            t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine4_cmd_payload_cas;
         end
         3'd5: begin
-            t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine5_cmd_payload_cas;
         end
         3'd6: begin
-            t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine6_cmd_payload_cas;
         end
         default: begin
-            t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine7_cmd_payload_cas;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed1 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_t_self1 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine0_cmd_payload_ras;
         end
         1'd1: begin
-            t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine1_cmd_payload_ras;
         end
         2'd2: begin
-            t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine2_cmd_payload_ras;
         end
         2'd3: begin
-            t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine3_cmd_payload_ras;
         end
         3'd4: begin
-            t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine4_cmd_payload_ras;
         end
         3'd5: begin
-            t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine5_cmd_payload_ras;
         end
         3'd6: begin
-            t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine6_cmd_payload_ras;
         end
         default: begin
-            t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine7_cmd_payload_ras;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed2 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_t_self2 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine0_cmd_payload_we;
         end
         1'd1: begin
-            t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine1_cmd_payload_we;
         end
         2'd2: begin
-            t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine2_cmd_payload_we;
         end
         2'd3: begin
-            t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine3_cmd_payload_we;
         end
         3'd4: begin
-            t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine4_cmd_payload_we;
         end
         3'd5: begin
-            t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine5_cmd_payload_we;
         end
         3'd6: begin
-            t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine6_cmd_payload_we;
         end
         default: begin
-            t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine7_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed6 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self6 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[0];
         end
         1'd1: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[1];
         end
         2'd2: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[2];
         end
         2'd3: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[3];
         end
         3'd4: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[4];
         end
         3'd5: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[5];
         end
         3'd6: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[6];
         end
         default: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[7];
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed7 <= 16'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self7 <= 16'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine0_cmd_payload_a;
         end
         1'd1: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine1_cmd_payload_a;
         end
         2'd2: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine2_cmd_payload_a;
         end
         2'd3: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine3_cmd_payload_a;
         end
         3'd4: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine4_cmd_payload_a;
         end
         3'd5: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine5_cmd_payload_a;
         end
         3'd6: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine6_cmd_payload_a;
         end
         default: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine7_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed8 <= 3'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self8 <= 3'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine0_cmd_payload_ba;
         end
         1'd1: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine1_cmd_payload_ba;
         end
         2'd2: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine2_cmd_payload_ba;
         end
         2'd3: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine3_cmd_payload_ba;
         end
         3'd4: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine4_cmd_payload_ba;
         end
         3'd5: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine5_cmd_payload_ba;
         end
         3'd6: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine6_cmd_payload_ba;
         end
         default: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine7_cmd_payload_ba;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed9 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self9 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine0_cmd_payload_is_read;
         end
         1'd1: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine1_cmd_payload_is_read;
         end
         2'd2: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine2_cmd_payload_is_read;
         end
         2'd3: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine3_cmd_payload_is_read;
         end
         3'd4: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine4_cmd_payload_is_read;
         end
         3'd5: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine5_cmd_payload_is_read;
         end
         3'd6: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine6_cmd_payload_is_read;
         end
         default: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed10 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self10 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine0_cmd_payload_is_write;
         end
         1'd1: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine1_cmd_payload_is_write;
         end
         2'd2: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine2_cmd_payload_is_write;
         end
         2'd3: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine3_cmd_payload_is_write;
         end
         3'd4: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine4_cmd_payload_is_write;
         end
         3'd5: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine5_cmd_payload_is_write;
         end
         3'd6: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine6_cmd_payload_is_write;
         end
         default: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed11 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self11 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd;
         end
         1'd1: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd;
         end
         2'd2: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd;
         end
         2'd3: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd;
         end
         3'd4: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd;
         end
         3'd5: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd;
         end
         3'd6: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd;
         end
         default: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed3 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_t_self3 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine0_cmd_payload_cas;
         end
         1'd1: begin
-            t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine1_cmd_payload_cas;
         end
         2'd2: begin
-            t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine2_cmd_payload_cas;
         end
         2'd3: begin
-            t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine3_cmd_payload_cas;
         end
         3'd4: begin
-            t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine4_cmd_payload_cas;
         end
         3'd5: begin
-            t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine5_cmd_payload_cas;
         end
         3'd6: begin
-            t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine6_cmd_payload_cas;
         end
         default: begin
-            t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine7_cmd_payload_cas;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed4 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_t_self4 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine0_cmd_payload_ras;
         end
         1'd1: begin
-            t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine1_cmd_payload_ras;
         end
         2'd2: begin
-            t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine2_cmd_payload_ras;
         end
         2'd3: begin
-            t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine3_cmd_payload_ras;
         end
         3'd4: begin
-            t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine4_cmd_payload_ras;
         end
         3'd5: begin
-            t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine5_cmd_payload_ras;
         end
         3'd6: begin
-            t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine6_cmd_payload_ras;
         end
         default: begin
-            t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine7_cmd_payload_ras;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed5 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_t_self5 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine0_cmd_payload_we;
         end
         1'd1: begin
-            t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine1_cmd_payload_we;
         end
         2'd2: begin
-            t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine2_cmd_payload_we;
         end
         2'd3: begin
-            t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine3_cmd_payload_we;
         end
         3'd4: begin
-            t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine4_cmd_payload_we;
         end
         3'd5: begin
-            t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine5_cmd_payload_we;
         end
         3'd6: begin
-            t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine6_cmd_payload_we;
         end
         default: begin
-            t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine7_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed12 <= 23'd0;
-    case (litedramcore_roundrobin0_grant)
+    builder_rhs_self12 <= 23'd0;
+    case (builder_roundrobin0_grant)
         default: begin
-            rhs_array_muxed12 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self12 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed13 <= 1'd0;
-    case (litedramcore_roundrobin0_grant)
+    builder_rhs_self13 <= 1'd0;
+    case (builder_roundrobin0_grant)
         default: begin
-            rhs_array_muxed13 <= user_port_cmd_payload_we;
+            builder_rhs_self13 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed14 <= 1'd0;
-    case (litedramcore_roundrobin0_grant)
+    builder_rhs_self14 <= 1'd0;
+    case (builder_roundrobin0_grant)
         default: begin
-            rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed15 <= 23'd0;
-    case (litedramcore_roundrobin1_grant)
+    builder_rhs_self15 <= 23'd0;
+    case (builder_roundrobin1_grant)
         default: begin
-            rhs_array_muxed15 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self15 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed16 <= 1'd0;
-    case (litedramcore_roundrobin1_grant)
+    builder_rhs_self16 <= 1'd0;
+    case (builder_roundrobin1_grant)
         default: begin
-            rhs_array_muxed16 <= user_port_cmd_payload_we;
+            builder_rhs_self16 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed17 <= 1'd0;
-    case (litedramcore_roundrobin1_grant)
+    builder_rhs_self17 <= 1'd0;
+    case (builder_roundrobin1_grant)
         default: begin
-            rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed18 <= 23'd0;
-    case (litedramcore_roundrobin2_grant)
+    builder_rhs_self18 <= 23'd0;
+    case (builder_roundrobin2_grant)
         default: begin
-            rhs_array_muxed18 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self18 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed19 <= 1'd0;
-    case (litedramcore_roundrobin2_grant)
+    builder_rhs_self19 <= 1'd0;
+    case (builder_roundrobin2_grant)
         default: begin
-            rhs_array_muxed19 <= user_port_cmd_payload_we;
+            builder_rhs_self19 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed20 <= 1'd0;
-    case (litedramcore_roundrobin2_grant)
+    builder_rhs_self20 <= 1'd0;
+    case (builder_roundrobin2_grant)
         default: begin
-            rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed21 <= 23'd0;
-    case (litedramcore_roundrobin3_grant)
+    builder_rhs_self21 <= 23'd0;
+    case (builder_roundrobin3_grant)
         default: begin
-            rhs_array_muxed21 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self21 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed22 <= 1'd0;
-    case (litedramcore_roundrobin3_grant)
+    builder_rhs_self22 <= 1'd0;
+    case (builder_roundrobin3_grant)
         default: begin
-            rhs_array_muxed22 <= user_port_cmd_payload_we;
+            builder_rhs_self22 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed23 <= 1'd0;
-    case (litedramcore_roundrobin3_grant)
+    builder_rhs_self23 <= 1'd0;
+    case (builder_roundrobin3_grant)
         default: begin
-            rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed24 <= 23'd0;
-    case (litedramcore_roundrobin4_grant)
+    builder_rhs_self24 <= 23'd0;
+    case (builder_roundrobin4_grant)
         default: begin
-            rhs_array_muxed24 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self24 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed25 <= 1'd0;
-    case (litedramcore_roundrobin4_grant)
+    builder_rhs_self25 <= 1'd0;
+    case (builder_roundrobin4_grant)
         default: begin
-            rhs_array_muxed25 <= user_port_cmd_payload_we;
+            builder_rhs_self25 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed26 <= 1'd0;
-    case (litedramcore_roundrobin4_grant)
+    builder_rhs_self26 <= 1'd0;
+    case (builder_roundrobin4_grant)
         default: begin
-            rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed27 <= 23'd0;
-    case (litedramcore_roundrobin5_grant)
+    builder_rhs_self27 <= 23'd0;
+    case (builder_roundrobin5_grant)
         default: begin
-            rhs_array_muxed27 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self27 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed28 <= 1'd0;
-    case (litedramcore_roundrobin5_grant)
+    builder_rhs_self28 <= 1'd0;
+    case (builder_roundrobin5_grant)
         default: begin
-            rhs_array_muxed28 <= user_port_cmd_payload_we;
+            builder_rhs_self28 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed29 <= 1'd0;
-    case (litedramcore_roundrobin5_grant)
+    builder_rhs_self29 <= 1'd0;
+    case (builder_roundrobin5_grant)
         default: begin
-            rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed30 <= 23'd0;
-    case (litedramcore_roundrobin6_grant)
+    builder_rhs_self30 <= 23'd0;
+    case (builder_roundrobin6_grant)
         default: begin
-            rhs_array_muxed30 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self30 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed31 <= 1'd0;
-    case (litedramcore_roundrobin6_grant)
+    builder_rhs_self31 <= 1'd0;
+    case (builder_roundrobin6_grant)
         default: begin
-            rhs_array_muxed31 <= user_port_cmd_payload_we;
+            builder_rhs_self31 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed32 <= 1'd0;
-    case (litedramcore_roundrobin6_grant)
+    builder_rhs_self32 <= 1'd0;
+    case (builder_roundrobin6_grant)
         default: begin
-            rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed33 <= 23'd0;
-    case (litedramcore_roundrobin7_grant)
+    builder_rhs_self33 <= 23'd0;
+    case (builder_roundrobin7_grant)
         default: begin
-            rhs_array_muxed33 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self33 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed34 <= 1'd0;
-    case (litedramcore_roundrobin7_grant)
+    builder_rhs_self34 <= 1'd0;
+    case (builder_roundrobin7_grant)
         default: begin
-            rhs_array_muxed34 <= user_port_cmd_payload_we;
+            builder_rhs_self34 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed35 <= 1'd0;
-    case (litedramcore_roundrobin7_grant)
+    builder_rhs_self35 <= 1'd0;
+    case (builder_roundrobin7_grant)
         default: begin
-            rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    array_muxed0 <= 3'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self0 <= 3'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed0 <= litedramcore_nop_ba[2:0];
+            builder_self0 <= main_litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed1 <= 16'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self1 <= 16'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed1 <= litedramcore_nop_a;
+            builder_self1 <= main_litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
+            builder_self1 <= main_litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
+            builder_self1 <= main_litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed1 <= litedramcore_cmd_payload_a;
+            builder_self1 <= main_litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed2 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self2 <= 1'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed2 <= 1'd0;
+            builder_self2 <= 1'd0;
         end
         1'd1: begin
-            array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+            builder_self2 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+            builder_self2 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+            builder_self2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed3 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self3 <= 1'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed3 <= 1'd0;
+            builder_self3 <= 1'd0;
         end
         1'd1: begin
-            array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+            builder_self3 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+            builder_self3 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+            builder_self3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed4 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self4 <= 1'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed4 <= 1'd0;
+            builder_self4 <= 1'd0;
         end
         1'd1: begin
-            array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+            builder_self4 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+            builder_self4 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+            builder_self4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed5 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self5 <= 1'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed5 <= 1'd0;
+            builder_self5 <= 1'd0;
         end
         1'd1: begin
-            array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+            builder_self5 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+            builder_self5 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+            builder_self5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed6 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self6 <= 1'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed6 <= 1'd0;
+            builder_self6 <= 1'd0;
         end
         1'd1: begin
-            array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+            builder_self6 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+            builder_self6 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+            builder_self6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
         end
     endcase
 end
 always @(*) begin
-    array_muxed7 <= 3'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self7 <= 3'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed7 <= litedramcore_nop_ba[2:0];
+            builder_self7 <= main_litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed8 <= 16'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self8 <= 16'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed8 <= litedramcore_nop_a;
+            builder_self8 <= main_litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
+            builder_self8 <= main_litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
+            builder_self8 <= main_litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed8 <= litedramcore_cmd_payload_a;
+            builder_self8 <= main_litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed9 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self9 <= 1'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed9 <= 1'd0;
+            builder_self9 <= 1'd0;
         end
         1'd1: begin
-            array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+            builder_self9 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+            builder_self9 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+            builder_self9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed10 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self10 <= 1'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed10 <= 1'd0;
+            builder_self10 <= 1'd0;
         end
         1'd1: begin
-            array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+            builder_self10 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+            builder_self10 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+            builder_self10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed11 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self11 <= 1'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed11 <= 1'd0;
+            builder_self11 <= 1'd0;
         end
         1'd1: begin
-            array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+            builder_self11 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+            builder_self11 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+            builder_self11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed12 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self12 <= 1'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed12 <= 1'd0;
+            builder_self12 <= 1'd0;
         end
         1'd1: begin
-            array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+            builder_self12 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+            builder_self12 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+            builder_self12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed13 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self13 <= 1'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed13 <= 1'd0;
+            builder_self13 <= 1'd0;
         end
         1'd1: begin
-            array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+            builder_self13 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+            builder_self13 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+            builder_self13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
         end
     endcase
 end
 always @(*) begin
-    array_muxed14 <= 3'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self14 <= 3'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed14 <= litedramcore_nop_ba[2:0];
+            builder_self14 <= main_litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed14 <= litedramcore_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed15 <= 16'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self15 <= 16'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed15 <= litedramcore_nop_a;
+            builder_self15 <= main_litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a;
+            builder_self15 <= main_litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed15 <= litedramcore_choose_req_cmd_payload_a;
+            builder_self15 <= main_litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed15 <= litedramcore_cmd_payload_a;
+            builder_self15 <= main_litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed16 <= 1'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self16 <= 1'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed16 <= 1'd0;
+            builder_self16 <= 1'd0;
         end
         1'd1: begin
-            array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+            builder_self16 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+            builder_self16 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+            builder_self16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed17 <= 1'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self17 <= 1'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed17 <= 1'd0;
+            builder_self17 <= 1'd0;
         end
         1'd1: begin
-            array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+            builder_self17 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+            builder_self17 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+            builder_self17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed18 <= 1'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self18 <= 1'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed18 <= 1'd0;
+            builder_self18 <= 1'd0;
         end
         1'd1: begin
-            array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+            builder_self18 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+            builder_self18 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+            builder_self18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed19 <= 1'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self19 <= 1'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed19 <= 1'd0;
+            builder_self19 <= 1'd0;
         end
         1'd1: begin
-            array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+            builder_self19 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+            builder_self19 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+            builder_self19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed20 <= 1'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self20 <= 1'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed20 <= 1'd0;
+            builder_self20 <= 1'd0;
         end
         1'd1: begin
-            array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+            builder_self20 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+            builder_self20 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+            builder_self20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
         end
     endcase
 end
 always @(*) begin
-    array_muxed21 <= 3'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self21 <= 3'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed21 <= litedramcore_nop_ba[2:0];
+            builder_self21 <= main_litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed21 <= litedramcore_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed22 <= 16'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self22 <= 16'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed22 <= litedramcore_nop_a;
+            builder_self22 <= main_litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a;
+            builder_self22 <= main_litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed22 <= litedramcore_choose_req_cmd_payload_a;
+            builder_self22 <= main_litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed22 <= litedramcore_cmd_payload_a;
+            builder_self22 <= main_litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed23 <= 1'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self23 <= 1'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed23 <= 1'd0;
+            builder_self23 <= 1'd0;
         end
         1'd1: begin
-            array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+            builder_self23 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+            builder_self23 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+            builder_self23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed24 <= 1'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self24 <= 1'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed24 <= 1'd0;
+            builder_self24 <= 1'd0;
         end
         1'd1: begin
-            array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+            builder_self24 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+            builder_self24 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+            builder_self24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed25 <= 1'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self25 <= 1'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed25 <= 1'd0;
+            builder_self25 <= 1'd0;
         end
         1'd1: begin
-            array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+            builder_self25 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+            builder_self25 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+            builder_self25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed26 <= 1'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self26 <= 1'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed26 <= 1'd0;
+            builder_self26 <= 1'd0;
         end
         1'd1: begin
-            array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+            builder_self26 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+            builder_self26 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+            builder_self26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed27 <= 1'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self27 <= 1'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed27 <= 1'd0;
+            builder_self27 <= 1'd0;
         end
         1'd1: begin
-            array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+            builder_self27 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+            builder_self27 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+            builder_self27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
         end
     endcase
 end
-assign xilinxasyncresetsynchronizerimpl0 = (~locked);
-assign xilinxasyncresetsynchronizerimpl1 = (~locked);
-assign xilinxasyncresetsynchronizerimpl2 = (~locked);
-assign xilinxasyncresetsynchronizerimpl3 = (~locked);
+assign builder_xilinxasyncresetsynchronizerimpl0_async_reset = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl1_async_reset = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl2_async_reset = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl3_async_reset = (~main_locked);
 
 
 //------------------------------------------------------------------------------
@@ -11983,1044 +12400,1044 @@ assign xilinxasyncresetsynchronizerimpl3 = (~locked);
 //------------------------------------------------------------------------------
 
 always @(posedge iodelay_clk) begin
-    if ((reset_counter != 1'd0)) begin
-        reset_counter <= (reset_counter - 1'd1);
+    if ((main_reset_counter != 1'd0)) begin
+        main_reset_counter <= (main_reset_counter - 1'd1);
     end else begin
-        ic_reset <= 1'd0;
+        main_ic_reset <= 1'd0;
     end
     if (iodelay_rst) begin
-        reset_counter <= 4'd15;
-        ic_reset <= 1'd1;
+        main_reset_counter <= 4'd15;
+        main_ic_reset <= 1'd1;
     end
 end
 
 always @(posedge sys_clk) begin
-    a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline;
-    a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
-    a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0;
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1);
+    main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline;
+    main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
+    main_a7ddrphy_dqspattern_o1 <= main_a7ddrphy_dqspattern_o0;
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip0_value0 <= (main_a7ddrphy_bitslip0_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip0_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip0_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1);
+    main_a7ddrphy_bitslip0_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip0_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip1_value0 <= (main_a7ddrphy_bitslip1_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip1_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip1_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1);
+    main_a7ddrphy_bitslip1_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip1_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip0_value1 <= (main_a7ddrphy_bitslip0_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip0_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip0_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1);
+    main_a7ddrphy_bitslip0_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[2], main_a7ddrphy_dfi_p3_wrdata_mask[0], main_a7ddrphy_dfi_p2_wrdata_mask[2], main_a7ddrphy_dfi_p2_wrdata_mask[0], main_a7ddrphy_dfi_p1_wrdata_mask[2], main_a7ddrphy_dfi_p1_wrdata_mask[0], main_a7ddrphy_dfi_p0_wrdata_mask[2], main_a7ddrphy_dfi_p0_wrdata_mask[0]}, main_a7ddrphy_bitslip0_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip1_value1 <= (main_a7ddrphy_bitslip1_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip1_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip1_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]};
-    a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline;
-    a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1);
+    main_a7ddrphy_bitslip1_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[3], main_a7ddrphy_dfi_p3_wrdata_mask[1], main_a7ddrphy_dfi_p2_wrdata_mask[3], main_a7ddrphy_dfi_p2_wrdata_mask[1], main_a7ddrphy_dfi_p1_wrdata_mask[3], main_a7ddrphy_dfi_p1_wrdata_mask[1], main_a7ddrphy_dfi_p0_wrdata_mask[3], main_a7ddrphy_dfi_p0_wrdata_mask[1]}, main_a7ddrphy_bitslip1_r1[15:8]};
+    main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dq_oe_delay_tappeddelayline;
+    main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip0_value2 <= (main_a7ddrphy_bitslip0_value2 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip0_value2 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip0_value2 <= 3'd7;
     end
-    a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1);
+    main_a7ddrphy_bitslip0_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[16], main_a7ddrphy_dfi_p3_wrdata[0], main_a7ddrphy_dfi_p2_wrdata[16], main_a7ddrphy_dfi_p2_wrdata[0], main_a7ddrphy_dfi_p1_wrdata[16], main_a7ddrphy_dfi_p1_wrdata[0], main_a7ddrphy_dfi_p0_wrdata[16], main_a7ddrphy_dfi_p0_wrdata[0]}, main_a7ddrphy_bitslip0_r2[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip0_value3 <= (main_a7ddrphy_bitslip0_value3 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip0_value3 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip0_value3 <= 3'd7;
     end
-    a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1);
+    main_a7ddrphy_bitslip0_r3 <= {main_a7ddrphy_bitslip03, main_a7ddrphy_bitslip0_r3[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip1_value2 <= (main_a7ddrphy_bitslip1_value2 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip1_value2 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip1_value2 <= 3'd7;
     end
-    a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1);
+    main_a7ddrphy_bitslip1_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[17], main_a7ddrphy_dfi_p3_wrdata[1], main_a7ddrphy_dfi_p2_wrdata[17], main_a7ddrphy_dfi_p2_wrdata[1], main_a7ddrphy_dfi_p1_wrdata[17], main_a7ddrphy_dfi_p1_wrdata[1], main_a7ddrphy_dfi_p0_wrdata[17], main_a7ddrphy_dfi_p0_wrdata[1]}, main_a7ddrphy_bitslip1_r2[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip1_value3 <= (main_a7ddrphy_bitslip1_value3 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip1_value3 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip1_value3 <= 3'd7;
     end
-    a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1);
+    main_a7ddrphy_bitslip1_r3 <= {main_a7ddrphy_bitslip13, main_a7ddrphy_bitslip1_r3[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip2_value0 <= (main_a7ddrphy_bitslip2_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip2_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip2_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1);
+    main_a7ddrphy_bitslip2_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[18], main_a7ddrphy_dfi_p3_wrdata[2], main_a7ddrphy_dfi_p2_wrdata[18], main_a7ddrphy_dfi_p2_wrdata[2], main_a7ddrphy_dfi_p1_wrdata[18], main_a7ddrphy_dfi_p1_wrdata[2], main_a7ddrphy_dfi_p0_wrdata[18], main_a7ddrphy_dfi_p0_wrdata[2]}, main_a7ddrphy_bitslip2_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip2_value1 <= (main_a7ddrphy_bitslip2_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip2_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip2_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1);
+    main_a7ddrphy_bitslip2_r1 <= {main_a7ddrphy_bitslip21, main_a7ddrphy_bitslip2_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip3_value0 <= (main_a7ddrphy_bitslip3_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip3_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip3_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1);
+    main_a7ddrphy_bitslip3_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[19], main_a7ddrphy_dfi_p3_wrdata[3], main_a7ddrphy_dfi_p2_wrdata[19], main_a7ddrphy_dfi_p2_wrdata[3], main_a7ddrphy_dfi_p1_wrdata[19], main_a7ddrphy_dfi_p1_wrdata[3], main_a7ddrphy_dfi_p0_wrdata[19], main_a7ddrphy_dfi_p0_wrdata[3]}, main_a7ddrphy_bitslip3_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip3_value1 <= (main_a7ddrphy_bitslip3_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip3_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip3_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1);
+    main_a7ddrphy_bitslip3_r1 <= {main_a7ddrphy_bitslip31, main_a7ddrphy_bitslip3_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip4_value0 <= (main_a7ddrphy_bitslip4_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip4_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip4_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1);
+    main_a7ddrphy_bitslip4_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[20], main_a7ddrphy_dfi_p3_wrdata[4], main_a7ddrphy_dfi_p2_wrdata[20], main_a7ddrphy_dfi_p2_wrdata[4], main_a7ddrphy_dfi_p1_wrdata[20], main_a7ddrphy_dfi_p1_wrdata[4], main_a7ddrphy_dfi_p0_wrdata[20], main_a7ddrphy_dfi_p0_wrdata[4]}, main_a7ddrphy_bitslip4_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip4_value1 <= (main_a7ddrphy_bitslip4_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip4_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip4_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1);
+    main_a7ddrphy_bitslip4_r1 <= {main_a7ddrphy_bitslip41, main_a7ddrphy_bitslip4_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip5_value0 <= (main_a7ddrphy_bitslip5_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip5_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip5_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1);
+    main_a7ddrphy_bitslip5_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[21], main_a7ddrphy_dfi_p3_wrdata[5], main_a7ddrphy_dfi_p2_wrdata[21], main_a7ddrphy_dfi_p2_wrdata[5], main_a7ddrphy_dfi_p1_wrdata[21], main_a7ddrphy_dfi_p1_wrdata[5], main_a7ddrphy_dfi_p0_wrdata[21], main_a7ddrphy_dfi_p0_wrdata[5]}, main_a7ddrphy_bitslip5_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip5_value1 <= (main_a7ddrphy_bitslip5_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip5_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip5_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1);
+    main_a7ddrphy_bitslip5_r1 <= {main_a7ddrphy_bitslip51, main_a7ddrphy_bitslip5_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip6_value0 <= (main_a7ddrphy_bitslip6_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip6_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip6_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1);
+    main_a7ddrphy_bitslip6_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[22], main_a7ddrphy_dfi_p3_wrdata[6], main_a7ddrphy_dfi_p2_wrdata[22], main_a7ddrphy_dfi_p2_wrdata[6], main_a7ddrphy_dfi_p1_wrdata[22], main_a7ddrphy_dfi_p1_wrdata[6], main_a7ddrphy_dfi_p0_wrdata[22], main_a7ddrphy_dfi_p0_wrdata[6]}, main_a7ddrphy_bitslip6_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip6_value1 <= (main_a7ddrphy_bitslip6_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip6_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip6_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1);
+    main_a7ddrphy_bitslip6_r1 <= {main_a7ddrphy_bitslip61, main_a7ddrphy_bitslip6_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip7_value0 <= (main_a7ddrphy_bitslip7_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip7_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip7_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1);
+    main_a7ddrphy_bitslip7_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[23], main_a7ddrphy_dfi_p3_wrdata[7], main_a7ddrphy_dfi_p2_wrdata[23], main_a7ddrphy_dfi_p2_wrdata[7], main_a7ddrphy_dfi_p1_wrdata[23], main_a7ddrphy_dfi_p1_wrdata[7], main_a7ddrphy_dfi_p0_wrdata[23], main_a7ddrphy_dfi_p0_wrdata[7]}, main_a7ddrphy_bitslip7_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip7_value1 <= (main_a7ddrphy_bitslip7_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip7_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip7_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1);
+    main_a7ddrphy_bitslip7_r1 <= {main_a7ddrphy_bitslip71, main_a7ddrphy_bitslip7_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip8_value0 <= (main_a7ddrphy_bitslip8_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip8_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip8_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1);
+    main_a7ddrphy_bitslip8_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[24], main_a7ddrphy_dfi_p3_wrdata[8], main_a7ddrphy_dfi_p2_wrdata[24], main_a7ddrphy_dfi_p2_wrdata[8], main_a7ddrphy_dfi_p1_wrdata[24], main_a7ddrphy_dfi_p1_wrdata[8], main_a7ddrphy_dfi_p0_wrdata[24], main_a7ddrphy_dfi_p0_wrdata[8]}, main_a7ddrphy_bitslip8_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip8_value1 <= (main_a7ddrphy_bitslip8_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip8_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip8_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1);
+    main_a7ddrphy_bitslip8_r1 <= {main_a7ddrphy_bitslip81, main_a7ddrphy_bitslip8_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip9_value0 <= (main_a7ddrphy_bitslip9_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip9_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip9_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1);
+    main_a7ddrphy_bitslip9_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[25], main_a7ddrphy_dfi_p3_wrdata[9], main_a7ddrphy_dfi_p2_wrdata[25], main_a7ddrphy_dfi_p2_wrdata[9], main_a7ddrphy_dfi_p1_wrdata[25], main_a7ddrphy_dfi_p1_wrdata[9], main_a7ddrphy_dfi_p0_wrdata[25], main_a7ddrphy_dfi_p0_wrdata[9]}, main_a7ddrphy_bitslip9_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip9_value1 <= (main_a7ddrphy_bitslip9_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip9_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip9_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1);
+    main_a7ddrphy_bitslip9_r1 <= {main_a7ddrphy_bitslip91, main_a7ddrphy_bitslip9_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip10_value0 <= (main_a7ddrphy_bitslip10_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip10_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip10_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1);
+    main_a7ddrphy_bitslip10_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[26], main_a7ddrphy_dfi_p3_wrdata[10], main_a7ddrphy_dfi_p2_wrdata[26], main_a7ddrphy_dfi_p2_wrdata[10], main_a7ddrphy_dfi_p1_wrdata[26], main_a7ddrphy_dfi_p1_wrdata[10], main_a7ddrphy_dfi_p0_wrdata[26], main_a7ddrphy_dfi_p0_wrdata[10]}, main_a7ddrphy_bitslip10_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip10_value1 <= (main_a7ddrphy_bitslip10_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip10_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip10_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1);
+    main_a7ddrphy_bitslip10_r1 <= {main_a7ddrphy_bitslip101, main_a7ddrphy_bitslip10_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip11_value0 <= (main_a7ddrphy_bitslip11_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip11_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip11_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1);
+    main_a7ddrphy_bitslip11_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[27], main_a7ddrphy_dfi_p3_wrdata[11], main_a7ddrphy_dfi_p2_wrdata[27], main_a7ddrphy_dfi_p2_wrdata[11], main_a7ddrphy_dfi_p1_wrdata[27], main_a7ddrphy_dfi_p1_wrdata[11], main_a7ddrphy_dfi_p0_wrdata[27], main_a7ddrphy_dfi_p0_wrdata[11]}, main_a7ddrphy_bitslip11_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip11_value1 <= (main_a7ddrphy_bitslip11_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip11_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip11_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1);
+    main_a7ddrphy_bitslip11_r1 <= {main_a7ddrphy_bitslip111, main_a7ddrphy_bitslip11_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip12_value0 <= (main_a7ddrphy_bitslip12_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip12_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip12_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1);
+    main_a7ddrphy_bitslip12_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[28], main_a7ddrphy_dfi_p3_wrdata[12], main_a7ddrphy_dfi_p2_wrdata[28], main_a7ddrphy_dfi_p2_wrdata[12], main_a7ddrphy_dfi_p1_wrdata[28], main_a7ddrphy_dfi_p1_wrdata[12], main_a7ddrphy_dfi_p0_wrdata[28], main_a7ddrphy_dfi_p0_wrdata[12]}, main_a7ddrphy_bitslip12_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip12_value1 <= (main_a7ddrphy_bitslip12_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip12_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip12_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1);
+    main_a7ddrphy_bitslip12_r1 <= {main_a7ddrphy_bitslip121, main_a7ddrphy_bitslip12_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip13_value0 <= (main_a7ddrphy_bitslip13_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip13_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip13_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1);
+    main_a7ddrphy_bitslip13_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[29], main_a7ddrphy_dfi_p3_wrdata[13], main_a7ddrphy_dfi_p2_wrdata[29], main_a7ddrphy_dfi_p2_wrdata[13], main_a7ddrphy_dfi_p1_wrdata[29], main_a7ddrphy_dfi_p1_wrdata[13], main_a7ddrphy_dfi_p0_wrdata[29], main_a7ddrphy_dfi_p0_wrdata[13]}, main_a7ddrphy_bitslip13_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip13_value1 <= (main_a7ddrphy_bitslip13_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip13_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip13_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1);
+    main_a7ddrphy_bitslip13_r1 <= {main_a7ddrphy_bitslip131, main_a7ddrphy_bitslip13_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip14_value0 <= (main_a7ddrphy_bitslip14_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip14_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip14_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1);
+    main_a7ddrphy_bitslip14_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[30], main_a7ddrphy_dfi_p3_wrdata[14], main_a7ddrphy_dfi_p2_wrdata[30], main_a7ddrphy_dfi_p2_wrdata[14], main_a7ddrphy_dfi_p1_wrdata[30], main_a7ddrphy_dfi_p1_wrdata[14], main_a7ddrphy_dfi_p0_wrdata[30], main_a7ddrphy_dfi_p0_wrdata[14]}, main_a7ddrphy_bitslip14_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip14_value1 <= (main_a7ddrphy_bitslip14_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip14_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip14_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1);
+    main_a7ddrphy_bitslip14_r1 <= {main_a7ddrphy_bitslip141, main_a7ddrphy_bitslip14_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip15_value0 <= (main_a7ddrphy_bitslip15_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip15_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip15_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1);
+    main_a7ddrphy_bitslip15_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[31], main_a7ddrphy_dfi_p3_wrdata[15], main_a7ddrphy_dfi_p2_wrdata[31], main_a7ddrphy_dfi_p2_wrdata[15], main_a7ddrphy_dfi_p1_wrdata[31], main_a7ddrphy_dfi_p1_wrdata[15], main_a7ddrphy_dfi_p0_wrdata[31], main_a7ddrphy_dfi_p0_wrdata[15]}, main_a7ddrphy_bitslip15_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip15_value1 <= (main_a7ddrphy_bitslip15_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip15_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip15_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]};
-    a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en);
-    a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0;
-    a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1;
-    a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2;
-    a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3;
-    a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4;
-    a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5;
-    a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6;
-    a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en);
-    a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0;
-    a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1;
-    if (litedramcore_csr_dfi_p0_rddata_valid) begin
-        litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata;
+    main_a7ddrphy_bitslip15_r1 <= {main_a7ddrphy_bitslip151, main_a7ddrphy_bitslip15_r1[15:8]};
+    main_a7ddrphy_rddata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_rddata_en | main_a7ddrphy_dfi_p1_rddata_en) | main_a7ddrphy_dfi_p2_rddata_en) | main_a7ddrphy_dfi_p3_rddata_en);
+    main_a7ddrphy_rddata_en_tappeddelayline1 <= main_a7ddrphy_rddata_en_tappeddelayline0;
+    main_a7ddrphy_rddata_en_tappeddelayline2 <= main_a7ddrphy_rddata_en_tappeddelayline1;
+    main_a7ddrphy_rddata_en_tappeddelayline3 <= main_a7ddrphy_rddata_en_tappeddelayline2;
+    main_a7ddrphy_rddata_en_tappeddelayline4 <= main_a7ddrphy_rddata_en_tappeddelayline3;
+    main_a7ddrphy_rddata_en_tappeddelayline5 <= main_a7ddrphy_rddata_en_tappeddelayline4;
+    main_a7ddrphy_rddata_en_tappeddelayline6 <= main_a7ddrphy_rddata_en_tappeddelayline5;
+    main_a7ddrphy_rddata_en_tappeddelayline7 <= main_a7ddrphy_rddata_en_tappeddelayline6;
+    main_a7ddrphy_wrdata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_wrdata_en | main_a7ddrphy_dfi_p1_wrdata_en) | main_a7ddrphy_dfi_p2_wrdata_en) | main_a7ddrphy_dfi_p3_wrdata_en);
+    main_a7ddrphy_wrdata_en_tappeddelayline1 <= main_a7ddrphy_wrdata_en_tappeddelayline0;
+    main_a7ddrphy_wrdata_en_tappeddelayline2 <= main_a7ddrphy_wrdata_en_tappeddelayline1;
+    if (main_litedramcore_csr_dfi_p0_rddata_valid) begin
+        main_litedramcore_phaseinjector0_rddata_status <= main_litedramcore_csr_dfi_p0_rddata;
     end
-    if (litedramcore_csr_dfi_p1_rddata_valid) begin
-        litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata;
+    if (main_litedramcore_csr_dfi_p1_rddata_valid) begin
+        main_litedramcore_phaseinjector1_rddata_status <= main_litedramcore_csr_dfi_p1_rddata;
     end
-    if (litedramcore_csr_dfi_p2_rddata_valid) begin
-        litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata;
+    if (main_litedramcore_csr_dfi_p2_rddata_valid) begin
+        main_litedramcore_phaseinjector2_rddata_status <= main_litedramcore_csr_dfi_p2_rddata;
     end
-    if (litedramcore_csr_dfi_p3_rddata_valid) begin
-        litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata;
+    if (main_litedramcore_csr_dfi_p3_rddata_valid) begin
+        main_litedramcore_phaseinjector3_rddata_status <= main_litedramcore_csr_dfi_p3_rddata;
     end
-    if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
-        litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
+    if ((main_litedramcore_timer_wait & (~main_litedramcore_timer_done0))) begin
+        main_litedramcore_timer_count1 <= (main_litedramcore_timer_count1 - 1'd1);
     end else begin
-        litedramcore_timer_count1 <= 10'd781;
+        main_litedramcore_timer_count1 <= 10'd781;
     end
-    litedramcore_postponer_req_o <= 1'd0;
-    if (litedramcore_postponer_req_i) begin
-        litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
-        if ((litedramcore_postponer_count == 1'd0)) begin
-            litedramcore_postponer_count <= 1'd0;
-            litedramcore_postponer_req_o <= 1'd1;
+    main_litedramcore_postponer_req_o <= 1'd0;
+    if (main_litedramcore_postponer_req_i) begin
+        main_litedramcore_postponer_count <= (main_litedramcore_postponer_count - 1'd1);
+        if ((main_litedramcore_postponer_count == 1'd0)) begin
+            main_litedramcore_postponer_count <= 1'd0;
+            main_litedramcore_postponer_req_o <= 1'd1;
         end
     end
-    if (litedramcore_sequencer_start0) begin
-        litedramcore_sequencer_count <= 1'd0;
+    if (main_litedramcore_sequencer_start0) begin
+        main_litedramcore_sequencer_count <= 1'd0;
     end else begin
-        if (litedramcore_sequencer_done1) begin
-            if ((litedramcore_sequencer_count != 1'd0)) begin
-                litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
-            end
-        end
-    end
-    litedramcore_cmd_payload_a <= 1'd0;
-    litedramcore_cmd_payload_ba <= 1'd0;
-    litedramcore_cmd_payload_cas <= 1'd0;
-    litedramcore_cmd_payload_ras <= 1'd0;
-    litedramcore_cmd_payload_we <= 1'd0;
-    litedramcore_sequencer_done1 <= 1'd0;
-    if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
-        litedramcore_cmd_payload_a <= 11'd1024;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd1;
-        litedramcore_cmd_payload_we <= 1'd1;
-    end
-    if ((litedramcore_sequencer_counter == 2'd3)) begin
-        litedramcore_cmd_payload_a <= 11'd1024;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd1;
-        litedramcore_cmd_payload_ras <= 1'd1;
-        litedramcore_cmd_payload_we <= 1'd0;
-    end
-    if ((litedramcore_sequencer_counter == 7'd73)) begin
-        litedramcore_cmd_payload_a <= 1'd0;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd0;
-        litedramcore_cmd_payload_we <= 1'd0;
-        litedramcore_sequencer_done1 <= 1'd1;
-    end
-    if ((litedramcore_sequencer_counter == 7'd73)) begin
-        litedramcore_sequencer_counter <= 1'd0;
+        if (main_litedramcore_sequencer_done1) begin
+            if ((main_litedramcore_sequencer_count != 1'd0)) begin
+                main_litedramcore_sequencer_count <= (main_litedramcore_sequencer_count - 1'd1);
+            end
+        end
+    end
+    main_litedramcore_cmd_payload_a <= 1'd0;
+    main_litedramcore_cmd_payload_ba <= 1'd0;
+    main_litedramcore_cmd_payload_cas <= 1'd0;
+    main_litedramcore_cmd_payload_ras <= 1'd0;
+    main_litedramcore_cmd_payload_we <= 1'd0;
+    main_litedramcore_sequencer_done1 <= 1'd0;
+    if ((main_litedramcore_sequencer_start1 & (main_litedramcore_sequencer_trigger == 1'd0))) begin
+        main_litedramcore_cmd_payload_a <= 11'd1024;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd1;
+        main_litedramcore_cmd_payload_we <= 1'd1;
+    end
+    if ((main_litedramcore_sequencer_trigger == 2'd3)) begin
+        main_litedramcore_cmd_payload_a <= 11'd1024;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd1;
+        main_litedramcore_cmd_payload_ras <= 1'd1;
+        main_litedramcore_cmd_payload_we <= 1'd0;
+    end
+    if ((main_litedramcore_sequencer_trigger == 7'd73)) begin
+        main_litedramcore_cmd_payload_a <= 1'd0;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd0;
+        main_litedramcore_cmd_payload_we <= 1'd0;
+        main_litedramcore_sequencer_done1 <= 1'd1;
+    end
+    if ((main_litedramcore_sequencer_trigger == 7'd73)) begin
+        main_litedramcore_sequencer_trigger <= 1'd0;
     end else begin
-        if ((litedramcore_sequencer_counter != 1'd0)) begin
-            litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
+        if ((main_litedramcore_sequencer_trigger != 1'd0)) begin
+            main_litedramcore_sequencer_trigger <= (main_litedramcore_sequencer_trigger + 1'd1);
         end else begin
-            if (litedramcore_sequencer_start1) begin
-                litedramcore_sequencer_counter <= 1'd1;
+            if (main_litedramcore_sequencer_start1) begin
+                main_litedramcore_sequencer_trigger <= 1'd1;
             end
         end
     end
-    if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
-        litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
+    if ((main_litedramcore_zqcs_timer_wait & (~main_litedramcore_zqcs_timer_done0))) begin
+        main_litedramcore_zqcs_timer_count1 <= (main_litedramcore_zqcs_timer_count1 - 1'd1);
     end else begin
-        litedramcore_zqcs_timer_count1 <= 27'd99999999;
-    end
-    litedramcore_zqcs_executer_done <= 1'd0;
-    if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
-        litedramcore_cmd_payload_a <= 11'd1024;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd1;
-        litedramcore_cmd_payload_we <= 1'd1;
-    end
-    if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
-        litedramcore_cmd_payload_a <= 1'd0;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd0;
-        litedramcore_cmd_payload_we <= 1'd1;
-    end
-    if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
-        litedramcore_cmd_payload_a <= 1'd0;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd0;
-        litedramcore_cmd_payload_we <= 1'd0;
-        litedramcore_zqcs_executer_done <= 1'd1;
-    end
-    if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
-        litedramcore_zqcs_executer_counter <= 1'd0;
+        main_litedramcore_zqcs_timer_count1 <= 27'd99999999;
+    end
+    main_litedramcore_zqcs_executer_done <= 1'd0;
+    if ((main_litedramcore_zqcs_executer_start & (main_litedramcore_zqcs_executer_trigger == 1'd0))) begin
+        main_litedramcore_cmd_payload_a <= 11'd1024;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd1;
+        main_litedramcore_cmd_payload_we <= 1'd1;
+    end
+    if ((main_litedramcore_zqcs_executer_trigger == 2'd3)) begin
+        main_litedramcore_cmd_payload_a <= 1'd0;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd0;
+        main_litedramcore_cmd_payload_we <= 1'd1;
+    end
+    if ((main_litedramcore_zqcs_executer_trigger == 5'd19)) begin
+        main_litedramcore_cmd_payload_a <= 1'd0;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd0;
+        main_litedramcore_cmd_payload_we <= 1'd0;
+        main_litedramcore_zqcs_executer_done <= 1'd1;
+    end
+    if ((main_litedramcore_zqcs_executer_trigger == 5'd19)) begin
+        main_litedramcore_zqcs_executer_trigger <= 1'd0;
     end else begin
-        if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
-            litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
+        if ((main_litedramcore_zqcs_executer_trigger != 1'd0)) begin
+            main_litedramcore_zqcs_executer_trigger <= (main_litedramcore_zqcs_executer_trigger + 1'd1);
         end else begin
-            if (litedramcore_zqcs_executer_start) begin
-                litedramcore_zqcs_executer_counter <= 1'd1;
+            if (main_litedramcore_zqcs_executer_start) begin
+                main_litedramcore_zqcs_executer_trigger <= 1'd1;
             end
         end
     end
-    litedramcore_refresher_state <= litedramcore_refresher_next_state;
-    if (litedramcore_bankmachine0_row_close) begin
-        litedramcore_bankmachine0_row_opened <= 1'd0;
+    builder_refresher_state <= builder_refresher_next_state;
+    if (main_litedramcore_bankmachine0_row_close) begin
+        main_litedramcore_bankmachine0_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine0_row_open) begin
-            litedramcore_bankmachine0_row_opened <= 1'd1;
-            litedramcore_bankmachine0_row <= litedramcore_bankmachine0_source_source_payload_addr[22:7];
+        if (main_litedramcore_bankmachine0_row_open) begin
+            main_litedramcore_bankmachine0_row_opened <= 1'd1;
+            main_litedramcore_bankmachine0_row <= main_litedramcore_bankmachine0_source_source_payload_addr[22:7];
         end
     end
-    if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin
-        litedramcore_bankmachine0_produce <= (litedramcore_bankmachine0_produce + 1'd1);
+    if (((main_litedramcore_bankmachine0_syncfifo0_we & main_litedramcore_bankmachine0_syncfifo0_writable) & (~main_litedramcore_bankmachine0_replace))) begin
+        main_litedramcore_bankmachine0_produce <= (main_litedramcore_bankmachine0_produce + 1'd1);
     end
-    if (litedramcore_bankmachine0_do_read) begin
-        litedramcore_bankmachine0_consume <= (litedramcore_bankmachine0_consume + 1'd1);
+    if (main_litedramcore_bankmachine0_do_read) begin
+        main_litedramcore_bankmachine0_consume <= (main_litedramcore_bankmachine0_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin
-        if ((~litedramcore_bankmachine0_do_read)) begin
-            litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level + 1'd1);
+    if (((main_litedramcore_bankmachine0_syncfifo0_we & main_litedramcore_bankmachine0_syncfifo0_writable) & (~main_litedramcore_bankmachine0_replace))) begin
+        if ((~main_litedramcore_bankmachine0_do_read)) begin
+            main_litedramcore_bankmachine0_level <= (main_litedramcore_bankmachine0_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine0_do_read) begin
-            litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level - 1'd1);
+        if (main_litedramcore_bankmachine0_do_read) begin
+            main_litedramcore_bankmachine0_level <= (main_litedramcore_bankmachine0_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine0_pipe_valid_source_valid <= litedramcore_bankmachine0_pipe_valid_sink_valid;
-        litedramcore_bankmachine0_pipe_valid_source_first <= litedramcore_bankmachine0_pipe_valid_sink_first;
-        litedramcore_bankmachine0_pipe_valid_source_last <= litedramcore_bankmachine0_pipe_valid_sink_last;
-        litedramcore_bankmachine0_pipe_valid_source_payload_we <= litedramcore_bankmachine0_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine0_pipe_valid_source_valid) | main_litedramcore_bankmachine0_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine0_pipe_valid_source_valid <= main_litedramcore_bankmachine0_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine0_pipe_valid_source_first <= main_litedramcore_bankmachine0_pipe_valid_sink_first;
+        main_litedramcore_bankmachine0_pipe_valid_source_last <= main_litedramcore_bankmachine0_pipe_valid_sink_last;
+        main_litedramcore_bankmachine0_pipe_valid_source_payload_we <= main_litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine0_twtpcon_valid) begin
-        litedramcore_bankmachine0_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine0_twtpcon_valid) begin
+        main_litedramcore_bankmachine0_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
-            litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine0_twtpcon_ready)) begin
+            main_litedramcore_bankmachine0_twtpcon_count <= (main_litedramcore_bankmachine0_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine0_trccon_valid) begin
-        litedramcore_bankmachine0_trccon_count <= 3'd6;
+    if (main_litedramcore_bankmachine0_trccon_valid) begin
+        main_litedramcore_bankmachine0_trccon_count <= 3'd6;
         if (1'd0) begin
-            litedramcore_bankmachine0_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine0_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine0_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine0_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine0_trccon_ready)) begin
-            litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine0_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine0_trccon_ready)) begin
+            main_litedramcore_bankmachine0_trccon_count <= (main_litedramcore_bankmachine0_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine0_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine0_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine0_trascon_valid) begin
-        litedramcore_bankmachine0_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine0_trascon_valid) begin
+        main_litedramcore_bankmachine0_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine0_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine0_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine0_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine0_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine0_trascon_ready)) begin
-            litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine0_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine0_trascon_ready)) begin
+            main_litedramcore_bankmachine0_trascon_count <= (main_litedramcore_bankmachine0_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine0_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine0_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
-    if (litedramcore_bankmachine1_row_close) begin
-        litedramcore_bankmachine1_row_opened <= 1'd0;
+    builder_bankmachine0_state <= builder_bankmachine0_next_state;
+    if (main_litedramcore_bankmachine1_row_close) begin
+        main_litedramcore_bankmachine1_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine1_row_open) begin
-            litedramcore_bankmachine1_row_opened <= 1'd1;
-            litedramcore_bankmachine1_row <= litedramcore_bankmachine1_source_source_payload_addr[22:7];
+        if (main_litedramcore_bankmachine1_row_open) begin
+            main_litedramcore_bankmachine1_row_opened <= 1'd1;
+            main_litedramcore_bankmachine1_row <= main_litedramcore_bankmachine1_source_source_payload_addr[22:7];
         end
     end
-    if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin
-        litedramcore_bankmachine1_produce <= (litedramcore_bankmachine1_produce + 1'd1);
+    if (((main_litedramcore_bankmachine1_syncfifo1_we & main_litedramcore_bankmachine1_syncfifo1_writable) & (~main_litedramcore_bankmachine1_replace))) begin
+        main_litedramcore_bankmachine1_produce <= (main_litedramcore_bankmachine1_produce + 1'd1);
     end
-    if (litedramcore_bankmachine1_do_read) begin
-        litedramcore_bankmachine1_consume <= (litedramcore_bankmachine1_consume + 1'd1);
+    if (main_litedramcore_bankmachine1_do_read) begin
+        main_litedramcore_bankmachine1_consume <= (main_litedramcore_bankmachine1_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin
-        if ((~litedramcore_bankmachine1_do_read)) begin
-            litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level + 1'd1);
+    if (((main_litedramcore_bankmachine1_syncfifo1_we & main_litedramcore_bankmachine1_syncfifo1_writable) & (~main_litedramcore_bankmachine1_replace))) begin
+        if ((~main_litedramcore_bankmachine1_do_read)) begin
+            main_litedramcore_bankmachine1_level <= (main_litedramcore_bankmachine1_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine1_do_read) begin
-            litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level - 1'd1);
+        if (main_litedramcore_bankmachine1_do_read) begin
+            main_litedramcore_bankmachine1_level <= (main_litedramcore_bankmachine1_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine1_pipe_valid_source_valid <= litedramcore_bankmachine1_pipe_valid_sink_valid;
-        litedramcore_bankmachine1_pipe_valid_source_first <= litedramcore_bankmachine1_pipe_valid_sink_first;
-        litedramcore_bankmachine1_pipe_valid_source_last <= litedramcore_bankmachine1_pipe_valid_sink_last;
-        litedramcore_bankmachine1_pipe_valid_source_payload_we <= litedramcore_bankmachine1_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine1_pipe_valid_source_valid) | main_litedramcore_bankmachine1_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine1_pipe_valid_source_valid <= main_litedramcore_bankmachine1_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine1_pipe_valid_source_first <= main_litedramcore_bankmachine1_pipe_valid_sink_first;
+        main_litedramcore_bankmachine1_pipe_valid_source_last <= main_litedramcore_bankmachine1_pipe_valid_sink_last;
+        main_litedramcore_bankmachine1_pipe_valid_source_payload_we <= main_litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine1_twtpcon_valid) begin
-        litedramcore_bankmachine1_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine1_twtpcon_valid) begin
+        main_litedramcore_bankmachine1_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
-            litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine1_twtpcon_ready)) begin
+            main_litedramcore_bankmachine1_twtpcon_count <= (main_litedramcore_bankmachine1_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine1_trccon_valid) begin
-        litedramcore_bankmachine1_trccon_count <= 3'd6;
+    if (main_litedramcore_bankmachine1_trccon_valid) begin
+        main_litedramcore_bankmachine1_trccon_count <= 3'd6;
         if (1'd0) begin
-            litedramcore_bankmachine1_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine1_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine1_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine1_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine1_trccon_ready)) begin
-            litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine1_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine1_trccon_ready)) begin
+            main_litedramcore_bankmachine1_trccon_count <= (main_litedramcore_bankmachine1_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine1_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine1_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine1_trascon_valid) begin
-        litedramcore_bankmachine1_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine1_trascon_valid) begin
+        main_litedramcore_bankmachine1_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine1_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine1_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine1_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine1_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine1_trascon_ready)) begin
-            litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine1_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine1_trascon_ready)) begin
+            main_litedramcore_bankmachine1_trascon_count <= (main_litedramcore_bankmachine1_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine1_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine1_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
-    if (litedramcore_bankmachine2_row_close) begin
-        litedramcore_bankmachine2_row_opened <= 1'd0;
+    builder_bankmachine1_state <= builder_bankmachine1_next_state;
+    if (main_litedramcore_bankmachine2_row_close) begin
+        main_litedramcore_bankmachine2_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine2_row_open) begin
-            litedramcore_bankmachine2_row_opened <= 1'd1;
-            litedramcore_bankmachine2_row <= litedramcore_bankmachine2_source_source_payload_addr[22:7];
+        if (main_litedramcore_bankmachine2_row_open) begin
+            main_litedramcore_bankmachine2_row_opened <= 1'd1;
+            main_litedramcore_bankmachine2_row <= main_litedramcore_bankmachine2_source_source_payload_addr[22:7];
         end
     end
-    if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin
-        litedramcore_bankmachine2_produce <= (litedramcore_bankmachine2_produce + 1'd1);
+    if (((main_litedramcore_bankmachine2_syncfifo2_we & main_litedramcore_bankmachine2_syncfifo2_writable) & (~main_litedramcore_bankmachine2_replace))) begin
+        main_litedramcore_bankmachine2_produce <= (main_litedramcore_bankmachine2_produce + 1'd1);
     end
-    if (litedramcore_bankmachine2_do_read) begin
-        litedramcore_bankmachine2_consume <= (litedramcore_bankmachine2_consume + 1'd1);
+    if (main_litedramcore_bankmachine2_do_read) begin
+        main_litedramcore_bankmachine2_consume <= (main_litedramcore_bankmachine2_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin
-        if ((~litedramcore_bankmachine2_do_read)) begin
-            litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level + 1'd1);
+    if (((main_litedramcore_bankmachine2_syncfifo2_we & main_litedramcore_bankmachine2_syncfifo2_writable) & (~main_litedramcore_bankmachine2_replace))) begin
+        if ((~main_litedramcore_bankmachine2_do_read)) begin
+            main_litedramcore_bankmachine2_level <= (main_litedramcore_bankmachine2_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine2_do_read) begin
-            litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level - 1'd1);
+        if (main_litedramcore_bankmachine2_do_read) begin
+            main_litedramcore_bankmachine2_level <= (main_litedramcore_bankmachine2_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine2_pipe_valid_source_valid <= litedramcore_bankmachine2_pipe_valid_sink_valid;
-        litedramcore_bankmachine2_pipe_valid_source_first <= litedramcore_bankmachine2_pipe_valid_sink_first;
-        litedramcore_bankmachine2_pipe_valid_source_last <= litedramcore_bankmachine2_pipe_valid_sink_last;
-        litedramcore_bankmachine2_pipe_valid_source_payload_we <= litedramcore_bankmachine2_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine2_pipe_valid_source_valid) | main_litedramcore_bankmachine2_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine2_pipe_valid_source_valid <= main_litedramcore_bankmachine2_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine2_pipe_valid_source_first <= main_litedramcore_bankmachine2_pipe_valid_sink_first;
+        main_litedramcore_bankmachine2_pipe_valid_source_last <= main_litedramcore_bankmachine2_pipe_valid_sink_last;
+        main_litedramcore_bankmachine2_pipe_valid_source_payload_we <= main_litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine2_twtpcon_valid) begin
-        litedramcore_bankmachine2_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine2_twtpcon_valid) begin
+        main_litedramcore_bankmachine2_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
-            litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine2_twtpcon_ready)) begin
+            main_litedramcore_bankmachine2_twtpcon_count <= (main_litedramcore_bankmachine2_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine2_trccon_valid) begin
-        litedramcore_bankmachine2_trccon_count <= 3'd6;
+    if (main_litedramcore_bankmachine2_trccon_valid) begin
+        main_litedramcore_bankmachine2_trccon_count <= 3'd6;
         if (1'd0) begin
-            litedramcore_bankmachine2_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine2_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine2_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine2_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine2_trccon_ready)) begin
-            litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine2_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine2_trccon_ready)) begin
+            main_litedramcore_bankmachine2_trccon_count <= (main_litedramcore_bankmachine2_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine2_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine2_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine2_trascon_valid) begin
-        litedramcore_bankmachine2_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine2_trascon_valid) begin
+        main_litedramcore_bankmachine2_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine2_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine2_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine2_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine2_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine2_trascon_ready)) begin
-            litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine2_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine2_trascon_ready)) begin
+            main_litedramcore_bankmachine2_trascon_count <= (main_litedramcore_bankmachine2_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine2_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine2_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
-    if (litedramcore_bankmachine3_row_close) begin
-        litedramcore_bankmachine3_row_opened <= 1'd0;
+    builder_bankmachine2_state <= builder_bankmachine2_next_state;
+    if (main_litedramcore_bankmachine3_row_close) begin
+        main_litedramcore_bankmachine3_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine3_row_open) begin
-            litedramcore_bankmachine3_row_opened <= 1'd1;
-            litedramcore_bankmachine3_row <= litedramcore_bankmachine3_source_source_payload_addr[22:7];
+        if (main_litedramcore_bankmachine3_row_open) begin
+            main_litedramcore_bankmachine3_row_opened <= 1'd1;
+            main_litedramcore_bankmachine3_row <= main_litedramcore_bankmachine3_source_source_payload_addr[22:7];
         end
     end
-    if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin
-        litedramcore_bankmachine3_produce <= (litedramcore_bankmachine3_produce + 1'd1);
+    if (((main_litedramcore_bankmachine3_syncfifo3_we & main_litedramcore_bankmachine3_syncfifo3_writable) & (~main_litedramcore_bankmachine3_replace))) begin
+        main_litedramcore_bankmachine3_produce <= (main_litedramcore_bankmachine3_produce + 1'd1);
     end
-    if (litedramcore_bankmachine3_do_read) begin
-        litedramcore_bankmachine3_consume <= (litedramcore_bankmachine3_consume + 1'd1);
+    if (main_litedramcore_bankmachine3_do_read) begin
+        main_litedramcore_bankmachine3_consume <= (main_litedramcore_bankmachine3_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin
-        if ((~litedramcore_bankmachine3_do_read)) begin
-            litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level + 1'd1);
+    if (((main_litedramcore_bankmachine3_syncfifo3_we & main_litedramcore_bankmachine3_syncfifo3_writable) & (~main_litedramcore_bankmachine3_replace))) begin
+        if ((~main_litedramcore_bankmachine3_do_read)) begin
+            main_litedramcore_bankmachine3_level <= (main_litedramcore_bankmachine3_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine3_do_read) begin
-            litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level - 1'd1);
+        if (main_litedramcore_bankmachine3_do_read) begin
+            main_litedramcore_bankmachine3_level <= (main_litedramcore_bankmachine3_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine3_pipe_valid_source_valid <= litedramcore_bankmachine3_pipe_valid_sink_valid;
-        litedramcore_bankmachine3_pipe_valid_source_first <= litedramcore_bankmachine3_pipe_valid_sink_first;
-        litedramcore_bankmachine3_pipe_valid_source_last <= litedramcore_bankmachine3_pipe_valid_sink_last;
-        litedramcore_bankmachine3_pipe_valid_source_payload_we <= litedramcore_bankmachine3_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine3_pipe_valid_source_valid) | main_litedramcore_bankmachine3_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine3_pipe_valid_source_valid <= main_litedramcore_bankmachine3_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine3_pipe_valid_source_first <= main_litedramcore_bankmachine3_pipe_valid_sink_first;
+        main_litedramcore_bankmachine3_pipe_valid_source_last <= main_litedramcore_bankmachine3_pipe_valid_sink_last;
+        main_litedramcore_bankmachine3_pipe_valid_source_payload_we <= main_litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine3_twtpcon_valid) begin
-        litedramcore_bankmachine3_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine3_twtpcon_valid) begin
+        main_litedramcore_bankmachine3_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
-            litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine3_twtpcon_ready)) begin
+            main_litedramcore_bankmachine3_twtpcon_count <= (main_litedramcore_bankmachine3_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine3_trccon_valid) begin
-        litedramcore_bankmachine3_trccon_count <= 3'd6;
+    if (main_litedramcore_bankmachine3_trccon_valid) begin
+        main_litedramcore_bankmachine3_trccon_count <= 3'd6;
         if (1'd0) begin
-            litedramcore_bankmachine3_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine3_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine3_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine3_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine3_trccon_ready)) begin
-            litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine3_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine3_trccon_ready)) begin
+            main_litedramcore_bankmachine3_trccon_count <= (main_litedramcore_bankmachine3_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine3_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine3_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine3_trascon_valid) begin
-        litedramcore_bankmachine3_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine3_trascon_valid) begin
+        main_litedramcore_bankmachine3_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine3_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine3_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine3_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine3_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine3_trascon_ready)) begin
-            litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine3_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine3_trascon_ready)) begin
+            main_litedramcore_bankmachine3_trascon_count <= (main_litedramcore_bankmachine3_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine3_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine3_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
-    if (litedramcore_bankmachine4_row_close) begin
-        litedramcore_bankmachine4_row_opened <= 1'd0;
+    builder_bankmachine3_state <= builder_bankmachine3_next_state;
+    if (main_litedramcore_bankmachine4_row_close) begin
+        main_litedramcore_bankmachine4_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine4_row_open) begin
-            litedramcore_bankmachine4_row_opened <= 1'd1;
-            litedramcore_bankmachine4_row <= litedramcore_bankmachine4_source_source_payload_addr[22:7];
+        if (main_litedramcore_bankmachine4_row_open) begin
+            main_litedramcore_bankmachine4_row_opened <= 1'd1;
+            main_litedramcore_bankmachine4_row <= main_litedramcore_bankmachine4_source_source_payload_addr[22:7];
         end
     end
-    if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin
-        litedramcore_bankmachine4_produce <= (litedramcore_bankmachine4_produce + 1'd1);
+    if (((main_litedramcore_bankmachine4_syncfifo4_we & main_litedramcore_bankmachine4_syncfifo4_writable) & (~main_litedramcore_bankmachine4_replace))) begin
+        main_litedramcore_bankmachine4_produce <= (main_litedramcore_bankmachine4_produce + 1'd1);
     end
-    if (litedramcore_bankmachine4_do_read) begin
-        litedramcore_bankmachine4_consume <= (litedramcore_bankmachine4_consume + 1'd1);
+    if (main_litedramcore_bankmachine4_do_read) begin
+        main_litedramcore_bankmachine4_consume <= (main_litedramcore_bankmachine4_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin
-        if ((~litedramcore_bankmachine4_do_read)) begin
-            litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level + 1'd1);
+    if (((main_litedramcore_bankmachine4_syncfifo4_we & main_litedramcore_bankmachine4_syncfifo4_writable) & (~main_litedramcore_bankmachine4_replace))) begin
+        if ((~main_litedramcore_bankmachine4_do_read)) begin
+            main_litedramcore_bankmachine4_level <= (main_litedramcore_bankmachine4_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine4_do_read) begin
-            litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level - 1'd1);
+        if (main_litedramcore_bankmachine4_do_read) begin
+            main_litedramcore_bankmachine4_level <= (main_litedramcore_bankmachine4_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine4_pipe_valid_source_valid <= litedramcore_bankmachine4_pipe_valid_sink_valid;
-        litedramcore_bankmachine4_pipe_valid_source_first <= litedramcore_bankmachine4_pipe_valid_sink_first;
-        litedramcore_bankmachine4_pipe_valid_source_last <= litedramcore_bankmachine4_pipe_valid_sink_last;
-        litedramcore_bankmachine4_pipe_valid_source_payload_we <= litedramcore_bankmachine4_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine4_pipe_valid_source_valid) | main_litedramcore_bankmachine4_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine4_pipe_valid_source_valid <= main_litedramcore_bankmachine4_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine4_pipe_valid_source_first <= main_litedramcore_bankmachine4_pipe_valid_sink_first;
+        main_litedramcore_bankmachine4_pipe_valid_source_last <= main_litedramcore_bankmachine4_pipe_valid_sink_last;
+        main_litedramcore_bankmachine4_pipe_valid_source_payload_we <= main_litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine4_twtpcon_valid) begin
-        litedramcore_bankmachine4_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine4_twtpcon_valid) begin
+        main_litedramcore_bankmachine4_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
-            litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine4_twtpcon_ready)) begin
+            main_litedramcore_bankmachine4_twtpcon_count <= (main_litedramcore_bankmachine4_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine4_trccon_valid) begin
-        litedramcore_bankmachine4_trccon_count <= 3'd6;
+    if (main_litedramcore_bankmachine4_trccon_valid) begin
+        main_litedramcore_bankmachine4_trccon_count <= 3'd6;
         if (1'd0) begin
-            litedramcore_bankmachine4_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine4_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine4_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine4_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine4_trccon_ready)) begin
-            litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine4_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine4_trccon_ready)) begin
+            main_litedramcore_bankmachine4_trccon_count <= (main_litedramcore_bankmachine4_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine4_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine4_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine4_trascon_valid) begin
-        litedramcore_bankmachine4_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine4_trascon_valid) begin
+        main_litedramcore_bankmachine4_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine4_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine4_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine4_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine4_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine4_trascon_ready)) begin
-            litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine4_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine4_trascon_ready)) begin
+            main_litedramcore_bankmachine4_trascon_count <= (main_litedramcore_bankmachine4_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine4_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine4_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
-    if (litedramcore_bankmachine5_row_close) begin
-        litedramcore_bankmachine5_row_opened <= 1'd0;
+    builder_bankmachine4_state <= builder_bankmachine4_next_state;
+    if (main_litedramcore_bankmachine5_row_close) begin
+        main_litedramcore_bankmachine5_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine5_row_open) begin
-            litedramcore_bankmachine5_row_opened <= 1'd1;
-            litedramcore_bankmachine5_row <= litedramcore_bankmachine5_source_source_payload_addr[22:7];
+        if (main_litedramcore_bankmachine5_row_open) begin
+            main_litedramcore_bankmachine5_row_opened <= 1'd1;
+            main_litedramcore_bankmachine5_row <= main_litedramcore_bankmachine5_source_source_payload_addr[22:7];
         end
     end
-    if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin
-        litedramcore_bankmachine5_produce <= (litedramcore_bankmachine5_produce + 1'd1);
+    if (((main_litedramcore_bankmachine5_syncfifo5_we & main_litedramcore_bankmachine5_syncfifo5_writable) & (~main_litedramcore_bankmachine5_replace))) begin
+        main_litedramcore_bankmachine5_produce <= (main_litedramcore_bankmachine5_produce + 1'd1);
     end
-    if (litedramcore_bankmachine5_do_read) begin
-        litedramcore_bankmachine5_consume <= (litedramcore_bankmachine5_consume + 1'd1);
+    if (main_litedramcore_bankmachine5_do_read) begin
+        main_litedramcore_bankmachine5_consume <= (main_litedramcore_bankmachine5_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin
-        if ((~litedramcore_bankmachine5_do_read)) begin
-            litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level + 1'd1);
+    if (((main_litedramcore_bankmachine5_syncfifo5_we & main_litedramcore_bankmachine5_syncfifo5_writable) & (~main_litedramcore_bankmachine5_replace))) begin
+        if ((~main_litedramcore_bankmachine5_do_read)) begin
+            main_litedramcore_bankmachine5_level <= (main_litedramcore_bankmachine5_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine5_do_read) begin
-            litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level - 1'd1);
+        if (main_litedramcore_bankmachine5_do_read) begin
+            main_litedramcore_bankmachine5_level <= (main_litedramcore_bankmachine5_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine5_pipe_valid_source_valid <= litedramcore_bankmachine5_pipe_valid_sink_valid;
-        litedramcore_bankmachine5_pipe_valid_source_first <= litedramcore_bankmachine5_pipe_valid_sink_first;
-        litedramcore_bankmachine5_pipe_valid_source_last <= litedramcore_bankmachine5_pipe_valid_sink_last;
-        litedramcore_bankmachine5_pipe_valid_source_payload_we <= litedramcore_bankmachine5_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine5_pipe_valid_source_valid) | main_litedramcore_bankmachine5_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine5_pipe_valid_source_valid <= main_litedramcore_bankmachine5_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine5_pipe_valid_source_first <= main_litedramcore_bankmachine5_pipe_valid_sink_first;
+        main_litedramcore_bankmachine5_pipe_valid_source_last <= main_litedramcore_bankmachine5_pipe_valid_sink_last;
+        main_litedramcore_bankmachine5_pipe_valid_source_payload_we <= main_litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine5_twtpcon_valid) begin
-        litedramcore_bankmachine5_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine5_twtpcon_valid) begin
+        main_litedramcore_bankmachine5_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
-            litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine5_twtpcon_ready)) begin
+            main_litedramcore_bankmachine5_twtpcon_count <= (main_litedramcore_bankmachine5_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine5_trccon_valid) begin
-        litedramcore_bankmachine5_trccon_count <= 3'd6;
+    if (main_litedramcore_bankmachine5_trccon_valid) begin
+        main_litedramcore_bankmachine5_trccon_count <= 3'd6;
         if (1'd0) begin
-            litedramcore_bankmachine5_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine5_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine5_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine5_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine5_trccon_ready)) begin
-            litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine5_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine5_trccon_ready)) begin
+            main_litedramcore_bankmachine5_trccon_count <= (main_litedramcore_bankmachine5_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine5_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine5_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine5_trascon_valid) begin
-        litedramcore_bankmachine5_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine5_trascon_valid) begin
+        main_litedramcore_bankmachine5_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine5_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine5_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine5_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine5_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine5_trascon_ready)) begin
-            litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine5_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine5_trascon_ready)) begin
+            main_litedramcore_bankmachine5_trascon_count <= (main_litedramcore_bankmachine5_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine5_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine5_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
-    if (litedramcore_bankmachine6_row_close) begin
-        litedramcore_bankmachine6_row_opened <= 1'd0;
+    builder_bankmachine5_state <= builder_bankmachine5_next_state;
+    if (main_litedramcore_bankmachine6_row_close) begin
+        main_litedramcore_bankmachine6_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine6_row_open) begin
-            litedramcore_bankmachine6_row_opened <= 1'd1;
-            litedramcore_bankmachine6_row <= litedramcore_bankmachine6_source_source_payload_addr[22:7];
+        if (main_litedramcore_bankmachine6_row_open) begin
+            main_litedramcore_bankmachine6_row_opened <= 1'd1;
+            main_litedramcore_bankmachine6_row <= main_litedramcore_bankmachine6_source_source_payload_addr[22:7];
         end
     end
-    if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin
-        litedramcore_bankmachine6_produce <= (litedramcore_bankmachine6_produce + 1'd1);
+    if (((main_litedramcore_bankmachine6_syncfifo6_we & main_litedramcore_bankmachine6_syncfifo6_writable) & (~main_litedramcore_bankmachine6_replace))) begin
+        main_litedramcore_bankmachine6_produce <= (main_litedramcore_bankmachine6_produce + 1'd1);
     end
-    if (litedramcore_bankmachine6_do_read) begin
-        litedramcore_bankmachine6_consume <= (litedramcore_bankmachine6_consume + 1'd1);
+    if (main_litedramcore_bankmachine6_do_read) begin
+        main_litedramcore_bankmachine6_consume <= (main_litedramcore_bankmachine6_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin
-        if ((~litedramcore_bankmachine6_do_read)) begin
-            litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level + 1'd1);
+    if (((main_litedramcore_bankmachine6_syncfifo6_we & main_litedramcore_bankmachine6_syncfifo6_writable) & (~main_litedramcore_bankmachine6_replace))) begin
+        if ((~main_litedramcore_bankmachine6_do_read)) begin
+            main_litedramcore_bankmachine6_level <= (main_litedramcore_bankmachine6_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine6_do_read) begin
-            litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level - 1'd1);
+        if (main_litedramcore_bankmachine6_do_read) begin
+            main_litedramcore_bankmachine6_level <= (main_litedramcore_bankmachine6_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine6_pipe_valid_source_valid <= litedramcore_bankmachine6_pipe_valid_sink_valid;
-        litedramcore_bankmachine6_pipe_valid_source_first <= litedramcore_bankmachine6_pipe_valid_sink_first;
-        litedramcore_bankmachine6_pipe_valid_source_last <= litedramcore_bankmachine6_pipe_valid_sink_last;
-        litedramcore_bankmachine6_pipe_valid_source_payload_we <= litedramcore_bankmachine6_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine6_pipe_valid_source_valid) | main_litedramcore_bankmachine6_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine6_pipe_valid_source_valid <= main_litedramcore_bankmachine6_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine6_pipe_valid_source_first <= main_litedramcore_bankmachine6_pipe_valid_sink_first;
+        main_litedramcore_bankmachine6_pipe_valid_source_last <= main_litedramcore_bankmachine6_pipe_valid_sink_last;
+        main_litedramcore_bankmachine6_pipe_valid_source_payload_we <= main_litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine6_twtpcon_valid) begin
-        litedramcore_bankmachine6_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine6_twtpcon_valid) begin
+        main_litedramcore_bankmachine6_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
-            litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine6_twtpcon_ready)) begin
+            main_litedramcore_bankmachine6_twtpcon_count <= (main_litedramcore_bankmachine6_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine6_trccon_valid) begin
-        litedramcore_bankmachine6_trccon_count <= 3'd6;
+    if (main_litedramcore_bankmachine6_trccon_valid) begin
+        main_litedramcore_bankmachine6_trccon_count <= 3'd6;
         if (1'd0) begin
-            litedramcore_bankmachine6_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine6_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine6_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine6_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine6_trccon_ready)) begin
-            litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine6_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine6_trccon_ready)) begin
+            main_litedramcore_bankmachine6_trccon_count <= (main_litedramcore_bankmachine6_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine6_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine6_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine6_trascon_valid) begin
-        litedramcore_bankmachine6_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine6_trascon_valid) begin
+        main_litedramcore_bankmachine6_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine6_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine6_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine6_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine6_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine6_trascon_ready)) begin
-            litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine6_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine6_trascon_ready)) begin
+            main_litedramcore_bankmachine6_trascon_count <= (main_litedramcore_bankmachine6_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine6_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine6_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
-    if (litedramcore_bankmachine7_row_close) begin
-        litedramcore_bankmachine7_row_opened <= 1'd0;
+    builder_bankmachine6_state <= builder_bankmachine6_next_state;
+    if (main_litedramcore_bankmachine7_row_close) begin
+        main_litedramcore_bankmachine7_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine7_row_open) begin
-            litedramcore_bankmachine7_row_opened <= 1'd1;
-            litedramcore_bankmachine7_row <= litedramcore_bankmachine7_source_source_payload_addr[22:7];
+        if (main_litedramcore_bankmachine7_row_open) begin
+            main_litedramcore_bankmachine7_row_opened <= 1'd1;
+            main_litedramcore_bankmachine7_row <= main_litedramcore_bankmachine7_source_source_payload_addr[22:7];
         end
     end
-    if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin
-        litedramcore_bankmachine7_produce <= (litedramcore_bankmachine7_produce + 1'd1);
+    if (((main_litedramcore_bankmachine7_syncfifo7_we & main_litedramcore_bankmachine7_syncfifo7_writable) & (~main_litedramcore_bankmachine7_replace))) begin
+        main_litedramcore_bankmachine7_produce <= (main_litedramcore_bankmachine7_produce + 1'd1);
     end
-    if (litedramcore_bankmachine7_do_read) begin
-        litedramcore_bankmachine7_consume <= (litedramcore_bankmachine7_consume + 1'd1);
+    if (main_litedramcore_bankmachine7_do_read) begin
+        main_litedramcore_bankmachine7_consume <= (main_litedramcore_bankmachine7_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin
-        if ((~litedramcore_bankmachine7_do_read)) begin
-            litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level + 1'd1);
+    if (((main_litedramcore_bankmachine7_syncfifo7_we & main_litedramcore_bankmachine7_syncfifo7_writable) & (~main_litedramcore_bankmachine7_replace))) begin
+        if ((~main_litedramcore_bankmachine7_do_read)) begin
+            main_litedramcore_bankmachine7_level <= (main_litedramcore_bankmachine7_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine7_do_read) begin
-            litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level - 1'd1);
+        if (main_litedramcore_bankmachine7_do_read) begin
+            main_litedramcore_bankmachine7_level <= (main_litedramcore_bankmachine7_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine7_pipe_valid_source_valid <= litedramcore_bankmachine7_pipe_valid_sink_valid;
-        litedramcore_bankmachine7_pipe_valid_source_first <= litedramcore_bankmachine7_pipe_valid_sink_first;
-        litedramcore_bankmachine7_pipe_valid_source_last <= litedramcore_bankmachine7_pipe_valid_sink_last;
-        litedramcore_bankmachine7_pipe_valid_source_payload_we <= litedramcore_bankmachine7_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine7_pipe_valid_source_valid) | main_litedramcore_bankmachine7_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine7_pipe_valid_source_valid <= main_litedramcore_bankmachine7_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine7_pipe_valid_source_first <= main_litedramcore_bankmachine7_pipe_valid_sink_first;
+        main_litedramcore_bankmachine7_pipe_valid_source_last <= main_litedramcore_bankmachine7_pipe_valid_sink_last;
+        main_litedramcore_bankmachine7_pipe_valid_source_payload_we <= main_litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine7_twtpcon_valid) begin
-        litedramcore_bankmachine7_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine7_twtpcon_valid) begin
+        main_litedramcore_bankmachine7_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
-            litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine7_twtpcon_ready)) begin
+            main_litedramcore_bankmachine7_twtpcon_count <= (main_litedramcore_bankmachine7_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine7_trccon_valid) begin
-        litedramcore_bankmachine7_trccon_count <= 3'd6;
+    if (main_litedramcore_bankmachine7_trccon_valid) begin
+        main_litedramcore_bankmachine7_trccon_count <= 3'd6;
         if (1'd0) begin
-            litedramcore_bankmachine7_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine7_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine7_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine7_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine7_trccon_ready)) begin
-            litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine7_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine7_trccon_ready)) begin
+            main_litedramcore_bankmachine7_trccon_count <= (main_litedramcore_bankmachine7_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine7_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine7_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine7_trascon_valid) begin
-        litedramcore_bankmachine7_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine7_trascon_valid) begin
+        main_litedramcore_bankmachine7_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine7_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine7_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine7_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine7_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine7_trascon_ready)) begin
-            litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine7_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine7_trascon_ready)) begin
+            main_litedramcore_bankmachine7_trascon_count <= (main_litedramcore_bankmachine7_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine7_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine7_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
-    if ((~litedramcore_en0)) begin
-        litedramcore_time0 <= 5'd31;
+    builder_bankmachine7_state <= builder_bankmachine7_next_state;
+    if ((~main_litedramcore_en0)) begin
+        main_litedramcore_time0 <= 5'd31;
     end else begin
-        if ((~litedramcore_max_time0)) begin
-            litedramcore_time0 <= (litedramcore_time0 - 1'd1);
+        if ((~main_litedramcore_max_time0)) begin
+            main_litedramcore_time0 <= (main_litedramcore_time0 - 1'd1);
         end
     end
-    if ((~litedramcore_en1)) begin
-        litedramcore_time1 <= 4'd15;
+    if ((~main_litedramcore_en1)) begin
+        main_litedramcore_time1 <= 4'd15;
     end else begin
-        if ((~litedramcore_max_time1)) begin
-            litedramcore_time1 <= (litedramcore_time1 - 1'd1);
+        if ((~main_litedramcore_max_time1)) begin
+            main_litedramcore_time1 <= (main_litedramcore_time1 - 1'd1);
         end
     end
-    if (litedramcore_choose_cmd_ce) begin
-        case (litedramcore_choose_cmd_grant)
+    if (main_litedramcore_choose_cmd_ce) begin
+        case (main_litedramcore_choose_cmd_grant)
             1'd0: begin
-                if (litedramcore_choose_cmd_request[1]) begin
-                    litedramcore_choose_cmd_grant <= 1'd1;
+                if (main_litedramcore_choose_cmd_request[1]) begin
+                    main_litedramcore_choose_cmd_grant <= 1'd1;
                 end else begin
-                    if (litedramcore_choose_cmd_request[2]) begin
-                        litedramcore_choose_cmd_grant <= 2'd2;
+                    if (main_litedramcore_choose_cmd_request[2]) begin
+                        main_litedramcore_choose_cmd_grant <= 2'd2;
                     end else begin
-                        if (litedramcore_choose_cmd_request[3]) begin
-                            litedramcore_choose_cmd_grant <= 2'd3;
+                        if (main_litedramcore_choose_cmd_request[3]) begin
+                            main_litedramcore_choose_cmd_grant <= 2'd3;
                         end else begin
-                            if (litedramcore_choose_cmd_request[4]) begin
-                                litedramcore_choose_cmd_grant <= 3'd4;
+                            if (main_litedramcore_choose_cmd_request[4]) begin
+                                main_litedramcore_choose_cmd_grant <= 3'd4;
                             end else begin
-                                if (litedramcore_choose_cmd_request[5]) begin
-                                    litedramcore_choose_cmd_grant <= 3'd5;
+                                if (main_litedramcore_choose_cmd_request[5]) begin
+                                    main_litedramcore_choose_cmd_grant <= 3'd5;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[6]) begin
-                                        litedramcore_choose_cmd_grant <= 3'd6;
+                                    if (main_litedramcore_choose_cmd_request[6]) begin
+                                        main_litedramcore_choose_cmd_grant <= 3'd6;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[7]) begin
-                                            litedramcore_choose_cmd_grant <= 3'd7;
+                                        if (main_litedramcore_choose_cmd_request[7]) begin
+                                            main_litedramcore_choose_cmd_grant <= 3'd7;
                                         end
                                     end
                                 end
@@ -13030,26 +13447,26 @@ always @(posedge sys_clk) begin
                 end
             end
             1'd1: begin
-                if (litedramcore_choose_cmd_request[2]) begin
-                    litedramcore_choose_cmd_grant <= 2'd2;
+                if (main_litedramcore_choose_cmd_request[2]) begin
+                    main_litedramcore_choose_cmd_grant <= 2'd2;
                 end else begin
-                    if (litedramcore_choose_cmd_request[3]) begin
-                        litedramcore_choose_cmd_grant <= 2'd3;
+                    if (main_litedramcore_choose_cmd_request[3]) begin
+                        main_litedramcore_choose_cmd_grant <= 2'd3;
                     end else begin
-                        if (litedramcore_choose_cmd_request[4]) begin
-                            litedramcore_choose_cmd_grant <= 3'd4;
+                        if (main_litedramcore_choose_cmd_request[4]) begin
+                            main_litedramcore_choose_cmd_grant <= 3'd4;
                         end else begin
-                            if (litedramcore_choose_cmd_request[5]) begin
-                                litedramcore_choose_cmd_grant <= 3'd5;
+                            if (main_litedramcore_choose_cmd_request[5]) begin
+                                main_litedramcore_choose_cmd_grant <= 3'd5;
                             end else begin
-                                if (litedramcore_choose_cmd_request[6]) begin
-                                    litedramcore_choose_cmd_grant <= 3'd6;
+                                if (main_litedramcore_choose_cmd_request[6]) begin
+                                    main_litedramcore_choose_cmd_grant <= 3'd6;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[7]) begin
-                                        litedramcore_choose_cmd_grant <= 3'd7;
+                                    if (main_litedramcore_choose_cmd_request[7]) begin
+                                        main_litedramcore_choose_cmd_grant <= 3'd7;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[0]) begin
-                                            litedramcore_choose_cmd_grant <= 1'd0;
+                                        if (main_litedramcore_choose_cmd_request[0]) begin
+                                            main_litedramcore_choose_cmd_grant <= 1'd0;
                                         end
                                     end
                                 end
@@ -13059,26 +13476,26 @@ always @(posedge sys_clk) begin
                 end
             end
             2'd2: begin
-                if (litedramcore_choose_cmd_request[3]) begin
-                    litedramcore_choose_cmd_grant <= 2'd3;
+                if (main_litedramcore_choose_cmd_request[3]) begin
+                    main_litedramcore_choose_cmd_grant <= 2'd3;
                 end else begin
-                    if (litedramcore_choose_cmd_request[4]) begin
-                        litedramcore_choose_cmd_grant <= 3'd4;
+                    if (main_litedramcore_choose_cmd_request[4]) begin
+                        main_litedramcore_choose_cmd_grant <= 3'd4;
                     end else begin
-                        if (litedramcore_choose_cmd_request[5]) begin
-                            litedramcore_choose_cmd_grant <= 3'd5;
+                        if (main_litedramcore_choose_cmd_request[5]) begin
+                            main_litedramcore_choose_cmd_grant <= 3'd5;
                         end else begin
-                            if (litedramcore_choose_cmd_request[6]) begin
-                                litedramcore_choose_cmd_grant <= 3'd6;
+                            if (main_litedramcore_choose_cmd_request[6]) begin
+                                main_litedramcore_choose_cmd_grant <= 3'd6;
                             end else begin
-                                if (litedramcore_choose_cmd_request[7]) begin
-                                    litedramcore_choose_cmd_grant <= 3'd7;
+                                if (main_litedramcore_choose_cmd_request[7]) begin
+                                    main_litedramcore_choose_cmd_grant <= 3'd7;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[0]) begin
-                                        litedramcore_choose_cmd_grant <= 1'd0;
+                                    if (main_litedramcore_choose_cmd_request[0]) begin
+                                        main_litedramcore_choose_cmd_grant <= 1'd0;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[1]) begin
-                                            litedramcore_choose_cmd_grant <= 1'd1;
+                                        if (main_litedramcore_choose_cmd_request[1]) begin
+                                            main_litedramcore_choose_cmd_grant <= 1'd1;
                                         end
                                     end
                                 end
@@ -13088,26 +13505,26 @@ always @(posedge sys_clk) begin
                 end
             end
             2'd3: begin
-                if (litedramcore_choose_cmd_request[4]) begin
-                    litedramcore_choose_cmd_grant <= 3'd4;
+                if (main_litedramcore_choose_cmd_request[4]) begin
+                    main_litedramcore_choose_cmd_grant <= 3'd4;
                 end else begin
-                    if (litedramcore_choose_cmd_request[5]) begin
-                        litedramcore_choose_cmd_grant <= 3'd5;
+                    if (main_litedramcore_choose_cmd_request[5]) begin
+                        main_litedramcore_choose_cmd_grant <= 3'd5;
                     end else begin
-                        if (litedramcore_choose_cmd_request[6]) begin
-                            litedramcore_choose_cmd_grant <= 3'd6;
+                        if (main_litedramcore_choose_cmd_request[6]) begin
+                            main_litedramcore_choose_cmd_grant <= 3'd6;
                         end else begin
-                            if (litedramcore_choose_cmd_request[7]) begin
-                                litedramcore_choose_cmd_grant <= 3'd7;
+                            if (main_litedramcore_choose_cmd_request[7]) begin
+                                main_litedramcore_choose_cmd_grant <= 3'd7;
                             end else begin
-                                if (litedramcore_choose_cmd_request[0]) begin
-                                    litedramcore_choose_cmd_grant <= 1'd0;
+                                if (main_litedramcore_choose_cmd_request[0]) begin
+                                    main_litedramcore_choose_cmd_grant <= 1'd0;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[1]) begin
-                                        litedramcore_choose_cmd_grant <= 1'd1;
+                                    if (main_litedramcore_choose_cmd_request[1]) begin
+                                        main_litedramcore_choose_cmd_grant <= 1'd1;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[2]) begin
-                                            litedramcore_choose_cmd_grant <= 2'd2;
+                                        if (main_litedramcore_choose_cmd_request[2]) begin
+                                            main_litedramcore_choose_cmd_grant <= 2'd2;
                                         end
                                     end
                                 end
@@ -13117,26 +13534,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd4: begin
-                if (litedramcore_choose_cmd_request[5]) begin
-                    litedramcore_choose_cmd_grant <= 3'd5;
+                if (main_litedramcore_choose_cmd_request[5]) begin
+                    main_litedramcore_choose_cmd_grant <= 3'd5;
                 end else begin
-                    if (litedramcore_choose_cmd_request[6]) begin
-                        litedramcore_choose_cmd_grant <= 3'd6;
+                    if (main_litedramcore_choose_cmd_request[6]) begin
+                        main_litedramcore_choose_cmd_grant <= 3'd6;
                     end else begin
-                        if (litedramcore_choose_cmd_request[7]) begin
-                            litedramcore_choose_cmd_grant <= 3'd7;
+                        if (main_litedramcore_choose_cmd_request[7]) begin
+                            main_litedramcore_choose_cmd_grant <= 3'd7;
                         end else begin
-                            if (litedramcore_choose_cmd_request[0]) begin
-                                litedramcore_choose_cmd_grant <= 1'd0;
+                            if (main_litedramcore_choose_cmd_request[0]) begin
+                                main_litedramcore_choose_cmd_grant <= 1'd0;
                             end else begin
-                                if (litedramcore_choose_cmd_request[1]) begin
-                                    litedramcore_choose_cmd_grant <= 1'd1;
+                                if (main_litedramcore_choose_cmd_request[1]) begin
+                                    main_litedramcore_choose_cmd_grant <= 1'd1;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[2]) begin
-                                        litedramcore_choose_cmd_grant <= 2'd2;
+                                    if (main_litedramcore_choose_cmd_request[2]) begin
+                                        main_litedramcore_choose_cmd_grant <= 2'd2;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[3]) begin
-                                            litedramcore_choose_cmd_grant <= 2'd3;
+                                        if (main_litedramcore_choose_cmd_request[3]) begin
+                                            main_litedramcore_choose_cmd_grant <= 2'd3;
                                         end
                                     end
                                 end
@@ -13146,26 +13563,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd5: begin
-                if (litedramcore_choose_cmd_request[6]) begin
-                    litedramcore_choose_cmd_grant <= 3'd6;
+                if (main_litedramcore_choose_cmd_request[6]) begin
+                    main_litedramcore_choose_cmd_grant <= 3'd6;
                 end else begin
-                    if (litedramcore_choose_cmd_request[7]) begin
-                        litedramcore_choose_cmd_grant <= 3'd7;
+                    if (main_litedramcore_choose_cmd_request[7]) begin
+                        main_litedramcore_choose_cmd_grant <= 3'd7;
                     end else begin
-                        if (litedramcore_choose_cmd_request[0]) begin
-                            litedramcore_choose_cmd_grant <= 1'd0;
+                        if (main_litedramcore_choose_cmd_request[0]) begin
+                            main_litedramcore_choose_cmd_grant <= 1'd0;
                         end else begin
-                            if (litedramcore_choose_cmd_request[1]) begin
-                                litedramcore_choose_cmd_grant <= 1'd1;
+                            if (main_litedramcore_choose_cmd_request[1]) begin
+                                main_litedramcore_choose_cmd_grant <= 1'd1;
                             end else begin
-                                if (litedramcore_choose_cmd_request[2]) begin
-                                    litedramcore_choose_cmd_grant <= 2'd2;
+                                if (main_litedramcore_choose_cmd_request[2]) begin
+                                    main_litedramcore_choose_cmd_grant <= 2'd2;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[3]) begin
-                                        litedramcore_choose_cmd_grant <= 2'd3;
+                                    if (main_litedramcore_choose_cmd_request[3]) begin
+                                        main_litedramcore_choose_cmd_grant <= 2'd3;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[4]) begin
-                                            litedramcore_choose_cmd_grant <= 3'd4;
+                                        if (main_litedramcore_choose_cmd_request[4]) begin
+                                            main_litedramcore_choose_cmd_grant <= 3'd4;
                                         end
                                     end
                                 end
@@ -13175,26 +13592,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd6: begin
-                if (litedramcore_choose_cmd_request[7]) begin
-                    litedramcore_choose_cmd_grant <= 3'd7;
+                if (main_litedramcore_choose_cmd_request[7]) begin
+                    main_litedramcore_choose_cmd_grant <= 3'd7;
                 end else begin
-                    if (litedramcore_choose_cmd_request[0]) begin
-                        litedramcore_choose_cmd_grant <= 1'd0;
+                    if (main_litedramcore_choose_cmd_request[0]) begin
+                        main_litedramcore_choose_cmd_grant <= 1'd0;
                     end else begin
-                        if (litedramcore_choose_cmd_request[1]) begin
-                            litedramcore_choose_cmd_grant <= 1'd1;
+                        if (main_litedramcore_choose_cmd_request[1]) begin
+                            main_litedramcore_choose_cmd_grant <= 1'd1;
                         end else begin
-                            if (litedramcore_choose_cmd_request[2]) begin
-                                litedramcore_choose_cmd_grant <= 2'd2;
+                            if (main_litedramcore_choose_cmd_request[2]) begin
+                                main_litedramcore_choose_cmd_grant <= 2'd2;
                             end else begin
-                                if (litedramcore_choose_cmd_request[3]) begin
-                                    litedramcore_choose_cmd_grant <= 2'd3;
+                                if (main_litedramcore_choose_cmd_request[3]) begin
+                                    main_litedramcore_choose_cmd_grant <= 2'd3;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[4]) begin
-                                        litedramcore_choose_cmd_grant <= 3'd4;
+                                    if (main_litedramcore_choose_cmd_request[4]) begin
+                                        main_litedramcore_choose_cmd_grant <= 3'd4;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[5]) begin
-                                            litedramcore_choose_cmd_grant <= 3'd5;
+                                        if (main_litedramcore_choose_cmd_request[5]) begin
+                                            main_litedramcore_choose_cmd_grant <= 3'd5;
                                         end
                                     end
                                 end
@@ -13204,26 +13621,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd7: begin
-                if (litedramcore_choose_cmd_request[0]) begin
-                    litedramcore_choose_cmd_grant <= 1'd0;
+                if (main_litedramcore_choose_cmd_request[0]) begin
+                    main_litedramcore_choose_cmd_grant <= 1'd0;
                 end else begin
-                    if (litedramcore_choose_cmd_request[1]) begin
-                        litedramcore_choose_cmd_grant <= 1'd1;
+                    if (main_litedramcore_choose_cmd_request[1]) begin
+                        main_litedramcore_choose_cmd_grant <= 1'd1;
                     end else begin
-                        if (litedramcore_choose_cmd_request[2]) begin
-                            litedramcore_choose_cmd_grant <= 2'd2;
+                        if (main_litedramcore_choose_cmd_request[2]) begin
+                            main_litedramcore_choose_cmd_grant <= 2'd2;
                         end else begin
-                            if (litedramcore_choose_cmd_request[3]) begin
-                                litedramcore_choose_cmd_grant <= 2'd3;
+                            if (main_litedramcore_choose_cmd_request[3]) begin
+                                main_litedramcore_choose_cmd_grant <= 2'd3;
                             end else begin
-                                if (litedramcore_choose_cmd_request[4]) begin
-                                    litedramcore_choose_cmd_grant <= 3'd4;
+                                if (main_litedramcore_choose_cmd_request[4]) begin
+                                    main_litedramcore_choose_cmd_grant <= 3'd4;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[5]) begin
-                                        litedramcore_choose_cmd_grant <= 3'd5;
+                                    if (main_litedramcore_choose_cmd_request[5]) begin
+                                        main_litedramcore_choose_cmd_grant <= 3'd5;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[6]) begin
-                                            litedramcore_choose_cmd_grant <= 3'd6;
+                                        if (main_litedramcore_choose_cmd_request[6]) begin
+                                            main_litedramcore_choose_cmd_grant <= 3'd6;
                                         end
                                     end
                                 end
@@ -13234,29 +13651,29 @@ always @(posedge sys_clk) begin
             end
         endcase
     end
-    if (litedramcore_choose_req_ce) begin
-        case (litedramcore_choose_req_grant)
+    if (main_litedramcore_choose_req_ce) begin
+        case (main_litedramcore_choose_req_grant)
             1'd0: begin
-                if (litedramcore_choose_req_request[1]) begin
-                    litedramcore_choose_req_grant <= 1'd1;
+                if (main_litedramcore_choose_req_request[1]) begin
+                    main_litedramcore_choose_req_grant <= 1'd1;
                 end else begin
-                    if (litedramcore_choose_req_request[2]) begin
-                        litedramcore_choose_req_grant <= 2'd2;
+                    if (main_litedramcore_choose_req_request[2]) begin
+                        main_litedramcore_choose_req_grant <= 2'd2;
                     end else begin
-                        if (litedramcore_choose_req_request[3]) begin
-                            litedramcore_choose_req_grant <= 2'd3;
+                        if (main_litedramcore_choose_req_request[3]) begin
+                            main_litedramcore_choose_req_grant <= 2'd3;
                         end else begin
-                            if (litedramcore_choose_req_request[4]) begin
-                                litedramcore_choose_req_grant <= 3'd4;
+                            if (main_litedramcore_choose_req_request[4]) begin
+                                main_litedramcore_choose_req_grant <= 3'd4;
                             end else begin
-                                if (litedramcore_choose_req_request[5]) begin
-                                    litedramcore_choose_req_grant <= 3'd5;
+                                if (main_litedramcore_choose_req_request[5]) begin
+                                    main_litedramcore_choose_req_grant <= 3'd5;
                                 end else begin
-                                    if (litedramcore_choose_req_request[6]) begin
-                                        litedramcore_choose_req_grant <= 3'd6;
+                                    if (main_litedramcore_choose_req_request[6]) begin
+                                        main_litedramcore_choose_req_grant <= 3'd6;
                                     end else begin
-                                        if (litedramcore_choose_req_request[7]) begin
-                                            litedramcore_choose_req_grant <= 3'd7;
+                                        if (main_litedramcore_choose_req_request[7]) begin
+                                            main_litedramcore_choose_req_grant <= 3'd7;
                                         end
                                     end
                                 end
@@ -13266,26 +13683,26 @@ always @(posedge sys_clk) begin
                 end
             end
             1'd1: begin
-                if (litedramcore_choose_req_request[2]) begin
-                    litedramcore_choose_req_grant <= 2'd2;
+                if (main_litedramcore_choose_req_request[2]) begin
+                    main_litedramcore_choose_req_grant <= 2'd2;
                 end else begin
-                    if (litedramcore_choose_req_request[3]) begin
-                        litedramcore_choose_req_grant <= 2'd3;
+                    if (main_litedramcore_choose_req_request[3]) begin
+                        main_litedramcore_choose_req_grant <= 2'd3;
                     end else begin
-                        if (litedramcore_choose_req_request[4]) begin
-                            litedramcore_choose_req_grant <= 3'd4;
+                        if (main_litedramcore_choose_req_request[4]) begin
+                            main_litedramcore_choose_req_grant <= 3'd4;
                         end else begin
-                            if (litedramcore_choose_req_request[5]) begin
-                                litedramcore_choose_req_grant <= 3'd5;
+                            if (main_litedramcore_choose_req_request[5]) begin
+                                main_litedramcore_choose_req_grant <= 3'd5;
                             end else begin
-                                if (litedramcore_choose_req_request[6]) begin
-                                    litedramcore_choose_req_grant <= 3'd6;
+                                if (main_litedramcore_choose_req_request[6]) begin
+                                    main_litedramcore_choose_req_grant <= 3'd6;
                                 end else begin
-                                    if (litedramcore_choose_req_request[7]) begin
-                                        litedramcore_choose_req_grant <= 3'd7;
+                                    if (main_litedramcore_choose_req_request[7]) begin
+                                        main_litedramcore_choose_req_grant <= 3'd7;
                                     end else begin
-                                        if (litedramcore_choose_req_request[0]) begin
-                                            litedramcore_choose_req_grant <= 1'd0;
+                                        if (main_litedramcore_choose_req_request[0]) begin
+                                            main_litedramcore_choose_req_grant <= 1'd0;
                                         end
                                     end
                                 end
@@ -13295,26 +13712,26 @@ always @(posedge sys_clk) begin
                 end
             end
             2'd2: begin
-                if (litedramcore_choose_req_request[3]) begin
-                    litedramcore_choose_req_grant <= 2'd3;
+                if (main_litedramcore_choose_req_request[3]) begin
+                    main_litedramcore_choose_req_grant <= 2'd3;
                 end else begin
-                    if (litedramcore_choose_req_request[4]) begin
-                        litedramcore_choose_req_grant <= 3'd4;
+                    if (main_litedramcore_choose_req_request[4]) begin
+                        main_litedramcore_choose_req_grant <= 3'd4;
                     end else begin
-                        if (litedramcore_choose_req_request[5]) begin
-                            litedramcore_choose_req_grant <= 3'd5;
+                        if (main_litedramcore_choose_req_request[5]) begin
+                            main_litedramcore_choose_req_grant <= 3'd5;
                         end else begin
-                            if (litedramcore_choose_req_request[6]) begin
-                                litedramcore_choose_req_grant <= 3'd6;
+                            if (main_litedramcore_choose_req_request[6]) begin
+                                main_litedramcore_choose_req_grant <= 3'd6;
                             end else begin
-                                if (litedramcore_choose_req_request[7]) begin
-                                    litedramcore_choose_req_grant <= 3'd7;
+                                if (main_litedramcore_choose_req_request[7]) begin
+                                    main_litedramcore_choose_req_grant <= 3'd7;
                                 end else begin
-                                    if (litedramcore_choose_req_request[0]) begin
-                                        litedramcore_choose_req_grant <= 1'd0;
+                                    if (main_litedramcore_choose_req_request[0]) begin
+                                        main_litedramcore_choose_req_grant <= 1'd0;
                                     end else begin
-                                        if (litedramcore_choose_req_request[1]) begin
-                                            litedramcore_choose_req_grant <= 1'd1;
+                                        if (main_litedramcore_choose_req_request[1]) begin
+                                            main_litedramcore_choose_req_grant <= 1'd1;
                                         end
                                     end
                                 end
@@ -13324,26 +13741,26 @@ always @(posedge sys_clk) begin
                 end
             end
             2'd3: begin
-                if (litedramcore_choose_req_request[4]) begin
-                    litedramcore_choose_req_grant <= 3'd4;
+                if (main_litedramcore_choose_req_request[4]) begin
+                    main_litedramcore_choose_req_grant <= 3'd4;
                 end else begin
-                    if (litedramcore_choose_req_request[5]) begin
-                        litedramcore_choose_req_grant <= 3'd5;
+                    if (main_litedramcore_choose_req_request[5]) begin
+                        main_litedramcore_choose_req_grant <= 3'd5;
                     end else begin
-                        if (litedramcore_choose_req_request[6]) begin
-                            litedramcore_choose_req_grant <= 3'd6;
+                        if (main_litedramcore_choose_req_request[6]) begin
+                            main_litedramcore_choose_req_grant <= 3'd6;
                         end else begin
-                            if (litedramcore_choose_req_request[7]) begin
-                                litedramcore_choose_req_grant <= 3'd7;
+                            if (main_litedramcore_choose_req_request[7]) begin
+                                main_litedramcore_choose_req_grant <= 3'd7;
                             end else begin
-                                if (litedramcore_choose_req_request[0]) begin
-                                    litedramcore_choose_req_grant <= 1'd0;
+                                if (main_litedramcore_choose_req_request[0]) begin
+                                    main_litedramcore_choose_req_grant <= 1'd0;
                                 end else begin
-                                    if (litedramcore_choose_req_request[1]) begin
-                                        litedramcore_choose_req_grant <= 1'd1;
+                                    if (main_litedramcore_choose_req_request[1]) begin
+                                        main_litedramcore_choose_req_grant <= 1'd1;
                                     end else begin
-                                        if (litedramcore_choose_req_request[2]) begin
-                                            litedramcore_choose_req_grant <= 2'd2;
+                                        if (main_litedramcore_choose_req_request[2]) begin
+                                            main_litedramcore_choose_req_grant <= 2'd2;
                                         end
                                     end
                                 end
@@ -13353,26 +13770,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd4: begin
-                if (litedramcore_choose_req_request[5]) begin
-                    litedramcore_choose_req_grant <= 3'd5;
+                if (main_litedramcore_choose_req_request[5]) begin
+                    main_litedramcore_choose_req_grant <= 3'd5;
                 end else begin
-                    if (litedramcore_choose_req_request[6]) begin
-                        litedramcore_choose_req_grant <= 3'd6;
+                    if (main_litedramcore_choose_req_request[6]) begin
+                        main_litedramcore_choose_req_grant <= 3'd6;
                     end else begin
-                        if (litedramcore_choose_req_request[7]) begin
-                            litedramcore_choose_req_grant <= 3'd7;
+                        if (main_litedramcore_choose_req_request[7]) begin
+                            main_litedramcore_choose_req_grant <= 3'd7;
                         end else begin
-                            if (litedramcore_choose_req_request[0]) begin
-                                litedramcore_choose_req_grant <= 1'd0;
+                            if (main_litedramcore_choose_req_request[0]) begin
+                                main_litedramcore_choose_req_grant <= 1'd0;
                             end else begin
-                                if (litedramcore_choose_req_request[1]) begin
-                                    litedramcore_choose_req_grant <= 1'd1;
+                                if (main_litedramcore_choose_req_request[1]) begin
+                                    main_litedramcore_choose_req_grant <= 1'd1;
                                 end else begin
-                                    if (litedramcore_choose_req_request[2]) begin
-                                        litedramcore_choose_req_grant <= 2'd2;
+                                    if (main_litedramcore_choose_req_request[2]) begin
+                                        main_litedramcore_choose_req_grant <= 2'd2;
                                     end else begin
-                                        if (litedramcore_choose_req_request[3]) begin
-                                            litedramcore_choose_req_grant <= 2'd3;
+                                        if (main_litedramcore_choose_req_request[3]) begin
+                                            main_litedramcore_choose_req_grant <= 2'd3;
                                         end
                                     end
                                 end
@@ -13382,26 +13799,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd5: begin
-                if (litedramcore_choose_req_request[6]) begin
-                    litedramcore_choose_req_grant <= 3'd6;
+                if (main_litedramcore_choose_req_request[6]) begin
+                    main_litedramcore_choose_req_grant <= 3'd6;
                 end else begin
-                    if (litedramcore_choose_req_request[7]) begin
-                        litedramcore_choose_req_grant <= 3'd7;
+                    if (main_litedramcore_choose_req_request[7]) begin
+                        main_litedramcore_choose_req_grant <= 3'd7;
                     end else begin
-                        if (litedramcore_choose_req_request[0]) begin
-                            litedramcore_choose_req_grant <= 1'd0;
+                        if (main_litedramcore_choose_req_request[0]) begin
+                            main_litedramcore_choose_req_grant <= 1'd0;
                         end else begin
-                            if (litedramcore_choose_req_request[1]) begin
-                                litedramcore_choose_req_grant <= 1'd1;
+                            if (main_litedramcore_choose_req_request[1]) begin
+                                main_litedramcore_choose_req_grant <= 1'd1;
                             end else begin
-                                if (litedramcore_choose_req_request[2]) begin
-                                    litedramcore_choose_req_grant <= 2'd2;
+                                if (main_litedramcore_choose_req_request[2]) begin
+                                    main_litedramcore_choose_req_grant <= 2'd2;
                                 end else begin
-                                    if (litedramcore_choose_req_request[3]) begin
-                                        litedramcore_choose_req_grant <= 2'd3;
+                                    if (main_litedramcore_choose_req_request[3]) begin
+                                        main_litedramcore_choose_req_grant <= 2'd3;
                                     end else begin
-                                        if (litedramcore_choose_req_request[4]) begin
-                                            litedramcore_choose_req_grant <= 3'd4;
+                                        if (main_litedramcore_choose_req_request[4]) begin
+                                            main_litedramcore_choose_req_grant <= 3'd4;
                                         end
                                     end
                                 end
@@ -13411,26 +13828,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd6: begin
-                if (litedramcore_choose_req_request[7]) begin
-                    litedramcore_choose_req_grant <= 3'd7;
+                if (main_litedramcore_choose_req_request[7]) begin
+                    main_litedramcore_choose_req_grant <= 3'd7;
                 end else begin
-                    if (litedramcore_choose_req_request[0]) begin
-                        litedramcore_choose_req_grant <= 1'd0;
+                    if (main_litedramcore_choose_req_request[0]) begin
+                        main_litedramcore_choose_req_grant <= 1'd0;
                     end else begin
-                        if (litedramcore_choose_req_request[1]) begin
-                            litedramcore_choose_req_grant <= 1'd1;
+                        if (main_litedramcore_choose_req_request[1]) begin
+                            main_litedramcore_choose_req_grant <= 1'd1;
                         end else begin
-                            if (litedramcore_choose_req_request[2]) begin
-                                litedramcore_choose_req_grant <= 2'd2;
+                            if (main_litedramcore_choose_req_request[2]) begin
+                                main_litedramcore_choose_req_grant <= 2'd2;
                             end else begin
-                                if (litedramcore_choose_req_request[3]) begin
-                                    litedramcore_choose_req_grant <= 2'd3;
+                                if (main_litedramcore_choose_req_request[3]) begin
+                                    main_litedramcore_choose_req_grant <= 2'd3;
                                 end else begin
-                                    if (litedramcore_choose_req_request[4]) begin
-                                        litedramcore_choose_req_grant <= 3'd4;
+                                    if (main_litedramcore_choose_req_request[4]) begin
+                                        main_litedramcore_choose_req_grant <= 3'd4;
                                     end else begin
-                                        if (litedramcore_choose_req_request[5]) begin
-                                            litedramcore_choose_req_grant <= 3'd5;
+                                        if (main_litedramcore_choose_req_request[5]) begin
+                                            main_litedramcore_choose_req_grant <= 3'd5;
                                         end
                                     end
                                 end
@@ -13440,26 +13857,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd7: begin
-                if (litedramcore_choose_req_request[0]) begin
-                    litedramcore_choose_req_grant <= 1'd0;
+                if (main_litedramcore_choose_req_request[0]) begin
+                    main_litedramcore_choose_req_grant <= 1'd0;
                 end else begin
-                    if (litedramcore_choose_req_request[1]) begin
-                        litedramcore_choose_req_grant <= 1'd1;
+                    if (main_litedramcore_choose_req_request[1]) begin
+                        main_litedramcore_choose_req_grant <= 1'd1;
                     end else begin
-                        if (litedramcore_choose_req_request[2]) begin
-                            litedramcore_choose_req_grant <= 2'd2;
+                        if (main_litedramcore_choose_req_request[2]) begin
+                            main_litedramcore_choose_req_grant <= 2'd2;
                         end else begin
-                            if (litedramcore_choose_req_request[3]) begin
-                                litedramcore_choose_req_grant <= 2'd3;
+                            if (main_litedramcore_choose_req_request[3]) begin
+                                main_litedramcore_choose_req_grant <= 2'd3;
                             end else begin
-                                if (litedramcore_choose_req_request[4]) begin
-                                    litedramcore_choose_req_grant <= 3'd4;
+                                if (main_litedramcore_choose_req_request[4]) begin
+                                    main_litedramcore_choose_req_grant <= 3'd4;
                                 end else begin
-                                    if (litedramcore_choose_req_request[5]) begin
-                                        litedramcore_choose_req_grant <= 3'd5;
+                                    if (main_litedramcore_choose_req_request[5]) begin
+                                        main_litedramcore_choose_req_grant <= 3'd5;
                                     end else begin
-                                        if (litedramcore_choose_req_request[6]) begin
-                                            litedramcore_choose_req_grant <= 3'd6;
+                                        if (main_litedramcore_choose_req_request[6]) begin
+                                            main_litedramcore_choose_req_grant <= 3'd6;
                                         end
                                     end
                                 end
@@ -13470,644 +13887,644 @@ always @(posedge sys_clk) begin
             end
         endcase
     end
-    litedramcore_dfi_p0_cs_n <= 1'd0;
-    litedramcore_dfi_p0_bank <= array_muxed0;
-    litedramcore_dfi_p0_address <= array_muxed1;
-    litedramcore_dfi_p0_cas_n <= (~array_muxed2);
-    litedramcore_dfi_p0_ras_n <= (~array_muxed3);
-    litedramcore_dfi_p0_we_n <= (~array_muxed4);
-    litedramcore_dfi_p0_rddata_en <= array_muxed5;
-    litedramcore_dfi_p0_wrdata_en <= array_muxed6;
-    litedramcore_dfi_p1_cs_n <= 1'd0;
-    litedramcore_dfi_p1_bank <= array_muxed7;
-    litedramcore_dfi_p1_address <= array_muxed8;
-    litedramcore_dfi_p1_cas_n <= (~array_muxed9);
-    litedramcore_dfi_p1_ras_n <= (~array_muxed10);
-    litedramcore_dfi_p1_we_n <= (~array_muxed11);
-    litedramcore_dfi_p1_rddata_en <= array_muxed12;
-    litedramcore_dfi_p1_wrdata_en <= array_muxed13;
-    litedramcore_dfi_p2_cs_n <= 1'd0;
-    litedramcore_dfi_p2_bank <= array_muxed14;
-    litedramcore_dfi_p2_address <= array_muxed15;
-    litedramcore_dfi_p2_cas_n <= (~array_muxed16);
-    litedramcore_dfi_p2_ras_n <= (~array_muxed17);
-    litedramcore_dfi_p2_we_n <= (~array_muxed18);
-    litedramcore_dfi_p2_rddata_en <= array_muxed19;
-    litedramcore_dfi_p2_wrdata_en <= array_muxed20;
-    litedramcore_dfi_p3_cs_n <= 1'd0;
-    litedramcore_dfi_p3_bank <= array_muxed21;
-    litedramcore_dfi_p3_address <= array_muxed22;
-    litedramcore_dfi_p3_cas_n <= (~array_muxed23);
-    litedramcore_dfi_p3_ras_n <= (~array_muxed24);
-    litedramcore_dfi_p3_we_n <= (~array_muxed25);
-    litedramcore_dfi_p3_rddata_en <= array_muxed26;
-    litedramcore_dfi_p3_wrdata_en <= array_muxed27;
-    if (litedramcore_trrdcon_valid) begin
-        litedramcore_trrdcon_count <= 1'd1;
+    main_litedramcore_dfi_p0_cs_n <= 1'd0;
+    main_litedramcore_dfi_p0_bank <= builder_self0;
+    main_litedramcore_dfi_p0_address <= builder_self1;
+    main_litedramcore_dfi_p0_cas_n <= (~builder_self2);
+    main_litedramcore_dfi_p0_ras_n <= (~builder_self3);
+    main_litedramcore_dfi_p0_we_n <= (~builder_self4);
+    main_litedramcore_dfi_p0_rddata_en <= builder_self5;
+    main_litedramcore_dfi_p0_wrdata_en <= builder_self6;
+    main_litedramcore_dfi_p1_cs_n <= 1'd0;
+    main_litedramcore_dfi_p1_bank <= builder_self7;
+    main_litedramcore_dfi_p1_address <= builder_self8;
+    main_litedramcore_dfi_p1_cas_n <= (~builder_self9);
+    main_litedramcore_dfi_p1_ras_n <= (~builder_self10);
+    main_litedramcore_dfi_p1_we_n <= (~builder_self11);
+    main_litedramcore_dfi_p1_rddata_en <= builder_self12;
+    main_litedramcore_dfi_p1_wrdata_en <= builder_self13;
+    main_litedramcore_dfi_p2_cs_n <= 1'd0;
+    main_litedramcore_dfi_p2_bank <= builder_self14;
+    main_litedramcore_dfi_p2_address <= builder_self15;
+    main_litedramcore_dfi_p2_cas_n <= (~builder_self16);
+    main_litedramcore_dfi_p2_ras_n <= (~builder_self17);
+    main_litedramcore_dfi_p2_we_n <= (~builder_self18);
+    main_litedramcore_dfi_p2_rddata_en <= builder_self19;
+    main_litedramcore_dfi_p2_wrdata_en <= builder_self20;
+    main_litedramcore_dfi_p3_cs_n <= 1'd0;
+    main_litedramcore_dfi_p3_bank <= builder_self21;
+    main_litedramcore_dfi_p3_address <= builder_self22;
+    main_litedramcore_dfi_p3_cas_n <= (~builder_self23);
+    main_litedramcore_dfi_p3_ras_n <= (~builder_self24);
+    main_litedramcore_dfi_p3_we_n <= (~builder_self25);
+    main_litedramcore_dfi_p3_rddata_en <= builder_self26;
+    main_litedramcore_dfi_p3_wrdata_en <= builder_self27;
+    if (main_litedramcore_trrdcon_valid) begin
+        main_litedramcore_trrdcon_count <= 1'd1;
         if (1'd0) begin
-            litedramcore_trrdcon_ready <= 1'd1;
+            main_litedramcore_trrdcon_ready <= 1'd1;
         end else begin
-            litedramcore_trrdcon_ready <= 1'd0;
+            main_litedramcore_trrdcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_trrdcon_ready)) begin
-            litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
-            if ((litedramcore_trrdcon_count == 1'd1)) begin
-                litedramcore_trrdcon_ready <= 1'd1;
+        if ((~main_litedramcore_trrdcon_ready)) begin
+            main_litedramcore_trrdcon_count <= (main_litedramcore_trrdcon_count - 1'd1);
+            if ((main_litedramcore_trrdcon_count == 1'd1)) begin
+                main_litedramcore_trrdcon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
-    if ((litedramcore_tfawcon_count < 3'd4)) begin
-        if ((litedramcore_tfawcon_count == 2'd3)) begin
-            litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
+    main_litedramcore_tfawcon_window <= {main_litedramcore_tfawcon_window, main_litedramcore_tfawcon_valid};
+    if ((main_litedramcore_tfawcon_count < 3'd4)) begin
+        if ((main_litedramcore_tfawcon_count == 2'd3)) begin
+            main_litedramcore_tfawcon_ready <= (~main_litedramcore_tfawcon_valid);
         end else begin
-            litedramcore_tfawcon_ready <= 1'd1;
+            main_litedramcore_tfawcon_ready <= 1'd1;
         end
     end
-    if (litedramcore_tccdcon_valid) begin
-        litedramcore_tccdcon_count <= 1'd0;
+    if (main_litedramcore_tccdcon_valid) begin
+        main_litedramcore_tccdcon_count <= 1'd0;
         if (1'd1) begin
-            litedramcore_tccdcon_ready <= 1'd1;
+            main_litedramcore_tccdcon_ready <= 1'd1;
         end else begin
-            litedramcore_tccdcon_ready <= 1'd0;
+            main_litedramcore_tccdcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_tccdcon_ready)) begin
-            litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
-            if ((litedramcore_tccdcon_count == 1'd1)) begin
-                litedramcore_tccdcon_ready <= 1'd1;
+        if ((~main_litedramcore_tccdcon_ready)) begin
+            main_litedramcore_tccdcon_count <= (main_litedramcore_tccdcon_count - 1'd1);
+            if ((main_litedramcore_tccdcon_count == 1'd1)) begin
+                main_litedramcore_tccdcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_twtrcon_valid) begin
-        litedramcore_twtrcon_count <= 3'd4;
+    if (main_litedramcore_twtrcon_valid) begin
+        main_litedramcore_twtrcon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_twtrcon_ready <= 1'd1;
+            main_litedramcore_twtrcon_ready <= 1'd1;
         end else begin
-            litedramcore_twtrcon_ready <= 1'd0;
+            main_litedramcore_twtrcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_twtrcon_ready)) begin
-            litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
-            if ((litedramcore_twtrcon_count == 1'd1)) begin
-                litedramcore_twtrcon_ready <= 1'd1;
-            end
-        end
-    end
-    litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
-    litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
-    litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
-    litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
-    litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
-    litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
-    litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
-    litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
-    litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
-    litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
-    litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
-    litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
-    litedramcore_state <= litedramcore_next_state;
-    if (litedramcore_dat_w_next_value_ce0) begin
-        litedramcore_dat_w <= litedramcore_dat_w_next_value0;
-    end
-    if (litedramcore_adr_next_value_ce1) begin
-        litedramcore_adr <= litedramcore_adr_next_value1;
-    end
-    if (litedramcore_we_next_value_ce2) begin
-        litedramcore_we <= litedramcore_we_next_value2;
-    end
-    interface0_bank_bus_dat_r <= 1'd0;
-    if (csrbank0_sel) begin
-        case (interface0_bank_bus_adr[8:0])
+        if ((~main_litedramcore_twtrcon_ready)) begin
+            main_litedramcore_twtrcon_count <= (main_litedramcore_twtrcon_count - 1'd1);
+            if ((main_litedramcore_twtrcon_count == 1'd1)) begin
+                main_litedramcore_twtrcon_ready <= 1'd1;
+            end
+        end
+    end
+    builder_multiplexer_state <= builder_multiplexer_next_state;
+    builder_new_master_wdata_ready0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_wdata_ready)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_wdata_ready)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_wdata_ready)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_wdata_ready)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_wdata_ready)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_wdata_ready)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_wdata_ready)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_wdata_ready));
+    builder_new_master_wdata_ready1 <= builder_new_master_wdata_ready0;
+    builder_new_master_rdata_valid0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_rdata_valid)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_rdata_valid)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_rdata_valid)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_rdata_valid)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_rdata_valid)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_rdata_valid)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_rdata_valid)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_rdata_valid));
+    builder_new_master_rdata_valid1 <= builder_new_master_rdata_valid0;
+    builder_new_master_rdata_valid2 <= builder_new_master_rdata_valid1;
+    builder_new_master_rdata_valid3 <= builder_new_master_rdata_valid2;
+    builder_new_master_rdata_valid4 <= builder_new_master_rdata_valid3;
+    builder_new_master_rdata_valid5 <= builder_new_master_rdata_valid4;
+    builder_new_master_rdata_valid6 <= builder_new_master_rdata_valid5;
+    builder_new_master_rdata_valid7 <= builder_new_master_rdata_valid6;
+    builder_new_master_rdata_valid8 <= builder_new_master_rdata_valid7;
+    builder_state <= builder_next_state;
+    if (builder_interface1_dat_w_next_value_ce0) begin
+        builder_interface1_dat_w <= builder_interface1_dat_w_next_value0;
+    end
+    if (builder_interface1_adr_next_value_ce1) begin
+        builder_interface1_adr <= builder_interface1_adr_next_value1;
+    end
+    if (builder_interface1_we_next_value_ce2) begin
+        builder_interface1_we <= builder_interface1_we_next_value2;
+    end
+    builder_interface0_bank_bus_dat_r <= 1'd0;
+    if (builder_csrbank0_sel) begin
+        case (builder_interface0_bank_bus_adr[8:0])
             1'd0: begin
-                interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
+                builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_done0_w;
             end
             1'd1: begin
-                interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
+                builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_error0_w;
             end
         endcase
     end
-    if (csrbank0_init_done0_re) begin
-        init_done_storage <= csrbank0_init_done0_r;
+    if (builder_csrbank0_init_done0_re) begin
+        main_init_done_storage <= builder_csrbank0_init_done0_r;
     end
-    init_done_re <= csrbank0_init_done0_re;
-    if (csrbank0_init_error0_re) begin
-        init_error_storage <= csrbank0_init_error0_r;
+    main_init_done_re <= builder_csrbank0_init_done0_re;
+    if (builder_csrbank0_init_error0_re) begin
+        main_init_error_storage <= builder_csrbank0_init_error0_r;
     end
-    init_error_re <= csrbank0_init_error0_re;
-    interface1_bank_bus_dat_r <= 1'd0;
-    if (csrbank1_sel) begin
-        case (interface1_bank_bus_adr[8:0])
+    main_init_error_re <= builder_csrbank0_init_error0_re;
+    builder_interface1_bank_bus_dat_r <= 1'd0;
+    if (builder_csrbank1_sel) begin
+        case (builder_interface1_bank_bus_adr[8:0])
             1'd0: begin
-                interface1_bank_bus_dat_r <= csrbank1_rst0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_rst0_w;
             end
             1'd1: begin
-                interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_dly_sel0_w;
             end
             2'd2: begin
-                interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_half_sys8x_taps0_w;
             end
             2'd3: begin
-                interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_wlevel_en0_w;
             end
             3'd4: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wlevel_strobe_w;
             end
             3'd5: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_rst_w;
             end
             3'd6: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_inc_w;
             end
             3'd7: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_rst_w;
             end
             4'd8: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_w;
             end
             4'd9: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_rst_w;
             end
             4'd10: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_w;
             end
             4'd11: begin
-                interface1_bank_bus_dat_r <= csrbank1_rdphase0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_rdphase0_w;
             end
             4'd12: begin
-                interface1_bank_bus_dat_r <= csrbank1_wrphase0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_wrphase0_w;
             end
         endcase
     end
-    if (csrbank1_rst0_re) begin
-        a7ddrphy_rst_storage <= csrbank1_rst0_r;
+    if (builder_csrbank1_rst0_re) begin
+        main_a7ddrphy_rst_storage <= builder_csrbank1_rst0_r;
     end
-    a7ddrphy_rst_re <= csrbank1_rst0_re;
-    if (csrbank1_dly_sel0_re) begin
-        a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r;
+    main_a7ddrphy_rst_re <= builder_csrbank1_rst0_re;
+    if (builder_csrbank1_dly_sel0_re) begin
+        main_a7ddrphy_dly_sel_storage[1:0] <= builder_csrbank1_dly_sel0_r;
     end
-    a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
-    if (csrbank1_half_sys8x_taps0_re) begin
-        a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r;
+    main_a7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re;
+    if (builder_csrbank1_half_sys8x_taps0_re) begin
+        main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r;
     end
-    a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re;
-    if (csrbank1_wlevel_en0_re) begin
-        a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r;
+    main_a7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re;
+    if (builder_csrbank1_wlevel_en0_re) begin
+        main_a7ddrphy_wlevel_en_storage <= builder_csrbank1_wlevel_en0_r;
     end
-    a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re;
-    if (csrbank1_rdphase0_re) begin
-        a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r;
+    main_a7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re;
+    if (builder_csrbank1_rdphase0_re) begin
+        main_a7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r;
     end
-    a7ddrphy_rdphase_re <= csrbank1_rdphase0_re;
-    if (csrbank1_wrphase0_re) begin
-        a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r;
+    main_a7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re;
+    if (builder_csrbank1_wrphase0_re) begin
+        main_a7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r;
     end
-    a7ddrphy_wrphase_re <= csrbank1_wrphase0_re;
-    interface2_bank_bus_dat_r <= 1'd0;
-    if (csrbank2_sel) begin
-        case (interface2_bank_bus_adr[8:0])
+    main_a7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re;
+    builder_interface2_bank_bus_dat_r <= 1'd0;
+    if (builder_csrbank2_sel) begin
+        case (builder_interface2_bank_bus_adr[8:0])
             1'd0: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_control0_w;
             end
             1'd1: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_command0_w;
             end
             2'd2: begin
-                interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
+                builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w;
             end
             2'd3: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w;
             end
             3'd4: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w;
             end
             3'd5: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w;
             end
             3'd6: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata_w;
             end
             3'd7: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w;
             end
             4'd8: begin
-                interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
+                builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w;
             end
             4'd9: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w;
             end
             4'd10: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w;
             end
             4'd11: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w;
             end
             4'd12: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata_w;
             end
             4'd13: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w;
             end
             4'd14: begin
-                interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
+                builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w;
             end
             4'd15: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w;
             end
             5'd16: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w;
             end
             5'd17: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w;
             end
             5'd18: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata_w;
             end
             5'd19: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w;
             end
             5'd20: begin
-                interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
+                builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w;
             end
             5'd21: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w;
             end
             5'd22: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w;
             end
             5'd23: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w;
             end
             5'd24: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata_w;
             end
         endcase
     end
-    if (csrbank2_dfii_control0_re) begin
-        litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
+    if (builder_csrbank2_dfii_control0_re) begin
+        main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r;
     end
-    litedramcore_re <= csrbank2_dfii_control0_re;
-    if (csrbank2_dfii_pi0_command0_re) begin
-        litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
+    main_litedramcore_re <= builder_csrbank2_dfii_control0_re;
+    if (builder_csrbank2_dfii_pi0_command0_re) begin
+        main_litedramcore_phaseinjector0_command_storage[7:0] <= builder_csrbank2_dfii_pi0_command0_r;
     end
-    litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
-    if (csrbank2_dfii_pi0_address0_re) begin
-        litedramcore_phaseinjector0_address_storage[15:0] <= csrbank2_dfii_pi0_address0_r;
+    main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re;
+    if (builder_csrbank2_dfii_pi0_address0_re) begin
+        main_litedramcore_phaseinjector0_address_storage[15:0] <= builder_csrbank2_dfii_pi0_address0_r;
     end
-    litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
-    if (csrbank2_dfii_pi0_baddress0_re) begin
-        litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
+    main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re;
+    if (builder_csrbank2_dfii_pi0_baddress0_re) begin
+        main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r;
     end
-    litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
-    if (csrbank2_dfii_pi0_wrdata0_re) begin
-        litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
+    main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re;
+    if (builder_csrbank2_dfii_pi0_wrdata0_re) begin
+        main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r;
     end
-    litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
-    litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re;
-    if (csrbank2_dfii_pi1_command0_re) begin
-        litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
+    main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re;
+    main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re;
+    if (builder_csrbank2_dfii_pi1_command0_re) begin
+        main_litedramcore_phaseinjector1_command_storage[7:0] <= builder_csrbank2_dfii_pi1_command0_r;
     end
-    litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
-    if (csrbank2_dfii_pi1_address0_re) begin
-        litedramcore_phaseinjector1_address_storage[15:0] <= csrbank2_dfii_pi1_address0_r;
+    main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re;
+    if (builder_csrbank2_dfii_pi1_address0_re) begin
+        main_litedramcore_phaseinjector1_address_storage[15:0] <= builder_csrbank2_dfii_pi1_address0_r;
     end
-    litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
-    if (csrbank2_dfii_pi1_baddress0_re) begin
-        litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
+    main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re;
+    if (builder_csrbank2_dfii_pi1_baddress0_re) begin
+        main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r;
     end
-    litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
-    if (csrbank2_dfii_pi1_wrdata0_re) begin
-        litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
+    main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re;
+    if (builder_csrbank2_dfii_pi1_wrdata0_re) begin
+        main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r;
     end
-    litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
-    litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re;
-    if (csrbank2_dfii_pi2_command0_re) begin
-        litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
+    main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re;
+    main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re;
+    if (builder_csrbank2_dfii_pi2_command0_re) begin
+        main_litedramcore_phaseinjector2_command_storage[7:0] <= builder_csrbank2_dfii_pi2_command0_r;
     end
-    litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
-    if (csrbank2_dfii_pi2_address0_re) begin
-        litedramcore_phaseinjector2_address_storage[15:0] <= csrbank2_dfii_pi2_address0_r;
+    main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re;
+    if (builder_csrbank2_dfii_pi2_address0_re) begin
+        main_litedramcore_phaseinjector2_address_storage[15:0] <= builder_csrbank2_dfii_pi2_address0_r;
     end
-    litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
-    if (csrbank2_dfii_pi2_baddress0_re) begin
-        litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
+    main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re;
+    if (builder_csrbank2_dfii_pi2_baddress0_re) begin
+        main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r;
     end
-    litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
-    if (csrbank2_dfii_pi2_wrdata0_re) begin
-        litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
+    main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re;
+    if (builder_csrbank2_dfii_pi2_wrdata0_re) begin
+        main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r;
     end
-    litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
-    litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re;
-    if (csrbank2_dfii_pi3_command0_re) begin
-        litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
+    main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re;
+    main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re;
+    if (builder_csrbank2_dfii_pi3_command0_re) begin
+        main_litedramcore_phaseinjector3_command_storage[7:0] <= builder_csrbank2_dfii_pi3_command0_r;
     end
-    litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
-    if (csrbank2_dfii_pi3_address0_re) begin
-        litedramcore_phaseinjector3_address_storage[15:0] <= csrbank2_dfii_pi3_address0_r;
+    main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re;
+    if (builder_csrbank2_dfii_pi3_address0_re) begin
+        main_litedramcore_phaseinjector3_address_storage[15:0] <= builder_csrbank2_dfii_pi3_address0_r;
     end
-    litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
-    if (csrbank2_dfii_pi3_baddress0_re) begin
-        litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
+    main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re;
+    if (builder_csrbank2_dfii_pi3_baddress0_re) begin
+        main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r;
     end
-    litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
-    if (csrbank2_dfii_pi3_wrdata0_re) begin
-        litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
+    main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re;
+    if (builder_csrbank2_dfii_pi3_wrdata0_re) begin
+        main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r;
     end
-    litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
-    litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re;
+    main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re;
+    main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re;
     if (sys_rst) begin
-        a7ddrphy_rst_storage <= 1'd0;
-        a7ddrphy_rst_re <= 1'd0;
-        a7ddrphy_dly_sel_storage <= 2'd0;
-        a7ddrphy_dly_sel_re <= 1'd0;
-        a7ddrphy_half_sys8x_taps_storage <= 5'd8;
-        a7ddrphy_half_sys8x_taps_re <= 1'd0;
-        a7ddrphy_wlevel_en_storage <= 1'd0;
-        a7ddrphy_wlevel_en_re <= 1'd0;
-        a7ddrphy_rdphase_storage <= 2'd2;
-        a7ddrphy_rdphase_re <= 1'd0;
-        a7ddrphy_wrphase_storage <= 2'd3;
-        a7ddrphy_wrphase_re <= 1'd0;
-        a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
-        a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
-        a7ddrphy_dqspattern_o1 <= 8'd0;
-        a7ddrphy_bitslip0_value0 <= 3'd7;
-        a7ddrphy_bitslip1_value0 <= 3'd7;
-        a7ddrphy_bitslip0_value1 <= 3'd7;
-        a7ddrphy_bitslip1_value1 <= 3'd7;
-        a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
-        a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
-        a7ddrphy_bitslip0_value2 <= 3'd7;
-        a7ddrphy_bitslip0_value3 <= 3'd7;
-        a7ddrphy_bitslip1_value2 <= 3'd7;
-        a7ddrphy_bitslip1_value3 <= 3'd7;
-        a7ddrphy_bitslip2_value0 <= 3'd7;
-        a7ddrphy_bitslip2_value1 <= 3'd7;
-        a7ddrphy_bitslip3_value0 <= 3'd7;
-        a7ddrphy_bitslip3_value1 <= 3'd7;
-        a7ddrphy_bitslip4_value0 <= 3'd7;
-        a7ddrphy_bitslip4_value1 <= 3'd7;
-        a7ddrphy_bitslip5_value0 <= 3'd7;
-        a7ddrphy_bitslip5_value1 <= 3'd7;
-        a7ddrphy_bitslip6_value0 <= 3'd7;
-        a7ddrphy_bitslip6_value1 <= 3'd7;
-        a7ddrphy_bitslip7_value0 <= 3'd7;
-        a7ddrphy_bitslip7_value1 <= 3'd7;
-        a7ddrphy_bitslip8_value0 <= 3'd7;
-        a7ddrphy_bitslip8_value1 <= 3'd7;
-        a7ddrphy_bitslip9_value0 <= 3'd7;
-        a7ddrphy_bitslip9_value1 <= 3'd7;
-        a7ddrphy_bitslip10_value0 <= 3'd7;
-        a7ddrphy_bitslip10_value1 <= 3'd7;
-        a7ddrphy_bitslip11_value0 <= 3'd7;
-        a7ddrphy_bitslip11_value1 <= 3'd7;
-        a7ddrphy_bitslip12_value0 <= 3'd7;
-        a7ddrphy_bitslip12_value1 <= 3'd7;
-        a7ddrphy_bitslip13_value0 <= 3'd7;
-        a7ddrphy_bitslip13_value1 <= 3'd7;
-        a7ddrphy_bitslip14_value0 <= 3'd7;
-        a7ddrphy_bitslip14_value1 <= 3'd7;
-        a7ddrphy_bitslip15_value0 <= 3'd7;
-        a7ddrphy_bitslip15_value1 <= 3'd7;
-        a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
-        a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
-        a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
-        a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
-        litedramcore_storage <= 4'd1;
-        litedramcore_re <= 1'd0;
-        litedramcore_phaseinjector0_command_storage <= 6'd0;
-        litedramcore_phaseinjector0_command_re <= 1'd0;
-        litedramcore_phaseinjector0_address_re <= 1'd0;
-        litedramcore_phaseinjector0_baddress_re <= 1'd0;
-        litedramcore_phaseinjector0_wrdata_re <= 1'd0;
-        litedramcore_phaseinjector0_rddata_status <= 32'd0;
-        litedramcore_phaseinjector0_rddata_re <= 1'd0;
-        litedramcore_phaseinjector1_command_storage <= 6'd0;
-        litedramcore_phaseinjector1_command_re <= 1'd0;
-        litedramcore_phaseinjector1_address_re <= 1'd0;
-        litedramcore_phaseinjector1_baddress_re <= 1'd0;
-        litedramcore_phaseinjector1_wrdata_re <= 1'd0;
-        litedramcore_phaseinjector1_rddata_status <= 32'd0;
-        litedramcore_phaseinjector1_rddata_re <= 1'd0;
-        litedramcore_phaseinjector2_command_storage <= 6'd0;
-        litedramcore_phaseinjector2_command_re <= 1'd0;
-        litedramcore_phaseinjector2_address_re <= 1'd0;
-        litedramcore_phaseinjector2_baddress_re <= 1'd0;
-        litedramcore_phaseinjector2_wrdata_re <= 1'd0;
-        litedramcore_phaseinjector2_rddata_status <= 32'd0;
-        litedramcore_phaseinjector2_rddata_re <= 1'd0;
-        litedramcore_phaseinjector3_command_storage <= 6'd0;
-        litedramcore_phaseinjector3_command_re <= 1'd0;
-        litedramcore_phaseinjector3_address_re <= 1'd0;
-        litedramcore_phaseinjector3_baddress_re <= 1'd0;
-        litedramcore_phaseinjector3_wrdata_re <= 1'd0;
-        litedramcore_phaseinjector3_rddata_status <= 32'd0;
-        litedramcore_phaseinjector3_rddata_re <= 1'd0;
-        litedramcore_dfi_p0_address <= 16'd0;
-        litedramcore_dfi_p0_bank <= 3'd0;
-        litedramcore_dfi_p0_cas_n <= 1'd1;
-        litedramcore_dfi_p0_cs_n <= 1'd1;
-        litedramcore_dfi_p0_ras_n <= 1'd1;
-        litedramcore_dfi_p0_we_n <= 1'd1;
-        litedramcore_dfi_p0_wrdata_en <= 1'd0;
-        litedramcore_dfi_p0_rddata_en <= 1'd0;
-        litedramcore_dfi_p1_address <= 16'd0;
-        litedramcore_dfi_p1_bank <= 3'd0;
-        litedramcore_dfi_p1_cas_n <= 1'd1;
-        litedramcore_dfi_p1_cs_n <= 1'd1;
-        litedramcore_dfi_p1_ras_n <= 1'd1;
-        litedramcore_dfi_p1_we_n <= 1'd1;
-        litedramcore_dfi_p1_wrdata_en <= 1'd0;
-        litedramcore_dfi_p1_rddata_en <= 1'd0;
-        litedramcore_dfi_p2_address <= 16'd0;
-        litedramcore_dfi_p2_bank <= 3'd0;
-        litedramcore_dfi_p2_cas_n <= 1'd1;
-        litedramcore_dfi_p2_cs_n <= 1'd1;
-        litedramcore_dfi_p2_ras_n <= 1'd1;
-        litedramcore_dfi_p2_we_n <= 1'd1;
-        litedramcore_dfi_p2_wrdata_en <= 1'd0;
-        litedramcore_dfi_p2_rddata_en <= 1'd0;
-        litedramcore_dfi_p3_address <= 16'd0;
-        litedramcore_dfi_p3_bank <= 3'd0;
-        litedramcore_dfi_p3_cas_n <= 1'd1;
-        litedramcore_dfi_p3_cs_n <= 1'd1;
-        litedramcore_dfi_p3_ras_n <= 1'd1;
-        litedramcore_dfi_p3_we_n <= 1'd1;
-        litedramcore_dfi_p3_wrdata_en <= 1'd0;
-        litedramcore_dfi_p3_rddata_en <= 1'd0;
-        litedramcore_cmd_payload_a <= 16'd0;
-        litedramcore_cmd_payload_ba <= 3'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd0;
-        litedramcore_cmd_payload_we <= 1'd0;
-        litedramcore_timer_count1 <= 10'd781;
-        litedramcore_postponer_req_o <= 1'd0;
-        litedramcore_postponer_count <= 1'd0;
-        litedramcore_sequencer_done1 <= 1'd0;
-        litedramcore_sequencer_counter <= 7'd0;
-        litedramcore_sequencer_count <= 1'd0;
-        litedramcore_zqcs_timer_count1 <= 27'd99999999;
-        litedramcore_zqcs_executer_done <= 1'd0;
-        litedramcore_zqcs_executer_counter <= 5'd0;
-        litedramcore_bankmachine0_level <= 5'd0;
-        litedramcore_bankmachine0_produce <= 4'd0;
-        litedramcore_bankmachine0_consume <= 4'd0;
-        litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 23'd0;
-        litedramcore_bankmachine0_row <= 16'd0;
-        litedramcore_bankmachine0_row_opened <= 1'd0;
-        litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine0_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine0_trccon_ready <= 1'd0;
-        litedramcore_bankmachine0_trccon_count <= 3'd0;
-        litedramcore_bankmachine0_trascon_ready <= 1'd0;
-        litedramcore_bankmachine0_trascon_count <= 3'd0;
-        litedramcore_bankmachine1_level <= 5'd0;
-        litedramcore_bankmachine1_produce <= 4'd0;
-        litedramcore_bankmachine1_consume <= 4'd0;
-        litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 23'd0;
-        litedramcore_bankmachine1_row <= 16'd0;
-        litedramcore_bankmachine1_row_opened <= 1'd0;
-        litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine1_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine1_trccon_ready <= 1'd0;
-        litedramcore_bankmachine1_trccon_count <= 3'd0;
-        litedramcore_bankmachine1_trascon_ready <= 1'd0;
-        litedramcore_bankmachine1_trascon_count <= 3'd0;
-        litedramcore_bankmachine2_level <= 5'd0;
-        litedramcore_bankmachine2_produce <= 4'd0;
-        litedramcore_bankmachine2_consume <= 4'd0;
-        litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 23'd0;
-        litedramcore_bankmachine2_row <= 16'd0;
-        litedramcore_bankmachine2_row_opened <= 1'd0;
-        litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine2_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine2_trccon_ready <= 1'd0;
-        litedramcore_bankmachine2_trccon_count <= 3'd0;
-        litedramcore_bankmachine2_trascon_ready <= 1'd0;
-        litedramcore_bankmachine2_trascon_count <= 3'd0;
-        litedramcore_bankmachine3_level <= 5'd0;
-        litedramcore_bankmachine3_produce <= 4'd0;
-        litedramcore_bankmachine3_consume <= 4'd0;
-        litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 23'd0;
-        litedramcore_bankmachine3_row <= 16'd0;
-        litedramcore_bankmachine3_row_opened <= 1'd0;
-        litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine3_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine3_trccon_ready <= 1'd0;
-        litedramcore_bankmachine3_trccon_count <= 3'd0;
-        litedramcore_bankmachine3_trascon_ready <= 1'd0;
-        litedramcore_bankmachine3_trascon_count <= 3'd0;
-        litedramcore_bankmachine4_level <= 5'd0;
-        litedramcore_bankmachine4_produce <= 4'd0;
-        litedramcore_bankmachine4_consume <= 4'd0;
-        litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 23'd0;
-        litedramcore_bankmachine4_row <= 16'd0;
-        litedramcore_bankmachine4_row_opened <= 1'd0;
-        litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine4_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine4_trccon_ready <= 1'd0;
-        litedramcore_bankmachine4_trccon_count <= 3'd0;
-        litedramcore_bankmachine4_trascon_ready <= 1'd0;
-        litedramcore_bankmachine4_trascon_count <= 3'd0;
-        litedramcore_bankmachine5_level <= 5'd0;
-        litedramcore_bankmachine5_produce <= 4'd0;
-        litedramcore_bankmachine5_consume <= 4'd0;
-        litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 23'd0;
-        litedramcore_bankmachine5_row <= 16'd0;
-        litedramcore_bankmachine5_row_opened <= 1'd0;
-        litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine5_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine5_trccon_ready <= 1'd0;
-        litedramcore_bankmachine5_trccon_count <= 3'd0;
-        litedramcore_bankmachine5_trascon_ready <= 1'd0;
-        litedramcore_bankmachine5_trascon_count <= 3'd0;
-        litedramcore_bankmachine6_level <= 5'd0;
-        litedramcore_bankmachine6_produce <= 4'd0;
-        litedramcore_bankmachine6_consume <= 4'd0;
-        litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 23'd0;
-        litedramcore_bankmachine6_row <= 16'd0;
-        litedramcore_bankmachine6_row_opened <= 1'd0;
-        litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine6_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine6_trccon_ready <= 1'd0;
-        litedramcore_bankmachine6_trccon_count <= 3'd0;
-        litedramcore_bankmachine6_trascon_ready <= 1'd0;
-        litedramcore_bankmachine6_trascon_count <= 3'd0;
-        litedramcore_bankmachine7_level <= 5'd0;
-        litedramcore_bankmachine7_produce <= 4'd0;
-        litedramcore_bankmachine7_consume <= 4'd0;
-        litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 23'd0;
-        litedramcore_bankmachine7_row <= 16'd0;
-        litedramcore_bankmachine7_row_opened <= 1'd0;
-        litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine7_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine7_trccon_ready <= 1'd0;
-        litedramcore_bankmachine7_trccon_count <= 3'd0;
-        litedramcore_bankmachine7_trascon_ready <= 1'd0;
-        litedramcore_bankmachine7_trascon_count <= 3'd0;
-        litedramcore_choose_cmd_grant <= 3'd0;
-        litedramcore_choose_req_grant <= 3'd0;
-        litedramcore_trrdcon_ready <= 1'd0;
-        litedramcore_trrdcon_count <= 1'd0;
-        litedramcore_tfawcon_ready <= 1'd1;
-        litedramcore_tfawcon_window <= 5'd0;
-        litedramcore_tccdcon_ready <= 1'd0;
-        litedramcore_tccdcon_count <= 1'd0;
-        litedramcore_twtrcon_ready <= 1'd0;
-        litedramcore_twtrcon_count <= 3'd0;
-        litedramcore_time0 <= 5'd0;
-        litedramcore_time1 <= 4'd0;
-        init_done_storage <= 1'd0;
-        init_done_re <= 1'd0;
-        init_error_storage <= 1'd0;
-        init_error_re <= 1'd0;
-        litedramcore_we <= 1'd0;
-        litedramcore_refresher_state <= 2'd0;
-        litedramcore_bankmachine0_state <= 4'd0;
-        litedramcore_bankmachine1_state <= 4'd0;
-        litedramcore_bankmachine2_state <= 4'd0;
-        litedramcore_bankmachine3_state <= 4'd0;
-        litedramcore_bankmachine4_state <= 4'd0;
-        litedramcore_bankmachine5_state <= 4'd0;
-        litedramcore_bankmachine6_state <= 4'd0;
-        litedramcore_bankmachine7_state <= 4'd0;
-        litedramcore_multiplexer_state <= 4'd0;
-        litedramcore_new_master_wdata_ready0 <= 1'd0;
-        litedramcore_new_master_wdata_ready1 <= 1'd0;
-        litedramcore_new_master_rdata_valid0 <= 1'd0;
-        litedramcore_new_master_rdata_valid1 <= 1'd0;
-        litedramcore_new_master_rdata_valid2 <= 1'd0;
-        litedramcore_new_master_rdata_valid3 <= 1'd0;
-        litedramcore_new_master_rdata_valid4 <= 1'd0;
-        litedramcore_new_master_rdata_valid5 <= 1'd0;
-        litedramcore_new_master_rdata_valid6 <= 1'd0;
-        litedramcore_new_master_rdata_valid7 <= 1'd0;
-        litedramcore_new_master_rdata_valid8 <= 1'd0;
-        litedramcore_state <= 2'd0;
+        main_a7ddrphy_rst_storage <= 1'd0;
+        main_a7ddrphy_rst_re <= 1'd0;
+        main_a7ddrphy_dly_sel_storage <= 2'd0;
+        main_a7ddrphy_dly_sel_re <= 1'd0;
+        main_a7ddrphy_half_sys8x_taps_storage <= 5'd8;
+        main_a7ddrphy_half_sys8x_taps_re <= 1'd0;
+        main_a7ddrphy_wlevel_en_storage <= 1'd0;
+        main_a7ddrphy_wlevel_en_re <= 1'd0;
+        main_a7ddrphy_rdphase_storage <= 2'd2;
+        main_a7ddrphy_rdphase_re <= 1'd0;
+        main_a7ddrphy_wrphase_storage <= 2'd3;
+        main_a7ddrphy_wrphase_re <= 1'd0;
+        main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+        main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+        main_a7ddrphy_dqspattern_o1 <= 8'd0;
+        main_a7ddrphy_bitslip0_value0 <= 3'd7;
+        main_a7ddrphy_bitslip1_value0 <= 3'd7;
+        main_a7ddrphy_bitslip0_value1 <= 3'd7;
+        main_a7ddrphy_bitslip1_value1 <= 3'd7;
+        main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+        main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+        main_a7ddrphy_bitslip0_value2 <= 3'd7;
+        main_a7ddrphy_bitslip0_value3 <= 3'd7;
+        main_a7ddrphy_bitslip1_value2 <= 3'd7;
+        main_a7ddrphy_bitslip1_value3 <= 3'd7;
+        main_a7ddrphy_bitslip2_value0 <= 3'd7;
+        main_a7ddrphy_bitslip2_value1 <= 3'd7;
+        main_a7ddrphy_bitslip3_value0 <= 3'd7;
+        main_a7ddrphy_bitslip3_value1 <= 3'd7;
+        main_a7ddrphy_bitslip4_value0 <= 3'd7;
+        main_a7ddrphy_bitslip4_value1 <= 3'd7;
+        main_a7ddrphy_bitslip5_value0 <= 3'd7;
+        main_a7ddrphy_bitslip5_value1 <= 3'd7;
+        main_a7ddrphy_bitslip6_value0 <= 3'd7;
+        main_a7ddrphy_bitslip6_value1 <= 3'd7;
+        main_a7ddrphy_bitslip7_value0 <= 3'd7;
+        main_a7ddrphy_bitslip7_value1 <= 3'd7;
+        main_a7ddrphy_bitslip8_value0 <= 3'd7;
+        main_a7ddrphy_bitslip8_value1 <= 3'd7;
+        main_a7ddrphy_bitslip9_value0 <= 3'd7;
+        main_a7ddrphy_bitslip9_value1 <= 3'd7;
+        main_a7ddrphy_bitslip10_value0 <= 3'd7;
+        main_a7ddrphy_bitslip10_value1 <= 3'd7;
+        main_a7ddrphy_bitslip11_value0 <= 3'd7;
+        main_a7ddrphy_bitslip11_value1 <= 3'd7;
+        main_a7ddrphy_bitslip12_value0 <= 3'd7;
+        main_a7ddrphy_bitslip12_value1 <= 3'd7;
+        main_a7ddrphy_bitslip13_value0 <= 3'd7;
+        main_a7ddrphy_bitslip13_value1 <= 3'd7;
+        main_a7ddrphy_bitslip14_value0 <= 3'd7;
+        main_a7ddrphy_bitslip14_value1 <= 3'd7;
+        main_a7ddrphy_bitslip15_value0 <= 3'd7;
+        main_a7ddrphy_bitslip15_value1 <= 3'd7;
+        main_a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
+        main_a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
+        main_a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
+        main_a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
+        main_litedramcore_storage <= 4'd1;
+        main_litedramcore_re <= 1'd0;
+        main_litedramcore_phaseinjector0_command_storage <= 8'd0;
+        main_litedramcore_phaseinjector0_command_re <= 1'd0;
+        main_litedramcore_phaseinjector0_address_re <= 1'd0;
+        main_litedramcore_phaseinjector0_baddress_re <= 1'd0;
+        main_litedramcore_phaseinjector0_wrdata_re <= 1'd0;
+        main_litedramcore_phaseinjector0_rddata_status <= 32'd0;
+        main_litedramcore_phaseinjector0_rddata_re <= 1'd0;
+        main_litedramcore_phaseinjector1_command_storage <= 8'd0;
+        main_litedramcore_phaseinjector1_command_re <= 1'd0;
+        main_litedramcore_phaseinjector1_address_re <= 1'd0;
+        main_litedramcore_phaseinjector1_baddress_re <= 1'd0;
+        main_litedramcore_phaseinjector1_wrdata_re <= 1'd0;
+        main_litedramcore_phaseinjector1_rddata_status <= 32'd0;
+        main_litedramcore_phaseinjector1_rddata_re <= 1'd0;
+        main_litedramcore_phaseinjector2_command_storage <= 8'd0;
+        main_litedramcore_phaseinjector2_command_re <= 1'd0;
+        main_litedramcore_phaseinjector2_address_re <= 1'd0;
+        main_litedramcore_phaseinjector2_baddress_re <= 1'd0;
+        main_litedramcore_phaseinjector2_wrdata_re <= 1'd0;
+        main_litedramcore_phaseinjector2_rddata_status <= 32'd0;
+        main_litedramcore_phaseinjector2_rddata_re <= 1'd0;
+        main_litedramcore_phaseinjector3_command_storage <= 8'd0;
+        main_litedramcore_phaseinjector3_command_re <= 1'd0;
+        main_litedramcore_phaseinjector3_address_re <= 1'd0;
+        main_litedramcore_phaseinjector3_baddress_re <= 1'd0;
+        main_litedramcore_phaseinjector3_wrdata_re <= 1'd0;
+        main_litedramcore_phaseinjector3_rddata_status <= 32'd0;
+        main_litedramcore_phaseinjector3_rddata_re <= 1'd0;
+        main_litedramcore_dfi_p0_address <= 16'd0;
+        main_litedramcore_dfi_p0_bank <= 3'd0;
+        main_litedramcore_dfi_p0_cas_n <= 1'd1;
+        main_litedramcore_dfi_p0_cs_n <= 1'd1;
+        main_litedramcore_dfi_p0_ras_n <= 1'd1;
+        main_litedramcore_dfi_p0_we_n <= 1'd1;
+        main_litedramcore_dfi_p0_wrdata_en <= 1'd0;
+        main_litedramcore_dfi_p0_rddata_en <= 1'd0;
+        main_litedramcore_dfi_p1_address <= 16'd0;
+        main_litedramcore_dfi_p1_bank <= 3'd0;
+        main_litedramcore_dfi_p1_cas_n <= 1'd1;
+        main_litedramcore_dfi_p1_cs_n <= 1'd1;
+        main_litedramcore_dfi_p1_ras_n <= 1'd1;
+        main_litedramcore_dfi_p1_we_n <= 1'd1;
+        main_litedramcore_dfi_p1_wrdata_en <= 1'd0;
+        main_litedramcore_dfi_p1_rddata_en <= 1'd0;
+        main_litedramcore_dfi_p2_address <= 16'd0;
+        main_litedramcore_dfi_p2_bank <= 3'd0;
+        main_litedramcore_dfi_p2_cas_n <= 1'd1;
+        main_litedramcore_dfi_p2_cs_n <= 1'd1;
+        main_litedramcore_dfi_p2_ras_n <= 1'd1;
+        main_litedramcore_dfi_p2_we_n <= 1'd1;
+        main_litedramcore_dfi_p2_wrdata_en <= 1'd0;
+        main_litedramcore_dfi_p2_rddata_en <= 1'd0;
+        main_litedramcore_dfi_p3_address <= 16'd0;
+        main_litedramcore_dfi_p3_bank <= 3'd0;
+        main_litedramcore_dfi_p3_cas_n <= 1'd1;
+        main_litedramcore_dfi_p3_cs_n <= 1'd1;
+        main_litedramcore_dfi_p3_ras_n <= 1'd1;
+        main_litedramcore_dfi_p3_we_n <= 1'd1;
+        main_litedramcore_dfi_p3_wrdata_en <= 1'd0;
+        main_litedramcore_dfi_p3_rddata_en <= 1'd0;
+        main_litedramcore_cmd_payload_a <= 16'd0;
+        main_litedramcore_cmd_payload_ba <= 3'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd0;
+        main_litedramcore_cmd_payload_we <= 1'd0;
+        main_litedramcore_timer_count1 <= 10'd781;
+        main_litedramcore_postponer_req_o <= 1'd0;
+        main_litedramcore_postponer_count <= 1'd0;
+        main_litedramcore_sequencer_done1 <= 1'd0;
+        main_litedramcore_sequencer_trigger <= 7'd0;
+        main_litedramcore_sequencer_count <= 1'd0;
+        main_litedramcore_zqcs_timer_count1 <= 27'd99999999;
+        main_litedramcore_zqcs_executer_done <= 1'd0;
+        main_litedramcore_zqcs_executer_trigger <= 5'd0;
+        main_litedramcore_bankmachine0_level <= 5'd0;
+        main_litedramcore_bankmachine0_produce <= 4'd0;
+        main_litedramcore_bankmachine0_consume <= 4'd0;
+        main_litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 23'd0;
+        main_litedramcore_bankmachine0_row <= 16'd0;
+        main_litedramcore_bankmachine0_row_opened <= 1'd0;
+        main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine0_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine0_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine0_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine0_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine0_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine1_level <= 5'd0;
+        main_litedramcore_bankmachine1_produce <= 4'd0;
+        main_litedramcore_bankmachine1_consume <= 4'd0;
+        main_litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 23'd0;
+        main_litedramcore_bankmachine1_row <= 16'd0;
+        main_litedramcore_bankmachine1_row_opened <= 1'd0;
+        main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine1_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine1_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine1_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine1_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine1_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine2_level <= 5'd0;
+        main_litedramcore_bankmachine2_produce <= 4'd0;
+        main_litedramcore_bankmachine2_consume <= 4'd0;
+        main_litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 23'd0;
+        main_litedramcore_bankmachine2_row <= 16'd0;
+        main_litedramcore_bankmachine2_row_opened <= 1'd0;
+        main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine2_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine2_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine2_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine2_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine2_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine3_level <= 5'd0;
+        main_litedramcore_bankmachine3_produce <= 4'd0;
+        main_litedramcore_bankmachine3_consume <= 4'd0;
+        main_litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 23'd0;
+        main_litedramcore_bankmachine3_row <= 16'd0;
+        main_litedramcore_bankmachine3_row_opened <= 1'd0;
+        main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine3_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine3_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine3_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine3_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine3_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine4_level <= 5'd0;
+        main_litedramcore_bankmachine4_produce <= 4'd0;
+        main_litedramcore_bankmachine4_consume <= 4'd0;
+        main_litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 23'd0;
+        main_litedramcore_bankmachine4_row <= 16'd0;
+        main_litedramcore_bankmachine4_row_opened <= 1'd0;
+        main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine4_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine4_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine4_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine4_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine4_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine5_level <= 5'd0;
+        main_litedramcore_bankmachine5_produce <= 4'd0;
+        main_litedramcore_bankmachine5_consume <= 4'd0;
+        main_litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 23'd0;
+        main_litedramcore_bankmachine5_row <= 16'd0;
+        main_litedramcore_bankmachine5_row_opened <= 1'd0;
+        main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine5_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine5_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine5_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine5_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine5_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine6_level <= 5'd0;
+        main_litedramcore_bankmachine6_produce <= 4'd0;
+        main_litedramcore_bankmachine6_consume <= 4'd0;
+        main_litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 23'd0;
+        main_litedramcore_bankmachine6_row <= 16'd0;
+        main_litedramcore_bankmachine6_row_opened <= 1'd0;
+        main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine6_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine6_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine6_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine6_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine6_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine7_level <= 5'd0;
+        main_litedramcore_bankmachine7_produce <= 4'd0;
+        main_litedramcore_bankmachine7_consume <= 4'd0;
+        main_litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 23'd0;
+        main_litedramcore_bankmachine7_row <= 16'd0;
+        main_litedramcore_bankmachine7_row_opened <= 1'd0;
+        main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine7_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine7_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine7_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine7_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine7_trascon_count <= 3'd0;
+        main_litedramcore_choose_cmd_grant <= 3'd0;
+        main_litedramcore_choose_req_grant <= 3'd0;
+        main_litedramcore_trrdcon_ready <= 1'd0;
+        main_litedramcore_trrdcon_count <= 1'd0;
+        main_litedramcore_tfawcon_ready <= 1'd1;
+        main_litedramcore_tfawcon_window <= 5'd0;
+        main_litedramcore_tccdcon_ready <= 1'd0;
+        main_litedramcore_tccdcon_count <= 1'd0;
+        main_litedramcore_twtrcon_ready <= 1'd0;
+        main_litedramcore_twtrcon_count <= 3'd0;
+        main_litedramcore_time0 <= 5'd0;
+        main_litedramcore_time1 <= 4'd0;
+        main_init_done_storage <= 1'd0;
+        main_init_done_re <= 1'd0;
+        main_init_error_storage <= 1'd0;
+        main_init_error_re <= 1'd0;
+        builder_interface1_we <= 1'd0;
+        builder_refresher_state <= 2'd0;
+        builder_bankmachine0_state <= 4'd0;
+        builder_bankmachine1_state <= 4'd0;
+        builder_bankmachine2_state <= 4'd0;
+        builder_bankmachine3_state <= 4'd0;
+        builder_bankmachine4_state <= 4'd0;
+        builder_bankmachine5_state <= 4'd0;
+        builder_bankmachine6_state <= 4'd0;
+        builder_bankmachine7_state <= 4'd0;
+        builder_multiplexer_state <= 4'd0;
+        builder_new_master_wdata_ready0 <= 1'd0;
+        builder_new_master_wdata_ready1 <= 1'd0;
+        builder_new_master_rdata_valid0 <= 1'd0;
+        builder_new_master_rdata_valid1 <= 1'd0;
+        builder_new_master_rdata_valid2 <= 1'd0;
+        builder_new_master_rdata_valid3 <= 1'd0;
+        builder_new_master_rdata_valid4 <= 1'd0;
+        builder_new_master_rdata_valid5 <= 1'd0;
+        builder_new_master_rdata_valid6 <= 1'd0;
+        builder_new_master_rdata_valid7 <= 1'd0;
+        builder_new_master_rdata_valid8 <= 1'd0;
+        builder_state <= 2'd0;
     end
 end
 
@@ -14116,1955 +14533,2682 @@ end
 // Specialized Logic
 //------------------------------------------------------------------------------
 
+//------------------------------------------------------------------------------
+// Instance BUFG of BUFG Module.
+//------------------------------------------------------------------------------
 BUFG BUFG(
-	.I(clkout0),
-	.O(clkout_buf0)
+	// Inputs.
+	.I (main_clkout0),
+
+	// Outputs.
+	.O (main_clkout_buf0)
 );
 
+//------------------------------------------------------------------------------
+// Instance BUFG_1 of BUFG Module.
+//------------------------------------------------------------------------------
 BUFG BUFG_1(
-	.I(clkout1),
-	.O(clkout_buf1)
+	// Inputs.
+	.I (main_clkout1),
+
+	// Outputs.
+	.O (main_clkout_buf1)
 );
 
+//------------------------------------------------------------------------------
+// Instance BUFG_2 of BUFG Module.
+//------------------------------------------------------------------------------
 BUFG BUFG_2(
-	.I(clkout2),
-	.O(clkout_buf2)
+	// Inputs.
+	.I (main_clkout2),
+
+	// Outputs.
+	.O (main_clkout_buf2)
 );
 
+//------------------------------------------------------------------------------
+// Instance BUFG_3 of BUFG Module.
+//------------------------------------------------------------------------------
 BUFG BUFG_3(
-	.I(clkout3),
-	.O(clkout_buf3)
+	// Inputs.
+	.I (main_clkout3),
+
+	// Outputs.
+	.O (main_clkout_buf3)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYCTRL of IDELAYCTRL Module.
+//------------------------------------------------------------------------------
 IDELAYCTRL IDELAYCTRL(
-	.REFCLK(iodelay_clk),
-	.RST(ic_reset)
+	// Inputs.
+	.REFCLK (iodelay_clk),
+	.RST    (main_ic_reset)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(1'd0),
-	.D2(1'd1),
-	.D3(1'd0),
-	.D4(1'd1),
-	.D5(1'd0),
-	.D6(1'd1),
-	.D7(1'd0),
-	.D8(1'd1),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(a7ddrphy_sd_clk_se_nodelay)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (1'd0),
+	.D2     (1'd1),
+	.D3     (1'd0),
+	.D4     (1'd1),
+	.D5     (1'd0),
+	.D6     (1'd1),
+	.D7     (1'd0),
+	.D8     (1'd1),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_sd_clk_se_nodelay)
 );
 
+//------------------------------------------------------------------------------
+// Instance OBUFDS of OBUFDS Module.
+//------------------------------------------------------------------------------
 OBUFDS OBUFDS(
-	.I(a7ddrphy_sd_clk_se_nodelay),
-	.O(ddram_clk_p),
-	.OB(ddram_clk_n)
+	// Inputs.
+	.I  (main_a7ddrphy_sd_clk_se_nodelay),
+
+	// Outputs.
+	.O  (ddram_clk_p),
+	.OB (ddram_clk_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_1 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_1 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_reset_n),
-	.D2(a7ddrphy_dfi_p0_reset_n),
-	.D3(a7ddrphy_dfi_p1_reset_n),
-	.D4(a7ddrphy_dfi_p1_reset_n),
-	.D5(a7ddrphy_dfi_p2_reset_n),
-	.D6(a7ddrphy_dfi_p2_reset_n),
-	.D7(a7ddrphy_dfi_p3_reset_n),
-	.D8(a7ddrphy_dfi_p3_reset_n),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_reset_n)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_reset_n),
+	.D2     (main_a7ddrphy_dfi_p0_reset_n),
+	.D3     (main_a7ddrphy_dfi_p1_reset_n),
+	.D4     (main_a7ddrphy_dfi_p1_reset_n),
+	.D5     (main_a7ddrphy_dfi_p2_reset_n),
+	.D6     (main_a7ddrphy_dfi_p2_reset_n),
+	.D7     (main_a7ddrphy_dfi_p3_reset_n),
+	.D8     (main_a7ddrphy_dfi_p3_reset_n),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_reset_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_2 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_2 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_cs_n),
-	.D2(a7ddrphy_dfi_p0_cs_n),
-	.D3(a7ddrphy_dfi_p1_cs_n),
-	.D4(a7ddrphy_dfi_p1_cs_n),
-	.D5(a7ddrphy_dfi_p2_cs_n),
-	.D6(a7ddrphy_dfi_p2_cs_n),
-	.D7(a7ddrphy_dfi_p3_cs_n),
-	.D8(a7ddrphy_dfi_p3_cs_n),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_cs_n)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_cs_n),
+	.D2     (main_a7ddrphy_dfi_p0_cs_n),
+	.D3     (main_a7ddrphy_dfi_p1_cs_n),
+	.D4     (main_a7ddrphy_dfi_p1_cs_n),
+	.D5     (main_a7ddrphy_dfi_p2_cs_n),
+	.D6     (main_a7ddrphy_dfi_p2_cs_n),
+	.D7     (main_a7ddrphy_dfi_p3_cs_n),
+	.D8     (main_a7ddrphy_dfi_p3_cs_n),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_cs_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_3 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_3 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[0]),
-	.D2(a7ddrphy_dfi_p0_address[0]),
-	.D3(a7ddrphy_dfi_p1_address[0]),
-	.D4(a7ddrphy_dfi_p1_address[0]),
-	.D5(a7ddrphy_dfi_p2_address[0]),
-	.D6(a7ddrphy_dfi_p2_address[0]),
-	.D7(a7ddrphy_dfi_p3_address[0]),
-	.D8(a7ddrphy_dfi_p3_address[0]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[0])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[0]),
+	.D2     (main_a7ddrphy_dfi_p0_address[0]),
+	.D3     (main_a7ddrphy_dfi_p1_address[0]),
+	.D4     (main_a7ddrphy_dfi_p1_address[0]),
+	.D5     (main_a7ddrphy_dfi_p2_address[0]),
+	.D6     (main_a7ddrphy_dfi_p2_address[0]),
+	.D7     (main_a7ddrphy_dfi_p3_address[0]),
+	.D8     (main_a7ddrphy_dfi_p3_address[0]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_4 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_4 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[1]),
-	.D2(a7ddrphy_dfi_p0_address[1]),
-	.D3(a7ddrphy_dfi_p1_address[1]),
-	.D4(a7ddrphy_dfi_p1_address[1]),
-	.D5(a7ddrphy_dfi_p2_address[1]),
-	.D6(a7ddrphy_dfi_p2_address[1]),
-	.D7(a7ddrphy_dfi_p3_address[1]),
-	.D8(a7ddrphy_dfi_p3_address[1]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[1])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[1]),
+	.D2     (main_a7ddrphy_dfi_p0_address[1]),
+	.D3     (main_a7ddrphy_dfi_p1_address[1]),
+	.D4     (main_a7ddrphy_dfi_p1_address[1]),
+	.D5     (main_a7ddrphy_dfi_p2_address[1]),
+	.D6     (main_a7ddrphy_dfi_p2_address[1]),
+	.D7     (main_a7ddrphy_dfi_p3_address[1]),
+	.D8     (main_a7ddrphy_dfi_p3_address[1]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[1])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_5 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_5 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[2]),
-	.D2(a7ddrphy_dfi_p0_address[2]),
-	.D3(a7ddrphy_dfi_p1_address[2]),
-	.D4(a7ddrphy_dfi_p1_address[2]),
-	.D5(a7ddrphy_dfi_p2_address[2]),
-	.D6(a7ddrphy_dfi_p2_address[2]),
-	.D7(a7ddrphy_dfi_p3_address[2]),
-	.D8(a7ddrphy_dfi_p3_address[2]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[2])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[2]),
+	.D2     (main_a7ddrphy_dfi_p0_address[2]),
+	.D3     (main_a7ddrphy_dfi_p1_address[2]),
+	.D4     (main_a7ddrphy_dfi_p1_address[2]),
+	.D5     (main_a7ddrphy_dfi_p2_address[2]),
+	.D6     (main_a7ddrphy_dfi_p2_address[2]),
+	.D7     (main_a7ddrphy_dfi_p3_address[2]),
+	.D8     (main_a7ddrphy_dfi_p3_address[2]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[2])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_6 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_6 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[3]),
-	.D2(a7ddrphy_dfi_p0_address[3]),
-	.D3(a7ddrphy_dfi_p1_address[3]),
-	.D4(a7ddrphy_dfi_p1_address[3]),
-	.D5(a7ddrphy_dfi_p2_address[3]),
-	.D6(a7ddrphy_dfi_p2_address[3]),
-	.D7(a7ddrphy_dfi_p3_address[3]),
-	.D8(a7ddrphy_dfi_p3_address[3]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[3])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[3]),
+	.D2     (main_a7ddrphy_dfi_p0_address[3]),
+	.D3     (main_a7ddrphy_dfi_p1_address[3]),
+	.D4     (main_a7ddrphy_dfi_p1_address[3]),
+	.D5     (main_a7ddrphy_dfi_p2_address[3]),
+	.D6     (main_a7ddrphy_dfi_p2_address[3]),
+	.D7     (main_a7ddrphy_dfi_p3_address[3]),
+	.D8     (main_a7ddrphy_dfi_p3_address[3]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_7 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_7 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[4]),
-	.D2(a7ddrphy_dfi_p0_address[4]),
-	.D3(a7ddrphy_dfi_p1_address[4]),
-	.D4(a7ddrphy_dfi_p1_address[4]),
-	.D5(a7ddrphy_dfi_p2_address[4]),
-	.D6(a7ddrphy_dfi_p2_address[4]),
-	.D7(a7ddrphy_dfi_p3_address[4]),
-	.D8(a7ddrphy_dfi_p3_address[4]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[4])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[4]),
+	.D2     (main_a7ddrphy_dfi_p0_address[4]),
+	.D3     (main_a7ddrphy_dfi_p1_address[4]),
+	.D4     (main_a7ddrphy_dfi_p1_address[4]),
+	.D5     (main_a7ddrphy_dfi_p2_address[4]),
+	.D6     (main_a7ddrphy_dfi_p2_address[4]),
+	.D7     (main_a7ddrphy_dfi_p3_address[4]),
+	.D8     (main_a7ddrphy_dfi_p3_address[4]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[4])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_8 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_8 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[5]),
-	.D2(a7ddrphy_dfi_p0_address[5]),
-	.D3(a7ddrphy_dfi_p1_address[5]),
-	.D4(a7ddrphy_dfi_p1_address[5]),
-	.D5(a7ddrphy_dfi_p2_address[5]),
-	.D6(a7ddrphy_dfi_p2_address[5]),
-	.D7(a7ddrphy_dfi_p3_address[5]),
-	.D8(a7ddrphy_dfi_p3_address[5]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[5])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[5]),
+	.D2     (main_a7ddrphy_dfi_p0_address[5]),
+	.D3     (main_a7ddrphy_dfi_p1_address[5]),
+	.D4     (main_a7ddrphy_dfi_p1_address[5]),
+	.D5     (main_a7ddrphy_dfi_p2_address[5]),
+	.D6     (main_a7ddrphy_dfi_p2_address[5]),
+	.D7     (main_a7ddrphy_dfi_p3_address[5]),
+	.D8     (main_a7ddrphy_dfi_p3_address[5]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[5])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_9 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_9 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[6]),
-	.D2(a7ddrphy_dfi_p0_address[6]),
-	.D3(a7ddrphy_dfi_p1_address[6]),
-	.D4(a7ddrphy_dfi_p1_address[6]),
-	.D5(a7ddrphy_dfi_p2_address[6]),
-	.D6(a7ddrphy_dfi_p2_address[6]),
-	.D7(a7ddrphy_dfi_p3_address[6]),
-	.D8(a7ddrphy_dfi_p3_address[6]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[6])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[6]),
+	.D2     (main_a7ddrphy_dfi_p0_address[6]),
+	.D3     (main_a7ddrphy_dfi_p1_address[6]),
+	.D4     (main_a7ddrphy_dfi_p1_address[6]),
+	.D5     (main_a7ddrphy_dfi_p2_address[6]),
+	.D6     (main_a7ddrphy_dfi_p2_address[6]),
+	.D7     (main_a7ddrphy_dfi_p3_address[6]),
+	.D8     (main_a7ddrphy_dfi_p3_address[6]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[6])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_10 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_10 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[7]),
-	.D2(a7ddrphy_dfi_p0_address[7]),
-	.D3(a7ddrphy_dfi_p1_address[7]),
-	.D4(a7ddrphy_dfi_p1_address[7]),
-	.D5(a7ddrphy_dfi_p2_address[7]),
-	.D6(a7ddrphy_dfi_p2_address[7]),
-	.D7(a7ddrphy_dfi_p3_address[7]),
-	.D8(a7ddrphy_dfi_p3_address[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[7])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[7]),
+	.D2     (main_a7ddrphy_dfi_p0_address[7]),
+	.D3     (main_a7ddrphy_dfi_p1_address[7]),
+	.D4     (main_a7ddrphy_dfi_p1_address[7]),
+	.D5     (main_a7ddrphy_dfi_p2_address[7]),
+	.D6     (main_a7ddrphy_dfi_p2_address[7]),
+	.D7     (main_a7ddrphy_dfi_p3_address[7]),
+	.D8     (main_a7ddrphy_dfi_p3_address[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[7])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_11 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_11 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[8]),
-	.D2(a7ddrphy_dfi_p0_address[8]),
-	.D3(a7ddrphy_dfi_p1_address[8]),
-	.D4(a7ddrphy_dfi_p1_address[8]),
-	.D5(a7ddrphy_dfi_p2_address[8]),
-	.D6(a7ddrphy_dfi_p2_address[8]),
-	.D7(a7ddrphy_dfi_p3_address[8]),
-	.D8(a7ddrphy_dfi_p3_address[8]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[8])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[8]),
+	.D2     (main_a7ddrphy_dfi_p0_address[8]),
+	.D3     (main_a7ddrphy_dfi_p1_address[8]),
+	.D4     (main_a7ddrphy_dfi_p1_address[8]),
+	.D5     (main_a7ddrphy_dfi_p2_address[8]),
+	.D6     (main_a7ddrphy_dfi_p2_address[8]),
+	.D7     (main_a7ddrphy_dfi_p3_address[8]),
+	.D8     (main_a7ddrphy_dfi_p3_address[8]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[8])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_12 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_12 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[9]),
-	.D2(a7ddrphy_dfi_p0_address[9]),
-	.D3(a7ddrphy_dfi_p1_address[9]),
-	.D4(a7ddrphy_dfi_p1_address[9]),
-	.D5(a7ddrphy_dfi_p2_address[9]),
-	.D6(a7ddrphy_dfi_p2_address[9]),
-	.D7(a7ddrphy_dfi_p3_address[9]),
-	.D8(a7ddrphy_dfi_p3_address[9]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[9])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[9]),
+	.D2     (main_a7ddrphy_dfi_p0_address[9]),
+	.D3     (main_a7ddrphy_dfi_p1_address[9]),
+	.D4     (main_a7ddrphy_dfi_p1_address[9]),
+	.D5     (main_a7ddrphy_dfi_p2_address[9]),
+	.D6     (main_a7ddrphy_dfi_p2_address[9]),
+	.D7     (main_a7ddrphy_dfi_p3_address[9]),
+	.D8     (main_a7ddrphy_dfi_p3_address[9]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[9])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_13 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_13 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[10]),
-	.D2(a7ddrphy_dfi_p0_address[10]),
-	.D3(a7ddrphy_dfi_p1_address[10]),
-	.D4(a7ddrphy_dfi_p1_address[10]),
-	.D5(a7ddrphy_dfi_p2_address[10]),
-	.D6(a7ddrphy_dfi_p2_address[10]),
-	.D7(a7ddrphy_dfi_p3_address[10]),
-	.D8(a7ddrphy_dfi_p3_address[10]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[10])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[10]),
+	.D2     (main_a7ddrphy_dfi_p0_address[10]),
+	.D3     (main_a7ddrphy_dfi_p1_address[10]),
+	.D4     (main_a7ddrphy_dfi_p1_address[10]),
+	.D5     (main_a7ddrphy_dfi_p2_address[10]),
+	.D6     (main_a7ddrphy_dfi_p2_address[10]),
+	.D7     (main_a7ddrphy_dfi_p3_address[10]),
+	.D8     (main_a7ddrphy_dfi_p3_address[10]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[10])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_14 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_14 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[11]),
-	.D2(a7ddrphy_dfi_p0_address[11]),
-	.D3(a7ddrphy_dfi_p1_address[11]),
-	.D4(a7ddrphy_dfi_p1_address[11]),
-	.D5(a7ddrphy_dfi_p2_address[11]),
-	.D6(a7ddrphy_dfi_p2_address[11]),
-	.D7(a7ddrphy_dfi_p3_address[11]),
-	.D8(a7ddrphy_dfi_p3_address[11]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[11])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[11]),
+	.D2     (main_a7ddrphy_dfi_p0_address[11]),
+	.D3     (main_a7ddrphy_dfi_p1_address[11]),
+	.D4     (main_a7ddrphy_dfi_p1_address[11]),
+	.D5     (main_a7ddrphy_dfi_p2_address[11]),
+	.D6     (main_a7ddrphy_dfi_p2_address[11]),
+	.D7     (main_a7ddrphy_dfi_p3_address[11]),
+	.D8     (main_a7ddrphy_dfi_p3_address[11]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[11])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_15 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_15 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[12]),
-	.D2(a7ddrphy_dfi_p0_address[12]),
-	.D3(a7ddrphy_dfi_p1_address[12]),
-	.D4(a7ddrphy_dfi_p1_address[12]),
-	.D5(a7ddrphy_dfi_p2_address[12]),
-	.D6(a7ddrphy_dfi_p2_address[12]),
-	.D7(a7ddrphy_dfi_p3_address[12]),
-	.D8(a7ddrphy_dfi_p3_address[12]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[12])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[12]),
+	.D2     (main_a7ddrphy_dfi_p0_address[12]),
+	.D3     (main_a7ddrphy_dfi_p1_address[12]),
+	.D4     (main_a7ddrphy_dfi_p1_address[12]),
+	.D5     (main_a7ddrphy_dfi_p2_address[12]),
+	.D6     (main_a7ddrphy_dfi_p2_address[12]),
+	.D7     (main_a7ddrphy_dfi_p3_address[12]),
+	.D8     (main_a7ddrphy_dfi_p3_address[12]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[12])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_16 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_16 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[13]),
-	.D2(a7ddrphy_dfi_p0_address[13]),
-	.D3(a7ddrphy_dfi_p1_address[13]),
-	.D4(a7ddrphy_dfi_p1_address[13]),
-	.D5(a7ddrphy_dfi_p2_address[13]),
-	.D6(a7ddrphy_dfi_p2_address[13]),
-	.D7(a7ddrphy_dfi_p3_address[13]),
-	.D8(a7ddrphy_dfi_p3_address[13]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[13])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[13]),
+	.D2     (main_a7ddrphy_dfi_p0_address[13]),
+	.D3     (main_a7ddrphy_dfi_p1_address[13]),
+	.D4     (main_a7ddrphy_dfi_p1_address[13]),
+	.D5     (main_a7ddrphy_dfi_p2_address[13]),
+	.D6     (main_a7ddrphy_dfi_p2_address[13]),
+	.D7     (main_a7ddrphy_dfi_p3_address[13]),
+	.D8     (main_a7ddrphy_dfi_p3_address[13]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[13])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_17 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_17 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[14]),
-	.D2(a7ddrphy_dfi_p0_address[14]),
-	.D3(a7ddrphy_dfi_p1_address[14]),
-	.D4(a7ddrphy_dfi_p1_address[14]),
-	.D5(a7ddrphy_dfi_p2_address[14]),
-	.D6(a7ddrphy_dfi_p2_address[14]),
-	.D7(a7ddrphy_dfi_p3_address[14]),
-	.D8(a7ddrphy_dfi_p3_address[14]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[14])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[14]),
+	.D2     (main_a7ddrphy_dfi_p0_address[14]),
+	.D3     (main_a7ddrphy_dfi_p1_address[14]),
+	.D4     (main_a7ddrphy_dfi_p1_address[14]),
+	.D5     (main_a7ddrphy_dfi_p2_address[14]),
+	.D6     (main_a7ddrphy_dfi_p2_address[14]),
+	.D7     (main_a7ddrphy_dfi_p3_address[14]),
+	.D8     (main_a7ddrphy_dfi_p3_address[14]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[14])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_18 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_18 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[15]),
-	.D2(a7ddrphy_dfi_p0_address[15]),
-	.D3(a7ddrphy_dfi_p1_address[15]),
-	.D4(a7ddrphy_dfi_p1_address[15]),
-	.D5(a7ddrphy_dfi_p2_address[15]),
-	.D6(a7ddrphy_dfi_p2_address[15]),
-	.D7(a7ddrphy_dfi_p3_address[15]),
-	.D8(a7ddrphy_dfi_p3_address[15]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[15])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[15]),
+	.D2     (main_a7ddrphy_dfi_p0_address[15]),
+	.D3     (main_a7ddrphy_dfi_p1_address[15]),
+	.D4     (main_a7ddrphy_dfi_p1_address[15]),
+	.D5     (main_a7ddrphy_dfi_p2_address[15]),
+	.D6     (main_a7ddrphy_dfi_p2_address[15]),
+	.D7     (main_a7ddrphy_dfi_p3_address[15]),
+	.D8     (main_a7ddrphy_dfi_p3_address[15]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[15])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_19 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_19 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_bank[0]),
-	.D2(a7ddrphy_dfi_p0_bank[0]),
-	.D3(a7ddrphy_dfi_p1_bank[0]),
-	.D4(a7ddrphy_dfi_p1_bank[0]),
-	.D5(a7ddrphy_dfi_p2_bank[0]),
-	.D6(a7ddrphy_dfi_p2_bank[0]),
-	.D7(a7ddrphy_dfi_p3_bank[0]),
-	.D8(a7ddrphy_dfi_p3_bank[0]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(a7ddrphy_pads_ba[0])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_bank[0]),
+	.D2     (main_a7ddrphy_dfi_p0_bank[0]),
+	.D3     (main_a7ddrphy_dfi_p1_bank[0]),
+	.D4     (main_a7ddrphy_dfi_p1_bank[0]),
+	.D5     (main_a7ddrphy_dfi_p2_bank[0]),
+	.D6     (main_a7ddrphy_dfi_p2_bank[0]),
+	.D7     (main_a7ddrphy_dfi_p3_bank[0]),
+	.D8     (main_a7ddrphy_dfi_p3_bank[0]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_pads_ba[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_20 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_20 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_bank[1]),
-	.D2(a7ddrphy_dfi_p0_bank[1]),
-	.D3(a7ddrphy_dfi_p1_bank[1]),
-	.D4(a7ddrphy_dfi_p1_bank[1]),
-	.D5(a7ddrphy_dfi_p2_bank[1]),
-	.D6(a7ddrphy_dfi_p2_bank[1]),
-	.D7(a7ddrphy_dfi_p3_bank[1]),
-	.D8(a7ddrphy_dfi_p3_bank[1]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(a7ddrphy_pads_ba[1])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_bank[1]),
+	.D2     (main_a7ddrphy_dfi_p0_bank[1]),
+	.D3     (main_a7ddrphy_dfi_p1_bank[1]),
+	.D4     (main_a7ddrphy_dfi_p1_bank[1]),
+	.D5     (main_a7ddrphy_dfi_p2_bank[1]),
+	.D6     (main_a7ddrphy_dfi_p2_bank[1]),
+	.D7     (main_a7ddrphy_dfi_p3_bank[1]),
+	.D8     (main_a7ddrphy_dfi_p3_bank[1]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_pads_ba[1])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_21 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_21 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_bank[2]),
-	.D2(a7ddrphy_dfi_p0_bank[2]),
-	.D3(a7ddrphy_dfi_p1_bank[2]),
-	.D4(a7ddrphy_dfi_p1_bank[2]),
-	.D5(a7ddrphy_dfi_p2_bank[2]),
-	.D6(a7ddrphy_dfi_p2_bank[2]),
-	.D7(a7ddrphy_dfi_p3_bank[2]),
-	.D8(a7ddrphy_dfi_p3_bank[2]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(a7ddrphy_pads_ba[2])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_bank[2]),
+	.D2     (main_a7ddrphy_dfi_p0_bank[2]),
+	.D3     (main_a7ddrphy_dfi_p1_bank[2]),
+	.D4     (main_a7ddrphy_dfi_p1_bank[2]),
+	.D5     (main_a7ddrphy_dfi_p2_bank[2]),
+	.D6     (main_a7ddrphy_dfi_p2_bank[2]),
+	.D7     (main_a7ddrphy_dfi_p3_bank[2]),
+	.D8     (main_a7ddrphy_dfi_p3_bank[2]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_pads_ba[2])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_22 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_22 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_ras_n),
-	.D2(a7ddrphy_dfi_p0_ras_n),
-	.D3(a7ddrphy_dfi_p1_ras_n),
-	.D4(a7ddrphy_dfi_p1_ras_n),
-	.D5(a7ddrphy_dfi_p2_ras_n),
-	.D6(a7ddrphy_dfi_p2_ras_n),
-	.D7(a7ddrphy_dfi_p3_ras_n),
-	.D8(a7ddrphy_dfi_p3_ras_n),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_ras_n)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_ras_n),
+	.D2     (main_a7ddrphy_dfi_p0_ras_n),
+	.D3     (main_a7ddrphy_dfi_p1_ras_n),
+	.D4     (main_a7ddrphy_dfi_p1_ras_n),
+	.D5     (main_a7ddrphy_dfi_p2_ras_n),
+	.D6     (main_a7ddrphy_dfi_p2_ras_n),
+	.D7     (main_a7ddrphy_dfi_p3_ras_n),
+	.D8     (main_a7ddrphy_dfi_p3_ras_n),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_ras_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_23 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_23 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_cas_n),
-	.D2(a7ddrphy_dfi_p0_cas_n),
-	.D3(a7ddrphy_dfi_p1_cas_n),
-	.D4(a7ddrphy_dfi_p1_cas_n),
-	.D5(a7ddrphy_dfi_p2_cas_n),
-	.D6(a7ddrphy_dfi_p2_cas_n),
-	.D7(a7ddrphy_dfi_p3_cas_n),
-	.D8(a7ddrphy_dfi_p3_cas_n),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_cas_n)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_cas_n),
+	.D2     (main_a7ddrphy_dfi_p0_cas_n),
+	.D3     (main_a7ddrphy_dfi_p1_cas_n),
+	.D4     (main_a7ddrphy_dfi_p1_cas_n),
+	.D5     (main_a7ddrphy_dfi_p2_cas_n),
+	.D6     (main_a7ddrphy_dfi_p2_cas_n),
+	.D7     (main_a7ddrphy_dfi_p3_cas_n),
+	.D8     (main_a7ddrphy_dfi_p3_cas_n),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_cas_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_24 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_24 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_we_n),
-	.D2(a7ddrphy_dfi_p0_we_n),
-	.D3(a7ddrphy_dfi_p1_we_n),
-	.D4(a7ddrphy_dfi_p1_we_n),
-	.D5(a7ddrphy_dfi_p2_we_n),
-	.D6(a7ddrphy_dfi_p2_we_n),
-	.D7(a7ddrphy_dfi_p3_we_n),
-	.D8(a7ddrphy_dfi_p3_we_n),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_we_n)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_we_n),
+	.D2     (main_a7ddrphy_dfi_p0_we_n),
+	.D3     (main_a7ddrphy_dfi_p1_we_n),
+	.D4     (main_a7ddrphy_dfi_p1_we_n),
+	.D5     (main_a7ddrphy_dfi_p2_we_n),
+	.D6     (main_a7ddrphy_dfi_p2_we_n),
+	.D7     (main_a7ddrphy_dfi_p3_we_n),
+	.D8     (main_a7ddrphy_dfi_p3_we_n),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_we_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_25 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_25 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_cke),
-	.D2(a7ddrphy_dfi_p0_cke),
-	.D3(a7ddrphy_dfi_p1_cke),
-	.D4(a7ddrphy_dfi_p1_cke),
-	.D5(a7ddrphy_dfi_p2_cke),
-	.D6(a7ddrphy_dfi_p2_cke),
-	.D7(a7ddrphy_dfi_p3_cke),
-	.D8(a7ddrphy_dfi_p3_cke),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_cke)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_cke),
+	.D2     (main_a7ddrphy_dfi_p0_cke),
+	.D3     (main_a7ddrphy_dfi_p1_cke),
+	.D4     (main_a7ddrphy_dfi_p1_cke),
+	.D5     (main_a7ddrphy_dfi_p2_cke),
+	.D6     (main_a7ddrphy_dfi_p2_cke),
+	.D7     (main_a7ddrphy_dfi_p3_cke),
+	.D8     (main_a7ddrphy_dfi_p3_cke),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_cke)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_26 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_26 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_odt),
-	.D2(a7ddrphy_dfi_p0_odt),
-	.D3(a7ddrphy_dfi_p1_odt),
-	.D4(a7ddrphy_dfi_p1_odt),
-	.D5(a7ddrphy_dfi_p2_odt),
-	.D6(a7ddrphy_dfi_p2_odt),
-	.D7(a7ddrphy_dfi_p3_odt),
-	.D8(a7ddrphy_dfi_p3_odt),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_odt)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_odt),
+	.D2     (main_a7ddrphy_dfi_p0_odt),
+	.D3     (main_a7ddrphy_dfi_p1_odt),
+	.D4     (main_a7ddrphy_dfi_p1_odt),
+	.D5     (main_a7ddrphy_dfi_p2_odt),
+	.D6     (main_a7ddrphy_dfi_p2_odt),
+	.D7     (main_a7ddrphy_dfi_p3_odt),
+	.D8     (main_a7ddrphy_dfi_p3_odt),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_odt)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_27 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_27 (
-	.CLK(sys4x_dqs_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip00[0]),
-	.D2(a7ddrphy_bitslip00[1]),
-	.D3(a7ddrphy_bitslip00[2]),
-	.D4(a7ddrphy_bitslip00[3]),
-	.D5(a7ddrphy_bitslip00[4]),
-	.D6(a7ddrphy_bitslip00[5]),
-	.D7(a7ddrphy_bitslip00[6]),
-	.D8(a7ddrphy_bitslip00[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OFB(a7ddrphy0),
-	.OQ(a7ddrphy_dqs_o_no_delay0),
-	.TQ(a7ddrphy_dqs_t0)
+	// Inputs.
+	.CLK    (sys4x_dqs_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip00[0]),
+	.D2     (main_a7ddrphy_bitslip00[1]),
+	.D3     (main_a7ddrphy_bitslip00[2]),
+	.D4     (main_a7ddrphy_bitslip00[3]),
+	.D5     (main_a7ddrphy_bitslip00[4]),
+	.D6     (main_a7ddrphy_bitslip00[5]),
+	.D7     (main_a7ddrphy_bitslip00[6]),
+	.D8     (main_a7ddrphy_bitslip00[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OFB    (main_a7ddrphy0),
+	.OQ     (main_a7ddrphy_dqs_o_no_delay0),
+	.TQ     (main_a7ddrphy_dqs_t0)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUFDS of IOBUFDS Module.
+//------------------------------------------------------------------------------
 IOBUFDS IOBUFDS(
-	.I(a7ddrphy_dqs_o_no_delay0),
-	.T(a7ddrphy_dqs_t0),
-	.IO(ddram_dqs_p[0]),
-	.IOB(ddram_dqs_n[0])
+	// Inputs.
+	.I   (main_a7ddrphy_dqs_o_no_delay0),
+	.T   (main_a7ddrphy_dqs_t0),
+
+	// InOuts.
+	.IO  (ddram_dqs_p[0]),
+	.IOB (ddram_dqs_n[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_28 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_28 (
-	.CLK(sys4x_dqs_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip10[0]),
-	.D2(a7ddrphy_bitslip10[1]),
-	.D3(a7ddrphy_bitslip10[2]),
-	.D4(a7ddrphy_bitslip10[3]),
-	.D5(a7ddrphy_bitslip10[4]),
-	.D6(a7ddrphy_bitslip10[5]),
-	.D7(a7ddrphy_bitslip10[6]),
-	.D8(a7ddrphy_bitslip10[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OFB(a7ddrphy1),
-	.OQ(a7ddrphy_dqs_o_no_delay1),
-	.TQ(a7ddrphy_dqs_t1)
+	// Inputs.
+	.CLK    (sys4x_dqs_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip10[0]),
+	.D2     (main_a7ddrphy_bitslip10[1]),
+	.D3     (main_a7ddrphy_bitslip10[2]),
+	.D4     (main_a7ddrphy_bitslip10[3]),
+	.D5     (main_a7ddrphy_bitslip10[4]),
+	.D6     (main_a7ddrphy_bitslip10[5]),
+	.D7     (main_a7ddrphy_bitslip10[6]),
+	.D8     (main_a7ddrphy_bitslip10[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OFB    (main_a7ddrphy1),
+	.OQ     (main_a7ddrphy_dqs_o_no_delay1),
+	.TQ     (main_a7ddrphy_dqs_t1)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUFDS_1 of IOBUFDS Module.
+//------------------------------------------------------------------------------
 IOBUFDS IOBUFDS_1(
-	.I(a7ddrphy_dqs_o_no_delay1),
-	.T(a7ddrphy_dqs_t1),
-	.IO(ddram_dqs_p[1]),
-	.IOB(ddram_dqs_n[1])
+	// Inputs.
+	.I   (main_a7ddrphy_dqs_o_no_delay1),
+	.T   (main_a7ddrphy_dqs_t1),
+
+	// InOuts.
+	.IO  (ddram_dqs_p[1]),
+	.IOB (ddram_dqs_n[1])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_29 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_29 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip01[0]),
-	.D2(a7ddrphy_bitslip01[1]),
-	.D3(a7ddrphy_bitslip01[2]),
-	.D4(a7ddrphy_bitslip01[3]),
-	.D5(a7ddrphy_bitslip01[4]),
-	.D6(a7ddrphy_bitslip01[5]),
-	.D7(a7ddrphy_bitslip01[6]),
-	.D8(a7ddrphy_bitslip01[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_dm[0])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip01[0]),
+	.D2     (main_a7ddrphy_bitslip01[1]),
+	.D3     (main_a7ddrphy_bitslip01[2]),
+	.D4     (main_a7ddrphy_bitslip01[3]),
+	.D5     (main_a7ddrphy_bitslip01[4]),
+	.D6     (main_a7ddrphy_bitslip01[5]),
+	.D7     (main_a7ddrphy_bitslip01[6]),
+	.D8     (main_a7ddrphy_bitslip01[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_dm[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_30 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_30 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip11[0]),
-	.D2(a7ddrphy_bitslip11[1]),
-	.D3(a7ddrphy_bitslip11[2]),
-	.D4(a7ddrphy_bitslip11[3]),
-	.D5(a7ddrphy_bitslip11[4]),
-	.D6(a7ddrphy_bitslip11[5]),
-	.D7(a7ddrphy_bitslip11[6]),
-	.D8(a7ddrphy_bitslip11[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_dm[1])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip11[0]),
+	.D2     (main_a7ddrphy_bitslip11[1]),
+	.D3     (main_a7ddrphy_bitslip11[2]),
+	.D4     (main_a7ddrphy_bitslip11[3]),
+	.D5     (main_a7ddrphy_bitslip11[4]),
+	.D6     (main_a7ddrphy_bitslip11[5]),
+	.D7     (main_a7ddrphy_bitslip11[6]),
+	.D8     (main_a7ddrphy_bitslip11[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_dm[1])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_31 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_31 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip02[0]),
-	.D2(a7ddrphy_bitslip02[1]),
-	.D3(a7ddrphy_bitslip02[2]),
-	.D4(a7ddrphy_bitslip02[3]),
-	.D5(a7ddrphy_bitslip02[4]),
-	.D6(a7ddrphy_bitslip02[5]),
-	.D7(a7ddrphy_bitslip02[6]),
-	.D8(a7ddrphy_bitslip02[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay0),
-	.TQ(a7ddrphy_dq_t0)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip02[0]),
+	.D2     (main_a7ddrphy_bitslip02[1]),
+	.D3     (main_a7ddrphy_bitslip02[2]),
+	.D4     (main_a7ddrphy_bitslip02[3]),
+	.D5     (main_a7ddrphy_bitslip02[4]),
+	.D6     (main_a7ddrphy_bitslip02[5]),
+	.D7     (main_a7ddrphy_bitslip02[6]),
+	.D8     (main_a7ddrphy_bitslip02[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay0),
+	.TQ     (main_a7ddrphy_dq_t0)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed0),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip03[7]),
-	.Q2(a7ddrphy_bitslip03[6]),
-	.Q3(a7ddrphy_bitslip03[5]),
-	.Q4(a7ddrphy_bitslip03[4]),
-	.Q5(a7ddrphy_bitslip03[3]),
-	.Q6(a7ddrphy_bitslip03[2]),
-	.Q7(a7ddrphy_bitslip03[1]),
-	.Q8(a7ddrphy_bitslip03[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed0),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip03[7]),
+	.Q2      (main_a7ddrphy_bitslip03[6]),
+	.Q3      (main_a7ddrphy_bitslip03[5]),
+	.Q4      (main_a7ddrphy_bitslip03[4]),
+	.Q5      (main_a7ddrphy_bitslip03[3]),
+	.Q6      (main_a7ddrphy_bitslip03[2]),
+	.Q7      (main_a7ddrphy_bitslip03[1]),
+	.Q8      (main_a7ddrphy_bitslip03[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay0),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed0)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay0),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed0)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF(
-	.I(a7ddrphy_dq_o_nodelay0),
-	.T(a7ddrphy_dq_t0),
-	.IO(ddram_dq[0]),
-	.O(a7ddrphy_dq_i_nodelay0)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay0),
+	.T  (main_a7ddrphy_dq_t0),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay0),
+
+	// InOuts.
+	.IO (ddram_dq[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_32 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_32 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip12[0]),
-	.D2(a7ddrphy_bitslip12[1]),
-	.D3(a7ddrphy_bitslip12[2]),
-	.D4(a7ddrphy_bitslip12[3]),
-	.D5(a7ddrphy_bitslip12[4]),
-	.D6(a7ddrphy_bitslip12[5]),
-	.D7(a7ddrphy_bitslip12[6]),
-	.D8(a7ddrphy_bitslip12[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay1),
-	.TQ(a7ddrphy_dq_t1)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip12[0]),
+	.D2     (main_a7ddrphy_bitslip12[1]),
+	.D3     (main_a7ddrphy_bitslip12[2]),
+	.D4     (main_a7ddrphy_bitslip12[3]),
+	.D5     (main_a7ddrphy_bitslip12[4]),
+	.D6     (main_a7ddrphy_bitslip12[5]),
+	.D7     (main_a7ddrphy_bitslip12[6]),
+	.D8     (main_a7ddrphy_bitslip12[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay1),
+	.TQ     (main_a7ddrphy_dq_t1)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_1 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_1 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip13[7]),
-	.Q2(a7ddrphy_bitslip13[6]),
-	.Q3(a7ddrphy_bitslip13[5]),
-	.Q4(a7ddrphy_bitslip13[4]),
-	.Q5(a7ddrphy_bitslip13[3]),
-	.Q6(a7ddrphy_bitslip13[2]),
-	.Q7(a7ddrphy_bitslip13[1]),
-	.Q8(a7ddrphy_bitslip13[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed1),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip13[7]),
+	.Q2      (main_a7ddrphy_bitslip13[6]),
+	.Q3      (main_a7ddrphy_bitslip13[5]),
+	.Q4      (main_a7ddrphy_bitslip13[4]),
+	.Q5      (main_a7ddrphy_bitslip13[3]),
+	.Q6      (main_a7ddrphy_bitslip13[2]),
+	.Q7      (main_a7ddrphy_bitslip13[1]),
+	.Q8      (main_a7ddrphy_bitslip13[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_1 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_1 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay1),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed1)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay1),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed1)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_1 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_1(
-	.I(a7ddrphy_dq_o_nodelay1),
-	.T(a7ddrphy_dq_t1),
-	.IO(ddram_dq[1]),
-	.O(a7ddrphy_dq_i_nodelay1)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay1),
+	.T  (main_a7ddrphy_dq_t1),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay1),
+
+	// InOuts.
+	.IO (ddram_dq[1])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_33 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_33 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip20[0]),
-	.D2(a7ddrphy_bitslip20[1]),
-	.D3(a7ddrphy_bitslip20[2]),
-	.D4(a7ddrphy_bitslip20[3]),
-	.D5(a7ddrphy_bitslip20[4]),
-	.D6(a7ddrphy_bitslip20[5]),
-	.D7(a7ddrphy_bitslip20[6]),
-	.D8(a7ddrphy_bitslip20[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay2),
-	.TQ(a7ddrphy_dq_t2)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip20[0]),
+	.D2     (main_a7ddrphy_bitslip20[1]),
+	.D3     (main_a7ddrphy_bitslip20[2]),
+	.D4     (main_a7ddrphy_bitslip20[3]),
+	.D5     (main_a7ddrphy_bitslip20[4]),
+	.D6     (main_a7ddrphy_bitslip20[5]),
+	.D7     (main_a7ddrphy_bitslip20[6]),
+	.D8     (main_a7ddrphy_bitslip20[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay2),
+	.TQ     (main_a7ddrphy_dq_t2)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_2 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_2 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed2),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip21[7]),
-	.Q2(a7ddrphy_bitslip21[6]),
-	.Q3(a7ddrphy_bitslip21[5]),
-	.Q4(a7ddrphy_bitslip21[4]),
-	.Q5(a7ddrphy_bitslip21[3]),
-	.Q6(a7ddrphy_bitslip21[2]),
-	.Q7(a7ddrphy_bitslip21[1]),
-	.Q8(a7ddrphy_bitslip21[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed2),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip21[7]),
+	.Q2      (main_a7ddrphy_bitslip21[6]),
+	.Q3      (main_a7ddrphy_bitslip21[5]),
+	.Q4      (main_a7ddrphy_bitslip21[4]),
+	.Q5      (main_a7ddrphy_bitslip21[3]),
+	.Q6      (main_a7ddrphy_bitslip21[2]),
+	.Q7      (main_a7ddrphy_bitslip21[1]),
+	.Q8      (main_a7ddrphy_bitslip21[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_2 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_2 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay2),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed2)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay2),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed2)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_2 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_2(
-	.I(a7ddrphy_dq_o_nodelay2),
-	.T(a7ddrphy_dq_t2),
-	.IO(ddram_dq[2]),
-	.O(a7ddrphy_dq_i_nodelay2)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay2),
+	.T  (main_a7ddrphy_dq_t2),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay2),
+
+	// InOuts.
+	.IO (ddram_dq[2])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_34 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_34 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip30[0]),
-	.D2(a7ddrphy_bitslip30[1]),
-	.D3(a7ddrphy_bitslip30[2]),
-	.D4(a7ddrphy_bitslip30[3]),
-	.D5(a7ddrphy_bitslip30[4]),
-	.D6(a7ddrphy_bitslip30[5]),
-	.D7(a7ddrphy_bitslip30[6]),
-	.D8(a7ddrphy_bitslip30[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay3),
-	.TQ(a7ddrphy_dq_t3)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip30[0]),
+	.D2     (main_a7ddrphy_bitslip30[1]),
+	.D3     (main_a7ddrphy_bitslip30[2]),
+	.D4     (main_a7ddrphy_bitslip30[3]),
+	.D5     (main_a7ddrphy_bitslip30[4]),
+	.D6     (main_a7ddrphy_bitslip30[5]),
+	.D7     (main_a7ddrphy_bitslip30[6]),
+	.D8     (main_a7ddrphy_bitslip30[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay3),
+	.TQ     (main_a7ddrphy_dq_t3)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_3 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_3 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed3),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip31[7]),
-	.Q2(a7ddrphy_bitslip31[6]),
-	.Q3(a7ddrphy_bitslip31[5]),
-	.Q4(a7ddrphy_bitslip31[4]),
-	.Q5(a7ddrphy_bitslip31[3]),
-	.Q6(a7ddrphy_bitslip31[2]),
-	.Q7(a7ddrphy_bitslip31[1]),
-	.Q8(a7ddrphy_bitslip31[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed3),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip31[7]),
+	.Q2      (main_a7ddrphy_bitslip31[6]),
+	.Q3      (main_a7ddrphy_bitslip31[5]),
+	.Q4      (main_a7ddrphy_bitslip31[4]),
+	.Q5      (main_a7ddrphy_bitslip31[3]),
+	.Q6      (main_a7ddrphy_bitslip31[2]),
+	.Q7      (main_a7ddrphy_bitslip31[1]),
+	.Q8      (main_a7ddrphy_bitslip31[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_3 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_3 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay3),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed3)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay3),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed3)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_3 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_3(
-	.I(a7ddrphy_dq_o_nodelay3),
-	.T(a7ddrphy_dq_t3),
-	.IO(ddram_dq[3]),
-	.O(a7ddrphy_dq_i_nodelay3)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay3),
+	.T  (main_a7ddrphy_dq_t3),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay3),
+
+	// InOuts.
+	.IO (ddram_dq[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_35 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_35 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip40[0]),
-	.D2(a7ddrphy_bitslip40[1]),
-	.D3(a7ddrphy_bitslip40[2]),
-	.D4(a7ddrphy_bitslip40[3]),
-	.D5(a7ddrphy_bitslip40[4]),
-	.D6(a7ddrphy_bitslip40[5]),
-	.D7(a7ddrphy_bitslip40[6]),
-	.D8(a7ddrphy_bitslip40[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay4),
-	.TQ(a7ddrphy_dq_t4)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip40[0]),
+	.D2     (main_a7ddrphy_bitslip40[1]),
+	.D3     (main_a7ddrphy_bitslip40[2]),
+	.D4     (main_a7ddrphy_bitslip40[3]),
+	.D5     (main_a7ddrphy_bitslip40[4]),
+	.D6     (main_a7ddrphy_bitslip40[5]),
+	.D7     (main_a7ddrphy_bitslip40[6]),
+	.D8     (main_a7ddrphy_bitslip40[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay4),
+	.TQ     (main_a7ddrphy_dq_t4)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_4 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_4 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed4),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip41[7]),
-	.Q2(a7ddrphy_bitslip41[6]),
-	.Q3(a7ddrphy_bitslip41[5]),
-	.Q4(a7ddrphy_bitslip41[4]),
-	.Q5(a7ddrphy_bitslip41[3]),
-	.Q6(a7ddrphy_bitslip41[2]),
-	.Q7(a7ddrphy_bitslip41[1]),
-	.Q8(a7ddrphy_bitslip41[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed4),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip41[7]),
+	.Q2      (main_a7ddrphy_bitslip41[6]),
+	.Q3      (main_a7ddrphy_bitslip41[5]),
+	.Q4      (main_a7ddrphy_bitslip41[4]),
+	.Q5      (main_a7ddrphy_bitslip41[3]),
+	.Q6      (main_a7ddrphy_bitslip41[2]),
+	.Q7      (main_a7ddrphy_bitslip41[1]),
+	.Q8      (main_a7ddrphy_bitslip41[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_4 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_4 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay4),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed4)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay4),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed4)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_4 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_4(
-	.I(a7ddrphy_dq_o_nodelay4),
-	.T(a7ddrphy_dq_t4),
-	.IO(ddram_dq[4]),
-	.O(a7ddrphy_dq_i_nodelay4)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay4),
+	.T  (main_a7ddrphy_dq_t4),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay4),
+
+	// InOuts.
+	.IO (ddram_dq[4])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_36 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_36 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip50[0]),
-	.D2(a7ddrphy_bitslip50[1]),
-	.D3(a7ddrphy_bitslip50[2]),
-	.D4(a7ddrphy_bitslip50[3]),
-	.D5(a7ddrphy_bitslip50[4]),
-	.D6(a7ddrphy_bitslip50[5]),
-	.D7(a7ddrphy_bitslip50[6]),
-	.D8(a7ddrphy_bitslip50[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay5),
-	.TQ(a7ddrphy_dq_t5)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip50[0]),
+	.D2     (main_a7ddrphy_bitslip50[1]),
+	.D3     (main_a7ddrphy_bitslip50[2]),
+	.D4     (main_a7ddrphy_bitslip50[3]),
+	.D5     (main_a7ddrphy_bitslip50[4]),
+	.D6     (main_a7ddrphy_bitslip50[5]),
+	.D7     (main_a7ddrphy_bitslip50[6]),
+	.D8     (main_a7ddrphy_bitslip50[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay5),
+	.TQ     (main_a7ddrphy_dq_t5)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_5 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_5 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed5),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip51[7]),
-	.Q2(a7ddrphy_bitslip51[6]),
-	.Q3(a7ddrphy_bitslip51[5]),
-	.Q4(a7ddrphy_bitslip51[4]),
-	.Q5(a7ddrphy_bitslip51[3]),
-	.Q6(a7ddrphy_bitslip51[2]),
-	.Q7(a7ddrphy_bitslip51[1]),
-	.Q8(a7ddrphy_bitslip51[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed5),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip51[7]),
+	.Q2      (main_a7ddrphy_bitslip51[6]),
+	.Q3      (main_a7ddrphy_bitslip51[5]),
+	.Q4      (main_a7ddrphy_bitslip51[4]),
+	.Q5      (main_a7ddrphy_bitslip51[3]),
+	.Q6      (main_a7ddrphy_bitslip51[2]),
+	.Q7      (main_a7ddrphy_bitslip51[1]),
+	.Q8      (main_a7ddrphy_bitslip51[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_5 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_5 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay5),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed5)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay5),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed5)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_5 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_5(
-	.I(a7ddrphy_dq_o_nodelay5),
-	.T(a7ddrphy_dq_t5),
-	.IO(ddram_dq[5]),
-	.O(a7ddrphy_dq_i_nodelay5)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay5),
+	.T  (main_a7ddrphy_dq_t5),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay5),
+
+	// InOuts.
+	.IO (ddram_dq[5])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_37 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_37 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip60[0]),
-	.D2(a7ddrphy_bitslip60[1]),
-	.D3(a7ddrphy_bitslip60[2]),
-	.D4(a7ddrphy_bitslip60[3]),
-	.D5(a7ddrphy_bitslip60[4]),
-	.D6(a7ddrphy_bitslip60[5]),
-	.D7(a7ddrphy_bitslip60[6]),
-	.D8(a7ddrphy_bitslip60[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay6),
-	.TQ(a7ddrphy_dq_t6)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip60[0]),
+	.D2     (main_a7ddrphy_bitslip60[1]),
+	.D3     (main_a7ddrphy_bitslip60[2]),
+	.D4     (main_a7ddrphy_bitslip60[3]),
+	.D5     (main_a7ddrphy_bitslip60[4]),
+	.D6     (main_a7ddrphy_bitslip60[5]),
+	.D7     (main_a7ddrphy_bitslip60[6]),
+	.D8     (main_a7ddrphy_bitslip60[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay6),
+	.TQ     (main_a7ddrphy_dq_t6)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_6 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_6 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed6),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip61[7]),
-	.Q2(a7ddrphy_bitslip61[6]),
-	.Q3(a7ddrphy_bitslip61[5]),
-	.Q4(a7ddrphy_bitslip61[4]),
-	.Q5(a7ddrphy_bitslip61[3]),
-	.Q6(a7ddrphy_bitslip61[2]),
-	.Q7(a7ddrphy_bitslip61[1]),
-	.Q8(a7ddrphy_bitslip61[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed6),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip61[7]),
+	.Q2      (main_a7ddrphy_bitslip61[6]),
+	.Q3      (main_a7ddrphy_bitslip61[5]),
+	.Q4      (main_a7ddrphy_bitslip61[4]),
+	.Q5      (main_a7ddrphy_bitslip61[3]),
+	.Q6      (main_a7ddrphy_bitslip61[2]),
+	.Q7      (main_a7ddrphy_bitslip61[1]),
+	.Q8      (main_a7ddrphy_bitslip61[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_6 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_6 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay6),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed6)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay6),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed6)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_6 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_6(
-	.I(a7ddrphy_dq_o_nodelay6),
-	.T(a7ddrphy_dq_t6),
-	.IO(ddram_dq[6]),
-	.O(a7ddrphy_dq_i_nodelay6)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay6),
+	.T  (main_a7ddrphy_dq_t6),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay6),
+
+	// InOuts.
+	.IO (ddram_dq[6])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_38 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_38 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip70[0]),
-	.D2(a7ddrphy_bitslip70[1]),
-	.D3(a7ddrphy_bitslip70[2]),
-	.D4(a7ddrphy_bitslip70[3]),
-	.D5(a7ddrphy_bitslip70[4]),
-	.D6(a7ddrphy_bitslip70[5]),
-	.D7(a7ddrphy_bitslip70[6]),
-	.D8(a7ddrphy_bitslip70[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay7),
-	.TQ(a7ddrphy_dq_t7)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip70[0]),
+	.D2     (main_a7ddrphy_bitslip70[1]),
+	.D3     (main_a7ddrphy_bitslip70[2]),
+	.D4     (main_a7ddrphy_bitslip70[3]),
+	.D5     (main_a7ddrphy_bitslip70[4]),
+	.D6     (main_a7ddrphy_bitslip70[5]),
+	.D7     (main_a7ddrphy_bitslip70[6]),
+	.D8     (main_a7ddrphy_bitslip70[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay7),
+	.TQ     (main_a7ddrphy_dq_t7)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_7 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_7 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed7),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip71[7]),
-	.Q2(a7ddrphy_bitslip71[6]),
-	.Q3(a7ddrphy_bitslip71[5]),
-	.Q4(a7ddrphy_bitslip71[4]),
-	.Q5(a7ddrphy_bitslip71[3]),
-	.Q6(a7ddrphy_bitslip71[2]),
-	.Q7(a7ddrphy_bitslip71[1]),
-	.Q8(a7ddrphy_bitslip71[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed7),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip71[7]),
+	.Q2      (main_a7ddrphy_bitslip71[6]),
+	.Q3      (main_a7ddrphy_bitslip71[5]),
+	.Q4      (main_a7ddrphy_bitslip71[4]),
+	.Q5      (main_a7ddrphy_bitslip71[3]),
+	.Q6      (main_a7ddrphy_bitslip71[2]),
+	.Q7      (main_a7ddrphy_bitslip71[1]),
+	.Q8      (main_a7ddrphy_bitslip71[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_7 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_7 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay7),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed7)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay7),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed7)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_7 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_7(
-	.I(a7ddrphy_dq_o_nodelay7),
-	.T(a7ddrphy_dq_t7),
-	.IO(ddram_dq[7]),
-	.O(a7ddrphy_dq_i_nodelay7)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay7),
+	.T  (main_a7ddrphy_dq_t7),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay7),
+
+	// InOuts.
+	.IO (ddram_dq[7])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_39 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_39 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip80[0]),
-	.D2(a7ddrphy_bitslip80[1]),
-	.D3(a7ddrphy_bitslip80[2]),
-	.D4(a7ddrphy_bitslip80[3]),
-	.D5(a7ddrphy_bitslip80[4]),
-	.D6(a7ddrphy_bitslip80[5]),
-	.D7(a7ddrphy_bitslip80[6]),
-	.D8(a7ddrphy_bitslip80[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay8),
-	.TQ(a7ddrphy_dq_t8)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip80[0]),
+	.D2     (main_a7ddrphy_bitslip80[1]),
+	.D3     (main_a7ddrphy_bitslip80[2]),
+	.D4     (main_a7ddrphy_bitslip80[3]),
+	.D5     (main_a7ddrphy_bitslip80[4]),
+	.D6     (main_a7ddrphy_bitslip80[5]),
+	.D7     (main_a7ddrphy_bitslip80[6]),
+	.D8     (main_a7ddrphy_bitslip80[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay8),
+	.TQ     (main_a7ddrphy_dq_t8)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_8 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_8 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed8),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip81[7]),
-	.Q2(a7ddrphy_bitslip81[6]),
-	.Q3(a7ddrphy_bitslip81[5]),
-	.Q4(a7ddrphy_bitslip81[4]),
-	.Q5(a7ddrphy_bitslip81[3]),
-	.Q6(a7ddrphy_bitslip81[2]),
-	.Q7(a7ddrphy_bitslip81[1]),
-	.Q8(a7ddrphy_bitslip81[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed8),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip81[7]),
+	.Q2      (main_a7ddrphy_bitslip81[6]),
+	.Q3      (main_a7ddrphy_bitslip81[5]),
+	.Q4      (main_a7ddrphy_bitslip81[4]),
+	.Q5      (main_a7ddrphy_bitslip81[3]),
+	.Q6      (main_a7ddrphy_bitslip81[2]),
+	.Q7      (main_a7ddrphy_bitslip81[1]),
+	.Q8      (main_a7ddrphy_bitslip81[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_8 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_8 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay8),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed8)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay8),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed8)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_8 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_8(
-	.I(a7ddrphy_dq_o_nodelay8),
-	.T(a7ddrphy_dq_t8),
-	.IO(ddram_dq[8]),
-	.O(a7ddrphy_dq_i_nodelay8)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay8),
+	.T  (main_a7ddrphy_dq_t8),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay8),
+
+	// InOuts.
+	.IO (ddram_dq[8])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_40 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_40 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip90[0]),
-	.D2(a7ddrphy_bitslip90[1]),
-	.D3(a7ddrphy_bitslip90[2]),
-	.D4(a7ddrphy_bitslip90[3]),
-	.D5(a7ddrphy_bitslip90[4]),
-	.D6(a7ddrphy_bitslip90[5]),
-	.D7(a7ddrphy_bitslip90[6]),
-	.D8(a7ddrphy_bitslip90[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay9),
-	.TQ(a7ddrphy_dq_t9)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip90[0]),
+	.D2     (main_a7ddrphy_bitslip90[1]),
+	.D3     (main_a7ddrphy_bitslip90[2]),
+	.D4     (main_a7ddrphy_bitslip90[3]),
+	.D5     (main_a7ddrphy_bitslip90[4]),
+	.D6     (main_a7ddrphy_bitslip90[5]),
+	.D7     (main_a7ddrphy_bitslip90[6]),
+	.D8     (main_a7ddrphy_bitslip90[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay9),
+	.TQ     (main_a7ddrphy_dq_t9)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_9 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_9 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed9),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip91[7]),
-	.Q2(a7ddrphy_bitslip91[6]),
-	.Q3(a7ddrphy_bitslip91[5]),
-	.Q4(a7ddrphy_bitslip91[4]),
-	.Q5(a7ddrphy_bitslip91[3]),
-	.Q6(a7ddrphy_bitslip91[2]),
-	.Q7(a7ddrphy_bitslip91[1]),
-	.Q8(a7ddrphy_bitslip91[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed9),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip91[7]),
+	.Q2      (main_a7ddrphy_bitslip91[6]),
+	.Q3      (main_a7ddrphy_bitslip91[5]),
+	.Q4      (main_a7ddrphy_bitslip91[4]),
+	.Q5      (main_a7ddrphy_bitslip91[3]),
+	.Q6      (main_a7ddrphy_bitslip91[2]),
+	.Q7      (main_a7ddrphy_bitslip91[1]),
+	.Q8      (main_a7ddrphy_bitslip91[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_9 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_9 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay9),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed9)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay9),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed9)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_9 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_9(
-	.I(a7ddrphy_dq_o_nodelay9),
-	.T(a7ddrphy_dq_t9),
-	.IO(ddram_dq[9]),
-	.O(a7ddrphy_dq_i_nodelay9)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay9),
+	.T  (main_a7ddrphy_dq_t9),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay9),
+
+	// InOuts.
+	.IO (ddram_dq[9])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_41 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_41 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip100[0]),
-	.D2(a7ddrphy_bitslip100[1]),
-	.D3(a7ddrphy_bitslip100[2]),
-	.D4(a7ddrphy_bitslip100[3]),
-	.D5(a7ddrphy_bitslip100[4]),
-	.D6(a7ddrphy_bitslip100[5]),
-	.D7(a7ddrphy_bitslip100[6]),
-	.D8(a7ddrphy_bitslip100[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay10),
-	.TQ(a7ddrphy_dq_t10)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip100[0]),
+	.D2     (main_a7ddrphy_bitslip100[1]),
+	.D3     (main_a7ddrphy_bitslip100[2]),
+	.D4     (main_a7ddrphy_bitslip100[3]),
+	.D5     (main_a7ddrphy_bitslip100[4]),
+	.D6     (main_a7ddrphy_bitslip100[5]),
+	.D7     (main_a7ddrphy_bitslip100[6]),
+	.D8     (main_a7ddrphy_bitslip100[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay10),
+	.TQ     (main_a7ddrphy_dq_t10)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_10 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_10 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed10),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip101[7]),
-	.Q2(a7ddrphy_bitslip101[6]),
-	.Q3(a7ddrphy_bitslip101[5]),
-	.Q4(a7ddrphy_bitslip101[4]),
-	.Q5(a7ddrphy_bitslip101[3]),
-	.Q6(a7ddrphy_bitslip101[2]),
-	.Q7(a7ddrphy_bitslip101[1]),
-	.Q8(a7ddrphy_bitslip101[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed10),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip101[7]),
+	.Q2      (main_a7ddrphy_bitslip101[6]),
+	.Q3      (main_a7ddrphy_bitslip101[5]),
+	.Q4      (main_a7ddrphy_bitslip101[4]),
+	.Q5      (main_a7ddrphy_bitslip101[3]),
+	.Q6      (main_a7ddrphy_bitslip101[2]),
+	.Q7      (main_a7ddrphy_bitslip101[1]),
+	.Q8      (main_a7ddrphy_bitslip101[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_10 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_10 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay10),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed10)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay10),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed10)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_10 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_10(
-	.I(a7ddrphy_dq_o_nodelay10),
-	.T(a7ddrphy_dq_t10),
-	.IO(ddram_dq[10]),
-	.O(a7ddrphy_dq_i_nodelay10)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay10),
+	.T  (main_a7ddrphy_dq_t10),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay10),
+
+	// InOuts.
+	.IO (ddram_dq[10])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_42 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_42 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip110[0]),
-	.D2(a7ddrphy_bitslip110[1]),
-	.D3(a7ddrphy_bitslip110[2]),
-	.D4(a7ddrphy_bitslip110[3]),
-	.D5(a7ddrphy_bitslip110[4]),
-	.D6(a7ddrphy_bitslip110[5]),
-	.D7(a7ddrphy_bitslip110[6]),
-	.D8(a7ddrphy_bitslip110[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay11),
-	.TQ(a7ddrphy_dq_t11)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip110[0]),
+	.D2     (main_a7ddrphy_bitslip110[1]),
+	.D3     (main_a7ddrphy_bitslip110[2]),
+	.D4     (main_a7ddrphy_bitslip110[3]),
+	.D5     (main_a7ddrphy_bitslip110[4]),
+	.D6     (main_a7ddrphy_bitslip110[5]),
+	.D7     (main_a7ddrphy_bitslip110[6]),
+	.D8     (main_a7ddrphy_bitslip110[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay11),
+	.TQ     (main_a7ddrphy_dq_t11)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_11 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_11 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed11),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip111[7]),
-	.Q2(a7ddrphy_bitslip111[6]),
-	.Q3(a7ddrphy_bitslip111[5]),
-	.Q4(a7ddrphy_bitslip111[4]),
-	.Q5(a7ddrphy_bitslip111[3]),
-	.Q6(a7ddrphy_bitslip111[2]),
-	.Q7(a7ddrphy_bitslip111[1]),
-	.Q8(a7ddrphy_bitslip111[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed11),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip111[7]),
+	.Q2      (main_a7ddrphy_bitslip111[6]),
+	.Q3      (main_a7ddrphy_bitslip111[5]),
+	.Q4      (main_a7ddrphy_bitslip111[4]),
+	.Q5      (main_a7ddrphy_bitslip111[3]),
+	.Q6      (main_a7ddrphy_bitslip111[2]),
+	.Q7      (main_a7ddrphy_bitslip111[1]),
+	.Q8      (main_a7ddrphy_bitslip111[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_11 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_11 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay11),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed11)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay11),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed11)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_11 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_11(
-	.I(a7ddrphy_dq_o_nodelay11),
-	.T(a7ddrphy_dq_t11),
-	.IO(ddram_dq[11]),
-	.O(a7ddrphy_dq_i_nodelay11)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay11),
+	.T  (main_a7ddrphy_dq_t11),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay11),
+
+	// InOuts.
+	.IO (ddram_dq[11])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_43 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_43 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip120[0]),
-	.D2(a7ddrphy_bitslip120[1]),
-	.D3(a7ddrphy_bitslip120[2]),
-	.D4(a7ddrphy_bitslip120[3]),
-	.D5(a7ddrphy_bitslip120[4]),
-	.D6(a7ddrphy_bitslip120[5]),
-	.D7(a7ddrphy_bitslip120[6]),
-	.D8(a7ddrphy_bitslip120[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay12),
-	.TQ(a7ddrphy_dq_t12)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip120[0]),
+	.D2     (main_a7ddrphy_bitslip120[1]),
+	.D3     (main_a7ddrphy_bitslip120[2]),
+	.D4     (main_a7ddrphy_bitslip120[3]),
+	.D5     (main_a7ddrphy_bitslip120[4]),
+	.D6     (main_a7ddrphy_bitslip120[5]),
+	.D7     (main_a7ddrphy_bitslip120[6]),
+	.D8     (main_a7ddrphy_bitslip120[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay12),
+	.TQ     (main_a7ddrphy_dq_t12)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_12 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_12 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed12),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip121[7]),
-	.Q2(a7ddrphy_bitslip121[6]),
-	.Q3(a7ddrphy_bitslip121[5]),
-	.Q4(a7ddrphy_bitslip121[4]),
-	.Q5(a7ddrphy_bitslip121[3]),
-	.Q6(a7ddrphy_bitslip121[2]),
-	.Q7(a7ddrphy_bitslip121[1]),
-	.Q8(a7ddrphy_bitslip121[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed12),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip121[7]),
+	.Q2      (main_a7ddrphy_bitslip121[6]),
+	.Q3      (main_a7ddrphy_bitslip121[5]),
+	.Q4      (main_a7ddrphy_bitslip121[4]),
+	.Q5      (main_a7ddrphy_bitslip121[3]),
+	.Q6      (main_a7ddrphy_bitslip121[2]),
+	.Q7      (main_a7ddrphy_bitslip121[1]),
+	.Q8      (main_a7ddrphy_bitslip121[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_12 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_12 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay12),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed12)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay12),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed12)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_12 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_12(
-	.I(a7ddrphy_dq_o_nodelay12),
-	.T(a7ddrphy_dq_t12),
-	.IO(ddram_dq[12]),
-	.O(a7ddrphy_dq_i_nodelay12)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay12),
+	.T  (main_a7ddrphy_dq_t12),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay12),
+
+	// InOuts.
+	.IO (ddram_dq[12])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_44 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_44 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip130[0]),
-	.D2(a7ddrphy_bitslip130[1]),
-	.D3(a7ddrphy_bitslip130[2]),
-	.D4(a7ddrphy_bitslip130[3]),
-	.D5(a7ddrphy_bitslip130[4]),
-	.D6(a7ddrphy_bitslip130[5]),
-	.D7(a7ddrphy_bitslip130[6]),
-	.D8(a7ddrphy_bitslip130[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay13),
-	.TQ(a7ddrphy_dq_t13)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip130[0]),
+	.D2     (main_a7ddrphy_bitslip130[1]),
+	.D3     (main_a7ddrphy_bitslip130[2]),
+	.D4     (main_a7ddrphy_bitslip130[3]),
+	.D5     (main_a7ddrphy_bitslip130[4]),
+	.D6     (main_a7ddrphy_bitslip130[5]),
+	.D7     (main_a7ddrphy_bitslip130[6]),
+	.D8     (main_a7ddrphy_bitslip130[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay13),
+	.TQ     (main_a7ddrphy_dq_t13)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_13 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_13 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed13),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip131[7]),
-	.Q2(a7ddrphy_bitslip131[6]),
-	.Q3(a7ddrphy_bitslip131[5]),
-	.Q4(a7ddrphy_bitslip131[4]),
-	.Q5(a7ddrphy_bitslip131[3]),
-	.Q6(a7ddrphy_bitslip131[2]),
-	.Q7(a7ddrphy_bitslip131[1]),
-	.Q8(a7ddrphy_bitslip131[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed13),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip131[7]),
+	.Q2      (main_a7ddrphy_bitslip131[6]),
+	.Q3      (main_a7ddrphy_bitslip131[5]),
+	.Q4      (main_a7ddrphy_bitslip131[4]),
+	.Q5      (main_a7ddrphy_bitslip131[3]),
+	.Q6      (main_a7ddrphy_bitslip131[2]),
+	.Q7      (main_a7ddrphy_bitslip131[1]),
+	.Q8      (main_a7ddrphy_bitslip131[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_13 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_13 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay13),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed13)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay13),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed13)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_13 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_13(
-	.I(a7ddrphy_dq_o_nodelay13),
-	.T(a7ddrphy_dq_t13),
-	.IO(ddram_dq[13]),
-	.O(a7ddrphy_dq_i_nodelay13)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay13),
+	.T  (main_a7ddrphy_dq_t13),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay13),
+
+	// InOuts.
+	.IO (ddram_dq[13])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_45 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_45 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip140[0]),
-	.D2(a7ddrphy_bitslip140[1]),
-	.D3(a7ddrphy_bitslip140[2]),
-	.D4(a7ddrphy_bitslip140[3]),
-	.D5(a7ddrphy_bitslip140[4]),
-	.D6(a7ddrphy_bitslip140[5]),
-	.D7(a7ddrphy_bitslip140[6]),
-	.D8(a7ddrphy_bitslip140[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay14),
-	.TQ(a7ddrphy_dq_t14)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip140[0]),
+	.D2     (main_a7ddrphy_bitslip140[1]),
+	.D3     (main_a7ddrphy_bitslip140[2]),
+	.D4     (main_a7ddrphy_bitslip140[3]),
+	.D5     (main_a7ddrphy_bitslip140[4]),
+	.D6     (main_a7ddrphy_bitslip140[5]),
+	.D7     (main_a7ddrphy_bitslip140[6]),
+	.D8     (main_a7ddrphy_bitslip140[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay14),
+	.TQ     (main_a7ddrphy_dq_t14)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_14 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_14 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed14),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip141[7]),
-	.Q2(a7ddrphy_bitslip141[6]),
-	.Q3(a7ddrphy_bitslip141[5]),
-	.Q4(a7ddrphy_bitslip141[4]),
-	.Q5(a7ddrphy_bitslip141[3]),
-	.Q6(a7ddrphy_bitslip141[2]),
-	.Q7(a7ddrphy_bitslip141[1]),
-	.Q8(a7ddrphy_bitslip141[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed14),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip141[7]),
+	.Q2      (main_a7ddrphy_bitslip141[6]),
+	.Q3      (main_a7ddrphy_bitslip141[5]),
+	.Q4      (main_a7ddrphy_bitslip141[4]),
+	.Q5      (main_a7ddrphy_bitslip141[3]),
+	.Q6      (main_a7ddrphy_bitslip141[2]),
+	.Q7      (main_a7ddrphy_bitslip141[1]),
+	.Q8      (main_a7ddrphy_bitslip141[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_14 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_14 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay14),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed14)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay14),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed14)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_14 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_14(
-	.I(a7ddrphy_dq_o_nodelay14),
-	.T(a7ddrphy_dq_t14),
-	.IO(ddram_dq[14]),
-	.O(a7ddrphy_dq_i_nodelay14)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay14),
+	.T  (main_a7ddrphy_dq_t14),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay14),
+
+	// InOuts.
+	.IO (ddram_dq[14])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_46 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_46 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip150[0]),
-	.D2(a7ddrphy_bitslip150[1]),
-	.D3(a7ddrphy_bitslip150[2]),
-	.D4(a7ddrphy_bitslip150[3]),
-	.D5(a7ddrphy_bitslip150[4]),
-	.D6(a7ddrphy_bitslip150[5]),
-	.D7(a7ddrphy_bitslip150[6]),
-	.D8(a7ddrphy_bitslip150[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay15),
-	.TQ(a7ddrphy_dq_t15)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip150[0]),
+	.D2     (main_a7ddrphy_bitslip150[1]),
+	.D3     (main_a7ddrphy_bitslip150[2]),
+	.D4     (main_a7ddrphy_bitslip150[3]),
+	.D5     (main_a7ddrphy_bitslip150[4]),
+	.D6     (main_a7ddrphy_bitslip150[5]),
+	.D7     (main_a7ddrphy_bitslip150[6]),
+	.D8     (main_a7ddrphy_bitslip150[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay15),
+	.TQ     (main_a7ddrphy_dq_t15)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_15 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_15 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed15),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip151[7]),
-	.Q2(a7ddrphy_bitslip151[6]),
-	.Q3(a7ddrphy_bitslip151[5]),
-	.Q4(a7ddrphy_bitslip151[4]),
-	.Q5(a7ddrphy_bitslip151[3]),
-	.Q6(a7ddrphy_bitslip151[2]),
-	.Q7(a7ddrphy_bitslip151[1]),
-	.Q8(a7ddrphy_bitslip151[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed15),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip151[7]),
+	.Q2      (main_a7ddrphy_bitslip151[6]),
+	.Q3      (main_a7ddrphy_bitslip151[5]),
+	.Q4      (main_a7ddrphy_bitslip151[4]),
+	.Q5      (main_a7ddrphy_bitslip151[3]),
+	.Q6      (main_a7ddrphy_bitslip151[2]),
+	.Q7      (main_a7ddrphy_bitslip151[1]),
+	.Q8      (main_a7ddrphy_bitslip151[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_15 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_15 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay15),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed15)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay15),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed15)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_15 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_15(
-	.I(a7ddrphy_dq_o_nodelay15),
-	.T(a7ddrphy_dq_t15),
-	.IO(ddram_dq[15]),
-	.O(a7ddrphy_dq_i_nodelay15)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay15),
+	.T  (main_a7ddrphy_dq_t15),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay15),
+
+	// InOuts.
+	.IO (ddram_dq[15])
 );
 
 //------------------------------------------------------------------------------
@@ -16075,14 +17219,14 @@ IOBUF IOBUF_15(
 reg [25:0] storage[0:15];
 reg [25:0] storage_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine0_wrport_we)
-		storage[litedramcore_bankmachine0_wrport_adr] <= litedramcore_bankmachine0_wrport_dat_w;
-	storage_dat0 <= storage[litedramcore_bankmachine0_wrport_adr];
+	if (main_litedramcore_bankmachine0_wrport_we)
+		storage[main_litedramcore_bankmachine0_wrport_adr] <= main_litedramcore_bankmachine0_wrport_dat_w;
+	storage_dat0 <= storage[main_litedramcore_bankmachine0_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine0_wrport_dat_r = storage_dat0;
-assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine0_rdport_adr];
+assign main_litedramcore_bankmachine0_wrport_dat_r = storage_dat0;
+assign main_litedramcore_bankmachine0_rdport_dat_r = storage[main_litedramcore_bankmachine0_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16093,14 +17237,14 @@ assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine
 reg [25:0] storage_1[0:15];
 reg [25:0] storage_1_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine1_wrport_we)
-		storage_1[litedramcore_bankmachine1_wrport_adr] <= litedramcore_bankmachine1_wrport_dat_w;
-	storage_1_dat0 <= storage_1[litedramcore_bankmachine1_wrport_adr];
+	if (main_litedramcore_bankmachine1_wrport_we)
+		storage_1[main_litedramcore_bankmachine1_wrport_adr] <= main_litedramcore_bankmachine1_wrport_dat_w;
+	storage_1_dat0 <= storage_1[main_litedramcore_bankmachine1_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0;
-assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachine1_rdport_adr];
+assign main_litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0;
+assign main_litedramcore_bankmachine1_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16111,14 +17255,14 @@ assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachi
 reg [25:0] storage_2[0:15];
 reg [25:0] storage_2_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine2_wrport_we)
-		storage_2[litedramcore_bankmachine2_wrport_adr] <= litedramcore_bankmachine2_wrport_dat_w;
-	storage_2_dat0 <= storage_2[litedramcore_bankmachine2_wrport_adr];
+	if (main_litedramcore_bankmachine2_wrport_we)
+		storage_2[main_litedramcore_bankmachine2_wrport_adr] <= main_litedramcore_bankmachine2_wrport_dat_w;
+	storage_2_dat0 <= storage_2[main_litedramcore_bankmachine2_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0;
-assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachine2_rdport_adr];
+assign main_litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0;
+assign main_litedramcore_bankmachine2_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16129,14 +17273,14 @@ assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachi
 reg [25:0] storage_3[0:15];
 reg [25:0] storage_3_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine3_wrport_we)
-		storage_3[litedramcore_bankmachine3_wrport_adr] <= litedramcore_bankmachine3_wrport_dat_w;
-	storage_3_dat0 <= storage_3[litedramcore_bankmachine3_wrport_adr];
+	if (main_litedramcore_bankmachine3_wrport_we)
+		storage_3[main_litedramcore_bankmachine3_wrport_adr] <= main_litedramcore_bankmachine3_wrport_dat_w;
+	storage_3_dat0 <= storage_3[main_litedramcore_bankmachine3_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0;
-assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachine3_rdport_adr];
+assign main_litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0;
+assign main_litedramcore_bankmachine3_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16147,14 +17291,14 @@ assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachi
 reg [25:0] storage_4[0:15];
 reg [25:0] storage_4_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine4_wrport_we)
-		storage_4[litedramcore_bankmachine4_wrport_adr] <= litedramcore_bankmachine4_wrport_dat_w;
-	storage_4_dat0 <= storage_4[litedramcore_bankmachine4_wrport_adr];
+	if (main_litedramcore_bankmachine4_wrport_we)
+		storage_4[main_litedramcore_bankmachine4_wrport_adr] <= main_litedramcore_bankmachine4_wrport_dat_w;
+	storage_4_dat0 <= storage_4[main_litedramcore_bankmachine4_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0;
-assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachine4_rdport_adr];
+assign main_litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0;
+assign main_litedramcore_bankmachine4_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16165,14 +17309,14 @@ assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachi
 reg [25:0] storage_5[0:15];
 reg [25:0] storage_5_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine5_wrport_we)
-		storage_5[litedramcore_bankmachine5_wrport_adr] <= litedramcore_bankmachine5_wrport_dat_w;
-	storage_5_dat0 <= storage_5[litedramcore_bankmachine5_wrport_adr];
+	if (main_litedramcore_bankmachine5_wrport_we)
+		storage_5[main_litedramcore_bankmachine5_wrport_adr] <= main_litedramcore_bankmachine5_wrport_dat_w;
+	storage_5_dat0 <= storage_5[main_litedramcore_bankmachine5_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0;
-assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachine5_rdport_adr];
+assign main_litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0;
+assign main_litedramcore_bankmachine5_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16183,14 +17327,14 @@ assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachi
 reg [25:0] storage_6[0:15];
 reg [25:0] storage_6_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine6_wrport_we)
-		storage_6[litedramcore_bankmachine6_wrport_adr] <= litedramcore_bankmachine6_wrport_dat_w;
-	storage_6_dat0 <= storage_6[litedramcore_bankmachine6_wrport_adr];
+	if (main_litedramcore_bankmachine6_wrport_we)
+		storage_6[main_litedramcore_bankmachine6_wrport_adr] <= main_litedramcore_bankmachine6_wrport_dat_w;
+	storage_6_dat0 <= storage_6[main_litedramcore_bankmachine6_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0;
-assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachine6_rdport_adr];
+assign main_litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0;
+assign main_litedramcore_bankmachine6_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16201,197 +17345,308 @@ assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachi
 reg [25:0] storage_7[0:15];
 reg [25:0] storage_7_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine7_wrport_we)
-		storage_7[litedramcore_bankmachine7_wrport_adr] <= litedramcore_bankmachine7_wrport_dat_w;
-	storage_7_dat0 <= storage_7[litedramcore_bankmachine7_wrport_adr];
+	if (main_litedramcore_bankmachine7_wrport_we)
+		storage_7[main_litedramcore_bankmachine7_wrport_adr] <= main_litedramcore_bankmachine7_wrport_dat_w;
+	storage_7_dat0 <= storage_7[main_litedramcore_bankmachine7_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0;
-assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachine7_rdport_adr];
+assign main_litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0;
+assign main_litedramcore_bankmachine7_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_rdport_adr];
 
 
+//------------------------------------------------------------------------------
+// Instance FDCE of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(reset),
-	.Q(litedramcore_reset0)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (main_reset),
+
+	// Outputs.
+	.Q   (builder_reset0)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_1 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_1(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset0),
-	.Q(litedramcore_reset1)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset0),
+
+	// Outputs.
+	.Q   (builder_reset1)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_2 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_2(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset1),
-	.Q(litedramcore_reset2)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset1),
+
+	// Outputs.
+	.Q   (builder_reset2)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_3 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_3(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset2),
-	.Q(litedramcore_reset3)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset2),
+
+	// Outputs.
+	.Q   (builder_reset3)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_4 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_4(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset3),
-	.Q(litedramcore_reset4)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset3),
+
+	// Outputs.
+	.Q   (builder_reset4)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_5 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_5(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset4),
-	.Q(litedramcore_reset5)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset4),
+
+	// Outputs.
+	.Q   (builder_reset5)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_6 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_6(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset5),
-	.Q(litedramcore_reset6)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset5),
+
+	// Outputs.
+	.Q   (builder_reset6)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_7 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_7(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset6),
-	.Q(litedramcore_reset7)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset6),
+
+	// Outputs.
+	.Q   (builder_reset7)
 );
 
+//------------------------------------------------------------------------------
+// Instance PLLE2_ADV of PLLE2_ADV Module.
+//------------------------------------------------------------------------------
 PLLE2_ADV #(
-	.CLKFBOUT_MULT(4'd8),
-	.CLKIN1_PERIOD(5.0),
-	.CLKOUT0_DIVIDE(4'd8),
-	.CLKOUT0_PHASE(1'd0),
-	.CLKOUT1_DIVIDE(5'd16),
-	.CLKOUT1_PHASE(1'd0),
-	.CLKOUT2_DIVIDE(3'd4),
-	.CLKOUT2_PHASE(1'd0),
-	.CLKOUT3_DIVIDE(3'd4),
-	.CLKOUT3_PHASE(7'd90),
-	.DIVCLK_DIVIDE(1'd1),
-	.REF_JITTER1(0.01),
-	.STARTUP_WAIT("FALSE")
+	// Parameters.
+	.CLKFBOUT_MULT  (4'd8),
+	.CLKIN1_PERIOD  (5.0),
+	.CLKOUT0_DIVIDE (4'd8),
+	.CLKOUT0_PHASE  (1'd0),
+	.CLKOUT1_DIVIDE (5'd16),
+	.CLKOUT1_PHASE  (1'd0),
+	.CLKOUT2_DIVIDE (3'd4),
+	.CLKOUT2_PHASE  (1'd0),
+	.CLKOUT3_DIVIDE (3'd4),
+	.CLKOUT3_PHASE  (7'd90),
+	.DIVCLK_DIVIDE  (1'd1),
+	.REF_JITTER1    (0.01),
+	.STARTUP_WAIT   ("FALSE")
 ) PLLE2_ADV (
-	.CLKFBIN(litedramcore_pll_fb),
-	.CLKIN1(clkin),
-	.PWRDWN(power_down),
-	.RST(litedramcore_reset7),
-	.CLKFBOUT(litedramcore_pll_fb),
-	.CLKOUT0(clkout0),
-	.CLKOUT1(clkout1),
-	.CLKOUT2(clkout2),
-	.CLKOUT3(clkout3),
-	.LOCKED(locked)
+	// Inputs.
+	.CLKFBIN  (builder_pll_fb),
+	.CLKIN1   (main_clkin),
+	.PWRDWN   (main_power_down),
+	.RST      (builder_reset7),
+
+	// Outputs.
+	.CLKFBOUT (builder_pll_fb),
+	.CLKOUT0  (main_clkout0),
+	.CLKOUT1  (main_clkout1),
+	.CLKOUT2  (main_clkout2),
+	.CLKOUT3  (main_clkout3),
+	.LOCKED   (main_locked)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE (
-	.C(iodelay_clk),
-	.CE(1'd1),
-	.D(1'd0),
-	.PRE(xilinxasyncresetsynchronizerimpl0),
-	.Q(xilinxasyncresetsynchronizerimpl0_rst_meta)
+	// Inputs.
+	.C   (iodelay_clk),
+	.CE  (1'd1),
+	.D   (1'd0),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl0_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_1 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_1 (
-	.C(iodelay_clk),
-	.CE(1'd1),
-	.D(xilinxasyncresetsynchronizerimpl0_rst_meta),
-	.PRE(xilinxasyncresetsynchronizerimpl0),
-	.Q(iodelay_rst)
+	// Inputs.
+	.C   (iodelay_clk),
+	.CE  (1'd1),
+	.D   (builder_xilinxasyncresetsynchronizerimpl0_rst_meta),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset),
+
+	// Outputs.
+	.Q   (iodelay_rst)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_2 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_2 (
-	.C(sys_clk),
-	.CE(1'd1),
-	.D(1'd0),
-	.PRE(xilinxasyncresetsynchronizerimpl1),
-	.Q(xilinxasyncresetsynchronizerimpl1_rst_meta)
+	// Inputs.
+	.C   (sys_clk),
+	.CE  (1'd1),
+	.D   (1'd0),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl1_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_3 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_3 (
-	.C(sys_clk),
-	.CE(1'd1),
-	.D(xilinxasyncresetsynchronizerimpl1_rst_meta),
-	.PRE(xilinxasyncresetsynchronizerimpl1),
-	.Q(sys_rst)
+	// Inputs.
+	.C   (sys_clk),
+	.CE  (1'd1),
+	.D   (builder_xilinxasyncresetsynchronizerimpl1_rst_meta),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset),
+
+	// Outputs.
+	.Q   (sys_rst)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_4 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_4 (
-	.C(sys4x_clk),
-	.CE(1'd1),
-	.D(1'd0),
-	.PRE(xilinxasyncresetsynchronizerimpl2),
-	.Q(xilinxasyncresetsynchronizerimpl2_rst_meta)
+	// Inputs.
+	.C   (sys4x_clk),
+	.CE  (1'd1),
+	.D   (1'd0),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl2_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_5 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_5 (
-	.C(sys4x_clk),
-	.CE(1'd1),
-	.D(xilinxasyncresetsynchronizerimpl2_rst_meta),
-	.PRE(xilinxasyncresetsynchronizerimpl2),
-	.Q(xilinxasyncresetsynchronizerimpl2_expr)
+	// Inputs.
+	.C   (sys4x_clk),
+	.CE  (1'd1),
+	.D   (builder_xilinxasyncresetsynchronizerimpl2_rst_meta),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl2_expr)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_6 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_6 (
-	.C(sys4x_dqs_clk),
-	.CE(1'd1),
-	.D(1'd0),
-	.PRE(xilinxasyncresetsynchronizerimpl3),
-	.Q(xilinxasyncresetsynchronizerimpl3_rst_meta)
+	// Inputs.
+	.C   (sys4x_dqs_clk),
+	.CE  (1'd1),
+	.D   (1'd0),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl3_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_7 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_7 (
-	.C(sys4x_dqs_clk),
-	.CE(1'd1),
-	.D(xilinxasyncresetsynchronizerimpl3_rst_meta),
-	.PRE(xilinxasyncresetsynchronizerimpl3),
-	.Q(xilinxasyncresetsynchronizerimpl3_expr)
+	// Inputs.
+	.C   (sys4x_dqs_clk),
+	.CE  (1'd1),
+	.D   (builder_xilinxasyncresetsynchronizerimpl3_rst_meta),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl3_expr)
 );
 
 endmodule
 
 // -----------------------------------------------------------------------------
-//  Auto-Generated by LiteX on 2022-10-28 19:01:23.
+//  Auto-Generated by LiteX on 2024-04-01 10:12:09.
 //------------------------------------------------------------------------------
diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init
index 61e54f3..0573632 100644
--- a/litedram/generated/arty/litedram_core.init
+++ b/litedram/generated/arty/litedram_core.init
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diff --git a/litedram/generated/arty/litedram_core.v b/litedram/generated/arty/litedram_core.v
index ea758b2..21cfb28 100644
--- a/litedram/generated/arty/litedram_core.v
+++ b/litedram/generated/arty/litedram_core.v
@@ -8,10 +8,11 @@
 //
 // Filename   : litedram_core.v
 // Device     : 
-// LiteX sha1 : --------
-// Date       : 2022-10-28 19:01:18
+// LiteX sha1 : 87137c30
+// Date       : 2024-04-01 10:12:05
 //------------------------------------------------------------------------------
 
+`timescale 1ns / 1ps
 
 //------------------------------------------------------------------------------
 // Module
@@ -19,4868 +20,5285 @@
 
 module litedram_core (
     input  wire          clk,
-    input  wire          rst,
-    output wire          pll_locked,
     output wire   [13:0] ddram_a,
     output wire    [2:0] ddram_ba,
-    output wire          ddram_ras_n,
     output wire          ddram_cas_n,
-    output wire          ddram_we_n,
+    output wire          ddram_cke,
+    output wire          ddram_clk_n,
+    output wire          ddram_clk_p,
     output wire          ddram_cs_n,
     output wire    [1:0] ddram_dm,
     inout  wire   [15:0] ddram_dq,
-    inout  wire    [1:0] ddram_dqs_p,
     inout  wire    [1:0] ddram_dqs_n,
-    output wire          ddram_clk_p,
-    output wire          ddram_clk_n,
-    output wire          ddram_cke,
+    inout  wire    [1:0] ddram_dqs_p,
     output wire          ddram_odt,
+    output wire          ddram_ras_n,
     output wire          ddram_reset_n,
+    output wire          ddram_we_n,
     output wire          init_done,
     output wire          init_error,
-    input  wire   [29:0] wb_ctrl_adr,
-    input  wire   [31:0] wb_ctrl_dat_w,
-    output wire   [31:0] wb_ctrl_dat_r,
-    input  wire    [3:0] wb_ctrl_sel,
-    input  wire          wb_ctrl_cyc,
-    input  wire          wb_ctrl_stb,
-    output wire          wb_ctrl_ack,
-    input  wire          wb_ctrl_we,
-    input  wire    [2:0] wb_ctrl_cti,
-    input  wire    [1:0] wb_ctrl_bte,
-    output wire          wb_ctrl_err,
+    output wire          pll_locked,
+    input  wire          rst,
     output wire          user_clk,
-    output wire          user_rst,
-    input  wire          user_port_native_0_cmd_valid,
+    input  wire   [23:0] user_port_native_0_cmd_addr,
     output wire          user_port_native_0_cmd_ready,
+    input  wire          user_port_native_0_cmd_valid,
     input  wire          user_port_native_0_cmd_we,
-    input  wire   [23:0] user_port_native_0_cmd_addr,
-    input  wire          user_port_native_0_wdata_valid,
+    output wire  [127:0] user_port_native_0_rdata_data,
+    input  wire          user_port_native_0_rdata_ready,
+    output wire          user_port_native_0_rdata_valid,
+    input  wire  [127:0] user_port_native_0_wdata_data,
     output wire          user_port_native_0_wdata_ready,
+    input  wire          user_port_native_0_wdata_valid,
     input  wire   [15:0] user_port_native_0_wdata_we,
-    input  wire  [127:0] user_port_native_0_wdata_data,
-    output wire          user_port_native_0_rdata_valid,
-    input  wire          user_port_native_0_rdata_ready,
-    output wire  [127:0] user_port_native_0_rdata_data
+    output wire          user_rst,
+    output wire          wb_ctrl_ack,
+    input  wire   [29:0] wb_ctrl_adr,
+    input  wire    [1:0] wb_ctrl_bte,
+    input  wire    [2:0] wb_ctrl_cti,
+    input  wire          wb_ctrl_cyc,
+    output wire   [31:0] wb_ctrl_dat_r,
+    input  wire   [31:0] wb_ctrl_dat_w,
+    output wire          wb_ctrl_err,
+    input  wire    [3:0] wb_ctrl_sel,
+    input  wire          wb_ctrl_stb,
+    input  wire          wb_ctrl_we
 );
 
 
+//------------------------------------------------------------------------------
+// Hierarchy
+//------------------------------------------------------------------------------
+
+/*
+LiteDRAMCore
+└─── bus (SoCBusHandler)
+│    └─── _interconnect (InterconnectPointToPoint)
+└─── csr (SoCCSRHandler)
+└─── irq (SoCIRQHandler)
+└─── cpu (CPUNone)
+└─── crg (LiteDRAMS7DDRPHYCRG)
+│    └─── pll (S7PLL)
+│    │    └─── [BUFG]
+│    │    └─── [BUFG]
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [BUFG]
+│    │    └─── [BUFG]
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [PLLE2_ADV]
+│    └─── idelayctrl (S7IDELAYCTRL)
+│    │    └─── [IDELAYCTRL]
+└─── ddrphy (A7DDRPHY)
+│    └─── tappeddelayline_0* (TappedDelayLine)
+│    └─── dqspattern_0* (DQSPattern)
+│    └─── bitslip_0* (BitSlip)
+│    └─── bitslip_1* (BitSlip)
+│    └─── bitslip_2* (BitSlip)
+│    └─── bitslip_3* (BitSlip)
+│    └─── tappeddelayline_1* (TappedDelayLine)
+│    └─── bitslip_4* (BitSlip)
+│    └─── bitslip_5* (BitSlip)
+│    └─── bitslip_6* (BitSlip)
+│    └─── bitslip_7* (BitSlip)
+│    └─── bitslip_8* (BitSlip)
+│    └─── bitslip_9* (BitSlip)
+│    └─── bitslip_10* (BitSlip)
+│    └─── bitslip_11* (BitSlip)
+│    └─── bitslip_12* (BitSlip)
+│    └─── bitslip_13* (BitSlip)
+│    └─── bitslip_14* (BitSlip)
+│    └─── bitslip_15* (BitSlip)
+│    └─── bitslip_16* (BitSlip)
+│    └─── bitslip_17* (BitSlip)
+│    └─── bitslip_18* (BitSlip)
+│    └─── bitslip_19* (BitSlip)
+│    └─── bitslip_20* (BitSlip)
+│    └─── bitslip_21* (BitSlip)
+│    └─── bitslip_22* (BitSlip)
+│    └─── bitslip_23* (BitSlip)
+│    └─── bitslip_24* (BitSlip)
+│    └─── bitslip_25* (BitSlip)
+│    └─── bitslip_26* (BitSlip)
+│    └─── bitslip_27* (BitSlip)
+│    └─── bitslip_28* (BitSlip)
+│    └─── bitslip_29* (BitSlip)
+│    └─── bitslip_30* (BitSlip)
+│    └─── bitslip_31* (BitSlip)
+│    └─── bitslip_32* (BitSlip)
+│    └─── bitslip_33* (BitSlip)
+│    └─── bitslip_34* (BitSlip)
+│    └─── bitslip_35* (BitSlip)
+│    └─── tappeddelayline_2* (TappedDelayLine)
+│    └─── tappeddelayline_3* (TappedDelayLine)
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [ISERDESE2]
+│    └─── [IOBUFDS]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUFDS]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [IDELAYE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [OBUFDS]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+└─── sdram (LiteDRAMCore)
+│    └─── dfii (DFIInjector)
+│    │    └─── pi0 (PhaseInjector)
+│    │    └─── pi1 (PhaseInjector)
+│    │    └─── pi2 (PhaseInjector)
+│    │    └─── pi3 (PhaseInjector)
+│    └─── controller (LiteDRAMController)
+│    │    └─── refresher (Refresher)
+│    │    │    └─── timer (RefreshTimer)
+│    │    │    └─── postponer (RefreshPostponer)
+│    │    │    └─── sequencer (RefreshSequencer)
+│    │    │    │    └─── refreshexecuter_0* (RefreshExecuter)
+│    │    │    └─── zqcs_timer (RefreshTimer)
+│    │    │    └─── zqs_executer (ZQCSExecuter)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_0* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_1* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_2* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_3* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_4* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_5* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_6* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_7* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── multiplexer (Multiplexer)
+│    │    │    └─── choose_cmd (_CommandChooser)
+│    │    │    │    └─── roundrobin_0* (RoundRobin)
+│    │    │    └─── choose_req (_CommandChooser)
+│    │    │    │    └─── roundrobin_0* (RoundRobin)
+│    │    │    └─── _steerer_0* (_Steerer)
+│    │    │    └─── trrdcon (tXXDController)
+│    │    │    └─── tfawcon (tFAWController)
+│    │    │    └─── tccdcon (tXXDController)
+│    │    │    └─── twtrcon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    └─── crossbar (LiteDRAMCrossbar)
+│    │    └─── roundrobin_0* (RoundRobin)
+│    │    └─── roundrobin_1* (RoundRobin)
+│    │    └─── roundrobin_2* (RoundRobin)
+│    │    └─── roundrobin_3* (RoundRobin)
+│    │    └─── roundrobin_4* (RoundRobin)
+│    │    └─── roundrobin_5* (RoundRobin)
+│    │    └─── roundrobin_6* (RoundRobin)
+│    │    └─── roundrobin_7* (RoundRobin)
+└─── ddrctrl (LiteDRAMCoreControl)
+└─── csr_bridge (Wishbone2CSR)
+│    └─── fsm (FSM)
+└─── csr_bankarray (CSRBankArray)
+│    └─── csrbank_0* (CSRBank)
+│    │    └─── csrstorage_0* (CSRStorage)
+│    │    └─── csrstorage_1* (CSRStorage)
+│    └─── csrbank_1* (CSRBank)
+│    │    └─── csrstorage_0* (CSRStorage)
+│    │    └─── csrstorage_1* (CSRStorage)
+│    │    └─── csrstorage_2* (CSRStorage)
+│    │    └─── csrstorage_3* (CSRStorage)
+│    │    └─── csrstorage_4* (CSRStorage)
+│    │    └─── csrstorage_5* (CSRStorage)
+│    └─── csrbank_2* (CSRBank)
+│    │    └─── csrstorage_0* (CSRStorage)
+│    │    └─── csrstorage_1* (CSRStorage)
+│    │    └─── csrstorage_2* (CSRStorage)
+│    │    └─── csrstorage_3* (CSRStorage)
+│    │    └─── csrstorage_4* (CSRStorage)
+│    │    └─── csrstatus_0* (CSRStatus)
+│    │    └─── csrstorage_5* (CSRStorage)
+│    │    └─── csrstorage_6* (CSRStorage)
+│    │    └─── csrstorage_7* (CSRStorage)
+│    │    └─── csrstorage_8* (CSRStorage)
+│    │    └─── csrstatus_1* (CSRStatus)
+│    │    └─── csrstorage_9* (CSRStorage)
+│    │    └─── csrstorage_10* (CSRStorage)
+│    │    └─── csrstorage_11* (CSRStorage)
+│    │    └─── csrstorage_12* (CSRStorage)
+│    │    └─── csrstatus_2* (CSRStatus)
+│    │    └─── csrstorage_13* (CSRStorage)
+│    │    └─── csrstorage_14* (CSRStorage)
+│    │    └─── csrstorage_15* (CSRStorage)
+│    │    └─── csrstorage_16* (CSRStorage)
+│    │    └─── csrstatus_3* (CSRStatus)
+└─── csr_interconnect (InterconnectShared)
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+* : Generated name.
+[]: BlackBox.
+*/
+
 //------------------------------------------------------------------------------
 // Signals
 //------------------------------------------------------------------------------
 
-reg           rst_1 = 1'd0;
-wire          sys_clk;
-wire          sys_rst;
-wire          sys4x_clk;
-wire          sys4x_dqs_clk;
+wire   [13:0] builder_adr;
+reg     [3:0] builder_bankmachine0_next_state = 4'd0;
+reg     [3:0] builder_bankmachine0_state = 4'd0;
+reg     [3:0] builder_bankmachine1_next_state = 4'd0;
+reg     [3:0] builder_bankmachine1_state = 4'd0;
+reg     [3:0] builder_bankmachine2_next_state = 4'd0;
+reg     [3:0] builder_bankmachine2_state = 4'd0;
+reg     [3:0] builder_bankmachine3_next_state = 4'd0;
+reg     [3:0] builder_bankmachine3_state = 4'd0;
+reg     [3:0] builder_bankmachine4_next_state = 4'd0;
+reg     [3:0] builder_bankmachine4_state = 4'd0;
+reg     [3:0] builder_bankmachine5_next_state = 4'd0;
+reg     [3:0] builder_bankmachine5_state = 4'd0;
+reg     [3:0] builder_bankmachine6_next_state = 4'd0;
+reg     [3:0] builder_bankmachine6_state = 4'd0;
+reg     [3:0] builder_bankmachine7_next_state = 4'd0;
+reg     [3:0] builder_bankmachine7_state = 4'd0;
+wire          builder_csrbank0_init_done0_r;
+reg           builder_csrbank0_init_done0_re = 1'd0;
+wire          builder_csrbank0_init_done0_w;
+reg           builder_csrbank0_init_done0_we = 1'd0;
+wire          builder_csrbank0_init_error0_r;
+reg           builder_csrbank0_init_error0_re = 1'd0;
+wire          builder_csrbank0_init_error0_w;
+reg           builder_csrbank0_init_error0_we = 1'd0;
+wire          builder_csrbank0_sel;
+wire    [1:0] builder_csrbank1_dly_sel0_r;
+reg           builder_csrbank1_dly_sel0_re = 1'd0;
+wire    [1:0] builder_csrbank1_dly_sel0_w;
+reg           builder_csrbank1_dly_sel0_we = 1'd0;
+wire    [4:0] builder_csrbank1_half_sys8x_taps0_r;
+reg           builder_csrbank1_half_sys8x_taps0_re = 1'd0;
+wire    [4:0] builder_csrbank1_half_sys8x_taps0_w;
+reg           builder_csrbank1_half_sys8x_taps0_we = 1'd0;
+wire    [1:0] builder_csrbank1_rdphase0_r;
+reg           builder_csrbank1_rdphase0_re = 1'd0;
+wire    [1:0] builder_csrbank1_rdphase0_w;
+reg           builder_csrbank1_rdphase0_we = 1'd0;
+wire          builder_csrbank1_rst0_r;
+reg           builder_csrbank1_rst0_re = 1'd0;
+wire          builder_csrbank1_rst0_w;
+reg           builder_csrbank1_rst0_we = 1'd0;
+wire          builder_csrbank1_sel;
+wire          builder_csrbank1_wlevel_en0_r;
+reg           builder_csrbank1_wlevel_en0_re = 1'd0;
+wire          builder_csrbank1_wlevel_en0_w;
+reg           builder_csrbank1_wlevel_en0_we = 1'd0;
+wire    [1:0] builder_csrbank1_wrphase0_r;
+reg           builder_csrbank1_wrphase0_re = 1'd0;
+wire    [1:0] builder_csrbank1_wrphase0_w;
+reg           builder_csrbank1_wrphase0_we = 1'd0;
+wire    [3:0] builder_csrbank2_dfii_control0_r;
+reg           builder_csrbank2_dfii_control0_re = 1'd0;
+wire    [3:0] builder_csrbank2_dfii_control0_w;
+reg           builder_csrbank2_dfii_control0_we = 1'd0;
+wire   [13:0] builder_csrbank2_dfii_pi0_address0_r;
+reg           builder_csrbank2_dfii_pi0_address0_re = 1'd0;
+wire   [13:0] builder_csrbank2_dfii_pi0_address0_w;
+reg           builder_csrbank2_dfii_pi0_address0_we = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi0_baddress0_r;
+reg           builder_csrbank2_dfii_pi0_baddress0_re = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi0_baddress0_w;
+reg           builder_csrbank2_dfii_pi0_baddress0_we = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi0_command0_r;
+reg           builder_csrbank2_dfii_pi0_command0_re = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi0_command0_w;
+reg           builder_csrbank2_dfii_pi0_command0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi0_rddata_r;
+reg           builder_csrbank2_dfii_pi0_rddata_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi0_rddata_w;
+reg           builder_csrbank2_dfii_pi0_rddata_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi0_wrdata0_r;
+reg           builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi0_wrdata0_w;
+reg           builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0;
+wire   [13:0] builder_csrbank2_dfii_pi1_address0_r;
+reg           builder_csrbank2_dfii_pi1_address0_re = 1'd0;
+wire   [13:0] builder_csrbank2_dfii_pi1_address0_w;
+reg           builder_csrbank2_dfii_pi1_address0_we = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi1_baddress0_r;
+reg           builder_csrbank2_dfii_pi1_baddress0_re = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi1_baddress0_w;
+reg           builder_csrbank2_dfii_pi1_baddress0_we = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi1_command0_r;
+reg           builder_csrbank2_dfii_pi1_command0_re = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi1_command0_w;
+reg           builder_csrbank2_dfii_pi1_command0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi1_rddata_r;
+reg           builder_csrbank2_dfii_pi1_rddata_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi1_rddata_w;
+reg           builder_csrbank2_dfii_pi1_rddata_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi1_wrdata0_r;
+reg           builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi1_wrdata0_w;
+reg           builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0;
+wire   [13:0] builder_csrbank2_dfii_pi2_address0_r;
+reg           builder_csrbank2_dfii_pi2_address0_re = 1'd0;
+wire   [13:0] builder_csrbank2_dfii_pi2_address0_w;
+reg           builder_csrbank2_dfii_pi2_address0_we = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi2_baddress0_r;
+reg           builder_csrbank2_dfii_pi2_baddress0_re = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi2_baddress0_w;
+reg           builder_csrbank2_dfii_pi2_baddress0_we = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi2_command0_r;
+reg           builder_csrbank2_dfii_pi2_command0_re = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi2_command0_w;
+reg           builder_csrbank2_dfii_pi2_command0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi2_rddata_r;
+reg           builder_csrbank2_dfii_pi2_rddata_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi2_rddata_w;
+reg           builder_csrbank2_dfii_pi2_rddata_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi2_wrdata0_r;
+reg           builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi2_wrdata0_w;
+reg           builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0;
+wire   [13:0] builder_csrbank2_dfii_pi3_address0_r;
+reg           builder_csrbank2_dfii_pi3_address0_re = 1'd0;
+wire   [13:0] builder_csrbank2_dfii_pi3_address0_w;
+reg           builder_csrbank2_dfii_pi3_address0_we = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi3_baddress0_r;
+reg           builder_csrbank2_dfii_pi3_baddress0_re = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi3_baddress0_w;
+reg           builder_csrbank2_dfii_pi3_baddress0_we = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi3_command0_r;
+reg           builder_csrbank2_dfii_pi3_command0_re = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi3_command0_w;
+reg           builder_csrbank2_dfii_pi3_command0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi3_rddata_r;
+reg           builder_csrbank2_dfii_pi3_rddata_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi3_rddata_w;
+reg           builder_csrbank2_dfii_pi3_rddata_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi3_wrdata0_r;
+reg           builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi3_wrdata0_w;
+reg           builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0;
+wire          builder_csrbank2_sel;
+wire   [31:0] builder_dat_r;
+wire   [31:0] builder_dat_w;
+reg           builder_interface0_ack = 1'd0;
+wire   [29:0] builder_interface0_adr;
+wire   [13:0] builder_interface0_bank_bus_adr;
+reg    [31:0] builder_interface0_bank_bus_dat_r = 32'd0;
+wire   [31:0] builder_interface0_bank_bus_dat_w;
+wire          builder_interface0_bank_bus_we;
+wire    [1:0] builder_interface0_bte;
+wire    [2:0] builder_interface0_cti;
+wire          builder_interface0_cyc;
+reg    [31:0] builder_interface0_dat_r = 32'd0;
+wire   [31:0] builder_interface0_dat_w;
+reg           builder_interface0_err = 1'd0;
+wire    [3:0] builder_interface0_sel;
+wire          builder_interface0_stb;
+wire          builder_interface0_we;
+reg    [13:0] builder_interface1_adr = 14'd0;
+reg    [13:0] builder_interface1_adr_next_value1 = 14'd0;
+reg           builder_interface1_adr_next_value_ce1 = 1'd0;
+wire   [13:0] builder_interface1_bank_bus_adr;
+reg    [31:0] builder_interface1_bank_bus_dat_r = 32'd0;
+wire   [31:0] builder_interface1_bank_bus_dat_w;
+wire          builder_interface1_bank_bus_we;
+wire   [31:0] builder_interface1_dat_r;
+reg    [31:0] builder_interface1_dat_w = 32'd0;
+reg    [31:0] builder_interface1_dat_w_next_value0 = 32'd0;
+reg           builder_interface1_dat_w_next_value_ce0 = 1'd0;
+reg           builder_interface1_we = 1'd0;
+reg           builder_interface1_we_next_value2 = 1'd0;
+reg           builder_interface1_we_next_value_ce2 = 1'd0;
+wire   [13:0] builder_interface2_bank_bus_adr;
+reg    [31:0] builder_interface2_bank_bus_dat_r = 32'd0;
+wire   [31:0] builder_interface2_bank_bus_dat_w;
+wire          builder_interface2_bank_bus_we;
+reg           builder_locked0 = 1'd0;
+reg           builder_locked1 = 1'd0;
+reg           builder_locked2 = 1'd0;
+reg           builder_locked3 = 1'd0;
+reg           builder_locked4 = 1'd0;
+reg           builder_locked5 = 1'd0;
+reg           builder_locked6 = 1'd0;
+reg           builder_locked7 = 1'd0;
+reg     [3:0] builder_multiplexer_next_state = 4'd0;
+reg     [3:0] builder_multiplexer_state = 4'd0;
+reg           builder_new_master_rdata_valid0 = 1'd0;
+reg           builder_new_master_rdata_valid1 = 1'd0;
+reg           builder_new_master_rdata_valid2 = 1'd0;
+reg           builder_new_master_rdata_valid3 = 1'd0;
+reg           builder_new_master_rdata_valid4 = 1'd0;
+reg           builder_new_master_rdata_valid5 = 1'd0;
+reg           builder_new_master_rdata_valid6 = 1'd0;
+reg           builder_new_master_rdata_valid7 = 1'd0;
+reg           builder_new_master_rdata_valid8 = 1'd0;
+reg           builder_new_master_wdata_ready0 = 1'd0;
+reg           builder_new_master_wdata_ready1 = 1'd0;
+reg     [1:0] builder_next_state = 2'd0;
+wire          builder_pll_fb;
+reg     [1:0] builder_refresher_next_state = 2'd0;
+reg     [1:0] builder_refresher_state = 2'd0;
+wire          builder_reset0;
+wire          builder_reset1;
+wire          builder_reset2;
+wire          builder_reset3;
+wire          builder_reset4;
+wire          builder_reset5;
+wire          builder_reset6;
+wire          builder_reset7;
+reg           builder_rhs_self0 = 1'd0;
+reg    [13:0] builder_rhs_self1 = 14'd0;
+reg           builder_rhs_self10 = 1'd0;
+reg           builder_rhs_self11 = 1'd0;
+reg    [20:0] builder_rhs_self12 = 21'd0;
+reg           builder_rhs_self13 = 1'd0;
+reg           builder_rhs_self14 = 1'd0;
+reg    [20:0] builder_rhs_self15 = 21'd0;
+reg           builder_rhs_self16 = 1'd0;
+reg           builder_rhs_self17 = 1'd0;
+reg    [20:0] builder_rhs_self18 = 21'd0;
+reg           builder_rhs_self19 = 1'd0;
+reg     [2:0] builder_rhs_self2 = 3'd0;
+reg           builder_rhs_self20 = 1'd0;
+reg    [20:0] builder_rhs_self21 = 21'd0;
+reg           builder_rhs_self22 = 1'd0;
+reg           builder_rhs_self23 = 1'd0;
+reg    [20:0] builder_rhs_self24 = 21'd0;
+reg           builder_rhs_self25 = 1'd0;
+reg           builder_rhs_self26 = 1'd0;
+reg    [20:0] builder_rhs_self27 = 21'd0;
+reg           builder_rhs_self28 = 1'd0;
+reg           builder_rhs_self29 = 1'd0;
+reg           builder_rhs_self3 = 1'd0;
+reg    [20:0] builder_rhs_self30 = 21'd0;
+reg           builder_rhs_self31 = 1'd0;
+reg           builder_rhs_self32 = 1'd0;
+reg    [20:0] builder_rhs_self33 = 21'd0;
+reg           builder_rhs_self34 = 1'd0;
+reg           builder_rhs_self35 = 1'd0;
+reg           builder_rhs_self4 = 1'd0;
+reg           builder_rhs_self5 = 1'd0;
+reg           builder_rhs_self6 = 1'd0;
+reg    [13:0] builder_rhs_self7 = 14'd0;
+reg     [2:0] builder_rhs_self8 = 3'd0;
+reg           builder_rhs_self9 = 1'd0;
+wire          builder_roundrobin0_ce;
+wire          builder_roundrobin0_grant;
+wire          builder_roundrobin0_request;
+wire          builder_roundrobin1_ce;
+wire          builder_roundrobin1_grant;
+wire          builder_roundrobin1_request;
+wire          builder_roundrobin2_ce;
+wire          builder_roundrobin2_grant;
+wire          builder_roundrobin2_request;
+wire          builder_roundrobin3_ce;
+wire          builder_roundrobin3_grant;
+wire          builder_roundrobin3_request;
+wire          builder_roundrobin4_ce;
+wire          builder_roundrobin4_grant;
+wire          builder_roundrobin4_request;
+wire          builder_roundrobin5_ce;
+wire          builder_roundrobin5_grant;
+wire          builder_roundrobin5_request;
+wire          builder_roundrobin6_ce;
+wire          builder_roundrobin6_grant;
+wire          builder_roundrobin6_request;
+wire          builder_roundrobin7_ce;
+wire          builder_roundrobin7_grant;
+wire          builder_roundrobin7_request;
+reg     [2:0] builder_self0 = 3'd0;
+reg    [13:0] builder_self1 = 14'd0;
+reg           builder_self10 = 1'd0;
+reg           builder_self11 = 1'd0;
+reg           builder_self12 = 1'd0;
+reg           builder_self13 = 1'd0;
+reg     [2:0] builder_self14 = 3'd0;
+reg    [13:0] builder_self15 = 14'd0;
+reg           builder_self16 = 1'd0;
+reg           builder_self17 = 1'd0;
+reg           builder_self18 = 1'd0;
+reg           builder_self19 = 1'd0;
+reg           builder_self2 = 1'd0;
+reg           builder_self20 = 1'd0;
+reg     [2:0] builder_self21 = 3'd0;
+reg    [13:0] builder_self22 = 14'd0;
+reg           builder_self23 = 1'd0;
+reg           builder_self24 = 1'd0;
+reg           builder_self25 = 1'd0;
+reg           builder_self26 = 1'd0;
+reg           builder_self27 = 1'd0;
+reg           builder_self3 = 1'd0;
+reg           builder_self4 = 1'd0;
+reg           builder_self5 = 1'd0;
+reg           builder_self6 = 1'd0;
+reg     [2:0] builder_self7 = 3'd0;
+reg    [13:0] builder_self8 = 14'd0;
+reg           builder_self9 = 1'd0;
+reg     [1:0] builder_state = 2'd0;
+reg           builder_t_self0 = 1'd0;
+reg           builder_t_self1 = 1'd0;
+reg           builder_t_self2 = 1'd0;
+reg           builder_t_self3 = 1'd0;
+reg           builder_t_self4 = 1'd0;
+reg           builder_t_self5 = 1'd0;
+wire          builder_we;
+wire          builder_xilinxasyncresetsynchronizerimpl0_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl0_rst_meta;
+wire          builder_xilinxasyncresetsynchronizerimpl1_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl1_rst_meta;
+wire          builder_xilinxasyncresetsynchronizerimpl2_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl2_expr;
+wire          builder_xilinxasyncresetsynchronizerimpl2_rst_meta;
+wire          builder_xilinxasyncresetsynchronizerimpl3_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl3_expr;
+wire          builder_xilinxasyncresetsynchronizerimpl3_rst_meta;
 wire          iodelay_clk;
 wire          iodelay_rst;
-wire          reset;
-reg           power_down = 1'd0;
-wire          locked;
-wire          clkin;
-wire          clkout0;
-wire          clkout_buf0;
-wire          clkout1;
-wire          clkout_buf1;
-wire          clkout2;
-wire          clkout_buf2;
-wire          clkout3;
-wire          clkout_buf3;
-reg     [3:0] reset_counter = 4'd15;
-reg           ic_reset = 1'd1;
-reg           a7ddrphy_rst_storage = 1'd0;
-reg           a7ddrphy_rst_re = 1'd0;
-reg     [1:0] a7ddrphy_dly_sel_storage = 2'd0;
-reg           a7ddrphy_dly_sel_re = 1'd0;
-reg     [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8;
-reg           a7ddrphy_half_sys8x_taps_re = 1'd0;
-reg           a7ddrphy_wlevel_en_storage = 1'd0;
-reg           a7ddrphy_wlevel_en_re = 1'd0;
-reg           a7ddrphy_wlevel_strobe_re = 1'd0;
-wire          a7ddrphy_wlevel_strobe_r;
-reg           a7ddrphy_wlevel_strobe_we = 1'd0;
-reg           a7ddrphy_wlevel_strobe_w = 1'd0;
-reg           a7ddrphy_rdly_dq_rst_re = 1'd0;
-wire          a7ddrphy_rdly_dq_rst_r;
-reg           a7ddrphy_rdly_dq_rst_we = 1'd0;
-reg           a7ddrphy_rdly_dq_rst_w = 1'd0;
-reg           a7ddrphy_rdly_dq_inc_re = 1'd0;
-wire          a7ddrphy_rdly_dq_inc_r;
-reg           a7ddrphy_rdly_dq_inc_we = 1'd0;
-reg           a7ddrphy_rdly_dq_inc_w = 1'd0;
-reg           a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
-wire          a7ddrphy_rdly_dq_bitslip_rst_r;
-reg           a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
-reg           a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-reg           a7ddrphy_rdly_dq_bitslip_re = 1'd0;
-wire          a7ddrphy_rdly_dq_bitslip_r;
-reg           a7ddrphy_rdly_dq_bitslip_we = 1'd0;
-reg           a7ddrphy_rdly_dq_bitslip_w = 1'd0;
-reg           a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
-wire          a7ddrphy_wdly_dq_bitslip_rst_r;
-reg           a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
-reg           a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
-reg           a7ddrphy_wdly_dq_bitslip_re = 1'd0;
-wire          a7ddrphy_wdly_dq_bitslip_r;
-reg           a7ddrphy_wdly_dq_bitslip_we = 1'd0;
-reg           a7ddrphy_wdly_dq_bitslip_w = 1'd0;
-reg     [1:0] a7ddrphy_rdphase_storage = 2'd2;
-reg           a7ddrphy_rdphase_re = 1'd0;
-reg     [1:0] a7ddrphy_wrphase_storage = 2'd3;
-reg           a7ddrphy_wrphase_re = 1'd0;
-wire   [13:0] a7ddrphy_dfi_p0_address;
-wire    [2:0] a7ddrphy_dfi_p0_bank;
-wire          a7ddrphy_dfi_p0_cas_n;
-wire          a7ddrphy_dfi_p0_cs_n;
-wire          a7ddrphy_dfi_p0_ras_n;
-wire          a7ddrphy_dfi_p0_we_n;
-wire          a7ddrphy_dfi_p0_cke;
-wire          a7ddrphy_dfi_p0_odt;
-wire          a7ddrphy_dfi_p0_reset_n;
-wire          a7ddrphy_dfi_p0_act_n;
-wire   [31:0] a7ddrphy_dfi_p0_wrdata;
-wire          a7ddrphy_dfi_p0_wrdata_en;
-wire    [3:0] a7ddrphy_dfi_p0_wrdata_mask;
-wire          a7ddrphy_dfi_p0_rddata_en;
-reg    [31:0] a7ddrphy_dfi_p0_rddata = 32'd0;
-wire          a7ddrphy_dfi_p0_rddata_valid;
-wire   [13:0] a7ddrphy_dfi_p1_address;
-wire    [2:0] a7ddrphy_dfi_p1_bank;
-wire          a7ddrphy_dfi_p1_cas_n;
-wire          a7ddrphy_dfi_p1_cs_n;
-wire          a7ddrphy_dfi_p1_ras_n;
-wire          a7ddrphy_dfi_p1_we_n;
-wire          a7ddrphy_dfi_p1_cke;
-wire          a7ddrphy_dfi_p1_odt;
-wire          a7ddrphy_dfi_p1_reset_n;
-wire          a7ddrphy_dfi_p1_act_n;
-wire   [31:0] a7ddrphy_dfi_p1_wrdata;
-wire          a7ddrphy_dfi_p1_wrdata_en;
-wire    [3:0] a7ddrphy_dfi_p1_wrdata_mask;
-wire          a7ddrphy_dfi_p1_rddata_en;
-reg    [31:0] a7ddrphy_dfi_p1_rddata = 32'd0;
-wire          a7ddrphy_dfi_p1_rddata_valid;
-wire   [13:0] a7ddrphy_dfi_p2_address;
-wire    [2:0] a7ddrphy_dfi_p2_bank;
-wire          a7ddrphy_dfi_p2_cas_n;
-wire          a7ddrphy_dfi_p2_cs_n;
-wire          a7ddrphy_dfi_p2_ras_n;
-wire          a7ddrphy_dfi_p2_we_n;
-wire          a7ddrphy_dfi_p2_cke;
-wire          a7ddrphy_dfi_p2_odt;
-wire          a7ddrphy_dfi_p2_reset_n;
-wire          a7ddrphy_dfi_p2_act_n;
-wire   [31:0] a7ddrphy_dfi_p2_wrdata;
-wire          a7ddrphy_dfi_p2_wrdata_en;
-wire    [3:0] a7ddrphy_dfi_p2_wrdata_mask;
-wire          a7ddrphy_dfi_p2_rddata_en;
-reg    [31:0] a7ddrphy_dfi_p2_rddata = 32'd0;
-wire          a7ddrphy_dfi_p2_rddata_valid;
-wire   [13:0] a7ddrphy_dfi_p3_address;
-wire    [2:0] a7ddrphy_dfi_p3_bank;
-wire          a7ddrphy_dfi_p3_cas_n;
-wire          a7ddrphy_dfi_p3_cs_n;
-wire          a7ddrphy_dfi_p3_ras_n;
-wire          a7ddrphy_dfi_p3_we_n;
-wire          a7ddrphy_dfi_p3_cke;
-wire          a7ddrphy_dfi_p3_odt;
-wire          a7ddrphy_dfi_p3_reset_n;
-wire          a7ddrphy_dfi_p3_act_n;
-wire   [31:0] a7ddrphy_dfi_p3_wrdata;
-wire          a7ddrphy_dfi_p3_wrdata_en;
-wire    [3:0] a7ddrphy_dfi_p3_wrdata_mask;
-wire          a7ddrphy_dfi_p3_rddata_en;
-reg    [31:0] a7ddrphy_dfi_p3_rddata = 32'd0;
-wire          a7ddrphy_dfi_p3_rddata_valid;
-wire          a7ddrphy_sd_clk_se_nodelay;
-wire    [2:0] a7ddrphy_pads_ba;
-reg           a7ddrphy_dqs_oe = 1'd0;
-wire          a7ddrphy_dqs_preamble;
-wire          a7ddrphy_dqs_postamble;
-wire          a7ddrphy_dqs_oe_delay_tappeddelayline;
-reg           a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg           a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-reg           a7ddrphy_dqspattern0 = 1'd0;
-reg           a7ddrphy_dqspattern1 = 1'd0;
-reg     [7:0] a7ddrphy_dqspattern_o0 = 8'd0;
-reg     [7:0] a7ddrphy_dqspattern_o1 = 8'd0;
-wire          a7ddrphy_dqs_o_no_delay0;
-wire          a7ddrphy_dqs_t0;
-reg     [7:0] a7ddrphy_bitslip00 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip0_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip0_r0 = 16'd0;
-wire          a7ddrphy0;
-wire          a7ddrphy_dqs_o_no_delay1;
-wire          a7ddrphy_dqs_t1;
-reg     [7:0] a7ddrphy_bitslip10 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip1_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip1_r0 = 16'd0;
-wire          a7ddrphy1;
-reg     [7:0] a7ddrphy_bitslip01 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip0_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip0_r1 = 16'd0;
-reg     [7:0] a7ddrphy_bitslip11 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip1_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip1_r1 = 16'd0;
-wire          a7ddrphy_dq_oe;
-wire          a7ddrphy_dq_oe_delay_tappeddelayline;
-reg           a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg           a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-wire          a7ddrphy_dq_o_nodelay0;
-wire          a7ddrphy_dq_i_nodelay0;
-wire          a7ddrphy_dq_i_delayed0;
-wire          a7ddrphy_dq_t0;
-reg     [7:0] a7ddrphy_bitslip02 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip0_value2 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip0_r2 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip03;
-reg     [7:0] a7ddrphy_bitslip04 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip0_value3 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip0_r3 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay1;
-wire          a7ddrphy_dq_i_nodelay1;
-wire          a7ddrphy_dq_i_delayed1;
-wire          a7ddrphy_dq_t1;
-reg     [7:0] a7ddrphy_bitslip12 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip1_value2 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip1_r2 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip13;
-reg     [7:0] a7ddrphy_bitslip14 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip1_value3 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip1_r3 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay2;
-wire          a7ddrphy_dq_i_nodelay2;
-wire          a7ddrphy_dq_i_delayed2;
-wire          a7ddrphy_dq_t2;
-reg     [7:0] a7ddrphy_bitslip20 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip2_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip2_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip21;
-reg     [7:0] a7ddrphy_bitslip22 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip2_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip2_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay3;
-wire          a7ddrphy_dq_i_nodelay3;
-wire          a7ddrphy_dq_i_delayed3;
-wire          a7ddrphy_dq_t3;
-reg     [7:0] a7ddrphy_bitslip30 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip3_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip3_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip31;
-reg     [7:0] a7ddrphy_bitslip32 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip3_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip3_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay4;
-wire          a7ddrphy_dq_i_nodelay4;
-wire          a7ddrphy_dq_i_delayed4;
-wire          a7ddrphy_dq_t4;
-reg     [7:0] a7ddrphy_bitslip40 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip4_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip4_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip41;
-reg     [7:0] a7ddrphy_bitslip42 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip4_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip4_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay5;
-wire          a7ddrphy_dq_i_nodelay5;
-wire          a7ddrphy_dq_i_delayed5;
-wire          a7ddrphy_dq_t5;
-reg     [7:0] a7ddrphy_bitslip50 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip5_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip5_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip51;
-reg     [7:0] a7ddrphy_bitslip52 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip5_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip5_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay6;
-wire          a7ddrphy_dq_i_nodelay6;
-wire          a7ddrphy_dq_i_delayed6;
-wire          a7ddrphy_dq_t6;
-reg     [7:0] a7ddrphy_bitslip60 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip6_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip6_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip61;
-reg     [7:0] a7ddrphy_bitslip62 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip6_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip6_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay7;
-wire          a7ddrphy_dq_i_nodelay7;
-wire          a7ddrphy_dq_i_delayed7;
-wire          a7ddrphy_dq_t7;
-reg     [7:0] a7ddrphy_bitslip70 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip7_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip7_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip71;
-reg     [7:0] a7ddrphy_bitslip72 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip7_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip7_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay8;
-wire          a7ddrphy_dq_i_nodelay8;
-wire          a7ddrphy_dq_i_delayed8;
-wire          a7ddrphy_dq_t8;
-reg     [7:0] a7ddrphy_bitslip80 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip8_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip8_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip81;
-reg     [7:0] a7ddrphy_bitslip82 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip8_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip8_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay9;
-wire          a7ddrphy_dq_i_nodelay9;
-wire          a7ddrphy_dq_i_delayed9;
-wire          a7ddrphy_dq_t9;
-reg     [7:0] a7ddrphy_bitslip90 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip9_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip9_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip91;
-reg     [7:0] a7ddrphy_bitslip92 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip9_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip9_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay10;
-wire          a7ddrphy_dq_i_nodelay10;
-wire          a7ddrphy_dq_i_delayed10;
-wire          a7ddrphy_dq_t10;
-reg     [7:0] a7ddrphy_bitslip100 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip10_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip10_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip101;
-reg     [7:0] a7ddrphy_bitslip102 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip10_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip10_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay11;
-wire          a7ddrphy_dq_i_nodelay11;
-wire          a7ddrphy_dq_i_delayed11;
-wire          a7ddrphy_dq_t11;
-reg     [7:0] a7ddrphy_bitslip110 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip11_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip11_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip111;
-reg     [7:0] a7ddrphy_bitslip112 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip11_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip11_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay12;
-wire          a7ddrphy_dq_i_nodelay12;
-wire          a7ddrphy_dq_i_delayed12;
-wire          a7ddrphy_dq_t12;
-reg     [7:0] a7ddrphy_bitslip120 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip12_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip12_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip121;
-reg     [7:0] a7ddrphy_bitslip122 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip12_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip12_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay13;
-wire          a7ddrphy_dq_i_nodelay13;
-wire          a7ddrphy_dq_i_delayed13;
-wire          a7ddrphy_dq_t13;
-reg     [7:0] a7ddrphy_bitslip130 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip13_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip13_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip131;
-reg     [7:0] a7ddrphy_bitslip132 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip13_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip13_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay14;
-wire          a7ddrphy_dq_i_nodelay14;
-wire          a7ddrphy_dq_i_delayed14;
-wire          a7ddrphy_dq_t14;
-reg     [7:0] a7ddrphy_bitslip140 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip14_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip14_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip141;
-reg     [7:0] a7ddrphy_bitslip142 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip14_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip14_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay15;
-wire          a7ddrphy_dq_i_nodelay15;
-wire          a7ddrphy_dq_i_delayed15;
-wire          a7ddrphy_dq_t15;
-reg     [7:0] a7ddrphy_bitslip150 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip15_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip15_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip151;
-reg     [7:0] a7ddrphy_bitslip152 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip15_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip15_r1 = 16'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
-reg           a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
-reg           a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
-reg           a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
-wire   [13:0] litedramcore_slave_p0_address;
-wire    [2:0] litedramcore_slave_p0_bank;
-wire          litedramcore_slave_p0_cas_n;
-wire          litedramcore_slave_p0_cs_n;
-wire          litedramcore_slave_p0_ras_n;
-wire          litedramcore_slave_p0_we_n;
-wire          litedramcore_slave_p0_cke;
-wire          litedramcore_slave_p0_odt;
-wire          litedramcore_slave_p0_reset_n;
-wire          litedramcore_slave_p0_act_n;
-wire   [31:0] litedramcore_slave_p0_wrdata;
-wire          litedramcore_slave_p0_wrdata_en;
-wire    [3:0] litedramcore_slave_p0_wrdata_mask;
-wire          litedramcore_slave_p0_rddata_en;
-reg    [31:0] litedramcore_slave_p0_rddata = 32'd0;
-reg           litedramcore_slave_p0_rddata_valid = 1'd0;
-wire   [13:0] litedramcore_slave_p1_address;
-wire    [2:0] litedramcore_slave_p1_bank;
-wire          litedramcore_slave_p1_cas_n;
-wire          litedramcore_slave_p1_cs_n;
-wire          litedramcore_slave_p1_ras_n;
-wire          litedramcore_slave_p1_we_n;
-wire          litedramcore_slave_p1_cke;
-wire          litedramcore_slave_p1_odt;
-wire          litedramcore_slave_p1_reset_n;
-wire          litedramcore_slave_p1_act_n;
-wire   [31:0] litedramcore_slave_p1_wrdata;
-wire          litedramcore_slave_p1_wrdata_en;
-wire    [3:0] litedramcore_slave_p1_wrdata_mask;
-wire          litedramcore_slave_p1_rddata_en;
-reg    [31:0] litedramcore_slave_p1_rddata = 32'd0;
-reg           litedramcore_slave_p1_rddata_valid = 1'd0;
-wire   [13:0] litedramcore_slave_p2_address;
-wire    [2:0] litedramcore_slave_p2_bank;
-wire          litedramcore_slave_p2_cas_n;
-wire          litedramcore_slave_p2_cs_n;
-wire          litedramcore_slave_p2_ras_n;
-wire          litedramcore_slave_p2_we_n;
-wire          litedramcore_slave_p2_cke;
-wire          litedramcore_slave_p2_odt;
-wire          litedramcore_slave_p2_reset_n;
-wire          litedramcore_slave_p2_act_n;
-wire   [31:0] litedramcore_slave_p2_wrdata;
-wire          litedramcore_slave_p2_wrdata_en;
-wire    [3:0] litedramcore_slave_p2_wrdata_mask;
-wire          litedramcore_slave_p2_rddata_en;
-reg    [31:0] litedramcore_slave_p2_rddata = 32'd0;
-reg           litedramcore_slave_p2_rddata_valid = 1'd0;
-wire   [13:0] litedramcore_slave_p3_address;
-wire    [2:0] litedramcore_slave_p3_bank;
-wire          litedramcore_slave_p3_cas_n;
-wire          litedramcore_slave_p3_cs_n;
-wire          litedramcore_slave_p3_ras_n;
-wire          litedramcore_slave_p3_we_n;
-wire          litedramcore_slave_p3_cke;
-wire          litedramcore_slave_p3_odt;
-wire          litedramcore_slave_p3_reset_n;
-wire          litedramcore_slave_p3_act_n;
-wire   [31:0] litedramcore_slave_p3_wrdata;
-wire          litedramcore_slave_p3_wrdata_en;
-wire    [3:0] litedramcore_slave_p3_wrdata_mask;
-wire          litedramcore_slave_p3_rddata_en;
-reg    [31:0] litedramcore_slave_p3_rddata = 32'd0;
-reg           litedramcore_slave_p3_rddata_valid = 1'd0;
-reg    [13:0] litedramcore_master_p0_address = 14'd0;
-reg     [2:0] litedramcore_master_p0_bank = 3'd0;
-reg           litedramcore_master_p0_cas_n = 1'd1;
-reg           litedramcore_master_p0_cs_n = 1'd1;
-reg           litedramcore_master_p0_ras_n = 1'd1;
-reg           litedramcore_master_p0_we_n = 1'd1;
-reg           litedramcore_master_p0_cke = 1'd0;
-reg           litedramcore_master_p0_odt = 1'd0;
-reg           litedramcore_master_p0_reset_n = 1'd0;
-reg           litedramcore_master_p0_act_n = 1'd1;
-reg    [31:0] litedramcore_master_p0_wrdata = 32'd0;
-reg           litedramcore_master_p0_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_master_p0_wrdata_mask = 4'd0;
-reg           litedramcore_master_p0_rddata_en = 1'd0;
-wire   [31:0] litedramcore_master_p0_rddata;
-wire          litedramcore_master_p0_rddata_valid;
-reg    [13:0] litedramcore_master_p1_address = 14'd0;
-reg     [2:0] litedramcore_master_p1_bank = 3'd0;
-reg           litedramcore_master_p1_cas_n = 1'd1;
-reg           litedramcore_master_p1_cs_n = 1'd1;
-reg           litedramcore_master_p1_ras_n = 1'd1;
-reg           litedramcore_master_p1_we_n = 1'd1;
-reg           litedramcore_master_p1_cke = 1'd0;
-reg           litedramcore_master_p1_odt = 1'd0;
-reg           litedramcore_master_p1_reset_n = 1'd0;
-reg           litedramcore_master_p1_act_n = 1'd1;
-reg    [31:0] litedramcore_master_p1_wrdata = 32'd0;
-reg           litedramcore_master_p1_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_master_p1_wrdata_mask = 4'd0;
-reg           litedramcore_master_p1_rddata_en = 1'd0;
-wire   [31:0] litedramcore_master_p1_rddata;
-wire          litedramcore_master_p1_rddata_valid;
-reg    [13:0] litedramcore_master_p2_address = 14'd0;
-reg     [2:0] litedramcore_master_p2_bank = 3'd0;
-reg           litedramcore_master_p2_cas_n = 1'd1;
-reg           litedramcore_master_p2_cs_n = 1'd1;
-reg           litedramcore_master_p2_ras_n = 1'd1;
-reg           litedramcore_master_p2_we_n = 1'd1;
-reg           litedramcore_master_p2_cke = 1'd0;
-reg           litedramcore_master_p2_odt = 1'd0;
-reg           litedramcore_master_p2_reset_n = 1'd0;
-reg           litedramcore_master_p2_act_n = 1'd1;
-reg    [31:0] litedramcore_master_p2_wrdata = 32'd0;
-reg           litedramcore_master_p2_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_master_p2_wrdata_mask = 4'd0;
-reg           litedramcore_master_p2_rddata_en = 1'd0;
-wire   [31:0] litedramcore_master_p2_rddata;
-wire          litedramcore_master_p2_rddata_valid;
-reg    [13:0] litedramcore_master_p3_address = 14'd0;
-reg     [2:0] litedramcore_master_p3_bank = 3'd0;
-reg           litedramcore_master_p3_cas_n = 1'd1;
-reg           litedramcore_master_p3_cs_n = 1'd1;
-reg           litedramcore_master_p3_ras_n = 1'd1;
-reg           litedramcore_master_p3_we_n = 1'd1;
-reg           litedramcore_master_p3_cke = 1'd0;
-reg           litedramcore_master_p3_odt = 1'd0;
-reg           litedramcore_master_p3_reset_n = 1'd0;
-reg           litedramcore_master_p3_act_n = 1'd1;
-reg    [31:0] litedramcore_master_p3_wrdata = 32'd0;
-reg           litedramcore_master_p3_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_master_p3_wrdata_mask = 4'd0;
-reg           litedramcore_master_p3_rddata_en = 1'd0;
-wire   [31:0] litedramcore_master_p3_rddata;
-wire          litedramcore_master_p3_rddata_valid;
-wire   [13:0] litedramcore_csr_dfi_p0_address;
-wire    [2:0] litedramcore_csr_dfi_p0_bank;
-reg           litedramcore_csr_dfi_p0_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p0_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p0_ras_n = 1'd1;
-reg           litedramcore_csr_dfi_p0_we_n = 1'd1;
-wire          litedramcore_csr_dfi_p0_cke;
-wire          litedramcore_csr_dfi_p0_odt;
-wire          litedramcore_csr_dfi_p0_reset_n;
-reg           litedramcore_csr_dfi_p0_act_n = 1'd1;
-wire   [31:0] litedramcore_csr_dfi_p0_wrdata;
-wire          litedramcore_csr_dfi_p0_wrdata_en;
-wire    [3:0] litedramcore_csr_dfi_p0_wrdata_mask;
-wire          litedramcore_csr_dfi_p0_rddata_en;
-reg    [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0;
-reg           litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
-wire   [13:0] litedramcore_csr_dfi_p1_address;
-wire    [2:0] litedramcore_csr_dfi_p1_bank;
-reg           litedramcore_csr_dfi_p1_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p1_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p1_ras_n = 1'd1;
-reg           litedramcore_csr_dfi_p1_we_n = 1'd1;
-wire          litedramcore_csr_dfi_p1_cke;
-wire          litedramcore_csr_dfi_p1_odt;
-wire          litedramcore_csr_dfi_p1_reset_n;
-reg           litedramcore_csr_dfi_p1_act_n = 1'd1;
-wire   [31:0] litedramcore_csr_dfi_p1_wrdata;
-wire          litedramcore_csr_dfi_p1_wrdata_en;
-wire    [3:0] litedramcore_csr_dfi_p1_wrdata_mask;
-wire          litedramcore_csr_dfi_p1_rddata_en;
-reg    [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0;
-reg           litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
-wire   [13:0] litedramcore_csr_dfi_p2_address;
-wire    [2:0] litedramcore_csr_dfi_p2_bank;
-reg           litedramcore_csr_dfi_p2_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p2_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p2_ras_n = 1'd1;
-reg           litedramcore_csr_dfi_p2_we_n = 1'd1;
-wire          litedramcore_csr_dfi_p2_cke;
-wire          litedramcore_csr_dfi_p2_odt;
-wire          litedramcore_csr_dfi_p2_reset_n;
-reg           litedramcore_csr_dfi_p2_act_n = 1'd1;
-wire   [31:0] litedramcore_csr_dfi_p2_wrdata;
-wire          litedramcore_csr_dfi_p2_wrdata_en;
-wire    [3:0] litedramcore_csr_dfi_p2_wrdata_mask;
-wire          litedramcore_csr_dfi_p2_rddata_en;
-reg    [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0;
-reg           litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
-wire   [13:0] litedramcore_csr_dfi_p3_address;
-wire    [2:0] litedramcore_csr_dfi_p3_bank;
-reg           litedramcore_csr_dfi_p3_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p3_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p3_ras_n = 1'd1;
-reg           litedramcore_csr_dfi_p3_we_n = 1'd1;
-wire          litedramcore_csr_dfi_p3_cke;
-wire          litedramcore_csr_dfi_p3_odt;
-wire          litedramcore_csr_dfi_p3_reset_n;
-reg           litedramcore_csr_dfi_p3_act_n = 1'd1;
-wire   [31:0] litedramcore_csr_dfi_p3_wrdata;
-wire          litedramcore_csr_dfi_p3_wrdata_en;
-wire    [3:0] litedramcore_csr_dfi_p3_wrdata_mask;
-wire          litedramcore_csr_dfi_p3_rddata_en;
-reg    [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0;
-reg           litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
-reg    [13:0] litedramcore_ext_dfi_p0_address = 14'd0;
-reg     [2:0] litedramcore_ext_dfi_p0_bank = 3'd0;
-reg           litedramcore_ext_dfi_p0_cas_n = 1'd1;
-reg           litedramcore_ext_dfi_p0_cs_n = 1'd1;
-reg           litedramcore_ext_dfi_p0_ras_n = 1'd1;
-reg           litedramcore_ext_dfi_p0_we_n = 1'd1;
-reg           litedramcore_ext_dfi_p0_cke = 1'd0;
-reg           litedramcore_ext_dfi_p0_odt = 1'd0;
-reg           litedramcore_ext_dfi_p0_reset_n = 1'd0;
-reg           litedramcore_ext_dfi_p0_act_n = 1'd1;
-reg    [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0;
-reg           litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
-reg           litedramcore_ext_dfi_p0_rddata_en = 1'd0;
-reg    [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0;
-reg           litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
-reg    [13:0] litedramcore_ext_dfi_p1_address = 14'd0;
-reg     [2:0] litedramcore_ext_dfi_p1_bank = 3'd0;
-reg           litedramcore_ext_dfi_p1_cas_n = 1'd1;
-reg           litedramcore_ext_dfi_p1_cs_n = 1'd1;
-reg           litedramcore_ext_dfi_p1_ras_n = 1'd1;
-reg           litedramcore_ext_dfi_p1_we_n = 1'd1;
-reg           litedramcore_ext_dfi_p1_cke = 1'd0;
-reg           litedramcore_ext_dfi_p1_odt = 1'd0;
-reg           litedramcore_ext_dfi_p1_reset_n = 1'd0;
-reg           litedramcore_ext_dfi_p1_act_n = 1'd1;
-reg    [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0;
-reg           litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
-reg           litedramcore_ext_dfi_p1_rddata_en = 1'd0;
-reg    [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0;
-reg           litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
-reg    [13:0] litedramcore_ext_dfi_p2_address = 14'd0;
-reg     [2:0] litedramcore_ext_dfi_p2_bank = 3'd0;
-reg           litedramcore_ext_dfi_p2_cas_n = 1'd1;
-reg           litedramcore_ext_dfi_p2_cs_n = 1'd1;
-reg           litedramcore_ext_dfi_p2_ras_n = 1'd1;
-reg           litedramcore_ext_dfi_p2_we_n = 1'd1;
-reg           litedramcore_ext_dfi_p2_cke = 1'd0;
-reg           litedramcore_ext_dfi_p2_odt = 1'd0;
-reg           litedramcore_ext_dfi_p2_reset_n = 1'd0;
-reg           litedramcore_ext_dfi_p2_act_n = 1'd1;
-reg    [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0;
-reg           litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
-reg           litedramcore_ext_dfi_p2_rddata_en = 1'd0;
-reg    [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0;
-reg           litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
-reg    [13:0] litedramcore_ext_dfi_p3_address = 14'd0;
-reg     [2:0] litedramcore_ext_dfi_p3_bank = 3'd0;
-reg           litedramcore_ext_dfi_p3_cas_n = 1'd1;
-reg           litedramcore_ext_dfi_p3_cs_n = 1'd1;
-reg           litedramcore_ext_dfi_p3_ras_n = 1'd1;
-reg           litedramcore_ext_dfi_p3_we_n = 1'd1;
-reg           litedramcore_ext_dfi_p3_cke = 1'd0;
-reg           litedramcore_ext_dfi_p3_odt = 1'd0;
-reg           litedramcore_ext_dfi_p3_reset_n = 1'd0;
-reg           litedramcore_ext_dfi_p3_act_n = 1'd1;
-reg    [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0;
-reg           litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
-reg           litedramcore_ext_dfi_p3_rddata_en = 1'd0;
-reg    [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0;
-reg           litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
-reg           litedramcore_ext_dfi_sel = 1'd0;
-wire          litedramcore_sel;
-wire          litedramcore_cke;
-wire          litedramcore_odt;
-wire          litedramcore_reset_n;
-reg     [3:0] litedramcore_storage = 4'd1;
-reg           litedramcore_re = 1'd0;
-wire          litedramcore_phaseinjector0_csrfield_cs;
-wire          litedramcore_phaseinjector0_csrfield_we;
-wire          litedramcore_phaseinjector0_csrfield_cas;
-wire          litedramcore_phaseinjector0_csrfield_ras;
-wire          litedramcore_phaseinjector0_csrfield_wren;
-wire          litedramcore_phaseinjector0_csrfield_rden;
-reg     [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
-reg           litedramcore_phaseinjector0_command_re = 1'd0;
-reg           litedramcore_phaseinjector0_command_issue_re = 1'd0;
-wire          litedramcore_phaseinjector0_command_issue_r;
-reg           litedramcore_phaseinjector0_command_issue_we = 1'd0;
-reg           litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg    [13:0] litedramcore_phaseinjector0_address_storage = 14'd0;
-reg           litedramcore_phaseinjector0_address_re = 1'd0;
-reg     [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg           litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0;
-reg           litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0;
-wire          litedramcore_phaseinjector0_rddata_we;
-reg           litedramcore_phaseinjector0_rddata_re = 1'd0;
-wire          litedramcore_phaseinjector1_csrfield_cs;
-wire          litedramcore_phaseinjector1_csrfield_we;
-wire          litedramcore_phaseinjector1_csrfield_cas;
-wire          litedramcore_phaseinjector1_csrfield_ras;
-wire          litedramcore_phaseinjector1_csrfield_wren;
-wire          litedramcore_phaseinjector1_csrfield_rden;
-reg     [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
-reg           litedramcore_phaseinjector1_command_re = 1'd0;
-reg           litedramcore_phaseinjector1_command_issue_re = 1'd0;
-wire          litedramcore_phaseinjector1_command_issue_r;
-reg           litedramcore_phaseinjector1_command_issue_we = 1'd0;
-reg           litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg    [13:0] litedramcore_phaseinjector1_address_storage = 14'd0;
-reg           litedramcore_phaseinjector1_address_re = 1'd0;
-reg     [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg           litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0;
-reg           litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0;
-wire          litedramcore_phaseinjector1_rddata_we;
-reg           litedramcore_phaseinjector1_rddata_re = 1'd0;
-wire          litedramcore_phaseinjector2_csrfield_cs;
-wire          litedramcore_phaseinjector2_csrfield_we;
-wire          litedramcore_phaseinjector2_csrfield_cas;
-wire          litedramcore_phaseinjector2_csrfield_ras;
-wire          litedramcore_phaseinjector2_csrfield_wren;
-wire          litedramcore_phaseinjector2_csrfield_rden;
-reg     [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
-reg           litedramcore_phaseinjector2_command_re = 1'd0;
-reg           litedramcore_phaseinjector2_command_issue_re = 1'd0;
-wire          litedramcore_phaseinjector2_command_issue_r;
-reg           litedramcore_phaseinjector2_command_issue_we = 1'd0;
-reg           litedramcore_phaseinjector2_command_issue_w = 1'd0;
-reg    [13:0] litedramcore_phaseinjector2_address_storage = 14'd0;
-reg           litedramcore_phaseinjector2_address_re = 1'd0;
-reg     [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
-reg           litedramcore_phaseinjector2_baddress_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0;
-reg           litedramcore_phaseinjector2_wrdata_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0;
-wire          litedramcore_phaseinjector2_rddata_we;
-reg           litedramcore_phaseinjector2_rddata_re = 1'd0;
-wire          litedramcore_phaseinjector3_csrfield_cs;
-wire          litedramcore_phaseinjector3_csrfield_we;
-wire          litedramcore_phaseinjector3_csrfield_cas;
-wire          litedramcore_phaseinjector3_csrfield_ras;
-wire          litedramcore_phaseinjector3_csrfield_wren;
-wire          litedramcore_phaseinjector3_csrfield_rden;
-reg     [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
-reg           litedramcore_phaseinjector3_command_re = 1'd0;
-reg           litedramcore_phaseinjector3_command_issue_re = 1'd0;
-wire          litedramcore_phaseinjector3_command_issue_r;
-reg           litedramcore_phaseinjector3_command_issue_we = 1'd0;
-reg           litedramcore_phaseinjector3_command_issue_w = 1'd0;
-reg    [13:0] litedramcore_phaseinjector3_address_storage = 14'd0;
-reg           litedramcore_phaseinjector3_address_re = 1'd0;
-reg     [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
-reg           litedramcore_phaseinjector3_baddress_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0;
-reg           litedramcore_phaseinjector3_wrdata_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0;
-wire          litedramcore_phaseinjector3_rddata_we;
-reg           litedramcore_phaseinjector3_rddata_re = 1'd0;
-wire          litedramcore_interface_bank0_valid;
-wire          litedramcore_interface_bank0_ready;
-wire          litedramcore_interface_bank0_we;
-wire   [20:0] litedramcore_interface_bank0_addr;
-wire          litedramcore_interface_bank0_lock;
-wire          litedramcore_interface_bank0_wdata_ready;
-wire          litedramcore_interface_bank0_rdata_valid;
-wire          litedramcore_interface_bank1_valid;
-wire          litedramcore_interface_bank1_ready;
-wire          litedramcore_interface_bank1_we;
-wire   [20:0] litedramcore_interface_bank1_addr;
-wire          litedramcore_interface_bank1_lock;
-wire          litedramcore_interface_bank1_wdata_ready;
-wire          litedramcore_interface_bank1_rdata_valid;
-wire          litedramcore_interface_bank2_valid;
-wire          litedramcore_interface_bank2_ready;
-wire          litedramcore_interface_bank2_we;
-wire   [20:0] litedramcore_interface_bank2_addr;
-wire          litedramcore_interface_bank2_lock;
-wire          litedramcore_interface_bank2_wdata_ready;
-wire          litedramcore_interface_bank2_rdata_valid;
-wire          litedramcore_interface_bank3_valid;
-wire          litedramcore_interface_bank3_ready;
-wire          litedramcore_interface_bank3_we;
-wire   [20:0] litedramcore_interface_bank3_addr;
-wire          litedramcore_interface_bank3_lock;
-wire          litedramcore_interface_bank3_wdata_ready;
-wire          litedramcore_interface_bank3_rdata_valid;
-wire          litedramcore_interface_bank4_valid;
-wire          litedramcore_interface_bank4_ready;
-wire          litedramcore_interface_bank4_we;
-wire   [20:0] litedramcore_interface_bank4_addr;
-wire          litedramcore_interface_bank4_lock;
-wire          litedramcore_interface_bank4_wdata_ready;
-wire          litedramcore_interface_bank4_rdata_valid;
-wire          litedramcore_interface_bank5_valid;
-wire          litedramcore_interface_bank5_ready;
-wire          litedramcore_interface_bank5_we;
-wire   [20:0] litedramcore_interface_bank5_addr;
-wire          litedramcore_interface_bank5_lock;
-wire          litedramcore_interface_bank5_wdata_ready;
-wire          litedramcore_interface_bank5_rdata_valid;
-wire          litedramcore_interface_bank6_valid;
-wire          litedramcore_interface_bank6_ready;
-wire          litedramcore_interface_bank6_we;
-wire   [20:0] litedramcore_interface_bank6_addr;
-wire          litedramcore_interface_bank6_lock;
-wire          litedramcore_interface_bank6_wdata_ready;
-wire          litedramcore_interface_bank6_rdata_valid;
-wire          litedramcore_interface_bank7_valid;
-wire          litedramcore_interface_bank7_ready;
-wire          litedramcore_interface_bank7_we;
-wire   [20:0] litedramcore_interface_bank7_addr;
-wire          litedramcore_interface_bank7_lock;
-wire          litedramcore_interface_bank7_wdata_ready;
-wire          litedramcore_interface_bank7_rdata_valid;
-reg   [127:0] litedramcore_interface_wdata = 128'd0;
-reg    [15:0] litedramcore_interface_wdata_we = 16'd0;
-wire  [127:0] litedramcore_interface_rdata;
-reg    [13:0] litedramcore_dfi_p0_address = 14'd0;
-reg     [2:0] litedramcore_dfi_p0_bank = 3'd0;
-reg           litedramcore_dfi_p0_cas_n = 1'd1;
-reg           litedramcore_dfi_p0_cs_n = 1'd1;
-reg           litedramcore_dfi_p0_ras_n = 1'd1;
-reg           litedramcore_dfi_p0_we_n = 1'd1;
-wire          litedramcore_dfi_p0_cke;
-wire          litedramcore_dfi_p0_odt;
-wire          litedramcore_dfi_p0_reset_n;
-reg           litedramcore_dfi_p0_act_n = 1'd1;
-wire   [31:0] litedramcore_dfi_p0_wrdata;
-reg           litedramcore_dfi_p0_wrdata_en = 1'd0;
-wire    [3:0] litedramcore_dfi_p0_wrdata_mask;
-reg           litedramcore_dfi_p0_rddata_en = 1'd0;
-wire   [31:0] litedramcore_dfi_p0_rddata;
-wire          litedramcore_dfi_p0_rddata_valid;
-reg    [13:0] litedramcore_dfi_p1_address = 14'd0;
-reg     [2:0] litedramcore_dfi_p1_bank = 3'd0;
-reg           litedramcore_dfi_p1_cas_n = 1'd1;
-reg           litedramcore_dfi_p1_cs_n = 1'd1;
-reg           litedramcore_dfi_p1_ras_n = 1'd1;
-reg           litedramcore_dfi_p1_we_n = 1'd1;
-wire          litedramcore_dfi_p1_cke;
-wire          litedramcore_dfi_p1_odt;
-wire          litedramcore_dfi_p1_reset_n;
-reg           litedramcore_dfi_p1_act_n = 1'd1;
-wire   [31:0] litedramcore_dfi_p1_wrdata;
-reg           litedramcore_dfi_p1_wrdata_en = 1'd0;
-wire    [3:0] litedramcore_dfi_p1_wrdata_mask;
-reg           litedramcore_dfi_p1_rddata_en = 1'd0;
-wire   [31:0] litedramcore_dfi_p1_rddata;
-wire          litedramcore_dfi_p1_rddata_valid;
-reg    [13:0] litedramcore_dfi_p2_address = 14'd0;
-reg     [2:0] litedramcore_dfi_p2_bank = 3'd0;
-reg           litedramcore_dfi_p2_cas_n = 1'd1;
-reg           litedramcore_dfi_p2_cs_n = 1'd1;
-reg           litedramcore_dfi_p2_ras_n = 1'd1;
-reg           litedramcore_dfi_p2_we_n = 1'd1;
-wire          litedramcore_dfi_p2_cke;
-wire          litedramcore_dfi_p2_odt;
-wire          litedramcore_dfi_p2_reset_n;
-reg           litedramcore_dfi_p2_act_n = 1'd1;
-wire   [31:0] litedramcore_dfi_p2_wrdata;
-reg           litedramcore_dfi_p2_wrdata_en = 1'd0;
-wire    [3:0] litedramcore_dfi_p2_wrdata_mask;
-reg           litedramcore_dfi_p2_rddata_en = 1'd0;
-wire   [31:0] litedramcore_dfi_p2_rddata;
-wire          litedramcore_dfi_p2_rddata_valid;
-reg    [13:0] litedramcore_dfi_p3_address = 14'd0;
-reg     [2:0] litedramcore_dfi_p3_bank = 3'd0;
-reg           litedramcore_dfi_p3_cas_n = 1'd1;
-reg           litedramcore_dfi_p3_cs_n = 1'd1;
-reg           litedramcore_dfi_p3_ras_n = 1'd1;
-reg           litedramcore_dfi_p3_we_n = 1'd1;
-wire          litedramcore_dfi_p3_cke;
-wire          litedramcore_dfi_p3_odt;
-wire          litedramcore_dfi_p3_reset_n;
-reg           litedramcore_dfi_p3_act_n = 1'd1;
-wire   [31:0] litedramcore_dfi_p3_wrdata;
-reg           litedramcore_dfi_p3_wrdata_en = 1'd0;
-wire    [3:0] litedramcore_dfi_p3_wrdata_mask;
-reg           litedramcore_dfi_p3_rddata_en = 1'd0;
-wire   [31:0] litedramcore_dfi_p3_rddata;
-wire          litedramcore_dfi_p3_rddata_valid;
-reg           litedramcore_cmd_valid = 1'd0;
-reg           litedramcore_cmd_ready = 1'd0;
-reg           litedramcore_cmd_last = 1'd0;
-reg    [13:0] litedramcore_cmd_payload_a = 14'd0;
-reg     [2:0] litedramcore_cmd_payload_ba = 3'd0;
-reg           litedramcore_cmd_payload_cas = 1'd0;
-reg           litedramcore_cmd_payload_ras = 1'd0;
-reg           litedramcore_cmd_payload_we = 1'd0;
-reg           litedramcore_cmd_payload_is_read = 1'd0;
-reg           litedramcore_cmd_payload_is_write = 1'd0;
-wire          litedramcore_wants_refresh;
-wire          litedramcore_wants_zqcs;
-wire          litedramcore_timer_wait;
-wire          litedramcore_timer_done0;
-wire    [9:0] litedramcore_timer_count0;
-wire          litedramcore_timer_done1;
-reg     [9:0] litedramcore_timer_count1 = 10'd781;
-wire          litedramcore_postponer_req_i;
-reg           litedramcore_postponer_req_o = 1'd0;
-reg           litedramcore_postponer_count = 1'd0;
-reg           litedramcore_sequencer_start0 = 1'd0;
-wire          litedramcore_sequencer_done0;
-wire          litedramcore_sequencer_start1;
-reg           litedramcore_sequencer_done1 = 1'd0;
-reg     [5:0] litedramcore_sequencer_counter = 6'd0;
-reg           litedramcore_sequencer_count = 1'd0;
-wire          litedramcore_zqcs_timer_wait;
-wire          litedramcore_zqcs_timer_done0;
-wire   [26:0] litedramcore_zqcs_timer_count0;
-wire          litedramcore_zqcs_timer_done1;
-reg    [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
-reg           litedramcore_zqcs_executer_start = 1'd0;
-reg           litedramcore_zqcs_executer_done = 1'd0;
-reg     [4:0] litedramcore_zqcs_executer_counter = 5'd0;
-wire          litedramcore_bankmachine0_req_valid;
-wire          litedramcore_bankmachine0_req_ready;
-wire          litedramcore_bankmachine0_req_we;
-wire   [20:0] litedramcore_bankmachine0_req_addr;
-wire          litedramcore_bankmachine0_req_lock;
-reg           litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine0_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine0_refresh_req;
-reg           litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg    [13:0] litedramcore_bankmachine0_cmd_payload_a = 14'd0;
-wire    [2:0] litedramcore_bankmachine0_cmd_payload_ba;
-reg           litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine0_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine0_sink_valid;
-wire          litedramcore_bankmachine0_sink_ready;
-reg           litedramcore_bankmachine0_sink_first = 1'd0;
-reg           litedramcore_bankmachine0_sink_last = 1'd0;
-wire          litedramcore_bankmachine0_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine0_sink_payload_addr;
-wire          litedramcore_bankmachine0_source_valid;
-wire          litedramcore_bankmachine0_source_ready;
-wire          litedramcore_bankmachine0_source_first;
-wire          litedramcore_bankmachine0_source_last;
-wire          litedramcore_bankmachine0_source_payload_we;
-wire   [20:0] litedramcore_bankmachine0_source_payload_addr;
-wire          litedramcore_bankmachine0_syncfifo0_we;
-wire          litedramcore_bankmachine0_syncfifo0_writable;
-wire          litedramcore_bankmachine0_syncfifo0_re;
-wire          litedramcore_bankmachine0_syncfifo0_readable;
-wire   [23:0] litedramcore_bankmachine0_syncfifo0_din;
-wire   [23:0] litedramcore_bankmachine0_syncfifo0_dout;
-reg     [4:0] litedramcore_bankmachine0_level = 5'd0;
-reg           litedramcore_bankmachine0_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine0_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine0_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0;
-wire   [23:0] litedramcore_bankmachine0_wrport_dat_r;
-wire          litedramcore_bankmachine0_wrport_we;
-wire   [23:0] litedramcore_bankmachine0_wrport_dat_w;
-wire          litedramcore_bankmachine0_do_read;
-wire    [3:0] litedramcore_bankmachine0_rdport_adr;
-wire   [23:0] litedramcore_bankmachine0_rdport_dat_r;
-wire          litedramcore_bankmachine0_fifo_in_payload_we;
-wire   [20:0] litedramcore_bankmachine0_fifo_in_payload_addr;
-wire          litedramcore_bankmachine0_fifo_in_first;
-wire          litedramcore_bankmachine0_fifo_in_last;
-wire          litedramcore_bankmachine0_fifo_out_payload_we;
-wire   [20:0] litedramcore_bankmachine0_fifo_out_payload_addr;
-wire          litedramcore_bankmachine0_fifo_out_first;
-wire          litedramcore_bankmachine0_fifo_out_last;
-wire          litedramcore_bankmachine0_sink_sink_valid;
-wire          litedramcore_bankmachine0_sink_sink_ready;
-wire          litedramcore_bankmachine0_sink_sink_first;
-wire          litedramcore_bankmachine0_sink_sink_last;
-wire          litedramcore_bankmachine0_sink_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine0_sink_sink_payload_addr;
-wire          litedramcore_bankmachine0_source_source_valid;
-wire          litedramcore_bankmachine0_source_source_ready;
-wire          litedramcore_bankmachine0_source_source_first;
-wire          litedramcore_bankmachine0_source_source_last;
-wire          litedramcore_bankmachine0_source_source_payload_we;
-wire   [20:0] litedramcore_bankmachine0_source_source_payload_addr;
-wire          litedramcore_bankmachine0_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine0_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine0_pipe_valid_sink_first;
-wire          litedramcore_bankmachine0_pipe_valid_sink_last;
-wire          litedramcore_bankmachine0_pipe_valid_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine0_pipe_valid_source_ready;
-reg           litedramcore_bankmachine0_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine0_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0;
-reg    [20:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 21'd0;
-reg    [13:0] litedramcore_bankmachine0_row = 14'd0;
-reg           litedramcore_bankmachine0_row_opened = 1'd0;
-wire          litedramcore_bankmachine0_row_hit;
-reg           litedramcore_bankmachine0_row_open = 1'd0;
-reg           litedramcore_bankmachine0_row_close = 1'd0;
-reg           litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine0_twtpcon_valid;
+wire          main_a7ddrphy0;
+wire          main_a7ddrphy1;
+reg     [7:0] main_a7ddrphy_bitslip00 = 8'd0;
+reg     [7:0] main_a7ddrphy_bitslip01 = 8'd0;
+reg     [7:0] main_a7ddrphy_bitslip02 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip03;
+reg     [7:0] main_a7ddrphy_bitslip04 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip10 = 8'd0;
+reg     [7:0] main_a7ddrphy_bitslip100 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip101;
+reg     [7:0] main_a7ddrphy_bitslip102 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip11 = 8'd0;
+reg     [7:0] main_a7ddrphy_bitslip110 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip111;
+reg     [7:0] main_a7ddrphy_bitslip112 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip12 = 8'd0;
+reg     [7:0] main_a7ddrphy_bitslip120 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip121;
+reg     [7:0] main_a7ddrphy_bitslip122 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7;
+wire    [7:0] main_a7ddrphy_bitslip13;
+reg     [7:0] main_a7ddrphy_bitslip130 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip131;
+reg     [7:0] main_a7ddrphy_bitslip132 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip14 = 8'd0;
+reg     [7:0] main_a7ddrphy_bitslip140 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip141;
+reg     [7:0] main_a7ddrphy_bitslip142 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip150 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip151;
+reg     [7:0] main_a7ddrphy_bitslip152 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7;
+reg    [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip20 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip21;
+reg     [7:0] main_a7ddrphy_bitslip22 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip30 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip31;
+reg     [7:0] main_a7ddrphy_bitslip32 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip40 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip41;
+reg     [7:0] main_a7ddrphy_bitslip42 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip50 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip51;
+reg     [7:0] main_a7ddrphy_bitslip52 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip60 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip61;
+reg     [7:0] main_a7ddrphy_bitslip62 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip70 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip71;
+reg     [7:0] main_a7ddrphy_bitslip72 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip80 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip81;
+reg     [7:0] main_a7ddrphy_bitslip82 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip90 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip91;
+reg     [7:0] main_a7ddrphy_bitslip92 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7;
+wire          main_a7ddrphy_dfi_p0_act_n;
+wire   [13:0] main_a7ddrphy_dfi_p0_address;
+wire    [2:0] main_a7ddrphy_dfi_p0_bank;
+wire          main_a7ddrphy_dfi_p0_cas_n;
+wire          main_a7ddrphy_dfi_p0_cke;
+wire          main_a7ddrphy_dfi_p0_cs_n;
+wire          main_a7ddrphy_dfi_p0_odt;
+wire          main_a7ddrphy_dfi_p0_ras_n;
+reg    [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0;
+wire          main_a7ddrphy_dfi_p0_rddata_en;
+wire          main_a7ddrphy_dfi_p0_rddata_valid;
+wire          main_a7ddrphy_dfi_p0_reset_n;
+wire          main_a7ddrphy_dfi_p0_we_n;
+wire   [31:0] main_a7ddrphy_dfi_p0_wrdata;
+wire          main_a7ddrphy_dfi_p0_wrdata_en;
+wire    [3:0] main_a7ddrphy_dfi_p0_wrdata_mask;
+wire          main_a7ddrphy_dfi_p1_act_n;
+wire   [13:0] main_a7ddrphy_dfi_p1_address;
+wire    [2:0] main_a7ddrphy_dfi_p1_bank;
+wire          main_a7ddrphy_dfi_p1_cas_n;
+wire          main_a7ddrphy_dfi_p1_cke;
+wire          main_a7ddrphy_dfi_p1_cs_n;
+wire          main_a7ddrphy_dfi_p1_odt;
+wire          main_a7ddrphy_dfi_p1_ras_n;
+reg    [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0;
+wire          main_a7ddrphy_dfi_p1_rddata_en;
+wire          main_a7ddrphy_dfi_p1_rddata_valid;
+wire          main_a7ddrphy_dfi_p1_reset_n;
+wire          main_a7ddrphy_dfi_p1_we_n;
+wire   [31:0] main_a7ddrphy_dfi_p1_wrdata;
+wire          main_a7ddrphy_dfi_p1_wrdata_en;
+wire    [3:0] main_a7ddrphy_dfi_p1_wrdata_mask;
+wire          main_a7ddrphy_dfi_p2_act_n;
+wire   [13:0] main_a7ddrphy_dfi_p2_address;
+wire    [2:0] main_a7ddrphy_dfi_p2_bank;
+wire          main_a7ddrphy_dfi_p2_cas_n;
+wire          main_a7ddrphy_dfi_p2_cke;
+wire          main_a7ddrphy_dfi_p2_cs_n;
+wire          main_a7ddrphy_dfi_p2_odt;
+wire          main_a7ddrphy_dfi_p2_ras_n;
+reg    [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0;
+wire          main_a7ddrphy_dfi_p2_rddata_en;
+wire          main_a7ddrphy_dfi_p2_rddata_valid;
+wire          main_a7ddrphy_dfi_p2_reset_n;
+wire          main_a7ddrphy_dfi_p2_we_n;
+wire   [31:0] main_a7ddrphy_dfi_p2_wrdata;
+wire          main_a7ddrphy_dfi_p2_wrdata_en;
+wire    [3:0] main_a7ddrphy_dfi_p2_wrdata_mask;
+wire          main_a7ddrphy_dfi_p3_act_n;
+wire   [13:0] main_a7ddrphy_dfi_p3_address;
+wire    [2:0] main_a7ddrphy_dfi_p3_bank;
+wire          main_a7ddrphy_dfi_p3_cas_n;
+wire          main_a7ddrphy_dfi_p3_cke;
+wire          main_a7ddrphy_dfi_p3_cs_n;
+wire          main_a7ddrphy_dfi_p3_odt;
+wire          main_a7ddrphy_dfi_p3_ras_n;
+reg    [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0;
+wire          main_a7ddrphy_dfi_p3_rddata_en;
+wire          main_a7ddrphy_dfi_p3_rddata_valid;
+wire          main_a7ddrphy_dfi_p3_reset_n;
+wire          main_a7ddrphy_dfi_p3_we_n;
+wire   [31:0] main_a7ddrphy_dfi_p3_wrdata;
+wire          main_a7ddrphy_dfi_p3_wrdata_en;
+wire    [3:0] main_a7ddrphy_dfi_p3_wrdata_mask;
+reg           main_a7ddrphy_dly_sel_re = 1'd0;
+reg     [1:0] main_a7ddrphy_dly_sel_storage = 2'd0;
+wire          main_a7ddrphy_dq_i_delayed0;
+wire          main_a7ddrphy_dq_i_delayed1;
+wire          main_a7ddrphy_dq_i_delayed10;
+wire          main_a7ddrphy_dq_i_delayed11;
+wire          main_a7ddrphy_dq_i_delayed12;
+wire          main_a7ddrphy_dq_i_delayed13;
+wire          main_a7ddrphy_dq_i_delayed14;
+wire          main_a7ddrphy_dq_i_delayed15;
+wire          main_a7ddrphy_dq_i_delayed2;
+wire          main_a7ddrphy_dq_i_delayed3;
+wire          main_a7ddrphy_dq_i_delayed4;
+wire          main_a7ddrphy_dq_i_delayed5;
+wire          main_a7ddrphy_dq_i_delayed6;
+wire          main_a7ddrphy_dq_i_delayed7;
+wire          main_a7ddrphy_dq_i_delayed8;
+wire          main_a7ddrphy_dq_i_delayed9;
+wire          main_a7ddrphy_dq_i_nodelay0;
+wire          main_a7ddrphy_dq_i_nodelay1;
+wire          main_a7ddrphy_dq_i_nodelay10;
+wire          main_a7ddrphy_dq_i_nodelay11;
+wire          main_a7ddrphy_dq_i_nodelay12;
+wire          main_a7ddrphy_dq_i_nodelay13;
+wire          main_a7ddrphy_dq_i_nodelay14;
+wire          main_a7ddrphy_dq_i_nodelay15;
+wire          main_a7ddrphy_dq_i_nodelay2;
+wire          main_a7ddrphy_dq_i_nodelay3;
+wire          main_a7ddrphy_dq_i_nodelay4;
+wire          main_a7ddrphy_dq_i_nodelay5;
+wire          main_a7ddrphy_dq_i_nodelay6;
+wire          main_a7ddrphy_dq_i_nodelay7;
+wire          main_a7ddrphy_dq_i_nodelay8;
+wire          main_a7ddrphy_dq_i_nodelay9;
+wire          main_a7ddrphy_dq_o_nodelay0;
+wire          main_a7ddrphy_dq_o_nodelay1;
+wire          main_a7ddrphy_dq_o_nodelay10;
+wire          main_a7ddrphy_dq_o_nodelay11;
+wire          main_a7ddrphy_dq_o_nodelay12;
+wire          main_a7ddrphy_dq_o_nodelay13;
+wire          main_a7ddrphy_dq_o_nodelay14;
+wire          main_a7ddrphy_dq_o_nodelay15;
+wire          main_a7ddrphy_dq_o_nodelay2;
+wire          main_a7ddrphy_dq_o_nodelay3;
+wire          main_a7ddrphy_dq_o_nodelay4;
+wire          main_a7ddrphy_dq_o_nodelay5;
+wire          main_a7ddrphy_dq_o_nodelay6;
+wire          main_a7ddrphy_dq_o_nodelay7;
+wire          main_a7ddrphy_dq_o_nodelay8;
+wire          main_a7ddrphy_dq_o_nodelay9;
+wire          main_a7ddrphy_dq_oe;
+wire          main_a7ddrphy_dq_oe_delay_tappeddelayline;
+reg           main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg           main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+wire          main_a7ddrphy_dq_t0;
+wire          main_a7ddrphy_dq_t1;
+wire          main_a7ddrphy_dq_t10;
+wire          main_a7ddrphy_dq_t11;
+wire          main_a7ddrphy_dq_t12;
+wire          main_a7ddrphy_dq_t13;
+wire          main_a7ddrphy_dq_t14;
+wire          main_a7ddrphy_dq_t15;
+wire          main_a7ddrphy_dq_t2;
+wire          main_a7ddrphy_dq_t3;
+wire          main_a7ddrphy_dq_t4;
+wire          main_a7ddrphy_dq_t5;
+wire          main_a7ddrphy_dq_t6;
+wire          main_a7ddrphy_dq_t7;
+wire          main_a7ddrphy_dq_t8;
+wire          main_a7ddrphy_dq_t9;
+wire          main_a7ddrphy_dqs_o_no_delay0;
+wire          main_a7ddrphy_dqs_o_no_delay1;
+reg           main_a7ddrphy_dqs_oe = 1'd0;
+wire          main_a7ddrphy_dqs_oe_delay_tappeddelayline;
+reg           main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg           main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+wire          main_a7ddrphy_dqs_postamble;
+wire          main_a7ddrphy_dqs_preamble;
+wire          main_a7ddrphy_dqs_t0;
+wire          main_a7ddrphy_dqs_t1;
+reg           main_a7ddrphy_dqspattern0 = 1'd0;
+reg           main_a7ddrphy_dqspattern1 = 1'd0;
+reg     [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0;
+reg     [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0;
+reg           main_a7ddrphy_half_sys8x_taps_re = 1'd0;
+reg     [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8;
+wire    [2:0] main_a7ddrphy_pads_ba;
+reg           main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
+wire          main_a7ddrphy_rdly_dq_bitslip_r;
+reg           main_a7ddrphy_rdly_dq_bitslip_re = 1'd0;
+wire          main_a7ddrphy_rdly_dq_bitslip_rst_r;
+reg           main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
+reg           main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+reg           main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
+reg           main_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
+reg           main_a7ddrphy_rdly_dq_bitslip_we = 1'd0;
+wire          main_a7ddrphy_rdly_dq_inc_r;
+reg           main_a7ddrphy_rdly_dq_inc_re = 1'd0;
+reg           main_a7ddrphy_rdly_dq_inc_w = 1'd0;
+reg           main_a7ddrphy_rdly_dq_inc_we = 1'd0;
+wire          main_a7ddrphy_rdly_dq_rst_r;
+reg           main_a7ddrphy_rdly_dq_rst_re = 1'd0;
+reg           main_a7ddrphy_rdly_dq_rst_w = 1'd0;
+reg           main_a7ddrphy_rdly_dq_rst_we = 1'd0;
+reg           main_a7ddrphy_rdphase_re = 1'd0;
+reg     [1:0] main_a7ddrphy_rdphase_storage = 2'd2;
+reg           main_a7ddrphy_rst_re = 1'd0;
+reg           main_a7ddrphy_rst_storage = 1'd0;
+wire          main_a7ddrphy_sd_clk_se_nodelay;
+wire          main_a7ddrphy_wdly_dq_bitslip_r;
+reg           main_a7ddrphy_wdly_dq_bitslip_re = 1'd0;
+wire          main_a7ddrphy_wdly_dq_bitslip_rst_r;
+reg           main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
+reg           main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
+reg           main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
+reg           main_a7ddrphy_wdly_dq_bitslip_w = 1'd0;
+reg           main_a7ddrphy_wdly_dq_bitslip_we = 1'd0;
+reg           main_a7ddrphy_wlevel_en_re = 1'd0;
+reg           main_a7ddrphy_wlevel_en_storage = 1'd0;
+wire          main_a7ddrphy_wlevel_strobe_r;
+reg           main_a7ddrphy_wlevel_strobe_re = 1'd0;
+reg           main_a7ddrphy_wlevel_strobe_w = 1'd0;
+reg           main_a7ddrphy_wlevel_strobe_we = 1'd0;
+reg           main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
+reg           main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
+reg           main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
+reg           main_a7ddrphy_wrphase_re = 1'd0;
+reg     [1:0] main_a7ddrphy_wrphase_storage = 2'd3;
+wire          main_clkin;
+wire          main_clkout0;
+wire          main_clkout1;
+wire          main_clkout2;
+wire          main_clkout3;
+wire          main_clkout_buf0;
+wire          main_clkout_buf1;
+wire          main_clkout_buf2;
+wire          main_clkout_buf3;
+reg           main_ic_reset = 1'd1;
+reg           main_init_done_re = 1'd0;
+reg           main_init_done_storage = 1'd0;
+reg           main_init_error_re = 1'd0;
+reg           main_init_error_storage = 1'd0;
+reg           main_litedramcore_bankmachine0_auto_precharge = 1'd0;
+reg    [13:0] main_litedramcore_bankmachine0_cmd_payload_a = 14'd0;
+wire    [2:0] main_litedramcore_bankmachine0_cmd_payload_ba;
+reg           main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine0_consume = 4'd0;
+wire          main_litedramcore_bankmachine0_do_read;
+wire          main_litedramcore_bankmachine0_fifo_in_first;
+wire          main_litedramcore_bankmachine0_fifo_in_last;
+wire   [20:0] main_litedramcore_bankmachine0_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine0_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine0_fifo_out_first;
+wire          main_litedramcore_bankmachine0_fifo_out_last;
+wire   [20:0] main_litedramcore_bankmachine0_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine0_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine0_level = 5'd0;
+wire          main_litedramcore_bankmachine0_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine0_pipe_valid_sink_last;
+wire   [20:0] main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine0_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine0_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine0_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine0_pipe_valid_source_last = 1'd0;
+reg    [20:0] main_litedramcore_bankmachine0_pipe_valid_source_payload_addr = 21'd0;
+reg           main_litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine0_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine0_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine0_rdport_adr;
+wire   [23:0] main_litedramcore_bankmachine0_rdport_dat_r;
+reg           main_litedramcore_bankmachine0_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine0_refresh_req;
+reg           main_litedramcore_bankmachine0_replace = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine0_req_addr;
+wire          main_litedramcore_bankmachine0_req_lock;
+reg           main_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine0_req_ready;
+wire          main_litedramcore_bankmachine0_req_valid;
+reg           main_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine0_req_we;
+reg    [13:0] main_litedramcore_bankmachine0_row = 14'd0;
+reg           main_litedramcore_bankmachine0_row_close = 1'd0;
+reg           main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine0_row_hit;
+reg           main_litedramcore_bankmachine0_row_open = 1'd0;
+reg           main_litedramcore_bankmachine0_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine0_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine0_sink_last = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine0_sink_payload_addr;
+wire          main_litedramcore_bankmachine0_sink_payload_we;
+wire          main_litedramcore_bankmachine0_sink_ready;
+wire          main_litedramcore_bankmachine0_sink_sink_first;
+wire          main_litedramcore_bankmachine0_sink_sink_last;
+wire   [20:0] main_litedramcore_bankmachine0_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine0_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine0_sink_sink_ready;
+wire          main_litedramcore_bankmachine0_sink_sink_valid;
+wire          main_litedramcore_bankmachine0_sink_valid;
+wire          main_litedramcore_bankmachine0_source_first;
+wire          main_litedramcore_bankmachine0_source_last;
+wire   [20:0] main_litedramcore_bankmachine0_source_payload_addr;
+wire          main_litedramcore_bankmachine0_source_payload_we;
+wire          main_litedramcore_bankmachine0_source_ready;
+wire          main_litedramcore_bankmachine0_source_source_first;
+wire          main_litedramcore_bankmachine0_source_source_last;
+wire   [20:0] main_litedramcore_bankmachine0_source_source_payload_addr;
+wire          main_litedramcore_bankmachine0_source_source_payload_we;
+wire          main_litedramcore_bankmachine0_source_source_ready;
+wire          main_litedramcore_bankmachine0_source_source_valid;
+wire          main_litedramcore_bankmachine0_source_valid;
+wire   [23:0] main_litedramcore_bankmachine0_syncfifo0_din;
+wire   [23:0] main_litedramcore_bankmachine0_syncfifo0_dout;
+wire          main_litedramcore_bankmachine0_syncfifo0_re;
+wire          main_litedramcore_bankmachine0_syncfifo0_readable;
+wire          main_litedramcore_bankmachine0_syncfifo0_we;
+wire          main_litedramcore_bankmachine0_syncfifo0_writable;
+reg     [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine0_trccon_valid;
+reg           main_litedramcore_bankmachine0_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine0_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
-wire          litedramcore_bankmachine0_trascon_valid;
+reg           main_litedramcore_bankmachine0_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine0_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine0_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
-wire          litedramcore_bankmachine1_req_valid;
-wire          litedramcore_bankmachine1_req_ready;
-wire          litedramcore_bankmachine1_req_we;
-wire   [20:0] litedramcore_bankmachine1_req_addr;
-wire          litedramcore_bankmachine1_req_lock;
-reg           litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine1_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine1_refresh_req;
-reg           litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine1_cmd_ready = 1'd0;
-reg    [13:0] litedramcore_bankmachine1_cmd_payload_a = 14'd0;
-wire    [2:0] litedramcore_bankmachine1_cmd_payload_ba;
-reg           litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine1_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine1_sink_valid;
-wire          litedramcore_bankmachine1_sink_ready;
-reg           litedramcore_bankmachine1_sink_first = 1'd0;
-reg           litedramcore_bankmachine1_sink_last = 1'd0;
-wire          litedramcore_bankmachine1_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine1_sink_payload_addr;
-wire          litedramcore_bankmachine1_source_valid;
-wire          litedramcore_bankmachine1_source_ready;
-wire          litedramcore_bankmachine1_source_first;
-wire          litedramcore_bankmachine1_source_last;
-wire          litedramcore_bankmachine1_source_payload_we;
-wire   [20:0] litedramcore_bankmachine1_source_payload_addr;
-wire          litedramcore_bankmachine1_syncfifo1_we;
-wire          litedramcore_bankmachine1_syncfifo1_writable;
-wire          litedramcore_bankmachine1_syncfifo1_re;
-wire          litedramcore_bankmachine1_syncfifo1_readable;
-wire   [23:0] litedramcore_bankmachine1_syncfifo1_din;
-wire   [23:0] litedramcore_bankmachine1_syncfifo1_dout;
-reg     [4:0] litedramcore_bankmachine1_level = 5'd0;
-reg           litedramcore_bankmachine1_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine1_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine1_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0;
-wire   [23:0] litedramcore_bankmachine1_wrport_dat_r;
-wire          litedramcore_bankmachine1_wrport_we;
-wire   [23:0] litedramcore_bankmachine1_wrport_dat_w;
-wire          litedramcore_bankmachine1_do_read;
-wire    [3:0] litedramcore_bankmachine1_rdport_adr;
-wire   [23:0] litedramcore_bankmachine1_rdport_dat_r;
-wire          litedramcore_bankmachine1_fifo_in_payload_we;
-wire   [20:0] litedramcore_bankmachine1_fifo_in_payload_addr;
-wire          litedramcore_bankmachine1_fifo_in_first;
-wire          litedramcore_bankmachine1_fifo_in_last;
-wire          litedramcore_bankmachine1_fifo_out_payload_we;
-wire   [20:0] litedramcore_bankmachine1_fifo_out_payload_addr;
-wire          litedramcore_bankmachine1_fifo_out_first;
-wire          litedramcore_bankmachine1_fifo_out_last;
-wire          litedramcore_bankmachine1_sink_sink_valid;
-wire          litedramcore_bankmachine1_sink_sink_ready;
-wire          litedramcore_bankmachine1_sink_sink_first;
-wire          litedramcore_bankmachine1_sink_sink_last;
-wire          litedramcore_bankmachine1_sink_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine1_sink_sink_payload_addr;
-wire          litedramcore_bankmachine1_source_source_valid;
-wire          litedramcore_bankmachine1_source_source_ready;
-wire          litedramcore_bankmachine1_source_source_first;
-wire          litedramcore_bankmachine1_source_source_last;
-wire          litedramcore_bankmachine1_source_source_payload_we;
-wire   [20:0] litedramcore_bankmachine1_source_source_payload_addr;
-wire          litedramcore_bankmachine1_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine1_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine1_pipe_valid_sink_first;
-wire          litedramcore_bankmachine1_pipe_valid_sink_last;
-wire          litedramcore_bankmachine1_pipe_valid_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine1_pipe_valid_source_ready;
-reg           litedramcore_bankmachine1_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine1_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0;
-reg    [20:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 21'd0;
-reg    [13:0] litedramcore_bankmachine1_row = 14'd0;
-reg           litedramcore_bankmachine1_row_opened = 1'd0;
-wire          litedramcore_bankmachine1_row_hit;
-reg           litedramcore_bankmachine1_row_open = 1'd0;
-reg           litedramcore_bankmachine1_row_close = 1'd0;
-reg           litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine1_twtpcon_valid;
+reg           main_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine0_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine0_wrport_adr = 4'd0;
+wire   [23:0] main_litedramcore_bankmachine0_wrport_dat_r;
+wire   [23:0] main_litedramcore_bankmachine0_wrport_dat_w;
+wire          main_litedramcore_bankmachine0_wrport_we;
+reg           main_litedramcore_bankmachine1_auto_precharge = 1'd0;
+reg    [13:0] main_litedramcore_bankmachine1_cmd_payload_a = 14'd0;
+wire    [2:0] main_litedramcore_bankmachine1_cmd_payload_ba;
+reg           main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine1_consume = 4'd0;
+wire          main_litedramcore_bankmachine1_do_read;
+wire          main_litedramcore_bankmachine1_fifo_in_first;
+wire          main_litedramcore_bankmachine1_fifo_in_last;
+wire   [20:0] main_litedramcore_bankmachine1_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine1_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine1_fifo_out_first;
+wire          main_litedramcore_bankmachine1_fifo_out_last;
+wire   [20:0] main_litedramcore_bankmachine1_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine1_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine1_level = 5'd0;
+wire          main_litedramcore_bankmachine1_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine1_pipe_valid_sink_last;
+wire   [20:0] main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine1_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine1_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine1_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine1_pipe_valid_source_last = 1'd0;
+reg    [20:0] main_litedramcore_bankmachine1_pipe_valid_source_payload_addr = 21'd0;
+reg           main_litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine1_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine1_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine1_rdport_adr;
+wire   [23:0] main_litedramcore_bankmachine1_rdport_dat_r;
+reg           main_litedramcore_bankmachine1_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine1_refresh_req;
+reg           main_litedramcore_bankmachine1_replace = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine1_req_addr;
+wire          main_litedramcore_bankmachine1_req_lock;
+reg           main_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine1_req_ready;
+wire          main_litedramcore_bankmachine1_req_valid;
+reg           main_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine1_req_we;
+reg    [13:0] main_litedramcore_bankmachine1_row = 14'd0;
+reg           main_litedramcore_bankmachine1_row_close = 1'd0;
+reg           main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine1_row_hit;
+reg           main_litedramcore_bankmachine1_row_open = 1'd0;
+reg           main_litedramcore_bankmachine1_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine1_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine1_sink_last = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine1_sink_payload_addr;
+wire          main_litedramcore_bankmachine1_sink_payload_we;
+wire          main_litedramcore_bankmachine1_sink_ready;
+wire          main_litedramcore_bankmachine1_sink_sink_first;
+wire          main_litedramcore_bankmachine1_sink_sink_last;
+wire   [20:0] main_litedramcore_bankmachine1_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine1_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine1_sink_sink_ready;
+wire          main_litedramcore_bankmachine1_sink_sink_valid;
+wire          main_litedramcore_bankmachine1_sink_valid;
+wire          main_litedramcore_bankmachine1_source_first;
+wire          main_litedramcore_bankmachine1_source_last;
+wire   [20:0] main_litedramcore_bankmachine1_source_payload_addr;
+wire          main_litedramcore_bankmachine1_source_payload_we;
+wire          main_litedramcore_bankmachine1_source_ready;
+wire          main_litedramcore_bankmachine1_source_source_first;
+wire          main_litedramcore_bankmachine1_source_source_last;
+wire   [20:0] main_litedramcore_bankmachine1_source_source_payload_addr;
+wire          main_litedramcore_bankmachine1_source_source_payload_we;
+wire          main_litedramcore_bankmachine1_source_source_ready;
+wire          main_litedramcore_bankmachine1_source_source_valid;
+wire          main_litedramcore_bankmachine1_source_valid;
+wire   [23:0] main_litedramcore_bankmachine1_syncfifo1_din;
+wire   [23:0] main_litedramcore_bankmachine1_syncfifo1_dout;
+wire          main_litedramcore_bankmachine1_syncfifo1_re;
+wire          main_litedramcore_bankmachine1_syncfifo1_readable;
+wire          main_litedramcore_bankmachine1_syncfifo1_we;
+wire          main_litedramcore_bankmachine1_syncfifo1_writable;
+reg     [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine1_trccon_valid;
+reg           main_litedramcore_bankmachine1_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine1_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
-wire          litedramcore_bankmachine1_trascon_valid;
+reg           main_litedramcore_bankmachine1_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine1_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine1_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
-wire          litedramcore_bankmachine2_req_valid;
-wire          litedramcore_bankmachine2_req_ready;
-wire          litedramcore_bankmachine2_req_we;
-wire   [20:0] litedramcore_bankmachine2_req_addr;
-wire          litedramcore_bankmachine2_req_lock;
-reg           litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine2_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine2_refresh_req;
-reg           litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine2_cmd_ready = 1'd0;
-reg    [13:0] litedramcore_bankmachine2_cmd_payload_a = 14'd0;
-wire    [2:0] litedramcore_bankmachine2_cmd_payload_ba;
-reg           litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine2_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine2_sink_valid;
-wire          litedramcore_bankmachine2_sink_ready;
-reg           litedramcore_bankmachine2_sink_first = 1'd0;
-reg           litedramcore_bankmachine2_sink_last = 1'd0;
-wire          litedramcore_bankmachine2_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine2_sink_payload_addr;
-wire          litedramcore_bankmachine2_source_valid;
-wire          litedramcore_bankmachine2_source_ready;
-wire          litedramcore_bankmachine2_source_first;
-wire          litedramcore_bankmachine2_source_last;
-wire          litedramcore_bankmachine2_source_payload_we;
-wire   [20:0] litedramcore_bankmachine2_source_payload_addr;
-wire          litedramcore_bankmachine2_syncfifo2_we;
-wire          litedramcore_bankmachine2_syncfifo2_writable;
-wire          litedramcore_bankmachine2_syncfifo2_re;
-wire          litedramcore_bankmachine2_syncfifo2_readable;
-wire   [23:0] litedramcore_bankmachine2_syncfifo2_din;
-wire   [23:0] litedramcore_bankmachine2_syncfifo2_dout;
-reg     [4:0] litedramcore_bankmachine2_level = 5'd0;
-reg           litedramcore_bankmachine2_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine2_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine2_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0;
-wire   [23:0] litedramcore_bankmachine2_wrport_dat_r;
-wire          litedramcore_bankmachine2_wrport_we;
-wire   [23:0] litedramcore_bankmachine2_wrport_dat_w;
-wire          litedramcore_bankmachine2_do_read;
-wire    [3:0] litedramcore_bankmachine2_rdport_adr;
-wire   [23:0] litedramcore_bankmachine2_rdport_dat_r;
-wire          litedramcore_bankmachine2_fifo_in_payload_we;
-wire   [20:0] litedramcore_bankmachine2_fifo_in_payload_addr;
-wire          litedramcore_bankmachine2_fifo_in_first;
-wire          litedramcore_bankmachine2_fifo_in_last;
-wire          litedramcore_bankmachine2_fifo_out_payload_we;
-wire   [20:0] litedramcore_bankmachine2_fifo_out_payload_addr;
-wire          litedramcore_bankmachine2_fifo_out_first;
-wire          litedramcore_bankmachine2_fifo_out_last;
-wire          litedramcore_bankmachine2_sink_sink_valid;
-wire          litedramcore_bankmachine2_sink_sink_ready;
-wire          litedramcore_bankmachine2_sink_sink_first;
-wire          litedramcore_bankmachine2_sink_sink_last;
-wire          litedramcore_bankmachine2_sink_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine2_sink_sink_payload_addr;
-wire          litedramcore_bankmachine2_source_source_valid;
-wire          litedramcore_bankmachine2_source_source_ready;
-wire          litedramcore_bankmachine2_source_source_first;
-wire          litedramcore_bankmachine2_source_source_last;
-wire          litedramcore_bankmachine2_source_source_payload_we;
-wire   [20:0] litedramcore_bankmachine2_source_source_payload_addr;
-wire          litedramcore_bankmachine2_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine2_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine2_pipe_valid_sink_first;
-wire          litedramcore_bankmachine2_pipe_valid_sink_last;
-wire          litedramcore_bankmachine2_pipe_valid_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine2_pipe_valid_source_ready;
-reg           litedramcore_bankmachine2_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine2_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0;
-reg    [20:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 21'd0;
-reg    [13:0] litedramcore_bankmachine2_row = 14'd0;
-reg           litedramcore_bankmachine2_row_opened = 1'd0;
-wire          litedramcore_bankmachine2_row_hit;
-reg           litedramcore_bankmachine2_row_open = 1'd0;
-reg           litedramcore_bankmachine2_row_close = 1'd0;
-reg           litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine2_twtpcon_valid;
+reg           main_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine1_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine1_wrport_adr = 4'd0;
+wire   [23:0] main_litedramcore_bankmachine1_wrport_dat_r;
+wire   [23:0] main_litedramcore_bankmachine1_wrport_dat_w;
+wire          main_litedramcore_bankmachine1_wrport_we;
+reg           main_litedramcore_bankmachine2_auto_precharge = 1'd0;
+reg    [13:0] main_litedramcore_bankmachine2_cmd_payload_a = 14'd0;
+wire    [2:0] main_litedramcore_bankmachine2_cmd_payload_ba;
+reg           main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine2_consume = 4'd0;
+wire          main_litedramcore_bankmachine2_do_read;
+wire          main_litedramcore_bankmachine2_fifo_in_first;
+wire          main_litedramcore_bankmachine2_fifo_in_last;
+wire   [20:0] main_litedramcore_bankmachine2_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine2_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine2_fifo_out_first;
+wire          main_litedramcore_bankmachine2_fifo_out_last;
+wire   [20:0] main_litedramcore_bankmachine2_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine2_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine2_level = 5'd0;
+wire          main_litedramcore_bankmachine2_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine2_pipe_valid_sink_last;
+wire   [20:0] main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine2_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine2_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine2_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine2_pipe_valid_source_last = 1'd0;
+reg    [20:0] main_litedramcore_bankmachine2_pipe_valid_source_payload_addr = 21'd0;
+reg           main_litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine2_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine2_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine2_rdport_adr;
+wire   [23:0] main_litedramcore_bankmachine2_rdport_dat_r;
+reg           main_litedramcore_bankmachine2_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine2_refresh_req;
+reg           main_litedramcore_bankmachine2_replace = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine2_req_addr;
+wire          main_litedramcore_bankmachine2_req_lock;
+reg           main_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine2_req_ready;
+wire          main_litedramcore_bankmachine2_req_valid;
+reg           main_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine2_req_we;
+reg    [13:0] main_litedramcore_bankmachine2_row = 14'd0;
+reg           main_litedramcore_bankmachine2_row_close = 1'd0;
+reg           main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine2_row_hit;
+reg           main_litedramcore_bankmachine2_row_open = 1'd0;
+reg           main_litedramcore_bankmachine2_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine2_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine2_sink_last = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine2_sink_payload_addr;
+wire          main_litedramcore_bankmachine2_sink_payload_we;
+wire          main_litedramcore_bankmachine2_sink_ready;
+wire          main_litedramcore_bankmachine2_sink_sink_first;
+wire          main_litedramcore_bankmachine2_sink_sink_last;
+wire   [20:0] main_litedramcore_bankmachine2_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine2_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine2_sink_sink_ready;
+wire          main_litedramcore_bankmachine2_sink_sink_valid;
+wire          main_litedramcore_bankmachine2_sink_valid;
+wire          main_litedramcore_bankmachine2_source_first;
+wire          main_litedramcore_bankmachine2_source_last;
+wire   [20:0] main_litedramcore_bankmachine2_source_payload_addr;
+wire          main_litedramcore_bankmachine2_source_payload_we;
+wire          main_litedramcore_bankmachine2_source_ready;
+wire          main_litedramcore_bankmachine2_source_source_first;
+wire          main_litedramcore_bankmachine2_source_source_last;
+wire   [20:0] main_litedramcore_bankmachine2_source_source_payload_addr;
+wire          main_litedramcore_bankmachine2_source_source_payload_we;
+wire          main_litedramcore_bankmachine2_source_source_ready;
+wire          main_litedramcore_bankmachine2_source_source_valid;
+wire          main_litedramcore_bankmachine2_source_valid;
+wire   [23:0] main_litedramcore_bankmachine2_syncfifo2_din;
+wire   [23:0] main_litedramcore_bankmachine2_syncfifo2_dout;
+wire          main_litedramcore_bankmachine2_syncfifo2_re;
+wire          main_litedramcore_bankmachine2_syncfifo2_readable;
+wire          main_litedramcore_bankmachine2_syncfifo2_we;
+wire          main_litedramcore_bankmachine2_syncfifo2_writable;
+reg     [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine2_trccon_valid;
+reg           main_litedramcore_bankmachine2_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine2_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
-wire          litedramcore_bankmachine2_trascon_valid;
+reg           main_litedramcore_bankmachine2_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine2_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine2_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
-wire          litedramcore_bankmachine3_req_valid;
-wire          litedramcore_bankmachine3_req_ready;
-wire          litedramcore_bankmachine3_req_we;
-wire   [20:0] litedramcore_bankmachine3_req_addr;
-wire          litedramcore_bankmachine3_req_lock;
-reg           litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine3_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine3_refresh_req;
-reg           litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine3_cmd_ready = 1'd0;
-reg    [13:0] litedramcore_bankmachine3_cmd_payload_a = 14'd0;
-wire    [2:0] litedramcore_bankmachine3_cmd_payload_ba;
-reg           litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine3_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine3_sink_valid;
-wire          litedramcore_bankmachine3_sink_ready;
-reg           litedramcore_bankmachine3_sink_first = 1'd0;
-reg           litedramcore_bankmachine3_sink_last = 1'd0;
-wire          litedramcore_bankmachine3_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine3_sink_payload_addr;
-wire          litedramcore_bankmachine3_source_valid;
-wire          litedramcore_bankmachine3_source_ready;
-wire          litedramcore_bankmachine3_source_first;
-wire          litedramcore_bankmachine3_source_last;
-wire          litedramcore_bankmachine3_source_payload_we;
-wire   [20:0] litedramcore_bankmachine3_source_payload_addr;
-wire          litedramcore_bankmachine3_syncfifo3_we;
-wire          litedramcore_bankmachine3_syncfifo3_writable;
-wire          litedramcore_bankmachine3_syncfifo3_re;
-wire          litedramcore_bankmachine3_syncfifo3_readable;
-wire   [23:0] litedramcore_bankmachine3_syncfifo3_din;
-wire   [23:0] litedramcore_bankmachine3_syncfifo3_dout;
-reg     [4:0] litedramcore_bankmachine3_level = 5'd0;
-reg           litedramcore_bankmachine3_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine3_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine3_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0;
-wire   [23:0] litedramcore_bankmachine3_wrport_dat_r;
-wire          litedramcore_bankmachine3_wrport_we;
-wire   [23:0] litedramcore_bankmachine3_wrport_dat_w;
-wire          litedramcore_bankmachine3_do_read;
-wire    [3:0] litedramcore_bankmachine3_rdport_adr;
-wire   [23:0] litedramcore_bankmachine3_rdport_dat_r;
-wire          litedramcore_bankmachine3_fifo_in_payload_we;
-wire   [20:0] litedramcore_bankmachine3_fifo_in_payload_addr;
-wire          litedramcore_bankmachine3_fifo_in_first;
-wire          litedramcore_bankmachine3_fifo_in_last;
-wire          litedramcore_bankmachine3_fifo_out_payload_we;
-wire   [20:0] litedramcore_bankmachine3_fifo_out_payload_addr;
-wire          litedramcore_bankmachine3_fifo_out_first;
-wire          litedramcore_bankmachine3_fifo_out_last;
-wire          litedramcore_bankmachine3_sink_sink_valid;
-wire          litedramcore_bankmachine3_sink_sink_ready;
-wire          litedramcore_bankmachine3_sink_sink_first;
-wire          litedramcore_bankmachine3_sink_sink_last;
-wire          litedramcore_bankmachine3_sink_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine3_sink_sink_payload_addr;
-wire          litedramcore_bankmachine3_source_source_valid;
-wire          litedramcore_bankmachine3_source_source_ready;
-wire          litedramcore_bankmachine3_source_source_first;
-wire          litedramcore_bankmachine3_source_source_last;
-wire          litedramcore_bankmachine3_source_source_payload_we;
-wire   [20:0] litedramcore_bankmachine3_source_source_payload_addr;
-wire          litedramcore_bankmachine3_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine3_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine3_pipe_valid_sink_first;
-wire          litedramcore_bankmachine3_pipe_valid_sink_last;
-wire          litedramcore_bankmachine3_pipe_valid_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine3_pipe_valid_source_ready;
-reg           litedramcore_bankmachine3_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine3_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0;
-reg    [20:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 21'd0;
-reg    [13:0] litedramcore_bankmachine3_row = 14'd0;
-reg           litedramcore_bankmachine3_row_opened = 1'd0;
-wire          litedramcore_bankmachine3_row_hit;
-reg           litedramcore_bankmachine3_row_open = 1'd0;
-reg           litedramcore_bankmachine3_row_close = 1'd0;
-reg           litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine3_twtpcon_valid;
+reg           main_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine2_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine2_wrport_adr = 4'd0;
+wire   [23:0] main_litedramcore_bankmachine2_wrport_dat_r;
+wire   [23:0] main_litedramcore_bankmachine2_wrport_dat_w;
+wire          main_litedramcore_bankmachine2_wrport_we;
+reg           main_litedramcore_bankmachine3_auto_precharge = 1'd0;
+reg    [13:0] main_litedramcore_bankmachine3_cmd_payload_a = 14'd0;
+wire    [2:0] main_litedramcore_bankmachine3_cmd_payload_ba;
+reg           main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine3_consume = 4'd0;
+wire          main_litedramcore_bankmachine3_do_read;
+wire          main_litedramcore_bankmachine3_fifo_in_first;
+wire          main_litedramcore_bankmachine3_fifo_in_last;
+wire   [20:0] main_litedramcore_bankmachine3_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine3_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine3_fifo_out_first;
+wire          main_litedramcore_bankmachine3_fifo_out_last;
+wire   [20:0] main_litedramcore_bankmachine3_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine3_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine3_level = 5'd0;
+wire          main_litedramcore_bankmachine3_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine3_pipe_valid_sink_last;
+wire   [20:0] main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine3_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine3_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine3_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine3_pipe_valid_source_last = 1'd0;
+reg    [20:0] main_litedramcore_bankmachine3_pipe_valid_source_payload_addr = 21'd0;
+reg           main_litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine3_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine3_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine3_rdport_adr;
+wire   [23:0] main_litedramcore_bankmachine3_rdport_dat_r;
+reg           main_litedramcore_bankmachine3_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine3_refresh_req;
+reg           main_litedramcore_bankmachine3_replace = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine3_req_addr;
+wire          main_litedramcore_bankmachine3_req_lock;
+reg           main_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine3_req_ready;
+wire          main_litedramcore_bankmachine3_req_valid;
+reg           main_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine3_req_we;
+reg    [13:0] main_litedramcore_bankmachine3_row = 14'd0;
+reg           main_litedramcore_bankmachine3_row_close = 1'd0;
+reg           main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine3_row_hit;
+reg           main_litedramcore_bankmachine3_row_open = 1'd0;
+reg           main_litedramcore_bankmachine3_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine3_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine3_sink_last = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine3_sink_payload_addr;
+wire          main_litedramcore_bankmachine3_sink_payload_we;
+wire          main_litedramcore_bankmachine3_sink_ready;
+wire          main_litedramcore_bankmachine3_sink_sink_first;
+wire          main_litedramcore_bankmachine3_sink_sink_last;
+wire   [20:0] main_litedramcore_bankmachine3_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine3_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine3_sink_sink_ready;
+wire          main_litedramcore_bankmachine3_sink_sink_valid;
+wire          main_litedramcore_bankmachine3_sink_valid;
+wire          main_litedramcore_bankmachine3_source_first;
+wire          main_litedramcore_bankmachine3_source_last;
+wire   [20:0] main_litedramcore_bankmachine3_source_payload_addr;
+wire          main_litedramcore_bankmachine3_source_payload_we;
+wire          main_litedramcore_bankmachine3_source_ready;
+wire          main_litedramcore_bankmachine3_source_source_first;
+wire          main_litedramcore_bankmachine3_source_source_last;
+wire   [20:0] main_litedramcore_bankmachine3_source_source_payload_addr;
+wire          main_litedramcore_bankmachine3_source_source_payload_we;
+wire          main_litedramcore_bankmachine3_source_source_ready;
+wire          main_litedramcore_bankmachine3_source_source_valid;
+wire          main_litedramcore_bankmachine3_source_valid;
+wire   [23:0] main_litedramcore_bankmachine3_syncfifo3_din;
+wire   [23:0] main_litedramcore_bankmachine3_syncfifo3_dout;
+wire          main_litedramcore_bankmachine3_syncfifo3_re;
+wire          main_litedramcore_bankmachine3_syncfifo3_readable;
+wire          main_litedramcore_bankmachine3_syncfifo3_we;
+wire          main_litedramcore_bankmachine3_syncfifo3_writable;
+reg     [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine3_trccon_valid;
+reg           main_litedramcore_bankmachine3_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine3_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
-wire          litedramcore_bankmachine3_trascon_valid;
+reg           main_litedramcore_bankmachine3_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine3_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine3_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
-wire          litedramcore_bankmachine4_req_valid;
-wire          litedramcore_bankmachine4_req_ready;
-wire          litedramcore_bankmachine4_req_we;
-wire   [20:0] litedramcore_bankmachine4_req_addr;
-wire          litedramcore_bankmachine4_req_lock;
-reg           litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine4_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine4_refresh_req;
-reg           litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine4_cmd_ready = 1'd0;
-reg    [13:0] litedramcore_bankmachine4_cmd_payload_a = 14'd0;
-wire    [2:0] litedramcore_bankmachine4_cmd_payload_ba;
-reg           litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine4_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine4_sink_valid;
-wire          litedramcore_bankmachine4_sink_ready;
-reg           litedramcore_bankmachine4_sink_first = 1'd0;
-reg           litedramcore_bankmachine4_sink_last = 1'd0;
-wire          litedramcore_bankmachine4_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine4_sink_payload_addr;
-wire          litedramcore_bankmachine4_source_valid;
-wire          litedramcore_bankmachine4_source_ready;
-wire          litedramcore_bankmachine4_source_first;
-wire          litedramcore_bankmachine4_source_last;
-wire          litedramcore_bankmachine4_source_payload_we;
-wire   [20:0] litedramcore_bankmachine4_source_payload_addr;
-wire          litedramcore_bankmachine4_syncfifo4_we;
-wire          litedramcore_bankmachine4_syncfifo4_writable;
-wire          litedramcore_bankmachine4_syncfifo4_re;
-wire          litedramcore_bankmachine4_syncfifo4_readable;
-wire   [23:0] litedramcore_bankmachine4_syncfifo4_din;
-wire   [23:0] litedramcore_bankmachine4_syncfifo4_dout;
-reg     [4:0] litedramcore_bankmachine4_level = 5'd0;
-reg           litedramcore_bankmachine4_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine4_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine4_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0;
-wire   [23:0] litedramcore_bankmachine4_wrport_dat_r;
-wire          litedramcore_bankmachine4_wrport_we;
-wire   [23:0] litedramcore_bankmachine4_wrport_dat_w;
-wire          litedramcore_bankmachine4_do_read;
-wire    [3:0] litedramcore_bankmachine4_rdport_adr;
-wire   [23:0] litedramcore_bankmachine4_rdport_dat_r;
-wire          litedramcore_bankmachine4_fifo_in_payload_we;
-wire   [20:0] litedramcore_bankmachine4_fifo_in_payload_addr;
-wire          litedramcore_bankmachine4_fifo_in_first;
-wire          litedramcore_bankmachine4_fifo_in_last;
-wire          litedramcore_bankmachine4_fifo_out_payload_we;
-wire   [20:0] litedramcore_bankmachine4_fifo_out_payload_addr;
-wire          litedramcore_bankmachine4_fifo_out_first;
-wire          litedramcore_bankmachine4_fifo_out_last;
-wire          litedramcore_bankmachine4_sink_sink_valid;
-wire          litedramcore_bankmachine4_sink_sink_ready;
-wire          litedramcore_bankmachine4_sink_sink_first;
-wire          litedramcore_bankmachine4_sink_sink_last;
-wire          litedramcore_bankmachine4_sink_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine4_sink_sink_payload_addr;
-wire          litedramcore_bankmachine4_source_source_valid;
-wire          litedramcore_bankmachine4_source_source_ready;
-wire          litedramcore_bankmachine4_source_source_first;
-wire          litedramcore_bankmachine4_source_source_last;
-wire          litedramcore_bankmachine4_source_source_payload_we;
-wire   [20:0] litedramcore_bankmachine4_source_source_payload_addr;
-wire          litedramcore_bankmachine4_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine4_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine4_pipe_valid_sink_first;
-wire          litedramcore_bankmachine4_pipe_valid_sink_last;
-wire          litedramcore_bankmachine4_pipe_valid_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine4_pipe_valid_source_ready;
-reg           litedramcore_bankmachine4_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine4_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0;
-reg    [20:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 21'd0;
-reg    [13:0] litedramcore_bankmachine4_row = 14'd0;
-reg           litedramcore_bankmachine4_row_opened = 1'd0;
-wire          litedramcore_bankmachine4_row_hit;
-reg           litedramcore_bankmachine4_row_open = 1'd0;
-reg           litedramcore_bankmachine4_row_close = 1'd0;
-reg           litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine4_twtpcon_valid;
+reg           main_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine3_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine3_wrport_adr = 4'd0;
+wire   [23:0] main_litedramcore_bankmachine3_wrport_dat_r;
+wire   [23:0] main_litedramcore_bankmachine3_wrport_dat_w;
+wire          main_litedramcore_bankmachine3_wrport_we;
+reg           main_litedramcore_bankmachine4_auto_precharge = 1'd0;
+reg    [13:0] main_litedramcore_bankmachine4_cmd_payload_a = 14'd0;
+wire    [2:0] main_litedramcore_bankmachine4_cmd_payload_ba;
+reg           main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine4_consume = 4'd0;
+wire          main_litedramcore_bankmachine4_do_read;
+wire          main_litedramcore_bankmachine4_fifo_in_first;
+wire          main_litedramcore_bankmachine4_fifo_in_last;
+wire   [20:0] main_litedramcore_bankmachine4_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine4_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine4_fifo_out_first;
+wire          main_litedramcore_bankmachine4_fifo_out_last;
+wire   [20:0] main_litedramcore_bankmachine4_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine4_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine4_level = 5'd0;
+wire          main_litedramcore_bankmachine4_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine4_pipe_valid_sink_last;
+wire   [20:0] main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine4_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine4_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine4_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine4_pipe_valid_source_last = 1'd0;
+reg    [20:0] main_litedramcore_bankmachine4_pipe_valid_source_payload_addr = 21'd0;
+reg           main_litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine4_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine4_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine4_rdport_adr;
+wire   [23:0] main_litedramcore_bankmachine4_rdport_dat_r;
+reg           main_litedramcore_bankmachine4_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine4_refresh_req;
+reg           main_litedramcore_bankmachine4_replace = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine4_req_addr;
+wire          main_litedramcore_bankmachine4_req_lock;
+reg           main_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine4_req_ready;
+wire          main_litedramcore_bankmachine4_req_valid;
+reg           main_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine4_req_we;
+reg    [13:0] main_litedramcore_bankmachine4_row = 14'd0;
+reg           main_litedramcore_bankmachine4_row_close = 1'd0;
+reg           main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine4_row_hit;
+reg           main_litedramcore_bankmachine4_row_open = 1'd0;
+reg           main_litedramcore_bankmachine4_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine4_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine4_sink_last = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine4_sink_payload_addr;
+wire          main_litedramcore_bankmachine4_sink_payload_we;
+wire          main_litedramcore_bankmachine4_sink_ready;
+wire          main_litedramcore_bankmachine4_sink_sink_first;
+wire          main_litedramcore_bankmachine4_sink_sink_last;
+wire   [20:0] main_litedramcore_bankmachine4_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine4_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine4_sink_sink_ready;
+wire          main_litedramcore_bankmachine4_sink_sink_valid;
+wire          main_litedramcore_bankmachine4_sink_valid;
+wire          main_litedramcore_bankmachine4_source_first;
+wire          main_litedramcore_bankmachine4_source_last;
+wire   [20:0] main_litedramcore_bankmachine4_source_payload_addr;
+wire          main_litedramcore_bankmachine4_source_payload_we;
+wire          main_litedramcore_bankmachine4_source_ready;
+wire          main_litedramcore_bankmachine4_source_source_first;
+wire          main_litedramcore_bankmachine4_source_source_last;
+wire   [20:0] main_litedramcore_bankmachine4_source_source_payload_addr;
+wire          main_litedramcore_bankmachine4_source_source_payload_we;
+wire          main_litedramcore_bankmachine4_source_source_ready;
+wire          main_litedramcore_bankmachine4_source_source_valid;
+wire          main_litedramcore_bankmachine4_source_valid;
+wire   [23:0] main_litedramcore_bankmachine4_syncfifo4_din;
+wire   [23:0] main_litedramcore_bankmachine4_syncfifo4_dout;
+wire          main_litedramcore_bankmachine4_syncfifo4_re;
+wire          main_litedramcore_bankmachine4_syncfifo4_readable;
+wire          main_litedramcore_bankmachine4_syncfifo4_we;
+wire          main_litedramcore_bankmachine4_syncfifo4_writable;
+reg     [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine4_trccon_valid;
+reg           main_litedramcore_bankmachine4_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine4_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
-wire          litedramcore_bankmachine4_trascon_valid;
+reg           main_litedramcore_bankmachine4_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine4_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine4_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
-wire          litedramcore_bankmachine5_req_valid;
-wire          litedramcore_bankmachine5_req_ready;
-wire          litedramcore_bankmachine5_req_we;
-wire   [20:0] litedramcore_bankmachine5_req_addr;
-wire          litedramcore_bankmachine5_req_lock;
-reg           litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine5_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine5_refresh_req;
-reg           litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine5_cmd_ready = 1'd0;
-reg    [13:0] litedramcore_bankmachine5_cmd_payload_a = 14'd0;
-wire    [2:0] litedramcore_bankmachine5_cmd_payload_ba;
-reg           litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine5_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine5_sink_valid;
-wire          litedramcore_bankmachine5_sink_ready;
-reg           litedramcore_bankmachine5_sink_first = 1'd0;
-reg           litedramcore_bankmachine5_sink_last = 1'd0;
-wire          litedramcore_bankmachine5_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine5_sink_payload_addr;
-wire          litedramcore_bankmachine5_source_valid;
-wire          litedramcore_bankmachine5_source_ready;
-wire          litedramcore_bankmachine5_source_first;
-wire          litedramcore_bankmachine5_source_last;
-wire          litedramcore_bankmachine5_source_payload_we;
-wire   [20:0] litedramcore_bankmachine5_source_payload_addr;
-wire          litedramcore_bankmachine5_syncfifo5_we;
-wire          litedramcore_bankmachine5_syncfifo5_writable;
-wire          litedramcore_bankmachine5_syncfifo5_re;
-wire          litedramcore_bankmachine5_syncfifo5_readable;
-wire   [23:0] litedramcore_bankmachine5_syncfifo5_din;
-wire   [23:0] litedramcore_bankmachine5_syncfifo5_dout;
-reg     [4:0] litedramcore_bankmachine5_level = 5'd0;
-reg           litedramcore_bankmachine5_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine5_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine5_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0;
-wire   [23:0] litedramcore_bankmachine5_wrport_dat_r;
-wire          litedramcore_bankmachine5_wrport_we;
-wire   [23:0] litedramcore_bankmachine5_wrport_dat_w;
-wire          litedramcore_bankmachine5_do_read;
-wire    [3:0] litedramcore_bankmachine5_rdport_adr;
-wire   [23:0] litedramcore_bankmachine5_rdport_dat_r;
-wire          litedramcore_bankmachine5_fifo_in_payload_we;
-wire   [20:0] litedramcore_bankmachine5_fifo_in_payload_addr;
-wire          litedramcore_bankmachine5_fifo_in_first;
-wire          litedramcore_bankmachine5_fifo_in_last;
-wire          litedramcore_bankmachine5_fifo_out_payload_we;
-wire   [20:0] litedramcore_bankmachine5_fifo_out_payload_addr;
-wire          litedramcore_bankmachine5_fifo_out_first;
-wire          litedramcore_bankmachine5_fifo_out_last;
-wire          litedramcore_bankmachine5_sink_sink_valid;
-wire          litedramcore_bankmachine5_sink_sink_ready;
-wire          litedramcore_bankmachine5_sink_sink_first;
-wire          litedramcore_bankmachine5_sink_sink_last;
-wire          litedramcore_bankmachine5_sink_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine5_sink_sink_payload_addr;
-wire          litedramcore_bankmachine5_source_source_valid;
-wire          litedramcore_bankmachine5_source_source_ready;
-wire          litedramcore_bankmachine5_source_source_first;
-wire          litedramcore_bankmachine5_source_source_last;
-wire          litedramcore_bankmachine5_source_source_payload_we;
-wire   [20:0] litedramcore_bankmachine5_source_source_payload_addr;
-wire          litedramcore_bankmachine5_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine5_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine5_pipe_valid_sink_first;
-wire          litedramcore_bankmachine5_pipe_valid_sink_last;
-wire          litedramcore_bankmachine5_pipe_valid_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine5_pipe_valid_source_ready;
-reg           litedramcore_bankmachine5_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine5_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0;
-reg    [20:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 21'd0;
-reg    [13:0] litedramcore_bankmachine5_row = 14'd0;
-reg           litedramcore_bankmachine5_row_opened = 1'd0;
-wire          litedramcore_bankmachine5_row_hit;
-reg           litedramcore_bankmachine5_row_open = 1'd0;
-reg           litedramcore_bankmachine5_row_close = 1'd0;
-reg           litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine5_twtpcon_valid;
+reg           main_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine4_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine4_wrport_adr = 4'd0;
+wire   [23:0] main_litedramcore_bankmachine4_wrport_dat_r;
+wire   [23:0] main_litedramcore_bankmachine4_wrport_dat_w;
+wire          main_litedramcore_bankmachine4_wrport_we;
+reg           main_litedramcore_bankmachine5_auto_precharge = 1'd0;
+reg    [13:0] main_litedramcore_bankmachine5_cmd_payload_a = 14'd0;
+wire    [2:0] main_litedramcore_bankmachine5_cmd_payload_ba;
+reg           main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine5_consume = 4'd0;
+wire          main_litedramcore_bankmachine5_do_read;
+wire          main_litedramcore_bankmachine5_fifo_in_first;
+wire          main_litedramcore_bankmachine5_fifo_in_last;
+wire   [20:0] main_litedramcore_bankmachine5_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine5_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine5_fifo_out_first;
+wire          main_litedramcore_bankmachine5_fifo_out_last;
+wire   [20:0] main_litedramcore_bankmachine5_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine5_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine5_level = 5'd0;
+wire          main_litedramcore_bankmachine5_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine5_pipe_valid_sink_last;
+wire   [20:0] main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine5_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine5_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine5_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine5_pipe_valid_source_last = 1'd0;
+reg    [20:0] main_litedramcore_bankmachine5_pipe_valid_source_payload_addr = 21'd0;
+reg           main_litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine5_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine5_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine5_rdport_adr;
+wire   [23:0] main_litedramcore_bankmachine5_rdport_dat_r;
+reg           main_litedramcore_bankmachine5_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine5_refresh_req;
+reg           main_litedramcore_bankmachine5_replace = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine5_req_addr;
+wire          main_litedramcore_bankmachine5_req_lock;
+reg           main_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine5_req_ready;
+wire          main_litedramcore_bankmachine5_req_valid;
+reg           main_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine5_req_we;
+reg    [13:0] main_litedramcore_bankmachine5_row = 14'd0;
+reg           main_litedramcore_bankmachine5_row_close = 1'd0;
+reg           main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine5_row_hit;
+reg           main_litedramcore_bankmachine5_row_open = 1'd0;
+reg           main_litedramcore_bankmachine5_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine5_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine5_sink_last = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine5_sink_payload_addr;
+wire          main_litedramcore_bankmachine5_sink_payload_we;
+wire          main_litedramcore_bankmachine5_sink_ready;
+wire          main_litedramcore_bankmachine5_sink_sink_first;
+wire          main_litedramcore_bankmachine5_sink_sink_last;
+wire   [20:0] main_litedramcore_bankmachine5_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine5_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine5_sink_sink_ready;
+wire          main_litedramcore_bankmachine5_sink_sink_valid;
+wire          main_litedramcore_bankmachine5_sink_valid;
+wire          main_litedramcore_bankmachine5_source_first;
+wire          main_litedramcore_bankmachine5_source_last;
+wire   [20:0] main_litedramcore_bankmachine5_source_payload_addr;
+wire          main_litedramcore_bankmachine5_source_payload_we;
+wire          main_litedramcore_bankmachine5_source_ready;
+wire          main_litedramcore_bankmachine5_source_source_first;
+wire          main_litedramcore_bankmachine5_source_source_last;
+wire   [20:0] main_litedramcore_bankmachine5_source_source_payload_addr;
+wire          main_litedramcore_bankmachine5_source_source_payload_we;
+wire          main_litedramcore_bankmachine5_source_source_ready;
+wire          main_litedramcore_bankmachine5_source_source_valid;
+wire          main_litedramcore_bankmachine5_source_valid;
+wire   [23:0] main_litedramcore_bankmachine5_syncfifo5_din;
+wire   [23:0] main_litedramcore_bankmachine5_syncfifo5_dout;
+wire          main_litedramcore_bankmachine5_syncfifo5_re;
+wire          main_litedramcore_bankmachine5_syncfifo5_readable;
+wire          main_litedramcore_bankmachine5_syncfifo5_we;
+wire          main_litedramcore_bankmachine5_syncfifo5_writable;
+reg     [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine5_trccon_valid;
+reg           main_litedramcore_bankmachine5_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine5_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
-wire          litedramcore_bankmachine5_trascon_valid;
+reg           main_litedramcore_bankmachine5_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine5_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine5_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
-wire          litedramcore_bankmachine6_req_valid;
-wire          litedramcore_bankmachine6_req_ready;
-wire          litedramcore_bankmachine6_req_we;
-wire   [20:0] litedramcore_bankmachine6_req_addr;
-wire          litedramcore_bankmachine6_req_lock;
-reg           litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine6_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine6_refresh_req;
-reg           litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine6_cmd_ready = 1'd0;
-reg    [13:0] litedramcore_bankmachine6_cmd_payload_a = 14'd0;
-wire    [2:0] litedramcore_bankmachine6_cmd_payload_ba;
-reg           litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine6_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine6_sink_valid;
-wire          litedramcore_bankmachine6_sink_ready;
-reg           litedramcore_bankmachine6_sink_first = 1'd0;
-reg           litedramcore_bankmachine6_sink_last = 1'd0;
-wire          litedramcore_bankmachine6_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine6_sink_payload_addr;
-wire          litedramcore_bankmachine6_source_valid;
-wire          litedramcore_bankmachine6_source_ready;
-wire          litedramcore_bankmachine6_source_first;
-wire          litedramcore_bankmachine6_source_last;
-wire          litedramcore_bankmachine6_source_payload_we;
-wire   [20:0] litedramcore_bankmachine6_source_payload_addr;
-wire          litedramcore_bankmachine6_syncfifo6_we;
-wire          litedramcore_bankmachine6_syncfifo6_writable;
-wire          litedramcore_bankmachine6_syncfifo6_re;
-wire          litedramcore_bankmachine6_syncfifo6_readable;
-wire   [23:0] litedramcore_bankmachine6_syncfifo6_din;
-wire   [23:0] litedramcore_bankmachine6_syncfifo6_dout;
-reg     [4:0] litedramcore_bankmachine6_level = 5'd0;
-reg           litedramcore_bankmachine6_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine6_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine6_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0;
-wire   [23:0] litedramcore_bankmachine6_wrport_dat_r;
-wire          litedramcore_bankmachine6_wrport_we;
-wire   [23:0] litedramcore_bankmachine6_wrport_dat_w;
-wire          litedramcore_bankmachine6_do_read;
-wire    [3:0] litedramcore_bankmachine6_rdport_adr;
-wire   [23:0] litedramcore_bankmachine6_rdport_dat_r;
-wire          litedramcore_bankmachine6_fifo_in_payload_we;
-wire   [20:0] litedramcore_bankmachine6_fifo_in_payload_addr;
-wire          litedramcore_bankmachine6_fifo_in_first;
-wire          litedramcore_bankmachine6_fifo_in_last;
-wire          litedramcore_bankmachine6_fifo_out_payload_we;
-wire   [20:0] litedramcore_bankmachine6_fifo_out_payload_addr;
-wire          litedramcore_bankmachine6_fifo_out_first;
-wire          litedramcore_bankmachine6_fifo_out_last;
-wire          litedramcore_bankmachine6_sink_sink_valid;
-wire          litedramcore_bankmachine6_sink_sink_ready;
-wire          litedramcore_bankmachine6_sink_sink_first;
-wire          litedramcore_bankmachine6_sink_sink_last;
-wire          litedramcore_bankmachine6_sink_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine6_sink_sink_payload_addr;
-wire          litedramcore_bankmachine6_source_source_valid;
-wire          litedramcore_bankmachine6_source_source_ready;
-wire          litedramcore_bankmachine6_source_source_first;
-wire          litedramcore_bankmachine6_source_source_last;
-wire          litedramcore_bankmachine6_source_source_payload_we;
-wire   [20:0] litedramcore_bankmachine6_source_source_payload_addr;
-wire          litedramcore_bankmachine6_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine6_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine6_pipe_valid_sink_first;
-wire          litedramcore_bankmachine6_pipe_valid_sink_last;
-wire          litedramcore_bankmachine6_pipe_valid_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine6_pipe_valid_source_ready;
-reg           litedramcore_bankmachine6_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine6_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0;
-reg    [20:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 21'd0;
-reg    [13:0] litedramcore_bankmachine6_row = 14'd0;
-reg           litedramcore_bankmachine6_row_opened = 1'd0;
-wire          litedramcore_bankmachine6_row_hit;
-reg           litedramcore_bankmachine6_row_open = 1'd0;
-reg           litedramcore_bankmachine6_row_close = 1'd0;
-reg           litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine6_twtpcon_valid;
+reg           main_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine5_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine5_wrport_adr = 4'd0;
+wire   [23:0] main_litedramcore_bankmachine5_wrport_dat_r;
+wire   [23:0] main_litedramcore_bankmachine5_wrport_dat_w;
+wire          main_litedramcore_bankmachine5_wrport_we;
+reg           main_litedramcore_bankmachine6_auto_precharge = 1'd0;
+reg    [13:0] main_litedramcore_bankmachine6_cmd_payload_a = 14'd0;
+wire    [2:0] main_litedramcore_bankmachine6_cmd_payload_ba;
+reg           main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine6_consume = 4'd0;
+wire          main_litedramcore_bankmachine6_do_read;
+wire          main_litedramcore_bankmachine6_fifo_in_first;
+wire          main_litedramcore_bankmachine6_fifo_in_last;
+wire   [20:0] main_litedramcore_bankmachine6_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine6_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine6_fifo_out_first;
+wire          main_litedramcore_bankmachine6_fifo_out_last;
+wire   [20:0] main_litedramcore_bankmachine6_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine6_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine6_level = 5'd0;
+wire          main_litedramcore_bankmachine6_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine6_pipe_valid_sink_last;
+wire   [20:0] main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine6_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine6_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine6_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine6_pipe_valid_source_last = 1'd0;
+reg    [20:0] main_litedramcore_bankmachine6_pipe_valid_source_payload_addr = 21'd0;
+reg           main_litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine6_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine6_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine6_rdport_adr;
+wire   [23:0] main_litedramcore_bankmachine6_rdport_dat_r;
+reg           main_litedramcore_bankmachine6_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine6_refresh_req;
+reg           main_litedramcore_bankmachine6_replace = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine6_req_addr;
+wire          main_litedramcore_bankmachine6_req_lock;
+reg           main_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine6_req_ready;
+wire          main_litedramcore_bankmachine6_req_valid;
+reg           main_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine6_req_we;
+reg    [13:0] main_litedramcore_bankmachine6_row = 14'd0;
+reg           main_litedramcore_bankmachine6_row_close = 1'd0;
+reg           main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine6_row_hit;
+reg           main_litedramcore_bankmachine6_row_open = 1'd0;
+reg           main_litedramcore_bankmachine6_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine6_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine6_sink_last = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine6_sink_payload_addr;
+wire          main_litedramcore_bankmachine6_sink_payload_we;
+wire          main_litedramcore_bankmachine6_sink_ready;
+wire          main_litedramcore_bankmachine6_sink_sink_first;
+wire          main_litedramcore_bankmachine6_sink_sink_last;
+wire   [20:0] main_litedramcore_bankmachine6_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine6_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine6_sink_sink_ready;
+wire          main_litedramcore_bankmachine6_sink_sink_valid;
+wire          main_litedramcore_bankmachine6_sink_valid;
+wire          main_litedramcore_bankmachine6_source_first;
+wire          main_litedramcore_bankmachine6_source_last;
+wire   [20:0] main_litedramcore_bankmachine6_source_payload_addr;
+wire          main_litedramcore_bankmachine6_source_payload_we;
+wire          main_litedramcore_bankmachine6_source_ready;
+wire          main_litedramcore_bankmachine6_source_source_first;
+wire          main_litedramcore_bankmachine6_source_source_last;
+wire   [20:0] main_litedramcore_bankmachine6_source_source_payload_addr;
+wire          main_litedramcore_bankmachine6_source_source_payload_we;
+wire          main_litedramcore_bankmachine6_source_source_ready;
+wire          main_litedramcore_bankmachine6_source_source_valid;
+wire          main_litedramcore_bankmachine6_source_valid;
+wire   [23:0] main_litedramcore_bankmachine6_syncfifo6_din;
+wire   [23:0] main_litedramcore_bankmachine6_syncfifo6_dout;
+wire          main_litedramcore_bankmachine6_syncfifo6_re;
+wire          main_litedramcore_bankmachine6_syncfifo6_readable;
+wire          main_litedramcore_bankmachine6_syncfifo6_we;
+wire          main_litedramcore_bankmachine6_syncfifo6_writable;
+reg     [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine6_trccon_valid;
+reg           main_litedramcore_bankmachine6_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine6_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
-wire          litedramcore_bankmachine6_trascon_valid;
+reg           main_litedramcore_bankmachine6_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine6_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine6_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
-wire          litedramcore_bankmachine7_req_valid;
-wire          litedramcore_bankmachine7_req_ready;
-wire          litedramcore_bankmachine7_req_we;
-wire   [20:0] litedramcore_bankmachine7_req_addr;
-wire          litedramcore_bankmachine7_req_lock;
-reg           litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine7_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine7_refresh_req;
-reg           litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine7_cmd_ready = 1'd0;
-reg    [13:0] litedramcore_bankmachine7_cmd_payload_a = 14'd0;
-wire    [2:0] litedramcore_bankmachine7_cmd_payload_ba;
-reg           litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine7_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine7_sink_valid;
-wire          litedramcore_bankmachine7_sink_ready;
-reg           litedramcore_bankmachine7_sink_first = 1'd0;
-reg           litedramcore_bankmachine7_sink_last = 1'd0;
-wire          litedramcore_bankmachine7_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine7_sink_payload_addr;
-wire          litedramcore_bankmachine7_source_valid;
-wire          litedramcore_bankmachine7_source_ready;
-wire          litedramcore_bankmachine7_source_first;
-wire          litedramcore_bankmachine7_source_last;
-wire          litedramcore_bankmachine7_source_payload_we;
-wire   [20:0] litedramcore_bankmachine7_source_payload_addr;
-wire          litedramcore_bankmachine7_syncfifo7_we;
-wire          litedramcore_bankmachine7_syncfifo7_writable;
-wire          litedramcore_bankmachine7_syncfifo7_re;
-wire          litedramcore_bankmachine7_syncfifo7_readable;
-wire   [23:0] litedramcore_bankmachine7_syncfifo7_din;
-wire   [23:0] litedramcore_bankmachine7_syncfifo7_dout;
-reg     [4:0] litedramcore_bankmachine7_level = 5'd0;
-reg           litedramcore_bankmachine7_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine7_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine7_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0;
-wire   [23:0] litedramcore_bankmachine7_wrport_dat_r;
-wire          litedramcore_bankmachine7_wrport_we;
-wire   [23:0] litedramcore_bankmachine7_wrport_dat_w;
-wire          litedramcore_bankmachine7_do_read;
-wire    [3:0] litedramcore_bankmachine7_rdport_adr;
-wire   [23:0] litedramcore_bankmachine7_rdport_dat_r;
-wire          litedramcore_bankmachine7_fifo_in_payload_we;
-wire   [20:0] litedramcore_bankmachine7_fifo_in_payload_addr;
-wire          litedramcore_bankmachine7_fifo_in_first;
-wire          litedramcore_bankmachine7_fifo_in_last;
-wire          litedramcore_bankmachine7_fifo_out_payload_we;
-wire   [20:0] litedramcore_bankmachine7_fifo_out_payload_addr;
-wire          litedramcore_bankmachine7_fifo_out_first;
-wire          litedramcore_bankmachine7_fifo_out_last;
-wire          litedramcore_bankmachine7_sink_sink_valid;
-wire          litedramcore_bankmachine7_sink_sink_ready;
-wire          litedramcore_bankmachine7_sink_sink_first;
-wire          litedramcore_bankmachine7_sink_sink_last;
-wire          litedramcore_bankmachine7_sink_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine7_sink_sink_payload_addr;
-wire          litedramcore_bankmachine7_source_source_valid;
-wire          litedramcore_bankmachine7_source_source_ready;
-wire          litedramcore_bankmachine7_source_source_first;
-wire          litedramcore_bankmachine7_source_source_last;
-wire          litedramcore_bankmachine7_source_source_payload_we;
-wire   [20:0] litedramcore_bankmachine7_source_source_payload_addr;
-wire          litedramcore_bankmachine7_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine7_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine7_pipe_valid_sink_first;
-wire          litedramcore_bankmachine7_pipe_valid_sink_last;
-wire          litedramcore_bankmachine7_pipe_valid_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine7_pipe_valid_source_ready;
-reg           litedramcore_bankmachine7_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine7_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0;
-reg    [20:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 21'd0;
-reg    [13:0] litedramcore_bankmachine7_row = 14'd0;
-reg           litedramcore_bankmachine7_row_opened = 1'd0;
-wire          litedramcore_bankmachine7_row_hit;
-reg           litedramcore_bankmachine7_row_open = 1'd0;
-reg           litedramcore_bankmachine7_row_close = 1'd0;
-reg           litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine7_twtpcon_valid;
+reg           main_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine6_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine6_wrport_adr = 4'd0;
+wire   [23:0] main_litedramcore_bankmachine6_wrport_dat_r;
+wire   [23:0] main_litedramcore_bankmachine6_wrport_dat_w;
+wire          main_litedramcore_bankmachine6_wrport_we;
+reg           main_litedramcore_bankmachine7_auto_precharge = 1'd0;
+reg    [13:0] main_litedramcore_bankmachine7_cmd_payload_a = 14'd0;
+wire    [2:0] main_litedramcore_bankmachine7_cmd_payload_ba;
+reg           main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine7_consume = 4'd0;
+wire          main_litedramcore_bankmachine7_do_read;
+wire          main_litedramcore_bankmachine7_fifo_in_first;
+wire          main_litedramcore_bankmachine7_fifo_in_last;
+wire   [20:0] main_litedramcore_bankmachine7_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine7_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine7_fifo_out_first;
+wire          main_litedramcore_bankmachine7_fifo_out_last;
+wire   [20:0] main_litedramcore_bankmachine7_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine7_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine7_level = 5'd0;
+wire          main_litedramcore_bankmachine7_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine7_pipe_valid_sink_last;
+wire   [20:0] main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine7_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine7_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine7_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine7_pipe_valid_source_last = 1'd0;
+reg    [20:0] main_litedramcore_bankmachine7_pipe_valid_source_payload_addr = 21'd0;
+reg           main_litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine7_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine7_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine7_rdport_adr;
+wire   [23:0] main_litedramcore_bankmachine7_rdport_dat_r;
+reg           main_litedramcore_bankmachine7_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine7_refresh_req;
+reg           main_litedramcore_bankmachine7_replace = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine7_req_addr;
+wire          main_litedramcore_bankmachine7_req_lock;
+reg           main_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine7_req_ready;
+wire          main_litedramcore_bankmachine7_req_valid;
+reg           main_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine7_req_we;
+reg    [13:0] main_litedramcore_bankmachine7_row = 14'd0;
+reg           main_litedramcore_bankmachine7_row_close = 1'd0;
+reg           main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine7_row_hit;
+reg           main_litedramcore_bankmachine7_row_open = 1'd0;
+reg           main_litedramcore_bankmachine7_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine7_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine7_sink_last = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine7_sink_payload_addr;
+wire          main_litedramcore_bankmachine7_sink_payload_we;
+wire          main_litedramcore_bankmachine7_sink_ready;
+wire          main_litedramcore_bankmachine7_sink_sink_first;
+wire          main_litedramcore_bankmachine7_sink_sink_last;
+wire   [20:0] main_litedramcore_bankmachine7_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine7_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine7_sink_sink_ready;
+wire          main_litedramcore_bankmachine7_sink_sink_valid;
+wire          main_litedramcore_bankmachine7_sink_valid;
+wire          main_litedramcore_bankmachine7_source_first;
+wire          main_litedramcore_bankmachine7_source_last;
+wire   [20:0] main_litedramcore_bankmachine7_source_payload_addr;
+wire          main_litedramcore_bankmachine7_source_payload_we;
+wire          main_litedramcore_bankmachine7_source_ready;
+wire          main_litedramcore_bankmachine7_source_source_first;
+wire          main_litedramcore_bankmachine7_source_source_last;
+wire   [20:0] main_litedramcore_bankmachine7_source_source_payload_addr;
+wire          main_litedramcore_bankmachine7_source_source_payload_we;
+wire          main_litedramcore_bankmachine7_source_source_ready;
+wire          main_litedramcore_bankmachine7_source_source_valid;
+wire          main_litedramcore_bankmachine7_source_valid;
+wire   [23:0] main_litedramcore_bankmachine7_syncfifo7_din;
+wire   [23:0] main_litedramcore_bankmachine7_syncfifo7_dout;
+wire          main_litedramcore_bankmachine7_syncfifo7_re;
+wire          main_litedramcore_bankmachine7_syncfifo7_readable;
+wire          main_litedramcore_bankmachine7_syncfifo7_we;
+wire          main_litedramcore_bankmachine7_syncfifo7_writable;
+reg     [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine7_trccon_valid;
+reg           main_litedramcore_bankmachine7_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine7_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
-wire          litedramcore_bankmachine7_trascon_valid;
+reg           main_litedramcore_bankmachine7_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine7_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine7_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
-wire          litedramcore_ras_allowed;
-wire          litedramcore_cas_allowed;
-wire    [1:0] litedramcore_rdcmdphase;
-wire    [1:0] litedramcore_wrcmdphase;
-reg           litedramcore_choose_cmd_want_reads = 1'd0;
-reg           litedramcore_choose_cmd_want_writes = 1'd0;
-reg           litedramcore_choose_cmd_want_cmds = 1'd0;
-reg           litedramcore_choose_cmd_want_activates = 1'd0;
-wire          litedramcore_choose_cmd_cmd_valid;
-reg           litedramcore_choose_cmd_cmd_ready = 1'd0;
-wire   [13:0] litedramcore_choose_cmd_cmd_payload_a;
-wire    [2:0] litedramcore_choose_cmd_cmd_payload_ba;
-reg           litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg           litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg           litedramcore_choose_cmd_cmd_payload_we = 1'd0;
-wire          litedramcore_choose_cmd_cmd_payload_is_cmd;
-wire          litedramcore_choose_cmd_cmd_payload_is_read;
-wire          litedramcore_choose_cmd_cmd_payload_is_write;
-reg     [7:0] litedramcore_choose_cmd_valids = 8'd0;
-wire    [7:0] litedramcore_choose_cmd_request;
-reg     [2:0] litedramcore_choose_cmd_grant = 3'd0;
-wire          litedramcore_choose_cmd_ce;
-reg           litedramcore_choose_req_want_reads = 1'd0;
-reg           litedramcore_choose_req_want_writes = 1'd0;
-reg           litedramcore_choose_req_want_cmds = 1'd0;
-reg           litedramcore_choose_req_want_activates = 1'd0;
-wire          litedramcore_choose_req_cmd_valid;
-reg           litedramcore_choose_req_cmd_ready = 1'd0;
-wire   [13:0] litedramcore_choose_req_cmd_payload_a;
-wire    [2:0] litedramcore_choose_req_cmd_payload_ba;
-reg           litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg           litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg           litedramcore_choose_req_cmd_payload_we = 1'd0;
-wire          litedramcore_choose_req_cmd_payload_is_cmd;
-wire          litedramcore_choose_req_cmd_payload_is_read;
-wire          litedramcore_choose_req_cmd_payload_is_write;
-reg     [7:0] litedramcore_choose_req_valids = 8'd0;
-wire    [7:0] litedramcore_choose_req_request;
-reg     [2:0] litedramcore_choose_req_grant = 3'd0;
-wire          litedramcore_choose_req_ce;
-reg    [13:0] litedramcore_nop_a = 14'd0;
-reg     [2:0] litedramcore_nop_ba = 3'd0;
-reg     [1:0] litedramcore_steerer_sel0 = 2'd0;
-reg     [1:0] litedramcore_steerer_sel1 = 2'd0;
-reg     [1:0] litedramcore_steerer_sel2 = 2'd0;
-reg     [1:0] litedramcore_steerer_sel3 = 2'd0;
-reg           litedramcore_steerer0 = 1'd1;
-reg           litedramcore_steerer1 = 1'd1;
-reg           litedramcore_steerer2 = 1'd1;
-reg           litedramcore_steerer3 = 1'd1;
-reg           litedramcore_steerer4 = 1'd1;
-reg           litedramcore_steerer5 = 1'd1;
-reg           litedramcore_steerer6 = 1'd1;
-reg           litedramcore_steerer7 = 1'd1;
-wire          litedramcore_trrdcon_valid;
+reg           main_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine7_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine7_wrport_adr = 4'd0;
+wire   [23:0] main_litedramcore_bankmachine7_wrport_dat_r;
+wire   [23:0] main_litedramcore_bankmachine7_wrport_dat_w;
+wire          main_litedramcore_bankmachine7_wrport_we;
+wire          main_litedramcore_cas_allowed;
+wire          main_litedramcore_choose_cmd_ce;
+wire   [13:0] main_litedramcore_choose_cmd_cmd_payload_a;
+wire    [2:0] main_litedramcore_choose_cmd_cmd_payload_ba;
+reg           main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+wire          main_litedramcore_choose_cmd_cmd_payload_is_cmd;
+wire          main_litedramcore_choose_cmd_cmd_payload_is_read;
+wire          main_litedramcore_choose_cmd_cmd_payload_is_write;
+reg           main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+reg           main_litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire          main_litedramcore_choose_cmd_cmd_valid;
+reg     [2:0] main_litedramcore_choose_cmd_grant = 3'd0;
+wire    [7:0] main_litedramcore_choose_cmd_request;
+reg     [7:0] main_litedramcore_choose_cmd_valids = 8'd0;
+reg           main_litedramcore_choose_cmd_want_activates = 1'd0;
+reg           main_litedramcore_choose_cmd_want_cmds = 1'd0;
+reg           main_litedramcore_choose_cmd_want_reads = 1'd0;
+reg           main_litedramcore_choose_cmd_want_writes = 1'd0;
+wire          main_litedramcore_choose_req_ce;
+wire   [13:0] main_litedramcore_choose_req_cmd_payload_a;
+wire    [2:0] main_litedramcore_choose_req_cmd_payload_ba;
+reg           main_litedramcore_choose_req_cmd_payload_cas = 1'd0;
+wire          main_litedramcore_choose_req_cmd_payload_is_cmd;
+wire          main_litedramcore_choose_req_cmd_payload_is_read;
+wire          main_litedramcore_choose_req_cmd_payload_is_write;
+reg           main_litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_choose_req_cmd_payload_we = 1'd0;
+reg           main_litedramcore_choose_req_cmd_ready = 1'd0;
+wire          main_litedramcore_choose_req_cmd_valid;
+reg     [2:0] main_litedramcore_choose_req_grant = 3'd0;
+wire    [7:0] main_litedramcore_choose_req_request;
+reg     [7:0] main_litedramcore_choose_req_valids = 8'd0;
+reg           main_litedramcore_choose_req_want_activates = 1'd0;
+reg           main_litedramcore_choose_req_want_cmds = 1'd0;
+reg           main_litedramcore_choose_req_want_reads = 1'd0;
+reg           main_litedramcore_choose_req_want_writes = 1'd0;
+wire          main_litedramcore_cke;
+reg           main_litedramcore_cmd_last = 1'd0;
+reg    [13:0] main_litedramcore_cmd_payload_a = 14'd0;
+reg     [2:0] main_litedramcore_cmd_payload_ba = 3'd0;
+reg           main_litedramcore_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_cmd_payload_we = 1'd0;
+reg           main_litedramcore_cmd_ready = 1'd0;
+reg           main_litedramcore_cmd_valid = 1'd0;
+reg           main_litedramcore_csr_dfi_p0_act_n = 1'd1;
+wire   [13:0] main_litedramcore_csr_dfi_p0_address;
+wire    [2:0] main_litedramcore_csr_dfi_p0_bank;
+reg           main_litedramcore_csr_dfi_p0_cas_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p0_cke = 1'd0;
+reg           main_litedramcore_csr_dfi_p0_cs_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p0_odt = 1'd0;
+reg           main_litedramcore_csr_dfi_p0_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_csr_dfi_p0_rddata = 32'd0;
+wire          main_litedramcore_csr_dfi_p0_rddata_en;
+reg           main_litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
+wire          main_litedramcore_csr_dfi_p0_reset_n;
+reg           main_litedramcore_csr_dfi_p0_we_n = 1'd1;
+wire   [31:0] main_litedramcore_csr_dfi_p0_wrdata;
+wire          main_litedramcore_csr_dfi_p0_wrdata_en;
+wire    [3:0] main_litedramcore_csr_dfi_p0_wrdata_mask;
+reg           main_litedramcore_csr_dfi_p1_act_n = 1'd1;
+wire   [13:0] main_litedramcore_csr_dfi_p1_address;
+wire    [2:0] main_litedramcore_csr_dfi_p1_bank;
+reg           main_litedramcore_csr_dfi_p1_cas_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p1_cke = 1'd0;
+reg           main_litedramcore_csr_dfi_p1_cs_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p1_odt = 1'd0;
+reg           main_litedramcore_csr_dfi_p1_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_csr_dfi_p1_rddata = 32'd0;
+wire          main_litedramcore_csr_dfi_p1_rddata_en;
+reg           main_litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
+wire          main_litedramcore_csr_dfi_p1_reset_n;
+reg           main_litedramcore_csr_dfi_p1_we_n = 1'd1;
+wire   [31:0] main_litedramcore_csr_dfi_p1_wrdata;
+wire          main_litedramcore_csr_dfi_p1_wrdata_en;
+wire    [3:0] main_litedramcore_csr_dfi_p1_wrdata_mask;
+reg           main_litedramcore_csr_dfi_p2_act_n = 1'd1;
+wire   [13:0] main_litedramcore_csr_dfi_p2_address;
+wire    [2:0] main_litedramcore_csr_dfi_p2_bank;
+reg           main_litedramcore_csr_dfi_p2_cas_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p2_cke = 1'd0;
+reg           main_litedramcore_csr_dfi_p2_cs_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p2_odt = 1'd0;
+reg           main_litedramcore_csr_dfi_p2_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_csr_dfi_p2_rddata = 32'd0;
+wire          main_litedramcore_csr_dfi_p2_rddata_en;
+reg           main_litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
+wire          main_litedramcore_csr_dfi_p2_reset_n;
+reg           main_litedramcore_csr_dfi_p2_we_n = 1'd1;
+wire   [31:0] main_litedramcore_csr_dfi_p2_wrdata;
+wire          main_litedramcore_csr_dfi_p2_wrdata_en;
+wire    [3:0] main_litedramcore_csr_dfi_p2_wrdata_mask;
+reg           main_litedramcore_csr_dfi_p3_act_n = 1'd1;
+wire   [13:0] main_litedramcore_csr_dfi_p3_address;
+wire    [2:0] main_litedramcore_csr_dfi_p3_bank;
+reg           main_litedramcore_csr_dfi_p3_cas_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p3_cke = 1'd0;
+reg           main_litedramcore_csr_dfi_p3_cs_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p3_odt = 1'd0;
+reg           main_litedramcore_csr_dfi_p3_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_csr_dfi_p3_rddata = 32'd0;
+wire          main_litedramcore_csr_dfi_p3_rddata_en;
+reg           main_litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
+wire          main_litedramcore_csr_dfi_p3_reset_n;
+reg           main_litedramcore_csr_dfi_p3_we_n = 1'd1;
+wire   [31:0] main_litedramcore_csr_dfi_p3_wrdata;
+wire          main_litedramcore_csr_dfi_p3_wrdata_en;
+wire    [3:0] main_litedramcore_csr_dfi_p3_wrdata_mask;
+reg           main_litedramcore_dfi_p0_act_n = 1'd1;
+reg    [13:0] main_litedramcore_dfi_p0_address = 14'd0;
+reg     [2:0] main_litedramcore_dfi_p0_bank = 3'd0;
+reg           main_litedramcore_dfi_p0_cas_n = 1'd1;
+wire          main_litedramcore_dfi_p0_cke;
+reg           main_litedramcore_dfi_p0_cs_n = 1'd1;
+wire          main_litedramcore_dfi_p0_odt;
+reg           main_litedramcore_dfi_p0_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p0_rddata;
+reg           main_litedramcore_dfi_p0_rddata_en = 1'd0;
+wire          main_litedramcore_dfi_p0_rddata_valid;
+wire          main_litedramcore_dfi_p0_reset_n;
+reg           main_litedramcore_dfi_p0_we_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p0_wrdata;
+reg           main_litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire    [3:0] main_litedramcore_dfi_p0_wrdata_mask;
+reg           main_litedramcore_dfi_p1_act_n = 1'd1;
+reg    [13:0] main_litedramcore_dfi_p1_address = 14'd0;
+reg     [2:0] main_litedramcore_dfi_p1_bank = 3'd0;
+reg           main_litedramcore_dfi_p1_cas_n = 1'd1;
+wire          main_litedramcore_dfi_p1_cke;
+reg           main_litedramcore_dfi_p1_cs_n = 1'd1;
+wire          main_litedramcore_dfi_p1_odt;
+reg           main_litedramcore_dfi_p1_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p1_rddata;
+reg           main_litedramcore_dfi_p1_rddata_en = 1'd0;
+wire          main_litedramcore_dfi_p1_rddata_valid;
+wire          main_litedramcore_dfi_p1_reset_n;
+reg           main_litedramcore_dfi_p1_we_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p1_wrdata;
+reg           main_litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire    [3:0] main_litedramcore_dfi_p1_wrdata_mask;
+reg           main_litedramcore_dfi_p2_act_n = 1'd1;
+reg    [13:0] main_litedramcore_dfi_p2_address = 14'd0;
+reg     [2:0] main_litedramcore_dfi_p2_bank = 3'd0;
+reg           main_litedramcore_dfi_p2_cas_n = 1'd1;
+wire          main_litedramcore_dfi_p2_cke;
+reg           main_litedramcore_dfi_p2_cs_n = 1'd1;
+wire          main_litedramcore_dfi_p2_odt;
+reg           main_litedramcore_dfi_p2_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p2_rddata;
+reg           main_litedramcore_dfi_p2_rddata_en = 1'd0;
+wire          main_litedramcore_dfi_p2_rddata_valid;
+wire          main_litedramcore_dfi_p2_reset_n;
+reg           main_litedramcore_dfi_p2_we_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p2_wrdata;
+reg           main_litedramcore_dfi_p2_wrdata_en = 1'd0;
+wire    [3:0] main_litedramcore_dfi_p2_wrdata_mask;
+reg           main_litedramcore_dfi_p3_act_n = 1'd1;
+reg    [13:0] main_litedramcore_dfi_p3_address = 14'd0;
+reg     [2:0] main_litedramcore_dfi_p3_bank = 3'd0;
+reg           main_litedramcore_dfi_p3_cas_n = 1'd1;
+wire          main_litedramcore_dfi_p3_cke;
+reg           main_litedramcore_dfi_p3_cs_n = 1'd1;
+wire          main_litedramcore_dfi_p3_odt;
+reg           main_litedramcore_dfi_p3_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p3_rddata;
+reg           main_litedramcore_dfi_p3_rddata_en = 1'd0;
+wire          main_litedramcore_dfi_p3_rddata_valid;
+wire          main_litedramcore_dfi_p3_reset_n;
+reg           main_litedramcore_dfi_p3_we_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p3_wrdata;
+reg           main_litedramcore_dfi_p3_wrdata_en = 1'd0;
+wire    [3:0] main_litedramcore_dfi_p3_wrdata_mask;
+reg           main_litedramcore_en0 = 1'd0;
+reg           main_litedramcore_en1 = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_act_n = 1'd1;
+reg    [13:0] main_litedramcore_ext_dfi_p0_address = 14'd0;
+reg     [2:0] main_litedramcore_ext_dfi_p0_bank = 3'd0;
+reg           main_litedramcore_ext_dfi_p0_cas_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p0_cke = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_cs_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p0_odt = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p0_rddata = 32'd0;
+reg           main_litedramcore_ext_dfi_p0_rddata_en = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_reset_n = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_we_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p0_wrdata = 32'd0;
+reg           main_litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
+reg           main_litedramcore_ext_dfi_p1_act_n = 1'd1;
+reg    [13:0] main_litedramcore_ext_dfi_p1_address = 14'd0;
+reg     [2:0] main_litedramcore_ext_dfi_p1_bank = 3'd0;
+reg           main_litedramcore_ext_dfi_p1_cas_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p1_cke = 1'd0;
+reg           main_litedramcore_ext_dfi_p1_cs_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p1_odt = 1'd0;
+reg           main_litedramcore_ext_dfi_p1_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p1_rddata = 32'd0;
+reg           main_litedramcore_ext_dfi_p1_rddata_en = 1'd0;
+reg           main_litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
+reg           main_litedramcore_ext_dfi_p1_reset_n = 1'd0;
+reg           main_litedramcore_ext_dfi_p1_we_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p1_wrdata = 32'd0;
+reg           main_litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
+reg           main_litedramcore_ext_dfi_p2_act_n = 1'd1;
+reg    [13:0] main_litedramcore_ext_dfi_p2_address = 14'd0;
+reg     [2:0] main_litedramcore_ext_dfi_p2_bank = 3'd0;
+reg           main_litedramcore_ext_dfi_p2_cas_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p2_cke = 1'd0;
+reg           main_litedramcore_ext_dfi_p2_cs_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p2_odt = 1'd0;
+reg           main_litedramcore_ext_dfi_p2_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p2_rddata = 32'd0;
+reg           main_litedramcore_ext_dfi_p2_rddata_en = 1'd0;
+reg           main_litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
+reg           main_litedramcore_ext_dfi_p2_reset_n = 1'd0;
+reg           main_litedramcore_ext_dfi_p2_we_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p2_wrdata = 32'd0;
+reg           main_litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
+reg           main_litedramcore_ext_dfi_p3_act_n = 1'd1;
+reg    [13:0] main_litedramcore_ext_dfi_p3_address = 14'd0;
+reg     [2:0] main_litedramcore_ext_dfi_p3_bank = 3'd0;
+reg           main_litedramcore_ext_dfi_p3_cas_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p3_cke = 1'd0;
+reg           main_litedramcore_ext_dfi_p3_cs_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p3_odt = 1'd0;
+reg           main_litedramcore_ext_dfi_p3_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p3_rddata = 32'd0;
+reg           main_litedramcore_ext_dfi_p3_rddata_en = 1'd0;
+reg           main_litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
+reg           main_litedramcore_ext_dfi_p3_reset_n = 1'd0;
+reg           main_litedramcore_ext_dfi_p3_we_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p3_wrdata = 32'd0;
+reg           main_litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
+reg           main_litedramcore_ext_dfi_sel = 1'd0;
+wire          main_litedramcore_go_to_refresh;
+wire   [20:0] main_litedramcore_interface_bank0_addr;
+wire          main_litedramcore_interface_bank0_lock;
+wire          main_litedramcore_interface_bank0_rdata_valid;
+wire          main_litedramcore_interface_bank0_ready;
+wire          main_litedramcore_interface_bank0_valid;
+wire          main_litedramcore_interface_bank0_wdata_ready;
+wire          main_litedramcore_interface_bank0_we;
+wire   [20:0] main_litedramcore_interface_bank1_addr;
+wire          main_litedramcore_interface_bank1_lock;
+wire          main_litedramcore_interface_bank1_rdata_valid;
+wire          main_litedramcore_interface_bank1_ready;
+wire          main_litedramcore_interface_bank1_valid;
+wire          main_litedramcore_interface_bank1_wdata_ready;
+wire          main_litedramcore_interface_bank1_we;
+wire   [20:0] main_litedramcore_interface_bank2_addr;
+wire          main_litedramcore_interface_bank2_lock;
+wire          main_litedramcore_interface_bank2_rdata_valid;
+wire          main_litedramcore_interface_bank2_ready;
+wire          main_litedramcore_interface_bank2_valid;
+wire          main_litedramcore_interface_bank2_wdata_ready;
+wire          main_litedramcore_interface_bank2_we;
+wire   [20:0] main_litedramcore_interface_bank3_addr;
+wire          main_litedramcore_interface_bank3_lock;
+wire          main_litedramcore_interface_bank3_rdata_valid;
+wire          main_litedramcore_interface_bank3_ready;
+wire          main_litedramcore_interface_bank3_valid;
+wire          main_litedramcore_interface_bank3_wdata_ready;
+wire          main_litedramcore_interface_bank3_we;
+wire   [20:0] main_litedramcore_interface_bank4_addr;
+wire          main_litedramcore_interface_bank4_lock;
+wire          main_litedramcore_interface_bank4_rdata_valid;
+wire          main_litedramcore_interface_bank4_ready;
+wire          main_litedramcore_interface_bank4_valid;
+wire          main_litedramcore_interface_bank4_wdata_ready;
+wire          main_litedramcore_interface_bank4_we;
+wire   [20:0] main_litedramcore_interface_bank5_addr;
+wire          main_litedramcore_interface_bank5_lock;
+wire          main_litedramcore_interface_bank5_rdata_valid;
+wire          main_litedramcore_interface_bank5_ready;
+wire          main_litedramcore_interface_bank5_valid;
+wire          main_litedramcore_interface_bank5_wdata_ready;
+wire          main_litedramcore_interface_bank5_we;
+wire   [20:0] main_litedramcore_interface_bank6_addr;
+wire          main_litedramcore_interface_bank6_lock;
+wire          main_litedramcore_interface_bank6_rdata_valid;
+wire          main_litedramcore_interface_bank6_ready;
+wire          main_litedramcore_interface_bank6_valid;
+wire          main_litedramcore_interface_bank6_wdata_ready;
+wire          main_litedramcore_interface_bank6_we;
+wire   [20:0] main_litedramcore_interface_bank7_addr;
+wire          main_litedramcore_interface_bank7_lock;
+wire          main_litedramcore_interface_bank7_rdata_valid;
+wire          main_litedramcore_interface_bank7_ready;
+wire          main_litedramcore_interface_bank7_valid;
+wire          main_litedramcore_interface_bank7_wdata_ready;
+wire          main_litedramcore_interface_bank7_we;
+wire  [127:0] main_litedramcore_interface_rdata;
+reg   [127:0] main_litedramcore_interface_wdata = 128'd0;
+reg    [15:0] main_litedramcore_interface_wdata_we = 16'd0;
+reg           main_litedramcore_master_p0_act_n = 1'd1;
+reg    [13:0] main_litedramcore_master_p0_address = 14'd0;
+reg     [2:0] main_litedramcore_master_p0_bank = 3'd0;
+reg           main_litedramcore_master_p0_cas_n = 1'd1;
+reg           main_litedramcore_master_p0_cke = 1'd0;
+reg           main_litedramcore_master_p0_cs_n = 1'd1;
+reg           main_litedramcore_master_p0_odt = 1'd0;
+reg           main_litedramcore_master_p0_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_master_p0_rddata;
+reg           main_litedramcore_master_p0_rddata_en = 1'd0;
+wire          main_litedramcore_master_p0_rddata_valid;
+reg           main_litedramcore_master_p0_reset_n = 1'd0;
+reg           main_litedramcore_master_p0_we_n = 1'd1;
+reg    [31:0] main_litedramcore_master_p0_wrdata = 32'd0;
+reg           main_litedramcore_master_p0_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0;
+reg           main_litedramcore_master_p1_act_n = 1'd1;
+reg    [13:0] main_litedramcore_master_p1_address = 14'd0;
+reg     [2:0] main_litedramcore_master_p1_bank = 3'd0;
+reg           main_litedramcore_master_p1_cas_n = 1'd1;
+reg           main_litedramcore_master_p1_cke = 1'd0;
+reg           main_litedramcore_master_p1_cs_n = 1'd1;
+reg           main_litedramcore_master_p1_odt = 1'd0;
+reg           main_litedramcore_master_p1_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_master_p1_rddata;
+reg           main_litedramcore_master_p1_rddata_en = 1'd0;
+wire          main_litedramcore_master_p1_rddata_valid;
+reg           main_litedramcore_master_p1_reset_n = 1'd0;
+reg           main_litedramcore_master_p1_we_n = 1'd1;
+reg    [31:0] main_litedramcore_master_p1_wrdata = 32'd0;
+reg           main_litedramcore_master_p1_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0;
+reg           main_litedramcore_master_p2_act_n = 1'd1;
+reg    [13:0] main_litedramcore_master_p2_address = 14'd0;
+reg     [2:0] main_litedramcore_master_p2_bank = 3'd0;
+reg           main_litedramcore_master_p2_cas_n = 1'd1;
+reg           main_litedramcore_master_p2_cke = 1'd0;
+reg           main_litedramcore_master_p2_cs_n = 1'd1;
+reg           main_litedramcore_master_p2_odt = 1'd0;
+reg           main_litedramcore_master_p2_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_master_p2_rddata;
+reg           main_litedramcore_master_p2_rddata_en = 1'd0;
+wire          main_litedramcore_master_p2_rddata_valid;
+reg           main_litedramcore_master_p2_reset_n = 1'd0;
+reg           main_litedramcore_master_p2_we_n = 1'd1;
+reg    [31:0] main_litedramcore_master_p2_wrdata = 32'd0;
+reg           main_litedramcore_master_p2_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0;
+reg           main_litedramcore_master_p3_act_n = 1'd1;
+reg    [13:0] main_litedramcore_master_p3_address = 14'd0;
+reg     [2:0] main_litedramcore_master_p3_bank = 3'd0;
+reg           main_litedramcore_master_p3_cas_n = 1'd1;
+reg           main_litedramcore_master_p3_cke = 1'd0;
+reg           main_litedramcore_master_p3_cs_n = 1'd1;
+reg           main_litedramcore_master_p3_odt = 1'd0;
+reg           main_litedramcore_master_p3_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_master_p3_rddata;
+reg           main_litedramcore_master_p3_rddata_en = 1'd0;
+wire          main_litedramcore_master_p3_rddata_valid;
+reg           main_litedramcore_master_p3_reset_n = 1'd0;
+reg           main_litedramcore_master_p3_we_n = 1'd1;
+reg    [31:0] main_litedramcore_master_p3_wrdata = 32'd0;
+reg           main_litedramcore_master_p3_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0;
+wire          main_litedramcore_max_time0;
+wire          main_litedramcore_max_time1;
+reg    [13:0] main_litedramcore_nop_a = 14'd0;
+reg     [2:0] main_litedramcore_nop_ba = 3'd0;
+wire    [1:0] main_litedramcore_nphases;
+wire          main_litedramcore_odt;
+reg           main_litedramcore_phaseinjector0_address_re = 1'd0;
+reg    [13:0] main_litedramcore_phaseinjector0_address_storage = 14'd0;
+reg           main_litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg     [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0;
+wire          main_litedramcore_phaseinjector0_command_issue_r;
+reg           main_litedramcore_phaseinjector0_command_issue_re = 1'd0;
+reg           main_litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg           main_litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg           main_litedramcore_phaseinjector0_command_re = 1'd0;
+reg     [7:0] main_litedramcore_phaseinjector0_command_storage = 8'd0;
+wire          main_litedramcore_phaseinjector0_csrfield_cas;
+wire          main_litedramcore_phaseinjector0_csrfield_cs;
+wire          main_litedramcore_phaseinjector0_csrfield_cs_bottom;
+wire          main_litedramcore_phaseinjector0_csrfield_cs_top;
+wire          main_litedramcore_phaseinjector0_csrfield_ras;
+wire          main_litedramcore_phaseinjector0_csrfield_rden;
+wire          main_litedramcore_phaseinjector0_csrfield_we;
+wire          main_litedramcore_phaseinjector0_csrfield_wren;
+reg           main_litedramcore_phaseinjector0_rddata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0;
+wire          main_litedramcore_phaseinjector0_rddata_we;
+reg           main_litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
+reg           main_litedramcore_phaseinjector1_address_re = 1'd0;
+reg    [13:0] main_litedramcore_phaseinjector1_address_storage = 14'd0;
+reg           main_litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg     [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0;
+wire          main_litedramcore_phaseinjector1_command_issue_r;
+reg           main_litedramcore_phaseinjector1_command_issue_re = 1'd0;
+reg           main_litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg           main_litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg           main_litedramcore_phaseinjector1_command_re = 1'd0;
+reg     [7:0] main_litedramcore_phaseinjector1_command_storage = 8'd0;
+wire          main_litedramcore_phaseinjector1_csrfield_cas;
+wire          main_litedramcore_phaseinjector1_csrfield_cs;
+wire          main_litedramcore_phaseinjector1_csrfield_cs_bottom;
+wire          main_litedramcore_phaseinjector1_csrfield_cs_top;
+wire          main_litedramcore_phaseinjector1_csrfield_ras;
+wire          main_litedramcore_phaseinjector1_csrfield_rden;
+wire          main_litedramcore_phaseinjector1_csrfield_we;
+wire          main_litedramcore_phaseinjector1_csrfield_wren;
+reg           main_litedramcore_phaseinjector1_rddata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0;
+wire          main_litedramcore_phaseinjector1_rddata_we;
+reg           main_litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
+reg           main_litedramcore_phaseinjector2_address_re = 1'd0;
+reg    [13:0] main_litedramcore_phaseinjector2_address_storage = 14'd0;
+reg           main_litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg     [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0;
+wire          main_litedramcore_phaseinjector2_command_issue_r;
+reg           main_litedramcore_phaseinjector2_command_issue_re = 1'd0;
+reg           main_litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg           main_litedramcore_phaseinjector2_command_issue_we = 1'd0;
+reg           main_litedramcore_phaseinjector2_command_re = 1'd0;
+reg     [7:0] main_litedramcore_phaseinjector2_command_storage = 8'd0;
+wire          main_litedramcore_phaseinjector2_csrfield_cas;
+wire          main_litedramcore_phaseinjector2_csrfield_cs;
+wire          main_litedramcore_phaseinjector2_csrfield_cs_bottom;
+wire          main_litedramcore_phaseinjector2_csrfield_cs_top;
+wire          main_litedramcore_phaseinjector2_csrfield_ras;
+wire          main_litedramcore_phaseinjector2_csrfield_rden;
+wire          main_litedramcore_phaseinjector2_csrfield_we;
+wire          main_litedramcore_phaseinjector2_csrfield_wren;
+reg           main_litedramcore_phaseinjector2_rddata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0;
+wire          main_litedramcore_phaseinjector2_rddata_we;
+reg           main_litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
+reg           main_litedramcore_phaseinjector3_address_re = 1'd0;
+reg    [13:0] main_litedramcore_phaseinjector3_address_storage = 14'd0;
+reg           main_litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg     [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0;
+wire          main_litedramcore_phaseinjector3_command_issue_r;
+reg           main_litedramcore_phaseinjector3_command_issue_re = 1'd0;
+reg           main_litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg           main_litedramcore_phaseinjector3_command_issue_we = 1'd0;
+reg           main_litedramcore_phaseinjector3_command_re = 1'd0;
+reg     [7:0] main_litedramcore_phaseinjector3_command_storage = 8'd0;
+wire          main_litedramcore_phaseinjector3_csrfield_cas;
+wire          main_litedramcore_phaseinjector3_csrfield_cs;
+wire          main_litedramcore_phaseinjector3_csrfield_cs_bottom;
+wire          main_litedramcore_phaseinjector3_csrfield_cs_top;
+wire          main_litedramcore_phaseinjector3_csrfield_ras;
+wire          main_litedramcore_phaseinjector3_csrfield_rden;
+wire          main_litedramcore_phaseinjector3_csrfield_we;
+wire          main_litedramcore_phaseinjector3_csrfield_wren;
+reg           main_litedramcore_phaseinjector3_rddata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0;
+wire          main_litedramcore_phaseinjector3_rddata_we;
+reg           main_litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
+reg           main_litedramcore_postponer_count = 1'd0;
+wire          main_litedramcore_postponer_req_i;
+reg           main_litedramcore_postponer_req_o = 1'd0;
+wire          main_litedramcore_ras_allowed;
+wire    [1:0] main_litedramcore_rdphase;
+reg           main_litedramcore_re = 1'd0;
+wire          main_litedramcore_read_available;
+wire          main_litedramcore_reset_n;
+wire          main_litedramcore_sel;
+reg           main_litedramcore_sequencer_count = 1'd0;
+wire          main_litedramcore_sequencer_done0;
+reg           main_litedramcore_sequencer_done1 = 1'd0;
+reg           main_litedramcore_sequencer_start0 = 1'd0;
+wire          main_litedramcore_sequencer_start1;
+reg     [5:0] main_litedramcore_sequencer_trigger = 6'd0;
+wire          main_litedramcore_slave_p0_act_n;
+wire   [13:0] main_litedramcore_slave_p0_address;
+wire    [2:0] main_litedramcore_slave_p0_bank;
+wire          main_litedramcore_slave_p0_cas_n;
+wire          main_litedramcore_slave_p0_cke;
+wire          main_litedramcore_slave_p0_cs_n;
+wire          main_litedramcore_slave_p0_odt;
+wire          main_litedramcore_slave_p0_ras_n;
+reg    [31:0] main_litedramcore_slave_p0_rddata = 32'd0;
+wire          main_litedramcore_slave_p0_rddata_en;
+reg           main_litedramcore_slave_p0_rddata_valid = 1'd0;
+wire          main_litedramcore_slave_p0_reset_n;
+wire          main_litedramcore_slave_p0_we_n;
+wire   [31:0] main_litedramcore_slave_p0_wrdata;
+wire          main_litedramcore_slave_p0_wrdata_en;
+wire    [3:0] main_litedramcore_slave_p0_wrdata_mask;
+wire          main_litedramcore_slave_p1_act_n;
+wire   [13:0] main_litedramcore_slave_p1_address;
+wire    [2:0] main_litedramcore_slave_p1_bank;
+wire          main_litedramcore_slave_p1_cas_n;
+wire          main_litedramcore_slave_p1_cke;
+wire          main_litedramcore_slave_p1_cs_n;
+wire          main_litedramcore_slave_p1_odt;
+wire          main_litedramcore_slave_p1_ras_n;
+reg    [31:0] main_litedramcore_slave_p1_rddata = 32'd0;
+wire          main_litedramcore_slave_p1_rddata_en;
+reg           main_litedramcore_slave_p1_rddata_valid = 1'd0;
+wire          main_litedramcore_slave_p1_reset_n;
+wire          main_litedramcore_slave_p1_we_n;
+wire   [31:0] main_litedramcore_slave_p1_wrdata;
+wire          main_litedramcore_slave_p1_wrdata_en;
+wire    [3:0] main_litedramcore_slave_p1_wrdata_mask;
+wire          main_litedramcore_slave_p2_act_n;
+wire   [13:0] main_litedramcore_slave_p2_address;
+wire    [2:0] main_litedramcore_slave_p2_bank;
+wire          main_litedramcore_slave_p2_cas_n;
+wire          main_litedramcore_slave_p2_cke;
+wire          main_litedramcore_slave_p2_cs_n;
+wire          main_litedramcore_slave_p2_odt;
+wire          main_litedramcore_slave_p2_ras_n;
+reg    [31:0] main_litedramcore_slave_p2_rddata = 32'd0;
+wire          main_litedramcore_slave_p2_rddata_en;
+reg           main_litedramcore_slave_p2_rddata_valid = 1'd0;
+wire          main_litedramcore_slave_p2_reset_n;
+wire          main_litedramcore_slave_p2_we_n;
+wire   [31:0] main_litedramcore_slave_p2_wrdata;
+wire          main_litedramcore_slave_p2_wrdata_en;
+wire    [3:0] main_litedramcore_slave_p2_wrdata_mask;
+wire          main_litedramcore_slave_p3_act_n;
+wire   [13:0] main_litedramcore_slave_p3_address;
+wire    [2:0] main_litedramcore_slave_p3_bank;
+wire          main_litedramcore_slave_p3_cas_n;
+wire          main_litedramcore_slave_p3_cke;
+wire          main_litedramcore_slave_p3_cs_n;
+wire          main_litedramcore_slave_p3_odt;
+wire          main_litedramcore_slave_p3_ras_n;
+reg    [31:0] main_litedramcore_slave_p3_rddata = 32'd0;
+wire          main_litedramcore_slave_p3_rddata_en;
+reg           main_litedramcore_slave_p3_rddata_valid = 1'd0;
+wire          main_litedramcore_slave_p3_reset_n;
+wire          main_litedramcore_slave_p3_we_n;
+wire   [31:0] main_litedramcore_slave_p3_wrdata;
+wire          main_litedramcore_slave_p3_wrdata_en;
+wire    [3:0] main_litedramcore_slave_p3_wrdata_mask;
+reg     [1:0] main_litedramcore_steerer0 = 2'd0;
+reg     [1:0] main_litedramcore_steerer1 = 2'd0;
+reg           main_litedramcore_steerer10 = 1'd1;
+reg           main_litedramcore_steerer11 = 1'd1;
+reg     [1:0] main_litedramcore_steerer2 = 2'd0;
+reg     [1:0] main_litedramcore_steerer3 = 2'd0;
+reg           main_litedramcore_steerer4 = 1'd1;
+reg           main_litedramcore_steerer5 = 1'd1;
+reg           main_litedramcore_steerer6 = 1'd1;
+reg           main_litedramcore_steerer7 = 1'd1;
+reg           main_litedramcore_steerer8 = 1'd1;
+reg           main_litedramcore_steerer9 = 1'd1;
+reg     [3:0] main_litedramcore_storage = 4'd1;
+reg           main_litedramcore_tccdcon_count = 1'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_trrdcon_ready = 1'd0;
-reg           litedramcore_trrdcon_count = 1'd0;
-wire          litedramcore_tfawcon_valid;
+reg           main_litedramcore_tccdcon_ready = 1'd0;
+wire          main_litedramcore_tccdcon_valid;
+wire    [2:0] main_litedramcore_tfawcon_count;
 (* dont_touch = "true" *)
-reg           litedramcore_tfawcon_ready = 1'd1;
-wire    [2:0] litedramcore_tfawcon_count;
-reg     [4:0] litedramcore_tfawcon_window = 5'd0;
-wire          litedramcore_tccdcon_valid;
+reg           main_litedramcore_tfawcon_ready = 1'd1;
+wire          main_litedramcore_tfawcon_valid;
+reg     [4:0] main_litedramcore_tfawcon_window = 5'd0;
+reg     [4:0] main_litedramcore_time0 = 5'd0;
+reg     [3:0] main_litedramcore_time1 = 4'd0;
+wire    [9:0] main_litedramcore_timer_count0;
+reg     [9:0] main_litedramcore_timer_count1 = 10'd781;
+wire          main_litedramcore_timer_done0;
+wire          main_litedramcore_timer_done1;
+wire          main_litedramcore_timer_wait;
+reg           main_litedramcore_trrdcon_count = 1'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_tccdcon_ready = 1'd0;
-reg           litedramcore_tccdcon_count = 1'd0;
-wire          litedramcore_twtrcon_valid;
+reg           main_litedramcore_trrdcon_ready = 1'd0;
+wire          main_litedramcore_trrdcon_valid;
+reg     [2:0] main_litedramcore_twtrcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_twtrcon_ready = 1'd0;
-reg     [2:0] litedramcore_twtrcon_count = 3'd0;
-wire          litedramcore_read_available;
-wire          litedramcore_write_available;
-reg           litedramcore_en0 = 1'd0;
-wire          litedramcore_max_time0;
-reg     [4:0] litedramcore_time0 = 5'd0;
-reg           litedramcore_en1 = 1'd0;
-wire          litedramcore_max_time1;
-reg     [3:0] litedramcore_time1 = 4'd0;
-wire          litedramcore_go_to_refresh;
-reg           init_done_storage = 1'd0;
-reg           init_done_re = 1'd0;
-reg           init_error_storage = 1'd0;
-reg           init_error_re = 1'd0;
-wire   [29:0] wb_bus_adr;
-wire   [31:0] wb_bus_dat_w;
-wire   [31:0] wb_bus_dat_r;
-wire    [3:0] wb_bus_sel;
-wire          wb_bus_cyc;
-wire          wb_bus_stb;
-wire          wb_bus_ack;
-wire          wb_bus_we;
-wire    [2:0] wb_bus_cti;
-wire    [1:0] wb_bus_bte;
-wire          wb_bus_err;
-wire          user_enable;
-wire          user_port_cmd_valid;
-wire          user_port_cmd_ready;
-wire          user_port_cmd_payload_we;
-wire   [23:0] user_port_cmd_payload_addr;
-wire          user_port_wdata_valid;
-wire          user_port_wdata_ready;
-wire  [127:0] user_port_wdata_payload_data;
-wire   [15:0] user_port_wdata_payload_we;
-wire          user_port_rdata_valid;
-wire          user_port_rdata_ready;
-wire  [127:0] user_port_rdata_payload_data;
-reg    [13:0] litedramcore_adr = 14'd0;
-reg           litedramcore_we = 1'd0;
-reg    [31:0] litedramcore_dat_w = 32'd0;
-wire   [31:0] litedramcore_dat_r;
-wire   [29:0] litedramcore_wishbone_adr;
-wire   [31:0] litedramcore_wishbone_dat_w;
-reg    [31:0] litedramcore_wishbone_dat_r = 32'd0;
-wire    [3:0] litedramcore_wishbone_sel;
-wire          litedramcore_wishbone_cyc;
-wire          litedramcore_wishbone_stb;
-reg           litedramcore_wishbone_ack = 1'd0;
-wire          litedramcore_wishbone_we;
-wire    [2:0] litedramcore_wishbone_cti;
-wire    [1:0] litedramcore_wishbone_bte;
-reg           litedramcore_wishbone_err = 1'd0;
-wire   [13:0] interface0_bank_bus_adr;
-wire          interface0_bank_bus_we;
-wire   [31:0] interface0_bank_bus_dat_w;
-reg    [31:0] interface0_bank_bus_dat_r = 32'd0;
-reg           csrbank0_init_done0_re = 1'd0;
-wire          csrbank0_init_done0_r;
-reg           csrbank0_init_done0_we = 1'd0;
-wire          csrbank0_init_done0_w;
-reg           csrbank0_init_error0_re = 1'd0;
-wire          csrbank0_init_error0_r;
-reg           csrbank0_init_error0_we = 1'd0;
-wire          csrbank0_init_error0_w;
-wire          csrbank0_sel;
-wire   [13:0] interface1_bank_bus_adr;
-wire          interface1_bank_bus_we;
-wire   [31:0] interface1_bank_bus_dat_w;
-reg    [31:0] interface1_bank_bus_dat_r = 32'd0;
-reg           csrbank1_rst0_re = 1'd0;
-wire          csrbank1_rst0_r;
-reg           csrbank1_rst0_we = 1'd0;
-wire          csrbank1_rst0_w;
-reg           csrbank1_dly_sel0_re = 1'd0;
-wire    [1:0] csrbank1_dly_sel0_r;
-reg           csrbank1_dly_sel0_we = 1'd0;
-wire    [1:0] csrbank1_dly_sel0_w;
-reg           csrbank1_half_sys8x_taps0_re = 1'd0;
-wire    [4:0] csrbank1_half_sys8x_taps0_r;
-reg           csrbank1_half_sys8x_taps0_we = 1'd0;
-wire    [4:0] csrbank1_half_sys8x_taps0_w;
-reg           csrbank1_wlevel_en0_re = 1'd0;
-wire          csrbank1_wlevel_en0_r;
-reg           csrbank1_wlevel_en0_we = 1'd0;
-wire          csrbank1_wlevel_en0_w;
-reg           csrbank1_rdphase0_re = 1'd0;
-wire    [1:0] csrbank1_rdphase0_r;
-reg           csrbank1_rdphase0_we = 1'd0;
-wire    [1:0] csrbank1_rdphase0_w;
-reg           csrbank1_wrphase0_re = 1'd0;
-wire    [1:0] csrbank1_wrphase0_r;
-reg           csrbank1_wrphase0_we = 1'd0;
-wire    [1:0] csrbank1_wrphase0_w;
-wire          csrbank1_sel;
-wire   [13:0] interface2_bank_bus_adr;
-wire          interface2_bank_bus_we;
-wire   [31:0] interface2_bank_bus_dat_w;
-reg    [31:0] interface2_bank_bus_dat_r = 32'd0;
-reg           csrbank2_dfii_control0_re = 1'd0;
-wire    [3:0] csrbank2_dfii_control0_r;
-reg           csrbank2_dfii_control0_we = 1'd0;
-wire    [3:0] csrbank2_dfii_control0_w;
-reg           csrbank2_dfii_pi0_command0_re = 1'd0;
-wire    [5:0] csrbank2_dfii_pi0_command0_r;
-reg           csrbank2_dfii_pi0_command0_we = 1'd0;
-wire    [5:0] csrbank2_dfii_pi0_command0_w;
-reg           csrbank2_dfii_pi0_address0_re = 1'd0;
-wire   [13:0] csrbank2_dfii_pi0_address0_r;
-reg           csrbank2_dfii_pi0_address0_we = 1'd0;
-wire   [13:0] csrbank2_dfii_pi0_address0_w;
-reg           csrbank2_dfii_pi0_baddress0_re = 1'd0;
-wire    [2:0] csrbank2_dfii_pi0_baddress0_r;
-reg           csrbank2_dfii_pi0_baddress0_we = 1'd0;
-wire    [2:0] csrbank2_dfii_pi0_baddress0_w;
-reg           csrbank2_dfii_pi0_wrdata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_wrdata0_r;
-reg           csrbank2_dfii_pi0_wrdata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_wrdata0_w;
-reg           csrbank2_dfii_pi0_rddata_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_rddata_r;
-reg           csrbank2_dfii_pi0_rddata_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_rddata_w;
-reg           csrbank2_dfii_pi1_command0_re = 1'd0;
-wire    [5:0] csrbank2_dfii_pi1_command0_r;
-reg           csrbank2_dfii_pi1_command0_we = 1'd0;
-wire    [5:0] csrbank2_dfii_pi1_command0_w;
-reg           csrbank2_dfii_pi1_address0_re = 1'd0;
-wire   [13:0] csrbank2_dfii_pi1_address0_r;
-reg           csrbank2_dfii_pi1_address0_we = 1'd0;
-wire   [13:0] csrbank2_dfii_pi1_address0_w;
-reg           csrbank2_dfii_pi1_baddress0_re = 1'd0;
-wire    [2:0] csrbank2_dfii_pi1_baddress0_r;
-reg           csrbank2_dfii_pi1_baddress0_we = 1'd0;
-wire    [2:0] csrbank2_dfii_pi1_baddress0_w;
-reg           csrbank2_dfii_pi1_wrdata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_wrdata0_r;
-reg           csrbank2_dfii_pi1_wrdata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_wrdata0_w;
-reg           csrbank2_dfii_pi1_rddata_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_rddata_r;
-reg           csrbank2_dfii_pi1_rddata_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_rddata_w;
-reg           csrbank2_dfii_pi2_command0_re = 1'd0;
-wire    [5:0] csrbank2_dfii_pi2_command0_r;
-reg           csrbank2_dfii_pi2_command0_we = 1'd0;
-wire    [5:0] csrbank2_dfii_pi2_command0_w;
-reg           csrbank2_dfii_pi2_address0_re = 1'd0;
-wire   [13:0] csrbank2_dfii_pi2_address0_r;
-reg           csrbank2_dfii_pi2_address0_we = 1'd0;
-wire   [13:0] csrbank2_dfii_pi2_address0_w;
-reg           csrbank2_dfii_pi2_baddress0_re = 1'd0;
-wire    [2:0] csrbank2_dfii_pi2_baddress0_r;
-reg           csrbank2_dfii_pi2_baddress0_we = 1'd0;
-wire    [2:0] csrbank2_dfii_pi2_baddress0_w;
-reg           csrbank2_dfii_pi2_wrdata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi2_wrdata0_r;
-reg           csrbank2_dfii_pi2_wrdata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi2_wrdata0_w;
-reg           csrbank2_dfii_pi2_rddata_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi2_rddata_r;
-reg           csrbank2_dfii_pi2_rddata_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi2_rddata_w;
-reg           csrbank2_dfii_pi3_command0_re = 1'd0;
-wire    [5:0] csrbank2_dfii_pi3_command0_r;
-reg           csrbank2_dfii_pi3_command0_we = 1'd0;
-wire    [5:0] csrbank2_dfii_pi3_command0_w;
-reg           csrbank2_dfii_pi3_address0_re = 1'd0;
-wire   [13:0] csrbank2_dfii_pi3_address0_r;
-reg           csrbank2_dfii_pi3_address0_we = 1'd0;
-wire   [13:0] csrbank2_dfii_pi3_address0_w;
-reg           csrbank2_dfii_pi3_baddress0_re = 1'd0;
-wire    [2:0] csrbank2_dfii_pi3_baddress0_r;
-reg           csrbank2_dfii_pi3_baddress0_we = 1'd0;
-wire    [2:0] csrbank2_dfii_pi3_baddress0_w;
-reg           csrbank2_dfii_pi3_wrdata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi3_wrdata0_r;
-reg           csrbank2_dfii_pi3_wrdata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi3_wrdata0_w;
-reg           csrbank2_dfii_pi3_rddata_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi3_rddata_r;
-reg           csrbank2_dfii_pi3_rddata_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi3_rddata_w;
-wire          csrbank2_sel;
-wire   [13:0] csr_interconnect_adr;
-wire          csr_interconnect_we;
-wire   [31:0] csr_interconnect_dat_w;
-wire   [31:0] csr_interconnect_dat_r;
-wire          litedramcore_reset0;
-wire          litedramcore_reset1;
-wire          litedramcore_reset2;
-wire          litedramcore_reset3;
-wire          litedramcore_reset4;
-wire          litedramcore_reset5;
-wire          litedramcore_reset6;
-wire          litedramcore_reset7;
-wire          litedramcore_pll_fb;
-reg     [1:0] litedramcore_refresher_state = 2'd0;
-reg     [1:0] litedramcore_refresher_next_state = 2'd0;
-reg     [3:0] litedramcore_bankmachine0_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine0_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine1_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine1_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine2_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine2_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine3_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine3_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine4_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine4_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine5_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine5_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine6_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine6_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine7_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine7_next_state = 4'd0;
-reg     [3:0] litedramcore_multiplexer_state = 4'd0;
-reg     [3:0] litedramcore_multiplexer_next_state = 4'd0;
-wire          litedramcore_roundrobin0_request;
-wire          litedramcore_roundrobin0_grant;
-wire          litedramcore_roundrobin0_ce;
-wire          litedramcore_roundrobin1_request;
-wire          litedramcore_roundrobin1_grant;
-wire          litedramcore_roundrobin1_ce;
-wire          litedramcore_roundrobin2_request;
-wire          litedramcore_roundrobin2_grant;
-wire          litedramcore_roundrobin2_ce;
-wire          litedramcore_roundrobin3_request;
-wire          litedramcore_roundrobin3_grant;
-wire          litedramcore_roundrobin3_ce;
-wire          litedramcore_roundrobin4_request;
-wire          litedramcore_roundrobin4_grant;
-wire          litedramcore_roundrobin4_ce;
-wire          litedramcore_roundrobin5_request;
-wire          litedramcore_roundrobin5_grant;
-wire          litedramcore_roundrobin5_ce;
-wire          litedramcore_roundrobin6_request;
-wire          litedramcore_roundrobin6_grant;
-wire          litedramcore_roundrobin6_ce;
-wire          litedramcore_roundrobin7_request;
-wire          litedramcore_roundrobin7_grant;
-wire          litedramcore_roundrobin7_ce;
-reg           litedramcore_locked0 = 1'd0;
-reg           litedramcore_locked1 = 1'd0;
-reg           litedramcore_locked2 = 1'd0;
-reg           litedramcore_locked3 = 1'd0;
-reg           litedramcore_locked4 = 1'd0;
-reg           litedramcore_locked5 = 1'd0;
-reg           litedramcore_locked6 = 1'd0;
-reg           litedramcore_locked7 = 1'd0;
-reg           litedramcore_new_master_wdata_ready0 = 1'd0;
-reg           litedramcore_new_master_wdata_ready1 = 1'd0;
-reg           litedramcore_new_master_rdata_valid0 = 1'd0;
-reg           litedramcore_new_master_rdata_valid1 = 1'd0;
-reg           litedramcore_new_master_rdata_valid2 = 1'd0;
-reg           litedramcore_new_master_rdata_valid3 = 1'd0;
-reg           litedramcore_new_master_rdata_valid4 = 1'd0;
-reg           litedramcore_new_master_rdata_valid5 = 1'd0;
-reg           litedramcore_new_master_rdata_valid6 = 1'd0;
-reg           litedramcore_new_master_rdata_valid7 = 1'd0;
-reg           litedramcore_new_master_rdata_valid8 = 1'd0;
-reg     [1:0] litedramcore_state = 2'd0;
-reg     [1:0] litedramcore_next_state = 2'd0;
-reg    [31:0] litedramcore_dat_w_next_value0 = 32'd0;
-reg           litedramcore_dat_w_next_value_ce0 = 1'd0;
-reg    [13:0] litedramcore_adr_next_value1 = 14'd0;
-reg           litedramcore_adr_next_value_ce1 = 1'd0;
-reg           litedramcore_we_next_value2 = 1'd0;
-reg           litedramcore_we_next_value_ce2 = 1'd0;
-reg           rhs_array_muxed0 = 1'd0;
-reg    [13:0] rhs_array_muxed1 = 14'd0;
-reg     [2:0] rhs_array_muxed2 = 3'd0;
-reg           rhs_array_muxed3 = 1'd0;
-reg           rhs_array_muxed4 = 1'd0;
-reg           rhs_array_muxed5 = 1'd0;
-reg           t_array_muxed0 = 1'd0;
-reg           t_array_muxed1 = 1'd0;
-reg           t_array_muxed2 = 1'd0;
-reg           rhs_array_muxed6 = 1'd0;
-reg    [13:0] rhs_array_muxed7 = 14'd0;
-reg     [2:0] rhs_array_muxed8 = 3'd0;
-reg           rhs_array_muxed9 = 1'd0;
-reg           rhs_array_muxed10 = 1'd0;
-reg           rhs_array_muxed11 = 1'd0;
-reg           t_array_muxed3 = 1'd0;
-reg           t_array_muxed4 = 1'd0;
-reg           t_array_muxed5 = 1'd0;
-reg    [20:0] rhs_array_muxed12 = 21'd0;
-reg           rhs_array_muxed13 = 1'd0;
-reg           rhs_array_muxed14 = 1'd0;
-reg    [20:0] rhs_array_muxed15 = 21'd0;
-reg           rhs_array_muxed16 = 1'd0;
-reg           rhs_array_muxed17 = 1'd0;
-reg    [20:0] rhs_array_muxed18 = 21'd0;
-reg           rhs_array_muxed19 = 1'd0;
-reg           rhs_array_muxed20 = 1'd0;
-reg    [20:0] rhs_array_muxed21 = 21'd0;
-reg           rhs_array_muxed22 = 1'd0;
-reg           rhs_array_muxed23 = 1'd0;
-reg    [20:0] rhs_array_muxed24 = 21'd0;
-reg           rhs_array_muxed25 = 1'd0;
-reg           rhs_array_muxed26 = 1'd0;
-reg    [20:0] rhs_array_muxed27 = 21'd0;
-reg           rhs_array_muxed28 = 1'd0;
-reg           rhs_array_muxed29 = 1'd0;
-reg    [20:0] rhs_array_muxed30 = 21'd0;
-reg           rhs_array_muxed31 = 1'd0;
-reg           rhs_array_muxed32 = 1'd0;
-reg    [20:0] rhs_array_muxed33 = 21'd0;
-reg           rhs_array_muxed34 = 1'd0;
-reg           rhs_array_muxed35 = 1'd0;
-reg     [2:0] array_muxed0 = 3'd0;
-reg    [13:0] array_muxed1 = 14'd0;
-reg           array_muxed2 = 1'd0;
-reg           array_muxed3 = 1'd0;
-reg           array_muxed4 = 1'd0;
-reg           array_muxed5 = 1'd0;
-reg           array_muxed6 = 1'd0;
-reg     [2:0] array_muxed7 = 3'd0;
-reg    [13:0] array_muxed8 = 14'd0;
-reg           array_muxed9 = 1'd0;
-reg           array_muxed10 = 1'd0;
-reg           array_muxed11 = 1'd0;
-reg           array_muxed12 = 1'd0;
-reg           array_muxed13 = 1'd0;
-reg     [2:0] array_muxed14 = 3'd0;
-reg    [13:0] array_muxed15 = 14'd0;
-reg           array_muxed16 = 1'd0;
-reg           array_muxed17 = 1'd0;
-reg           array_muxed18 = 1'd0;
-reg           array_muxed19 = 1'd0;
-reg           array_muxed20 = 1'd0;
-reg     [2:0] array_muxed21 = 3'd0;
-reg    [13:0] array_muxed22 = 14'd0;
-reg           array_muxed23 = 1'd0;
-reg           array_muxed24 = 1'd0;
-reg           array_muxed25 = 1'd0;
-reg           array_muxed26 = 1'd0;
-reg           array_muxed27 = 1'd0;
-wire          xilinxasyncresetsynchronizerimpl0;
-wire          xilinxasyncresetsynchronizerimpl0_rst_meta;
-wire          xilinxasyncresetsynchronizerimpl1;
-wire          xilinxasyncresetsynchronizerimpl1_rst_meta;
-wire          xilinxasyncresetsynchronizerimpl2;
-wire          xilinxasyncresetsynchronizerimpl2_rst_meta;
-wire          xilinxasyncresetsynchronizerimpl2_expr;
-wire          xilinxasyncresetsynchronizerimpl3;
-wire          xilinxasyncresetsynchronizerimpl3_rst_meta;
-wire          xilinxasyncresetsynchronizerimpl3_expr;
+reg           main_litedramcore_twtrcon_ready = 1'd0;
+wire          main_litedramcore_twtrcon_valid;
+wire          main_litedramcore_wants_refresh;
+wire          main_litedramcore_wants_zqcs;
+wire          main_litedramcore_write_available;
+reg           main_litedramcore_zqcs_executer_done = 1'd0;
+reg           main_litedramcore_zqcs_executer_start = 1'd0;
+reg     [4:0] main_litedramcore_zqcs_executer_trigger = 5'd0;
+wire   [26:0] main_litedramcore_zqcs_timer_count0;
+reg    [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999;
+wire          main_litedramcore_zqcs_timer_done0;
+wire          main_litedramcore_zqcs_timer_done1;
+wire          main_litedramcore_zqcs_timer_wait;
+wire          main_locked;
+reg           main_power_down = 1'd0;
+wire          main_reset;
+reg     [3:0] main_reset_counter = 4'd15;
+reg           main_rst = 1'd0;
+wire          main_user_enable;
+wire   [23:0] main_user_port_cmd_payload_addr;
+wire          main_user_port_cmd_payload_we;
+wire          main_user_port_cmd_ready;
+wire          main_user_port_cmd_valid;
+wire  [127:0] main_user_port_rdata_payload_data;
+wire          main_user_port_rdata_ready;
+wire          main_user_port_rdata_valid;
+wire  [127:0] main_user_port_wdata_payload_data;
+wire   [15:0] main_user_port_wdata_payload_we;
+wire          main_user_port_wdata_ready;
+wire          main_user_port_wdata_valid;
+wire          main_wb_bus_ack;
+wire   [29:0] main_wb_bus_adr;
+wire    [1:0] main_wb_bus_bte;
+wire    [2:0] main_wb_bus_cti;
+wire          main_wb_bus_cyc;
+wire   [31:0] main_wb_bus_dat_r;
+wire   [31:0] main_wb_bus_dat_w;
+wire          main_wb_bus_err;
+wire    [3:0] main_wb_bus_sel;
+wire          main_wb_bus_stb;
+wire          main_wb_bus_we;
+wire          sys4x_clk;
+wire          sys4x_dqs_clk;
+wire          sys_clk;
+wire          sys_rst;
 
 //------------------------------------------------------------------------------
 // Combinatorial Logic
 //------------------------------------------------------------------------------
 
-assign init_done = init_done_storage;
-assign init_error = init_error_storage;
-assign wb_bus_adr = wb_ctrl_adr;
-assign wb_bus_dat_w = wb_ctrl_dat_w;
-assign wb_ctrl_dat_r = wb_bus_dat_r;
-assign wb_bus_sel = wb_ctrl_sel;
-assign wb_bus_cyc = wb_ctrl_cyc;
-assign wb_bus_stb = wb_ctrl_stb;
-assign wb_ctrl_ack = wb_bus_ack;
-assign wb_bus_we = wb_ctrl_we;
-assign wb_bus_cti = wb_ctrl_cti;
-assign wb_bus_bte = wb_ctrl_bte;
-assign wb_ctrl_err = wb_bus_err;
+assign init_done = main_init_done_storage;
+assign init_error = main_init_error_storage;
+assign main_wb_bus_adr = wb_ctrl_adr;
+assign main_wb_bus_dat_w = wb_ctrl_dat_w;
+assign wb_ctrl_dat_r = main_wb_bus_dat_r;
+assign main_wb_bus_sel = wb_ctrl_sel;
+assign main_wb_bus_cyc = wb_ctrl_cyc;
+assign main_wb_bus_stb = wb_ctrl_stb;
+assign wb_ctrl_ack = main_wb_bus_ack;
+assign main_wb_bus_we = wb_ctrl_we;
+assign main_wb_bus_cti = wb_ctrl_cti;
+assign main_wb_bus_bte = wb_ctrl_bte;
+assign wb_ctrl_err = main_wb_bus_err;
 assign user_clk = sys_clk;
 assign user_rst = sys_rst;
-assign user_enable = 1'd1;
-assign user_port_cmd_valid = (user_port_native_0_cmd_valid & user_enable);
-assign user_port_native_0_cmd_ready = (user_port_cmd_ready & user_enable);
-assign user_port_cmd_payload_we = user_port_native_0_cmd_we;
-assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
-assign user_port_wdata_valid = (user_port_native_0_wdata_valid & user_enable);
-assign user_port_native_0_wdata_ready = (user_port_wdata_ready & user_enable);
-assign user_port_wdata_payload_we = user_port_native_0_wdata_we;
-assign user_port_wdata_payload_data = user_port_native_0_wdata_data;
-assign user_port_native_0_rdata_valid = (user_port_rdata_valid & user_enable);
-assign user_port_rdata_ready = (user_port_native_0_rdata_ready & user_enable);
-assign user_port_native_0_rdata_data = user_port_rdata_payload_data;
-assign reset = (rst | rst_1);
-assign pll_locked = locked;
-assign clkin = clk;
-assign iodelay_clk = clkout_buf0;
-assign sys_clk = clkout_buf1;
-assign sys4x_clk = clkout_buf2;
-assign sys4x_dqs_clk = clkout_buf3;
-assign ddram_ba = a7ddrphy_pads_ba;
-assign a7ddrphy_dqs_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dqs_oe) | a7ddrphy_dqs_postamble);
-assign a7ddrphy_dq_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dq_oe) | a7ddrphy_dqs_postamble);
-always @(*) begin
-    a7ddrphy_dfi_p0_rddata <= 32'd0;
-    a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0];
-    a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1];
-    a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0];
-    a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1];
-    a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0];
-    a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1];
-    a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0];
-    a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1];
-    a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0];
-    a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1];
-    a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0];
-    a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1];
-    a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0];
-    a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1];
-    a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0];
-    a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1];
-    a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0];
-    a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1];
-    a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0];
-    a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1];
-    a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0];
-    a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1];
-    a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0];
-    a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1];
-    a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0];
-    a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1];
-    a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0];
-    a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1];
-    a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0];
-    a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1];
-    a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0];
-    a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1];
-end
-always @(*) begin
-    a7ddrphy_dfi_p1_rddata <= 32'd0;
-    a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2];
-    a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3];
-    a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2];
-    a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3];
-    a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2];
-    a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3];
-    a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2];
-    a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3];
-    a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2];
-    a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3];
-    a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2];
-    a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3];
-    a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2];
-    a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3];
-    a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2];
-    a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3];
-    a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2];
-    a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3];
-    a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2];
-    a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3];
-    a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2];
-    a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3];
-    a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2];
-    a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3];
-    a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2];
-    a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3];
-    a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2];
-    a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3];
-    a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2];
-    a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3];
-    a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2];
-    a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3];
-end
-always @(*) begin
-    a7ddrphy_dfi_p2_rddata <= 32'd0;
-    a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4];
-    a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5];
-    a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4];
-    a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5];
-    a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4];
-    a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5];
-    a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4];
-    a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5];
-    a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4];
-    a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5];
-    a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4];
-    a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5];
-    a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4];
-    a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5];
-    a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4];
-    a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5];
-    a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4];
-    a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5];
-    a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4];
-    a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5];
-    a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4];
-    a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5];
-    a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4];
-    a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5];
-    a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4];
-    a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5];
-    a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4];
-    a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5];
-    a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4];
-    a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5];
-    a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4];
-    a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5];
-end
-always @(*) begin
-    a7ddrphy_dfi_p3_rddata <= 32'd0;
-    a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6];
-    a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7];
-    a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6];
-    a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7];
-    a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6];
-    a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7];
-    a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6];
-    a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7];
-    a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6];
-    a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7];
-    a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6];
-    a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7];
-    a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6];
-    a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7];
-    a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6];
-    a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7];
-    a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6];
-    a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7];
-    a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6];
-    a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7];
-    a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6];
-    a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7];
-    a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6];
-    a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7];
-    a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6];
-    a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7];
-    a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6];
-    a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7];
-    a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6];
-    a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7];
-    a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6];
-    a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7];
-end
-assign a7ddrphy_dfi_p0_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
-assign a7ddrphy_dfi_p1_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
-assign a7ddrphy_dfi_p2_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
-assign a7ddrphy_dfi_p3_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
-assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en_tappeddelayline1;
-always @(*) begin
-    a7ddrphy_dqs_oe <= 1'd0;
-    if (a7ddrphy_wlevel_en_storage) begin
-        a7ddrphy_dqs_oe <= 1'd1;
-    end else begin
-        a7ddrphy_dqs_oe <= a7ddrphy_dq_oe;
-    end
-end
-assign a7ddrphy_dqs_preamble = (a7ddrphy_wrdata_en_tappeddelayline0 & (~a7ddrphy_wrdata_en_tappeddelayline1));
-assign a7ddrphy_dqs_postamble = (a7ddrphy_wrdata_en_tappeddelayline2 & (~a7ddrphy_wrdata_en_tappeddelayline1));
-always @(*) begin
-    a7ddrphy_dqspattern_o0 <= 8'd0;
-    a7ddrphy_dqspattern_o0 <= 7'd85;
-    if (a7ddrphy_dqspattern0) begin
-        a7ddrphy_dqspattern_o0 <= 5'd21;
-    end
-    if (a7ddrphy_dqspattern1) begin
-        a7ddrphy_dqspattern_o0 <= 7'd84;
-    end
-    if (a7ddrphy_wlevel_en_storage) begin
-        a7ddrphy_dqspattern_o0 <= 1'd0;
-        if (a7ddrphy_wlevel_strobe_re) begin
-            a7ddrphy_dqspattern_o0 <= 1'd1;
-        end
-    end
-end
-always @(*) begin
-    a7ddrphy_bitslip00 <= 8'd0;
-    case (a7ddrphy_bitslip0_value0)
+assign main_user_enable = 1'd1;
+assign main_user_port_cmd_valid = (user_port_native_0_cmd_valid & main_user_enable);
+assign user_port_native_0_cmd_ready = (main_user_port_cmd_ready & main_user_enable);
+assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we;
+assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
+assign main_user_port_wdata_valid = (user_port_native_0_wdata_valid & main_user_enable);
+assign user_port_native_0_wdata_ready = (main_user_port_wdata_ready & main_user_enable);
+assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we;
+assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data;
+assign user_port_native_0_rdata_valid = (main_user_port_rdata_valid & main_user_enable);
+assign main_user_port_rdata_ready = (user_port_native_0_rdata_ready & main_user_enable);
+assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data;
+assign builder_interface0_adr = main_wb_bus_adr;
+assign builder_interface0_dat_w = main_wb_bus_dat_w;
+assign main_wb_bus_dat_r = builder_interface0_dat_r;
+assign builder_interface0_sel = main_wb_bus_sel;
+assign builder_interface0_cyc = main_wb_bus_cyc;
+assign builder_interface0_stb = main_wb_bus_stb;
+assign main_wb_bus_ack = builder_interface0_ack;
+assign builder_interface0_we = main_wb_bus_we;
+assign builder_interface0_cti = main_wb_bus_cti;
+assign builder_interface0_bte = main_wb_bus_bte;
+assign main_wb_bus_err = builder_interface0_err;
+assign main_reset = (rst | main_rst);
+assign pll_locked = main_locked;
+assign main_clkin = clk;
+assign iodelay_clk = main_clkout_buf0;
+assign sys_clk = main_clkout_buf1;
+assign sys4x_clk = main_clkout_buf2;
+assign sys4x_dqs_clk = main_clkout_buf3;
+assign ddram_ba = main_a7ddrphy_pads_ba;
+assign main_a7ddrphy_dqs_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_oe) | main_a7ddrphy_dqs_postamble);
+assign main_a7ddrphy_dq_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dq_oe) | main_a7ddrphy_dqs_postamble);
+always @(*) begin
+    main_a7ddrphy_dfi_p0_rddata <= 32'd0;
+    main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip04[0];
+    main_a7ddrphy_dfi_p0_rddata[16] <= main_a7ddrphy_bitslip04[1];
+    main_a7ddrphy_dfi_p0_rddata[1] <= main_a7ddrphy_bitslip14[0];
+    main_a7ddrphy_dfi_p0_rddata[17] <= main_a7ddrphy_bitslip14[1];
+    main_a7ddrphy_dfi_p0_rddata[2] <= main_a7ddrphy_bitslip22[0];
+    main_a7ddrphy_dfi_p0_rddata[18] <= main_a7ddrphy_bitslip22[1];
+    main_a7ddrphy_dfi_p0_rddata[3] <= main_a7ddrphy_bitslip32[0];
+    main_a7ddrphy_dfi_p0_rddata[19] <= main_a7ddrphy_bitslip32[1];
+    main_a7ddrphy_dfi_p0_rddata[4] <= main_a7ddrphy_bitslip42[0];
+    main_a7ddrphy_dfi_p0_rddata[20] <= main_a7ddrphy_bitslip42[1];
+    main_a7ddrphy_dfi_p0_rddata[5] <= main_a7ddrphy_bitslip52[0];
+    main_a7ddrphy_dfi_p0_rddata[21] <= main_a7ddrphy_bitslip52[1];
+    main_a7ddrphy_dfi_p0_rddata[6] <= main_a7ddrphy_bitslip62[0];
+    main_a7ddrphy_dfi_p0_rddata[22] <= main_a7ddrphy_bitslip62[1];
+    main_a7ddrphy_dfi_p0_rddata[7] <= main_a7ddrphy_bitslip72[0];
+    main_a7ddrphy_dfi_p0_rddata[23] <= main_a7ddrphy_bitslip72[1];
+    main_a7ddrphy_dfi_p0_rddata[8] <= main_a7ddrphy_bitslip82[0];
+    main_a7ddrphy_dfi_p0_rddata[24] <= main_a7ddrphy_bitslip82[1];
+    main_a7ddrphy_dfi_p0_rddata[9] <= main_a7ddrphy_bitslip92[0];
+    main_a7ddrphy_dfi_p0_rddata[25] <= main_a7ddrphy_bitslip92[1];
+    main_a7ddrphy_dfi_p0_rddata[10] <= main_a7ddrphy_bitslip102[0];
+    main_a7ddrphy_dfi_p0_rddata[26] <= main_a7ddrphy_bitslip102[1];
+    main_a7ddrphy_dfi_p0_rddata[11] <= main_a7ddrphy_bitslip112[0];
+    main_a7ddrphy_dfi_p0_rddata[27] <= main_a7ddrphy_bitslip112[1];
+    main_a7ddrphy_dfi_p0_rddata[12] <= main_a7ddrphy_bitslip122[0];
+    main_a7ddrphy_dfi_p0_rddata[28] <= main_a7ddrphy_bitslip122[1];
+    main_a7ddrphy_dfi_p0_rddata[13] <= main_a7ddrphy_bitslip132[0];
+    main_a7ddrphy_dfi_p0_rddata[29] <= main_a7ddrphy_bitslip132[1];
+    main_a7ddrphy_dfi_p0_rddata[14] <= main_a7ddrphy_bitslip142[0];
+    main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip142[1];
+    main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip152[0];
+    main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip152[1];
+end
+always @(*) begin
+    main_a7ddrphy_dfi_p1_rddata <= 32'd0;
+    main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip04[2];
+    main_a7ddrphy_dfi_p1_rddata[16] <= main_a7ddrphy_bitslip04[3];
+    main_a7ddrphy_dfi_p1_rddata[1] <= main_a7ddrphy_bitslip14[2];
+    main_a7ddrphy_dfi_p1_rddata[17] <= main_a7ddrphy_bitslip14[3];
+    main_a7ddrphy_dfi_p1_rddata[2] <= main_a7ddrphy_bitslip22[2];
+    main_a7ddrphy_dfi_p1_rddata[18] <= main_a7ddrphy_bitslip22[3];
+    main_a7ddrphy_dfi_p1_rddata[3] <= main_a7ddrphy_bitslip32[2];
+    main_a7ddrphy_dfi_p1_rddata[19] <= main_a7ddrphy_bitslip32[3];
+    main_a7ddrphy_dfi_p1_rddata[4] <= main_a7ddrphy_bitslip42[2];
+    main_a7ddrphy_dfi_p1_rddata[20] <= main_a7ddrphy_bitslip42[3];
+    main_a7ddrphy_dfi_p1_rddata[5] <= main_a7ddrphy_bitslip52[2];
+    main_a7ddrphy_dfi_p1_rddata[21] <= main_a7ddrphy_bitslip52[3];
+    main_a7ddrphy_dfi_p1_rddata[6] <= main_a7ddrphy_bitslip62[2];
+    main_a7ddrphy_dfi_p1_rddata[22] <= main_a7ddrphy_bitslip62[3];
+    main_a7ddrphy_dfi_p1_rddata[7] <= main_a7ddrphy_bitslip72[2];
+    main_a7ddrphy_dfi_p1_rddata[23] <= main_a7ddrphy_bitslip72[3];
+    main_a7ddrphy_dfi_p1_rddata[8] <= main_a7ddrphy_bitslip82[2];
+    main_a7ddrphy_dfi_p1_rddata[24] <= main_a7ddrphy_bitslip82[3];
+    main_a7ddrphy_dfi_p1_rddata[9] <= main_a7ddrphy_bitslip92[2];
+    main_a7ddrphy_dfi_p1_rddata[25] <= main_a7ddrphy_bitslip92[3];
+    main_a7ddrphy_dfi_p1_rddata[10] <= main_a7ddrphy_bitslip102[2];
+    main_a7ddrphy_dfi_p1_rddata[26] <= main_a7ddrphy_bitslip102[3];
+    main_a7ddrphy_dfi_p1_rddata[11] <= main_a7ddrphy_bitslip112[2];
+    main_a7ddrphy_dfi_p1_rddata[27] <= main_a7ddrphy_bitslip112[3];
+    main_a7ddrphy_dfi_p1_rddata[12] <= main_a7ddrphy_bitslip122[2];
+    main_a7ddrphy_dfi_p1_rddata[28] <= main_a7ddrphy_bitslip122[3];
+    main_a7ddrphy_dfi_p1_rddata[13] <= main_a7ddrphy_bitslip132[2];
+    main_a7ddrphy_dfi_p1_rddata[29] <= main_a7ddrphy_bitslip132[3];
+    main_a7ddrphy_dfi_p1_rddata[14] <= main_a7ddrphy_bitslip142[2];
+    main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip142[3];
+    main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip152[2];
+    main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip152[3];
+end
+always @(*) begin
+    main_a7ddrphy_dfi_p2_rddata <= 32'd0;
+    main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip04[4];
+    main_a7ddrphy_dfi_p2_rddata[16] <= main_a7ddrphy_bitslip04[5];
+    main_a7ddrphy_dfi_p2_rddata[1] <= main_a7ddrphy_bitslip14[4];
+    main_a7ddrphy_dfi_p2_rddata[17] <= main_a7ddrphy_bitslip14[5];
+    main_a7ddrphy_dfi_p2_rddata[2] <= main_a7ddrphy_bitslip22[4];
+    main_a7ddrphy_dfi_p2_rddata[18] <= main_a7ddrphy_bitslip22[5];
+    main_a7ddrphy_dfi_p2_rddata[3] <= main_a7ddrphy_bitslip32[4];
+    main_a7ddrphy_dfi_p2_rddata[19] <= main_a7ddrphy_bitslip32[5];
+    main_a7ddrphy_dfi_p2_rddata[4] <= main_a7ddrphy_bitslip42[4];
+    main_a7ddrphy_dfi_p2_rddata[20] <= main_a7ddrphy_bitslip42[5];
+    main_a7ddrphy_dfi_p2_rddata[5] <= main_a7ddrphy_bitslip52[4];
+    main_a7ddrphy_dfi_p2_rddata[21] <= main_a7ddrphy_bitslip52[5];
+    main_a7ddrphy_dfi_p2_rddata[6] <= main_a7ddrphy_bitslip62[4];
+    main_a7ddrphy_dfi_p2_rddata[22] <= main_a7ddrphy_bitslip62[5];
+    main_a7ddrphy_dfi_p2_rddata[7] <= main_a7ddrphy_bitslip72[4];
+    main_a7ddrphy_dfi_p2_rddata[23] <= main_a7ddrphy_bitslip72[5];
+    main_a7ddrphy_dfi_p2_rddata[8] <= main_a7ddrphy_bitslip82[4];
+    main_a7ddrphy_dfi_p2_rddata[24] <= main_a7ddrphy_bitslip82[5];
+    main_a7ddrphy_dfi_p2_rddata[9] <= main_a7ddrphy_bitslip92[4];
+    main_a7ddrphy_dfi_p2_rddata[25] <= main_a7ddrphy_bitslip92[5];
+    main_a7ddrphy_dfi_p2_rddata[10] <= main_a7ddrphy_bitslip102[4];
+    main_a7ddrphy_dfi_p2_rddata[26] <= main_a7ddrphy_bitslip102[5];
+    main_a7ddrphy_dfi_p2_rddata[11] <= main_a7ddrphy_bitslip112[4];
+    main_a7ddrphy_dfi_p2_rddata[27] <= main_a7ddrphy_bitslip112[5];
+    main_a7ddrphy_dfi_p2_rddata[12] <= main_a7ddrphy_bitslip122[4];
+    main_a7ddrphy_dfi_p2_rddata[28] <= main_a7ddrphy_bitslip122[5];
+    main_a7ddrphy_dfi_p2_rddata[13] <= main_a7ddrphy_bitslip132[4];
+    main_a7ddrphy_dfi_p2_rddata[29] <= main_a7ddrphy_bitslip132[5];
+    main_a7ddrphy_dfi_p2_rddata[14] <= main_a7ddrphy_bitslip142[4];
+    main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip142[5];
+    main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip152[4];
+    main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip152[5];
+end
+always @(*) begin
+    main_a7ddrphy_dfi_p3_rddata <= 32'd0;
+    main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip04[6];
+    main_a7ddrphy_dfi_p3_rddata[16] <= main_a7ddrphy_bitslip04[7];
+    main_a7ddrphy_dfi_p3_rddata[1] <= main_a7ddrphy_bitslip14[6];
+    main_a7ddrphy_dfi_p3_rddata[17] <= main_a7ddrphy_bitslip14[7];
+    main_a7ddrphy_dfi_p3_rddata[2] <= main_a7ddrphy_bitslip22[6];
+    main_a7ddrphy_dfi_p3_rddata[18] <= main_a7ddrphy_bitslip22[7];
+    main_a7ddrphy_dfi_p3_rddata[3] <= main_a7ddrphy_bitslip32[6];
+    main_a7ddrphy_dfi_p3_rddata[19] <= main_a7ddrphy_bitslip32[7];
+    main_a7ddrphy_dfi_p3_rddata[4] <= main_a7ddrphy_bitslip42[6];
+    main_a7ddrphy_dfi_p3_rddata[20] <= main_a7ddrphy_bitslip42[7];
+    main_a7ddrphy_dfi_p3_rddata[5] <= main_a7ddrphy_bitslip52[6];
+    main_a7ddrphy_dfi_p3_rddata[21] <= main_a7ddrphy_bitslip52[7];
+    main_a7ddrphy_dfi_p3_rddata[6] <= main_a7ddrphy_bitslip62[6];
+    main_a7ddrphy_dfi_p3_rddata[22] <= main_a7ddrphy_bitslip62[7];
+    main_a7ddrphy_dfi_p3_rddata[7] <= main_a7ddrphy_bitslip72[6];
+    main_a7ddrphy_dfi_p3_rddata[23] <= main_a7ddrphy_bitslip72[7];
+    main_a7ddrphy_dfi_p3_rddata[8] <= main_a7ddrphy_bitslip82[6];
+    main_a7ddrphy_dfi_p3_rddata[24] <= main_a7ddrphy_bitslip82[7];
+    main_a7ddrphy_dfi_p3_rddata[9] <= main_a7ddrphy_bitslip92[6];
+    main_a7ddrphy_dfi_p3_rddata[25] <= main_a7ddrphy_bitslip92[7];
+    main_a7ddrphy_dfi_p3_rddata[10] <= main_a7ddrphy_bitslip102[6];
+    main_a7ddrphy_dfi_p3_rddata[26] <= main_a7ddrphy_bitslip102[7];
+    main_a7ddrphy_dfi_p3_rddata[11] <= main_a7ddrphy_bitslip112[6];
+    main_a7ddrphy_dfi_p3_rddata[27] <= main_a7ddrphy_bitslip112[7];
+    main_a7ddrphy_dfi_p3_rddata[12] <= main_a7ddrphy_bitslip122[6];
+    main_a7ddrphy_dfi_p3_rddata[28] <= main_a7ddrphy_bitslip122[7];
+    main_a7ddrphy_dfi_p3_rddata[13] <= main_a7ddrphy_bitslip132[6];
+    main_a7ddrphy_dfi_p3_rddata[29] <= main_a7ddrphy_bitslip132[7];
+    main_a7ddrphy_dfi_p3_rddata[14] <= main_a7ddrphy_bitslip142[6];
+    main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip142[7];
+    main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip152[6];
+    main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip152[7];
+end
+assign main_a7ddrphy_dfi_p0_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
+assign main_a7ddrphy_dfi_p1_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
+assign main_a7ddrphy_dfi_p2_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
+assign main_a7ddrphy_dfi_p3_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
+assign main_a7ddrphy_dq_oe = main_a7ddrphy_wrdata_en_tappeddelayline1;
+always @(*) begin
+    main_a7ddrphy_dqs_oe <= 1'd0;
+    if (main_a7ddrphy_wlevel_en_storage) begin
+        main_a7ddrphy_dqs_oe <= 1'd1;
+    end else begin
+        main_a7ddrphy_dqs_oe <= main_a7ddrphy_dq_oe;
+    end
+end
+assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_wrdata_en_tappeddelayline0 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
+assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_wrdata_en_tappeddelayline2 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
+always @(*) begin
+    main_a7ddrphy_dqspattern_o0 <= 8'd0;
+    main_a7ddrphy_dqspattern_o0 <= 7'd85;
+    if (main_a7ddrphy_dqspattern0) begin
+        main_a7ddrphy_dqspattern_o0 <= 5'd21;
+    end
+    if (main_a7ddrphy_dqspattern1) begin
+        main_a7ddrphy_dqspattern_o0 <= 7'd84;
+    end
+    if (main_a7ddrphy_wlevel_en_storage) begin
+        main_a7ddrphy_dqspattern_o0 <= 1'd0;
+        if (main_a7ddrphy_wlevel_strobe_re) begin
+            main_a7ddrphy_dqspattern_o0 <= 1'd1;
+        end
+    end
+end
+always @(*) begin
+    main_a7ddrphy_bitslip00 <= 8'd0;
+    case (main_a7ddrphy_bitslip0_value0)
         1'd0: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip10 <= 8'd0;
-    case (a7ddrphy_bitslip1_value0)
+    main_a7ddrphy_bitslip10 <= 8'd0;
+    case (main_a7ddrphy_bitslip1_value0)
         1'd0: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip01 <= 8'd0;
-    case (a7ddrphy_bitslip0_value1)
+    main_a7ddrphy_bitslip01 <= 8'd0;
+    case (main_a7ddrphy_bitslip0_value1)
         1'd0: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip11 <= 8'd0;
-    case (a7ddrphy_bitslip1_value1)
+    main_a7ddrphy_bitslip11 <= 8'd0;
+    case (main_a7ddrphy_bitslip1_value1)
         1'd0: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip02 <= 8'd0;
-    case (a7ddrphy_bitslip0_value2)
+    main_a7ddrphy_bitslip02 <= 8'd0;
+    case (main_a7ddrphy_bitslip0_value2)
         1'd0: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip04 <= 8'd0;
-    case (a7ddrphy_bitslip0_value3)
+    main_a7ddrphy_bitslip04 <= 8'd0;
+    case (main_a7ddrphy_bitslip0_value3)
         1'd0: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip12 <= 8'd0;
-    case (a7ddrphy_bitslip1_value2)
+    main_a7ddrphy_bitslip12 <= 8'd0;
+    case (main_a7ddrphy_bitslip1_value2)
         1'd0: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip14 <= 8'd0;
-    case (a7ddrphy_bitslip1_value3)
+    main_a7ddrphy_bitslip14 <= 8'd0;
+    case (main_a7ddrphy_bitslip1_value3)
         1'd0: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip20 <= 8'd0;
-    case (a7ddrphy_bitslip2_value0)
+    main_a7ddrphy_bitslip20 <= 8'd0;
+    case (main_a7ddrphy_bitslip2_value0)
         1'd0: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip22 <= 8'd0;
-    case (a7ddrphy_bitslip2_value1)
+    main_a7ddrphy_bitslip22 <= 8'd0;
+    case (main_a7ddrphy_bitslip2_value1)
         1'd0: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip30 <= 8'd0;
-    case (a7ddrphy_bitslip3_value0)
+    main_a7ddrphy_bitslip30 <= 8'd0;
+    case (main_a7ddrphy_bitslip3_value0)
         1'd0: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip32 <= 8'd0;
-    case (a7ddrphy_bitslip3_value1)
+    main_a7ddrphy_bitslip32 <= 8'd0;
+    case (main_a7ddrphy_bitslip3_value1)
         1'd0: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip40 <= 8'd0;
-    case (a7ddrphy_bitslip4_value0)
+    main_a7ddrphy_bitslip40 <= 8'd0;
+    case (main_a7ddrphy_bitslip4_value0)
         1'd0: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip42 <= 8'd0;
-    case (a7ddrphy_bitslip4_value1)
+    main_a7ddrphy_bitslip42 <= 8'd0;
+    case (main_a7ddrphy_bitslip4_value1)
         1'd0: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip50 <= 8'd0;
-    case (a7ddrphy_bitslip5_value0)
+    main_a7ddrphy_bitslip50 <= 8'd0;
+    case (main_a7ddrphy_bitslip5_value0)
         1'd0: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip52 <= 8'd0;
-    case (a7ddrphy_bitslip5_value1)
+    main_a7ddrphy_bitslip52 <= 8'd0;
+    case (main_a7ddrphy_bitslip5_value1)
         1'd0: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip60 <= 8'd0;
-    case (a7ddrphy_bitslip6_value0)
+    main_a7ddrphy_bitslip60 <= 8'd0;
+    case (main_a7ddrphy_bitslip6_value0)
         1'd0: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip62 <= 8'd0;
-    case (a7ddrphy_bitslip6_value1)
+    main_a7ddrphy_bitslip62 <= 8'd0;
+    case (main_a7ddrphy_bitslip6_value1)
         1'd0: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip70 <= 8'd0;
-    case (a7ddrphy_bitslip7_value0)
+    main_a7ddrphy_bitslip70 <= 8'd0;
+    case (main_a7ddrphy_bitslip7_value0)
         1'd0: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip72 <= 8'd0;
-    case (a7ddrphy_bitslip7_value1)
+    main_a7ddrphy_bitslip72 <= 8'd0;
+    case (main_a7ddrphy_bitslip7_value1)
         1'd0: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip80 <= 8'd0;
-    case (a7ddrphy_bitslip8_value0)
+    main_a7ddrphy_bitslip80 <= 8'd0;
+    case (main_a7ddrphy_bitslip8_value0)
         1'd0: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip82 <= 8'd0;
-    case (a7ddrphy_bitslip8_value1)
+    main_a7ddrphy_bitslip82 <= 8'd0;
+    case (main_a7ddrphy_bitslip8_value1)
         1'd0: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip90 <= 8'd0;
-    case (a7ddrphy_bitslip9_value0)
+    main_a7ddrphy_bitslip90 <= 8'd0;
+    case (main_a7ddrphy_bitslip9_value0)
         1'd0: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip92 <= 8'd0;
-    case (a7ddrphy_bitslip9_value1)
+    main_a7ddrphy_bitslip92 <= 8'd0;
+    case (main_a7ddrphy_bitslip9_value1)
         1'd0: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip100 <= 8'd0;
-    case (a7ddrphy_bitslip10_value0)
+    main_a7ddrphy_bitslip100 <= 8'd0;
+    case (main_a7ddrphy_bitslip10_value0)
         1'd0: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip102 <= 8'd0;
-    case (a7ddrphy_bitslip10_value1)
+    main_a7ddrphy_bitslip102 <= 8'd0;
+    case (main_a7ddrphy_bitslip10_value1)
         1'd0: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip110 <= 8'd0;
-    case (a7ddrphy_bitslip11_value0)
+    main_a7ddrphy_bitslip110 <= 8'd0;
+    case (main_a7ddrphy_bitslip11_value0)
         1'd0: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip112 <= 8'd0;
-    case (a7ddrphy_bitslip11_value1)
+    main_a7ddrphy_bitslip112 <= 8'd0;
+    case (main_a7ddrphy_bitslip11_value1)
         1'd0: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip120 <= 8'd0;
-    case (a7ddrphy_bitslip12_value0)
+    main_a7ddrphy_bitslip120 <= 8'd0;
+    case (main_a7ddrphy_bitslip12_value0)
         1'd0: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip122 <= 8'd0;
-    case (a7ddrphy_bitslip12_value1)
+    main_a7ddrphy_bitslip122 <= 8'd0;
+    case (main_a7ddrphy_bitslip12_value1)
         1'd0: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip130 <= 8'd0;
-    case (a7ddrphy_bitslip13_value0)
+    main_a7ddrphy_bitslip130 <= 8'd0;
+    case (main_a7ddrphy_bitslip13_value0)
         1'd0: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip132 <= 8'd0;
-    case (a7ddrphy_bitslip13_value1)
+    main_a7ddrphy_bitslip132 <= 8'd0;
+    case (main_a7ddrphy_bitslip13_value1)
         1'd0: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip140 <= 8'd0;
-    case (a7ddrphy_bitslip14_value0)
+    main_a7ddrphy_bitslip140 <= 8'd0;
+    case (main_a7ddrphy_bitslip14_value0)
         1'd0: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip142 <= 8'd0;
-    case (a7ddrphy_bitslip14_value1)
+    main_a7ddrphy_bitslip142 <= 8'd0;
+    case (main_a7ddrphy_bitslip14_value1)
         1'd0: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip150 <= 8'd0;
-    case (a7ddrphy_bitslip15_value0)
+    main_a7ddrphy_bitslip150 <= 8'd0;
+    case (main_a7ddrphy_bitslip15_value0)
         1'd0: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip152 <= 8'd0;
-    case (a7ddrphy_bitslip15_value1)
+    main_a7ddrphy_bitslip152 <= 8'd0;
+    case (main_a7ddrphy_bitslip15_value1)
         1'd0: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1];
-        end
-        1'd1: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2];
-        end
-        2'd2: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3];
-        end
-        2'd3: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4];
-        end
-        3'd4: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5];
-        end
-        3'd5: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6];
-        end
-        3'd6: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7];
-        end
-        3'd7: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8];
-        end
-    endcase
-end
-assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address;
-assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
-assign a7ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n;
-assign a7ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n;
-assign a7ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n;
-assign a7ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n;
-assign a7ddrphy_dfi_p0_cke = litedramcore_master_p0_cke;
-assign a7ddrphy_dfi_p0_odt = litedramcore_master_p0_odt;
-assign a7ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n;
-assign a7ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n;
-assign a7ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata;
-assign a7ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en;
-assign a7ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask;
-assign a7ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en;
-assign litedramcore_master_p0_rddata = a7ddrphy_dfi_p0_rddata;
-assign litedramcore_master_p0_rddata_valid = a7ddrphy_dfi_p0_rddata_valid;
-assign a7ddrphy_dfi_p1_address = litedramcore_master_p1_address;
-assign a7ddrphy_dfi_p1_bank = litedramcore_master_p1_bank;
-assign a7ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n;
-assign a7ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n;
-assign a7ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n;
-assign a7ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n;
-assign a7ddrphy_dfi_p1_cke = litedramcore_master_p1_cke;
-assign a7ddrphy_dfi_p1_odt = litedramcore_master_p1_odt;
-assign a7ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n;
-assign a7ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n;
-assign a7ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata;
-assign a7ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en;
-assign a7ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask;
-assign a7ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en;
-assign litedramcore_master_p1_rddata = a7ddrphy_dfi_p1_rddata;
-assign litedramcore_master_p1_rddata_valid = a7ddrphy_dfi_p1_rddata_valid;
-assign a7ddrphy_dfi_p2_address = litedramcore_master_p2_address;
-assign a7ddrphy_dfi_p2_bank = litedramcore_master_p2_bank;
-assign a7ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n;
-assign a7ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n;
-assign a7ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n;
-assign a7ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n;
-assign a7ddrphy_dfi_p2_cke = litedramcore_master_p2_cke;
-assign a7ddrphy_dfi_p2_odt = litedramcore_master_p2_odt;
-assign a7ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n;
-assign a7ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n;
-assign a7ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata;
-assign a7ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en;
-assign a7ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask;
-assign a7ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en;
-assign litedramcore_master_p2_rddata = a7ddrphy_dfi_p2_rddata;
-assign litedramcore_master_p2_rddata_valid = a7ddrphy_dfi_p2_rddata_valid;
-assign a7ddrphy_dfi_p3_address = litedramcore_master_p3_address;
-assign a7ddrphy_dfi_p3_bank = litedramcore_master_p3_bank;
-assign a7ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n;
-assign a7ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n;
-assign a7ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n;
-assign a7ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n;
-assign a7ddrphy_dfi_p3_cke = litedramcore_master_p3_cke;
-assign a7ddrphy_dfi_p3_odt = litedramcore_master_p3_odt;
-assign a7ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n;
-assign a7ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n;
-assign a7ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata;
-assign a7ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en;
-assign a7ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask;
-assign a7ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en;
-assign litedramcore_master_p3_rddata = a7ddrphy_dfi_p3_rddata;
-assign litedramcore_master_p3_rddata_valid = a7ddrphy_dfi_p3_rddata_valid;
-assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address;
-assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank;
-assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n;
-assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n;
-assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n;
-assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n;
-assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke;
-assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt;
-assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n;
-assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n;
-assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata;
-assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en;
-assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask;
-assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en;
-assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata;
-assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid;
-assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address;
-assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank;
-assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n;
-assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n;
-assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n;
-assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n;
-assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke;
-assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt;
-assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n;
-assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n;
-assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata;
-assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en;
-assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask;
-assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en;
-assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata;
-assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid;
-assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address;
-assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank;
-assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n;
-assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n;
-assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n;
-assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n;
-assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke;
-assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt;
-assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n;
-assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n;
-assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata;
-assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en;
-assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask;
-assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en;
-assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata;
-assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid;
-assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address;
-assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank;
-assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n;
-assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n;
-assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n;
-assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n;
-assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke;
-assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt;
-assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n;
-assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n;
-assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata;
-assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en;
-assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask;
-assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en;
-assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
-assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;
-always @(*) begin
-    litedramcore_csr_dfi_p0_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-    end else begin
-        litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata;
-    end
-end
-always @(*) begin
-    litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-    end else begin
-        litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
-    end
-end
-always @(*) begin
-    litedramcore_csr_dfi_p1_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-    end else begin
-        litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
-    end
-end
-always @(*) begin
-    litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-    end else begin
-        litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[8:1];
+        end
+        1'd1: begin
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[9:2];
+        end
+        2'd2: begin
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[10:3];
+        end
+        2'd3: begin
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[11:4];
+        end
+        3'd4: begin
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[12:5];
+        end
+        3'd5: begin
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[13:6];
+        end
+        3'd6: begin
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[14:7];
+        end
+        3'd7: begin
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[15:8];
+        end
+    endcase
+end
+assign main_a7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address;
+assign main_a7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank;
+assign main_a7ddrphy_dfi_p0_cas_n = main_litedramcore_master_p0_cas_n;
+assign main_a7ddrphy_dfi_p0_cs_n = main_litedramcore_master_p0_cs_n;
+assign main_a7ddrphy_dfi_p0_ras_n = main_litedramcore_master_p0_ras_n;
+assign main_a7ddrphy_dfi_p0_we_n = main_litedramcore_master_p0_we_n;
+assign main_a7ddrphy_dfi_p0_cke = main_litedramcore_master_p0_cke;
+assign main_a7ddrphy_dfi_p0_odt = main_litedramcore_master_p0_odt;
+assign main_a7ddrphy_dfi_p0_reset_n = main_litedramcore_master_p0_reset_n;
+assign main_a7ddrphy_dfi_p0_act_n = main_litedramcore_master_p0_act_n;
+assign main_a7ddrphy_dfi_p0_wrdata = main_litedramcore_master_p0_wrdata;
+assign main_a7ddrphy_dfi_p0_wrdata_en = main_litedramcore_master_p0_wrdata_en;
+assign main_a7ddrphy_dfi_p0_wrdata_mask = main_litedramcore_master_p0_wrdata_mask;
+assign main_a7ddrphy_dfi_p0_rddata_en = main_litedramcore_master_p0_rddata_en;
+assign main_litedramcore_master_p0_rddata = main_a7ddrphy_dfi_p0_rddata;
+assign main_litedramcore_master_p0_rddata_valid = main_a7ddrphy_dfi_p0_rddata_valid;
+assign main_a7ddrphy_dfi_p1_address = main_litedramcore_master_p1_address;
+assign main_a7ddrphy_dfi_p1_bank = main_litedramcore_master_p1_bank;
+assign main_a7ddrphy_dfi_p1_cas_n = main_litedramcore_master_p1_cas_n;
+assign main_a7ddrphy_dfi_p1_cs_n = main_litedramcore_master_p1_cs_n;
+assign main_a7ddrphy_dfi_p1_ras_n = main_litedramcore_master_p1_ras_n;
+assign main_a7ddrphy_dfi_p1_we_n = main_litedramcore_master_p1_we_n;
+assign main_a7ddrphy_dfi_p1_cke = main_litedramcore_master_p1_cke;
+assign main_a7ddrphy_dfi_p1_odt = main_litedramcore_master_p1_odt;
+assign main_a7ddrphy_dfi_p1_reset_n = main_litedramcore_master_p1_reset_n;
+assign main_a7ddrphy_dfi_p1_act_n = main_litedramcore_master_p1_act_n;
+assign main_a7ddrphy_dfi_p1_wrdata = main_litedramcore_master_p1_wrdata;
+assign main_a7ddrphy_dfi_p1_wrdata_en = main_litedramcore_master_p1_wrdata_en;
+assign main_a7ddrphy_dfi_p1_wrdata_mask = main_litedramcore_master_p1_wrdata_mask;
+assign main_a7ddrphy_dfi_p1_rddata_en = main_litedramcore_master_p1_rddata_en;
+assign main_litedramcore_master_p1_rddata = main_a7ddrphy_dfi_p1_rddata;
+assign main_litedramcore_master_p1_rddata_valid = main_a7ddrphy_dfi_p1_rddata_valid;
+assign main_a7ddrphy_dfi_p2_address = main_litedramcore_master_p2_address;
+assign main_a7ddrphy_dfi_p2_bank = main_litedramcore_master_p2_bank;
+assign main_a7ddrphy_dfi_p2_cas_n = main_litedramcore_master_p2_cas_n;
+assign main_a7ddrphy_dfi_p2_cs_n = main_litedramcore_master_p2_cs_n;
+assign main_a7ddrphy_dfi_p2_ras_n = main_litedramcore_master_p2_ras_n;
+assign main_a7ddrphy_dfi_p2_we_n = main_litedramcore_master_p2_we_n;
+assign main_a7ddrphy_dfi_p2_cke = main_litedramcore_master_p2_cke;
+assign main_a7ddrphy_dfi_p2_odt = main_litedramcore_master_p2_odt;
+assign main_a7ddrphy_dfi_p2_reset_n = main_litedramcore_master_p2_reset_n;
+assign main_a7ddrphy_dfi_p2_act_n = main_litedramcore_master_p2_act_n;
+assign main_a7ddrphy_dfi_p2_wrdata = main_litedramcore_master_p2_wrdata;
+assign main_a7ddrphy_dfi_p2_wrdata_en = main_litedramcore_master_p2_wrdata_en;
+assign main_a7ddrphy_dfi_p2_wrdata_mask = main_litedramcore_master_p2_wrdata_mask;
+assign main_a7ddrphy_dfi_p2_rddata_en = main_litedramcore_master_p2_rddata_en;
+assign main_litedramcore_master_p2_rddata = main_a7ddrphy_dfi_p2_rddata;
+assign main_litedramcore_master_p2_rddata_valid = main_a7ddrphy_dfi_p2_rddata_valid;
+assign main_a7ddrphy_dfi_p3_address = main_litedramcore_master_p3_address;
+assign main_a7ddrphy_dfi_p3_bank = main_litedramcore_master_p3_bank;
+assign main_a7ddrphy_dfi_p3_cas_n = main_litedramcore_master_p3_cas_n;
+assign main_a7ddrphy_dfi_p3_cs_n = main_litedramcore_master_p3_cs_n;
+assign main_a7ddrphy_dfi_p3_ras_n = main_litedramcore_master_p3_ras_n;
+assign main_a7ddrphy_dfi_p3_we_n = main_litedramcore_master_p3_we_n;
+assign main_a7ddrphy_dfi_p3_cke = main_litedramcore_master_p3_cke;
+assign main_a7ddrphy_dfi_p3_odt = main_litedramcore_master_p3_odt;
+assign main_a7ddrphy_dfi_p3_reset_n = main_litedramcore_master_p3_reset_n;
+assign main_a7ddrphy_dfi_p3_act_n = main_litedramcore_master_p3_act_n;
+assign main_a7ddrphy_dfi_p3_wrdata = main_litedramcore_master_p3_wrdata;
+assign main_a7ddrphy_dfi_p3_wrdata_en = main_litedramcore_master_p3_wrdata_en;
+assign main_a7ddrphy_dfi_p3_wrdata_mask = main_litedramcore_master_p3_wrdata_mask;
+assign main_a7ddrphy_dfi_p3_rddata_en = main_litedramcore_master_p3_rddata_en;
+assign main_litedramcore_master_p3_rddata = main_a7ddrphy_dfi_p3_rddata;
+assign main_litedramcore_master_p3_rddata_valid = main_a7ddrphy_dfi_p3_rddata_valid;
+assign main_litedramcore_slave_p0_address = main_litedramcore_dfi_p0_address;
+assign main_litedramcore_slave_p0_bank = main_litedramcore_dfi_p0_bank;
+assign main_litedramcore_slave_p0_cas_n = main_litedramcore_dfi_p0_cas_n;
+assign main_litedramcore_slave_p0_cs_n = main_litedramcore_dfi_p0_cs_n;
+assign main_litedramcore_slave_p0_ras_n = main_litedramcore_dfi_p0_ras_n;
+assign main_litedramcore_slave_p0_we_n = main_litedramcore_dfi_p0_we_n;
+assign main_litedramcore_slave_p0_cke = main_litedramcore_dfi_p0_cke;
+assign main_litedramcore_slave_p0_odt = main_litedramcore_dfi_p0_odt;
+assign main_litedramcore_slave_p0_reset_n = main_litedramcore_dfi_p0_reset_n;
+assign main_litedramcore_slave_p0_act_n = main_litedramcore_dfi_p0_act_n;
+assign main_litedramcore_slave_p0_wrdata = main_litedramcore_dfi_p0_wrdata;
+assign main_litedramcore_slave_p0_wrdata_en = main_litedramcore_dfi_p0_wrdata_en;
+assign main_litedramcore_slave_p0_wrdata_mask = main_litedramcore_dfi_p0_wrdata_mask;
+assign main_litedramcore_slave_p0_rddata_en = main_litedramcore_dfi_p0_rddata_en;
+assign main_litedramcore_dfi_p0_rddata = main_litedramcore_slave_p0_rddata;
+assign main_litedramcore_dfi_p0_rddata_valid = main_litedramcore_slave_p0_rddata_valid;
+assign main_litedramcore_slave_p1_address = main_litedramcore_dfi_p1_address;
+assign main_litedramcore_slave_p1_bank = main_litedramcore_dfi_p1_bank;
+assign main_litedramcore_slave_p1_cas_n = main_litedramcore_dfi_p1_cas_n;
+assign main_litedramcore_slave_p1_cs_n = main_litedramcore_dfi_p1_cs_n;
+assign main_litedramcore_slave_p1_ras_n = main_litedramcore_dfi_p1_ras_n;
+assign main_litedramcore_slave_p1_we_n = main_litedramcore_dfi_p1_we_n;
+assign main_litedramcore_slave_p1_cke = main_litedramcore_dfi_p1_cke;
+assign main_litedramcore_slave_p1_odt = main_litedramcore_dfi_p1_odt;
+assign main_litedramcore_slave_p1_reset_n = main_litedramcore_dfi_p1_reset_n;
+assign main_litedramcore_slave_p1_act_n = main_litedramcore_dfi_p1_act_n;
+assign main_litedramcore_slave_p1_wrdata = main_litedramcore_dfi_p1_wrdata;
+assign main_litedramcore_slave_p1_wrdata_en = main_litedramcore_dfi_p1_wrdata_en;
+assign main_litedramcore_slave_p1_wrdata_mask = main_litedramcore_dfi_p1_wrdata_mask;
+assign main_litedramcore_slave_p1_rddata_en = main_litedramcore_dfi_p1_rddata_en;
+assign main_litedramcore_dfi_p1_rddata = main_litedramcore_slave_p1_rddata;
+assign main_litedramcore_dfi_p1_rddata_valid = main_litedramcore_slave_p1_rddata_valid;
+assign main_litedramcore_slave_p2_address = main_litedramcore_dfi_p2_address;
+assign main_litedramcore_slave_p2_bank = main_litedramcore_dfi_p2_bank;
+assign main_litedramcore_slave_p2_cas_n = main_litedramcore_dfi_p2_cas_n;
+assign main_litedramcore_slave_p2_cs_n = main_litedramcore_dfi_p2_cs_n;
+assign main_litedramcore_slave_p2_ras_n = main_litedramcore_dfi_p2_ras_n;
+assign main_litedramcore_slave_p2_we_n = main_litedramcore_dfi_p2_we_n;
+assign main_litedramcore_slave_p2_cke = main_litedramcore_dfi_p2_cke;
+assign main_litedramcore_slave_p2_odt = main_litedramcore_dfi_p2_odt;
+assign main_litedramcore_slave_p2_reset_n = main_litedramcore_dfi_p2_reset_n;
+assign main_litedramcore_slave_p2_act_n = main_litedramcore_dfi_p2_act_n;
+assign main_litedramcore_slave_p2_wrdata = main_litedramcore_dfi_p2_wrdata;
+assign main_litedramcore_slave_p2_wrdata_en = main_litedramcore_dfi_p2_wrdata_en;
+assign main_litedramcore_slave_p2_wrdata_mask = main_litedramcore_dfi_p2_wrdata_mask;
+assign main_litedramcore_slave_p2_rddata_en = main_litedramcore_dfi_p2_rddata_en;
+assign main_litedramcore_dfi_p2_rddata = main_litedramcore_slave_p2_rddata;
+assign main_litedramcore_dfi_p2_rddata_valid = main_litedramcore_slave_p2_rddata_valid;
+assign main_litedramcore_slave_p3_address = main_litedramcore_dfi_p3_address;
+assign main_litedramcore_slave_p3_bank = main_litedramcore_dfi_p3_bank;
+assign main_litedramcore_slave_p3_cas_n = main_litedramcore_dfi_p3_cas_n;
+assign main_litedramcore_slave_p3_cs_n = main_litedramcore_dfi_p3_cs_n;
+assign main_litedramcore_slave_p3_ras_n = main_litedramcore_dfi_p3_ras_n;
+assign main_litedramcore_slave_p3_we_n = main_litedramcore_dfi_p3_we_n;
+assign main_litedramcore_slave_p3_cke = main_litedramcore_dfi_p3_cke;
+assign main_litedramcore_slave_p3_odt = main_litedramcore_dfi_p3_odt;
+assign main_litedramcore_slave_p3_reset_n = main_litedramcore_dfi_p3_reset_n;
+assign main_litedramcore_slave_p3_act_n = main_litedramcore_dfi_p3_act_n;
+assign main_litedramcore_slave_p3_wrdata = main_litedramcore_dfi_p3_wrdata;
+assign main_litedramcore_slave_p3_wrdata_en = main_litedramcore_dfi_p3_wrdata_en;
+assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_mask;
+assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en;
+assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata;
+assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid;
+always @(*) begin
+    main_litedramcore_csr_dfi_p0_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+    end else begin
+        main_litedramcore_csr_dfi_p0_rddata <= main_litedramcore_master_p0_rddata;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p2_rddata <= 32'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata;
+        main_litedramcore_csr_dfi_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p1_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+        main_litedramcore_csr_dfi_p1_rddata <= main_litedramcore_master_p1_rddata;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p3_rddata <= 32'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata;
+        main_litedramcore_csr_dfi_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p2_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+        main_litedramcore_csr_dfi_p2_rddata <= main_litedramcore_master_p2_rddata;
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p0_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata;
-        end else begin
-        end
+    main_litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+    end else begin
+        main_litedramcore_csr_dfi_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
+    end
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p3_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
     end else begin
+        main_litedramcore_csr_dfi_p3_rddata <= main_litedramcore_master_p3_rddata;
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+    main_litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+    end else begin
+        main_litedramcore_csr_dfi_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
+    end
+end
+always @(*) begin
+    main_litedramcore_ext_dfi_p0_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p0_rddata <= main_litedramcore_master_p0_rddata;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p1_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+    main_litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+    main_litedramcore_ext_dfi_p1_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p1_rddata <= main_litedramcore_master_p1_rddata;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p2_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata;
+    main_litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+    main_litedramcore_ext_dfi_p2_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p2_rddata <= main_litedramcore_master_p2_rddata;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p0_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
         end else begin
-            litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p0_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p0_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+            main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p3_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata;
+    main_litedramcore_slave_p0_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
+            main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+    main_litedramcore_ext_dfi_p3_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p3_rddata <= main_litedramcore_master_p3_rddata;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p1_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
         end else begin
-            litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p1_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p1_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+            main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p2_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p1_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
+            main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p2_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p2_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+            main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p3_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p2_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
+            main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p3_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p3_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+            main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_master_p0_address <= 14'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address;
+    main_litedramcore_slave_p3_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_master_p0_address <= litedramcore_slave_p0_address;
+            main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
         end
     end else begin
-        litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_bank <= 3'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank;
+    main_litedramcore_master_p0_address <= 14'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_address <= main_litedramcore_ext_dfi_p0_address;
         end else begin
-            litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
+            main_litedramcore_master_p0_address <= main_litedramcore_slave_p0_address;
         end
     end else begin
-        litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank;
+        main_litedramcore_master_p0_address <= main_litedramcore_csr_dfi_p0_address;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_cas_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n;
+    main_litedramcore_master_p0_bank <= 3'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_bank <= main_litedramcore_ext_dfi_p0_bank;
         end else begin
-            litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
+            main_litedramcore_master_p0_bank <= main_litedramcore_slave_p0_bank;
         end
     end else begin
-        litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n;
+        main_litedramcore_master_p0_bank <= main_litedramcore_csr_dfi_p0_bank;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_cs_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
+    main_litedramcore_master_p0_cas_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_cas_n <= main_litedramcore_ext_dfi_p0_cas_n;
         end else begin
-            litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+            main_litedramcore_master_p0_cas_n <= main_litedramcore_slave_p0_cas_n;
         end
     end else begin
-        litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
+        main_litedramcore_master_p0_cas_n <= main_litedramcore_csr_dfi_p0_cas_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_ras_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
+    main_litedramcore_master_p0_cs_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_cs_n <= main_litedramcore_ext_dfi_p0_cs_n;
         end else begin
-            litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+            main_litedramcore_master_p0_cs_n <= main_litedramcore_slave_p0_cs_n;
+            if (1'd0) begin
+                main_litedramcore_master_p0_cs_n <= {2{main_litedramcore_slave_p0_cs_n}};
+            end
         end
     end else begin
-        litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
+        main_litedramcore_master_p0_cs_n <= main_litedramcore_csr_dfi_p0_cs_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_we_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
+    main_litedramcore_master_p0_ras_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_ras_n <= main_litedramcore_ext_dfi_p0_ras_n;
         end else begin
-            litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+            main_litedramcore_master_p0_ras_n <= main_litedramcore_slave_p0_ras_n;
         end
     end else begin
-        litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
+        main_litedramcore_master_p0_ras_n <= main_litedramcore_csr_dfi_p0_ras_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_cke <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke;
+    main_litedramcore_master_p0_we_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_we_n <= main_litedramcore_ext_dfi_p0_we_n;
         end else begin
-            litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
+            main_litedramcore_master_p0_we_n <= main_litedramcore_slave_p0_we_n;
         end
     end else begin
-        litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke;
+        main_litedramcore_master_p0_we_n <= main_litedramcore_csr_dfi_p0_we_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_odt <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt;
+    main_litedramcore_master_p0_cke <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_cke <= main_litedramcore_ext_dfi_p0_cke;
         end else begin
-            litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
+            main_litedramcore_master_p0_cke <= main_litedramcore_slave_p0_cke;
         end
     end else begin
-        litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt;
+        main_litedramcore_master_p0_cke <= main_litedramcore_csr_dfi_p0_cke;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_reset_n <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n;
+    main_litedramcore_master_p0_odt <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_odt <= main_litedramcore_ext_dfi_p0_odt;
         end else begin
-            litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
+            main_litedramcore_master_p0_odt <= main_litedramcore_slave_p0_odt;
         end
     end else begin
-        litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n;
+        main_litedramcore_master_p0_odt <= main_litedramcore_csr_dfi_p0_odt;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_act_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n;
+    main_litedramcore_master_p0_reset_n <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_reset_n <= main_litedramcore_ext_dfi_p0_reset_n;
         end else begin
-            litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
+            main_litedramcore_master_p0_reset_n <= main_litedramcore_slave_p0_reset_n;
         end
     end else begin
-        litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n;
+        main_litedramcore_master_p0_reset_n <= main_litedramcore_csr_dfi_p0_reset_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_wrdata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata;
+    main_litedramcore_master_p0_act_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_act_n <= main_litedramcore_ext_dfi_p0_act_n;
         end else begin
-            litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
+            main_litedramcore_master_p0_act_n <= main_litedramcore_slave_p0_act_n;
         end
     end else begin
-        litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata;
+        main_litedramcore_master_p0_act_n <= main_litedramcore_csr_dfi_p0_act_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_wrdata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en;
+    main_litedramcore_master_p0_wrdata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_wrdata <= main_litedramcore_ext_dfi_p0_wrdata;
         end else begin
-            litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
+            main_litedramcore_master_p0_wrdata <= main_litedramcore_slave_p0_wrdata;
         end
     end else begin
-        litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en;
+        main_litedramcore_master_p0_wrdata <= main_litedramcore_csr_dfi_p0_wrdata;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_wrdata_mask <= 4'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask;
+    main_litedramcore_master_p0_wrdata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_wrdata_en <= main_litedramcore_ext_dfi_p0_wrdata_en;
         end else begin
-            litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
+            main_litedramcore_master_p0_wrdata_en <= main_litedramcore_slave_p0_wrdata_en;
         end
     end else begin
-        litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask;
+        main_litedramcore_master_p0_wrdata_en <= main_litedramcore_csr_dfi_p0_wrdata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_rddata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en;
+    main_litedramcore_master_p0_wrdata_mask <= 4'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_ext_dfi_p0_wrdata_mask;
         end else begin
-            litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
+            main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_slave_p0_wrdata_mask;
         end
     end else begin
-        litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en;
+        main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_csr_dfi_p0_wrdata_mask;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_address <= 14'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address;
+    main_litedramcore_master_p0_rddata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_rddata_en <= main_litedramcore_ext_dfi_p0_rddata_en;
         end else begin
-            litedramcore_master_p1_address <= litedramcore_slave_p1_address;
+            main_litedramcore_master_p0_rddata_en <= main_litedramcore_slave_p0_rddata_en;
         end
     end else begin
-        litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address;
+        main_litedramcore_master_p0_rddata_en <= main_litedramcore_csr_dfi_p0_rddata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_bank <= 3'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank;
+    main_litedramcore_master_p1_address <= 14'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_address <= main_litedramcore_ext_dfi_p1_address;
         end else begin
-            litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
+            main_litedramcore_master_p1_address <= main_litedramcore_slave_p1_address;
         end
     end else begin
-        litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank;
+        main_litedramcore_master_p1_address <= main_litedramcore_csr_dfi_p1_address;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_cas_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n;
+    main_litedramcore_master_p1_bank <= 3'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_bank <= main_litedramcore_ext_dfi_p1_bank;
         end else begin
-            litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
+            main_litedramcore_master_p1_bank <= main_litedramcore_slave_p1_bank;
         end
     end else begin
-        litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n;
+        main_litedramcore_master_p1_bank <= main_litedramcore_csr_dfi_p1_bank;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_cs_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n;
+    main_litedramcore_master_p1_cas_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_cas_n <= main_litedramcore_ext_dfi_p1_cas_n;
         end else begin
-            litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
+            main_litedramcore_master_p1_cas_n <= main_litedramcore_slave_p1_cas_n;
         end
     end else begin
-        litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n;
+        main_litedramcore_master_p1_cas_n <= main_litedramcore_csr_dfi_p1_cas_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_ras_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n;
+    main_litedramcore_master_p1_cs_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_cs_n <= main_litedramcore_ext_dfi_p1_cs_n;
         end else begin
-            litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
+            main_litedramcore_master_p1_cs_n <= main_litedramcore_slave_p1_cs_n;
+            if (1'd0) begin
+                main_litedramcore_master_p1_cs_n <= {2{main_litedramcore_slave_p1_cs_n}};
+            end
         end
     end else begin
-        litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n;
+        main_litedramcore_master_p1_cs_n <= main_litedramcore_csr_dfi_p1_cs_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_we_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n;
+    main_litedramcore_master_p1_ras_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_ras_n <= main_litedramcore_ext_dfi_p1_ras_n;
         end else begin
-            litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
+            main_litedramcore_master_p1_ras_n <= main_litedramcore_slave_p1_ras_n;
         end
     end else begin
-        litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n;
+        main_litedramcore_master_p1_ras_n <= main_litedramcore_csr_dfi_p1_ras_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_cke <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke;
+    main_litedramcore_master_p1_we_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_we_n <= main_litedramcore_ext_dfi_p1_we_n;
         end else begin
-            litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
+            main_litedramcore_master_p1_we_n <= main_litedramcore_slave_p1_we_n;
         end
     end else begin
-        litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke;
+        main_litedramcore_master_p1_we_n <= main_litedramcore_csr_dfi_p1_we_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_odt <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt;
+    main_litedramcore_master_p1_cke <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_cke <= main_litedramcore_ext_dfi_p1_cke;
         end else begin
-            litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
+            main_litedramcore_master_p1_cke <= main_litedramcore_slave_p1_cke;
         end
     end else begin
-        litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt;
+        main_litedramcore_master_p1_cke <= main_litedramcore_csr_dfi_p1_cke;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_reset_n <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n;
+    main_litedramcore_master_p1_odt <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_odt <= main_litedramcore_ext_dfi_p1_odt;
         end else begin
-            litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+            main_litedramcore_master_p1_odt <= main_litedramcore_slave_p1_odt;
         end
     end else begin
-        litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n;
+        main_litedramcore_master_p1_odt <= main_litedramcore_csr_dfi_p1_odt;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_act_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n;
+    main_litedramcore_master_p1_reset_n <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_reset_n <= main_litedramcore_ext_dfi_p1_reset_n;
         end else begin
-            litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
+            main_litedramcore_master_p1_reset_n <= main_litedramcore_slave_p1_reset_n;
         end
     end else begin
-        litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n;
+        main_litedramcore_master_p1_reset_n <= main_litedramcore_csr_dfi_p1_reset_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_wrdata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata;
+    main_litedramcore_master_p1_act_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_act_n <= main_litedramcore_ext_dfi_p1_act_n;
         end else begin
-            litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
+            main_litedramcore_master_p1_act_n <= main_litedramcore_slave_p1_act_n;
         end
     end else begin
-        litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata;
+        main_litedramcore_master_p1_act_n <= main_litedramcore_csr_dfi_p1_act_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_wrdata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en;
+    main_litedramcore_master_p1_wrdata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_wrdata <= main_litedramcore_ext_dfi_p1_wrdata;
         end else begin
-            litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
+            main_litedramcore_master_p1_wrdata <= main_litedramcore_slave_p1_wrdata;
         end
     end else begin
-        litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en;
+        main_litedramcore_master_p1_wrdata <= main_litedramcore_csr_dfi_p1_wrdata;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_wrdata_mask <= 4'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask;
+    main_litedramcore_master_p1_wrdata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_wrdata_en <= main_litedramcore_ext_dfi_p1_wrdata_en;
         end else begin
-            litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
+            main_litedramcore_master_p1_wrdata_en <= main_litedramcore_slave_p1_wrdata_en;
         end
     end else begin
-        litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask;
+        main_litedramcore_master_p1_wrdata_en <= main_litedramcore_csr_dfi_p1_wrdata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_rddata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en;
+    main_litedramcore_master_p1_wrdata_mask <= 4'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_ext_dfi_p1_wrdata_mask;
         end else begin
-            litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
+            main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_slave_p1_wrdata_mask;
         end
     end else begin
-        litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en;
+        main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_csr_dfi_p1_wrdata_mask;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_address <= 14'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address;
+    main_litedramcore_master_p1_rddata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_rddata_en <= main_litedramcore_ext_dfi_p1_rddata_en;
         end else begin
-            litedramcore_master_p2_address <= litedramcore_slave_p2_address;
+            main_litedramcore_master_p1_rddata_en <= main_litedramcore_slave_p1_rddata_en;
         end
     end else begin
-        litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address;
+        main_litedramcore_master_p1_rddata_en <= main_litedramcore_csr_dfi_p1_rddata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_bank <= 3'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank;
+    main_litedramcore_master_p2_address <= 14'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_address <= main_litedramcore_ext_dfi_p2_address;
         end else begin
-            litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
+            main_litedramcore_master_p2_address <= main_litedramcore_slave_p2_address;
         end
     end else begin
-        litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank;
+        main_litedramcore_master_p2_address <= main_litedramcore_csr_dfi_p2_address;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_cas_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n;
+    main_litedramcore_master_p2_bank <= 3'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_bank <= main_litedramcore_ext_dfi_p2_bank;
         end else begin
-            litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
+            main_litedramcore_master_p2_bank <= main_litedramcore_slave_p2_bank;
         end
     end else begin
-        litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n;
+        main_litedramcore_master_p2_bank <= main_litedramcore_csr_dfi_p2_bank;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_cs_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n;
+    main_litedramcore_master_p2_cas_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_cas_n <= main_litedramcore_ext_dfi_p2_cas_n;
         end else begin
-            litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
+            main_litedramcore_master_p2_cas_n <= main_litedramcore_slave_p2_cas_n;
         end
     end else begin
-        litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n;
+        main_litedramcore_master_p2_cas_n <= main_litedramcore_csr_dfi_p2_cas_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_ras_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n;
+    main_litedramcore_master_p2_cs_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_cs_n <= main_litedramcore_ext_dfi_p2_cs_n;
         end else begin
-            litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
+            main_litedramcore_master_p2_cs_n <= main_litedramcore_slave_p2_cs_n;
+            if (1'd0) begin
+                main_litedramcore_master_p2_cs_n <= {2{main_litedramcore_slave_p2_cs_n}};
+            end
         end
     end else begin
-        litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n;
+        main_litedramcore_master_p2_cs_n <= main_litedramcore_csr_dfi_p2_cs_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_we_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n;
+    main_litedramcore_master_p2_ras_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_ras_n <= main_litedramcore_ext_dfi_p2_ras_n;
         end else begin
-            litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
+            main_litedramcore_master_p2_ras_n <= main_litedramcore_slave_p2_ras_n;
         end
     end else begin
-        litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n;
+        main_litedramcore_master_p2_ras_n <= main_litedramcore_csr_dfi_p2_ras_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_cke <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke;
+    main_litedramcore_master_p2_we_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_we_n <= main_litedramcore_ext_dfi_p2_we_n;
         end else begin
-            litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
+            main_litedramcore_master_p2_we_n <= main_litedramcore_slave_p2_we_n;
         end
     end else begin
-        litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke;
+        main_litedramcore_master_p2_we_n <= main_litedramcore_csr_dfi_p2_we_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_odt <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt;
+    main_litedramcore_master_p2_cke <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_cke <= main_litedramcore_ext_dfi_p2_cke;
         end else begin
-            litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
+            main_litedramcore_master_p2_cke <= main_litedramcore_slave_p2_cke;
         end
     end else begin
-        litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt;
+        main_litedramcore_master_p2_cke <= main_litedramcore_csr_dfi_p2_cke;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_reset_n <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n;
+    main_litedramcore_master_p2_odt <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_odt <= main_litedramcore_ext_dfi_p2_odt;
         end else begin
-            litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
+            main_litedramcore_master_p2_odt <= main_litedramcore_slave_p2_odt;
         end
     end else begin
-        litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n;
+        main_litedramcore_master_p2_odt <= main_litedramcore_csr_dfi_p2_odt;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_act_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n;
+    main_litedramcore_master_p2_reset_n <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_reset_n <= main_litedramcore_ext_dfi_p2_reset_n;
         end else begin
-            litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
+            main_litedramcore_master_p2_reset_n <= main_litedramcore_slave_p2_reset_n;
         end
     end else begin
-        litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n;
+        main_litedramcore_master_p2_reset_n <= main_litedramcore_csr_dfi_p2_reset_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_wrdata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata;
+    main_litedramcore_master_p2_act_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_act_n <= main_litedramcore_ext_dfi_p2_act_n;
         end else begin
-            litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
+            main_litedramcore_master_p2_act_n <= main_litedramcore_slave_p2_act_n;
         end
     end else begin
-        litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata;
+        main_litedramcore_master_p2_act_n <= main_litedramcore_csr_dfi_p2_act_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_wrdata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en;
+    main_litedramcore_master_p2_wrdata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_wrdata <= main_litedramcore_ext_dfi_p2_wrdata;
         end else begin
-            litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
+            main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata;
         end
     end else begin
-        litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en;
+        main_litedramcore_master_p2_wrdata <= main_litedramcore_csr_dfi_p2_wrdata;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_wrdata_mask <= 4'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask;
+    main_litedramcore_master_p2_wrdata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_wrdata_en <= main_litedramcore_ext_dfi_p2_wrdata_en;
         end else begin
-            litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
+            main_litedramcore_master_p2_wrdata_en <= main_litedramcore_slave_p2_wrdata_en;
         end
     end else begin
-        litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask;
+        main_litedramcore_master_p2_wrdata_en <= main_litedramcore_csr_dfi_p2_wrdata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_rddata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en;
+    main_litedramcore_master_p2_wrdata_mask <= 4'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_ext_dfi_p2_wrdata_mask;
         end else begin
-            litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
+            main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_slave_p2_wrdata_mask;
         end
     end else begin
-        litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en;
+        main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_csr_dfi_p2_wrdata_mask;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_address <= 14'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address;
+    main_litedramcore_master_p2_rddata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_rddata_en <= main_litedramcore_ext_dfi_p2_rddata_en;
         end else begin
-            litedramcore_master_p3_address <= litedramcore_slave_p3_address;
+            main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en;
         end
     end else begin
-        litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address;
+        main_litedramcore_master_p2_rddata_en <= main_litedramcore_csr_dfi_p2_rddata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_bank <= 3'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank;
+    main_litedramcore_master_p3_address <= 14'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_address <= main_litedramcore_ext_dfi_p3_address;
         end else begin
-            litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
+            main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address;
         end
     end else begin
-        litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank;
+        main_litedramcore_master_p3_address <= main_litedramcore_csr_dfi_p3_address;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_cas_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n;
+    main_litedramcore_master_p3_bank <= 3'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_bank <= main_litedramcore_ext_dfi_p3_bank;
         end else begin
-            litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
+            main_litedramcore_master_p3_bank <= main_litedramcore_slave_p3_bank;
         end
     end else begin
-        litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n;
+        main_litedramcore_master_p3_bank <= main_litedramcore_csr_dfi_p3_bank;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_cs_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n;
+    main_litedramcore_master_p3_cas_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_cas_n <= main_litedramcore_ext_dfi_p3_cas_n;
         end else begin
-            litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
+            main_litedramcore_master_p3_cas_n <= main_litedramcore_slave_p3_cas_n;
         end
     end else begin
-        litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n;
+        main_litedramcore_master_p3_cas_n <= main_litedramcore_csr_dfi_p3_cas_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_ras_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n;
+    main_litedramcore_master_p3_cs_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_cs_n <= main_litedramcore_ext_dfi_p3_cs_n;
         end else begin
-            litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
+            main_litedramcore_master_p3_cs_n <= main_litedramcore_slave_p3_cs_n;
+            if (1'd0) begin
+                main_litedramcore_master_p3_cs_n <= {2{main_litedramcore_slave_p3_cs_n}};
+            end
         end
     end else begin
-        litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n;
+        main_litedramcore_master_p3_cs_n <= main_litedramcore_csr_dfi_p3_cs_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_we_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n;
+    main_litedramcore_master_p3_ras_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_ras_n <= main_litedramcore_ext_dfi_p3_ras_n;
         end else begin
-            litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
+            main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n;
         end
     end else begin
-        litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n;
+        main_litedramcore_master_p3_ras_n <= main_litedramcore_csr_dfi_p3_ras_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_cke <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke;
+    main_litedramcore_master_p3_we_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_we_n <= main_litedramcore_ext_dfi_p3_we_n;
         end else begin
-            litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
+            main_litedramcore_master_p3_we_n <= main_litedramcore_slave_p3_we_n;
         end
     end else begin
-        litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke;
+        main_litedramcore_master_p3_we_n <= main_litedramcore_csr_dfi_p3_we_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_odt <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt;
+    main_litedramcore_master_p3_cke <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_cke <= main_litedramcore_ext_dfi_p3_cke;
         end else begin
-            litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
+            main_litedramcore_master_p3_cke <= main_litedramcore_slave_p3_cke;
         end
     end else begin
-        litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt;
+        main_litedramcore_master_p3_cke <= main_litedramcore_csr_dfi_p3_cke;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_reset_n <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n;
+    main_litedramcore_master_p3_odt <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_odt <= main_litedramcore_ext_dfi_p3_odt;
         end else begin
-            litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
+            main_litedramcore_master_p3_odt <= main_litedramcore_slave_p3_odt;
         end
     end else begin
-        litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n;
+        main_litedramcore_master_p3_odt <= main_litedramcore_csr_dfi_p3_odt;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_act_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n;
+    main_litedramcore_master_p3_reset_n <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_reset_n <= main_litedramcore_ext_dfi_p3_reset_n;
         end else begin
-            litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
+            main_litedramcore_master_p3_reset_n <= main_litedramcore_slave_p3_reset_n;
         end
     end else begin
-        litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n;
+        main_litedramcore_master_p3_reset_n <= main_litedramcore_csr_dfi_p3_reset_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_wrdata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata;
+    main_litedramcore_master_p3_act_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_act_n <= main_litedramcore_ext_dfi_p3_act_n;
         end else begin
-            litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
+            main_litedramcore_master_p3_act_n <= main_litedramcore_slave_p3_act_n;
         end
     end else begin
-        litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata;
+        main_litedramcore_master_p3_act_n <= main_litedramcore_csr_dfi_p3_act_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_wrdata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en;
+    main_litedramcore_master_p3_wrdata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_wrdata <= main_litedramcore_ext_dfi_p3_wrdata;
         end else begin
-            litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
+            main_litedramcore_master_p3_wrdata <= main_litedramcore_slave_p3_wrdata;
         end
     end else begin
-        litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en;
+        main_litedramcore_master_p3_wrdata <= main_litedramcore_csr_dfi_p3_wrdata;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_wrdata_mask <= 4'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask;
+    main_litedramcore_master_p3_wrdata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_wrdata_en <= main_litedramcore_ext_dfi_p3_wrdata_en;
         end else begin
-            litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
+            main_litedramcore_master_p3_wrdata_en <= main_litedramcore_slave_p3_wrdata_en;
         end
     end else begin
-        litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask;
+        main_litedramcore_master_p3_wrdata_en <= main_litedramcore_csr_dfi_p3_wrdata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_rddata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en;
+    main_litedramcore_master_p3_wrdata_mask <= 4'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_ext_dfi_p3_wrdata_mask;
         end else begin
-            litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
+            main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_slave_p3_wrdata_mask;
         end
     end else begin
-        litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en;
+        main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_csr_dfi_p3_wrdata_mask;
     end
 end
-assign litedramcore_csr_dfi_p0_cke = litedramcore_cke;
-assign litedramcore_csr_dfi_p1_cke = litedramcore_cke;
-assign litedramcore_csr_dfi_p2_cke = litedramcore_cke;
-assign litedramcore_csr_dfi_p3_cke = litedramcore_cke;
-assign litedramcore_csr_dfi_p0_odt = litedramcore_odt;
-assign litedramcore_csr_dfi_p1_odt = litedramcore_odt;
-assign litedramcore_csr_dfi_p2_odt = litedramcore_odt;
-assign litedramcore_csr_dfi_p3_odt = litedramcore_odt;
-assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n;
-assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n;
-assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n;
-assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n;
 always @(*) begin
-    litedramcore_csr_dfi_p0_we_n <= 1'd1;
-    if (litedramcore_phaseinjector0_command_issue_re) begin
-        litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
+    main_litedramcore_master_p3_rddata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_rddata_en <= main_litedramcore_ext_dfi_p3_rddata_en;
+        end else begin
+            main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en;
+        end
     end else begin
-        litedramcore_csr_dfi_p0_we_n <= 1'd1;
+        main_litedramcore_master_p3_rddata_en <= main_litedramcore_csr_dfi_p3_rddata_en;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p0_cas_n <= 1'd1;
-    if (litedramcore_phaseinjector0_command_issue_re) begin
-        litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas);
+    main_litedramcore_csr_dfi_p0_cke <= 1'd0;
+    main_litedramcore_csr_dfi_p0_cke <= main_litedramcore_cke;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p1_cke <= 1'd0;
+    main_litedramcore_csr_dfi_p1_cke <= main_litedramcore_cke;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p2_cke <= 1'd0;
+    main_litedramcore_csr_dfi_p2_cke <= main_litedramcore_cke;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p3_cke <= 1'd0;
+    main_litedramcore_csr_dfi_p3_cke <= main_litedramcore_cke;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p0_odt <= 1'd0;
+    main_litedramcore_csr_dfi_p0_odt <= main_litedramcore_odt;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p1_odt <= 1'd0;
+    main_litedramcore_csr_dfi_p1_odt <= main_litedramcore_odt;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p2_odt <= 1'd0;
+    main_litedramcore_csr_dfi_p2_odt <= main_litedramcore_odt;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p3_odt <= 1'd0;
+    main_litedramcore_csr_dfi_p3_odt <= main_litedramcore_odt;
+end
+assign main_litedramcore_csr_dfi_p0_reset_n = main_litedramcore_reset_n;
+assign main_litedramcore_csr_dfi_p1_reset_n = main_litedramcore_reset_n;
+assign main_litedramcore_csr_dfi_p2_reset_n = main_litedramcore_reset_n;
+assign main_litedramcore_csr_dfi_p3_reset_n = main_litedramcore_reset_n;
+always @(*) begin
+    main_litedramcore_csr_dfi_p0_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        main_litedramcore_csr_dfi_p0_we_n <= (~main_litedramcore_phaseinjector0_csrfield_we);
     end else begin
-        litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+        main_litedramcore_csr_dfi_p0_we_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p0_cs_n <= 1'd1;
-    if (litedramcore_phaseinjector0_command_issue_re) begin
-        litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}};
+    main_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        main_litedramcore_csr_dfi_p0_cas_n <= (~main_litedramcore_phaseinjector0_csrfield_cas);
     end else begin
-        litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
+        main_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p0_ras_n <= 1'd1;
-    if (litedramcore_phaseinjector0_command_issue_re) begin
-        litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras);
+    main_litedramcore_csr_dfi_p0_cs_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        if (main_litedramcore_phaseinjector0_csrfield_cs_top) begin
+            main_litedramcore_csr_dfi_p0_cs_n <= 2'd2;
+        end else begin
+            if (main_litedramcore_phaseinjector0_csrfield_cs_bottom) begin
+                main_litedramcore_csr_dfi_p0_cs_n <= 1'd1;
+            end else begin
+                main_litedramcore_csr_dfi_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_csrfield_cs)}};
+            end
+        end
     end else begin
-        litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+        main_litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
     end
 end
-assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage;
-assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage;
-assign litedramcore_csr_dfi_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_wren);
-assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_rden);
-assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
-assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
 always @(*) begin
-    litedramcore_csr_dfi_p1_we_n <= 1'd1;
-    if (litedramcore_phaseinjector1_command_issue_re) begin
-        litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
+    main_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        main_litedramcore_csr_dfi_p0_ras_n <= (~main_litedramcore_phaseinjector0_csrfield_ras);
     end else begin
-        litedramcore_csr_dfi_p1_we_n <= 1'd1;
+        main_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
     end
 end
+assign main_litedramcore_csr_dfi_p0_address = main_litedramcore_phaseinjector0_address_storage;
+assign main_litedramcore_csr_dfi_p0_bank = main_litedramcore_phaseinjector0_baddress_storage;
+assign main_litedramcore_csr_dfi_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_wren);
+assign main_litedramcore_csr_dfi_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_rden);
+assign main_litedramcore_csr_dfi_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage;
+assign main_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
 always @(*) begin
-    litedramcore_csr_dfi_p1_cas_n <= 1'd1;
-    if (litedramcore_phaseinjector1_command_issue_re) begin
-        litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas);
+    main_litedramcore_csr_dfi_p1_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        main_litedramcore_csr_dfi_p1_we_n <= (~main_litedramcore_phaseinjector1_csrfield_we);
     end else begin
-        litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+        main_litedramcore_csr_dfi_p1_we_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p1_cs_n <= 1'd1;
-    if (litedramcore_phaseinjector1_command_issue_re) begin
-        litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}};
+    main_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        main_litedramcore_csr_dfi_p1_cas_n <= (~main_litedramcore_phaseinjector1_csrfield_cas);
     end else begin
-        litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
+        main_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p1_ras_n <= 1'd1;
-    if (litedramcore_phaseinjector1_command_issue_re) begin
-        litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras);
+    main_litedramcore_csr_dfi_p1_cs_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        if (main_litedramcore_phaseinjector1_csrfield_cs_top) begin
+            main_litedramcore_csr_dfi_p1_cs_n <= 2'd2;
+        end else begin
+            if (main_litedramcore_phaseinjector1_csrfield_cs_bottom) begin
+                main_litedramcore_csr_dfi_p1_cs_n <= 1'd1;
+            end else begin
+                main_litedramcore_csr_dfi_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_csrfield_cs)}};
+            end
+        end
     end else begin
-        litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+        main_litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
     end
 end
-assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage;
-assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage;
-assign litedramcore_csr_dfi_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_wren);
-assign litedramcore_csr_dfi_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_rden);
-assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
-assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
 always @(*) begin
-    litedramcore_csr_dfi_p2_we_n <= 1'd1;
-    if (litedramcore_phaseinjector2_command_issue_re) begin
-        litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we);
+    main_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        main_litedramcore_csr_dfi_p1_ras_n <= (~main_litedramcore_phaseinjector1_csrfield_ras);
     end else begin
-        litedramcore_csr_dfi_p2_we_n <= 1'd1;
+        main_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
     end
 end
+assign main_litedramcore_csr_dfi_p1_address = main_litedramcore_phaseinjector1_address_storage;
+assign main_litedramcore_csr_dfi_p1_bank = main_litedramcore_phaseinjector1_baddress_storage;
+assign main_litedramcore_csr_dfi_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_wren);
+assign main_litedramcore_csr_dfi_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_rden);
+assign main_litedramcore_csr_dfi_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage;
+assign main_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
 always @(*) begin
-    litedramcore_csr_dfi_p2_cas_n <= 1'd1;
-    if (litedramcore_phaseinjector2_command_issue_re) begin
-        litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas);
+    main_litedramcore_csr_dfi_p2_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        main_litedramcore_csr_dfi_p2_we_n <= (~main_litedramcore_phaseinjector2_csrfield_we);
     end else begin
-        litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+        main_litedramcore_csr_dfi_p2_we_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p2_cs_n <= 1'd1;
-    if (litedramcore_phaseinjector2_command_issue_re) begin
-        litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}};
+    main_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        main_litedramcore_csr_dfi_p2_cas_n <= (~main_litedramcore_phaseinjector2_csrfield_cas);
     end else begin
-        litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
+        main_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p2_ras_n <= 1'd1;
-    if (litedramcore_phaseinjector2_command_issue_re) begin
-        litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras);
+    main_litedramcore_csr_dfi_p2_cs_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        if (main_litedramcore_phaseinjector2_csrfield_cs_top) begin
+            main_litedramcore_csr_dfi_p2_cs_n <= 2'd2;
+        end else begin
+            if (main_litedramcore_phaseinjector2_csrfield_cs_bottom) begin
+                main_litedramcore_csr_dfi_p2_cs_n <= 1'd1;
+            end else begin
+                main_litedramcore_csr_dfi_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_csrfield_cs)}};
+            end
+        end
     end else begin
-        litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+        main_litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
     end
 end
-assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage;
-assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage;
-assign litedramcore_csr_dfi_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_wren);
-assign litedramcore_csr_dfi_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_rden);
-assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
-assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
 always @(*) begin
-    litedramcore_csr_dfi_p3_we_n <= 1'd1;
-    if (litedramcore_phaseinjector3_command_issue_re) begin
-        litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we);
+    main_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        main_litedramcore_csr_dfi_p2_ras_n <= (~main_litedramcore_phaseinjector2_csrfield_ras);
     end else begin
-        litedramcore_csr_dfi_p3_we_n <= 1'd1;
+        main_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
     end
 end
+assign main_litedramcore_csr_dfi_p2_address = main_litedramcore_phaseinjector2_address_storage;
+assign main_litedramcore_csr_dfi_p2_bank = main_litedramcore_phaseinjector2_baddress_storage;
+assign main_litedramcore_csr_dfi_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_wren);
+assign main_litedramcore_csr_dfi_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_rden);
+assign main_litedramcore_csr_dfi_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage;
+assign main_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
 always @(*) begin
-    litedramcore_csr_dfi_p3_cas_n <= 1'd1;
-    if (litedramcore_phaseinjector3_command_issue_re) begin
-        litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas);
+    main_litedramcore_csr_dfi_p3_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        main_litedramcore_csr_dfi_p3_we_n <= (~main_litedramcore_phaseinjector3_csrfield_we);
     end else begin
-        litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+        main_litedramcore_csr_dfi_p3_we_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p3_cs_n <= 1'd1;
-    if (litedramcore_phaseinjector3_command_issue_re) begin
-        litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}};
+    main_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        main_litedramcore_csr_dfi_p3_cas_n <= (~main_litedramcore_phaseinjector3_csrfield_cas);
     end else begin
-        litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
+        main_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p3_ras_n <= 1'd1;
-    if (litedramcore_phaseinjector3_command_issue_re) begin
-        litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras);
+    main_litedramcore_csr_dfi_p3_cs_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        if (main_litedramcore_phaseinjector3_csrfield_cs_top) begin
+            main_litedramcore_csr_dfi_p3_cs_n <= 2'd2;
+        end else begin
+            if (main_litedramcore_phaseinjector3_csrfield_cs_bottom) begin
+                main_litedramcore_csr_dfi_p3_cs_n <= 1'd1;
+            end else begin
+                main_litedramcore_csr_dfi_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_csrfield_cs)}};
+            end
+        end
     end else begin
-        litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+        main_litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
     end
 end
-assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage;
-assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage;
-assign litedramcore_csr_dfi_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_wren);
-assign litedramcore_csr_dfi_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_rden);
-assign litedramcore_csr_dfi_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage;
-assign litedramcore_csr_dfi_p3_wrdata_mask = 1'd0;
-assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid;
-assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready;
-assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we;
-assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr;
-assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock;
-assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready;
-assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid;
-assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid;
-assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready;
-assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we;
-assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr;
-assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock;
-assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready;
-assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid;
-assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid;
-assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready;
-assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we;
-assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr;
-assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock;
-assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready;
-assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid;
-assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid;
-assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready;
-assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we;
-assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr;
-assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock;
-assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready;
-assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid;
-assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid;
-assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready;
-assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we;
-assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr;
-assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock;
-assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready;
-assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid;
-assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid;
-assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready;
-assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we;
-assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr;
-assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock;
-assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready;
-assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid;
-assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid;
-assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready;
-assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we;
-assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr;
-assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock;
-assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready;
-assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid;
-assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid;
-assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready;
-assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we;
-assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr;
-assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock;
-assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready;
-assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid;
-assign litedramcore_timer_wait = (~litedramcore_timer_done0);
-assign litedramcore_postponer_req_i = litedramcore_timer_done0;
-assign litedramcore_wants_refresh = litedramcore_postponer_req_o;
-assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0;
-assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done);
-assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0);
-assign litedramcore_timer_done0 = litedramcore_timer_done1;
-assign litedramcore_timer_count0 = litedramcore_timer_count1;
-assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0));
-assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0));
-assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0);
-assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
-assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
-always @(*) begin
-    litedramcore_refresher_next_state <= 2'd0;
-    litedramcore_refresher_next_state <= litedramcore_refresher_state;
-    case (litedramcore_refresher_state)
-        1'd1: begin
-            if (litedramcore_cmd_ready) begin
-                litedramcore_refresher_next_state <= 2'd2;
-            end
-        end
-        2'd2: begin
-            if (litedramcore_sequencer_done0) begin
-                if (litedramcore_wants_zqcs) begin
-                    litedramcore_refresher_next_state <= 2'd3;
+always @(*) begin
+    main_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        main_litedramcore_csr_dfi_p3_ras_n <= (~main_litedramcore_phaseinjector3_csrfield_ras);
+    end else begin
+        main_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+    end
+end
+assign main_litedramcore_csr_dfi_p3_address = main_litedramcore_phaseinjector3_address_storage;
+assign main_litedramcore_csr_dfi_p3_bank = main_litedramcore_phaseinjector3_baddress_storage;
+assign main_litedramcore_csr_dfi_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_wren);
+assign main_litedramcore_csr_dfi_p3_rddata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_rden);
+assign main_litedramcore_csr_dfi_p3_wrdata = main_litedramcore_phaseinjector3_wrdata_storage;
+assign main_litedramcore_csr_dfi_p3_wrdata_mask = 1'd0;
+assign main_litedramcore_bankmachine0_req_valid = main_litedramcore_interface_bank0_valid;
+assign main_litedramcore_interface_bank0_ready = main_litedramcore_bankmachine0_req_ready;
+assign main_litedramcore_bankmachine0_req_we = main_litedramcore_interface_bank0_we;
+assign main_litedramcore_bankmachine0_req_addr = main_litedramcore_interface_bank0_addr;
+assign main_litedramcore_interface_bank0_lock = main_litedramcore_bankmachine0_req_lock;
+assign main_litedramcore_interface_bank0_wdata_ready = main_litedramcore_bankmachine0_req_wdata_ready;
+assign main_litedramcore_interface_bank0_rdata_valid = main_litedramcore_bankmachine0_req_rdata_valid;
+assign main_litedramcore_bankmachine1_req_valid = main_litedramcore_interface_bank1_valid;
+assign main_litedramcore_interface_bank1_ready = main_litedramcore_bankmachine1_req_ready;
+assign main_litedramcore_bankmachine1_req_we = main_litedramcore_interface_bank1_we;
+assign main_litedramcore_bankmachine1_req_addr = main_litedramcore_interface_bank1_addr;
+assign main_litedramcore_interface_bank1_lock = main_litedramcore_bankmachine1_req_lock;
+assign main_litedramcore_interface_bank1_wdata_ready = main_litedramcore_bankmachine1_req_wdata_ready;
+assign main_litedramcore_interface_bank1_rdata_valid = main_litedramcore_bankmachine1_req_rdata_valid;
+assign main_litedramcore_bankmachine2_req_valid = main_litedramcore_interface_bank2_valid;
+assign main_litedramcore_interface_bank2_ready = main_litedramcore_bankmachine2_req_ready;
+assign main_litedramcore_bankmachine2_req_we = main_litedramcore_interface_bank2_we;
+assign main_litedramcore_bankmachine2_req_addr = main_litedramcore_interface_bank2_addr;
+assign main_litedramcore_interface_bank2_lock = main_litedramcore_bankmachine2_req_lock;
+assign main_litedramcore_interface_bank2_wdata_ready = main_litedramcore_bankmachine2_req_wdata_ready;
+assign main_litedramcore_interface_bank2_rdata_valid = main_litedramcore_bankmachine2_req_rdata_valid;
+assign main_litedramcore_bankmachine3_req_valid = main_litedramcore_interface_bank3_valid;
+assign main_litedramcore_interface_bank3_ready = main_litedramcore_bankmachine3_req_ready;
+assign main_litedramcore_bankmachine3_req_we = main_litedramcore_interface_bank3_we;
+assign main_litedramcore_bankmachine3_req_addr = main_litedramcore_interface_bank3_addr;
+assign main_litedramcore_interface_bank3_lock = main_litedramcore_bankmachine3_req_lock;
+assign main_litedramcore_interface_bank3_wdata_ready = main_litedramcore_bankmachine3_req_wdata_ready;
+assign main_litedramcore_interface_bank3_rdata_valid = main_litedramcore_bankmachine3_req_rdata_valid;
+assign main_litedramcore_bankmachine4_req_valid = main_litedramcore_interface_bank4_valid;
+assign main_litedramcore_interface_bank4_ready = main_litedramcore_bankmachine4_req_ready;
+assign main_litedramcore_bankmachine4_req_we = main_litedramcore_interface_bank4_we;
+assign main_litedramcore_bankmachine4_req_addr = main_litedramcore_interface_bank4_addr;
+assign main_litedramcore_interface_bank4_lock = main_litedramcore_bankmachine4_req_lock;
+assign main_litedramcore_interface_bank4_wdata_ready = main_litedramcore_bankmachine4_req_wdata_ready;
+assign main_litedramcore_interface_bank4_rdata_valid = main_litedramcore_bankmachine4_req_rdata_valid;
+assign main_litedramcore_bankmachine5_req_valid = main_litedramcore_interface_bank5_valid;
+assign main_litedramcore_interface_bank5_ready = main_litedramcore_bankmachine5_req_ready;
+assign main_litedramcore_bankmachine5_req_we = main_litedramcore_interface_bank5_we;
+assign main_litedramcore_bankmachine5_req_addr = main_litedramcore_interface_bank5_addr;
+assign main_litedramcore_interface_bank5_lock = main_litedramcore_bankmachine5_req_lock;
+assign main_litedramcore_interface_bank5_wdata_ready = main_litedramcore_bankmachine5_req_wdata_ready;
+assign main_litedramcore_interface_bank5_rdata_valid = main_litedramcore_bankmachine5_req_rdata_valid;
+assign main_litedramcore_bankmachine6_req_valid = main_litedramcore_interface_bank6_valid;
+assign main_litedramcore_interface_bank6_ready = main_litedramcore_bankmachine6_req_ready;
+assign main_litedramcore_bankmachine6_req_we = main_litedramcore_interface_bank6_we;
+assign main_litedramcore_bankmachine6_req_addr = main_litedramcore_interface_bank6_addr;
+assign main_litedramcore_interface_bank6_lock = main_litedramcore_bankmachine6_req_lock;
+assign main_litedramcore_interface_bank6_wdata_ready = main_litedramcore_bankmachine6_req_wdata_ready;
+assign main_litedramcore_interface_bank6_rdata_valid = main_litedramcore_bankmachine6_req_rdata_valid;
+assign main_litedramcore_bankmachine7_req_valid = main_litedramcore_interface_bank7_valid;
+assign main_litedramcore_interface_bank7_ready = main_litedramcore_bankmachine7_req_ready;
+assign main_litedramcore_bankmachine7_req_we = main_litedramcore_interface_bank7_we;
+assign main_litedramcore_bankmachine7_req_addr = main_litedramcore_interface_bank7_addr;
+assign main_litedramcore_interface_bank7_lock = main_litedramcore_bankmachine7_req_lock;
+assign main_litedramcore_interface_bank7_wdata_ready = main_litedramcore_bankmachine7_req_wdata_ready;
+assign main_litedramcore_interface_bank7_rdata_valid = main_litedramcore_bankmachine7_req_rdata_valid;
+assign main_litedramcore_timer_wait = (~main_litedramcore_timer_done0);
+assign main_litedramcore_postponer_req_i = main_litedramcore_timer_done0;
+assign main_litedramcore_wants_refresh = main_litedramcore_postponer_req_o;
+assign main_litedramcore_wants_zqcs = main_litedramcore_zqcs_timer_done0;
+assign main_litedramcore_zqcs_timer_wait = (~main_litedramcore_zqcs_executer_done);
+assign main_litedramcore_timer_done1 = (main_litedramcore_timer_count1 == 1'd0);
+assign main_litedramcore_timer_done0 = main_litedramcore_timer_done1;
+assign main_litedramcore_timer_count0 = main_litedramcore_timer_count1;
+assign main_litedramcore_sequencer_start1 = (main_litedramcore_sequencer_start0 | (main_litedramcore_sequencer_count != 1'd0));
+assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 & (main_litedramcore_sequencer_count == 1'd0));
+assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0);
+assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1;
+assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1;
+always @(*) begin
+    builder_refresher_next_state <= 2'd0;
+    builder_refresher_next_state <= builder_refresher_state;
+    case (builder_refresher_state)
+        1'd1: begin
+            if (main_litedramcore_cmd_ready) begin
+                builder_refresher_next_state <= 2'd2;
+            end
+        end
+        2'd2: begin
+            if (main_litedramcore_sequencer_done0) begin
+                if (main_litedramcore_wants_zqcs) begin
+                    builder_refresher_next_state <= 2'd3;
                 end else begin
-                    litedramcore_refresher_next_state <= 1'd0;
+                    builder_refresher_next_state <= 1'd0;
                 end
             end
         end
         2'd3: begin
-            if (litedramcore_zqcs_executer_done) begin
-                litedramcore_refresher_next_state <= 1'd0;
+            if (main_litedramcore_zqcs_executer_done) begin
+                builder_refresher_next_state <= 1'd0;
             end
         end
         default: begin
             if (1'd1) begin
-                if (litedramcore_wants_refresh) begin
-                    litedramcore_refresher_next_state <= 1'd1;
+                if (main_litedramcore_wants_refresh) begin
+                    builder_refresher_next_state <= 1'd1;
                 end
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_zqcs_executer_start <= 1'd0;
-    case (litedramcore_refresher_state)
+    main_litedramcore_cmd_valid <= 1'd0;
+    case (builder_refresher_state)
         1'd1: begin
+            main_litedramcore_cmd_valid <= 1'd1;
         end
         2'd2: begin
-            if (litedramcore_sequencer_done0) begin
-                if (litedramcore_wants_zqcs) begin
-                    litedramcore_zqcs_executer_start <= 1'd1;
+            main_litedramcore_cmd_valid <= 1'd1;
+            if (main_litedramcore_sequencer_done0) begin
+                if (main_litedramcore_wants_zqcs) begin
                 end else begin
+                    main_litedramcore_cmd_valid <= 1'd0;
                 end
             end
         end
         2'd3: begin
+            main_litedramcore_cmd_valid <= 1'd1;
+            if (main_litedramcore_zqcs_executer_done) begin
+                main_litedramcore_cmd_valid <= 1'd0;
+            end
         end
         default: begin
         end
     endcase
 end
 always @(*) begin
-    litedramcore_cmd_last <= 1'd0;
-    case (litedramcore_refresher_state)
+    main_litedramcore_zqcs_executer_start <= 1'd0;
+    case (builder_refresher_state)
         1'd1: begin
         end
         2'd2: begin
-            if (litedramcore_sequencer_done0) begin
-                if (litedramcore_wants_zqcs) begin
+            if (main_litedramcore_sequencer_done0) begin
+                if (main_litedramcore_wants_zqcs) begin
+                    main_litedramcore_zqcs_executer_start <= 1'd1;
                 end else begin
-                    litedramcore_cmd_last <= 1'd1;
                 end
             end
         end
         2'd3: begin
-            if (litedramcore_zqcs_executer_done) begin
-                litedramcore_cmd_last <= 1'd1;
-            end
         end
         default: begin
         end
     endcase
 end
 always @(*) begin
-    litedramcore_sequencer_start0 <= 1'd0;
-    case (litedramcore_refresher_state)
+    main_litedramcore_cmd_last <= 1'd0;
+    case (builder_refresher_state)
         1'd1: begin
-            if (litedramcore_cmd_ready) begin
-                litedramcore_sequencer_start0 <= 1'd1;
-            end
         end
         2'd2: begin
+            if (main_litedramcore_sequencer_done0) begin
+                if (main_litedramcore_wants_zqcs) begin
+                end else begin
+                    main_litedramcore_cmd_last <= 1'd1;
+                end
+            end
         end
         2'd3: begin
+            if (main_litedramcore_zqcs_executer_done) begin
+                main_litedramcore_cmd_last <= 1'd1;
+            end
         end
         default: begin
         end
     endcase
 end
 always @(*) begin
-    litedramcore_cmd_valid <= 1'd0;
-    case (litedramcore_refresher_state)
+    main_litedramcore_sequencer_start0 <= 1'd0;
+    case (builder_refresher_state)
         1'd1: begin
-            litedramcore_cmd_valid <= 1'd1;
+            if (main_litedramcore_cmd_ready) begin
+                main_litedramcore_sequencer_start0 <= 1'd1;
+            end
         end
         2'd2: begin
-            litedramcore_cmd_valid <= 1'd1;
-            if (litedramcore_sequencer_done0) begin
-                if (litedramcore_wants_zqcs) begin
-                end else begin
-                    litedramcore_cmd_valid <= 1'd0;
-                end
-            end
         end
         2'd3: begin
-            litedramcore_cmd_valid <= 1'd1;
-            if (litedramcore_zqcs_executer_done) begin
-                litedramcore_cmd_valid <= 1'd0;
-            end
-        end
-        default: begin
-        end
-    endcase
-end
-assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid;
-assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready;
-assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we;
-assign litedramcore_bankmachine0_sink_payload_addr = litedramcore_bankmachine0_req_addr;
-assign litedramcore_bankmachine0_sink_sink_valid = litedramcore_bankmachine0_source_valid;
-assign litedramcore_bankmachine0_source_ready = litedramcore_bankmachine0_sink_sink_ready;
-assign litedramcore_bankmachine0_sink_sink_first = litedramcore_bankmachine0_source_first;
-assign litedramcore_bankmachine0_sink_sink_last = litedramcore_bankmachine0_source_last;
-assign litedramcore_bankmachine0_sink_sink_payload_we = litedramcore_bankmachine0_source_payload_we;
-assign litedramcore_bankmachine0_sink_sink_payload_addr = litedramcore_bankmachine0_source_payload_addr;
-assign litedramcore_bankmachine0_source_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
-assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_source_valid | litedramcore_bankmachine0_source_source_valid);
-assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_source_source_payload_addr[20:7]);
-assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
-always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_a <= 14'd0;
-    if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
-        litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_source_source_payload_addr[20:7];
-    end else begin
-        litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
-assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
-assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
-always @(*) begin
-    litedramcore_bankmachine0_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine0_source_valid & litedramcore_bankmachine0_source_source_valid)) begin
-        if ((litedramcore_bankmachine0_source_payload_addr[20:7] != litedramcore_bankmachine0_source_source_payload_addr[20:7])) begin
-            litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine0_syncfifo0_din = {litedramcore_bankmachine0_fifo_in_last, litedramcore_bankmachine0_fifo_in_first, litedramcore_bankmachine0_fifo_in_payload_addr, litedramcore_bankmachine0_fifo_in_payload_we};
-assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
-assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
-assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
-assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
-assign litedramcore_bankmachine0_sink_ready = litedramcore_bankmachine0_syncfifo0_writable;
-assign litedramcore_bankmachine0_syncfifo0_we = litedramcore_bankmachine0_sink_valid;
-assign litedramcore_bankmachine0_fifo_in_first = litedramcore_bankmachine0_sink_first;
-assign litedramcore_bankmachine0_fifo_in_last = litedramcore_bankmachine0_sink_last;
-assign litedramcore_bankmachine0_fifo_in_payload_we = litedramcore_bankmachine0_sink_payload_we;
-assign litedramcore_bankmachine0_fifo_in_payload_addr = litedramcore_bankmachine0_sink_payload_addr;
-assign litedramcore_bankmachine0_source_valid = litedramcore_bankmachine0_syncfifo0_readable;
-assign litedramcore_bankmachine0_source_first = litedramcore_bankmachine0_fifo_out_first;
-assign litedramcore_bankmachine0_source_last = litedramcore_bankmachine0_fifo_out_last;
-assign litedramcore_bankmachine0_source_payload_we = litedramcore_bankmachine0_fifo_out_payload_we;
-assign litedramcore_bankmachine0_source_payload_addr = litedramcore_bankmachine0_fifo_out_payload_addr;
-assign litedramcore_bankmachine0_syncfifo0_re = litedramcore_bankmachine0_source_ready;
-always @(*) begin
-    litedramcore_bankmachine0_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine0_replace) begin
-        litedramcore_bankmachine0_wrport_adr <= (litedramcore_bankmachine0_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine0_wrport_adr <= litedramcore_bankmachine0_produce;
-    end
-end
-assign litedramcore_bankmachine0_wrport_dat_w = litedramcore_bankmachine0_syncfifo0_din;
-assign litedramcore_bankmachine0_wrport_we = (litedramcore_bankmachine0_syncfifo0_we & (litedramcore_bankmachine0_syncfifo0_writable | litedramcore_bankmachine0_replace));
-assign litedramcore_bankmachine0_do_read = (litedramcore_bankmachine0_syncfifo0_readable & litedramcore_bankmachine0_syncfifo0_re);
-assign litedramcore_bankmachine0_rdport_adr = litedramcore_bankmachine0_consume;
-assign litedramcore_bankmachine0_syncfifo0_dout = litedramcore_bankmachine0_rdport_dat_r;
-assign litedramcore_bankmachine0_syncfifo0_writable = (litedramcore_bankmachine0_level != 5'd16);
-assign litedramcore_bankmachine0_syncfifo0_readable = (litedramcore_bankmachine0_level != 1'd0);
-assign litedramcore_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready);
-assign litedramcore_bankmachine0_pipe_valid_sink_valid = litedramcore_bankmachine0_sink_sink_valid;
-assign litedramcore_bankmachine0_sink_sink_ready = litedramcore_bankmachine0_pipe_valid_sink_ready;
-assign litedramcore_bankmachine0_pipe_valid_sink_first = litedramcore_bankmachine0_sink_sink_first;
-assign litedramcore_bankmachine0_pipe_valid_sink_last = litedramcore_bankmachine0_sink_sink_last;
-assign litedramcore_bankmachine0_pipe_valid_sink_payload_we = litedramcore_bankmachine0_sink_sink_payload_we;
-assign litedramcore_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_bankmachine0_sink_sink_payload_addr;
-assign litedramcore_bankmachine0_source_source_valid = litedramcore_bankmachine0_pipe_valid_source_valid;
-assign litedramcore_bankmachine0_pipe_valid_source_ready = litedramcore_bankmachine0_source_source_ready;
-assign litedramcore_bankmachine0_source_source_first = litedramcore_bankmachine0_pipe_valid_source_first;
-assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_pipe_valid_source_last;
-assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine0_next_state <= 4'd0;
-    litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
-    case (litedramcore_bankmachine0_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                if (litedramcore_bankmachine0_cmd_ready) begin
-                    litedramcore_bankmachine0_next_state <= 3'd5;
+        end
+        default: begin
+        end
+    endcase
+end
+assign main_litedramcore_bankmachine0_sink_valid = main_litedramcore_bankmachine0_req_valid;
+assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_sink_ready;
+assign main_litedramcore_bankmachine0_sink_payload_we = main_litedramcore_bankmachine0_req_we;
+assign main_litedramcore_bankmachine0_sink_payload_addr = main_litedramcore_bankmachine0_req_addr;
+assign main_litedramcore_bankmachine0_sink_sink_valid = main_litedramcore_bankmachine0_source_valid;
+assign main_litedramcore_bankmachine0_source_ready = main_litedramcore_bankmachine0_sink_sink_ready;
+assign main_litedramcore_bankmachine0_sink_sink_first = main_litedramcore_bankmachine0_source_first;
+assign main_litedramcore_bankmachine0_sink_sink_last = main_litedramcore_bankmachine0_source_last;
+assign main_litedramcore_bankmachine0_sink_sink_payload_we = main_litedramcore_bankmachine0_source_payload_we;
+assign main_litedramcore_bankmachine0_sink_sink_payload_addr = main_litedramcore_bankmachine0_source_payload_addr;
+assign main_litedramcore_bankmachine0_source_source_ready = (main_litedramcore_bankmachine0_req_wdata_ready | main_litedramcore_bankmachine0_req_rdata_valid);
+assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_source_valid | main_litedramcore_bankmachine0_source_source_valid);
+assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_source_source_payload_addr[20:7]);
+assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
+always @(*) begin
+    main_litedramcore_bankmachine0_cmd_payload_a <= 14'd0;
+    if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine0_cmd_payload_a <= main_litedramcore_bankmachine0_source_source_payload_addr[20:7];
+    end else begin
+        main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write);
+assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
+assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine0_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine0_source_valid & main_litedramcore_bankmachine0_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine0_source_payload_addr[20:7] != main_litedramcore_bankmachine0_source_source_payload_addr[20:7])) begin
+            main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine0_syncfifo0_din = {main_litedramcore_bankmachine0_fifo_in_last, main_litedramcore_bankmachine0_fifo_in_first, main_litedramcore_bankmachine0_fifo_in_payload_addr, main_litedramcore_bankmachine0_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout;
+assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout;
+assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout;
+assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout;
+assign main_litedramcore_bankmachine0_sink_ready = main_litedramcore_bankmachine0_syncfifo0_writable;
+assign main_litedramcore_bankmachine0_syncfifo0_we = main_litedramcore_bankmachine0_sink_valid;
+assign main_litedramcore_bankmachine0_fifo_in_first = main_litedramcore_bankmachine0_sink_first;
+assign main_litedramcore_bankmachine0_fifo_in_last = main_litedramcore_bankmachine0_sink_last;
+assign main_litedramcore_bankmachine0_fifo_in_payload_we = main_litedramcore_bankmachine0_sink_payload_we;
+assign main_litedramcore_bankmachine0_fifo_in_payload_addr = main_litedramcore_bankmachine0_sink_payload_addr;
+assign main_litedramcore_bankmachine0_source_valid = main_litedramcore_bankmachine0_syncfifo0_readable;
+assign main_litedramcore_bankmachine0_source_first = main_litedramcore_bankmachine0_fifo_out_first;
+assign main_litedramcore_bankmachine0_source_last = main_litedramcore_bankmachine0_fifo_out_last;
+assign main_litedramcore_bankmachine0_source_payload_we = main_litedramcore_bankmachine0_fifo_out_payload_we;
+assign main_litedramcore_bankmachine0_source_payload_addr = main_litedramcore_bankmachine0_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine0_syncfifo0_re = main_litedramcore_bankmachine0_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine0_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine0_replace) begin
+        main_litedramcore_bankmachine0_wrport_adr <= (main_litedramcore_bankmachine0_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine0_wrport_adr <= main_litedramcore_bankmachine0_produce;
+    end
+end
+assign main_litedramcore_bankmachine0_wrport_dat_w = main_litedramcore_bankmachine0_syncfifo0_din;
+assign main_litedramcore_bankmachine0_wrport_we = (main_litedramcore_bankmachine0_syncfifo0_we & (main_litedramcore_bankmachine0_syncfifo0_writable | main_litedramcore_bankmachine0_replace));
+assign main_litedramcore_bankmachine0_do_read = (main_litedramcore_bankmachine0_syncfifo0_readable & main_litedramcore_bankmachine0_syncfifo0_re);
+assign main_litedramcore_bankmachine0_rdport_adr = main_litedramcore_bankmachine0_consume;
+assign main_litedramcore_bankmachine0_syncfifo0_dout = main_litedramcore_bankmachine0_rdport_dat_r;
+assign main_litedramcore_bankmachine0_syncfifo0_writable = (main_litedramcore_bankmachine0_level != 5'd16);
+assign main_litedramcore_bankmachine0_syncfifo0_readable = (main_litedramcore_bankmachine0_level != 1'd0);
+assign main_litedramcore_bankmachine0_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine0_pipe_valid_source_valid) | main_litedramcore_bankmachine0_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine0_pipe_valid_sink_valid = main_litedramcore_bankmachine0_sink_sink_valid;
+assign main_litedramcore_bankmachine0_sink_sink_ready = main_litedramcore_bankmachine0_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine0_pipe_valid_sink_first = main_litedramcore_bankmachine0_sink_sink_first;
+assign main_litedramcore_bankmachine0_pipe_valid_sink_last = main_litedramcore_bankmachine0_sink_sink_last;
+assign main_litedramcore_bankmachine0_pipe_valid_sink_payload_we = main_litedramcore_bankmachine0_sink_sink_payload_we;
+assign main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine0_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine0_source_source_valid = main_litedramcore_bankmachine0_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine0_pipe_valid_source_ready = main_litedramcore_bankmachine0_source_source_ready;
+assign main_litedramcore_bankmachine0_source_source_first = main_litedramcore_bankmachine0_pipe_valid_source_first;
+assign main_litedramcore_bankmachine0_source_source_last = main_litedramcore_bankmachine0_pipe_valid_source_last;
+assign main_litedramcore_bankmachine0_source_source_payload_we = main_litedramcore_bankmachine0_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine0_source_source_payload_addr = main_litedramcore_bankmachine0_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine0_next_state <= 4'd0;
+    builder_bankmachine0_next_state <= builder_bankmachine0_state;
+    case (builder_bankmachine0_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                if (main_litedramcore_bankmachine0_cmd_ready) begin
+                    builder_bankmachine0_next_state <= 3'd5;
                 end
             end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_next_state <= 3'd5;
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                builder_bankmachine0_next_state <= 3'd5;
             end
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                if (litedramcore_bankmachine0_cmd_ready) begin
-                    litedramcore_bankmachine0_next_state <= 3'd7;
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                if (main_litedramcore_bankmachine0_cmd_ready) begin
+                    builder_bankmachine0_next_state <= 3'd7;
                 end
             end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine0_refresh_req)) begin
-                litedramcore_bankmachine0_next_state <= 1'd0;
+            if ((~main_litedramcore_bankmachine0_refresh_req)) begin
+                builder_bankmachine0_next_state <= 1'd0;
             end
         end
         3'd5: begin
-            litedramcore_bankmachine0_next_state <= 3'd6;
+            builder_bankmachine0_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine0_next_state <= 2'd3;
+            builder_bankmachine0_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine0_next_state <= 4'd8;
+            builder_bankmachine0_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine0_next_state <= 1'd0;
+            builder_bankmachine0_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
-                litedramcore_bankmachine0_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine0_refresh_req) begin
+                builder_bankmachine0_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
-                                litedramcore_bankmachine0_next_state <= 2'd2;
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if ((main_litedramcore_bankmachine0_cmd_ready & main_litedramcore_bankmachine0_auto_precharge)) begin
+                                builder_bankmachine0_next_state <= 2'd2;
                             end
                         end else begin
-                            litedramcore_bankmachine0_next_state <= 1'd1;
+                            builder_bankmachine0_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine0_next_state <= 2'd3;
+                        builder_bankmachine0_next_state <= 2'd3;
                     end
                 end
             end
@@ -4888,8 +5306,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -4907,14 +5325,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
+                                main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
                             end else begin
-                                litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
                             end
                         end else begin
                         end
@@ -4926,8 +5344,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -4935,9 +5353,6 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine0_twtpcon_ready) begin
-                litedramcore_bankmachine0_refresh_gnt <= 1'd1;
-            end
         end
         3'd5: begin
         end
@@ -4948,20 +5363,32 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
+                                main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_row_open <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_row_open <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -4974,25 +5401,37 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
+                            end else begin
+                                main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_cmd_valid <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_cmd_valid <= 1'd1;
-            end
         end
         3'd4: begin
+            if (main_litedramcore_bankmachine0_twtpcon_ready) begin
+                main_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -5003,34 +5442,22 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            litedramcore_bankmachine0_cmd_valid <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_row_close <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_row_open <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
-            litedramcore_bankmachine0_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine0_row_close <= 1'd1;
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_row_open <= 1'd1;
+            end
         end
         3'd4: begin
-            litedramcore_bankmachine0_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -5045,15 +5472,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_valid <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -5067,19 +5497,34 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_row_close <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
+            main_litedramcore_bankmachine0_row_close <= 1'd1;
         end
         2'd2: begin
+            main_litedramcore_bankmachine0_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
+            main_litedramcore_bankmachine0_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -5090,34 +5535,19 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -5135,12 +5565,9 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
-            end
         end
         2'd2: begin
         end
@@ -5157,15 +5584,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
-                                litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
-                            end else begin
-                            end
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -5176,22 +5600,21 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -5206,9 +5629,12 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+            end
         end
         2'd2: begin
         end
@@ -5225,14 +5651,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
+                                main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
                             end else begin
-                                litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -5244,15 +5670,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         3'd4: begin
+            main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -5263,27 +5696,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
-                                litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5301,14 +5719,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
-                                litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
                             end else begin
+                                main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -5319,139 +5737,139 @@ always @(*) begin
         end
     endcase
 end
-assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid;
-assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready;
-assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we;
-assign litedramcore_bankmachine1_sink_payload_addr = litedramcore_bankmachine1_req_addr;
-assign litedramcore_bankmachine1_sink_sink_valid = litedramcore_bankmachine1_source_valid;
-assign litedramcore_bankmachine1_source_ready = litedramcore_bankmachine1_sink_sink_ready;
-assign litedramcore_bankmachine1_sink_sink_first = litedramcore_bankmachine1_source_first;
-assign litedramcore_bankmachine1_sink_sink_last = litedramcore_bankmachine1_source_last;
-assign litedramcore_bankmachine1_sink_sink_payload_we = litedramcore_bankmachine1_source_payload_we;
-assign litedramcore_bankmachine1_sink_sink_payload_addr = litedramcore_bankmachine1_source_payload_addr;
-assign litedramcore_bankmachine1_source_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
-assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_source_valid | litedramcore_bankmachine1_source_source_valid);
-assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_source_source_payload_addr[20:7]);
-assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
-always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_a <= 14'd0;
-    if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
-        litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_source_source_payload_addr[20:7];
-    end else begin
-        litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
-assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
-assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
-always @(*) begin
-    litedramcore_bankmachine1_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine1_source_valid & litedramcore_bankmachine1_source_source_valid)) begin
-        if ((litedramcore_bankmachine1_source_payload_addr[20:7] != litedramcore_bankmachine1_source_source_payload_addr[20:7])) begin
-            litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine1_syncfifo1_din = {litedramcore_bankmachine1_fifo_in_last, litedramcore_bankmachine1_fifo_in_first, litedramcore_bankmachine1_fifo_in_payload_addr, litedramcore_bankmachine1_fifo_in_payload_we};
-assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
-assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
-assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
-assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
-assign litedramcore_bankmachine1_sink_ready = litedramcore_bankmachine1_syncfifo1_writable;
-assign litedramcore_bankmachine1_syncfifo1_we = litedramcore_bankmachine1_sink_valid;
-assign litedramcore_bankmachine1_fifo_in_first = litedramcore_bankmachine1_sink_first;
-assign litedramcore_bankmachine1_fifo_in_last = litedramcore_bankmachine1_sink_last;
-assign litedramcore_bankmachine1_fifo_in_payload_we = litedramcore_bankmachine1_sink_payload_we;
-assign litedramcore_bankmachine1_fifo_in_payload_addr = litedramcore_bankmachine1_sink_payload_addr;
-assign litedramcore_bankmachine1_source_valid = litedramcore_bankmachine1_syncfifo1_readable;
-assign litedramcore_bankmachine1_source_first = litedramcore_bankmachine1_fifo_out_first;
-assign litedramcore_bankmachine1_source_last = litedramcore_bankmachine1_fifo_out_last;
-assign litedramcore_bankmachine1_source_payload_we = litedramcore_bankmachine1_fifo_out_payload_we;
-assign litedramcore_bankmachine1_source_payload_addr = litedramcore_bankmachine1_fifo_out_payload_addr;
-assign litedramcore_bankmachine1_syncfifo1_re = litedramcore_bankmachine1_source_ready;
-always @(*) begin
-    litedramcore_bankmachine1_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine1_replace) begin
-        litedramcore_bankmachine1_wrport_adr <= (litedramcore_bankmachine1_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine1_wrport_adr <= litedramcore_bankmachine1_produce;
-    end
-end
-assign litedramcore_bankmachine1_wrport_dat_w = litedramcore_bankmachine1_syncfifo1_din;
-assign litedramcore_bankmachine1_wrport_we = (litedramcore_bankmachine1_syncfifo1_we & (litedramcore_bankmachine1_syncfifo1_writable | litedramcore_bankmachine1_replace));
-assign litedramcore_bankmachine1_do_read = (litedramcore_bankmachine1_syncfifo1_readable & litedramcore_bankmachine1_syncfifo1_re);
-assign litedramcore_bankmachine1_rdport_adr = litedramcore_bankmachine1_consume;
-assign litedramcore_bankmachine1_syncfifo1_dout = litedramcore_bankmachine1_rdport_dat_r;
-assign litedramcore_bankmachine1_syncfifo1_writable = (litedramcore_bankmachine1_level != 5'd16);
-assign litedramcore_bankmachine1_syncfifo1_readable = (litedramcore_bankmachine1_level != 1'd0);
-assign litedramcore_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready);
-assign litedramcore_bankmachine1_pipe_valid_sink_valid = litedramcore_bankmachine1_sink_sink_valid;
-assign litedramcore_bankmachine1_sink_sink_ready = litedramcore_bankmachine1_pipe_valid_sink_ready;
-assign litedramcore_bankmachine1_pipe_valid_sink_first = litedramcore_bankmachine1_sink_sink_first;
-assign litedramcore_bankmachine1_pipe_valid_sink_last = litedramcore_bankmachine1_sink_sink_last;
-assign litedramcore_bankmachine1_pipe_valid_sink_payload_we = litedramcore_bankmachine1_sink_sink_payload_we;
-assign litedramcore_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_bankmachine1_sink_sink_payload_addr;
-assign litedramcore_bankmachine1_source_source_valid = litedramcore_bankmachine1_pipe_valid_source_valid;
-assign litedramcore_bankmachine1_pipe_valid_source_ready = litedramcore_bankmachine1_source_source_ready;
-assign litedramcore_bankmachine1_source_source_first = litedramcore_bankmachine1_pipe_valid_source_first;
-assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_pipe_valid_source_last;
-assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine1_next_state <= 4'd0;
-    litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
-    case (litedramcore_bankmachine1_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                if (litedramcore_bankmachine1_cmd_ready) begin
-                    litedramcore_bankmachine1_next_state <= 3'd5;
+assign main_litedramcore_bankmachine1_sink_valid = main_litedramcore_bankmachine1_req_valid;
+assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_sink_ready;
+assign main_litedramcore_bankmachine1_sink_payload_we = main_litedramcore_bankmachine1_req_we;
+assign main_litedramcore_bankmachine1_sink_payload_addr = main_litedramcore_bankmachine1_req_addr;
+assign main_litedramcore_bankmachine1_sink_sink_valid = main_litedramcore_bankmachine1_source_valid;
+assign main_litedramcore_bankmachine1_source_ready = main_litedramcore_bankmachine1_sink_sink_ready;
+assign main_litedramcore_bankmachine1_sink_sink_first = main_litedramcore_bankmachine1_source_first;
+assign main_litedramcore_bankmachine1_sink_sink_last = main_litedramcore_bankmachine1_source_last;
+assign main_litedramcore_bankmachine1_sink_sink_payload_we = main_litedramcore_bankmachine1_source_payload_we;
+assign main_litedramcore_bankmachine1_sink_sink_payload_addr = main_litedramcore_bankmachine1_source_payload_addr;
+assign main_litedramcore_bankmachine1_source_source_ready = (main_litedramcore_bankmachine1_req_wdata_ready | main_litedramcore_bankmachine1_req_rdata_valid);
+assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_source_valid | main_litedramcore_bankmachine1_source_source_valid);
+assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_source_source_payload_addr[20:7]);
+assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
+always @(*) begin
+    main_litedramcore_bankmachine1_cmd_payload_a <= 14'd0;
+    if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine1_cmd_payload_a <= main_litedramcore_bankmachine1_source_source_payload_addr[20:7];
+    end else begin
+        main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write);
+assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
+assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine1_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine1_source_valid & main_litedramcore_bankmachine1_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine1_source_payload_addr[20:7] != main_litedramcore_bankmachine1_source_source_payload_addr[20:7])) begin
+            main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine1_syncfifo1_din = {main_litedramcore_bankmachine1_fifo_in_last, main_litedramcore_bankmachine1_fifo_in_first, main_litedramcore_bankmachine1_fifo_in_payload_addr, main_litedramcore_bankmachine1_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout;
+assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout;
+assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout;
+assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout;
+assign main_litedramcore_bankmachine1_sink_ready = main_litedramcore_bankmachine1_syncfifo1_writable;
+assign main_litedramcore_bankmachine1_syncfifo1_we = main_litedramcore_bankmachine1_sink_valid;
+assign main_litedramcore_bankmachine1_fifo_in_first = main_litedramcore_bankmachine1_sink_first;
+assign main_litedramcore_bankmachine1_fifo_in_last = main_litedramcore_bankmachine1_sink_last;
+assign main_litedramcore_bankmachine1_fifo_in_payload_we = main_litedramcore_bankmachine1_sink_payload_we;
+assign main_litedramcore_bankmachine1_fifo_in_payload_addr = main_litedramcore_bankmachine1_sink_payload_addr;
+assign main_litedramcore_bankmachine1_source_valid = main_litedramcore_bankmachine1_syncfifo1_readable;
+assign main_litedramcore_bankmachine1_source_first = main_litedramcore_bankmachine1_fifo_out_first;
+assign main_litedramcore_bankmachine1_source_last = main_litedramcore_bankmachine1_fifo_out_last;
+assign main_litedramcore_bankmachine1_source_payload_we = main_litedramcore_bankmachine1_fifo_out_payload_we;
+assign main_litedramcore_bankmachine1_source_payload_addr = main_litedramcore_bankmachine1_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine1_syncfifo1_re = main_litedramcore_bankmachine1_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine1_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine1_replace) begin
+        main_litedramcore_bankmachine1_wrport_adr <= (main_litedramcore_bankmachine1_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine1_wrport_adr <= main_litedramcore_bankmachine1_produce;
+    end
+end
+assign main_litedramcore_bankmachine1_wrport_dat_w = main_litedramcore_bankmachine1_syncfifo1_din;
+assign main_litedramcore_bankmachine1_wrport_we = (main_litedramcore_bankmachine1_syncfifo1_we & (main_litedramcore_bankmachine1_syncfifo1_writable | main_litedramcore_bankmachine1_replace));
+assign main_litedramcore_bankmachine1_do_read = (main_litedramcore_bankmachine1_syncfifo1_readable & main_litedramcore_bankmachine1_syncfifo1_re);
+assign main_litedramcore_bankmachine1_rdport_adr = main_litedramcore_bankmachine1_consume;
+assign main_litedramcore_bankmachine1_syncfifo1_dout = main_litedramcore_bankmachine1_rdport_dat_r;
+assign main_litedramcore_bankmachine1_syncfifo1_writable = (main_litedramcore_bankmachine1_level != 5'd16);
+assign main_litedramcore_bankmachine1_syncfifo1_readable = (main_litedramcore_bankmachine1_level != 1'd0);
+assign main_litedramcore_bankmachine1_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine1_pipe_valid_source_valid) | main_litedramcore_bankmachine1_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine1_pipe_valid_sink_valid = main_litedramcore_bankmachine1_sink_sink_valid;
+assign main_litedramcore_bankmachine1_sink_sink_ready = main_litedramcore_bankmachine1_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine1_pipe_valid_sink_first = main_litedramcore_bankmachine1_sink_sink_first;
+assign main_litedramcore_bankmachine1_pipe_valid_sink_last = main_litedramcore_bankmachine1_sink_sink_last;
+assign main_litedramcore_bankmachine1_pipe_valid_sink_payload_we = main_litedramcore_bankmachine1_sink_sink_payload_we;
+assign main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine1_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine1_source_source_valid = main_litedramcore_bankmachine1_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine1_pipe_valid_source_ready = main_litedramcore_bankmachine1_source_source_ready;
+assign main_litedramcore_bankmachine1_source_source_first = main_litedramcore_bankmachine1_pipe_valid_source_first;
+assign main_litedramcore_bankmachine1_source_source_last = main_litedramcore_bankmachine1_pipe_valid_source_last;
+assign main_litedramcore_bankmachine1_source_source_payload_we = main_litedramcore_bankmachine1_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine1_source_source_payload_addr = main_litedramcore_bankmachine1_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine1_next_state <= 4'd0;
+    builder_bankmachine1_next_state <= builder_bankmachine1_state;
+    case (builder_bankmachine1_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                if (main_litedramcore_bankmachine1_cmd_ready) begin
+                    builder_bankmachine1_next_state <= 3'd5;
                 end
             end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_next_state <= 3'd5;
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                builder_bankmachine1_next_state <= 3'd5;
             end
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                if (litedramcore_bankmachine1_cmd_ready) begin
-                    litedramcore_bankmachine1_next_state <= 3'd7;
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                if (main_litedramcore_bankmachine1_cmd_ready) begin
+                    builder_bankmachine1_next_state <= 3'd7;
                 end
             end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine1_refresh_req)) begin
-                litedramcore_bankmachine1_next_state <= 1'd0;
+            if ((~main_litedramcore_bankmachine1_refresh_req)) begin
+                builder_bankmachine1_next_state <= 1'd0;
             end
         end
         3'd5: begin
-            litedramcore_bankmachine1_next_state <= 3'd6;
+            builder_bankmachine1_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine1_next_state <= 2'd3;
+            builder_bankmachine1_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine1_next_state <= 4'd8;
+            builder_bankmachine1_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine1_next_state <= 1'd0;
+            builder_bankmachine1_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
-                litedramcore_bankmachine1_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine1_refresh_req) begin
+                builder_bankmachine1_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
-                                litedramcore_bankmachine1_next_state <= 2'd2;
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if ((main_litedramcore_bankmachine1_cmd_ready & main_litedramcore_bankmachine1_auto_precharge)) begin
+                                builder_bankmachine1_next_state <= 2'd2;
                             end
                         end else begin
-                            litedramcore_bankmachine1_next_state <= 1'd1;
+                            builder_bankmachine1_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine1_next_state <= 2'd3;
+                        builder_bankmachine1_next_state <= 2'd3;
                     end
                 end
             end
@@ -5459,18 +5877,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
-            end
         end
         3'd4: begin
+            if (main_litedramcore_bankmachine1_twtpcon_ready) begin
+                main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -5485,13 +5903,16 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_row_open <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_row_open <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -5504,34 +5925,22 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -5545,22 +5954,34 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_row_close <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
-            end
+            main_litedramcore_bankmachine1_row_close <= 1'd1;
         end
         2'd2: begin
+            main_litedramcore_bankmachine1_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
+            main_litedramcore_bankmachine1_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -5571,41 +5992,22 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                                litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -5620,8 +6022,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5639,15 +6041,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
-                            end
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -5658,13 +6057,19 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -5677,28 +6082,16 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                                litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+            end
         end
         2'd2: begin
         end
@@ -5715,13 +6108,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                                litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
+                                main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -5734,15 +6127,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         3'd4: begin
+            main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -5753,27 +6153,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5781,9 +6166,6 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine1_twtpcon_ready) begin
-                litedramcore_bankmachine1_refresh_gnt <= 1'd1;
-            end
         end
         3'd5: begin
         end
@@ -5794,20 +6176,32 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
+                            end else begin
+                                main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_row_open <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_row_open <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -5820,23 +6214,32 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
+                                main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_cmd_valid <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_cmd_valid <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -5849,12 +6252,15 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            litedramcore_bankmachine1_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
+                                main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready;
+                            end else begin
+                            end
                         end else begin
                         end
                     end else begin
@@ -5865,18 +6271,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_row_close <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            litedramcore_bankmachine1_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine1_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine1_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -5887,142 +6290,157 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
+                            end else begin
+                                main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
-assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid;
-assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready;
-assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we;
-assign litedramcore_bankmachine2_sink_payload_addr = litedramcore_bankmachine2_req_addr;
-assign litedramcore_bankmachine2_sink_sink_valid = litedramcore_bankmachine2_source_valid;
-assign litedramcore_bankmachine2_source_ready = litedramcore_bankmachine2_sink_sink_ready;
-assign litedramcore_bankmachine2_sink_sink_first = litedramcore_bankmachine2_source_first;
-assign litedramcore_bankmachine2_sink_sink_last = litedramcore_bankmachine2_source_last;
-assign litedramcore_bankmachine2_sink_sink_payload_we = litedramcore_bankmachine2_source_payload_we;
-assign litedramcore_bankmachine2_sink_sink_payload_addr = litedramcore_bankmachine2_source_payload_addr;
-assign litedramcore_bankmachine2_source_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
-assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_source_valid | litedramcore_bankmachine2_source_source_valid);
-assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_source_source_payload_addr[20:7]);
-assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
-always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_a <= 14'd0;
-    if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
-        litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_source_source_payload_addr[20:7];
-    end else begin
-        litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
-assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
-assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
-always @(*) begin
-    litedramcore_bankmachine2_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine2_source_valid & litedramcore_bankmachine2_source_source_valid)) begin
-        if ((litedramcore_bankmachine2_source_payload_addr[20:7] != litedramcore_bankmachine2_source_source_payload_addr[20:7])) begin
-            litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine2_syncfifo2_din = {litedramcore_bankmachine2_fifo_in_last, litedramcore_bankmachine2_fifo_in_first, litedramcore_bankmachine2_fifo_in_payload_addr, litedramcore_bankmachine2_fifo_in_payload_we};
-assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
-assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
-assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
-assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
-assign litedramcore_bankmachine2_sink_ready = litedramcore_bankmachine2_syncfifo2_writable;
-assign litedramcore_bankmachine2_syncfifo2_we = litedramcore_bankmachine2_sink_valid;
-assign litedramcore_bankmachine2_fifo_in_first = litedramcore_bankmachine2_sink_first;
-assign litedramcore_bankmachine2_fifo_in_last = litedramcore_bankmachine2_sink_last;
-assign litedramcore_bankmachine2_fifo_in_payload_we = litedramcore_bankmachine2_sink_payload_we;
-assign litedramcore_bankmachine2_fifo_in_payload_addr = litedramcore_bankmachine2_sink_payload_addr;
-assign litedramcore_bankmachine2_source_valid = litedramcore_bankmachine2_syncfifo2_readable;
-assign litedramcore_bankmachine2_source_first = litedramcore_bankmachine2_fifo_out_first;
-assign litedramcore_bankmachine2_source_last = litedramcore_bankmachine2_fifo_out_last;
-assign litedramcore_bankmachine2_source_payload_we = litedramcore_bankmachine2_fifo_out_payload_we;
-assign litedramcore_bankmachine2_source_payload_addr = litedramcore_bankmachine2_fifo_out_payload_addr;
-assign litedramcore_bankmachine2_syncfifo2_re = litedramcore_bankmachine2_source_ready;
-always @(*) begin
-    litedramcore_bankmachine2_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine2_replace) begin
-        litedramcore_bankmachine2_wrport_adr <= (litedramcore_bankmachine2_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine2_wrport_adr <= litedramcore_bankmachine2_produce;
-    end
-end
-assign litedramcore_bankmachine2_wrport_dat_w = litedramcore_bankmachine2_syncfifo2_din;
-assign litedramcore_bankmachine2_wrport_we = (litedramcore_bankmachine2_syncfifo2_we & (litedramcore_bankmachine2_syncfifo2_writable | litedramcore_bankmachine2_replace));
-assign litedramcore_bankmachine2_do_read = (litedramcore_bankmachine2_syncfifo2_readable & litedramcore_bankmachine2_syncfifo2_re);
-assign litedramcore_bankmachine2_rdport_adr = litedramcore_bankmachine2_consume;
-assign litedramcore_bankmachine2_syncfifo2_dout = litedramcore_bankmachine2_rdport_dat_r;
-assign litedramcore_bankmachine2_syncfifo2_writable = (litedramcore_bankmachine2_level != 5'd16);
-assign litedramcore_bankmachine2_syncfifo2_readable = (litedramcore_bankmachine2_level != 1'd0);
-assign litedramcore_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready);
-assign litedramcore_bankmachine2_pipe_valid_sink_valid = litedramcore_bankmachine2_sink_sink_valid;
-assign litedramcore_bankmachine2_sink_sink_ready = litedramcore_bankmachine2_pipe_valid_sink_ready;
-assign litedramcore_bankmachine2_pipe_valid_sink_first = litedramcore_bankmachine2_sink_sink_first;
-assign litedramcore_bankmachine2_pipe_valid_sink_last = litedramcore_bankmachine2_sink_sink_last;
-assign litedramcore_bankmachine2_pipe_valid_sink_payload_we = litedramcore_bankmachine2_sink_sink_payload_we;
-assign litedramcore_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_bankmachine2_sink_sink_payload_addr;
-assign litedramcore_bankmachine2_source_source_valid = litedramcore_bankmachine2_pipe_valid_source_valid;
-assign litedramcore_bankmachine2_pipe_valid_source_ready = litedramcore_bankmachine2_source_source_ready;
-assign litedramcore_bankmachine2_source_source_first = litedramcore_bankmachine2_pipe_valid_source_first;
-assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_pipe_valid_source_last;
-assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine2_next_state <= 4'd0;
-    litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
-    case (litedramcore_bankmachine2_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                if (litedramcore_bankmachine2_cmd_ready) begin
-                    litedramcore_bankmachine2_next_state <= 3'd5;
+assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid;
+assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready;
+assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we;
+assign main_litedramcore_bankmachine2_sink_payload_addr = main_litedramcore_bankmachine2_req_addr;
+assign main_litedramcore_bankmachine2_sink_sink_valid = main_litedramcore_bankmachine2_source_valid;
+assign main_litedramcore_bankmachine2_source_ready = main_litedramcore_bankmachine2_sink_sink_ready;
+assign main_litedramcore_bankmachine2_sink_sink_first = main_litedramcore_bankmachine2_source_first;
+assign main_litedramcore_bankmachine2_sink_sink_last = main_litedramcore_bankmachine2_source_last;
+assign main_litedramcore_bankmachine2_sink_sink_payload_we = main_litedramcore_bankmachine2_source_payload_we;
+assign main_litedramcore_bankmachine2_sink_sink_payload_addr = main_litedramcore_bankmachine2_source_payload_addr;
+assign main_litedramcore_bankmachine2_source_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid);
+assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_source_valid | main_litedramcore_bankmachine2_source_source_valid);
+assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_source_source_payload_addr[20:7]);
+assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
+always @(*) begin
+    main_litedramcore_bankmachine2_cmd_payload_a <= 14'd0;
+    if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine2_cmd_payload_a <= main_litedramcore_bankmachine2_source_source_payload_addr[20:7];
+    end else begin
+        main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write);
+assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
+assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine2_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine2_source_valid & main_litedramcore_bankmachine2_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine2_source_payload_addr[20:7] != main_litedramcore_bankmachine2_source_source_payload_addr[20:7])) begin
+            main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine2_syncfifo2_din = {main_litedramcore_bankmachine2_fifo_in_last, main_litedramcore_bankmachine2_fifo_in_first, main_litedramcore_bankmachine2_fifo_in_payload_addr, main_litedramcore_bankmachine2_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
+assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
+assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
+assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
+assign main_litedramcore_bankmachine2_sink_ready = main_litedramcore_bankmachine2_syncfifo2_writable;
+assign main_litedramcore_bankmachine2_syncfifo2_we = main_litedramcore_bankmachine2_sink_valid;
+assign main_litedramcore_bankmachine2_fifo_in_first = main_litedramcore_bankmachine2_sink_first;
+assign main_litedramcore_bankmachine2_fifo_in_last = main_litedramcore_bankmachine2_sink_last;
+assign main_litedramcore_bankmachine2_fifo_in_payload_we = main_litedramcore_bankmachine2_sink_payload_we;
+assign main_litedramcore_bankmachine2_fifo_in_payload_addr = main_litedramcore_bankmachine2_sink_payload_addr;
+assign main_litedramcore_bankmachine2_source_valid = main_litedramcore_bankmachine2_syncfifo2_readable;
+assign main_litedramcore_bankmachine2_source_first = main_litedramcore_bankmachine2_fifo_out_first;
+assign main_litedramcore_bankmachine2_source_last = main_litedramcore_bankmachine2_fifo_out_last;
+assign main_litedramcore_bankmachine2_source_payload_we = main_litedramcore_bankmachine2_fifo_out_payload_we;
+assign main_litedramcore_bankmachine2_source_payload_addr = main_litedramcore_bankmachine2_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine2_syncfifo2_re = main_litedramcore_bankmachine2_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine2_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine2_replace) begin
+        main_litedramcore_bankmachine2_wrport_adr <= (main_litedramcore_bankmachine2_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine2_wrport_adr <= main_litedramcore_bankmachine2_produce;
+    end
+end
+assign main_litedramcore_bankmachine2_wrport_dat_w = main_litedramcore_bankmachine2_syncfifo2_din;
+assign main_litedramcore_bankmachine2_wrport_we = (main_litedramcore_bankmachine2_syncfifo2_we & (main_litedramcore_bankmachine2_syncfifo2_writable | main_litedramcore_bankmachine2_replace));
+assign main_litedramcore_bankmachine2_do_read = (main_litedramcore_bankmachine2_syncfifo2_readable & main_litedramcore_bankmachine2_syncfifo2_re);
+assign main_litedramcore_bankmachine2_rdport_adr = main_litedramcore_bankmachine2_consume;
+assign main_litedramcore_bankmachine2_syncfifo2_dout = main_litedramcore_bankmachine2_rdport_dat_r;
+assign main_litedramcore_bankmachine2_syncfifo2_writable = (main_litedramcore_bankmachine2_level != 5'd16);
+assign main_litedramcore_bankmachine2_syncfifo2_readable = (main_litedramcore_bankmachine2_level != 1'd0);
+assign main_litedramcore_bankmachine2_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine2_pipe_valid_source_valid) | main_litedramcore_bankmachine2_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine2_pipe_valid_sink_valid = main_litedramcore_bankmachine2_sink_sink_valid;
+assign main_litedramcore_bankmachine2_sink_sink_ready = main_litedramcore_bankmachine2_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine2_pipe_valid_sink_first = main_litedramcore_bankmachine2_sink_sink_first;
+assign main_litedramcore_bankmachine2_pipe_valid_sink_last = main_litedramcore_bankmachine2_sink_sink_last;
+assign main_litedramcore_bankmachine2_pipe_valid_sink_payload_we = main_litedramcore_bankmachine2_sink_sink_payload_we;
+assign main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine2_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine2_source_source_valid = main_litedramcore_bankmachine2_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine2_pipe_valid_source_ready = main_litedramcore_bankmachine2_source_source_ready;
+assign main_litedramcore_bankmachine2_source_source_first = main_litedramcore_bankmachine2_pipe_valid_source_first;
+assign main_litedramcore_bankmachine2_source_source_last = main_litedramcore_bankmachine2_pipe_valid_source_last;
+assign main_litedramcore_bankmachine2_source_source_payload_we = main_litedramcore_bankmachine2_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine2_source_source_payload_addr = main_litedramcore_bankmachine2_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine2_next_state <= 4'd0;
+    builder_bankmachine2_next_state <= builder_bankmachine2_state;
+    case (builder_bankmachine2_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                if (main_litedramcore_bankmachine2_cmd_ready) begin
+                    builder_bankmachine2_next_state <= 3'd5;
                 end
             end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_next_state <= 3'd5;
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                builder_bankmachine2_next_state <= 3'd5;
             end
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                if (litedramcore_bankmachine2_cmd_ready) begin
-                    litedramcore_bankmachine2_next_state <= 3'd7;
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                if (main_litedramcore_bankmachine2_cmd_ready) begin
+                    builder_bankmachine2_next_state <= 3'd7;
                 end
             end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine2_refresh_req)) begin
-                litedramcore_bankmachine2_next_state <= 1'd0;
+            if ((~main_litedramcore_bankmachine2_refresh_req)) begin
+                builder_bankmachine2_next_state <= 1'd0;
             end
         end
         3'd5: begin
-            litedramcore_bankmachine2_next_state <= 3'd6;
+            builder_bankmachine2_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine2_next_state <= 2'd3;
+            builder_bankmachine2_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine2_next_state <= 4'd8;
+            builder_bankmachine2_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine2_next_state <= 1'd0;
+            builder_bankmachine2_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
-                litedramcore_bankmachine2_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine2_refresh_req) begin
+                builder_bankmachine2_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
-                                litedramcore_bankmachine2_next_state <= 2'd2;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if ((main_litedramcore_bankmachine2_cmd_ready & main_litedramcore_bankmachine2_auto_precharge)) begin
+                                builder_bankmachine2_next_state <= 2'd2;
                             end
                         end else begin
-                            litedramcore_bankmachine2_next_state <= 1'd1;
+                            builder_bankmachine2_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine2_next_state <= 2'd3;
+                        builder_bankmachine2_next_state <= 2'd3;
                     end
                 end
             end
@@ -6030,8 +6448,34 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine2_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6049,12 +6493,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -6065,18 +6509,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -6094,11 +6538,11 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
@@ -6116,13 +6560,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
-                                litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
+                                main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -6135,22 +6579,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -6165,8 +6609,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6184,14 +6628,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -6203,8 +6647,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6222,13 +6666,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
-                                litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
+                                main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -6241,8 +6685,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6260,13 +6704,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
-                                litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
+                                main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -6279,8 +6723,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6298,14 +6742,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
+                                main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
                             end
                         end else begin
                         end
@@ -6317,8 +6761,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6326,8 +6770,8 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine2_twtpcon_ready) begin
-                litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+            if (main_litedramcore_bankmachine2_twtpcon_ready) begin
+                main_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
             end
         end
         3'd5: begin
@@ -6343,15 +6787,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_row_open <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_row_open <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -6369,18 +6813,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -6394,12 +6838,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            litedramcore_bankmachine2_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -6410,18 +6854,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_row_close <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_row_close <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
-            litedramcore_bankmachine2_row_close <= 1'd1;
+            main_litedramcore_bankmachine2_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine2_row_close <= 1'd1;
+            main_litedramcore_bankmachine2_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine2_row_close <= 1'd1;
+            main_litedramcore_bankmachine2_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -6435,165 +6879,209 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+assign main_litedramcore_bankmachine3_sink_valid = main_litedramcore_bankmachine3_req_valid;
+assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_sink_ready;
+assign main_litedramcore_bankmachine3_sink_payload_we = main_litedramcore_bankmachine3_req_we;
+assign main_litedramcore_bankmachine3_sink_payload_addr = main_litedramcore_bankmachine3_req_addr;
+assign main_litedramcore_bankmachine3_sink_sink_valid = main_litedramcore_bankmachine3_source_valid;
+assign main_litedramcore_bankmachine3_source_ready = main_litedramcore_bankmachine3_sink_sink_ready;
+assign main_litedramcore_bankmachine3_sink_sink_first = main_litedramcore_bankmachine3_source_first;
+assign main_litedramcore_bankmachine3_sink_sink_last = main_litedramcore_bankmachine3_source_last;
+assign main_litedramcore_bankmachine3_sink_sink_payload_we = main_litedramcore_bankmachine3_source_payload_we;
+assign main_litedramcore_bankmachine3_sink_sink_payload_addr = main_litedramcore_bankmachine3_source_payload_addr;
+assign main_litedramcore_bankmachine3_source_source_ready = (main_litedramcore_bankmachine3_req_wdata_ready | main_litedramcore_bankmachine3_req_rdata_valid);
+assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_source_valid | main_litedramcore_bankmachine3_source_source_valid);
+assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_source_source_payload_addr[20:7]);
+assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
+always @(*) begin
+    main_litedramcore_bankmachine3_cmd_payload_a <= 14'd0;
+    if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine3_cmd_payload_a <= main_litedramcore_bankmachine3_source_source_payload_addr[20:7];
+    end else begin
+        main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write);
+assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
+assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine3_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine3_source_valid & main_litedramcore_bankmachine3_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine3_source_payload_addr[20:7] != main_litedramcore_bankmachine3_source_source_payload_addr[20:7])) begin
+            main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine3_syncfifo3_din = {main_litedramcore_bankmachine3_fifo_in_last, main_litedramcore_bankmachine3_fifo_in_first, main_litedramcore_bankmachine3_fifo_in_payload_addr, main_litedramcore_bankmachine3_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout;
+assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout;
+assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout;
+assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout;
+assign main_litedramcore_bankmachine3_sink_ready = main_litedramcore_bankmachine3_syncfifo3_writable;
+assign main_litedramcore_bankmachine3_syncfifo3_we = main_litedramcore_bankmachine3_sink_valid;
+assign main_litedramcore_bankmachine3_fifo_in_first = main_litedramcore_bankmachine3_sink_first;
+assign main_litedramcore_bankmachine3_fifo_in_last = main_litedramcore_bankmachine3_sink_last;
+assign main_litedramcore_bankmachine3_fifo_in_payload_we = main_litedramcore_bankmachine3_sink_payload_we;
+assign main_litedramcore_bankmachine3_fifo_in_payload_addr = main_litedramcore_bankmachine3_sink_payload_addr;
+assign main_litedramcore_bankmachine3_source_valid = main_litedramcore_bankmachine3_syncfifo3_readable;
+assign main_litedramcore_bankmachine3_source_first = main_litedramcore_bankmachine3_fifo_out_first;
+assign main_litedramcore_bankmachine3_source_last = main_litedramcore_bankmachine3_fifo_out_last;
+assign main_litedramcore_bankmachine3_source_payload_we = main_litedramcore_bankmachine3_fifo_out_payload_we;
+assign main_litedramcore_bankmachine3_source_payload_addr = main_litedramcore_bankmachine3_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine3_syncfifo3_re = main_litedramcore_bankmachine3_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine3_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine3_replace) begin
+        main_litedramcore_bankmachine3_wrport_adr <= (main_litedramcore_bankmachine3_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine3_wrport_adr <= main_litedramcore_bankmachine3_produce;
+    end
+end
+assign main_litedramcore_bankmachine3_wrport_dat_w = main_litedramcore_bankmachine3_syncfifo3_din;
+assign main_litedramcore_bankmachine3_wrport_we = (main_litedramcore_bankmachine3_syncfifo3_we & (main_litedramcore_bankmachine3_syncfifo3_writable | main_litedramcore_bankmachine3_replace));
+assign main_litedramcore_bankmachine3_do_read = (main_litedramcore_bankmachine3_syncfifo3_readable & main_litedramcore_bankmachine3_syncfifo3_re);
+assign main_litedramcore_bankmachine3_rdport_adr = main_litedramcore_bankmachine3_consume;
+assign main_litedramcore_bankmachine3_syncfifo3_dout = main_litedramcore_bankmachine3_rdport_dat_r;
+assign main_litedramcore_bankmachine3_syncfifo3_writable = (main_litedramcore_bankmachine3_level != 5'd16);
+assign main_litedramcore_bankmachine3_syncfifo3_readable = (main_litedramcore_bankmachine3_level != 1'd0);
+assign main_litedramcore_bankmachine3_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine3_pipe_valid_source_valid) | main_litedramcore_bankmachine3_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine3_pipe_valid_sink_valid = main_litedramcore_bankmachine3_sink_sink_valid;
+assign main_litedramcore_bankmachine3_sink_sink_ready = main_litedramcore_bankmachine3_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine3_pipe_valid_sink_first = main_litedramcore_bankmachine3_sink_sink_first;
+assign main_litedramcore_bankmachine3_pipe_valid_sink_last = main_litedramcore_bankmachine3_sink_sink_last;
+assign main_litedramcore_bankmachine3_pipe_valid_sink_payload_we = main_litedramcore_bankmachine3_sink_sink_payload_we;
+assign main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine3_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine3_source_source_valid = main_litedramcore_bankmachine3_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine3_pipe_valid_source_ready = main_litedramcore_bankmachine3_source_source_ready;
+assign main_litedramcore_bankmachine3_source_source_first = main_litedramcore_bankmachine3_pipe_valid_source_first;
+assign main_litedramcore_bankmachine3_source_source_last = main_litedramcore_bankmachine3_pipe_valid_source_last;
+assign main_litedramcore_bankmachine3_source_source_payload_we = main_litedramcore_bankmachine3_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine3_source_source_payload_addr = main_litedramcore_bankmachine3_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine3_next_state <= 4'd0;
+    builder_bankmachine3_next_state <= builder_bankmachine3_state;
+    case (builder_bankmachine3_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                if (main_litedramcore_bankmachine3_cmd_ready) begin
+                    builder_bankmachine3_next_state <= 3'd5;
+                end
+            end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                builder_bankmachine3_next_state <= 3'd5;
+            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                if (main_litedramcore_bankmachine3_cmd_ready) begin
+                    builder_bankmachine3_next_state <= 3'd7;
+                end
             end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine3_refresh_req)) begin
+                builder_bankmachine3_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine3_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine3_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine3_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine3_next_state <= 1'd0;
         end
         default: begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
+                builder_bankmachine3_next_state <= 3'd4;
+            end else begin
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin
+                                builder_bankmachine3_next_state <= 2'd2;
+                            end
+                        end else begin
+                            builder_bankmachine3_next_state <= 1'd1;
+                        end
+                    end else begin
+                        builder_bankmachine3_next_state <= 2'd3;
+                    end
+                end
+            end
         end
     endcase
 end
-assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid;
-assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready;
-assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we;
-assign litedramcore_bankmachine3_sink_payload_addr = litedramcore_bankmachine3_req_addr;
-assign litedramcore_bankmachine3_sink_sink_valid = litedramcore_bankmachine3_source_valid;
-assign litedramcore_bankmachine3_source_ready = litedramcore_bankmachine3_sink_sink_ready;
-assign litedramcore_bankmachine3_sink_sink_first = litedramcore_bankmachine3_source_first;
-assign litedramcore_bankmachine3_sink_sink_last = litedramcore_bankmachine3_source_last;
-assign litedramcore_bankmachine3_sink_sink_payload_we = litedramcore_bankmachine3_source_payload_we;
-assign litedramcore_bankmachine3_sink_sink_payload_addr = litedramcore_bankmachine3_source_payload_addr;
-assign litedramcore_bankmachine3_source_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
-assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_source_valid | litedramcore_bankmachine3_source_source_valid);
-assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_source_source_payload_addr[20:7]);
-assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
-always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_a <= 14'd0;
-    if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
-        litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_source_source_payload_addr[20:7];
-    end else begin
-        litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
-assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
-assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
-always @(*) begin
-    litedramcore_bankmachine3_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine3_source_valid & litedramcore_bankmachine3_source_source_valid)) begin
-        if ((litedramcore_bankmachine3_source_payload_addr[20:7] != litedramcore_bankmachine3_source_source_payload_addr[20:7])) begin
-            litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine3_syncfifo3_din = {litedramcore_bankmachine3_fifo_in_last, litedramcore_bankmachine3_fifo_in_first, litedramcore_bankmachine3_fifo_in_payload_addr, litedramcore_bankmachine3_fifo_in_payload_we};
-assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
-assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
-assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
-assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
-assign litedramcore_bankmachine3_sink_ready = litedramcore_bankmachine3_syncfifo3_writable;
-assign litedramcore_bankmachine3_syncfifo3_we = litedramcore_bankmachine3_sink_valid;
-assign litedramcore_bankmachine3_fifo_in_first = litedramcore_bankmachine3_sink_first;
-assign litedramcore_bankmachine3_fifo_in_last = litedramcore_bankmachine3_sink_last;
-assign litedramcore_bankmachine3_fifo_in_payload_we = litedramcore_bankmachine3_sink_payload_we;
-assign litedramcore_bankmachine3_fifo_in_payload_addr = litedramcore_bankmachine3_sink_payload_addr;
-assign litedramcore_bankmachine3_source_valid = litedramcore_bankmachine3_syncfifo3_readable;
-assign litedramcore_bankmachine3_source_first = litedramcore_bankmachine3_fifo_out_first;
-assign litedramcore_bankmachine3_source_last = litedramcore_bankmachine3_fifo_out_last;
-assign litedramcore_bankmachine3_source_payload_we = litedramcore_bankmachine3_fifo_out_payload_we;
-assign litedramcore_bankmachine3_source_payload_addr = litedramcore_bankmachine3_fifo_out_payload_addr;
-assign litedramcore_bankmachine3_syncfifo3_re = litedramcore_bankmachine3_source_ready;
-always @(*) begin
-    litedramcore_bankmachine3_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine3_replace) begin
-        litedramcore_bankmachine3_wrport_adr <= (litedramcore_bankmachine3_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine3_wrport_adr <= litedramcore_bankmachine3_produce;
-    end
-end
-assign litedramcore_bankmachine3_wrport_dat_w = litedramcore_bankmachine3_syncfifo3_din;
-assign litedramcore_bankmachine3_wrport_we = (litedramcore_bankmachine3_syncfifo3_we & (litedramcore_bankmachine3_syncfifo3_writable | litedramcore_bankmachine3_replace));
-assign litedramcore_bankmachine3_do_read = (litedramcore_bankmachine3_syncfifo3_readable & litedramcore_bankmachine3_syncfifo3_re);
-assign litedramcore_bankmachine3_rdport_adr = litedramcore_bankmachine3_consume;
-assign litedramcore_bankmachine3_syncfifo3_dout = litedramcore_bankmachine3_rdport_dat_r;
-assign litedramcore_bankmachine3_syncfifo3_writable = (litedramcore_bankmachine3_level != 5'd16);
-assign litedramcore_bankmachine3_syncfifo3_readable = (litedramcore_bankmachine3_level != 1'd0);
-assign litedramcore_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready);
-assign litedramcore_bankmachine3_pipe_valid_sink_valid = litedramcore_bankmachine3_sink_sink_valid;
-assign litedramcore_bankmachine3_sink_sink_ready = litedramcore_bankmachine3_pipe_valid_sink_ready;
-assign litedramcore_bankmachine3_pipe_valid_sink_first = litedramcore_bankmachine3_sink_sink_first;
-assign litedramcore_bankmachine3_pipe_valid_sink_last = litedramcore_bankmachine3_sink_sink_last;
-assign litedramcore_bankmachine3_pipe_valid_sink_payload_we = litedramcore_bankmachine3_sink_sink_payload_we;
-assign litedramcore_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_bankmachine3_sink_sink_payload_addr;
-assign litedramcore_bankmachine3_source_source_valid = litedramcore_bankmachine3_pipe_valid_source_valid;
-assign litedramcore_bankmachine3_pipe_valid_source_ready = litedramcore_bankmachine3_source_source_ready;
-assign litedramcore_bankmachine3_source_source_first = litedramcore_bankmachine3_pipe_valid_source_first;
-assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_pipe_valid_source_last;
-assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine3_next_state <= 4'd0;
-    litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
-    case (litedramcore_bankmachine3_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                if (litedramcore_bankmachine3_cmd_ready) begin
-                    litedramcore_bankmachine3_next_state <= 3'd5;
-                end
+always @(*) begin
+    main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine3_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                if (litedramcore_bankmachine3_cmd_ready) begin
-                    litedramcore_bankmachine3_next_state <= 3'd7;
-                end
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine3_refresh_req)) begin
-                litedramcore_bankmachine3_next_state <= 1'd0;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine3_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
             end
         end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
         3'd5: begin
-            litedramcore_bankmachine3_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine3_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine3_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine3_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
-                litedramcore_bankmachine3_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
-                                litedramcore_bankmachine3_next_state <= 2'd2;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
+                                main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+                            end else begin
                             end
                         end else begin
-                            litedramcore_bankmachine3_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine3_next_state <= 2'd3;
                     end
                 end
             end
@@ -6601,22 +7089,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -6631,8 +7119,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6650,14 +7138,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -6669,8 +7157,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6688,13 +7176,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
-                                litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
+                                main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -6707,8 +7195,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6726,13 +7214,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
-                                litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
+                                main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -6745,8 +7233,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6764,14 +7252,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
+                                main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
                             end
                         end else begin
                         end
@@ -6783,8 +7271,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6792,8 +7280,8 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine3_twtpcon_ready) begin
-                litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+            if (main_litedramcore_bankmachine3_twtpcon_ready) begin
+                main_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
             end
         end
         3'd5: begin
@@ -6809,15 +7297,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_row_open <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_row_open <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -6835,18 +7323,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -6860,12 +7348,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            litedramcore_bankmachine3_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -6876,18 +7364,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_row_close <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_row_close <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
-            litedramcore_bankmachine3_row_close <= 1'd1;
+            main_litedramcore_bankmachine3_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine3_row_close <= 1'd1;
+            main_litedramcore_bankmachine3_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine3_row_close <= 1'd1;
+            main_litedramcore_bankmachine3_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -6902,15 +7390,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -6928,8 +7416,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6947,12 +7435,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -6962,42 +7450,149 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+assign main_litedramcore_bankmachine4_sink_valid = main_litedramcore_bankmachine4_req_valid;
+assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_sink_ready;
+assign main_litedramcore_bankmachine4_sink_payload_we = main_litedramcore_bankmachine4_req_we;
+assign main_litedramcore_bankmachine4_sink_payload_addr = main_litedramcore_bankmachine4_req_addr;
+assign main_litedramcore_bankmachine4_sink_sink_valid = main_litedramcore_bankmachine4_source_valid;
+assign main_litedramcore_bankmachine4_source_ready = main_litedramcore_bankmachine4_sink_sink_ready;
+assign main_litedramcore_bankmachine4_sink_sink_first = main_litedramcore_bankmachine4_source_first;
+assign main_litedramcore_bankmachine4_sink_sink_last = main_litedramcore_bankmachine4_source_last;
+assign main_litedramcore_bankmachine4_sink_sink_payload_we = main_litedramcore_bankmachine4_source_payload_we;
+assign main_litedramcore_bankmachine4_sink_sink_payload_addr = main_litedramcore_bankmachine4_source_payload_addr;
+assign main_litedramcore_bankmachine4_source_source_ready = (main_litedramcore_bankmachine4_req_wdata_ready | main_litedramcore_bankmachine4_req_rdata_valid);
+assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_source_valid | main_litedramcore_bankmachine4_source_source_valid);
+assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_source_source_payload_addr[20:7]);
+assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
+always @(*) begin
+    main_litedramcore_bankmachine4_cmd_payload_a <= 14'd0;
+    if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine4_cmd_payload_a <= main_litedramcore_bankmachine4_source_source_payload_addr[20:7];
+    end else begin
+        main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write);
+assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
+assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine4_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine4_source_valid & main_litedramcore_bankmachine4_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine4_source_payload_addr[20:7] != main_litedramcore_bankmachine4_source_source_payload_addr[20:7])) begin
+            main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine4_syncfifo4_din = {main_litedramcore_bankmachine4_fifo_in_last, main_litedramcore_bankmachine4_fifo_in_first, main_litedramcore_bankmachine4_fifo_in_payload_addr, main_litedramcore_bankmachine4_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout;
+assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout;
+assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout;
+assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout;
+assign main_litedramcore_bankmachine4_sink_ready = main_litedramcore_bankmachine4_syncfifo4_writable;
+assign main_litedramcore_bankmachine4_syncfifo4_we = main_litedramcore_bankmachine4_sink_valid;
+assign main_litedramcore_bankmachine4_fifo_in_first = main_litedramcore_bankmachine4_sink_first;
+assign main_litedramcore_bankmachine4_fifo_in_last = main_litedramcore_bankmachine4_sink_last;
+assign main_litedramcore_bankmachine4_fifo_in_payload_we = main_litedramcore_bankmachine4_sink_payload_we;
+assign main_litedramcore_bankmachine4_fifo_in_payload_addr = main_litedramcore_bankmachine4_sink_payload_addr;
+assign main_litedramcore_bankmachine4_source_valid = main_litedramcore_bankmachine4_syncfifo4_readable;
+assign main_litedramcore_bankmachine4_source_first = main_litedramcore_bankmachine4_fifo_out_first;
+assign main_litedramcore_bankmachine4_source_last = main_litedramcore_bankmachine4_fifo_out_last;
+assign main_litedramcore_bankmachine4_source_payload_we = main_litedramcore_bankmachine4_fifo_out_payload_we;
+assign main_litedramcore_bankmachine4_source_payload_addr = main_litedramcore_bankmachine4_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine4_syncfifo4_re = main_litedramcore_bankmachine4_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine4_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine4_replace) begin
+        main_litedramcore_bankmachine4_wrport_adr <= (main_litedramcore_bankmachine4_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine4_wrport_adr <= main_litedramcore_bankmachine4_produce;
+    end
+end
+assign main_litedramcore_bankmachine4_wrport_dat_w = main_litedramcore_bankmachine4_syncfifo4_din;
+assign main_litedramcore_bankmachine4_wrport_we = (main_litedramcore_bankmachine4_syncfifo4_we & (main_litedramcore_bankmachine4_syncfifo4_writable | main_litedramcore_bankmachine4_replace));
+assign main_litedramcore_bankmachine4_do_read = (main_litedramcore_bankmachine4_syncfifo4_readable & main_litedramcore_bankmachine4_syncfifo4_re);
+assign main_litedramcore_bankmachine4_rdport_adr = main_litedramcore_bankmachine4_consume;
+assign main_litedramcore_bankmachine4_syncfifo4_dout = main_litedramcore_bankmachine4_rdport_dat_r;
+assign main_litedramcore_bankmachine4_syncfifo4_writable = (main_litedramcore_bankmachine4_level != 5'd16);
+assign main_litedramcore_bankmachine4_syncfifo4_readable = (main_litedramcore_bankmachine4_level != 1'd0);
+assign main_litedramcore_bankmachine4_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine4_pipe_valid_source_valid) | main_litedramcore_bankmachine4_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine4_pipe_valid_sink_valid = main_litedramcore_bankmachine4_sink_sink_valid;
+assign main_litedramcore_bankmachine4_sink_sink_ready = main_litedramcore_bankmachine4_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine4_pipe_valid_sink_first = main_litedramcore_bankmachine4_sink_sink_first;
+assign main_litedramcore_bankmachine4_pipe_valid_sink_last = main_litedramcore_bankmachine4_sink_sink_last;
+assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_we = main_litedramcore_bankmachine4_sink_sink_payload_we;
+assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine4_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine4_source_source_valid = main_litedramcore_bankmachine4_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine4_pipe_valid_source_ready = main_litedramcore_bankmachine4_source_source_ready;
+assign main_litedramcore_bankmachine4_source_source_first = main_litedramcore_bankmachine4_pipe_valid_source_first;
+assign main_litedramcore_bankmachine4_source_source_last = main_litedramcore_bankmachine4_pipe_valid_source_last;
+assign main_litedramcore_bankmachine4_source_source_payload_we = main_litedramcore_bankmachine4_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine4_source_source_payload_addr = main_litedramcore_bankmachine4_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine4_next_state <= 4'd0;
+    builder_bankmachine4_next_state <= builder_bankmachine4_state;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                if (main_litedramcore_bankmachine4_cmd_ready) begin
+                    builder_bankmachine4_next_state <= 3'd5;
+                end
             end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                builder_bankmachine4_next_state <= 3'd5;
+            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                if (main_litedramcore_bankmachine4_cmd_ready) begin
+                    builder_bankmachine4_next_state <= 3'd7;
+                end
             end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine4_refresh_req)) begin
+                builder_bankmachine4_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine4_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine4_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine4_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine4_next_state <= 1'd0;
         end
         default: begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
+                builder_bankmachine4_next_state <= 3'd4;
+            end else begin
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if ((main_litedramcore_bankmachine4_cmd_ready & main_litedramcore_bankmachine4_auto_precharge)) begin
+                                builder_bankmachine4_next_state <= 2'd2;
+                            end
+                        end else begin
+                            builder_bankmachine4_next_state <= 1'd1;
+                        end
+                    end else begin
+                        builder_bankmachine4_next_state <= 2'd3;
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
-            end
         end
         2'd2: begin
         end
@@ -7014,13 +7609,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
-                                litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
+                                main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -7032,139 +7627,38 @@ always @(*) begin
         end
     endcase
 end
-assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid;
-assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready;
-assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we;
-assign litedramcore_bankmachine4_sink_payload_addr = litedramcore_bankmachine4_req_addr;
-assign litedramcore_bankmachine4_sink_sink_valid = litedramcore_bankmachine4_source_valid;
-assign litedramcore_bankmachine4_source_ready = litedramcore_bankmachine4_sink_sink_ready;
-assign litedramcore_bankmachine4_sink_sink_first = litedramcore_bankmachine4_source_first;
-assign litedramcore_bankmachine4_sink_sink_last = litedramcore_bankmachine4_source_last;
-assign litedramcore_bankmachine4_sink_sink_payload_we = litedramcore_bankmachine4_source_payload_we;
-assign litedramcore_bankmachine4_sink_sink_payload_addr = litedramcore_bankmachine4_source_payload_addr;
-assign litedramcore_bankmachine4_source_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
-assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_source_valid | litedramcore_bankmachine4_source_source_valid);
-assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_source_source_payload_addr[20:7]);
-assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
-always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_a <= 14'd0;
-    if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
-        litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_source_source_payload_addr[20:7];
-    end else begin
-        litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
-assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
-assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
-always @(*) begin
-    litedramcore_bankmachine4_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine4_source_valid & litedramcore_bankmachine4_source_source_valid)) begin
-        if ((litedramcore_bankmachine4_source_payload_addr[20:7] != litedramcore_bankmachine4_source_source_payload_addr[20:7])) begin
-            litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine4_syncfifo4_din = {litedramcore_bankmachine4_fifo_in_last, litedramcore_bankmachine4_fifo_in_first, litedramcore_bankmachine4_fifo_in_payload_addr, litedramcore_bankmachine4_fifo_in_payload_we};
-assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
-assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
-assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
-assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
-assign litedramcore_bankmachine4_sink_ready = litedramcore_bankmachine4_syncfifo4_writable;
-assign litedramcore_bankmachine4_syncfifo4_we = litedramcore_bankmachine4_sink_valid;
-assign litedramcore_bankmachine4_fifo_in_first = litedramcore_bankmachine4_sink_first;
-assign litedramcore_bankmachine4_fifo_in_last = litedramcore_bankmachine4_sink_last;
-assign litedramcore_bankmachine4_fifo_in_payload_we = litedramcore_bankmachine4_sink_payload_we;
-assign litedramcore_bankmachine4_fifo_in_payload_addr = litedramcore_bankmachine4_sink_payload_addr;
-assign litedramcore_bankmachine4_source_valid = litedramcore_bankmachine4_syncfifo4_readable;
-assign litedramcore_bankmachine4_source_first = litedramcore_bankmachine4_fifo_out_first;
-assign litedramcore_bankmachine4_source_last = litedramcore_bankmachine4_fifo_out_last;
-assign litedramcore_bankmachine4_source_payload_we = litedramcore_bankmachine4_fifo_out_payload_we;
-assign litedramcore_bankmachine4_source_payload_addr = litedramcore_bankmachine4_fifo_out_payload_addr;
-assign litedramcore_bankmachine4_syncfifo4_re = litedramcore_bankmachine4_source_ready;
-always @(*) begin
-    litedramcore_bankmachine4_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine4_replace) begin
-        litedramcore_bankmachine4_wrport_adr <= (litedramcore_bankmachine4_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine4_wrport_adr <= litedramcore_bankmachine4_produce;
-    end
-end
-assign litedramcore_bankmachine4_wrport_dat_w = litedramcore_bankmachine4_syncfifo4_din;
-assign litedramcore_bankmachine4_wrport_we = (litedramcore_bankmachine4_syncfifo4_we & (litedramcore_bankmachine4_syncfifo4_writable | litedramcore_bankmachine4_replace));
-assign litedramcore_bankmachine4_do_read = (litedramcore_bankmachine4_syncfifo4_readable & litedramcore_bankmachine4_syncfifo4_re);
-assign litedramcore_bankmachine4_rdport_adr = litedramcore_bankmachine4_consume;
-assign litedramcore_bankmachine4_syncfifo4_dout = litedramcore_bankmachine4_rdport_dat_r;
-assign litedramcore_bankmachine4_syncfifo4_writable = (litedramcore_bankmachine4_level != 5'd16);
-assign litedramcore_bankmachine4_syncfifo4_readable = (litedramcore_bankmachine4_level != 1'd0);
-assign litedramcore_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready);
-assign litedramcore_bankmachine4_pipe_valid_sink_valid = litedramcore_bankmachine4_sink_sink_valid;
-assign litedramcore_bankmachine4_sink_sink_ready = litedramcore_bankmachine4_pipe_valid_sink_ready;
-assign litedramcore_bankmachine4_pipe_valid_sink_first = litedramcore_bankmachine4_sink_sink_first;
-assign litedramcore_bankmachine4_pipe_valid_sink_last = litedramcore_bankmachine4_sink_sink_last;
-assign litedramcore_bankmachine4_pipe_valid_sink_payload_we = litedramcore_bankmachine4_sink_sink_payload_we;
-assign litedramcore_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_bankmachine4_sink_sink_payload_addr;
-assign litedramcore_bankmachine4_source_source_valid = litedramcore_bankmachine4_pipe_valid_source_valid;
-assign litedramcore_bankmachine4_pipe_valid_source_ready = litedramcore_bankmachine4_source_source_ready;
-assign litedramcore_bankmachine4_source_source_first = litedramcore_bankmachine4_pipe_valid_source_first;
-assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_pipe_valid_source_last;
-assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine4_next_state <= 4'd0;
-    litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
-    case (litedramcore_bankmachine4_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                if (litedramcore_bankmachine4_cmd_ready) begin
-                    litedramcore_bankmachine4_next_state <= 3'd5;
-                end
-            end
+always @(*) begin
+    main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine4_state)
+        1'd1: begin
         end
         2'd2: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                if (litedramcore_bankmachine4_cmd_ready) begin
-                    litedramcore_bankmachine4_next_state <= 3'd7;
-                end
-            end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine4_refresh_req)) begin
-                litedramcore_bankmachine4_next_state <= 1'd0;
-            end
         end
         3'd5: begin
-            litedramcore_bankmachine4_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine4_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine4_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine4_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
-                litedramcore_bankmachine4_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
-                                litedramcore_bankmachine4_next_state <= 2'd2;
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
+                                main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready;
+                            end else begin
                             end
                         end else begin
-                            litedramcore_bankmachine4_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine4_next_state <= 2'd3;
                     end
                 end
             end
@@ -7172,8 +7666,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7191,14 +7685,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
+                                main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready;
                             end
                         end else begin
                         end
@@ -7210,8 +7704,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7219,8 +7713,8 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine4_twtpcon_ready) begin
-                litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+            if (main_litedramcore_bankmachine4_twtpcon_ready) begin
+                main_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
             end
         end
         3'd5: begin
@@ -7236,15 +7730,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_row_open <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_row_open <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -7262,18 +7756,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_valid <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -7287,12 +7781,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            litedramcore_bankmachine4_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -7303,18 +7797,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_row_close <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_row_close <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            litedramcore_bankmachine4_row_close <= 1'd1;
+            main_litedramcore_bankmachine4_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine4_row_close <= 1'd1;
+            main_litedramcore_bankmachine4_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine4_row_close <= 1'd1;
+            main_litedramcore_bankmachine4_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -7329,15 +7823,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -7355,8 +7849,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7374,12 +7868,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -7390,18 +7884,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -7419,11 +7913,11 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
@@ -7441,13 +7935,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
-                                litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
+                                main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -7460,22 +7954,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -7490,8 +7984,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7509,14 +8003,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -7527,38 +8021,139 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+assign main_litedramcore_bankmachine5_sink_valid = main_litedramcore_bankmachine5_req_valid;
+assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_sink_ready;
+assign main_litedramcore_bankmachine5_sink_payload_we = main_litedramcore_bankmachine5_req_we;
+assign main_litedramcore_bankmachine5_sink_payload_addr = main_litedramcore_bankmachine5_req_addr;
+assign main_litedramcore_bankmachine5_sink_sink_valid = main_litedramcore_bankmachine5_source_valid;
+assign main_litedramcore_bankmachine5_source_ready = main_litedramcore_bankmachine5_sink_sink_ready;
+assign main_litedramcore_bankmachine5_sink_sink_first = main_litedramcore_bankmachine5_source_first;
+assign main_litedramcore_bankmachine5_sink_sink_last = main_litedramcore_bankmachine5_source_last;
+assign main_litedramcore_bankmachine5_sink_sink_payload_we = main_litedramcore_bankmachine5_source_payload_we;
+assign main_litedramcore_bankmachine5_sink_sink_payload_addr = main_litedramcore_bankmachine5_source_payload_addr;
+assign main_litedramcore_bankmachine5_source_source_ready = (main_litedramcore_bankmachine5_req_wdata_ready | main_litedramcore_bankmachine5_req_rdata_valid);
+assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_source_valid | main_litedramcore_bankmachine5_source_source_valid);
+assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_source_source_payload_addr[20:7]);
+assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
+always @(*) begin
+    main_litedramcore_bankmachine5_cmd_payload_a <= 14'd0;
+    if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine5_cmd_payload_a <= main_litedramcore_bankmachine5_source_source_payload_addr[20:7];
+    end else begin
+        main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write);
+assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
+assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine5_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine5_source_valid & main_litedramcore_bankmachine5_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine5_source_payload_addr[20:7] != main_litedramcore_bankmachine5_source_source_payload_addr[20:7])) begin
+            main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine5_syncfifo5_din = {main_litedramcore_bankmachine5_fifo_in_last, main_litedramcore_bankmachine5_fifo_in_first, main_litedramcore_bankmachine5_fifo_in_payload_addr, main_litedramcore_bankmachine5_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout;
+assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout;
+assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout;
+assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout;
+assign main_litedramcore_bankmachine5_sink_ready = main_litedramcore_bankmachine5_syncfifo5_writable;
+assign main_litedramcore_bankmachine5_syncfifo5_we = main_litedramcore_bankmachine5_sink_valid;
+assign main_litedramcore_bankmachine5_fifo_in_first = main_litedramcore_bankmachine5_sink_first;
+assign main_litedramcore_bankmachine5_fifo_in_last = main_litedramcore_bankmachine5_sink_last;
+assign main_litedramcore_bankmachine5_fifo_in_payload_we = main_litedramcore_bankmachine5_sink_payload_we;
+assign main_litedramcore_bankmachine5_fifo_in_payload_addr = main_litedramcore_bankmachine5_sink_payload_addr;
+assign main_litedramcore_bankmachine5_source_valid = main_litedramcore_bankmachine5_syncfifo5_readable;
+assign main_litedramcore_bankmachine5_source_first = main_litedramcore_bankmachine5_fifo_out_first;
+assign main_litedramcore_bankmachine5_source_last = main_litedramcore_bankmachine5_fifo_out_last;
+assign main_litedramcore_bankmachine5_source_payload_we = main_litedramcore_bankmachine5_fifo_out_payload_we;
+assign main_litedramcore_bankmachine5_source_payload_addr = main_litedramcore_bankmachine5_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine5_syncfifo5_re = main_litedramcore_bankmachine5_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine5_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine5_replace) begin
+        main_litedramcore_bankmachine5_wrport_adr <= (main_litedramcore_bankmachine5_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine5_wrport_adr <= main_litedramcore_bankmachine5_produce;
+    end
+end
+assign main_litedramcore_bankmachine5_wrport_dat_w = main_litedramcore_bankmachine5_syncfifo5_din;
+assign main_litedramcore_bankmachine5_wrport_we = (main_litedramcore_bankmachine5_syncfifo5_we & (main_litedramcore_bankmachine5_syncfifo5_writable | main_litedramcore_bankmachine5_replace));
+assign main_litedramcore_bankmachine5_do_read = (main_litedramcore_bankmachine5_syncfifo5_readable & main_litedramcore_bankmachine5_syncfifo5_re);
+assign main_litedramcore_bankmachine5_rdport_adr = main_litedramcore_bankmachine5_consume;
+assign main_litedramcore_bankmachine5_syncfifo5_dout = main_litedramcore_bankmachine5_rdport_dat_r;
+assign main_litedramcore_bankmachine5_syncfifo5_writable = (main_litedramcore_bankmachine5_level != 5'd16);
+assign main_litedramcore_bankmachine5_syncfifo5_readable = (main_litedramcore_bankmachine5_level != 1'd0);
+assign main_litedramcore_bankmachine5_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine5_pipe_valid_source_valid) | main_litedramcore_bankmachine5_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine5_pipe_valid_sink_valid = main_litedramcore_bankmachine5_sink_sink_valid;
+assign main_litedramcore_bankmachine5_sink_sink_ready = main_litedramcore_bankmachine5_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine5_pipe_valid_sink_first = main_litedramcore_bankmachine5_sink_sink_first;
+assign main_litedramcore_bankmachine5_pipe_valid_sink_last = main_litedramcore_bankmachine5_sink_sink_last;
+assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_we = main_litedramcore_bankmachine5_sink_sink_payload_we;
+assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine5_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine5_source_source_valid = main_litedramcore_bankmachine5_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine5_pipe_valid_source_ready = main_litedramcore_bankmachine5_source_source_ready;
+assign main_litedramcore_bankmachine5_source_source_first = main_litedramcore_bankmachine5_pipe_valid_source_first;
+assign main_litedramcore_bankmachine5_source_source_last = main_litedramcore_bankmachine5_pipe_valid_source_last;
+assign main_litedramcore_bankmachine5_source_source_payload_we = main_litedramcore_bankmachine5_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine5_source_source_payload_addr = main_litedramcore_bankmachine5_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine5_next_state <= 4'd0;
+    builder_bankmachine5_next_state <= builder_bankmachine5_state;
+    case (builder_bankmachine5_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                if (main_litedramcore_bankmachine5_cmd_ready) begin
+                    builder_bankmachine5_next_state <= 3'd5;
+                end
+            end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                builder_bankmachine5_next_state <= 3'd5;
+            end
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                if (main_litedramcore_bankmachine5_cmd_ready) begin
+                    builder_bankmachine5_next_state <= 3'd7;
+                end
+            end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine5_refresh_req)) begin
+                builder_bankmachine5_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine5_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine5_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine5_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine5_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
+                builder_bankmachine5_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
-                                litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
-                            end else begin
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin
+                                builder_bankmachine5_next_state <= 2'd2;
                             end
                         end else begin
+                            builder_bankmachine5_next_state <= 1'd1;
                         end
                     end else begin
+                        builder_bankmachine5_next_state <= 2'd3;
                     end
                 end
             end
@@ -7566,8 +8161,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7575,6 +8170,9 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
+            if (main_litedramcore_bankmachine5_twtpcon_ready) begin
+                main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -7585,157 +8183,70 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
-                                litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine5_row_open <= 1'd0;
+    case (builder_bankmachine5_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_row_open <= 1'd1;
             end
         end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
     endcase
 end
-assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid;
-assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready;
-assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we;
-assign litedramcore_bankmachine5_sink_payload_addr = litedramcore_bankmachine5_req_addr;
-assign litedramcore_bankmachine5_sink_sink_valid = litedramcore_bankmachine5_source_valid;
-assign litedramcore_bankmachine5_source_ready = litedramcore_bankmachine5_sink_sink_ready;
-assign litedramcore_bankmachine5_sink_sink_first = litedramcore_bankmachine5_source_first;
-assign litedramcore_bankmachine5_sink_sink_last = litedramcore_bankmachine5_source_last;
-assign litedramcore_bankmachine5_sink_sink_payload_we = litedramcore_bankmachine5_source_payload_we;
-assign litedramcore_bankmachine5_sink_sink_payload_addr = litedramcore_bankmachine5_source_payload_addr;
-assign litedramcore_bankmachine5_source_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
-assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_source_valid | litedramcore_bankmachine5_source_source_valid);
-assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_source_source_payload_addr[20:7]);
-assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
-always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_a <= 14'd0;
-    if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
-        litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_source_source_payload_addr[20:7];
-    end else begin
-        litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
-assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
-assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
-always @(*) begin
-    litedramcore_bankmachine5_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine5_source_valid & litedramcore_bankmachine5_source_source_valid)) begin
-        if ((litedramcore_bankmachine5_source_payload_addr[20:7] != litedramcore_bankmachine5_source_source_payload_addr[20:7])) begin
-            litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine5_syncfifo5_din = {litedramcore_bankmachine5_fifo_in_last, litedramcore_bankmachine5_fifo_in_first, litedramcore_bankmachine5_fifo_in_payload_addr, litedramcore_bankmachine5_fifo_in_payload_we};
-assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
-assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
-assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
-assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
-assign litedramcore_bankmachine5_sink_ready = litedramcore_bankmachine5_syncfifo5_writable;
-assign litedramcore_bankmachine5_syncfifo5_we = litedramcore_bankmachine5_sink_valid;
-assign litedramcore_bankmachine5_fifo_in_first = litedramcore_bankmachine5_sink_first;
-assign litedramcore_bankmachine5_fifo_in_last = litedramcore_bankmachine5_sink_last;
-assign litedramcore_bankmachine5_fifo_in_payload_we = litedramcore_bankmachine5_sink_payload_we;
-assign litedramcore_bankmachine5_fifo_in_payload_addr = litedramcore_bankmachine5_sink_payload_addr;
-assign litedramcore_bankmachine5_source_valid = litedramcore_bankmachine5_syncfifo5_readable;
-assign litedramcore_bankmachine5_source_first = litedramcore_bankmachine5_fifo_out_first;
-assign litedramcore_bankmachine5_source_last = litedramcore_bankmachine5_fifo_out_last;
-assign litedramcore_bankmachine5_source_payload_we = litedramcore_bankmachine5_fifo_out_payload_we;
-assign litedramcore_bankmachine5_source_payload_addr = litedramcore_bankmachine5_fifo_out_payload_addr;
-assign litedramcore_bankmachine5_syncfifo5_re = litedramcore_bankmachine5_source_ready;
-always @(*) begin
-    litedramcore_bankmachine5_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine5_replace) begin
-        litedramcore_bankmachine5_wrport_adr <= (litedramcore_bankmachine5_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine5_wrport_adr <= litedramcore_bankmachine5_produce;
-    end
-end
-assign litedramcore_bankmachine5_wrport_dat_w = litedramcore_bankmachine5_syncfifo5_din;
-assign litedramcore_bankmachine5_wrport_we = (litedramcore_bankmachine5_syncfifo5_we & (litedramcore_bankmachine5_syncfifo5_writable | litedramcore_bankmachine5_replace));
-assign litedramcore_bankmachine5_do_read = (litedramcore_bankmachine5_syncfifo5_readable & litedramcore_bankmachine5_syncfifo5_re);
-assign litedramcore_bankmachine5_rdport_adr = litedramcore_bankmachine5_consume;
-assign litedramcore_bankmachine5_syncfifo5_dout = litedramcore_bankmachine5_rdport_dat_r;
-assign litedramcore_bankmachine5_syncfifo5_writable = (litedramcore_bankmachine5_level != 5'd16);
-assign litedramcore_bankmachine5_syncfifo5_readable = (litedramcore_bankmachine5_level != 1'd0);
-assign litedramcore_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready);
-assign litedramcore_bankmachine5_pipe_valid_sink_valid = litedramcore_bankmachine5_sink_sink_valid;
-assign litedramcore_bankmachine5_sink_sink_ready = litedramcore_bankmachine5_pipe_valid_sink_ready;
-assign litedramcore_bankmachine5_pipe_valid_sink_first = litedramcore_bankmachine5_sink_sink_first;
-assign litedramcore_bankmachine5_pipe_valid_sink_last = litedramcore_bankmachine5_sink_sink_last;
-assign litedramcore_bankmachine5_pipe_valid_sink_payload_we = litedramcore_bankmachine5_sink_sink_payload_we;
-assign litedramcore_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_bankmachine5_sink_sink_payload_addr;
-assign litedramcore_bankmachine5_source_source_valid = litedramcore_bankmachine5_pipe_valid_source_valid;
-assign litedramcore_bankmachine5_pipe_valid_source_ready = litedramcore_bankmachine5_source_source_ready;
-assign litedramcore_bankmachine5_source_source_first = litedramcore_bankmachine5_pipe_valid_source_first;
-assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_pipe_valid_source_last;
-assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine5_next_state <= 4'd0;
-    litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
-    case (litedramcore_bankmachine5_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                if (litedramcore_bankmachine5_cmd_ready) begin
-                    litedramcore_bankmachine5_next_state <= 3'd5;
-                end
+always @(*) begin
+    main_litedramcore_bankmachine5_cmd_valid <= 1'd0;
+    case (builder_bankmachine5_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                if (litedramcore_bankmachine5_cmd_ready) begin
-                    litedramcore_bankmachine5_next_state <= 3'd7;
-                end
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine5_refresh_req)) begin
-                litedramcore_bankmachine5_next_state <= 1'd0;
-            end
         end
         3'd5: begin
-            litedramcore_bankmachine5_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine5_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine5_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine5_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
-                litedramcore_bankmachine5_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
-                                litedramcore_bankmachine5_next_state <= 2'd2;
-                            end
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
                         end else begin
-                            litedramcore_bankmachine5_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine5_next_state <= 2'd3;
                     end
                 end
             end
@@ -7743,15 +8254,41 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_row_close <= 1'd0;
+    case (builder_bankmachine5_state)
+        1'd1: begin
+            main_litedramcore_bankmachine5_row_close <= 1'd1;
+        end
+        2'd2: begin
+            main_litedramcore_bankmachine5_row_close <= 1'd1;
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            main_litedramcore_bankmachine5_row_close <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -7769,8 +8306,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7788,12 +8325,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -7804,18 +8341,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -7833,11 +8370,11 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
@@ -7855,13 +8392,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
-                                litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
+                                main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -7874,22 +8411,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -7904,8 +8441,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7923,14 +8460,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -7942,8 +8479,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7961,13 +8498,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
-                                litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
+                                main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -7980,8 +8517,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7999,13 +8536,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
-                                litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
+                                main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -8018,8 +8555,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8037,14 +8574,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
+                                main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
                             end
                         end else begin
                         end
@@ -8055,42 +8592,155 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine5_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+assign main_litedramcore_bankmachine6_sink_valid = main_litedramcore_bankmachine6_req_valid;
+assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_sink_ready;
+assign main_litedramcore_bankmachine6_sink_payload_we = main_litedramcore_bankmachine6_req_we;
+assign main_litedramcore_bankmachine6_sink_payload_addr = main_litedramcore_bankmachine6_req_addr;
+assign main_litedramcore_bankmachine6_sink_sink_valid = main_litedramcore_bankmachine6_source_valid;
+assign main_litedramcore_bankmachine6_source_ready = main_litedramcore_bankmachine6_sink_sink_ready;
+assign main_litedramcore_bankmachine6_sink_sink_first = main_litedramcore_bankmachine6_source_first;
+assign main_litedramcore_bankmachine6_sink_sink_last = main_litedramcore_bankmachine6_source_last;
+assign main_litedramcore_bankmachine6_sink_sink_payload_we = main_litedramcore_bankmachine6_source_payload_we;
+assign main_litedramcore_bankmachine6_sink_sink_payload_addr = main_litedramcore_bankmachine6_source_payload_addr;
+assign main_litedramcore_bankmachine6_source_source_ready = (main_litedramcore_bankmachine6_req_wdata_ready | main_litedramcore_bankmachine6_req_rdata_valid);
+assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_source_valid | main_litedramcore_bankmachine6_source_source_valid);
+assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_source_source_payload_addr[20:7]);
+assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
+always @(*) begin
+    main_litedramcore_bankmachine6_cmd_payload_a <= 14'd0;
+    if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine6_cmd_payload_a <= main_litedramcore_bankmachine6_source_source_payload_addr[20:7];
+    end else begin
+        main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write);
+assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
+assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine6_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine6_source_valid & main_litedramcore_bankmachine6_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine6_source_payload_addr[20:7] != main_litedramcore_bankmachine6_source_source_payload_addr[20:7])) begin
+            main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine6_syncfifo6_din = {main_litedramcore_bankmachine6_fifo_in_last, main_litedramcore_bankmachine6_fifo_in_first, main_litedramcore_bankmachine6_fifo_in_payload_addr, main_litedramcore_bankmachine6_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout;
+assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout;
+assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout;
+assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout;
+assign main_litedramcore_bankmachine6_sink_ready = main_litedramcore_bankmachine6_syncfifo6_writable;
+assign main_litedramcore_bankmachine6_syncfifo6_we = main_litedramcore_bankmachine6_sink_valid;
+assign main_litedramcore_bankmachine6_fifo_in_first = main_litedramcore_bankmachine6_sink_first;
+assign main_litedramcore_bankmachine6_fifo_in_last = main_litedramcore_bankmachine6_sink_last;
+assign main_litedramcore_bankmachine6_fifo_in_payload_we = main_litedramcore_bankmachine6_sink_payload_we;
+assign main_litedramcore_bankmachine6_fifo_in_payload_addr = main_litedramcore_bankmachine6_sink_payload_addr;
+assign main_litedramcore_bankmachine6_source_valid = main_litedramcore_bankmachine6_syncfifo6_readable;
+assign main_litedramcore_bankmachine6_source_first = main_litedramcore_bankmachine6_fifo_out_first;
+assign main_litedramcore_bankmachine6_source_last = main_litedramcore_bankmachine6_fifo_out_last;
+assign main_litedramcore_bankmachine6_source_payload_we = main_litedramcore_bankmachine6_fifo_out_payload_we;
+assign main_litedramcore_bankmachine6_source_payload_addr = main_litedramcore_bankmachine6_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine6_syncfifo6_re = main_litedramcore_bankmachine6_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine6_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine6_replace) begin
+        main_litedramcore_bankmachine6_wrport_adr <= (main_litedramcore_bankmachine6_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine6_wrport_adr <= main_litedramcore_bankmachine6_produce;
+    end
+end
+assign main_litedramcore_bankmachine6_wrport_dat_w = main_litedramcore_bankmachine6_syncfifo6_din;
+assign main_litedramcore_bankmachine6_wrport_we = (main_litedramcore_bankmachine6_syncfifo6_we & (main_litedramcore_bankmachine6_syncfifo6_writable | main_litedramcore_bankmachine6_replace));
+assign main_litedramcore_bankmachine6_do_read = (main_litedramcore_bankmachine6_syncfifo6_readable & main_litedramcore_bankmachine6_syncfifo6_re);
+assign main_litedramcore_bankmachine6_rdport_adr = main_litedramcore_bankmachine6_consume;
+assign main_litedramcore_bankmachine6_syncfifo6_dout = main_litedramcore_bankmachine6_rdport_dat_r;
+assign main_litedramcore_bankmachine6_syncfifo6_writable = (main_litedramcore_bankmachine6_level != 5'd16);
+assign main_litedramcore_bankmachine6_syncfifo6_readable = (main_litedramcore_bankmachine6_level != 1'd0);
+assign main_litedramcore_bankmachine6_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine6_pipe_valid_source_valid) | main_litedramcore_bankmachine6_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine6_pipe_valid_sink_valid = main_litedramcore_bankmachine6_sink_sink_valid;
+assign main_litedramcore_bankmachine6_sink_sink_ready = main_litedramcore_bankmachine6_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine6_pipe_valid_sink_first = main_litedramcore_bankmachine6_sink_sink_first;
+assign main_litedramcore_bankmachine6_pipe_valid_sink_last = main_litedramcore_bankmachine6_sink_sink_last;
+assign main_litedramcore_bankmachine6_pipe_valid_sink_payload_we = main_litedramcore_bankmachine6_sink_sink_payload_we;
+assign main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine6_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine6_source_source_valid = main_litedramcore_bankmachine6_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine6_pipe_valid_source_ready = main_litedramcore_bankmachine6_source_source_ready;
+assign main_litedramcore_bankmachine6_source_source_first = main_litedramcore_bankmachine6_pipe_valid_source_first;
+assign main_litedramcore_bankmachine6_source_source_last = main_litedramcore_bankmachine6_pipe_valid_source_last;
+assign main_litedramcore_bankmachine6_source_source_payload_we = main_litedramcore_bankmachine6_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine6_source_source_payload_addr = main_litedramcore_bankmachine6_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine6_next_state <= 4'd0;
+    builder_bankmachine6_next_state <= builder_bankmachine6_state;
+    case (builder_bankmachine6_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                if (main_litedramcore_bankmachine6_cmd_ready) begin
+                    builder_bankmachine6_next_state <= 3'd5;
+                end
+            end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                builder_bankmachine6_next_state <= 3'd5;
+            end
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                if (main_litedramcore_bankmachine6_cmd_ready) begin
+                    builder_bankmachine6_next_state <= 3'd7;
+                end
+            end
         end
         3'd4: begin
-            if (litedramcore_bankmachine5_twtpcon_ready) begin
-                litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+            if ((~main_litedramcore_bankmachine6_refresh_req)) begin
+                builder_bankmachine6_next_state <= 1'd0;
             end
         end
         3'd5: begin
+            builder_bankmachine6_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine6_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine6_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine6_next_state <= 1'd0;
         end
         default: begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
+                builder_bankmachine6_next_state <= 3'd4;
+            end else begin
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if ((main_litedramcore_bankmachine6_cmd_ready & main_litedramcore_bankmachine6_auto_precharge)) begin
+                                builder_bankmachine6_next_state <= 2'd2;
+                            end
+                        end else begin
+                            builder_bankmachine6_next_state <= 1'd1;
+                        end
+                    end else begin
+                        builder_bankmachine6_next_state <= 2'd3;
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_row_open <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -8108,19 +8758,13 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_cmd_valid <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_cmd_valid <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -8133,12 +8777,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            litedramcore_bankmachine5_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -8149,18 +8793,21 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_row_close <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
-            litedramcore_bankmachine5_row_close <= 1'd1;
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+            end
         end
         2'd2: begin
-            litedramcore_bankmachine5_row_close <= 1'd1;
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+            end
         end
         3'd4: begin
-            litedramcore_bankmachine5_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -8174,139 +8821,41 @@ always @(*) begin
         end
     endcase
 end
-assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid;
-assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready;
-assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we;
-assign litedramcore_bankmachine6_sink_payload_addr = litedramcore_bankmachine6_req_addr;
-assign litedramcore_bankmachine6_sink_sink_valid = litedramcore_bankmachine6_source_valid;
-assign litedramcore_bankmachine6_source_ready = litedramcore_bankmachine6_sink_sink_ready;
-assign litedramcore_bankmachine6_sink_sink_first = litedramcore_bankmachine6_source_first;
-assign litedramcore_bankmachine6_sink_sink_last = litedramcore_bankmachine6_source_last;
-assign litedramcore_bankmachine6_sink_sink_payload_we = litedramcore_bankmachine6_source_payload_we;
-assign litedramcore_bankmachine6_sink_sink_payload_addr = litedramcore_bankmachine6_source_payload_addr;
-assign litedramcore_bankmachine6_source_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
-assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_source_valid | litedramcore_bankmachine6_source_source_valid);
-assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_source_source_payload_addr[20:7]);
-assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
-always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_a <= 14'd0;
-    if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
-        litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_source_source_payload_addr[20:7];
-    end else begin
-        litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
-assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
-assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
-always @(*) begin
-    litedramcore_bankmachine6_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine6_source_valid & litedramcore_bankmachine6_source_source_valid)) begin
-        if ((litedramcore_bankmachine6_source_payload_addr[20:7] != litedramcore_bankmachine6_source_source_payload_addr[20:7])) begin
-            litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine6_syncfifo6_din = {litedramcore_bankmachine6_fifo_in_last, litedramcore_bankmachine6_fifo_in_first, litedramcore_bankmachine6_fifo_in_payload_addr, litedramcore_bankmachine6_fifo_in_payload_we};
-assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
-assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
-assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
-assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
-assign litedramcore_bankmachine6_sink_ready = litedramcore_bankmachine6_syncfifo6_writable;
-assign litedramcore_bankmachine6_syncfifo6_we = litedramcore_bankmachine6_sink_valid;
-assign litedramcore_bankmachine6_fifo_in_first = litedramcore_bankmachine6_sink_first;
-assign litedramcore_bankmachine6_fifo_in_last = litedramcore_bankmachine6_sink_last;
-assign litedramcore_bankmachine6_fifo_in_payload_we = litedramcore_bankmachine6_sink_payload_we;
-assign litedramcore_bankmachine6_fifo_in_payload_addr = litedramcore_bankmachine6_sink_payload_addr;
-assign litedramcore_bankmachine6_source_valid = litedramcore_bankmachine6_syncfifo6_readable;
-assign litedramcore_bankmachine6_source_first = litedramcore_bankmachine6_fifo_out_first;
-assign litedramcore_bankmachine6_source_last = litedramcore_bankmachine6_fifo_out_last;
-assign litedramcore_bankmachine6_source_payload_we = litedramcore_bankmachine6_fifo_out_payload_we;
-assign litedramcore_bankmachine6_source_payload_addr = litedramcore_bankmachine6_fifo_out_payload_addr;
-assign litedramcore_bankmachine6_syncfifo6_re = litedramcore_bankmachine6_source_ready;
-always @(*) begin
-    litedramcore_bankmachine6_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine6_replace) begin
-        litedramcore_bankmachine6_wrport_adr <= (litedramcore_bankmachine6_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine6_wrport_adr <= litedramcore_bankmachine6_produce;
-    end
-end
-assign litedramcore_bankmachine6_wrport_dat_w = litedramcore_bankmachine6_syncfifo6_din;
-assign litedramcore_bankmachine6_wrport_we = (litedramcore_bankmachine6_syncfifo6_we & (litedramcore_bankmachine6_syncfifo6_writable | litedramcore_bankmachine6_replace));
-assign litedramcore_bankmachine6_do_read = (litedramcore_bankmachine6_syncfifo6_readable & litedramcore_bankmachine6_syncfifo6_re);
-assign litedramcore_bankmachine6_rdport_adr = litedramcore_bankmachine6_consume;
-assign litedramcore_bankmachine6_syncfifo6_dout = litedramcore_bankmachine6_rdport_dat_r;
-assign litedramcore_bankmachine6_syncfifo6_writable = (litedramcore_bankmachine6_level != 5'd16);
-assign litedramcore_bankmachine6_syncfifo6_readable = (litedramcore_bankmachine6_level != 1'd0);
-assign litedramcore_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready);
-assign litedramcore_bankmachine6_pipe_valid_sink_valid = litedramcore_bankmachine6_sink_sink_valid;
-assign litedramcore_bankmachine6_sink_sink_ready = litedramcore_bankmachine6_pipe_valid_sink_ready;
-assign litedramcore_bankmachine6_pipe_valid_sink_first = litedramcore_bankmachine6_sink_sink_first;
-assign litedramcore_bankmachine6_pipe_valid_sink_last = litedramcore_bankmachine6_sink_sink_last;
-assign litedramcore_bankmachine6_pipe_valid_sink_payload_we = litedramcore_bankmachine6_sink_sink_payload_we;
-assign litedramcore_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_bankmachine6_sink_sink_payload_addr;
-assign litedramcore_bankmachine6_source_source_valid = litedramcore_bankmachine6_pipe_valid_source_valid;
-assign litedramcore_bankmachine6_pipe_valid_source_ready = litedramcore_bankmachine6_source_source_ready;
-assign litedramcore_bankmachine6_source_source_first = litedramcore_bankmachine6_pipe_valid_source_first;
-assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_pipe_valid_source_last;
-assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine6_next_state <= 4'd0;
-    litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
-    case (litedramcore_bankmachine6_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                if (litedramcore_bankmachine6_cmd_ready) begin
-                    litedramcore_bankmachine6_next_state <= 3'd5;
-                end
+always @(*) begin
+    main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine6_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                if (litedramcore_bankmachine6_cmd_ready) begin
-                    litedramcore_bankmachine6_next_state <= 3'd7;
-                end
-            end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine6_refresh_req)) begin
-                litedramcore_bankmachine6_next_state <= 1'd0;
-            end
         end
         3'd5: begin
-            litedramcore_bankmachine6_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine6_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine6_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine6_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
-                litedramcore_bankmachine6_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
-                                litedramcore_bankmachine6_next_state <= 2'd2;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
+                                main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+                            end else begin
                             end
                         end else begin
-                            litedramcore_bankmachine6_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine6_next_state <= 2'd3;
                     end
                 end
             end
@@ -8314,56 +8863,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine6_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
-            end
-        end
-        3'd4: begin
+            main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -8378,12 +8893,9 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
-            end
         end
         2'd2: begin
         end
@@ -8400,14 +8912,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
-                                litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
                             end else begin
+                                main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -8419,38 +8931,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine6_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
-            end
-        end
-        3'd4: begin
-            litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8468,14 +8950,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
+                                main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
                             end else begin
-                                litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -8487,8 +8969,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8506,13 +8988,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
-                                litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
+                                main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -8525,8 +9007,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8544,14 +9026,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
-                                litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
                             end else begin
+                                main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
                             end
                         end else begin
                         end
@@ -8563,8 +9045,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8572,6 +9054,9 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
+            if (main_litedramcore_bankmachine6_twtpcon_ready) begin
+                main_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -8582,37 +9067,22 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_row_open <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_row_open <= 1'd1;
+            end
         end
         3'd4: begin
-            if (litedramcore_bankmachine6_twtpcon_ready) begin
-                litedramcore_bankmachine6_refresh_gnt <= 1'd1;
-            end
         end
         3'd5: begin
         end
@@ -8627,15 +9097,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_row_open <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -8649,25 +9122,34 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_row_close <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_cmd_valid <= 1'd1;
-            end
+            main_litedramcore_bankmachine6_row_close <= 1'd1;
         end
         2'd2: begin
+            main_litedramcore_bankmachine6_row_close <= 1'd1;
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_cmd_valid <= 1'd1;
-            end
         end
         3'd4: begin
+            main_litedramcore_bankmachine6_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -8678,57 +9160,161 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            litedramcore_bankmachine6_cmd_valid <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine6_row_close <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+assign main_litedramcore_bankmachine7_sink_valid = main_litedramcore_bankmachine7_req_valid;
+assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_sink_ready;
+assign main_litedramcore_bankmachine7_sink_payload_we = main_litedramcore_bankmachine7_req_we;
+assign main_litedramcore_bankmachine7_sink_payload_addr = main_litedramcore_bankmachine7_req_addr;
+assign main_litedramcore_bankmachine7_sink_sink_valid = main_litedramcore_bankmachine7_source_valid;
+assign main_litedramcore_bankmachine7_source_ready = main_litedramcore_bankmachine7_sink_sink_ready;
+assign main_litedramcore_bankmachine7_sink_sink_first = main_litedramcore_bankmachine7_source_first;
+assign main_litedramcore_bankmachine7_sink_sink_last = main_litedramcore_bankmachine7_source_last;
+assign main_litedramcore_bankmachine7_sink_sink_payload_we = main_litedramcore_bankmachine7_source_payload_we;
+assign main_litedramcore_bankmachine7_sink_sink_payload_addr = main_litedramcore_bankmachine7_source_payload_addr;
+assign main_litedramcore_bankmachine7_source_source_ready = (main_litedramcore_bankmachine7_req_wdata_ready | main_litedramcore_bankmachine7_req_rdata_valid);
+assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_source_valid | main_litedramcore_bankmachine7_source_source_valid);
+assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_source_source_payload_addr[20:7]);
+assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
+always @(*) begin
+    main_litedramcore_bankmachine7_cmd_payload_a <= 14'd0;
+    if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine7_cmd_payload_a <= main_litedramcore_bankmachine7_source_source_payload_addr[20:7];
+    end else begin
+        main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write);
+assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
+assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine7_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine7_source_valid & main_litedramcore_bankmachine7_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine7_source_payload_addr[20:7] != main_litedramcore_bankmachine7_source_source_payload_addr[20:7])) begin
+            main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine7_syncfifo7_din = {main_litedramcore_bankmachine7_fifo_in_last, main_litedramcore_bankmachine7_fifo_in_first, main_litedramcore_bankmachine7_fifo_in_payload_addr, main_litedramcore_bankmachine7_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout;
+assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout;
+assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout;
+assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout;
+assign main_litedramcore_bankmachine7_sink_ready = main_litedramcore_bankmachine7_syncfifo7_writable;
+assign main_litedramcore_bankmachine7_syncfifo7_we = main_litedramcore_bankmachine7_sink_valid;
+assign main_litedramcore_bankmachine7_fifo_in_first = main_litedramcore_bankmachine7_sink_first;
+assign main_litedramcore_bankmachine7_fifo_in_last = main_litedramcore_bankmachine7_sink_last;
+assign main_litedramcore_bankmachine7_fifo_in_payload_we = main_litedramcore_bankmachine7_sink_payload_we;
+assign main_litedramcore_bankmachine7_fifo_in_payload_addr = main_litedramcore_bankmachine7_sink_payload_addr;
+assign main_litedramcore_bankmachine7_source_valid = main_litedramcore_bankmachine7_syncfifo7_readable;
+assign main_litedramcore_bankmachine7_source_first = main_litedramcore_bankmachine7_fifo_out_first;
+assign main_litedramcore_bankmachine7_source_last = main_litedramcore_bankmachine7_fifo_out_last;
+assign main_litedramcore_bankmachine7_source_payload_we = main_litedramcore_bankmachine7_fifo_out_payload_we;
+assign main_litedramcore_bankmachine7_source_payload_addr = main_litedramcore_bankmachine7_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine7_syncfifo7_re = main_litedramcore_bankmachine7_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine7_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine7_replace) begin
+        main_litedramcore_bankmachine7_wrport_adr <= (main_litedramcore_bankmachine7_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine7_wrport_adr <= main_litedramcore_bankmachine7_produce;
+    end
+end
+assign main_litedramcore_bankmachine7_wrport_dat_w = main_litedramcore_bankmachine7_syncfifo7_din;
+assign main_litedramcore_bankmachine7_wrport_we = (main_litedramcore_bankmachine7_syncfifo7_we & (main_litedramcore_bankmachine7_syncfifo7_writable | main_litedramcore_bankmachine7_replace));
+assign main_litedramcore_bankmachine7_do_read = (main_litedramcore_bankmachine7_syncfifo7_readable & main_litedramcore_bankmachine7_syncfifo7_re);
+assign main_litedramcore_bankmachine7_rdport_adr = main_litedramcore_bankmachine7_consume;
+assign main_litedramcore_bankmachine7_syncfifo7_dout = main_litedramcore_bankmachine7_rdport_dat_r;
+assign main_litedramcore_bankmachine7_syncfifo7_writable = (main_litedramcore_bankmachine7_level != 5'd16);
+assign main_litedramcore_bankmachine7_syncfifo7_readable = (main_litedramcore_bankmachine7_level != 1'd0);
+assign main_litedramcore_bankmachine7_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine7_pipe_valid_source_valid) | main_litedramcore_bankmachine7_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine7_pipe_valid_sink_valid = main_litedramcore_bankmachine7_sink_sink_valid;
+assign main_litedramcore_bankmachine7_sink_sink_ready = main_litedramcore_bankmachine7_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine7_pipe_valid_sink_first = main_litedramcore_bankmachine7_sink_sink_first;
+assign main_litedramcore_bankmachine7_pipe_valid_sink_last = main_litedramcore_bankmachine7_sink_sink_last;
+assign main_litedramcore_bankmachine7_pipe_valid_sink_payload_we = main_litedramcore_bankmachine7_sink_sink_payload_we;
+assign main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine7_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine7_source_source_valid = main_litedramcore_bankmachine7_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine7_pipe_valid_source_ready = main_litedramcore_bankmachine7_source_source_ready;
+assign main_litedramcore_bankmachine7_source_source_first = main_litedramcore_bankmachine7_pipe_valid_source_first;
+assign main_litedramcore_bankmachine7_source_source_last = main_litedramcore_bankmachine7_pipe_valid_source_last;
+assign main_litedramcore_bankmachine7_source_source_payload_we = main_litedramcore_bankmachine7_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine7_source_source_payload_addr = main_litedramcore_bankmachine7_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine7_next_state <= 4'd0;
+    builder_bankmachine7_next_state <= builder_bankmachine7_state;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            litedramcore_bankmachine6_row_close <= 1'd1;
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                if (main_litedramcore_bankmachine7_cmd_ready) begin
+                    builder_bankmachine7_next_state <= 3'd5;
+                end
+            end
         end
         2'd2: begin
-            litedramcore_bankmachine6_row_close <= 1'd1;
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                builder_bankmachine7_next_state <= 3'd5;
+            end
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                if (main_litedramcore_bankmachine7_cmd_ready) begin
+                    builder_bankmachine7_next_state <= 3'd7;
+                end
+            end
         end
         3'd4: begin
-            litedramcore_bankmachine6_row_close <= 1'd1;
+            if ((~main_litedramcore_bankmachine7_refresh_req)) begin
+                builder_bankmachine7_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine7_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine7_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine7_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine7_next_state <= 1'd0;
         end
         default: begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
+                builder_bankmachine7_next_state <= 3'd4;
+            end else begin
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if ((main_litedramcore_bankmachine7_cmd_ready & main_litedramcore_bankmachine7_auto_precharge)) begin
+                                builder_bankmachine7_next_state <= 2'd2;
+                            end
+                        end else begin
+                            builder_bankmachine7_next_state <= 1'd1;
+                        end
+                    end else begin
+                        builder_bankmachine7_next_state <= 2'd3;
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -8745,139 +9331,41 @@ always @(*) begin
         end
     endcase
 end
-assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid;
-assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready;
-assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we;
-assign litedramcore_bankmachine7_sink_payload_addr = litedramcore_bankmachine7_req_addr;
-assign litedramcore_bankmachine7_sink_sink_valid = litedramcore_bankmachine7_source_valid;
-assign litedramcore_bankmachine7_source_ready = litedramcore_bankmachine7_sink_sink_ready;
-assign litedramcore_bankmachine7_sink_sink_first = litedramcore_bankmachine7_source_first;
-assign litedramcore_bankmachine7_sink_sink_last = litedramcore_bankmachine7_source_last;
-assign litedramcore_bankmachine7_sink_sink_payload_we = litedramcore_bankmachine7_source_payload_we;
-assign litedramcore_bankmachine7_sink_sink_payload_addr = litedramcore_bankmachine7_source_payload_addr;
-assign litedramcore_bankmachine7_source_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
-assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_source_valid | litedramcore_bankmachine7_source_source_valid);
-assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_source_source_payload_addr[20:7]);
-assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
-always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_a <= 14'd0;
-    if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
-        litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_source_source_payload_addr[20:7];
-    end else begin
-        litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
-assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
-assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
-always @(*) begin
-    litedramcore_bankmachine7_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine7_source_valid & litedramcore_bankmachine7_source_source_valid)) begin
-        if ((litedramcore_bankmachine7_source_payload_addr[20:7] != litedramcore_bankmachine7_source_source_payload_addr[20:7])) begin
-            litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine7_syncfifo7_din = {litedramcore_bankmachine7_fifo_in_last, litedramcore_bankmachine7_fifo_in_first, litedramcore_bankmachine7_fifo_in_payload_addr, litedramcore_bankmachine7_fifo_in_payload_we};
-assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
-assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
-assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
-assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
-assign litedramcore_bankmachine7_sink_ready = litedramcore_bankmachine7_syncfifo7_writable;
-assign litedramcore_bankmachine7_syncfifo7_we = litedramcore_bankmachine7_sink_valid;
-assign litedramcore_bankmachine7_fifo_in_first = litedramcore_bankmachine7_sink_first;
-assign litedramcore_bankmachine7_fifo_in_last = litedramcore_bankmachine7_sink_last;
-assign litedramcore_bankmachine7_fifo_in_payload_we = litedramcore_bankmachine7_sink_payload_we;
-assign litedramcore_bankmachine7_fifo_in_payload_addr = litedramcore_bankmachine7_sink_payload_addr;
-assign litedramcore_bankmachine7_source_valid = litedramcore_bankmachine7_syncfifo7_readable;
-assign litedramcore_bankmachine7_source_first = litedramcore_bankmachine7_fifo_out_first;
-assign litedramcore_bankmachine7_source_last = litedramcore_bankmachine7_fifo_out_last;
-assign litedramcore_bankmachine7_source_payload_we = litedramcore_bankmachine7_fifo_out_payload_we;
-assign litedramcore_bankmachine7_source_payload_addr = litedramcore_bankmachine7_fifo_out_payload_addr;
-assign litedramcore_bankmachine7_syncfifo7_re = litedramcore_bankmachine7_source_ready;
-always @(*) begin
-    litedramcore_bankmachine7_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine7_replace) begin
-        litedramcore_bankmachine7_wrport_adr <= (litedramcore_bankmachine7_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine7_wrport_adr <= litedramcore_bankmachine7_produce;
-    end
-end
-assign litedramcore_bankmachine7_wrport_dat_w = litedramcore_bankmachine7_syncfifo7_din;
-assign litedramcore_bankmachine7_wrport_we = (litedramcore_bankmachine7_syncfifo7_we & (litedramcore_bankmachine7_syncfifo7_writable | litedramcore_bankmachine7_replace));
-assign litedramcore_bankmachine7_do_read = (litedramcore_bankmachine7_syncfifo7_readable & litedramcore_bankmachine7_syncfifo7_re);
-assign litedramcore_bankmachine7_rdport_adr = litedramcore_bankmachine7_consume;
-assign litedramcore_bankmachine7_syncfifo7_dout = litedramcore_bankmachine7_rdport_dat_r;
-assign litedramcore_bankmachine7_syncfifo7_writable = (litedramcore_bankmachine7_level != 5'd16);
-assign litedramcore_bankmachine7_syncfifo7_readable = (litedramcore_bankmachine7_level != 1'd0);
-assign litedramcore_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready);
-assign litedramcore_bankmachine7_pipe_valid_sink_valid = litedramcore_bankmachine7_sink_sink_valid;
-assign litedramcore_bankmachine7_sink_sink_ready = litedramcore_bankmachine7_pipe_valid_sink_ready;
-assign litedramcore_bankmachine7_pipe_valid_sink_first = litedramcore_bankmachine7_sink_sink_first;
-assign litedramcore_bankmachine7_pipe_valid_sink_last = litedramcore_bankmachine7_sink_sink_last;
-assign litedramcore_bankmachine7_pipe_valid_sink_payload_we = litedramcore_bankmachine7_sink_sink_payload_we;
-assign litedramcore_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_bankmachine7_sink_sink_payload_addr;
-assign litedramcore_bankmachine7_source_source_valid = litedramcore_bankmachine7_pipe_valid_source_valid;
-assign litedramcore_bankmachine7_pipe_valid_source_ready = litedramcore_bankmachine7_source_source_ready;
-assign litedramcore_bankmachine7_source_source_first = litedramcore_bankmachine7_pipe_valid_source_first;
-assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_pipe_valid_source_last;
-assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine7_next_state <= 4'd0;
-    litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
-    case (litedramcore_bankmachine7_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                if (litedramcore_bankmachine7_cmd_ready) begin
-                    litedramcore_bankmachine7_next_state <= 3'd5;
-                end
+always @(*) begin
+    main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine7_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                if (litedramcore_bankmachine7_cmd_ready) begin
-                    litedramcore_bankmachine7_next_state <= 3'd7;
-                end
-            end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine7_refresh_req)) begin
-                litedramcore_bankmachine7_next_state <= 1'd0;
-            end
         end
         3'd5: begin
-            litedramcore_bankmachine7_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine7_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine7_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine7_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
-                litedramcore_bankmachine7_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
-                                litedramcore_bankmachine7_next_state <= 2'd2;
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
+                                main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+                            end else begin
                             end
                         end else begin
-                            litedramcore_bankmachine7_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine7_next_state <= 2'd3;
                     end
                 end
             end
@@ -8885,22 +9373,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -8915,8 +9403,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8934,14 +9422,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -8953,8 +9441,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8972,13 +9460,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
-                                litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
+                                main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -8991,8 +9479,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9010,13 +9498,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
-                                litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
+                                main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -9029,8 +9517,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9048,14 +9536,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
+                                main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
                             end
                         end else begin
                         end
@@ -9067,8 +9555,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9076,8 +9564,8 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine7_twtpcon_ready) begin
-                litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+            if (main_litedramcore_bankmachine7_twtpcon_ready) begin
+                main_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
             end
         end
         3'd5: begin
@@ -9093,15 +9581,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_row_open <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_row_open <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -9119,18 +9607,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -9144,12 +9632,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            litedramcore_bankmachine7_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -9160,67 +9648,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_row_close <= 1'd0;
-    case (litedramcore_bankmachine7_state)
-        1'd1: begin
-            litedramcore_bankmachine7_row_close <= 1'd1;
-        end
-        2'd2: begin
-            litedramcore_bankmachine7_row_close <= 1'd1;
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            litedramcore_bankmachine7_row_close <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine7_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_row_close <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd2: begin
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -9231,34 +9670,19 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -9276,12 +9700,9 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
-            end
         end
         2'd2: begin
         end
@@ -9298,15 +9719,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
-                                litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
-                            end else begin
-                            end
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -9316,266 +9734,266 @@ always @(*) begin
         end
     endcase
 end
-assign litedramcore_rdcmdphase = (a7ddrphy_rdphase_storage - 1'd1);
-assign litedramcore_wrcmdphase = (a7ddrphy_wrphase_storage - 1'd1);
-assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
-assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
-assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready);
-assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read));
-assign litedramcore_cas_allowed = litedramcore_tccdcon_ready;
-assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
-assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read));
-assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write));
-assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0);
-assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0);
-assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt);
-assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata};
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign main_litedramcore_nphases = (main_a7ddrphy_rdphase_storage - 1'd1);
+assign main_litedramcore_rdphase = (main_a7ddrphy_wrphase_storage - 1'd1);
+assign main_litedramcore_trrdcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we)));
+assign main_litedramcore_tfawcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we)));
+assign main_litedramcore_ras_allowed = (main_litedramcore_trrdcon_ready & main_litedramcore_tfawcon_ready);
+assign main_litedramcore_tccdcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_cmd_payload_is_write | main_litedramcore_choose_req_cmd_payload_is_read));
+assign main_litedramcore_cas_allowed = main_litedramcore_tccdcon_ready;
+assign main_litedramcore_twtrcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+assign main_litedramcore_read_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_read) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_read)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_read)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_read)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_read)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_read)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_read)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_read));
+assign main_litedramcore_write_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_write) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_write)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_write)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_write)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_write)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_write)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_write)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_write));
+assign main_litedramcore_max_time0 = (main_litedramcore_time0 == 1'd0);
+assign main_litedramcore_max_time1 = (main_litedramcore_time1 == 1'd0);
+assign main_litedramcore_bankmachine0_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine1_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine2_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine3_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine4_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine5_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine6_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine7_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_go_to_refresh = (((((((main_litedramcore_bankmachine0_refresh_gnt & main_litedramcore_bankmachine1_refresh_gnt) & main_litedramcore_bankmachine2_refresh_gnt) & main_litedramcore_bankmachine3_refresh_gnt) & main_litedramcore_bankmachine4_refresh_gnt) & main_litedramcore_bankmachine5_refresh_gnt) & main_litedramcore_bankmachine6_refresh_gnt) & main_litedramcore_bankmachine7_refresh_gnt);
+assign main_litedramcore_interface_rdata = {main_litedramcore_dfi_p3_rddata, main_litedramcore_dfi_p2_rddata, main_litedramcore_dfi_p1_rddata, main_litedramcore_dfi_p0_rddata};
+assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
+assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
+assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
+assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
+assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
+assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
+assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
+assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
 always @(*) begin
-    litedramcore_choose_cmd_valids <= 8'd0;
-    litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids <= 8'd0;
+    main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
 end
-assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
-assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
-assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1;
-assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
-assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
-assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
-assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
+assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids;
+assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_self0;
+assign main_litedramcore_choose_cmd_cmd_payload_a = builder_rhs_self1;
+assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_self2;
+assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_self3;
+assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_self4;
+assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_self5;
 always @(*) begin
-    litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
-    if (litedramcore_choose_cmd_cmd_valid) begin
-        litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
+    main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
+    if (main_litedramcore_choose_cmd_cmd_valid) begin
+        main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_self0;
     end
 end
 always @(*) begin
-    litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
-    if (litedramcore_choose_cmd_cmd_valid) begin
-        litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
+    main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
+    if (main_litedramcore_choose_cmd_cmd_valid) begin
+        main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_self1;
     end
 end
 always @(*) begin
-    litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
-    if (litedramcore_choose_cmd_cmd_valid) begin
-        litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
+    main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
+    if (main_litedramcore_choose_cmd_cmd_valid) begin
+        main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_self2;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
-        litedramcore_bankmachine0_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine0_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin
+        main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
-        litedramcore_bankmachine0_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin
+        main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
-        litedramcore_bankmachine1_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine1_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin
+        main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
-        litedramcore_bankmachine1_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin
+        main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
-        litedramcore_bankmachine2_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine2_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin
+        main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
-        litedramcore_bankmachine2_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin
+        main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
-        litedramcore_bankmachine3_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine3_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin
+        main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
-        litedramcore_bankmachine3_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin
+        main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
-        litedramcore_bankmachine4_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine4_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin
+        main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
-        litedramcore_bankmachine4_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin
+        main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
-        litedramcore_bankmachine5_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine5_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin
+        main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
-        litedramcore_bankmachine5_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin
+        main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
-        litedramcore_bankmachine6_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine6_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin
+        main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
-        litedramcore_bankmachine6_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin
+        main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
-        litedramcore_bankmachine7_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine7_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin
+        main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
-        litedramcore_bankmachine7_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin
+        main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
     end
 end
-assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
+assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid));
 always @(*) begin
-    litedramcore_choose_req_valids <= 8'd0;
-    litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids <= 8'd0;
+    main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
 end
-assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
-assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
-assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7;
-assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8;
-assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9;
-assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
-assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
+assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids;
+assign main_litedramcore_choose_req_cmd_valid = builder_rhs_self6;
+assign main_litedramcore_choose_req_cmd_payload_a = builder_rhs_self7;
+assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_self8;
+assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_self9;
+assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_self10;
+assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_self11;
 always @(*) begin
-    litedramcore_choose_req_cmd_payload_cas <= 1'd0;
-    if (litedramcore_choose_req_cmd_valid) begin
-        litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
+    main_litedramcore_choose_req_cmd_payload_cas <= 1'd0;
+    if (main_litedramcore_choose_req_cmd_valid) begin
+        main_litedramcore_choose_req_cmd_payload_cas <= builder_t_self3;
     end
 end
 always @(*) begin
-    litedramcore_choose_req_cmd_payload_ras <= 1'd0;
-    if (litedramcore_choose_req_cmd_valid) begin
-        litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
+    main_litedramcore_choose_req_cmd_payload_ras <= 1'd0;
+    if (main_litedramcore_choose_req_cmd_valid) begin
+        main_litedramcore_choose_req_cmd_payload_ras <= builder_t_self4;
     end
 end
 always @(*) begin
-    litedramcore_choose_req_cmd_payload_we <= 1'd0;
-    if (litedramcore_choose_req_cmd_valid) begin
-        litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
+    main_litedramcore_choose_req_cmd_payload_we <= 1'd0;
+    if (main_litedramcore_choose_req_cmd_valid) begin
+        main_litedramcore_choose_req_cmd_payload_we <= builder_t_self5;
     end
 end
-assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
-assign litedramcore_dfi_p0_reset_n = 1'd1;
-assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}};
-assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}};
-assign litedramcore_dfi_p1_reset_n = 1'd1;
-assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}};
-assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}};
-assign litedramcore_dfi_p2_reset_n = 1'd1;
-assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}};
-assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}};
-assign litedramcore_dfi_p3_reset_n = 1'd1;
-assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}};
-assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}};
-assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]);
+assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid));
+assign main_litedramcore_dfi_p0_reset_n = 1'd1;
+assign main_litedramcore_dfi_p0_cke = {1{main_litedramcore_steerer4}};
+assign main_litedramcore_dfi_p0_odt = {1{main_litedramcore_steerer5}};
+assign main_litedramcore_dfi_p1_reset_n = 1'd1;
+assign main_litedramcore_dfi_p1_cke = {1{main_litedramcore_steerer6}};
+assign main_litedramcore_dfi_p1_odt = {1{main_litedramcore_steerer7}};
+assign main_litedramcore_dfi_p2_reset_n = 1'd1;
+assign main_litedramcore_dfi_p2_cke = {1{main_litedramcore_steerer8}};
+assign main_litedramcore_dfi_p2_odt = {1{main_litedramcore_steerer9}};
+assign main_litedramcore_dfi_p3_reset_n = 1'd1;
+assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer10}};
+assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer11}};
+assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]);
 always @(*) begin
-    litedramcore_multiplexer_next_state <= 4'd0;
-    litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
-    case (litedramcore_multiplexer_state)
+    builder_multiplexer_next_state <= 4'd0;
+    builder_multiplexer_next_state <= builder_multiplexer_state;
+    case (builder_multiplexer_state)
         1'd1: begin
-            if (litedramcore_read_available) begin
-                if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
-                    litedramcore_multiplexer_next_state <= 2'd3;
+            if (main_litedramcore_read_available) begin
+                if (((~main_litedramcore_write_available) | main_litedramcore_max_time1)) begin
+                    builder_multiplexer_next_state <= 2'd3;
                 end
             end
-            if (litedramcore_go_to_refresh) begin
-                litedramcore_multiplexer_next_state <= 2'd2;
+            if (main_litedramcore_go_to_refresh) begin
+                builder_multiplexer_next_state <= 2'd2;
             end
         end
         2'd2: begin
-            if (litedramcore_cmd_last) begin
-                litedramcore_multiplexer_next_state <= 1'd0;
+            if (main_litedramcore_cmd_last) begin
+                builder_multiplexer_next_state <= 1'd0;
             end
         end
         2'd3: begin
-            if (litedramcore_twtrcon_ready) begin
-                litedramcore_multiplexer_next_state <= 1'd0;
+            if (main_litedramcore_twtrcon_ready) begin
+                builder_multiplexer_next_state <= 1'd0;
             end
         end
         3'd4: begin
-            litedramcore_multiplexer_next_state <= 3'd5;
+            builder_multiplexer_next_state <= 3'd5;
         end
         3'd5: begin
-            litedramcore_multiplexer_next_state <= 3'd6;
+            builder_multiplexer_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_multiplexer_next_state <= 3'd7;
+            builder_multiplexer_next_state <= 3'd7;
         end
         3'd7: begin
-            litedramcore_multiplexer_next_state <= 4'd8;
+            builder_multiplexer_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_multiplexer_next_state <= 4'd9;
+            builder_multiplexer_next_state <= 4'd9;
         end
         4'd9: begin
-            litedramcore_multiplexer_next_state <= 4'd10;
+            builder_multiplexer_next_state <= 4'd10;
         end
         4'd10: begin
-            litedramcore_multiplexer_next_state <= 1'd1;
+            builder_multiplexer_next_state <= 1'd1;
         end
         default: begin
-            if (litedramcore_write_available) begin
-                if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
-                    litedramcore_multiplexer_next_state <= 3'd4;
+            if (main_litedramcore_write_available) begin
+                if (((~main_litedramcore_read_available) | main_litedramcore_max_time0)) begin
+                    builder_multiplexer_next_state <= 3'd4;
                 end
             end
-            if (litedramcore_go_to_refresh) begin
-                litedramcore_multiplexer_next_state <= 2'd2;
+            if (main_litedramcore_go_to_refresh) begin
+                builder_multiplexer_next_state <= 2'd2;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_steerer_sel0 <= 2'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_steerer0 <= 2'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer_sel0 <= 1'd0;
-            if ((a7ddrphy_wrphase_storage == 1'd0)) begin
-                litedramcore_steerer_sel0 <= 2'd2;
+            main_litedramcore_steerer0 <= 1'd0;
+            if ((main_a7ddrphy_wrphase_storage == 1'd0)) begin
+                main_litedramcore_steerer0 <= 2'd2;
             end
-            if ((litedramcore_wrcmdphase == 1'd0)) begin
-                litedramcore_steerer_sel0 <= 1'd1;
+            if ((main_litedramcore_rdphase == 1'd0)) begin
+                main_litedramcore_steerer0 <= 1'd1;
             end
         end
         2'd2: begin
-            litedramcore_steerer_sel0 <= 2'd3;
+            main_litedramcore_steerer0 <= 2'd3;
         end
         2'd3: begin
         end
@@ -9594,23 +10012,23 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_steerer_sel0 <= 1'd0;
-            if ((a7ddrphy_rdphase_storage == 1'd0)) begin
-                litedramcore_steerer_sel0 <= 2'd2;
+            main_litedramcore_steerer0 <= 1'd0;
+            if ((main_a7ddrphy_rdphase_storage == 1'd0)) begin
+                main_litedramcore_steerer0 <= 2'd2;
             end
-            if ((litedramcore_rdcmdphase == 1'd0)) begin
-                litedramcore_steerer_sel0 <= 1'd1;
+            if ((main_litedramcore_nphases == 1'd0)) begin
+                main_litedramcore_steerer0 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_cmd_ready <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_cmd_ready <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
         end
         2'd2: begin
-            litedramcore_cmd_ready <= 1'd1;
+            main_litedramcore_cmd_ready <= 1'd1;
         end
         2'd3: begin
         end
@@ -9633,15 +10051,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_steerer_sel1 <= 2'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_steerer1 <= 2'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer_sel1 <= 1'd0;
-            if ((a7ddrphy_wrphase_storage == 1'd1)) begin
-                litedramcore_steerer_sel1 <= 2'd2;
+            main_litedramcore_steerer1 <= 1'd0;
+            if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin
+                main_litedramcore_steerer1 <= 2'd2;
             end
-            if ((litedramcore_wrcmdphase == 1'd1)) begin
-                litedramcore_steerer_sel1 <= 1'd1;
+            if ((main_litedramcore_rdphase == 1'd1)) begin
+                main_litedramcore_steerer1 <= 1'd1;
             end
         end
         2'd2: begin
@@ -9663,26 +10081,26 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_steerer_sel1 <= 1'd0;
-            if ((a7ddrphy_rdphase_storage == 1'd1)) begin
-                litedramcore_steerer_sel1 <= 2'd2;
+            main_litedramcore_steerer1 <= 1'd0;
+            if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin
+                main_litedramcore_steerer1 <= 2'd2;
             end
-            if ((litedramcore_rdcmdphase == 1'd1)) begin
-                litedramcore_steerer_sel1 <= 1'd1;
+            if ((main_litedramcore_nphases == 1'd1)) begin
+                main_litedramcore_steerer1 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_steerer_sel2 <= 2'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_steerer2 <= 2'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer_sel2 <= 1'd0;
-            if ((a7ddrphy_wrphase_storage == 2'd2)) begin
-                litedramcore_steerer_sel2 <= 2'd2;
+            main_litedramcore_steerer2 <= 1'd0;
+            if ((main_a7ddrphy_wrphase_storage == 2'd2)) begin
+                main_litedramcore_steerer2 <= 2'd2;
             end
-            if ((litedramcore_wrcmdphase == 2'd2)) begin
-                litedramcore_steerer_sel2 <= 1'd1;
+            if ((main_litedramcore_rdphase == 2'd2)) begin
+                main_litedramcore_steerer2 <= 1'd1;
             end
         end
         2'd2: begin
@@ -9704,23 +10122,23 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_steerer_sel2 <= 1'd0;
-            if ((a7ddrphy_rdphase_storage == 2'd2)) begin
-                litedramcore_steerer_sel2 <= 2'd2;
+            main_litedramcore_steerer2 <= 1'd0;
+            if ((main_a7ddrphy_rdphase_storage == 2'd2)) begin
+                main_litedramcore_steerer2 <= 2'd2;
             end
-            if ((litedramcore_rdcmdphase == 2'd2)) begin
-                litedramcore_steerer_sel2 <= 1'd1;
+            if ((main_litedramcore_nphases == 2'd2)) begin
+                main_litedramcore_steerer2 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_cmd_want_activates <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_choose_cmd_want_activates <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
             if (1'd0) begin
             end else begin
-                litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+                main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
             end
         end
         2'd2: begin
@@ -9744,21 +10162,21 @@ always @(*) begin
         default: begin
             if (1'd0) begin
             end else begin
-                litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+                main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_steerer_sel3 <= 2'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_steerer3 <= 2'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer_sel3 <= 1'd0;
-            if ((a7ddrphy_wrphase_storage == 2'd3)) begin
-                litedramcore_steerer_sel3 <= 2'd2;
+            main_litedramcore_steerer3 <= 1'd0;
+            if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin
+                main_litedramcore_steerer3 <= 2'd2;
             end
-            if ((litedramcore_wrcmdphase == 2'd3)) begin
-                litedramcore_steerer_sel3 <= 1'd1;
+            if ((main_litedramcore_rdphase == 2'd3)) begin
+                main_litedramcore_steerer3 <= 1'd1;
             end
         end
         2'd2: begin
@@ -9780,19 +10198,19 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_steerer_sel3 <= 1'd0;
-            if ((a7ddrphy_rdphase_storage == 2'd3)) begin
-                litedramcore_steerer_sel3 <= 2'd2;
+            main_litedramcore_steerer3 <= 1'd0;
+            if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin
+                main_litedramcore_steerer3 <= 2'd2;
             end
-            if ((litedramcore_rdcmdphase == 2'd3)) begin
-                litedramcore_steerer_sel3 <= 1'd1;
+            if ((main_litedramcore_nphases == 2'd3)) begin
+                main_litedramcore_steerer3 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_en0 <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_en0 <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9814,17 +10232,17 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_en0 <= 1'd1;
+            main_litedramcore_en0 <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_cmd_cmd_ready <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
             if (1'd0) begin
             end else begin
-                litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+                main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
             end
         end
         2'd2: begin
@@ -9848,14 +10266,14 @@ always @(*) begin
         default: begin
             if (1'd0) begin
             end else begin
-                litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+                main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_req_want_reads <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_choose_req_want_reads <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9877,15 +10295,15 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_choose_req_want_reads <= 1'd1;
+            main_litedramcore_choose_req_want_reads <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_req_want_writes <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_choose_req_want_writes <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_choose_req_want_writes <= 1'd1;
+            main_litedramcore_choose_req_want_writes <= 1'd1;
         end
         2'd2: begin
         end
@@ -9910,14 +10328,10 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_choose_req_cmd_ready <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_en1 <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            if (1'd0) begin
-                litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
-            end else begin
-                litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
-            end
+            main_litedramcore_en1 <= 1'd1;
         end
         2'd2: begin
         end
@@ -9938,19 +10352,18 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            if (1'd0) begin
-                litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
-            end else begin
-                litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_en1 <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_choose_req_cmd_ready <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_en1 <= 1'd1;
+            if (1'd0) begin
+                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+            end else begin
+                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
+            end
         end
         2'd2: begin
         end
@@ -9971,2011 +10384,2013 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
+            if (1'd0) begin
+                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+            end else begin
+                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
+            end
         end
     endcase
 end
-assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
-assign litedramcore_interface_bank0_addr = rhs_array_muxed12;
-assign litedramcore_interface_bank0_we = rhs_array_muxed13;
-assign litedramcore_interface_bank0_valid = rhs_array_muxed14;
-assign litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock));
-assign litedramcore_interface_bank1_addr = rhs_array_muxed15;
-assign litedramcore_interface_bank1_we = rhs_array_muxed16;
-assign litedramcore_interface_bank1_valid = rhs_array_muxed17;
-assign litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock));
-assign litedramcore_interface_bank2_addr = rhs_array_muxed18;
-assign litedramcore_interface_bank2_we = rhs_array_muxed19;
-assign litedramcore_interface_bank2_valid = rhs_array_muxed20;
-assign litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock));
-assign litedramcore_interface_bank3_addr = rhs_array_muxed21;
-assign litedramcore_interface_bank3_we = rhs_array_muxed22;
-assign litedramcore_interface_bank3_valid = rhs_array_muxed23;
-assign litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock));
-assign litedramcore_interface_bank4_addr = rhs_array_muxed24;
-assign litedramcore_interface_bank4_we = rhs_array_muxed25;
-assign litedramcore_interface_bank4_valid = rhs_array_muxed26;
-assign litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock));
-assign litedramcore_interface_bank5_addr = rhs_array_muxed27;
-assign litedramcore_interface_bank5_we = rhs_array_muxed28;
-assign litedramcore_interface_bank5_valid = rhs_array_muxed29;
-assign litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock));
-assign litedramcore_interface_bank6_addr = rhs_array_muxed30;
-assign litedramcore_interface_bank6_we = rhs_array_muxed31;
-assign litedramcore_interface_bank6_valid = rhs_array_muxed32;
-assign litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock));
-assign litedramcore_interface_bank7_addr = rhs_array_muxed33;
-assign litedramcore_interface_bank7_we = rhs_array_muxed34;
-assign litedramcore_interface_bank7_valid = rhs_array_muxed35;
-assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready));
-assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1;
-assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8;
-always @(*) begin
-    litedramcore_interface_wdata <= 128'd0;
-    case ({litedramcore_new_master_wdata_ready1})
+assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock));
+assign main_litedramcore_interface_bank0_addr = builder_rhs_self12;
+assign main_litedramcore_interface_bank0_we = builder_rhs_self13;
+assign main_litedramcore_interface_bank0_valid = builder_rhs_self14;
+assign builder_roundrobin1_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin1_ce = ((~main_litedramcore_interface_bank1_valid) & (~main_litedramcore_interface_bank1_lock));
+assign main_litedramcore_interface_bank1_addr = builder_rhs_self15;
+assign main_litedramcore_interface_bank1_we = builder_rhs_self16;
+assign main_litedramcore_interface_bank1_valid = builder_rhs_self17;
+assign builder_roundrobin2_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin2_ce = ((~main_litedramcore_interface_bank2_valid) & (~main_litedramcore_interface_bank2_lock));
+assign main_litedramcore_interface_bank2_addr = builder_rhs_self18;
+assign main_litedramcore_interface_bank2_we = builder_rhs_self19;
+assign main_litedramcore_interface_bank2_valid = builder_rhs_self20;
+assign builder_roundrobin3_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin3_ce = ((~main_litedramcore_interface_bank3_valid) & (~main_litedramcore_interface_bank3_lock));
+assign main_litedramcore_interface_bank3_addr = builder_rhs_self21;
+assign main_litedramcore_interface_bank3_we = builder_rhs_self22;
+assign main_litedramcore_interface_bank3_valid = builder_rhs_self23;
+assign builder_roundrobin4_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin4_ce = ((~main_litedramcore_interface_bank4_valid) & (~main_litedramcore_interface_bank4_lock));
+assign main_litedramcore_interface_bank4_addr = builder_rhs_self24;
+assign main_litedramcore_interface_bank4_we = builder_rhs_self25;
+assign main_litedramcore_interface_bank4_valid = builder_rhs_self26;
+assign builder_roundrobin5_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin5_ce = ((~main_litedramcore_interface_bank5_valid) & (~main_litedramcore_interface_bank5_lock));
+assign main_litedramcore_interface_bank5_addr = builder_rhs_self27;
+assign main_litedramcore_interface_bank5_we = builder_rhs_self28;
+assign main_litedramcore_interface_bank5_valid = builder_rhs_self29;
+assign builder_roundrobin6_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin6_ce = ((~main_litedramcore_interface_bank6_valid) & (~main_litedramcore_interface_bank6_lock));
+assign main_litedramcore_interface_bank6_addr = builder_rhs_self30;
+assign main_litedramcore_interface_bank6_we = builder_rhs_self31;
+assign main_litedramcore_interface_bank6_valid = builder_rhs_self32;
+assign builder_roundrobin7_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin7_ce = ((~main_litedramcore_interface_bank7_valid) & (~main_litedramcore_interface_bank7_lock));
+assign main_litedramcore_interface_bank7_addr = builder_rhs_self33;
+assign main_litedramcore_interface_bank7_we = builder_rhs_self34;
+assign main_litedramcore_interface_bank7_valid = builder_rhs_self35;
+assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready));
+assign main_user_port_wdata_ready = builder_new_master_wdata_ready1;
+assign main_user_port_rdata_valid = builder_new_master_rdata_valid8;
+always @(*) begin
+    main_litedramcore_interface_wdata <= 128'd0;
+    case ({builder_new_master_wdata_ready1})
         1'd1: begin
-            litedramcore_interface_wdata <= user_port_wdata_payload_data;
+            main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data;
         end
         default: begin
-            litedramcore_interface_wdata <= 1'd0;
+            main_litedramcore_interface_wdata <= 1'd0;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_interface_wdata_we <= 16'd0;
-    case ({litedramcore_new_master_wdata_ready1})
+    main_litedramcore_interface_wdata_we <= 16'd0;
+    case ({builder_new_master_wdata_ready1})
         1'd1: begin
-            litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
+            main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we;
         end
         default: begin
-            litedramcore_interface_wdata_we <= 1'd0;
+            main_litedramcore_interface_wdata_we <= 1'd0;
         end
     endcase
 end
-assign user_port_rdata_payload_data = litedramcore_interface_rdata;
-assign litedramcore_roundrobin0_grant = 1'd0;
-assign litedramcore_roundrobin1_grant = 1'd0;
-assign litedramcore_roundrobin2_grant = 1'd0;
-assign litedramcore_roundrobin3_grant = 1'd0;
-assign litedramcore_roundrobin4_grant = 1'd0;
-assign litedramcore_roundrobin5_grant = 1'd0;
-assign litedramcore_roundrobin6_grant = 1'd0;
-assign litedramcore_roundrobin7_grant = 1'd0;
-always @(*) begin
-    litedramcore_next_state <= 2'd0;
-    litedramcore_next_state <= litedramcore_state;
-    case (litedramcore_state)
+assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata;
+assign builder_roundrobin0_grant = 1'd0;
+assign builder_roundrobin1_grant = 1'd0;
+assign builder_roundrobin2_grant = 1'd0;
+assign builder_roundrobin3_grant = 1'd0;
+assign builder_roundrobin4_grant = 1'd0;
+assign builder_roundrobin5_grant = 1'd0;
+assign builder_roundrobin6_grant = 1'd0;
+assign builder_roundrobin7_grant = 1'd0;
+always @(*) begin
+    builder_next_state <= 2'd0;
+    builder_next_state <= builder_state;
+    case (builder_state)
         1'd1: begin
-            litedramcore_next_state <= 2'd2;
+            builder_next_state <= 2'd2;
         end
         2'd2: begin
-            litedramcore_next_state <= 1'd0;
+            builder_next_state <= 1'd0;
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_next_state <= 1'd1;
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_next_state <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_we_next_value2 <= 1'd0;
-    case (litedramcore_state)
+    builder_interface1_adr_next_value1 <= 14'd0;
+    case (builder_state)
         1'd1: begin
-            litedramcore_we_next_value2 <= 1'd0;
+            builder_interface1_adr_next_value1 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_adr_next_value1 <= builder_interface0_adr[29:0];
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_we_next_value_ce2 <= 1'd0;
-    case (litedramcore_state)
+    builder_interface0_ack <= 1'd0;
+    case (builder_state)
         1'd1: begin
-            litedramcore_we_next_value_ce2 <= 1'd1;
         end
         2'd2: begin
+            builder_interface0_ack <= 1'd1;
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_we_next_value_ce2 <= 1'd1;
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_wishbone_ack <= 1'd0;
-    case (litedramcore_state)
+    builder_interface1_adr_next_value_ce1 <= 1'd0;
+    case (builder_state)
         1'd1: begin
+            builder_interface1_adr_next_value_ce1 <= 1'd1;
         end
         2'd2: begin
-            litedramcore_wishbone_ack <= 1'd1;
         end
         default: begin
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_adr_next_value_ce1 <= 1'd1;
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_wishbone_dat_r <= 32'd0;
-    case (litedramcore_state)
+    builder_interface1_we_next_value2 <= 1'd0;
+    case (builder_state)
         1'd1: begin
+            builder_interface1_we_next_value2 <= 1'd0;
         end
         2'd2: begin
-            litedramcore_wishbone_dat_r <= litedramcore_dat_r;
         end
         default: begin
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_we_next_value2 <= (builder_interface0_we & (builder_interface0_sel != 1'd0));
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_dat_w_next_value0 <= 32'd0;
-    case (litedramcore_state)
+    builder_interface1_we_next_value_ce2 <= 1'd0;
+    case (builder_state)
         1'd1: begin
+            builder_interface1_we_next_value_ce2 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
-            litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_we_next_value_ce2 <= 1'd1;
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_dat_w_next_value_ce0 <= 1'd0;
-    case (litedramcore_state)
+    builder_interface0_dat_r <= 32'd0;
+    case (builder_state)
         1'd1: begin
         end
         2'd2: begin
+            builder_interface0_dat_r <= builder_interface1_dat_r;
         end
         default: begin
-            litedramcore_dat_w_next_value_ce0 <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_adr_next_value1 <= 14'd0;
-    case (litedramcore_state)
+    builder_interface1_dat_w_next_value0 <= 32'd0;
+    case (builder_state)
         1'd1: begin
-            litedramcore_adr_next_value1 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
-            end
+            builder_interface1_dat_w_next_value0 <= builder_interface0_dat_w;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_adr_next_value_ce1 <= 1'd0;
-    case (litedramcore_state)
+    builder_interface1_dat_w_next_value_ce0 <= 1'd0;
+    case (builder_state)
         1'd1: begin
-            litedramcore_adr_next_value_ce1 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_adr_next_value_ce1 <= 1'd1;
-            end
+            builder_interface1_dat_w_next_value_ce0 <= 1'd1;
         end
     endcase
 end
-assign litedramcore_wishbone_adr = wb_bus_adr;
-assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
-assign wb_bus_dat_r = litedramcore_wishbone_dat_r;
-assign litedramcore_wishbone_sel = wb_bus_sel;
-assign litedramcore_wishbone_cyc = wb_bus_cyc;
-assign litedramcore_wishbone_stb = wb_bus_stb;
-assign wb_bus_ack = litedramcore_wishbone_ack;
-assign litedramcore_wishbone_we = wb_bus_we;
-assign litedramcore_wishbone_cti = wb_bus_cti;
-assign litedramcore_wishbone_bte = wb_bus_bte;
-assign wb_bus_err = litedramcore_wishbone_err;
-assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
-assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
+assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0);
+assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank0_init_done0_we <= 1'd0;
-    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank0_init_done0_we <= (~interface0_bank_bus_we);
+    builder_csrbank0_init_done0_we <= 1'd0;
+    if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank0_init_done0_re <= 1'd0;
-    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank0_init_done0_re <= interface0_bank_bus_we;
+    builder_csrbank0_init_done0_re <= 1'd0;
+    if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
     end
 end
-assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
+assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank0_init_error0_re <= 1'd0;
-    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank0_init_error0_re <= interface0_bank_bus_we;
+    builder_csrbank0_init_error0_we <= 1'd0;
+    if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank0_init_error0_we <= 1'd0;
-    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank0_init_error0_we <= (~interface0_bank_bus_we);
+    builder_csrbank0_init_error0_re <= 1'd0;
+    if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
     end
 end
-assign csrbank0_init_done0_w = init_done_storage;
-assign csrbank0_init_error0_w = init_error_storage;
-assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
-assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0];
+assign builder_csrbank0_init_done0_w = main_init_done_storage;
+assign builder_csrbank0_init_error0_w = main_init_error_storage;
+assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
+assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank1_rst0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank1_rst0_re <= interface1_bank_bus_we;
+    builder_csrbank1_rst0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank1_rst0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank1_rst0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_rst0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
     end
 end
-assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
+assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    csrbank1_dly_sel0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_dly_sel0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_dly_sel0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank1_dly_sel0_re <= interface1_bank_bus_we;
+    builder_csrbank1_dly_sel0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
+assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0];
 always @(*) begin
-    csrbank1_half_sys8x_taps0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
+        builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank1_half_sys8x_taps0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we;
+    builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
+        builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
     end
 end
-assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0];
+assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank1_wlevel_en0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank1_wlevel_en0_re <= interface1_bank_bus_we;
+    builder_csrbank1_wlevel_en0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
+        builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_wlevel_en0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_wlevel_en0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
+        builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_wlevel_strobe_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
-        a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we;
+    main_a7ddrphy_wlevel_strobe_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
+        main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    a7ddrphy_wlevel_strobe_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
-        a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_wlevel_strobe_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
+        main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_rdly_dq_rst_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
+    main_a7ddrphy_rdly_dq_rst_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
+        main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    a7ddrphy_rdly_dq_rst_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_rdly_dq_rst_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
+        main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_rdly_dq_inc_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
+    main_a7ddrphy_rdly_dq_inc_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
+        main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    a7ddrphy_rdly_dq_inc_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_rdly_dq_inc_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
+        main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
-        a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
+        main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
-        a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
+    main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
+        main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
     end
 end
-assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
-        a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
+        main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
-        a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we;
+    main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
+        main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
     end
 end
-assign a7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
-        a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
+        main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
-        a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
+    main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
+        main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
     end
 end
-assign a7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
-        a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
+        main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
-        a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we;
+    main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
+        main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
     end
 end
-assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0];
+assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    csrbank1_rdphase0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
-        csrbank1_rdphase0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_rdphase0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
+        builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_rdphase0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
-        csrbank1_rdphase0_re <= interface1_bank_bus_we;
+    builder_csrbank1_rdphase0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
+        builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0];
+assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    csrbank1_wrphase0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
-        csrbank1_wrphase0_re <= interface1_bank_bus_we;
+    builder_csrbank1_wrphase0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
+        builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank1_wrphase0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
-        csrbank1_wrphase0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_wrphase0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
+        builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
     end
 end
-assign csrbank1_rst0_w = a7ddrphy_rst_storage;
-assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0];
-assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0];
-assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage;
-assign csrbank1_rdphase0_w = a7ddrphy_rdphase_storage[1:0];
-assign csrbank1_wrphase0_w = a7ddrphy_wrphase_storage[1:0];
-assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2);
-assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
+assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage;
+assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0];
+assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0];
+assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage;
+assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0];
+assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0];
+assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
+assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
 always @(*) begin
-    csrbank2_dfii_control0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_control0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_control0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank2_dfii_control0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_control0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
+assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi0_command0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_command0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_command0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
+assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    litedramcore_phaseinjector0_command_issue_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
-        litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
+    main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
+        main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    litedramcore_phaseinjector0_command_issue_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
-        litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
+    main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
+        main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[13:0];
+assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[13:0];
 always @(*) begin
-    csrbank2_dfii_pi0_address0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_address0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
+        builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_address0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
+        builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank2_dfii_pi0_baddress0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
-        csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
+        builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_baddress0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
-        csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
+        builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
-        csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
+        builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
-        csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
+        builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi0_rddata_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
-        csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_rddata_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
+        builder_csrbank2_dfii_pi0_rddata_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_rddata_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
-        csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_rddata_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
+        builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
+assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi1_command0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
-        csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
+        builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_command0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
-        csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_command0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
+        builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
+assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    litedramcore_phaseinjector1_command_issue_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
-        litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
+    main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
+        main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    litedramcore_phaseinjector1_command_issue_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
-        litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we;
+    main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
+        main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[13:0];
+assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[13:0];
 always @(*) begin
-    csrbank2_dfii_pi1_address0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
-        csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
+        builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_address0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
-        csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_address0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
+        builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank2_dfii_pi1_baddress0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
-        csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
+        builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_baddress0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
-        csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
+        builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
-        csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
+        builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
-        csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
+        builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi1_rddata_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
-        csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_rddata_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
+        builder_csrbank2_dfii_pi1_rddata_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_rddata_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
-        csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_rddata_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
+        builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0];
+assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi2_command0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
-        csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_command0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
+        builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_command0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
-        csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_command0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
+        builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0];
+assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    litedramcore_phaseinjector2_command_issue_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
-        litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we);
+    main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
+        main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    litedramcore_phaseinjector2_command_issue_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
-        litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we;
+    main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
+        main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[13:0];
+assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[13:0];
 always @(*) begin
-    csrbank2_dfii_pi2_address0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
-        csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
+        builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_address0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
-        csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_address0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
+        builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank2_dfii_pi2_baddress0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
-        csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
+        builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_baddress0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
-        csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
+        builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
-        csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+        builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
-        csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+        builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi2_rddata_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
-        csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_rddata_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+        builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_rddata_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
-        csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_rddata_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+        builder_csrbank2_dfii_pi2_rddata_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0];
+assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi3_command0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
-        csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_command0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
+        builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_command0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
-        csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
+        builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0];
+assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    litedramcore_phaseinjector3_command_issue_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
-        litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we;
+    main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
+        main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    litedramcore_phaseinjector3_command_issue_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
-        litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we);
+    main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
+        main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[13:0];
+assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[13:0];
 always @(*) begin
-    csrbank2_dfii_pi3_address0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
-        csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_address0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
+        builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_address0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
-        csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
+        builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank2_dfii_pi3_baddress0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
-        csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+        builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_baddress0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
-        csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+        builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
-        csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
+        builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
-        csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
+        builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi3_rddata_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
-        csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_rddata_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
+        builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_rddata_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
-        csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_rddata_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
+        builder_csrbank2_dfii_pi3_rddata_re <= builder_interface2_bank_bus_we;
     end
 end
-assign litedramcore_sel = litedramcore_storage[0];
-assign litedramcore_cke = litedramcore_storage[1];
-assign litedramcore_odt = litedramcore_storage[2];
-assign litedramcore_reset_n = litedramcore_storage[3];
-assign csrbank2_dfii_control0_w = litedramcore_storage[3:0];
-assign litedramcore_phaseinjector0_csrfield_cs = litedramcore_phaseinjector0_command_storage[0];
-assign litedramcore_phaseinjector0_csrfield_we = litedramcore_phaseinjector0_command_storage[1];
-assign litedramcore_phaseinjector0_csrfield_cas = litedramcore_phaseinjector0_command_storage[2];
-assign litedramcore_phaseinjector0_csrfield_ras = litedramcore_phaseinjector0_command_storage[3];
-assign litedramcore_phaseinjector0_csrfield_wren = litedramcore_phaseinjector0_command_storage[4];
-assign litedramcore_phaseinjector0_csrfield_rden = litedramcore_phaseinjector0_command_storage[5];
-assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
-assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0];
-assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
-assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
-assign csrbank2_dfii_pi0_rddata_w = litedramcore_phaseinjector0_rddata_status[31:0];
-assign litedramcore_phaseinjector0_rddata_we = csrbank2_dfii_pi0_rddata_we;
-assign litedramcore_phaseinjector1_csrfield_cs = litedramcore_phaseinjector1_command_storage[0];
-assign litedramcore_phaseinjector1_csrfield_we = litedramcore_phaseinjector1_command_storage[1];
-assign litedramcore_phaseinjector1_csrfield_cas = litedramcore_phaseinjector1_command_storage[2];
-assign litedramcore_phaseinjector1_csrfield_ras = litedramcore_phaseinjector1_command_storage[3];
-assign litedramcore_phaseinjector1_csrfield_wren = litedramcore_phaseinjector1_command_storage[4];
-assign litedramcore_phaseinjector1_csrfield_rden = litedramcore_phaseinjector1_command_storage[5];
-assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
-assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[13:0];
-assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
-assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
-assign csrbank2_dfii_pi1_rddata_w = litedramcore_phaseinjector1_rddata_status[31:0];
-assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata_we;
-assign litedramcore_phaseinjector2_csrfield_cs = litedramcore_phaseinjector2_command_storage[0];
-assign litedramcore_phaseinjector2_csrfield_we = litedramcore_phaseinjector2_command_storage[1];
-assign litedramcore_phaseinjector2_csrfield_cas = litedramcore_phaseinjector2_command_storage[2];
-assign litedramcore_phaseinjector2_csrfield_ras = litedramcore_phaseinjector2_command_storage[3];
-assign litedramcore_phaseinjector2_csrfield_wren = litedramcore_phaseinjector2_command_storage[4];
-assign litedramcore_phaseinjector2_csrfield_rden = litedramcore_phaseinjector2_command_storage[5];
-assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
-assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[13:0];
-assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
-assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0];
-assign csrbank2_dfii_pi2_rddata_w = litedramcore_phaseinjector2_rddata_status[31:0];
-assign litedramcore_phaseinjector2_rddata_we = csrbank2_dfii_pi2_rddata_we;
-assign litedramcore_phaseinjector3_csrfield_cs = litedramcore_phaseinjector3_command_storage[0];
-assign litedramcore_phaseinjector3_csrfield_we = litedramcore_phaseinjector3_command_storage[1];
-assign litedramcore_phaseinjector3_csrfield_cas = litedramcore_phaseinjector3_command_storage[2];
-assign litedramcore_phaseinjector3_csrfield_ras = litedramcore_phaseinjector3_command_storage[3];
-assign litedramcore_phaseinjector3_csrfield_wren = litedramcore_phaseinjector3_command_storage[4];
-assign litedramcore_phaseinjector3_csrfield_rden = litedramcore_phaseinjector3_command_storage[5];
-assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
-assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[13:0];
-assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
-assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0];
-assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_rddata_status[31:0];
-assign litedramcore_phaseinjector3_rddata_we = csrbank2_dfii_pi3_rddata_we;
-assign csr_interconnect_adr = litedramcore_adr;
-assign csr_interconnect_we = litedramcore_we;
-assign csr_interconnect_dat_w = litedramcore_dat_w;
-assign litedramcore_dat_r = csr_interconnect_dat_r;
-assign interface0_bank_bus_adr = csr_interconnect_adr;
-assign interface1_bank_bus_adr = csr_interconnect_adr;
-assign interface2_bank_bus_adr = csr_interconnect_adr;
-assign interface0_bank_bus_we = csr_interconnect_we;
-assign interface1_bank_bus_we = csr_interconnect_we;
-assign interface2_bank_bus_we = csr_interconnect_we;
-assign interface0_bank_bus_dat_w = csr_interconnect_dat_w;
-assign interface1_bank_bus_dat_w = csr_interconnect_dat_w;
-assign interface2_bank_bus_dat_w = csr_interconnect_dat_w;
-assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
-always @(*) begin
-    rhs_array_muxed0 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+assign main_litedramcore_sel = main_litedramcore_storage[0];
+assign main_litedramcore_cke = main_litedramcore_storage[1];
+assign main_litedramcore_odt = main_litedramcore_storage[2];
+assign main_litedramcore_reset_n = main_litedramcore_storage[3];
+assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0];
+assign main_litedramcore_phaseinjector0_csrfield_cs = main_litedramcore_phaseinjector0_command_storage[0];
+assign main_litedramcore_phaseinjector0_csrfield_we = main_litedramcore_phaseinjector0_command_storage[1];
+assign main_litedramcore_phaseinjector0_csrfield_cas = main_litedramcore_phaseinjector0_command_storage[2];
+assign main_litedramcore_phaseinjector0_csrfield_ras = main_litedramcore_phaseinjector0_command_storage[3];
+assign main_litedramcore_phaseinjector0_csrfield_wren = main_litedramcore_phaseinjector0_command_storage[4];
+assign main_litedramcore_phaseinjector0_csrfield_rden = main_litedramcore_phaseinjector0_command_storage[5];
+assign main_litedramcore_phaseinjector0_csrfield_cs_top = main_litedramcore_phaseinjector0_command_storage[6];
+assign main_litedramcore_phaseinjector0_csrfield_cs_bottom = main_litedramcore_phaseinjector0_command_storage[7];
+assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[7:0];
+assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[13:0];
+assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0];
+assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we;
+assign main_litedramcore_phaseinjector1_csrfield_cs = main_litedramcore_phaseinjector1_command_storage[0];
+assign main_litedramcore_phaseinjector1_csrfield_we = main_litedramcore_phaseinjector1_command_storage[1];
+assign main_litedramcore_phaseinjector1_csrfield_cas = main_litedramcore_phaseinjector1_command_storage[2];
+assign main_litedramcore_phaseinjector1_csrfield_ras = main_litedramcore_phaseinjector1_command_storage[3];
+assign main_litedramcore_phaseinjector1_csrfield_wren = main_litedramcore_phaseinjector1_command_storage[4];
+assign main_litedramcore_phaseinjector1_csrfield_rden = main_litedramcore_phaseinjector1_command_storage[5];
+assign main_litedramcore_phaseinjector1_csrfield_cs_top = main_litedramcore_phaseinjector1_command_storage[6];
+assign main_litedramcore_phaseinjector1_csrfield_cs_bottom = main_litedramcore_phaseinjector1_command_storage[7];
+assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[7:0];
+assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[13:0];
+assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0];
+assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we;
+assign main_litedramcore_phaseinjector2_csrfield_cs = main_litedramcore_phaseinjector2_command_storage[0];
+assign main_litedramcore_phaseinjector2_csrfield_we = main_litedramcore_phaseinjector2_command_storage[1];
+assign main_litedramcore_phaseinjector2_csrfield_cas = main_litedramcore_phaseinjector2_command_storage[2];
+assign main_litedramcore_phaseinjector2_csrfield_ras = main_litedramcore_phaseinjector2_command_storage[3];
+assign main_litedramcore_phaseinjector2_csrfield_wren = main_litedramcore_phaseinjector2_command_storage[4];
+assign main_litedramcore_phaseinjector2_csrfield_rden = main_litedramcore_phaseinjector2_command_storage[5];
+assign main_litedramcore_phaseinjector2_csrfield_cs_top = main_litedramcore_phaseinjector2_command_storage[6];
+assign main_litedramcore_phaseinjector2_csrfield_cs_bottom = main_litedramcore_phaseinjector2_command_storage[7];
+assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[7:0];
+assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[13:0];
+assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0];
+assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we;
+assign main_litedramcore_phaseinjector3_csrfield_cs = main_litedramcore_phaseinjector3_command_storage[0];
+assign main_litedramcore_phaseinjector3_csrfield_we = main_litedramcore_phaseinjector3_command_storage[1];
+assign main_litedramcore_phaseinjector3_csrfield_cas = main_litedramcore_phaseinjector3_command_storage[2];
+assign main_litedramcore_phaseinjector3_csrfield_ras = main_litedramcore_phaseinjector3_command_storage[3];
+assign main_litedramcore_phaseinjector3_csrfield_wren = main_litedramcore_phaseinjector3_command_storage[4];
+assign main_litedramcore_phaseinjector3_csrfield_rden = main_litedramcore_phaseinjector3_command_storage[5];
+assign main_litedramcore_phaseinjector3_csrfield_cs_top = main_litedramcore_phaseinjector3_command_storage[6];
+assign main_litedramcore_phaseinjector3_csrfield_cs_bottom = main_litedramcore_phaseinjector3_command_storage[7];
+assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[7:0];
+assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[13:0];
+assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0];
+assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we;
+assign builder_adr = builder_interface1_adr;
+assign builder_we = builder_interface1_we;
+assign builder_dat_w = builder_interface1_dat_w;
+assign builder_interface1_dat_r = builder_dat_r;
+assign builder_interface0_bank_bus_adr = builder_adr;
+assign builder_interface1_bank_bus_adr = builder_adr;
+assign builder_interface2_bank_bus_adr = builder_adr;
+assign builder_interface0_bank_bus_we = builder_we;
+assign builder_interface1_bank_bus_we = builder_we;
+assign builder_interface2_bank_bus_we = builder_we;
+assign builder_interface0_bank_bus_dat_w = builder_dat_w;
+assign builder_interface1_bank_bus_dat_w = builder_dat_w;
+assign builder_interface2_bank_bus_dat_w = builder_dat_w;
+assign builder_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r);
+always @(*) begin
+    builder_rhs_self0 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[0];
         end
         1'd1: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[1];
         end
         2'd2: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[2];
         end
         2'd3: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[3];
         end
         3'd4: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[4];
         end
         3'd5: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[5];
         end
         3'd6: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[6];
         end
         default: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[7];
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed1 <= 14'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_rhs_self1 <= 14'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine0_cmd_payload_a;
         end
         1'd1: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine1_cmd_payload_a;
         end
         2'd2: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine2_cmd_payload_a;
         end
         2'd3: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine3_cmd_payload_a;
         end
         3'd4: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine4_cmd_payload_a;
         end
         3'd5: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine5_cmd_payload_a;
         end
         3'd6: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine6_cmd_payload_a;
         end
         default: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine7_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed2 <= 3'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_rhs_self2 <= 3'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine0_cmd_payload_ba;
         end
         1'd1: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine1_cmd_payload_ba;
         end
         2'd2: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine2_cmd_payload_ba;
         end
         2'd3: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine3_cmd_payload_ba;
         end
         3'd4: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine4_cmd_payload_ba;
         end
         3'd5: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine5_cmd_payload_ba;
         end
         3'd6: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine6_cmd_payload_ba;
         end
         default: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine7_cmd_payload_ba;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed3 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_rhs_self3 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine0_cmd_payload_is_read;
         end
         1'd1: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine1_cmd_payload_is_read;
         end
         2'd2: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine2_cmd_payload_is_read;
         end
         2'd3: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine3_cmd_payload_is_read;
         end
         3'd4: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine4_cmd_payload_is_read;
         end
         3'd5: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine5_cmd_payload_is_read;
         end
         3'd6: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine6_cmd_payload_is_read;
         end
         default: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed4 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_rhs_self4 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine0_cmd_payload_is_write;
         end
         1'd1: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine1_cmd_payload_is_write;
         end
         2'd2: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine2_cmd_payload_is_write;
         end
         2'd3: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine3_cmd_payload_is_write;
         end
         3'd4: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine4_cmd_payload_is_write;
         end
         3'd5: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine5_cmd_payload_is_write;
         end
         3'd6: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine6_cmd_payload_is_write;
         end
         default: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed5 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_rhs_self5 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd;
         end
         1'd1: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd;
         end
         2'd2: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd;
         end
         2'd3: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd;
         end
         3'd4: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd;
         end
         3'd5: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd;
         end
         3'd6: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd;
         end
         default: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed0 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_t_self0 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine0_cmd_payload_cas;
         end
         1'd1: begin
-            t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine1_cmd_payload_cas;
         end
         2'd2: begin
-            t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine2_cmd_payload_cas;
         end
         2'd3: begin
-            t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine3_cmd_payload_cas;
         end
         3'd4: begin
-            t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine4_cmd_payload_cas;
         end
         3'd5: begin
-            t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine5_cmd_payload_cas;
         end
         3'd6: begin
-            t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine6_cmd_payload_cas;
         end
         default: begin
-            t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine7_cmd_payload_cas;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed1 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_t_self1 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine0_cmd_payload_ras;
         end
         1'd1: begin
-            t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine1_cmd_payload_ras;
         end
         2'd2: begin
-            t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine2_cmd_payload_ras;
         end
         2'd3: begin
-            t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine3_cmd_payload_ras;
         end
         3'd4: begin
-            t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine4_cmd_payload_ras;
         end
         3'd5: begin
-            t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine5_cmd_payload_ras;
         end
         3'd6: begin
-            t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine6_cmd_payload_ras;
         end
         default: begin
-            t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine7_cmd_payload_ras;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed2 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_t_self2 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine0_cmd_payload_we;
         end
         1'd1: begin
-            t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine1_cmd_payload_we;
         end
         2'd2: begin
-            t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine2_cmd_payload_we;
         end
         2'd3: begin
-            t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine3_cmd_payload_we;
         end
         3'd4: begin
-            t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine4_cmd_payload_we;
         end
         3'd5: begin
-            t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine5_cmd_payload_we;
         end
         3'd6: begin
-            t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine6_cmd_payload_we;
         end
         default: begin
-            t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine7_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed6 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self6 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[0];
         end
         1'd1: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[1];
         end
         2'd2: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[2];
         end
         2'd3: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[3];
         end
         3'd4: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[4];
         end
         3'd5: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[5];
         end
         3'd6: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[6];
         end
         default: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[7];
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed7 <= 14'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self7 <= 14'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine0_cmd_payload_a;
         end
         1'd1: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine1_cmd_payload_a;
         end
         2'd2: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine2_cmd_payload_a;
         end
         2'd3: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine3_cmd_payload_a;
         end
         3'd4: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine4_cmd_payload_a;
         end
         3'd5: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine5_cmd_payload_a;
         end
         3'd6: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine6_cmd_payload_a;
         end
         default: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine7_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed8 <= 3'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self8 <= 3'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine0_cmd_payload_ba;
         end
         1'd1: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine1_cmd_payload_ba;
         end
         2'd2: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine2_cmd_payload_ba;
         end
         2'd3: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine3_cmd_payload_ba;
         end
         3'd4: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine4_cmd_payload_ba;
         end
         3'd5: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine5_cmd_payload_ba;
         end
         3'd6: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine6_cmd_payload_ba;
         end
         default: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine7_cmd_payload_ba;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed9 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self9 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine0_cmd_payload_is_read;
         end
         1'd1: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine1_cmd_payload_is_read;
         end
         2'd2: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine2_cmd_payload_is_read;
         end
         2'd3: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine3_cmd_payload_is_read;
         end
         3'd4: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine4_cmd_payload_is_read;
         end
         3'd5: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine5_cmd_payload_is_read;
         end
         3'd6: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine6_cmd_payload_is_read;
         end
         default: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed10 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self10 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine0_cmd_payload_is_write;
         end
         1'd1: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine1_cmd_payload_is_write;
         end
         2'd2: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine2_cmd_payload_is_write;
         end
         2'd3: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine3_cmd_payload_is_write;
         end
         3'd4: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine4_cmd_payload_is_write;
         end
         3'd5: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine5_cmd_payload_is_write;
         end
         3'd6: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine6_cmd_payload_is_write;
         end
         default: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed11 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self11 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd;
         end
         1'd1: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd;
         end
         2'd2: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd;
         end
         2'd3: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd;
         end
         3'd4: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd;
         end
         3'd5: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd;
         end
         3'd6: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd;
         end
         default: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed3 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_t_self3 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine0_cmd_payload_cas;
         end
         1'd1: begin
-            t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine1_cmd_payload_cas;
         end
         2'd2: begin
-            t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine2_cmd_payload_cas;
         end
         2'd3: begin
-            t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine3_cmd_payload_cas;
         end
         3'd4: begin
-            t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine4_cmd_payload_cas;
         end
         3'd5: begin
-            t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine5_cmd_payload_cas;
         end
         3'd6: begin
-            t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine6_cmd_payload_cas;
         end
         default: begin
-            t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine7_cmd_payload_cas;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed4 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_t_self4 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine0_cmd_payload_ras;
         end
         1'd1: begin
-            t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine1_cmd_payload_ras;
         end
         2'd2: begin
-            t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine2_cmd_payload_ras;
         end
         2'd3: begin
-            t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine3_cmd_payload_ras;
         end
         3'd4: begin
-            t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine4_cmd_payload_ras;
         end
         3'd5: begin
-            t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine5_cmd_payload_ras;
         end
         3'd6: begin
-            t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine6_cmd_payload_ras;
         end
         default: begin
-            t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine7_cmd_payload_ras;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed5 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_t_self5 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine0_cmd_payload_we;
         end
         1'd1: begin
-            t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine1_cmd_payload_we;
         end
         2'd2: begin
-            t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine2_cmd_payload_we;
         end
         2'd3: begin
-            t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine3_cmd_payload_we;
         end
         3'd4: begin
-            t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine4_cmd_payload_we;
         end
         3'd5: begin
-            t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine5_cmd_payload_we;
         end
         3'd6: begin
-            t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine6_cmd_payload_we;
         end
         default: begin
-            t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine7_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed12 <= 21'd0;
-    case (litedramcore_roundrobin0_grant)
+    builder_rhs_self12 <= 21'd0;
+    case (builder_roundrobin0_grant)
         default: begin
-            rhs_array_muxed12 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self12 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed13 <= 1'd0;
-    case (litedramcore_roundrobin0_grant)
+    builder_rhs_self13 <= 1'd0;
+    case (builder_roundrobin0_grant)
         default: begin
-            rhs_array_muxed13 <= user_port_cmd_payload_we;
+            builder_rhs_self13 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed14 <= 1'd0;
-    case (litedramcore_roundrobin0_grant)
+    builder_rhs_self14 <= 1'd0;
+    case (builder_roundrobin0_grant)
         default: begin
-            rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed15 <= 21'd0;
-    case (litedramcore_roundrobin1_grant)
+    builder_rhs_self15 <= 21'd0;
+    case (builder_roundrobin1_grant)
         default: begin
-            rhs_array_muxed15 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self15 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed16 <= 1'd0;
-    case (litedramcore_roundrobin1_grant)
+    builder_rhs_self16 <= 1'd0;
+    case (builder_roundrobin1_grant)
         default: begin
-            rhs_array_muxed16 <= user_port_cmd_payload_we;
+            builder_rhs_self16 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed17 <= 1'd0;
-    case (litedramcore_roundrobin1_grant)
+    builder_rhs_self17 <= 1'd0;
+    case (builder_roundrobin1_grant)
         default: begin
-            rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed18 <= 21'd0;
-    case (litedramcore_roundrobin2_grant)
+    builder_rhs_self18 <= 21'd0;
+    case (builder_roundrobin2_grant)
         default: begin
-            rhs_array_muxed18 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self18 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed19 <= 1'd0;
-    case (litedramcore_roundrobin2_grant)
+    builder_rhs_self19 <= 1'd0;
+    case (builder_roundrobin2_grant)
         default: begin
-            rhs_array_muxed19 <= user_port_cmd_payload_we;
+            builder_rhs_self19 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed20 <= 1'd0;
-    case (litedramcore_roundrobin2_grant)
+    builder_rhs_self20 <= 1'd0;
+    case (builder_roundrobin2_grant)
         default: begin
-            rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed21 <= 21'd0;
-    case (litedramcore_roundrobin3_grant)
+    builder_rhs_self21 <= 21'd0;
+    case (builder_roundrobin3_grant)
         default: begin
-            rhs_array_muxed21 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self21 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed22 <= 1'd0;
-    case (litedramcore_roundrobin3_grant)
+    builder_rhs_self22 <= 1'd0;
+    case (builder_roundrobin3_grant)
         default: begin
-            rhs_array_muxed22 <= user_port_cmd_payload_we;
+            builder_rhs_self22 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed23 <= 1'd0;
-    case (litedramcore_roundrobin3_grant)
+    builder_rhs_self23 <= 1'd0;
+    case (builder_roundrobin3_grant)
         default: begin
-            rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed24 <= 21'd0;
-    case (litedramcore_roundrobin4_grant)
+    builder_rhs_self24 <= 21'd0;
+    case (builder_roundrobin4_grant)
         default: begin
-            rhs_array_muxed24 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self24 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed25 <= 1'd0;
-    case (litedramcore_roundrobin4_grant)
+    builder_rhs_self25 <= 1'd0;
+    case (builder_roundrobin4_grant)
         default: begin
-            rhs_array_muxed25 <= user_port_cmd_payload_we;
+            builder_rhs_self25 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed26 <= 1'd0;
-    case (litedramcore_roundrobin4_grant)
+    builder_rhs_self26 <= 1'd0;
+    case (builder_roundrobin4_grant)
         default: begin
-            rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed27 <= 21'd0;
-    case (litedramcore_roundrobin5_grant)
+    builder_rhs_self27 <= 21'd0;
+    case (builder_roundrobin5_grant)
         default: begin
-            rhs_array_muxed27 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self27 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed28 <= 1'd0;
-    case (litedramcore_roundrobin5_grant)
+    builder_rhs_self28 <= 1'd0;
+    case (builder_roundrobin5_grant)
         default: begin
-            rhs_array_muxed28 <= user_port_cmd_payload_we;
+            builder_rhs_self28 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed29 <= 1'd0;
-    case (litedramcore_roundrobin5_grant)
+    builder_rhs_self29 <= 1'd0;
+    case (builder_roundrobin5_grant)
         default: begin
-            rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed30 <= 21'd0;
-    case (litedramcore_roundrobin6_grant)
+    builder_rhs_self30 <= 21'd0;
+    case (builder_roundrobin6_grant)
         default: begin
-            rhs_array_muxed30 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self30 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed31 <= 1'd0;
-    case (litedramcore_roundrobin6_grant)
+    builder_rhs_self31 <= 1'd0;
+    case (builder_roundrobin6_grant)
         default: begin
-            rhs_array_muxed31 <= user_port_cmd_payload_we;
+            builder_rhs_self31 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed32 <= 1'd0;
-    case (litedramcore_roundrobin6_grant)
+    builder_rhs_self32 <= 1'd0;
+    case (builder_roundrobin6_grant)
         default: begin
-            rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed33 <= 21'd0;
-    case (litedramcore_roundrobin7_grant)
+    builder_rhs_self33 <= 21'd0;
+    case (builder_roundrobin7_grant)
         default: begin
-            rhs_array_muxed33 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self33 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed34 <= 1'd0;
-    case (litedramcore_roundrobin7_grant)
+    builder_rhs_self34 <= 1'd0;
+    case (builder_roundrobin7_grant)
         default: begin
-            rhs_array_muxed34 <= user_port_cmd_payload_we;
+            builder_rhs_self34 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed35 <= 1'd0;
-    case (litedramcore_roundrobin7_grant)
+    builder_rhs_self35 <= 1'd0;
+    case (builder_roundrobin7_grant)
         default: begin
-            rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    array_muxed0 <= 3'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self0 <= 3'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed0 <= litedramcore_nop_ba[2:0];
+            builder_self0 <= main_litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed1 <= 14'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self1 <= 14'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed1 <= litedramcore_nop_a;
+            builder_self1 <= main_litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
+            builder_self1 <= main_litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
+            builder_self1 <= main_litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed1 <= litedramcore_cmd_payload_a;
+            builder_self1 <= main_litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed2 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self2 <= 1'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed2 <= 1'd0;
+            builder_self2 <= 1'd0;
         end
         1'd1: begin
-            array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+            builder_self2 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+            builder_self2 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+            builder_self2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed3 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self3 <= 1'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed3 <= 1'd0;
+            builder_self3 <= 1'd0;
         end
         1'd1: begin
-            array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+            builder_self3 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+            builder_self3 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+            builder_self3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed4 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self4 <= 1'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed4 <= 1'd0;
+            builder_self4 <= 1'd0;
         end
         1'd1: begin
-            array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+            builder_self4 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+            builder_self4 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+            builder_self4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed5 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self5 <= 1'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed5 <= 1'd0;
+            builder_self5 <= 1'd0;
         end
         1'd1: begin
-            array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+            builder_self5 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+            builder_self5 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+            builder_self5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed6 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self6 <= 1'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed6 <= 1'd0;
+            builder_self6 <= 1'd0;
         end
         1'd1: begin
-            array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+            builder_self6 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+            builder_self6 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+            builder_self6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
         end
     endcase
 end
 always @(*) begin
-    array_muxed7 <= 3'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self7 <= 3'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed7 <= litedramcore_nop_ba[2:0];
+            builder_self7 <= main_litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed8 <= 14'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self8 <= 14'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed8 <= litedramcore_nop_a;
+            builder_self8 <= main_litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
+            builder_self8 <= main_litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
+            builder_self8 <= main_litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed8 <= litedramcore_cmd_payload_a;
+            builder_self8 <= main_litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed9 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self9 <= 1'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed9 <= 1'd0;
+            builder_self9 <= 1'd0;
         end
         1'd1: begin
-            array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+            builder_self9 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+            builder_self9 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+            builder_self9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed10 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self10 <= 1'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed10 <= 1'd0;
+            builder_self10 <= 1'd0;
         end
         1'd1: begin
-            array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+            builder_self10 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+            builder_self10 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+            builder_self10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed11 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self11 <= 1'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed11 <= 1'd0;
+            builder_self11 <= 1'd0;
         end
         1'd1: begin
-            array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+            builder_self11 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+            builder_self11 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+            builder_self11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed12 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self12 <= 1'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed12 <= 1'd0;
+            builder_self12 <= 1'd0;
         end
         1'd1: begin
-            array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+            builder_self12 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+            builder_self12 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+            builder_self12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed13 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self13 <= 1'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed13 <= 1'd0;
+            builder_self13 <= 1'd0;
         end
         1'd1: begin
-            array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+            builder_self13 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+            builder_self13 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+            builder_self13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
         end
     endcase
 end
 always @(*) begin
-    array_muxed14 <= 3'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self14 <= 3'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed14 <= litedramcore_nop_ba[2:0];
+            builder_self14 <= main_litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed14 <= litedramcore_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed15 <= 14'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self15 <= 14'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed15 <= litedramcore_nop_a;
+            builder_self15 <= main_litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a;
+            builder_self15 <= main_litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed15 <= litedramcore_choose_req_cmd_payload_a;
+            builder_self15 <= main_litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed15 <= litedramcore_cmd_payload_a;
+            builder_self15 <= main_litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed16 <= 1'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self16 <= 1'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed16 <= 1'd0;
+            builder_self16 <= 1'd0;
         end
         1'd1: begin
-            array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+            builder_self16 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+            builder_self16 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+            builder_self16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed17 <= 1'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self17 <= 1'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed17 <= 1'd0;
+            builder_self17 <= 1'd0;
         end
         1'd1: begin
-            array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+            builder_self17 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+            builder_self17 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+            builder_self17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed18 <= 1'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self18 <= 1'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed18 <= 1'd0;
+            builder_self18 <= 1'd0;
         end
         1'd1: begin
-            array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+            builder_self18 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+            builder_self18 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+            builder_self18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed19 <= 1'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self19 <= 1'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed19 <= 1'd0;
+            builder_self19 <= 1'd0;
         end
         1'd1: begin
-            array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+            builder_self19 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+            builder_self19 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+            builder_self19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed20 <= 1'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self20 <= 1'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed20 <= 1'd0;
+            builder_self20 <= 1'd0;
         end
         1'd1: begin
-            array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+            builder_self20 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+            builder_self20 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+            builder_self20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
         end
     endcase
 end
 always @(*) begin
-    array_muxed21 <= 3'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self21 <= 3'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed21 <= litedramcore_nop_ba[2:0];
+            builder_self21 <= main_litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed21 <= litedramcore_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed22 <= 14'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self22 <= 14'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed22 <= litedramcore_nop_a;
+            builder_self22 <= main_litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a;
+            builder_self22 <= main_litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed22 <= litedramcore_choose_req_cmd_payload_a;
+            builder_self22 <= main_litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed22 <= litedramcore_cmd_payload_a;
+            builder_self22 <= main_litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed23 <= 1'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self23 <= 1'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed23 <= 1'd0;
+            builder_self23 <= 1'd0;
         end
         1'd1: begin
-            array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+            builder_self23 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+            builder_self23 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+            builder_self23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed24 <= 1'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self24 <= 1'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed24 <= 1'd0;
+            builder_self24 <= 1'd0;
         end
         1'd1: begin
-            array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+            builder_self24 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+            builder_self24 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+            builder_self24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed25 <= 1'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self25 <= 1'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed25 <= 1'd0;
+            builder_self25 <= 1'd0;
         end
         1'd1: begin
-            array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+            builder_self25 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+            builder_self25 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+            builder_self25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed26 <= 1'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self26 <= 1'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed26 <= 1'd0;
+            builder_self26 <= 1'd0;
         end
         1'd1: begin
-            array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+            builder_self26 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+            builder_self26 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+            builder_self26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed27 <= 1'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self27 <= 1'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed27 <= 1'd0;
+            builder_self27 <= 1'd0;
         end
         1'd1: begin
-            array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+            builder_self27 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+            builder_self27 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+            builder_self27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
         end
     endcase
 end
-assign xilinxasyncresetsynchronizerimpl0 = (~locked);
-assign xilinxasyncresetsynchronizerimpl1 = (~locked);
-assign xilinxasyncresetsynchronizerimpl2 = (~locked);
-assign xilinxasyncresetsynchronizerimpl3 = (~locked);
+assign builder_xilinxasyncresetsynchronizerimpl0_async_reset = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl1_async_reset = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl2_async_reset = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl3_async_reset = (~main_locked);
 
 
 //------------------------------------------------------------------------------
@@ -11983,1044 +12398,1044 @@ assign xilinxasyncresetsynchronizerimpl3 = (~locked);
 //------------------------------------------------------------------------------
 
 always @(posedge iodelay_clk) begin
-    if ((reset_counter != 1'd0)) begin
-        reset_counter <= (reset_counter - 1'd1);
+    if ((main_reset_counter != 1'd0)) begin
+        main_reset_counter <= (main_reset_counter - 1'd1);
     end else begin
-        ic_reset <= 1'd0;
+        main_ic_reset <= 1'd0;
     end
     if (iodelay_rst) begin
-        reset_counter <= 4'd15;
-        ic_reset <= 1'd1;
+        main_reset_counter <= 4'd15;
+        main_ic_reset <= 1'd1;
     end
 end
 
 always @(posedge sys_clk) begin
-    a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline;
-    a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
-    a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0;
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1);
+    main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline;
+    main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
+    main_a7ddrphy_dqspattern_o1 <= main_a7ddrphy_dqspattern_o0;
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip0_value0 <= (main_a7ddrphy_bitslip0_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip0_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip0_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1);
+    main_a7ddrphy_bitslip0_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip0_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip1_value0 <= (main_a7ddrphy_bitslip1_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip1_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip1_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1);
+    main_a7ddrphy_bitslip1_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip1_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip0_value1 <= (main_a7ddrphy_bitslip0_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip0_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip0_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1);
+    main_a7ddrphy_bitslip0_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[2], main_a7ddrphy_dfi_p3_wrdata_mask[0], main_a7ddrphy_dfi_p2_wrdata_mask[2], main_a7ddrphy_dfi_p2_wrdata_mask[0], main_a7ddrphy_dfi_p1_wrdata_mask[2], main_a7ddrphy_dfi_p1_wrdata_mask[0], main_a7ddrphy_dfi_p0_wrdata_mask[2], main_a7ddrphy_dfi_p0_wrdata_mask[0]}, main_a7ddrphy_bitslip0_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip1_value1 <= (main_a7ddrphy_bitslip1_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip1_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip1_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]};
-    a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline;
-    a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1);
+    main_a7ddrphy_bitslip1_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[3], main_a7ddrphy_dfi_p3_wrdata_mask[1], main_a7ddrphy_dfi_p2_wrdata_mask[3], main_a7ddrphy_dfi_p2_wrdata_mask[1], main_a7ddrphy_dfi_p1_wrdata_mask[3], main_a7ddrphy_dfi_p1_wrdata_mask[1], main_a7ddrphy_dfi_p0_wrdata_mask[3], main_a7ddrphy_dfi_p0_wrdata_mask[1]}, main_a7ddrphy_bitslip1_r1[15:8]};
+    main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dq_oe_delay_tappeddelayline;
+    main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip0_value2 <= (main_a7ddrphy_bitslip0_value2 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip0_value2 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip0_value2 <= 3'd7;
     end
-    a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1);
+    main_a7ddrphy_bitslip0_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[16], main_a7ddrphy_dfi_p3_wrdata[0], main_a7ddrphy_dfi_p2_wrdata[16], main_a7ddrphy_dfi_p2_wrdata[0], main_a7ddrphy_dfi_p1_wrdata[16], main_a7ddrphy_dfi_p1_wrdata[0], main_a7ddrphy_dfi_p0_wrdata[16], main_a7ddrphy_dfi_p0_wrdata[0]}, main_a7ddrphy_bitslip0_r2[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip0_value3 <= (main_a7ddrphy_bitslip0_value3 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip0_value3 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip0_value3 <= 3'd7;
     end
-    a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1);
+    main_a7ddrphy_bitslip0_r3 <= {main_a7ddrphy_bitslip03, main_a7ddrphy_bitslip0_r3[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip1_value2 <= (main_a7ddrphy_bitslip1_value2 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip1_value2 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip1_value2 <= 3'd7;
     end
-    a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1);
+    main_a7ddrphy_bitslip1_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[17], main_a7ddrphy_dfi_p3_wrdata[1], main_a7ddrphy_dfi_p2_wrdata[17], main_a7ddrphy_dfi_p2_wrdata[1], main_a7ddrphy_dfi_p1_wrdata[17], main_a7ddrphy_dfi_p1_wrdata[1], main_a7ddrphy_dfi_p0_wrdata[17], main_a7ddrphy_dfi_p0_wrdata[1]}, main_a7ddrphy_bitslip1_r2[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip1_value3 <= (main_a7ddrphy_bitslip1_value3 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip1_value3 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip1_value3 <= 3'd7;
     end
-    a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1);
+    main_a7ddrphy_bitslip1_r3 <= {main_a7ddrphy_bitslip13, main_a7ddrphy_bitslip1_r3[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip2_value0 <= (main_a7ddrphy_bitslip2_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip2_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip2_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1);
+    main_a7ddrphy_bitslip2_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[18], main_a7ddrphy_dfi_p3_wrdata[2], main_a7ddrphy_dfi_p2_wrdata[18], main_a7ddrphy_dfi_p2_wrdata[2], main_a7ddrphy_dfi_p1_wrdata[18], main_a7ddrphy_dfi_p1_wrdata[2], main_a7ddrphy_dfi_p0_wrdata[18], main_a7ddrphy_dfi_p0_wrdata[2]}, main_a7ddrphy_bitslip2_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip2_value1 <= (main_a7ddrphy_bitslip2_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip2_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip2_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1);
+    main_a7ddrphy_bitslip2_r1 <= {main_a7ddrphy_bitslip21, main_a7ddrphy_bitslip2_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip3_value0 <= (main_a7ddrphy_bitslip3_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip3_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip3_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1);
+    main_a7ddrphy_bitslip3_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[19], main_a7ddrphy_dfi_p3_wrdata[3], main_a7ddrphy_dfi_p2_wrdata[19], main_a7ddrphy_dfi_p2_wrdata[3], main_a7ddrphy_dfi_p1_wrdata[19], main_a7ddrphy_dfi_p1_wrdata[3], main_a7ddrphy_dfi_p0_wrdata[19], main_a7ddrphy_dfi_p0_wrdata[3]}, main_a7ddrphy_bitslip3_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip3_value1 <= (main_a7ddrphy_bitslip3_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip3_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip3_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1);
+    main_a7ddrphy_bitslip3_r1 <= {main_a7ddrphy_bitslip31, main_a7ddrphy_bitslip3_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip4_value0 <= (main_a7ddrphy_bitslip4_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip4_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip4_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1);
+    main_a7ddrphy_bitslip4_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[20], main_a7ddrphy_dfi_p3_wrdata[4], main_a7ddrphy_dfi_p2_wrdata[20], main_a7ddrphy_dfi_p2_wrdata[4], main_a7ddrphy_dfi_p1_wrdata[20], main_a7ddrphy_dfi_p1_wrdata[4], main_a7ddrphy_dfi_p0_wrdata[20], main_a7ddrphy_dfi_p0_wrdata[4]}, main_a7ddrphy_bitslip4_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip4_value1 <= (main_a7ddrphy_bitslip4_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip4_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip4_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1);
+    main_a7ddrphy_bitslip4_r1 <= {main_a7ddrphy_bitslip41, main_a7ddrphy_bitslip4_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip5_value0 <= (main_a7ddrphy_bitslip5_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip5_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip5_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1);
+    main_a7ddrphy_bitslip5_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[21], main_a7ddrphy_dfi_p3_wrdata[5], main_a7ddrphy_dfi_p2_wrdata[21], main_a7ddrphy_dfi_p2_wrdata[5], main_a7ddrphy_dfi_p1_wrdata[21], main_a7ddrphy_dfi_p1_wrdata[5], main_a7ddrphy_dfi_p0_wrdata[21], main_a7ddrphy_dfi_p0_wrdata[5]}, main_a7ddrphy_bitslip5_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip5_value1 <= (main_a7ddrphy_bitslip5_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip5_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip5_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1);
+    main_a7ddrphy_bitslip5_r1 <= {main_a7ddrphy_bitslip51, main_a7ddrphy_bitslip5_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip6_value0 <= (main_a7ddrphy_bitslip6_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip6_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip6_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1);
+    main_a7ddrphy_bitslip6_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[22], main_a7ddrphy_dfi_p3_wrdata[6], main_a7ddrphy_dfi_p2_wrdata[22], main_a7ddrphy_dfi_p2_wrdata[6], main_a7ddrphy_dfi_p1_wrdata[22], main_a7ddrphy_dfi_p1_wrdata[6], main_a7ddrphy_dfi_p0_wrdata[22], main_a7ddrphy_dfi_p0_wrdata[6]}, main_a7ddrphy_bitslip6_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip6_value1 <= (main_a7ddrphy_bitslip6_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip6_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip6_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1);
+    main_a7ddrphy_bitslip6_r1 <= {main_a7ddrphy_bitslip61, main_a7ddrphy_bitslip6_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip7_value0 <= (main_a7ddrphy_bitslip7_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip7_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip7_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1);
+    main_a7ddrphy_bitslip7_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[23], main_a7ddrphy_dfi_p3_wrdata[7], main_a7ddrphy_dfi_p2_wrdata[23], main_a7ddrphy_dfi_p2_wrdata[7], main_a7ddrphy_dfi_p1_wrdata[23], main_a7ddrphy_dfi_p1_wrdata[7], main_a7ddrphy_dfi_p0_wrdata[23], main_a7ddrphy_dfi_p0_wrdata[7]}, main_a7ddrphy_bitslip7_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip7_value1 <= (main_a7ddrphy_bitslip7_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip7_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip7_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1);
+    main_a7ddrphy_bitslip7_r1 <= {main_a7ddrphy_bitslip71, main_a7ddrphy_bitslip7_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip8_value0 <= (main_a7ddrphy_bitslip8_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip8_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip8_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1);
+    main_a7ddrphy_bitslip8_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[24], main_a7ddrphy_dfi_p3_wrdata[8], main_a7ddrphy_dfi_p2_wrdata[24], main_a7ddrphy_dfi_p2_wrdata[8], main_a7ddrphy_dfi_p1_wrdata[24], main_a7ddrphy_dfi_p1_wrdata[8], main_a7ddrphy_dfi_p0_wrdata[24], main_a7ddrphy_dfi_p0_wrdata[8]}, main_a7ddrphy_bitslip8_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip8_value1 <= (main_a7ddrphy_bitslip8_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip8_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip8_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1);
+    main_a7ddrphy_bitslip8_r1 <= {main_a7ddrphy_bitslip81, main_a7ddrphy_bitslip8_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip9_value0 <= (main_a7ddrphy_bitslip9_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip9_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip9_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1);
+    main_a7ddrphy_bitslip9_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[25], main_a7ddrphy_dfi_p3_wrdata[9], main_a7ddrphy_dfi_p2_wrdata[25], main_a7ddrphy_dfi_p2_wrdata[9], main_a7ddrphy_dfi_p1_wrdata[25], main_a7ddrphy_dfi_p1_wrdata[9], main_a7ddrphy_dfi_p0_wrdata[25], main_a7ddrphy_dfi_p0_wrdata[9]}, main_a7ddrphy_bitslip9_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip9_value1 <= (main_a7ddrphy_bitslip9_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip9_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip9_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1);
+    main_a7ddrphy_bitslip9_r1 <= {main_a7ddrphy_bitslip91, main_a7ddrphy_bitslip9_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip10_value0 <= (main_a7ddrphy_bitslip10_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip10_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip10_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1);
+    main_a7ddrphy_bitslip10_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[26], main_a7ddrphy_dfi_p3_wrdata[10], main_a7ddrphy_dfi_p2_wrdata[26], main_a7ddrphy_dfi_p2_wrdata[10], main_a7ddrphy_dfi_p1_wrdata[26], main_a7ddrphy_dfi_p1_wrdata[10], main_a7ddrphy_dfi_p0_wrdata[26], main_a7ddrphy_dfi_p0_wrdata[10]}, main_a7ddrphy_bitslip10_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip10_value1 <= (main_a7ddrphy_bitslip10_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip10_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip10_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1);
+    main_a7ddrphy_bitslip10_r1 <= {main_a7ddrphy_bitslip101, main_a7ddrphy_bitslip10_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip11_value0 <= (main_a7ddrphy_bitslip11_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip11_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip11_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1);
+    main_a7ddrphy_bitslip11_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[27], main_a7ddrphy_dfi_p3_wrdata[11], main_a7ddrphy_dfi_p2_wrdata[27], main_a7ddrphy_dfi_p2_wrdata[11], main_a7ddrphy_dfi_p1_wrdata[27], main_a7ddrphy_dfi_p1_wrdata[11], main_a7ddrphy_dfi_p0_wrdata[27], main_a7ddrphy_dfi_p0_wrdata[11]}, main_a7ddrphy_bitslip11_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip11_value1 <= (main_a7ddrphy_bitslip11_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip11_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip11_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1);
+    main_a7ddrphy_bitslip11_r1 <= {main_a7ddrphy_bitslip111, main_a7ddrphy_bitslip11_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip12_value0 <= (main_a7ddrphy_bitslip12_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip12_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip12_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1);
+    main_a7ddrphy_bitslip12_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[28], main_a7ddrphy_dfi_p3_wrdata[12], main_a7ddrphy_dfi_p2_wrdata[28], main_a7ddrphy_dfi_p2_wrdata[12], main_a7ddrphy_dfi_p1_wrdata[28], main_a7ddrphy_dfi_p1_wrdata[12], main_a7ddrphy_dfi_p0_wrdata[28], main_a7ddrphy_dfi_p0_wrdata[12]}, main_a7ddrphy_bitslip12_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip12_value1 <= (main_a7ddrphy_bitslip12_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip12_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip12_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1);
+    main_a7ddrphy_bitslip12_r1 <= {main_a7ddrphy_bitslip121, main_a7ddrphy_bitslip12_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip13_value0 <= (main_a7ddrphy_bitslip13_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip13_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip13_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1);
+    main_a7ddrphy_bitslip13_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[29], main_a7ddrphy_dfi_p3_wrdata[13], main_a7ddrphy_dfi_p2_wrdata[29], main_a7ddrphy_dfi_p2_wrdata[13], main_a7ddrphy_dfi_p1_wrdata[29], main_a7ddrphy_dfi_p1_wrdata[13], main_a7ddrphy_dfi_p0_wrdata[29], main_a7ddrphy_dfi_p0_wrdata[13]}, main_a7ddrphy_bitslip13_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip13_value1 <= (main_a7ddrphy_bitslip13_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip13_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip13_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1);
+    main_a7ddrphy_bitslip13_r1 <= {main_a7ddrphy_bitslip131, main_a7ddrphy_bitslip13_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip14_value0 <= (main_a7ddrphy_bitslip14_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip14_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip14_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1);
+    main_a7ddrphy_bitslip14_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[30], main_a7ddrphy_dfi_p3_wrdata[14], main_a7ddrphy_dfi_p2_wrdata[30], main_a7ddrphy_dfi_p2_wrdata[14], main_a7ddrphy_dfi_p1_wrdata[30], main_a7ddrphy_dfi_p1_wrdata[14], main_a7ddrphy_dfi_p0_wrdata[30], main_a7ddrphy_dfi_p0_wrdata[14]}, main_a7ddrphy_bitslip14_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip14_value1 <= (main_a7ddrphy_bitslip14_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip14_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip14_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1);
+    main_a7ddrphy_bitslip14_r1 <= {main_a7ddrphy_bitslip141, main_a7ddrphy_bitslip14_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip15_value0 <= (main_a7ddrphy_bitslip15_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip15_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip15_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1);
+    main_a7ddrphy_bitslip15_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[31], main_a7ddrphy_dfi_p3_wrdata[15], main_a7ddrphy_dfi_p2_wrdata[31], main_a7ddrphy_dfi_p2_wrdata[15], main_a7ddrphy_dfi_p1_wrdata[31], main_a7ddrphy_dfi_p1_wrdata[15], main_a7ddrphy_dfi_p0_wrdata[31], main_a7ddrphy_dfi_p0_wrdata[15]}, main_a7ddrphy_bitslip15_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip15_value1 <= (main_a7ddrphy_bitslip15_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip15_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip15_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]};
-    a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en);
-    a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0;
-    a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1;
-    a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2;
-    a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3;
-    a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4;
-    a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5;
-    a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6;
-    a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en);
-    a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0;
-    a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1;
-    if (litedramcore_csr_dfi_p0_rddata_valid) begin
-        litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata;
+    main_a7ddrphy_bitslip15_r1 <= {main_a7ddrphy_bitslip151, main_a7ddrphy_bitslip15_r1[15:8]};
+    main_a7ddrphy_rddata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_rddata_en | main_a7ddrphy_dfi_p1_rddata_en) | main_a7ddrphy_dfi_p2_rddata_en) | main_a7ddrphy_dfi_p3_rddata_en);
+    main_a7ddrphy_rddata_en_tappeddelayline1 <= main_a7ddrphy_rddata_en_tappeddelayline0;
+    main_a7ddrphy_rddata_en_tappeddelayline2 <= main_a7ddrphy_rddata_en_tappeddelayline1;
+    main_a7ddrphy_rddata_en_tappeddelayline3 <= main_a7ddrphy_rddata_en_tappeddelayline2;
+    main_a7ddrphy_rddata_en_tappeddelayline4 <= main_a7ddrphy_rddata_en_tappeddelayline3;
+    main_a7ddrphy_rddata_en_tappeddelayline5 <= main_a7ddrphy_rddata_en_tappeddelayline4;
+    main_a7ddrphy_rddata_en_tappeddelayline6 <= main_a7ddrphy_rddata_en_tappeddelayline5;
+    main_a7ddrphy_rddata_en_tappeddelayline7 <= main_a7ddrphy_rddata_en_tappeddelayline6;
+    main_a7ddrphy_wrdata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_wrdata_en | main_a7ddrphy_dfi_p1_wrdata_en) | main_a7ddrphy_dfi_p2_wrdata_en) | main_a7ddrphy_dfi_p3_wrdata_en);
+    main_a7ddrphy_wrdata_en_tappeddelayline1 <= main_a7ddrphy_wrdata_en_tappeddelayline0;
+    main_a7ddrphy_wrdata_en_tappeddelayline2 <= main_a7ddrphy_wrdata_en_tappeddelayline1;
+    if (main_litedramcore_csr_dfi_p0_rddata_valid) begin
+        main_litedramcore_phaseinjector0_rddata_status <= main_litedramcore_csr_dfi_p0_rddata;
     end
-    if (litedramcore_csr_dfi_p1_rddata_valid) begin
-        litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata;
+    if (main_litedramcore_csr_dfi_p1_rddata_valid) begin
+        main_litedramcore_phaseinjector1_rddata_status <= main_litedramcore_csr_dfi_p1_rddata;
     end
-    if (litedramcore_csr_dfi_p2_rddata_valid) begin
-        litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata;
+    if (main_litedramcore_csr_dfi_p2_rddata_valid) begin
+        main_litedramcore_phaseinjector2_rddata_status <= main_litedramcore_csr_dfi_p2_rddata;
     end
-    if (litedramcore_csr_dfi_p3_rddata_valid) begin
-        litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata;
-    end
-    if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
-        litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
+    if (main_litedramcore_csr_dfi_p3_rddata_valid) begin
+        main_litedramcore_phaseinjector3_rddata_status <= main_litedramcore_csr_dfi_p3_rddata;
+    end
+    if ((main_litedramcore_timer_wait & (~main_litedramcore_timer_done0))) begin
+        main_litedramcore_timer_count1 <= (main_litedramcore_timer_count1 - 1'd1);
     end else begin
-        litedramcore_timer_count1 <= 10'd781;
+        main_litedramcore_timer_count1 <= 10'd781;
     end
-    litedramcore_postponer_req_o <= 1'd0;
-    if (litedramcore_postponer_req_i) begin
-        litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
-        if ((litedramcore_postponer_count == 1'd0)) begin
-            litedramcore_postponer_count <= 1'd0;
-            litedramcore_postponer_req_o <= 1'd1;
-        end
+    main_litedramcore_postponer_req_o <= 1'd0;
+    if (main_litedramcore_postponer_req_i) begin
+        main_litedramcore_postponer_count <= (main_litedramcore_postponer_count - 1'd1);
+        if ((main_litedramcore_postponer_count == 1'd0)) begin
+            main_litedramcore_postponer_count <= 1'd0;
+            main_litedramcore_postponer_req_o <= 1'd1;
+        end
     end
-    if (litedramcore_sequencer_start0) begin
-        litedramcore_sequencer_count <= 1'd0;
-    end else begin
-        if (litedramcore_sequencer_done1) begin
-            if ((litedramcore_sequencer_count != 1'd0)) begin
-                litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
-            end
-        end
-    end
-    litedramcore_cmd_payload_a <= 1'd0;
-    litedramcore_cmd_payload_ba <= 1'd0;
-    litedramcore_cmd_payload_cas <= 1'd0;
-    litedramcore_cmd_payload_ras <= 1'd0;
-    litedramcore_cmd_payload_we <= 1'd0;
-    litedramcore_sequencer_done1 <= 1'd0;
-    if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
-        litedramcore_cmd_payload_a <= 11'd1024;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd1;
-        litedramcore_cmd_payload_we <= 1'd1;
-    end
-    if ((litedramcore_sequencer_counter == 2'd3)) begin
-        litedramcore_cmd_payload_a <= 11'd1024;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd1;
-        litedramcore_cmd_payload_ras <= 1'd1;
-        litedramcore_cmd_payload_we <= 1'd0;
-    end
-    if ((litedramcore_sequencer_counter == 6'd35)) begin
-        litedramcore_cmd_payload_a <= 1'd0;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd0;
-        litedramcore_cmd_payload_we <= 1'd0;
-        litedramcore_sequencer_done1 <= 1'd1;
-    end
-    if ((litedramcore_sequencer_counter == 6'd35)) begin
-        litedramcore_sequencer_counter <= 1'd0;
-    end else begin
-        if ((litedramcore_sequencer_counter != 1'd0)) begin
-            litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
+    if (main_litedramcore_sequencer_start0) begin
+        main_litedramcore_sequencer_count <= 1'd0;
+    end else begin
+        if (main_litedramcore_sequencer_done1) begin
+            if ((main_litedramcore_sequencer_count != 1'd0)) begin
+                main_litedramcore_sequencer_count <= (main_litedramcore_sequencer_count - 1'd1);
+            end
+        end
+    end
+    main_litedramcore_cmd_payload_a <= 1'd0;
+    main_litedramcore_cmd_payload_ba <= 1'd0;
+    main_litedramcore_cmd_payload_cas <= 1'd0;
+    main_litedramcore_cmd_payload_ras <= 1'd0;
+    main_litedramcore_cmd_payload_we <= 1'd0;
+    main_litedramcore_sequencer_done1 <= 1'd0;
+    if ((main_litedramcore_sequencer_start1 & (main_litedramcore_sequencer_trigger == 1'd0))) begin
+        main_litedramcore_cmd_payload_a <= 11'd1024;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd1;
+        main_litedramcore_cmd_payload_we <= 1'd1;
+    end
+    if ((main_litedramcore_sequencer_trigger == 2'd3)) begin
+        main_litedramcore_cmd_payload_a <= 11'd1024;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd1;
+        main_litedramcore_cmd_payload_ras <= 1'd1;
+        main_litedramcore_cmd_payload_we <= 1'd0;
+    end
+    if ((main_litedramcore_sequencer_trigger == 6'd35)) begin
+        main_litedramcore_cmd_payload_a <= 1'd0;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd0;
+        main_litedramcore_cmd_payload_we <= 1'd0;
+        main_litedramcore_sequencer_done1 <= 1'd1;
+    end
+    if ((main_litedramcore_sequencer_trigger == 6'd35)) begin
+        main_litedramcore_sequencer_trigger <= 1'd0;
+    end else begin
+        if ((main_litedramcore_sequencer_trigger != 1'd0)) begin
+            main_litedramcore_sequencer_trigger <= (main_litedramcore_sequencer_trigger + 1'd1);
         end else begin
-            if (litedramcore_sequencer_start1) begin
-                litedramcore_sequencer_counter <= 1'd1;
+            if (main_litedramcore_sequencer_start1) begin
+                main_litedramcore_sequencer_trigger <= 1'd1;
             end
         end
     end
-    if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
-        litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
+    if ((main_litedramcore_zqcs_timer_wait & (~main_litedramcore_zqcs_timer_done0))) begin
+        main_litedramcore_zqcs_timer_count1 <= (main_litedramcore_zqcs_timer_count1 - 1'd1);
     end else begin
-        litedramcore_zqcs_timer_count1 <= 27'd99999999;
-    end
-    litedramcore_zqcs_executer_done <= 1'd0;
-    if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
-        litedramcore_cmd_payload_a <= 11'd1024;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd1;
-        litedramcore_cmd_payload_we <= 1'd1;
-    end
-    if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
-        litedramcore_cmd_payload_a <= 1'd0;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd0;
-        litedramcore_cmd_payload_we <= 1'd1;
-    end
-    if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
-        litedramcore_cmd_payload_a <= 1'd0;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd0;
-        litedramcore_cmd_payload_we <= 1'd0;
-        litedramcore_zqcs_executer_done <= 1'd1;
-    end
-    if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
-        litedramcore_zqcs_executer_counter <= 1'd0;
+        main_litedramcore_zqcs_timer_count1 <= 27'd99999999;
+    end
+    main_litedramcore_zqcs_executer_done <= 1'd0;
+    if ((main_litedramcore_zqcs_executer_start & (main_litedramcore_zqcs_executer_trigger == 1'd0))) begin
+        main_litedramcore_cmd_payload_a <= 11'd1024;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd1;
+        main_litedramcore_cmd_payload_we <= 1'd1;
+    end
+    if ((main_litedramcore_zqcs_executer_trigger == 2'd3)) begin
+        main_litedramcore_cmd_payload_a <= 1'd0;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd0;
+        main_litedramcore_cmd_payload_we <= 1'd1;
+    end
+    if ((main_litedramcore_zqcs_executer_trigger == 5'd19)) begin
+        main_litedramcore_cmd_payload_a <= 1'd0;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd0;
+        main_litedramcore_cmd_payload_we <= 1'd0;
+        main_litedramcore_zqcs_executer_done <= 1'd1;
+    end
+    if ((main_litedramcore_zqcs_executer_trigger == 5'd19)) begin
+        main_litedramcore_zqcs_executer_trigger <= 1'd0;
     end else begin
-        if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
-            litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
+        if ((main_litedramcore_zqcs_executer_trigger != 1'd0)) begin
+            main_litedramcore_zqcs_executer_trigger <= (main_litedramcore_zqcs_executer_trigger + 1'd1);
         end else begin
-            if (litedramcore_zqcs_executer_start) begin
-                litedramcore_zqcs_executer_counter <= 1'd1;
+            if (main_litedramcore_zqcs_executer_start) begin
+                main_litedramcore_zqcs_executer_trigger <= 1'd1;
             end
         end
     end
-    litedramcore_refresher_state <= litedramcore_refresher_next_state;
-    if (litedramcore_bankmachine0_row_close) begin
-        litedramcore_bankmachine0_row_opened <= 1'd0;
+    builder_refresher_state <= builder_refresher_next_state;
+    if (main_litedramcore_bankmachine0_row_close) begin
+        main_litedramcore_bankmachine0_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine0_row_open) begin
-            litedramcore_bankmachine0_row_opened <= 1'd1;
-            litedramcore_bankmachine0_row <= litedramcore_bankmachine0_source_source_payload_addr[20:7];
+        if (main_litedramcore_bankmachine0_row_open) begin
+            main_litedramcore_bankmachine0_row_opened <= 1'd1;
+            main_litedramcore_bankmachine0_row <= main_litedramcore_bankmachine0_source_source_payload_addr[20:7];
         end
     end
-    if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin
-        litedramcore_bankmachine0_produce <= (litedramcore_bankmachine0_produce + 1'd1);
+    if (((main_litedramcore_bankmachine0_syncfifo0_we & main_litedramcore_bankmachine0_syncfifo0_writable) & (~main_litedramcore_bankmachine0_replace))) begin
+        main_litedramcore_bankmachine0_produce <= (main_litedramcore_bankmachine0_produce + 1'd1);
     end
-    if (litedramcore_bankmachine0_do_read) begin
-        litedramcore_bankmachine0_consume <= (litedramcore_bankmachine0_consume + 1'd1);
+    if (main_litedramcore_bankmachine0_do_read) begin
+        main_litedramcore_bankmachine0_consume <= (main_litedramcore_bankmachine0_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin
-        if ((~litedramcore_bankmachine0_do_read)) begin
-            litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level + 1'd1);
+    if (((main_litedramcore_bankmachine0_syncfifo0_we & main_litedramcore_bankmachine0_syncfifo0_writable) & (~main_litedramcore_bankmachine0_replace))) begin
+        if ((~main_litedramcore_bankmachine0_do_read)) begin
+            main_litedramcore_bankmachine0_level <= (main_litedramcore_bankmachine0_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine0_do_read) begin
-            litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level - 1'd1);
+        if (main_litedramcore_bankmachine0_do_read) begin
+            main_litedramcore_bankmachine0_level <= (main_litedramcore_bankmachine0_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine0_pipe_valid_source_valid <= litedramcore_bankmachine0_pipe_valid_sink_valid;
-        litedramcore_bankmachine0_pipe_valid_source_first <= litedramcore_bankmachine0_pipe_valid_sink_first;
-        litedramcore_bankmachine0_pipe_valid_source_last <= litedramcore_bankmachine0_pipe_valid_sink_last;
-        litedramcore_bankmachine0_pipe_valid_source_payload_we <= litedramcore_bankmachine0_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine0_pipe_valid_source_valid) | main_litedramcore_bankmachine0_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine0_pipe_valid_source_valid <= main_litedramcore_bankmachine0_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine0_pipe_valid_source_first <= main_litedramcore_bankmachine0_pipe_valid_sink_first;
+        main_litedramcore_bankmachine0_pipe_valid_source_last <= main_litedramcore_bankmachine0_pipe_valid_sink_last;
+        main_litedramcore_bankmachine0_pipe_valid_source_payload_we <= main_litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine0_twtpcon_valid) begin
-        litedramcore_bankmachine0_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine0_twtpcon_valid) begin
+        main_litedramcore_bankmachine0_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
-            litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine0_twtpcon_ready)) begin
+            main_litedramcore_bankmachine0_twtpcon_count <= (main_litedramcore_bankmachine0_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine0_trccon_valid) begin
-        litedramcore_bankmachine0_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine0_trccon_valid) begin
+        main_litedramcore_bankmachine0_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine0_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine0_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine0_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine0_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine0_trccon_ready)) begin
-            litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine0_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine0_trccon_ready)) begin
+            main_litedramcore_bankmachine0_trccon_count <= (main_litedramcore_bankmachine0_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine0_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine0_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine0_trascon_valid) begin
-        litedramcore_bankmachine0_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine0_trascon_valid) begin
+        main_litedramcore_bankmachine0_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine0_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine0_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine0_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine0_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine0_trascon_ready)) begin
-            litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine0_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine0_trascon_ready)) begin
+            main_litedramcore_bankmachine0_trascon_count <= (main_litedramcore_bankmachine0_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine0_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine0_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
-    if (litedramcore_bankmachine1_row_close) begin
-        litedramcore_bankmachine1_row_opened <= 1'd0;
+    builder_bankmachine0_state <= builder_bankmachine0_next_state;
+    if (main_litedramcore_bankmachine1_row_close) begin
+        main_litedramcore_bankmachine1_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine1_row_open) begin
-            litedramcore_bankmachine1_row_opened <= 1'd1;
-            litedramcore_bankmachine1_row <= litedramcore_bankmachine1_source_source_payload_addr[20:7];
+        if (main_litedramcore_bankmachine1_row_open) begin
+            main_litedramcore_bankmachine1_row_opened <= 1'd1;
+            main_litedramcore_bankmachine1_row <= main_litedramcore_bankmachine1_source_source_payload_addr[20:7];
         end
     end
-    if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin
-        litedramcore_bankmachine1_produce <= (litedramcore_bankmachine1_produce + 1'd1);
+    if (((main_litedramcore_bankmachine1_syncfifo1_we & main_litedramcore_bankmachine1_syncfifo1_writable) & (~main_litedramcore_bankmachine1_replace))) begin
+        main_litedramcore_bankmachine1_produce <= (main_litedramcore_bankmachine1_produce + 1'd1);
     end
-    if (litedramcore_bankmachine1_do_read) begin
-        litedramcore_bankmachine1_consume <= (litedramcore_bankmachine1_consume + 1'd1);
+    if (main_litedramcore_bankmachine1_do_read) begin
+        main_litedramcore_bankmachine1_consume <= (main_litedramcore_bankmachine1_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin
-        if ((~litedramcore_bankmachine1_do_read)) begin
-            litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level + 1'd1);
+    if (((main_litedramcore_bankmachine1_syncfifo1_we & main_litedramcore_bankmachine1_syncfifo1_writable) & (~main_litedramcore_bankmachine1_replace))) begin
+        if ((~main_litedramcore_bankmachine1_do_read)) begin
+            main_litedramcore_bankmachine1_level <= (main_litedramcore_bankmachine1_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine1_do_read) begin
-            litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level - 1'd1);
+        if (main_litedramcore_bankmachine1_do_read) begin
+            main_litedramcore_bankmachine1_level <= (main_litedramcore_bankmachine1_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine1_pipe_valid_source_valid <= litedramcore_bankmachine1_pipe_valid_sink_valid;
-        litedramcore_bankmachine1_pipe_valid_source_first <= litedramcore_bankmachine1_pipe_valid_sink_first;
-        litedramcore_bankmachine1_pipe_valid_source_last <= litedramcore_bankmachine1_pipe_valid_sink_last;
-        litedramcore_bankmachine1_pipe_valid_source_payload_we <= litedramcore_bankmachine1_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine1_pipe_valid_source_valid) | main_litedramcore_bankmachine1_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine1_pipe_valid_source_valid <= main_litedramcore_bankmachine1_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine1_pipe_valid_source_first <= main_litedramcore_bankmachine1_pipe_valid_sink_first;
+        main_litedramcore_bankmachine1_pipe_valid_source_last <= main_litedramcore_bankmachine1_pipe_valid_sink_last;
+        main_litedramcore_bankmachine1_pipe_valid_source_payload_we <= main_litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine1_twtpcon_valid) begin
-        litedramcore_bankmachine1_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine1_twtpcon_valid) begin
+        main_litedramcore_bankmachine1_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
-            litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine1_twtpcon_ready)) begin
+            main_litedramcore_bankmachine1_twtpcon_count <= (main_litedramcore_bankmachine1_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine1_trccon_valid) begin
-        litedramcore_bankmachine1_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine1_trccon_valid) begin
+        main_litedramcore_bankmachine1_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine1_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine1_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine1_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine1_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine1_trccon_ready)) begin
-            litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine1_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine1_trccon_ready)) begin
+            main_litedramcore_bankmachine1_trccon_count <= (main_litedramcore_bankmachine1_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine1_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine1_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine1_trascon_valid) begin
-        litedramcore_bankmachine1_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine1_trascon_valid) begin
+        main_litedramcore_bankmachine1_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine1_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine1_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine1_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine1_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine1_trascon_ready)) begin
-            litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine1_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine1_trascon_ready)) begin
+            main_litedramcore_bankmachine1_trascon_count <= (main_litedramcore_bankmachine1_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine1_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine1_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
-    if (litedramcore_bankmachine2_row_close) begin
-        litedramcore_bankmachine2_row_opened <= 1'd0;
+    builder_bankmachine1_state <= builder_bankmachine1_next_state;
+    if (main_litedramcore_bankmachine2_row_close) begin
+        main_litedramcore_bankmachine2_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine2_row_open) begin
-            litedramcore_bankmachine2_row_opened <= 1'd1;
-            litedramcore_bankmachine2_row <= litedramcore_bankmachine2_source_source_payload_addr[20:7];
+        if (main_litedramcore_bankmachine2_row_open) begin
+            main_litedramcore_bankmachine2_row_opened <= 1'd1;
+            main_litedramcore_bankmachine2_row <= main_litedramcore_bankmachine2_source_source_payload_addr[20:7];
         end
     end
-    if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin
-        litedramcore_bankmachine2_produce <= (litedramcore_bankmachine2_produce + 1'd1);
+    if (((main_litedramcore_bankmachine2_syncfifo2_we & main_litedramcore_bankmachine2_syncfifo2_writable) & (~main_litedramcore_bankmachine2_replace))) begin
+        main_litedramcore_bankmachine2_produce <= (main_litedramcore_bankmachine2_produce + 1'd1);
     end
-    if (litedramcore_bankmachine2_do_read) begin
-        litedramcore_bankmachine2_consume <= (litedramcore_bankmachine2_consume + 1'd1);
+    if (main_litedramcore_bankmachine2_do_read) begin
+        main_litedramcore_bankmachine2_consume <= (main_litedramcore_bankmachine2_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin
-        if ((~litedramcore_bankmachine2_do_read)) begin
-            litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level + 1'd1);
+    if (((main_litedramcore_bankmachine2_syncfifo2_we & main_litedramcore_bankmachine2_syncfifo2_writable) & (~main_litedramcore_bankmachine2_replace))) begin
+        if ((~main_litedramcore_bankmachine2_do_read)) begin
+            main_litedramcore_bankmachine2_level <= (main_litedramcore_bankmachine2_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine2_do_read) begin
-            litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level - 1'd1);
+        if (main_litedramcore_bankmachine2_do_read) begin
+            main_litedramcore_bankmachine2_level <= (main_litedramcore_bankmachine2_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine2_pipe_valid_source_valid <= litedramcore_bankmachine2_pipe_valid_sink_valid;
-        litedramcore_bankmachine2_pipe_valid_source_first <= litedramcore_bankmachine2_pipe_valid_sink_first;
-        litedramcore_bankmachine2_pipe_valid_source_last <= litedramcore_bankmachine2_pipe_valid_sink_last;
-        litedramcore_bankmachine2_pipe_valid_source_payload_we <= litedramcore_bankmachine2_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine2_pipe_valid_source_valid) | main_litedramcore_bankmachine2_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine2_pipe_valid_source_valid <= main_litedramcore_bankmachine2_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine2_pipe_valid_source_first <= main_litedramcore_bankmachine2_pipe_valid_sink_first;
+        main_litedramcore_bankmachine2_pipe_valid_source_last <= main_litedramcore_bankmachine2_pipe_valid_sink_last;
+        main_litedramcore_bankmachine2_pipe_valid_source_payload_we <= main_litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine2_twtpcon_valid) begin
-        litedramcore_bankmachine2_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine2_twtpcon_valid) begin
+        main_litedramcore_bankmachine2_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
-            litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine2_twtpcon_ready)) begin
+            main_litedramcore_bankmachine2_twtpcon_count <= (main_litedramcore_bankmachine2_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine2_trccon_valid) begin
-        litedramcore_bankmachine2_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine2_trccon_valid) begin
+        main_litedramcore_bankmachine2_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine2_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine2_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine2_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine2_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine2_trccon_ready)) begin
-            litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine2_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine2_trccon_ready)) begin
+            main_litedramcore_bankmachine2_trccon_count <= (main_litedramcore_bankmachine2_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine2_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine2_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine2_trascon_valid) begin
-        litedramcore_bankmachine2_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine2_trascon_valid) begin
+        main_litedramcore_bankmachine2_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine2_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine2_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine2_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine2_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine2_trascon_ready)) begin
-            litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine2_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine2_trascon_ready)) begin
+            main_litedramcore_bankmachine2_trascon_count <= (main_litedramcore_bankmachine2_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine2_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine2_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
-    if (litedramcore_bankmachine3_row_close) begin
-        litedramcore_bankmachine3_row_opened <= 1'd0;
+    builder_bankmachine2_state <= builder_bankmachine2_next_state;
+    if (main_litedramcore_bankmachine3_row_close) begin
+        main_litedramcore_bankmachine3_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine3_row_open) begin
-            litedramcore_bankmachine3_row_opened <= 1'd1;
-            litedramcore_bankmachine3_row <= litedramcore_bankmachine3_source_source_payload_addr[20:7];
+        if (main_litedramcore_bankmachine3_row_open) begin
+            main_litedramcore_bankmachine3_row_opened <= 1'd1;
+            main_litedramcore_bankmachine3_row <= main_litedramcore_bankmachine3_source_source_payload_addr[20:7];
         end
     end
-    if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin
-        litedramcore_bankmachine3_produce <= (litedramcore_bankmachine3_produce + 1'd1);
+    if (((main_litedramcore_bankmachine3_syncfifo3_we & main_litedramcore_bankmachine3_syncfifo3_writable) & (~main_litedramcore_bankmachine3_replace))) begin
+        main_litedramcore_bankmachine3_produce <= (main_litedramcore_bankmachine3_produce + 1'd1);
     end
-    if (litedramcore_bankmachine3_do_read) begin
-        litedramcore_bankmachine3_consume <= (litedramcore_bankmachine3_consume + 1'd1);
+    if (main_litedramcore_bankmachine3_do_read) begin
+        main_litedramcore_bankmachine3_consume <= (main_litedramcore_bankmachine3_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin
-        if ((~litedramcore_bankmachine3_do_read)) begin
-            litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level + 1'd1);
+    if (((main_litedramcore_bankmachine3_syncfifo3_we & main_litedramcore_bankmachine3_syncfifo3_writable) & (~main_litedramcore_bankmachine3_replace))) begin
+        if ((~main_litedramcore_bankmachine3_do_read)) begin
+            main_litedramcore_bankmachine3_level <= (main_litedramcore_bankmachine3_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine3_do_read) begin
-            litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level - 1'd1);
+        if (main_litedramcore_bankmachine3_do_read) begin
+            main_litedramcore_bankmachine3_level <= (main_litedramcore_bankmachine3_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine3_pipe_valid_source_valid <= litedramcore_bankmachine3_pipe_valid_sink_valid;
-        litedramcore_bankmachine3_pipe_valid_source_first <= litedramcore_bankmachine3_pipe_valid_sink_first;
-        litedramcore_bankmachine3_pipe_valid_source_last <= litedramcore_bankmachine3_pipe_valid_sink_last;
-        litedramcore_bankmachine3_pipe_valid_source_payload_we <= litedramcore_bankmachine3_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine3_pipe_valid_source_valid) | main_litedramcore_bankmachine3_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine3_pipe_valid_source_valid <= main_litedramcore_bankmachine3_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine3_pipe_valid_source_first <= main_litedramcore_bankmachine3_pipe_valid_sink_first;
+        main_litedramcore_bankmachine3_pipe_valid_source_last <= main_litedramcore_bankmachine3_pipe_valid_sink_last;
+        main_litedramcore_bankmachine3_pipe_valid_source_payload_we <= main_litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine3_twtpcon_valid) begin
-        litedramcore_bankmachine3_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine3_twtpcon_valid) begin
+        main_litedramcore_bankmachine3_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
-            litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine3_twtpcon_ready)) begin
+            main_litedramcore_bankmachine3_twtpcon_count <= (main_litedramcore_bankmachine3_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine3_trccon_valid) begin
-        litedramcore_bankmachine3_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine3_trccon_valid) begin
+        main_litedramcore_bankmachine3_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine3_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine3_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine3_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine3_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine3_trccon_ready)) begin
-            litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine3_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine3_trccon_ready)) begin
+            main_litedramcore_bankmachine3_trccon_count <= (main_litedramcore_bankmachine3_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine3_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine3_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine3_trascon_valid) begin
-        litedramcore_bankmachine3_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine3_trascon_valid) begin
+        main_litedramcore_bankmachine3_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine3_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine3_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine3_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine3_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine3_trascon_ready)) begin
-            litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine3_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine3_trascon_ready)) begin
+            main_litedramcore_bankmachine3_trascon_count <= (main_litedramcore_bankmachine3_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine3_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine3_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
-    if (litedramcore_bankmachine4_row_close) begin
-        litedramcore_bankmachine4_row_opened <= 1'd0;
+    builder_bankmachine3_state <= builder_bankmachine3_next_state;
+    if (main_litedramcore_bankmachine4_row_close) begin
+        main_litedramcore_bankmachine4_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine4_row_open) begin
-            litedramcore_bankmachine4_row_opened <= 1'd1;
-            litedramcore_bankmachine4_row <= litedramcore_bankmachine4_source_source_payload_addr[20:7];
+        if (main_litedramcore_bankmachine4_row_open) begin
+            main_litedramcore_bankmachine4_row_opened <= 1'd1;
+            main_litedramcore_bankmachine4_row <= main_litedramcore_bankmachine4_source_source_payload_addr[20:7];
         end
     end
-    if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin
-        litedramcore_bankmachine4_produce <= (litedramcore_bankmachine4_produce + 1'd1);
+    if (((main_litedramcore_bankmachine4_syncfifo4_we & main_litedramcore_bankmachine4_syncfifo4_writable) & (~main_litedramcore_bankmachine4_replace))) begin
+        main_litedramcore_bankmachine4_produce <= (main_litedramcore_bankmachine4_produce + 1'd1);
     end
-    if (litedramcore_bankmachine4_do_read) begin
-        litedramcore_bankmachine4_consume <= (litedramcore_bankmachine4_consume + 1'd1);
+    if (main_litedramcore_bankmachine4_do_read) begin
+        main_litedramcore_bankmachine4_consume <= (main_litedramcore_bankmachine4_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin
-        if ((~litedramcore_bankmachine4_do_read)) begin
-            litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level + 1'd1);
+    if (((main_litedramcore_bankmachine4_syncfifo4_we & main_litedramcore_bankmachine4_syncfifo4_writable) & (~main_litedramcore_bankmachine4_replace))) begin
+        if ((~main_litedramcore_bankmachine4_do_read)) begin
+            main_litedramcore_bankmachine4_level <= (main_litedramcore_bankmachine4_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine4_do_read) begin
-            litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level - 1'd1);
+        if (main_litedramcore_bankmachine4_do_read) begin
+            main_litedramcore_bankmachine4_level <= (main_litedramcore_bankmachine4_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine4_pipe_valid_source_valid <= litedramcore_bankmachine4_pipe_valid_sink_valid;
-        litedramcore_bankmachine4_pipe_valid_source_first <= litedramcore_bankmachine4_pipe_valid_sink_first;
-        litedramcore_bankmachine4_pipe_valid_source_last <= litedramcore_bankmachine4_pipe_valid_sink_last;
-        litedramcore_bankmachine4_pipe_valid_source_payload_we <= litedramcore_bankmachine4_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine4_pipe_valid_source_valid) | main_litedramcore_bankmachine4_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine4_pipe_valid_source_valid <= main_litedramcore_bankmachine4_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine4_pipe_valid_source_first <= main_litedramcore_bankmachine4_pipe_valid_sink_first;
+        main_litedramcore_bankmachine4_pipe_valid_source_last <= main_litedramcore_bankmachine4_pipe_valid_sink_last;
+        main_litedramcore_bankmachine4_pipe_valid_source_payload_we <= main_litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine4_twtpcon_valid) begin
-        litedramcore_bankmachine4_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine4_twtpcon_valid) begin
+        main_litedramcore_bankmachine4_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
-            litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine4_twtpcon_ready)) begin
+            main_litedramcore_bankmachine4_twtpcon_count <= (main_litedramcore_bankmachine4_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine4_trccon_valid) begin
-        litedramcore_bankmachine4_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine4_trccon_valid) begin
+        main_litedramcore_bankmachine4_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine4_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine4_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine4_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine4_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine4_trccon_ready)) begin
-            litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine4_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine4_trccon_ready)) begin
+            main_litedramcore_bankmachine4_trccon_count <= (main_litedramcore_bankmachine4_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine4_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine4_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine4_trascon_valid) begin
-        litedramcore_bankmachine4_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine4_trascon_valid) begin
+        main_litedramcore_bankmachine4_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine4_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine4_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine4_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine4_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine4_trascon_ready)) begin
-            litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine4_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine4_trascon_ready)) begin
+            main_litedramcore_bankmachine4_trascon_count <= (main_litedramcore_bankmachine4_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine4_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine4_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
-    if (litedramcore_bankmachine5_row_close) begin
-        litedramcore_bankmachine5_row_opened <= 1'd0;
+    builder_bankmachine4_state <= builder_bankmachine4_next_state;
+    if (main_litedramcore_bankmachine5_row_close) begin
+        main_litedramcore_bankmachine5_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine5_row_open) begin
-            litedramcore_bankmachine5_row_opened <= 1'd1;
-            litedramcore_bankmachine5_row <= litedramcore_bankmachine5_source_source_payload_addr[20:7];
+        if (main_litedramcore_bankmachine5_row_open) begin
+            main_litedramcore_bankmachine5_row_opened <= 1'd1;
+            main_litedramcore_bankmachine5_row <= main_litedramcore_bankmachine5_source_source_payload_addr[20:7];
         end
     end
-    if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin
-        litedramcore_bankmachine5_produce <= (litedramcore_bankmachine5_produce + 1'd1);
+    if (((main_litedramcore_bankmachine5_syncfifo5_we & main_litedramcore_bankmachine5_syncfifo5_writable) & (~main_litedramcore_bankmachine5_replace))) begin
+        main_litedramcore_bankmachine5_produce <= (main_litedramcore_bankmachine5_produce + 1'd1);
     end
-    if (litedramcore_bankmachine5_do_read) begin
-        litedramcore_bankmachine5_consume <= (litedramcore_bankmachine5_consume + 1'd1);
+    if (main_litedramcore_bankmachine5_do_read) begin
+        main_litedramcore_bankmachine5_consume <= (main_litedramcore_bankmachine5_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin
-        if ((~litedramcore_bankmachine5_do_read)) begin
-            litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level + 1'd1);
+    if (((main_litedramcore_bankmachine5_syncfifo5_we & main_litedramcore_bankmachine5_syncfifo5_writable) & (~main_litedramcore_bankmachine5_replace))) begin
+        if ((~main_litedramcore_bankmachine5_do_read)) begin
+            main_litedramcore_bankmachine5_level <= (main_litedramcore_bankmachine5_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine5_do_read) begin
-            litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level - 1'd1);
+        if (main_litedramcore_bankmachine5_do_read) begin
+            main_litedramcore_bankmachine5_level <= (main_litedramcore_bankmachine5_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine5_pipe_valid_source_valid <= litedramcore_bankmachine5_pipe_valid_sink_valid;
-        litedramcore_bankmachine5_pipe_valid_source_first <= litedramcore_bankmachine5_pipe_valid_sink_first;
-        litedramcore_bankmachine5_pipe_valid_source_last <= litedramcore_bankmachine5_pipe_valid_sink_last;
-        litedramcore_bankmachine5_pipe_valid_source_payload_we <= litedramcore_bankmachine5_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine5_pipe_valid_source_valid) | main_litedramcore_bankmachine5_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine5_pipe_valid_source_valid <= main_litedramcore_bankmachine5_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine5_pipe_valid_source_first <= main_litedramcore_bankmachine5_pipe_valid_sink_first;
+        main_litedramcore_bankmachine5_pipe_valid_source_last <= main_litedramcore_bankmachine5_pipe_valid_sink_last;
+        main_litedramcore_bankmachine5_pipe_valid_source_payload_we <= main_litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine5_twtpcon_valid) begin
-        litedramcore_bankmachine5_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine5_twtpcon_valid) begin
+        main_litedramcore_bankmachine5_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
-            litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine5_twtpcon_ready)) begin
+            main_litedramcore_bankmachine5_twtpcon_count <= (main_litedramcore_bankmachine5_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine5_trccon_valid) begin
-        litedramcore_bankmachine5_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine5_trccon_valid) begin
+        main_litedramcore_bankmachine5_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine5_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine5_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine5_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine5_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine5_trccon_ready)) begin
-            litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine5_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine5_trccon_ready)) begin
+            main_litedramcore_bankmachine5_trccon_count <= (main_litedramcore_bankmachine5_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine5_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine5_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine5_trascon_valid) begin
-        litedramcore_bankmachine5_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine5_trascon_valid) begin
+        main_litedramcore_bankmachine5_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine5_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine5_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine5_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine5_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine5_trascon_ready)) begin
-            litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine5_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine5_trascon_ready)) begin
+            main_litedramcore_bankmachine5_trascon_count <= (main_litedramcore_bankmachine5_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine5_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine5_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
-    if (litedramcore_bankmachine6_row_close) begin
-        litedramcore_bankmachine6_row_opened <= 1'd0;
+    builder_bankmachine5_state <= builder_bankmachine5_next_state;
+    if (main_litedramcore_bankmachine6_row_close) begin
+        main_litedramcore_bankmachine6_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine6_row_open) begin
-            litedramcore_bankmachine6_row_opened <= 1'd1;
-            litedramcore_bankmachine6_row <= litedramcore_bankmachine6_source_source_payload_addr[20:7];
+        if (main_litedramcore_bankmachine6_row_open) begin
+            main_litedramcore_bankmachine6_row_opened <= 1'd1;
+            main_litedramcore_bankmachine6_row <= main_litedramcore_bankmachine6_source_source_payload_addr[20:7];
         end
     end
-    if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin
-        litedramcore_bankmachine6_produce <= (litedramcore_bankmachine6_produce + 1'd1);
+    if (((main_litedramcore_bankmachine6_syncfifo6_we & main_litedramcore_bankmachine6_syncfifo6_writable) & (~main_litedramcore_bankmachine6_replace))) begin
+        main_litedramcore_bankmachine6_produce <= (main_litedramcore_bankmachine6_produce + 1'd1);
     end
-    if (litedramcore_bankmachine6_do_read) begin
-        litedramcore_bankmachine6_consume <= (litedramcore_bankmachine6_consume + 1'd1);
+    if (main_litedramcore_bankmachine6_do_read) begin
+        main_litedramcore_bankmachine6_consume <= (main_litedramcore_bankmachine6_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin
-        if ((~litedramcore_bankmachine6_do_read)) begin
-            litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level + 1'd1);
+    if (((main_litedramcore_bankmachine6_syncfifo6_we & main_litedramcore_bankmachine6_syncfifo6_writable) & (~main_litedramcore_bankmachine6_replace))) begin
+        if ((~main_litedramcore_bankmachine6_do_read)) begin
+            main_litedramcore_bankmachine6_level <= (main_litedramcore_bankmachine6_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine6_do_read) begin
-            litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level - 1'd1);
+        if (main_litedramcore_bankmachine6_do_read) begin
+            main_litedramcore_bankmachine6_level <= (main_litedramcore_bankmachine6_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine6_pipe_valid_source_valid <= litedramcore_bankmachine6_pipe_valid_sink_valid;
-        litedramcore_bankmachine6_pipe_valid_source_first <= litedramcore_bankmachine6_pipe_valid_sink_first;
-        litedramcore_bankmachine6_pipe_valid_source_last <= litedramcore_bankmachine6_pipe_valid_sink_last;
-        litedramcore_bankmachine6_pipe_valid_source_payload_we <= litedramcore_bankmachine6_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine6_pipe_valid_source_valid) | main_litedramcore_bankmachine6_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine6_pipe_valid_source_valid <= main_litedramcore_bankmachine6_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine6_pipe_valid_source_first <= main_litedramcore_bankmachine6_pipe_valid_sink_first;
+        main_litedramcore_bankmachine6_pipe_valid_source_last <= main_litedramcore_bankmachine6_pipe_valid_sink_last;
+        main_litedramcore_bankmachine6_pipe_valid_source_payload_we <= main_litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine6_twtpcon_valid) begin
-        litedramcore_bankmachine6_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine6_twtpcon_valid) begin
+        main_litedramcore_bankmachine6_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
-            litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine6_twtpcon_ready)) begin
+            main_litedramcore_bankmachine6_twtpcon_count <= (main_litedramcore_bankmachine6_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine6_trccon_valid) begin
-        litedramcore_bankmachine6_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine6_trccon_valid) begin
+        main_litedramcore_bankmachine6_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine6_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine6_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine6_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine6_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine6_trccon_ready)) begin
-            litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine6_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine6_trccon_ready)) begin
+            main_litedramcore_bankmachine6_trccon_count <= (main_litedramcore_bankmachine6_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine6_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine6_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine6_trascon_valid) begin
-        litedramcore_bankmachine6_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine6_trascon_valid) begin
+        main_litedramcore_bankmachine6_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine6_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine6_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine6_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine6_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine6_trascon_ready)) begin
-            litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine6_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine6_trascon_ready)) begin
+            main_litedramcore_bankmachine6_trascon_count <= (main_litedramcore_bankmachine6_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine6_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine6_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
-    if (litedramcore_bankmachine7_row_close) begin
-        litedramcore_bankmachine7_row_opened <= 1'd0;
+    builder_bankmachine6_state <= builder_bankmachine6_next_state;
+    if (main_litedramcore_bankmachine7_row_close) begin
+        main_litedramcore_bankmachine7_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine7_row_open) begin
-            litedramcore_bankmachine7_row_opened <= 1'd1;
-            litedramcore_bankmachine7_row <= litedramcore_bankmachine7_source_source_payload_addr[20:7];
+        if (main_litedramcore_bankmachine7_row_open) begin
+            main_litedramcore_bankmachine7_row_opened <= 1'd1;
+            main_litedramcore_bankmachine7_row <= main_litedramcore_bankmachine7_source_source_payload_addr[20:7];
         end
     end
-    if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin
-        litedramcore_bankmachine7_produce <= (litedramcore_bankmachine7_produce + 1'd1);
+    if (((main_litedramcore_bankmachine7_syncfifo7_we & main_litedramcore_bankmachine7_syncfifo7_writable) & (~main_litedramcore_bankmachine7_replace))) begin
+        main_litedramcore_bankmachine7_produce <= (main_litedramcore_bankmachine7_produce + 1'd1);
     end
-    if (litedramcore_bankmachine7_do_read) begin
-        litedramcore_bankmachine7_consume <= (litedramcore_bankmachine7_consume + 1'd1);
+    if (main_litedramcore_bankmachine7_do_read) begin
+        main_litedramcore_bankmachine7_consume <= (main_litedramcore_bankmachine7_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin
-        if ((~litedramcore_bankmachine7_do_read)) begin
-            litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level + 1'd1);
+    if (((main_litedramcore_bankmachine7_syncfifo7_we & main_litedramcore_bankmachine7_syncfifo7_writable) & (~main_litedramcore_bankmachine7_replace))) begin
+        if ((~main_litedramcore_bankmachine7_do_read)) begin
+            main_litedramcore_bankmachine7_level <= (main_litedramcore_bankmachine7_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine7_do_read) begin
-            litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level - 1'd1);
+        if (main_litedramcore_bankmachine7_do_read) begin
+            main_litedramcore_bankmachine7_level <= (main_litedramcore_bankmachine7_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine7_pipe_valid_source_valid <= litedramcore_bankmachine7_pipe_valid_sink_valid;
-        litedramcore_bankmachine7_pipe_valid_source_first <= litedramcore_bankmachine7_pipe_valid_sink_first;
-        litedramcore_bankmachine7_pipe_valid_source_last <= litedramcore_bankmachine7_pipe_valid_sink_last;
-        litedramcore_bankmachine7_pipe_valid_source_payload_we <= litedramcore_bankmachine7_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine7_pipe_valid_source_valid) | main_litedramcore_bankmachine7_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine7_pipe_valid_source_valid <= main_litedramcore_bankmachine7_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine7_pipe_valid_source_first <= main_litedramcore_bankmachine7_pipe_valid_sink_first;
+        main_litedramcore_bankmachine7_pipe_valid_source_last <= main_litedramcore_bankmachine7_pipe_valid_sink_last;
+        main_litedramcore_bankmachine7_pipe_valid_source_payload_we <= main_litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine7_twtpcon_valid) begin
-        litedramcore_bankmachine7_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine7_twtpcon_valid) begin
+        main_litedramcore_bankmachine7_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
-            litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine7_twtpcon_ready)) begin
+            main_litedramcore_bankmachine7_twtpcon_count <= (main_litedramcore_bankmachine7_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine7_trccon_valid) begin
-        litedramcore_bankmachine7_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine7_trccon_valid) begin
+        main_litedramcore_bankmachine7_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine7_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine7_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine7_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine7_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine7_trccon_ready)) begin
-            litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine7_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine7_trccon_ready)) begin
+            main_litedramcore_bankmachine7_trccon_count <= (main_litedramcore_bankmachine7_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine7_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine7_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine7_trascon_valid) begin
-        litedramcore_bankmachine7_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine7_trascon_valid) begin
+        main_litedramcore_bankmachine7_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine7_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine7_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine7_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine7_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine7_trascon_ready)) begin
-            litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine7_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine7_trascon_ready)) begin
+            main_litedramcore_bankmachine7_trascon_count <= (main_litedramcore_bankmachine7_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine7_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine7_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
-    if ((~litedramcore_en0)) begin
-        litedramcore_time0 <= 5'd31;
+    builder_bankmachine7_state <= builder_bankmachine7_next_state;
+    if ((~main_litedramcore_en0)) begin
+        main_litedramcore_time0 <= 5'd31;
     end else begin
-        if ((~litedramcore_max_time0)) begin
-            litedramcore_time0 <= (litedramcore_time0 - 1'd1);
+        if ((~main_litedramcore_max_time0)) begin
+            main_litedramcore_time0 <= (main_litedramcore_time0 - 1'd1);
         end
     end
-    if ((~litedramcore_en1)) begin
-        litedramcore_time1 <= 4'd15;
+    if ((~main_litedramcore_en1)) begin
+        main_litedramcore_time1 <= 4'd15;
     end else begin
-        if ((~litedramcore_max_time1)) begin
-            litedramcore_time1 <= (litedramcore_time1 - 1'd1);
+        if ((~main_litedramcore_max_time1)) begin
+            main_litedramcore_time1 <= (main_litedramcore_time1 - 1'd1);
         end
     end
-    if (litedramcore_choose_cmd_ce) begin
-        case (litedramcore_choose_cmd_grant)
+    if (main_litedramcore_choose_cmd_ce) begin
+        case (main_litedramcore_choose_cmd_grant)
             1'd0: begin
-                if (litedramcore_choose_cmd_request[1]) begin
-                    litedramcore_choose_cmd_grant <= 1'd1;
+                if (main_litedramcore_choose_cmd_request[1]) begin
+                    main_litedramcore_choose_cmd_grant <= 1'd1;
                 end else begin
-                    if (litedramcore_choose_cmd_request[2]) begin
-                        litedramcore_choose_cmd_grant <= 2'd2;
+                    if (main_litedramcore_choose_cmd_request[2]) begin
+                        main_litedramcore_choose_cmd_grant <= 2'd2;
                     end else begin
-                        if (litedramcore_choose_cmd_request[3]) begin
-                            litedramcore_choose_cmd_grant <= 2'd3;
+                        if (main_litedramcore_choose_cmd_request[3]) begin
+                            main_litedramcore_choose_cmd_grant <= 2'd3;
                         end else begin
-                            if (litedramcore_choose_cmd_request[4]) begin
-                                litedramcore_choose_cmd_grant <= 3'd4;
+                            if (main_litedramcore_choose_cmd_request[4]) begin
+                                main_litedramcore_choose_cmd_grant <= 3'd4;
                             end else begin
-                                if (litedramcore_choose_cmd_request[5]) begin
-                                    litedramcore_choose_cmd_grant <= 3'd5;
+                                if (main_litedramcore_choose_cmd_request[5]) begin
+                                    main_litedramcore_choose_cmd_grant <= 3'd5;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[6]) begin
-                                        litedramcore_choose_cmd_grant <= 3'd6;
+                                    if (main_litedramcore_choose_cmd_request[6]) begin
+                                        main_litedramcore_choose_cmd_grant <= 3'd6;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[7]) begin
-                                            litedramcore_choose_cmd_grant <= 3'd7;
+                                        if (main_litedramcore_choose_cmd_request[7]) begin
+                                            main_litedramcore_choose_cmd_grant <= 3'd7;
                                         end
                                     end
                                 end
@@ -13030,26 +13445,26 @@ always @(posedge sys_clk) begin
                 end
             end
             1'd1: begin
-                if (litedramcore_choose_cmd_request[2]) begin
-                    litedramcore_choose_cmd_grant <= 2'd2;
+                if (main_litedramcore_choose_cmd_request[2]) begin
+                    main_litedramcore_choose_cmd_grant <= 2'd2;
                 end else begin
-                    if (litedramcore_choose_cmd_request[3]) begin
-                        litedramcore_choose_cmd_grant <= 2'd3;
+                    if (main_litedramcore_choose_cmd_request[3]) begin
+                        main_litedramcore_choose_cmd_grant <= 2'd3;
                     end else begin
-                        if (litedramcore_choose_cmd_request[4]) begin
-                            litedramcore_choose_cmd_grant <= 3'd4;
+                        if (main_litedramcore_choose_cmd_request[4]) begin
+                            main_litedramcore_choose_cmd_grant <= 3'd4;
                         end else begin
-                            if (litedramcore_choose_cmd_request[5]) begin
-                                litedramcore_choose_cmd_grant <= 3'd5;
+                            if (main_litedramcore_choose_cmd_request[5]) begin
+                                main_litedramcore_choose_cmd_grant <= 3'd5;
                             end else begin
-                                if (litedramcore_choose_cmd_request[6]) begin
-                                    litedramcore_choose_cmd_grant <= 3'd6;
+                                if (main_litedramcore_choose_cmd_request[6]) begin
+                                    main_litedramcore_choose_cmd_grant <= 3'd6;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[7]) begin
-                                        litedramcore_choose_cmd_grant <= 3'd7;
+                                    if (main_litedramcore_choose_cmd_request[7]) begin
+                                        main_litedramcore_choose_cmd_grant <= 3'd7;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[0]) begin
-                                            litedramcore_choose_cmd_grant <= 1'd0;
+                                        if (main_litedramcore_choose_cmd_request[0]) begin
+                                            main_litedramcore_choose_cmd_grant <= 1'd0;
                                         end
                                     end
                                 end
@@ -13059,26 +13474,26 @@ always @(posedge sys_clk) begin
                 end
             end
             2'd2: begin
-                if (litedramcore_choose_cmd_request[3]) begin
-                    litedramcore_choose_cmd_grant <= 2'd3;
+                if (main_litedramcore_choose_cmd_request[3]) begin
+                    main_litedramcore_choose_cmd_grant <= 2'd3;
                 end else begin
-                    if (litedramcore_choose_cmd_request[4]) begin
-                        litedramcore_choose_cmd_grant <= 3'd4;
+                    if (main_litedramcore_choose_cmd_request[4]) begin
+                        main_litedramcore_choose_cmd_grant <= 3'd4;
                     end else begin
-                        if (litedramcore_choose_cmd_request[5]) begin
-                            litedramcore_choose_cmd_grant <= 3'd5;
+                        if (main_litedramcore_choose_cmd_request[5]) begin
+                            main_litedramcore_choose_cmd_grant <= 3'd5;
                         end else begin
-                            if (litedramcore_choose_cmd_request[6]) begin
-                                litedramcore_choose_cmd_grant <= 3'd6;
+                            if (main_litedramcore_choose_cmd_request[6]) begin
+                                main_litedramcore_choose_cmd_grant <= 3'd6;
                             end else begin
-                                if (litedramcore_choose_cmd_request[7]) begin
-                                    litedramcore_choose_cmd_grant <= 3'd7;
+                                if (main_litedramcore_choose_cmd_request[7]) begin
+                                    main_litedramcore_choose_cmd_grant <= 3'd7;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[0]) begin
-                                        litedramcore_choose_cmd_grant <= 1'd0;
+                                    if (main_litedramcore_choose_cmd_request[0]) begin
+                                        main_litedramcore_choose_cmd_grant <= 1'd0;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[1]) begin
-                                            litedramcore_choose_cmd_grant <= 1'd1;
+                                        if (main_litedramcore_choose_cmd_request[1]) begin
+                                            main_litedramcore_choose_cmd_grant <= 1'd1;
                                         end
                                     end
                                 end
@@ -13088,26 +13503,26 @@ always @(posedge sys_clk) begin
                 end
             end
             2'd3: begin
-                if (litedramcore_choose_cmd_request[4]) begin
-                    litedramcore_choose_cmd_grant <= 3'd4;
+                if (main_litedramcore_choose_cmd_request[4]) begin
+                    main_litedramcore_choose_cmd_grant <= 3'd4;
                 end else begin
-                    if (litedramcore_choose_cmd_request[5]) begin
-                        litedramcore_choose_cmd_grant <= 3'd5;
+                    if (main_litedramcore_choose_cmd_request[5]) begin
+                        main_litedramcore_choose_cmd_grant <= 3'd5;
                     end else begin
-                        if (litedramcore_choose_cmd_request[6]) begin
-                            litedramcore_choose_cmd_grant <= 3'd6;
+                        if (main_litedramcore_choose_cmd_request[6]) begin
+                            main_litedramcore_choose_cmd_grant <= 3'd6;
                         end else begin
-                            if (litedramcore_choose_cmd_request[7]) begin
-                                litedramcore_choose_cmd_grant <= 3'd7;
+                            if (main_litedramcore_choose_cmd_request[7]) begin
+                                main_litedramcore_choose_cmd_grant <= 3'd7;
                             end else begin
-                                if (litedramcore_choose_cmd_request[0]) begin
-                                    litedramcore_choose_cmd_grant <= 1'd0;
+                                if (main_litedramcore_choose_cmd_request[0]) begin
+                                    main_litedramcore_choose_cmd_grant <= 1'd0;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[1]) begin
-                                        litedramcore_choose_cmd_grant <= 1'd1;
+                                    if (main_litedramcore_choose_cmd_request[1]) begin
+                                        main_litedramcore_choose_cmd_grant <= 1'd1;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[2]) begin
-                                            litedramcore_choose_cmd_grant <= 2'd2;
+                                        if (main_litedramcore_choose_cmd_request[2]) begin
+                                            main_litedramcore_choose_cmd_grant <= 2'd2;
                                         end
                                     end
                                 end
@@ -13117,26 +13532,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd4: begin
-                if (litedramcore_choose_cmd_request[5]) begin
-                    litedramcore_choose_cmd_grant <= 3'd5;
+                if (main_litedramcore_choose_cmd_request[5]) begin
+                    main_litedramcore_choose_cmd_grant <= 3'd5;
                 end else begin
-                    if (litedramcore_choose_cmd_request[6]) begin
-                        litedramcore_choose_cmd_grant <= 3'd6;
+                    if (main_litedramcore_choose_cmd_request[6]) begin
+                        main_litedramcore_choose_cmd_grant <= 3'd6;
                     end else begin
-                        if (litedramcore_choose_cmd_request[7]) begin
-                            litedramcore_choose_cmd_grant <= 3'd7;
+                        if (main_litedramcore_choose_cmd_request[7]) begin
+                            main_litedramcore_choose_cmd_grant <= 3'd7;
                         end else begin
-                            if (litedramcore_choose_cmd_request[0]) begin
-                                litedramcore_choose_cmd_grant <= 1'd0;
+                            if (main_litedramcore_choose_cmd_request[0]) begin
+                                main_litedramcore_choose_cmd_grant <= 1'd0;
                             end else begin
-                                if (litedramcore_choose_cmd_request[1]) begin
-                                    litedramcore_choose_cmd_grant <= 1'd1;
+                                if (main_litedramcore_choose_cmd_request[1]) begin
+                                    main_litedramcore_choose_cmd_grant <= 1'd1;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[2]) begin
-                                        litedramcore_choose_cmd_grant <= 2'd2;
+                                    if (main_litedramcore_choose_cmd_request[2]) begin
+                                        main_litedramcore_choose_cmd_grant <= 2'd2;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[3]) begin
-                                            litedramcore_choose_cmd_grant <= 2'd3;
+                                        if (main_litedramcore_choose_cmd_request[3]) begin
+                                            main_litedramcore_choose_cmd_grant <= 2'd3;
                                         end
                                     end
                                 end
@@ -13146,26 +13561,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd5: begin
-                if (litedramcore_choose_cmd_request[6]) begin
-                    litedramcore_choose_cmd_grant <= 3'd6;
+                if (main_litedramcore_choose_cmd_request[6]) begin
+                    main_litedramcore_choose_cmd_grant <= 3'd6;
                 end else begin
-                    if (litedramcore_choose_cmd_request[7]) begin
-                        litedramcore_choose_cmd_grant <= 3'd7;
+                    if (main_litedramcore_choose_cmd_request[7]) begin
+                        main_litedramcore_choose_cmd_grant <= 3'd7;
                     end else begin
-                        if (litedramcore_choose_cmd_request[0]) begin
-                            litedramcore_choose_cmd_grant <= 1'd0;
+                        if (main_litedramcore_choose_cmd_request[0]) begin
+                            main_litedramcore_choose_cmd_grant <= 1'd0;
                         end else begin
-                            if (litedramcore_choose_cmd_request[1]) begin
-                                litedramcore_choose_cmd_grant <= 1'd1;
+                            if (main_litedramcore_choose_cmd_request[1]) begin
+                                main_litedramcore_choose_cmd_grant <= 1'd1;
                             end else begin
-                                if (litedramcore_choose_cmd_request[2]) begin
-                                    litedramcore_choose_cmd_grant <= 2'd2;
+                                if (main_litedramcore_choose_cmd_request[2]) begin
+                                    main_litedramcore_choose_cmd_grant <= 2'd2;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[3]) begin
-                                        litedramcore_choose_cmd_grant <= 2'd3;
+                                    if (main_litedramcore_choose_cmd_request[3]) begin
+                                        main_litedramcore_choose_cmd_grant <= 2'd3;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[4]) begin
-                                            litedramcore_choose_cmd_grant <= 3'd4;
+                                        if (main_litedramcore_choose_cmd_request[4]) begin
+                                            main_litedramcore_choose_cmd_grant <= 3'd4;
                                         end
                                     end
                                 end
@@ -13175,26 +13590,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd6: begin
-                if (litedramcore_choose_cmd_request[7]) begin
-                    litedramcore_choose_cmd_grant <= 3'd7;
+                if (main_litedramcore_choose_cmd_request[7]) begin
+                    main_litedramcore_choose_cmd_grant <= 3'd7;
                 end else begin
-                    if (litedramcore_choose_cmd_request[0]) begin
-                        litedramcore_choose_cmd_grant <= 1'd0;
+                    if (main_litedramcore_choose_cmd_request[0]) begin
+                        main_litedramcore_choose_cmd_grant <= 1'd0;
                     end else begin
-                        if (litedramcore_choose_cmd_request[1]) begin
-                            litedramcore_choose_cmd_grant <= 1'd1;
+                        if (main_litedramcore_choose_cmd_request[1]) begin
+                            main_litedramcore_choose_cmd_grant <= 1'd1;
                         end else begin
-                            if (litedramcore_choose_cmd_request[2]) begin
-                                litedramcore_choose_cmd_grant <= 2'd2;
+                            if (main_litedramcore_choose_cmd_request[2]) begin
+                                main_litedramcore_choose_cmd_grant <= 2'd2;
                             end else begin
-                                if (litedramcore_choose_cmd_request[3]) begin
-                                    litedramcore_choose_cmd_grant <= 2'd3;
+                                if (main_litedramcore_choose_cmd_request[3]) begin
+                                    main_litedramcore_choose_cmd_grant <= 2'd3;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[4]) begin
-                                        litedramcore_choose_cmd_grant <= 3'd4;
+                                    if (main_litedramcore_choose_cmd_request[4]) begin
+                                        main_litedramcore_choose_cmd_grant <= 3'd4;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[5]) begin
-                                            litedramcore_choose_cmd_grant <= 3'd5;
+                                        if (main_litedramcore_choose_cmd_request[5]) begin
+                                            main_litedramcore_choose_cmd_grant <= 3'd5;
                                         end
                                     end
                                 end
@@ -13204,26 +13619,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd7: begin
-                if (litedramcore_choose_cmd_request[0]) begin
-                    litedramcore_choose_cmd_grant <= 1'd0;
+                if (main_litedramcore_choose_cmd_request[0]) begin
+                    main_litedramcore_choose_cmd_grant <= 1'd0;
                 end else begin
-                    if (litedramcore_choose_cmd_request[1]) begin
-                        litedramcore_choose_cmd_grant <= 1'd1;
+                    if (main_litedramcore_choose_cmd_request[1]) begin
+                        main_litedramcore_choose_cmd_grant <= 1'd1;
                     end else begin
-                        if (litedramcore_choose_cmd_request[2]) begin
-                            litedramcore_choose_cmd_grant <= 2'd2;
+                        if (main_litedramcore_choose_cmd_request[2]) begin
+                            main_litedramcore_choose_cmd_grant <= 2'd2;
                         end else begin
-                            if (litedramcore_choose_cmd_request[3]) begin
-                                litedramcore_choose_cmd_grant <= 2'd3;
+                            if (main_litedramcore_choose_cmd_request[3]) begin
+                                main_litedramcore_choose_cmd_grant <= 2'd3;
                             end else begin
-                                if (litedramcore_choose_cmd_request[4]) begin
-                                    litedramcore_choose_cmd_grant <= 3'd4;
+                                if (main_litedramcore_choose_cmd_request[4]) begin
+                                    main_litedramcore_choose_cmd_grant <= 3'd4;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[5]) begin
-                                        litedramcore_choose_cmd_grant <= 3'd5;
+                                    if (main_litedramcore_choose_cmd_request[5]) begin
+                                        main_litedramcore_choose_cmd_grant <= 3'd5;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[6]) begin
-                                            litedramcore_choose_cmd_grant <= 3'd6;
+                                        if (main_litedramcore_choose_cmd_request[6]) begin
+                                            main_litedramcore_choose_cmd_grant <= 3'd6;
                                         end
                                     end
                                 end
@@ -13234,29 +13649,29 @@ always @(posedge sys_clk) begin
             end
         endcase
     end
-    if (litedramcore_choose_req_ce) begin
-        case (litedramcore_choose_req_grant)
+    if (main_litedramcore_choose_req_ce) begin
+        case (main_litedramcore_choose_req_grant)
             1'd0: begin
-                if (litedramcore_choose_req_request[1]) begin
-                    litedramcore_choose_req_grant <= 1'd1;
+                if (main_litedramcore_choose_req_request[1]) begin
+                    main_litedramcore_choose_req_grant <= 1'd1;
                 end else begin
-                    if (litedramcore_choose_req_request[2]) begin
-                        litedramcore_choose_req_grant <= 2'd2;
+                    if (main_litedramcore_choose_req_request[2]) begin
+                        main_litedramcore_choose_req_grant <= 2'd2;
                     end else begin
-                        if (litedramcore_choose_req_request[3]) begin
-                            litedramcore_choose_req_grant <= 2'd3;
+                        if (main_litedramcore_choose_req_request[3]) begin
+                            main_litedramcore_choose_req_grant <= 2'd3;
                         end else begin
-                            if (litedramcore_choose_req_request[4]) begin
-                                litedramcore_choose_req_grant <= 3'd4;
+                            if (main_litedramcore_choose_req_request[4]) begin
+                                main_litedramcore_choose_req_grant <= 3'd4;
                             end else begin
-                                if (litedramcore_choose_req_request[5]) begin
-                                    litedramcore_choose_req_grant <= 3'd5;
+                                if (main_litedramcore_choose_req_request[5]) begin
+                                    main_litedramcore_choose_req_grant <= 3'd5;
                                 end else begin
-                                    if (litedramcore_choose_req_request[6]) begin
-                                        litedramcore_choose_req_grant <= 3'd6;
+                                    if (main_litedramcore_choose_req_request[6]) begin
+                                        main_litedramcore_choose_req_grant <= 3'd6;
                                     end else begin
-                                        if (litedramcore_choose_req_request[7]) begin
-                                            litedramcore_choose_req_grant <= 3'd7;
+                                        if (main_litedramcore_choose_req_request[7]) begin
+                                            main_litedramcore_choose_req_grant <= 3'd7;
                                         end
                                     end
                                 end
@@ -13266,26 +13681,26 @@ always @(posedge sys_clk) begin
                 end
             end
             1'd1: begin
-                if (litedramcore_choose_req_request[2]) begin
-                    litedramcore_choose_req_grant <= 2'd2;
+                if (main_litedramcore_choose_req_request[2]) begin
+                    main_litedramcore_choose_req_grant <= 2'd2;
                 end else begin
-                    if (litedramcore_choose_req_request[3]) begin
-                        litedramcore_choose_req_grant <= 2'd3;
+                    if (main_litedramcore_choose_req_request[3]) begin
+                        main_litedramcore_choose_req_grant <= 2'd3;
                     end else begin
-                        if (litedramcore_choose_req_request[4]) begin
-                            litedramcore_choose_req_grant <= 3'd4;
+                        if (main_litedramcore_choose_req_request[4]) begin
+                            main_litedramcore_choose_req_grant <= 3'd4;
                         end else begin
-                            if (litedramcore_choose_req_request[5]) begin
-                                litedramcore_choose_req_grant <= 3'd5;
+                            if (main_litedramcore_choose_req_request[5]) begin
+                                main_litedramcore_choose_req_grant <= 3'd5;
                             end else begin
-                                if (litedramcore_choose_req_request[6]) begin
-                                    litedramcore_choose_req_grant <= 3'd6;
+                                if (main_litedramcore_choose_req_request[6]) begin
+                                    main_litedramcore_choose_req_grant <= 3'd6;
                                 end else begin
-                                    if (litedramcore_choose_req_request[7]) begin
-                                        litedramcore_choose_req_grant <= 3'd7;
+                                    if (main_litedramcore_choose_req_request[7]) begin
+                                        main_litedramcore_choose_req_grant <= 3'd7;
                                     end else begin
-                                        if (litedramcore_choose_req_request[0]) begin
-                                            litedramcore_choose_req_grant <= 1'd0;
+                                        if (main_litedramcore_choose_req_request[0]) begin
+                                            main_litedramcore_choose_req_grant <= 1'd0;
                                         end
                                     end
                                 end
@@ -13295,26 +13710,26 @@ always @(posedge sys_clk) begin
                 end
             end
             2'd2: begin
-                if (litedramcore_choose_req_request[3]) begin
-                    litedramcore_choose_req_grant <= 2'd3;
+                if (main_litedramcore_choose_req_request[3]) begin
+                    main_litedramcore_choose_req_grant <= 2'd3;
                 end else begin
-                    if (litedramcore_choose_req_request[4]) begin
-                        litedramcore_choose_req_grant <= 3'd4;
+                    if (main_litedramcore_choose_req_request[4]) begin
+                        main_litedramcore_choose_req_grant <= 3'd4;
                     end else begin
-                        if (litedramcore_choose_req_request[5]) begin
-                            litedramcore_choose_req_grant <= 3'd5;
+                        if (main_litedramcore_choose_req_request[5]) begin
+                            main_litedramcore_choose_req_grant <= 3'd5;
                         end else begin
-                            if (litedramcore_choose_req_request[6]) begin
-                                litedramcore_choose_req_grant <= 3'd6;
+                            if (main_litedramcore_choose_req_request[6]) begin
+                                main_litedramcore_choose_req_grant <= 3'd6;
                             end else begin
-                                if (litedramcore_choose_req_request[7]) begin
-                                    litedramcore_choose_req_grant <= 3'd7;
+                                if (main_litedramcore_choose_req_request[7]) begin
+                                    main_litedramcore_choose_req_grant <= 3'd7;
                                 end else begin
-                                    if (litedramcore_choose_req_request[0]) begin
-                                        litedramcore_choose_req_grant <= 1'd0;
+                                    if (main_litedramcore_choose_req_request[0]) begin
+                                        main_litedramcore_choose_req_grant <= 1'd0;
                                     end else begin
-                                        if (litedramcore_choose_req_request[1]) begin
-                                            litedramcore_choose_req_grant <= 1'd1;
+                                        if (main_litedramcore_choose_req_request[1]) begin
+                                            main_litedramcore_choose_req_grant <= 1'd1;
                                         end
                                     end
                                 end
@@ -13324,26 +13739,26 @@ always @(posedge sys_clk) begin
                 end
             end
             2'd3: begin
-                if (litedramcore_choose_req_request[4]) begin
-                    litedramcore_choose_req_grant <= 3'd4;
+                if (main_litedramcore_choose_req_request[4]) begin
+                    main_litedramcore_choose_req_grant <= 3'd4;
                 end else begin
-                    if (litedramcore_choose_req_request[5]) begin
-                        litedramcore_choose_req_grant <= 3'd5;
+                    if (main_litedramcore_choose_req_request[5]) begin
+                        main_litedramcore_choose_req_grant <= 3'd5;
                     end else begin
-                        if (litedramcore_choose_req_request[6]) begin
-                            litedramcore_choose_req_grant <= 3'd6;
+                        if (main_litedramcore_choose_req_request[6]) begin
+                            main_litedramcore_choose_req_grant <= 3'd6;
                         end else begin
-                            if (litedramcore_choose_req_request[7]) begin
-                                litedramcore_choose_req_grant <= 3'd7;
+                            if (main_litedramcore_choose_req_request[7]) begin
+                                main_litedramcore_choose_req_grant <= 3'd7;
                             end else begin
-                                if (litedramcore_choose_req_request[0]) begin
-                                    litedramcore_choose_req_grant <= 1'd0;
+                                if (main_litedramcore_choose_req_request[0]) begin
+                                    main_litedramcore_choose_req_grant <= 1'd0;
                                 end else begin
-                                    if (litedramcore_choose_req_request[1]) begin
-                                        litedramcore_choose_req_grant <= 1'd1;
+                                    if (main_litedramcore_choose_req_request[1]) begin
+                                        main_litedramcore_choose_req_grant <= 1'd1;
                                     end else begin
-                                        if (litedramcore_choose_req_request[2]) begin
-                                            litedramcore_choose_req_grant <= 2'd2;
+                                        if (main_litedramcore_choose_req_request[2]) begin
+                                            main_litedramcore_choose_req_grant <= 2'd2;
                                         end
                                     end
                                 end
@@ -13353,26 +13768,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd4: begin
-                if (litedramcore_choose_req_request[5]) begin
-                    litedramcore_choose_req_grant <= 3'd5;
+                if (main_litedramcore_choose_req_request[5]) begin
+                    main_litedramcore_choose_req_grant <= 3'd5;
                 end else begin
-                    if (litedramcore_choose_req_request[6]) begin
-                        litedramcore_choose_req_grant <= 3'd6;
+                    if (main_litedramcore_choose_req_request[6]) begin
+                        main_litedramcore_choose_req_grant <= 3'd6;
                     end else begin
-                        if (litedramcore_choose_req_request[7]) begin
-                            litedramcore_choose_req_grant <= 3'd7;
+                        if (main_litedramcore_choose_req_request[7]) begin
+                            main_litedramcore_choose_req_grant <= 3'd7;
                         end else begin
-                            if (litedramcore_choose_req_request[0]) begin
-                                litedramcore_choose_req_grant <= 1'd0;
+                            if (main_litedramcore_choose_req_request[0]) begin
+                                main_litedramcore_choose_req_grant <= 1'd0;
                             end else begin
-                                if (litedramcore_choose_req_request[1]) begin
-                                    litedramcore_choose_req_grant <= 1'd1;
+                                if (main_litedramcore_choose_req_request[1]) begin
+                                    main_litedramcore_choose_req_grant <= 1'd1;
                                 end else begin
-                                    if (litedramcore_choose_req_request[2]) begin
-                                        litedramcore_choose_req_grant <= 2'd2;
+                                    if (main_litedramcore_choose_req_request[2]) begin
+                                        main_litedramcore_choose_req_grant <= 2'd2;
                                     end else begin
-                                        if (litedramcore_choose_req_request[3]) begin
-                                            litedramcore_choose_req_grant <= 2'd3;
+                                        if (main_litedramcore_choose_req_request[3]) begin
+                                            main_litedramcore_choose_req_grant <= 2'd3;
                                         end
                                     end
                                 end
@@ -13382,26 +13797,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd5: begin
-                if (litedramcore_choose_req_request[6]) begin
-                    litedramcore_choose_req_grant <= 3'd6;
+                if (main_litedramcore_choose_req_request[6]) begin
+                    main_litedramcore_choose_req_grant <= 3'd6;
                 end else begin
-                    if (litedramcore_choose_req_request[7]) begin
-                        litedramcore_choose_req_grant <= 3'd7;
+                    if (main_litedramcore_choose_req_request[7]) begin
+                        main_litedramcore_choose_req_grant <= 3'd7;
                     end else begin
-                        if (litedramcore_choose_req_request[0]) begin
-                            litedramcore_choose_req_grant <= 1'd0;
+                        if (main_litedramcore_choose_req_request[0]) begin
+                            main_litedramcore_choose_req_grant <= 1'd0;
                         end else begin
-                            if (litedramcore_choose_req_request[1]) begin
-                                litedramcore_choose_req_grant <= 1'd1;
+                            if (main_litedramcore_choose_req_request[1]) begin
+                                main_litedramcore_choose_req_grant <= 1'd1;
                             end else begin
-                                if (litedramcore_choose_req_request[2]) begin
-                                    litedramcore_choose_req_grant <= 2'd2;
+                                if (main_litedramcore_choose_req_request[2]) begin
+                                    main_litedramcore_choose_req_grant <= 2'd2;
                                 end else begin
-                                    if (litedramcore_choose_req_request[3]) begin
-                                        litedramcore_choose_req_grant <= 2'd3;
+                                    if (main_litedramcore_choose_req_request[3]) begin
+                                        main_litedramcore_choose_req_grant <= 2'd3;
                                     end else begin
-                                        if (litedramcore_choose_req_request[4]) begin
-                                            litedramcore_choose_req_grant <= 3'd4;
+                                        if (main_litedramcore_choose_req_request[4]) begin
+                                            main_litedramcore_choose_req_grant <= 3'd4;
                                         end
                                     end
                                 end
@@ -13411,26 +13826,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd6: begin
-                if (litedramcore_choose_req_request[7]) begin
-                    litedramcore_choose_req_grant <= 3'd7;
+                if (main_litedramcore_choose_req_request[7]) begin
+                    main_litedramcore_choose_req_grant <= 3'd7;
                 end else begin
-                    if (litedramcore_choose_req_request[0]) begin
-                        litedramcore_choose_req_grant <= 1'd0;
+                    if (main_litedramcore_choose_req_request[0]) begin
+                        main_litedramcore_choose_req_grant <= 1'd0;
                     end else begin
-                        if (litedramcore_choose_req_request[1]) begin
-                            litedramcore_choose_req_grant <= 1'd1;
+                        if (main_litedramcore_choose_req_request[1]) begin
+                            main_litedramcore_choose_req_grant <= 1'd1;
                         end else begin
-                            if (litedramcore_choose_req_request[2]) begin
-                                litedramcore_choose_req_grant <= 2'd2;
+                            if (main_litedramcore_choose_req_request[2]) begin
+                                main_litedramcore_choose_req_grant <= 2'd2;
                             end else begin
-                                if (litedramcore_choose_req_request[3]) begin
-                                    litedramcore_choose_req_grant <= 2'd3;
+                                if (main_litedramcore_choose_req_request[3]) begin
+                                    main_litedramcore_choose_req_grant <= 2'd3;
                                 end else begin
-                                    if (litedramcore_choose_req_request[4]) begin
-                                        litedramcore_choose_req_grant <= 3'd4;
+                                    if (main_litedramcore_choose_req_request[4]) begin
+                                        main_litedramcore_choose_req_grant <= 3'd4;
                                     end else begin
-                                        if (litedramcore_choose_req_request[5]) begin
-                                            litedramcore_choose_req_grant <= 3'd5;
+                                        if (main_litedramcore_choose_req_request[5]) begin
+                                            main_litedramcore_choose_req_grant <= 3'd5;
                                         end
                                     end
                                 end
@@ -13440,26 +13855,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd7: begin
-                if (litedramcore_choose_req_request[0]) begin
-                    litedramcore_choose_req_grant <= 1'd0;
+                if (main_litedramcore_choose_req_request[0]) begin
+                    main_litedramcore_choose_req_grant <= 1'd0;
                 end else begin
-                    if (litedramcore_choose_req_request[1]) begin
-                        litedramcore_choose_req_grant <= 1'd1;
+                    if (main_litedramcore_choose_req_request[1]) begin
+                        main_litedramcore_choose_req_grant <= 1'd1;
                     end else begin
-                        if (litedramcore_choose_req_request[2]) begin
-                            litedramcore_choose_req_grant <= 2'd2;
+                        if (main_litedramcore_choose_req_request[2]) begin
+                            main_litedramcore_choose_req_grant <= 2'd2;
                         end else begin
-                            if (litedramcore_choose_req_request[3]) begin
-                                litedramcore_choose_req_grant <= 2'd3;
+                            if (main_litedramcore_choose_req_request[3]) begin
+                                main_litedramcore_choose_req_grant <= 2'd3;
                             end else begin
-                                if (litedramcore_choose_req_request[4]) begin
-                                    litedramcore_choose_req_grant <= 3'd4;
+                                if (main_litedramcore_choose_req_request[4]) begin
+                                    main_litedramcore_choose_req_grant <= 3'd4;
                                 end else begin
-                                    if (litedramcore_choose_req_request[5]) begin
-                                        litedramcore_choose_req_grant <= 3'd5;
+                                    if (main_litedramcore_choose_req_request[5]) begin
+                                        main_litedramcore_choose_req_grant <= 3'd5;
                                     end else begin
-                                        if (litedramcore_choose_req_request[6]) begin
-                                            litedramcore_choose_req_grant <= 3'd6;
+                                        if (main_litedramcore_choose_req_request[6]) begin
+                                            main_litedramcore_choose_req_grant <= 3'd6;
                                         end
                                     end
                                 end
@@ -13470,644 +13885,644 @@ always @(posedge sys_clk) begin
             end
         endcase
     end
-    litedramcore_dfi_p0_cs_n <= 1'd0;
-    litedramcore_dfi_p0_bank <= array_muxed0;
-    litedramcore_dfi_p0_address <= array_muxed1;
-    litedramcore_dfi_p0_cas_n <= (~array_muxed2);
-    litedramcore_dfi_p0_ras_n <= (~array_muxed3);
-    litedramcore_dfi_p0_we_n <= (~array_muxed4);
-    litedramcore_dfi_p0_rddata_en <= array_muxed5;
-    litedramcore_dfi_p0_wrdata_en <= array_muxed6;
-    litedramcore_dfi_p1_cs_n <= 1'd0;
-    litedramcore_dfi_p1_bank <= array_muxed7;
-    litedramcore_dfi_p1_address <= array_muxed8;
-    litedramcore_dfi_p1_cas_n <= (~array_muxed9);
-    litedramcore_dfi_p1_ras_n <= (~array_muxed10);
-    litedramcore_dfi_p1_we_n <= (~array_muxed11);
-    litedramcore_dfi_p1_rddata_en <= array_muxed12;
-    litedramcore_dfi_p1_wrdata_en <= array_muxed13;
-    litedramcore_dfi_p2_cs_n <= 1'd0;
-    litedramcore_dfi_p2_bank <= array_muxed14;
-    litedramcore_dfi_p2_address <= array_muxed15;
-    litedramcore_dfi_p2_cas_n <= (~array_muxed16);
-    litedramcore_dfi_p2_ras_n <= (~array_muxed17);
-    litedramcore_dfi_p2_we_n <= (~array_muxed18);
-    litedramcore_dfi_p2_rddata_en <= array_muxed19;
-    litedramcore_dfi_p2_wrdata_en <= array_muxed20;
-    litedramcore_dfi_p3_cs_n <= 1'd0;
-    litedramcore_dfi_p3_bank <= array_muxed21;
-    litedramcore_dfi_p3_address <= array_muxed22;
-    litedramcore_dfi_p3_cas_n <= (~array_muxed23);
-    litedramcore_dfi_p3_ras_n <= (~array_muxed24);
-    litedramcore_dfi_p3_we_n <= (~array_muxed25);
-    litedramcore_dfi_p3_rddata_en <= array_muxed26;
-    litedramcore_dfi_p3_wrdata_en <= array_muxed27;
-    if (litedramcore_trrdcon_valid) begin
-        litedramcore_trrdcon_count <= 1'd1;
+    main_litedramcore_dfi_p0_cs_n <= 1'd0;
+    main_litedramcore_dfi_p0_bank <= builder_self0;
+    main_litedramcore_dfi_p0_address <= builder_self1;
+    main_litedramcore_dfi_p0_cas_n <= (~builder_self2);
+    main_litedramcore_dfi_p0_ras_n <= (~builder_self3);
+    main_litedramcore_dfi_p0_we_n <= (~builder_self4);
+    main_litedramcore_dfi_p0_rddata_en <= builder_self5;
+    main_litedramcore_dfi_p0_wrdata_en <= builder_self6;
+    main_litedramcore_dfi_p1_cs_n <= 1'd0;
+    main_litedramcore_dfi_p1_bank <= builder_self7;
+    main_litedramcore_dfi_p1_address <= builder_self8;
+    main_litedramcore_dfi_p1_cas_n <= (~builder_self9);
+    main_litedramcore_dfi_p1_ras_n <= (~builder_self10);
+    main_litedramcore_dfi_p1_we_n <= (~builder_self11);
+    main_litedramcore_dfi_p1_rddata_en <= builder_self12;
+    main_litedramcore_dfi_p1_wrdata_en <= builder_self13;
+    main_litedramcore_dfi_p2_cs_n <= 1'd0;
+    main_litedramcore_dfi_p2_bank <= builder_self14;
+    main_litedramcore_dfi_p2_address <= builder_self15;
+    main_litedramcore_dfi_p2_cas_n <= (~builder_self16);
+    main_litedramcore_dfi_p2_ras_n <= (~builder_self17);
+    main_litedramcore_dfi_p2_we_n <= (~builder_self18);
+    main_litedramcore_dfi_p2_rddata_en <= builder_self19;
+    main_litedramcore_dfi_p2_wrdata_en <= builder_self20;
+    main_litedramcore_dfi_p3_cs_n <= 1'd0;
+    main_litedramcore_dfi_p3_bank <= builder_self21;
+    main_litedramcore_dfi_p3_address <= builder_self22;
+    main_litedramcore_dfi_p3_cas_n <= (~builder_self23);
+    main_litedramcore_dfi_p3_ras_n <= (~builder_self24);
+    main_litedramcore_dfi_p3_we_n <= (~builder_self25);
+    main_litedramcore_dfi_p3_rddata_en <= builder_self26;
+    main_litedramcore_dfi_p3_wrdata_en <= builder_self27;
+    if (main_litedramcore_trrdcon_valid) begin
+        main_litedramcore_trrdcon_count <= 1'd1;
         if (1'd0) begin
-            litedramcore_trrdcon_ready <= 1'd1;
+            main_litedramcore_trrdcon_ready <= 1'd1;
         end else begin
-            litedramcore_trrdcon_ready <= 1'd0;
+            main_litedramcore_trrdcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_trrdcon_ready)) begin
-            litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
-            if ((litedramcore_trrdcon_count == 1'd1)) begin
-                litedramcore_trrdcon_ready <= 1'd1;
+        if ((~main_litedramcore_trrdcon_ready)) begin
+            main_litedramcore_trrdcon_count <= (main_litedramcore_trrdcon_count - 1'd1);
+            if ((main_litedramcore_trrdcon_count == 1'd1)) begin
+                main_litedramcore_trrdcon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
-    if ((litedramcore_tfawcon_count < 3'd4)) begin
-        if ((litedramcore_tfawcon_count == 2'd3)) begin
-            litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
+    main_litedramcore_tfawcon_window <= {main_litedramcore_tfawcon_window, main_litedramcore_tfawcon_valid};
+    if ((main_litedramcore_tfawcon_count < 3'd4)) begin
+        if ((main_litedramcore_tfawcon_count == 2'd3)) begin
+            main_litedramcore_tfawcon_ready <= (~main_litedramcore_tfawcon_valid);
         end else begin
-            litedramcore_tfawcon_ready <= 1'd1;
+            main_litedramcore_tfawcon_ready <= 1'd1;
         end
     end
-    if (litedramcore_tccdcon_valid) begin
-        litedramcore_tccdcon_count <= 1'd0;
+    if (main_litedramcore_tccdcon_valid) begin
+        main_litedramcore_tccdcon_count <= 1'd0;
         if (1'd1) begin
-            litedramcore_tccdcon_ready <= 1'd1;
+            main_litedramcore_tccdcon_ready <= 1'd1;
         end else begin
-            litedramcore_tccdcon_ready <= 1'd0;
+            main_litedramcore_tccdcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_tccdcon_ready)) begin
-            litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
-            if ((litedramcore_tccdcon_count == 1'd1)) begin
-                litedramcore_tccdcon_ready <= 1'd1;
+        if ((~main_litedramcore_tccdcon_ready)) begin
+            main_litedramcore_tccdcon_count <= (main_litedramcore_tccdcon_count - 1'd1);
+            if ((main_litedramcore_tccdcon_count == 1'd1)) begin
+                main_litedramcore_tccdcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_twtrcon_valid) begin
-        litedramcore_twtrcon_count <= 3'd4;
+    if (main_litedramcore_twtrcon_valid) begin
+        main_litedramcore_twtrcon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_twtrcon_ready <= 1'd1;
+            main_litedramcore_twtrcon_ready <= 1'd1;
         end else begin
-            litedramcore_twtrcon_ready <= 1'd0;
+            main_litedramcore_twtrcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_twtrcon_ready)) begin
-            litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
-            if ((litedramcore_twtrcon_count == 1'd1)) begin
-                litedramcore_twtrcon_ready <= 1'd1;
-            end
-        end
-    end
-    litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
-    litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
-    litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
-    litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
-    litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
-    litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
-    litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
-    litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
-    litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
-    litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
-    litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
-    litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
-    litedramcore_state <= litedramcore_next_state;
-    if (litedramcore_dat_w_next_value_ce0) begin
-        litedramcore_dat_w <= litedramcore_dat_w_next_value0;
-    end
-    if (litedramcore_adr_next_value_ce1) begin
-        litedramcore_adr <= litedramcore_adr_next_value1;
-    end
-    if (litedramcore_we_next_value_ce2) begin
-        litedramcore_we <= litedramcore_we_next_value2;
-    end
-    interface0_bank_bus_dat_r <= 1'd0;
-    if (csrbank0_sel) begin
-        case (interface0_bank_bus_adr[8:0])
+        if ((~main_litedramcore_twtrcon_ready)) begin
+            main_litedramcore_twtrcon_count <= (main_litedramcore_twtrcon_count - 1'd1);
+            if ((main_litedramcore_twtrcon_count == 1'd1)) begin
+                main_litedramcore_twtrcon_ready <= 1'd1;
+            end
+        end
+    end
+    builder_multiplexer_state <= builder_multiplexer_next_state;
+    builder_new_master_wdata_ready0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_wdata_ready)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_wdata_ready)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_wdata_ready)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_wdata_ready)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_wdata_ready)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_wdata_ready)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_wdata_ready)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_wdata_ready));
+    builder_new_master_wdata_ready1 <= builder_new_master_wdata_ready0;
+    builder_new_master_rdata_valid0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_rdata_valid)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_rdata_valid)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_rdata_valid)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_rdata_valid)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_rdata_valid)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_rdata_valid)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_rdata_valid)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_rdata_valid));
+    builder_new_master_rdata_valid1 <= builder_new_master_rdata_valid0;
+    builder_new_master_rdata_valid2 <= builder_new_master_rdata_valid1;
+    builder_new_master_rdata_valid3 <= builder_new_master_rdata_valid2;
+    builder_new_master_rdata_valid4 <= builder_new_master_rdata_valid3;
+    builder_new_master_rdata_valid5 <= builder_new_master_rdata_valid4;
+    builder_new_master_rdata_valid6 <= builder_new_master_rdata_valid5;
+    builder_new_master_rdata_valid7 <= builder_new_master_rdata_valid6;
+    builder_new_master_rdata_valid8 <= builder_new_master_rdata_valid7;
+    builder_state <= builder_next_state;
+    if (builder_interface1_dat_w_next_value_ce0) begin
+        builder_interface1_dat_w <= builder_interface1_dat_w_next_value0;
+    end
+    if (builder_interface1_adr_next_value_ce1) begin
+        builder_interface1_adr <= builder_interface1_adr_next_value1;
+    end
+    if (builder_interface1_we_next_value_ce2) begin
+        builder_interface1_we <= builder_interface1_we_next_value2;
+    end
+    builder_interface0_bank_bus_dat_r <= 1'd0;
+    if (builder_csrbank0_sel) begin
+        case (builder_interface0_bank_bus_adr[8:0])
             1'd0: begin
-                interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
+                builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_done0_w;
             end
             1'd1: begin
-                interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
+                builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_error0_w;
             end
         endcase
     end
-    if (csrbank0_init_done0_re) begin
-        init_done_storage <= csrbank0_init_done0_r;
+    if (builder_csrbank0_init_done0_re) begin
+        main_init_done_storage <= builder_csrbank0_init_done0_r;
     end
-    init_done_re <= csrbank0_init_done0_re;
-    if (csrbank0_init_error0_re) begin
-        init_error_storage <= csrbank0_init_error0_r;
+    main_init_done_re <= builder_csrbank0_init_done0_re;
+    if (builder_csrbank0_init_error0_re) begin
+        main_init_error_storage <= builder_csrbank0_init_error0_r;
     end
-    init_error_re <= csrbank0_init_error0_re;
-    interface1_bank_bus_dat_r <= 1'd0;
-    if (csrbank1_sel) begin
-        case (interface1_bank_bus_adr[8:0])
+    main_init_error_re <= builder_csrbank0_init_error0_re;
+    builder_interface1_bank_bus_dat_r <= 1'd0;
+    if (builder_csrbank1_sel) begin
+        case (builder_interface1_bank_bus_adr[8:0])
             1'd0: begin
-                interface1_bank_bus_dat_r <= csrbank1_rst0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_rst0_w;
             end
             1'd1: begin
-                interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_dly_sel0_w;
             end
             2'd2: begin
-                interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_half_sys8x_taps0_w;
             end
             2'd3: begin
-                interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_wlevel_en0_w;
             end
             3'd4: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wlevel_strobe_w;
             end
             3'd5: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_rst_w;
             end
             3'd6: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_inc_w;
             end
             3'd7: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_rst_w;
             end
             4'd8: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_w;
             end
             4'd9: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_rst_w;
             end
             4'd10: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_w;
             end
             4'd11: begin
-                interface1_bank_bus_dat_r <= csrbank1_rdphase0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_rdphase0_w;
             end
             4'd12: begin
-                interface1_bank_bus_dat_r <= csrbank1_wrphase0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_wrphase0_w;
             end
         endcase
     end
-    if (csrbank1_rst0_re) begin
-        a7ddrphy_rst_storage <= csrbank1_rst0_r;
+    if (builder_csrbank1_rst0_re) begin
+        main_a7ddrphy_rst_storage <= builder_csrbank1_rst0_r;
     end
-    a7ddrphy_rst_re <= csrbank1_rst0_re;
-    if (csrbank1_dly_sel0_re) begin
-        a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r;
+    main_a7ddrphy_rst_re <= builder_csrbank1_rst0_re;
+    if (builder_csrbank1_dly_sel0_re) begin
+        main_a7ddrphy_dly_sel_storage[1:0] <= builder_csrbank1_dly_sel0_r;
     end
-    a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
-    if (csrbank1_half_sys8x_taps0_re) begin
-        a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r;
+    main_a7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re;
+    if (builder_csrbank1_half_sys8x_taps0_re) begin
+        main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r;
     end
-    a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re;
-    if (csrbank1_wlevel_en0_re) begin
-        a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r;
+    main_a7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re;
+    if (builder_csrbank1_wlevel_en0_re) begin
+        main_a7ddrphy_wlevel_en_storage <= builder_csrbank1_wlevel_en0_r;
     end
-    a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re;
-    if (csrbank1_rdphase0_re) begin
-        a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r;
+    main_a7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re;
+    if (builder_csrbank1_rdphase0_re) begin
+        main_a7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r;
     end
-    a7ddrphy_rdphase_re <= csrbank1_rdphase0_re;
-    if (csrbank1_wrphase0_re) begin
-        a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r;
+    main_a7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re;
+    if (builder_csrbank1_wrphase0_re) begin
+        main_a7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r;
     end
-    a7ddrphy_wrphase_re <= csrbank1_wrphase0_re;
-    interface2_bank_bus_dat_r <= 1'd0;
-    if (csrbank2_sel) begin
-        case (interface2_bank_bus_adr[8:0])
+    main_a7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re;
+    builder_interface2_bank_bus_dat_r <= 1'd0;
+    if (builder_csrbank2_sel) begin
+        case (builder_interface2_bank_bus_adr[8:0])
             1'd0: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_control0_w;
             end
             1'd1: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_command0_w;
             end
             2'd2: begin
-                interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
+                builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w;
             end
             2'd3: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w;
             end
             3'd4: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w;
             end
             3'd5: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w;
             end
             3'd6: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata_w;
             end
             3'd7: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w;
             end
             4'd8: begin
-                interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
+                builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w;
             end
             4'd9: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w;
             end
             4'd10: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w;
             end
             4'd11: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w;
             end
             4'd12: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata_w;
             end
             4'd13: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w;
             end
             4'd14: begin
-                interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
+                builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w;
             end
             4'd15: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w;
             end
             5'd16: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w;
             end
             5'd17: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w;
             end
             5'd18: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata_w;
             end
             5'd19: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w;
             end
             5'd20: begin
-                interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
+                builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w;
             end
             5'd21: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w;
             end
             5'd22: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w;
             end
             5'd23: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w;
             end
             5'd24: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata_w;
             end
         endcase
     end
-    if (csrbank2_dfii_control0_re) begin
-        litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
+    if (builder_csrbank2_dfii_control0_re) begin
+        main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r;
     end
-    litedramcore_re <= csrbank2_dfii_control0_re;
-    if (csrbank2_dfii_pi0_command0_re) begin
-        litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
+    main_litedramcore_re <= builder_csrbank2_dfii_control0_re;
+    if (builder_csrbank2_dfii_pi0_command0_re) begin
+        main_litedramcore_phaseinjector0_command_storage[7:0] <= builder_csrbank2_dfii_pi0_command0_r;
     end
-    litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
-    if (csrbank2_dfii_pi0_address0_re) begin
-        litedramcore_phaseinjector0_address_storage[13:0] <= csrbank2_dfii_pi0_address0_r;
+    main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re;
+    if (builder_csrbank2_dfii_pi0_address0_re) begin
+        main_litedramcore_phaseinjector0_address_storage[13:0] <= builder_csrbank2_dfii_pi0_address0_r;
     end
-    litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
-    if (csrbank2_dfii_pi0_baddress0_re) begin
-        litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
+    main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re;
+    if (builder_csrbank2_dfii_pi0_baddress0_re) begin
+        main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r;
     end
-    litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
-    if (csrbank2_dfii_pi0_wrdata0_re) begin
-        litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
+    main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re;
+    if (builder_csrbank2_dfii_pi0_wrdata0_re) begin
+        main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r;
     end
-    litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
-    litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re;
-    if (csrbank2_dfii_pi1_command0_re) begin
-        litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
+    main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re;
+    main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re;
+    if (builder_csrbank2_dfii_pi1_command0_re) begin
+        main_litedramcore_phaseinjector1_command_storage[7:0] <= builder_csrbank2_dfii_pi1_command0_r;
     end
-    litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
-    if (csrbank2_dfii_pi1_address0_re) begin
-        litedramcore_phaseinjector1_address_storage[13:0] <= csrbank2_dfii_pi1_address0_r;
+    main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re;
+    if (builder_csrbank2_dfii_pi1_address0_re) begin
+        main_litedramcore_phaseinjector1_address_storage[13:0] <= builder_csrbank2_dfii_pi1_address0_r;
     end
-    litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
-    if (csrbank2_dfii_pi1_baddress0_re) begin
-        litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
+    main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re;
+    if (builder_csrbank2_dfii_pi1_baddress0_re) begin
+        main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r;
     end
-    litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
-    if (csrbank2_dfii_pi1_wrdata0_re) begin
-        litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
+    main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re;
+    if (builder_csrbank2_dfii_pi1_wrdata0_re) begin
+        main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r;
     end
-    litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
-    litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re;
-    if (csrbank2_dfii_pi2_command0_re) begin
-        litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
+    main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re;
+    main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re;
+    if (builder_csrbank2_dfii_pi2_command0_re) begin
+        main_litedramcore_phaseinjector2_command_storage[7:0] <= builder_csrbank2_dfii_pi2_command0_r;
     end
-    litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
-    if (csrbank2_dfii_pi2_address0_re) begin
-        litedramcore_phaseinjector2_address_storage[13:0] <= csrbank2_dfii_pi2_address0_r;
+    main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re;
+    if (builder_csrbank2_dfii_pi2_address0_re) begin
+        main_litedramcore_phaseinjector2_address_storage[13:0] <= builder_csrbank2_dfii_pi2_address0_r;
     end
-    litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
-    if (csrbank2_dfii_pi2_baddress0_re) begin
-        litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
+    main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re;
+    if (builder_csrbank2_dfii_pi2_baddress0_re) begin
+        main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r;
     end
-    litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
-    if (csrbank2_dfii_pi2_wrdata0_re) begin
-        litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
+    main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re;
+    if (builder_csrbank2_dfii_pi2_wrdata0_re) begin
+        main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r;
     end
-    litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
-    litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re;
-    if (csrbank2_dfii_pi3_command0_re) begin
-        litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
+    main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re;
+    main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re;
+    if (builder_csrbank2_dfii_pi3_command0_re) begin
+        main_litedramcore_phaseinjector3_command_storage[7:0] <= builder_csrbank2_dfii_pi3_command0_r;
     end
-    litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
-    if (csrbank2_dfii_pi3_address0_re) begin
-        litedramcore_phaseinjector3_address_storage[13:0] <= csrbank2_dfii_pi3_address0_r;
+    main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re;
+    if (builder_csrbank2_dfii_pi3_address0_re) begin
+        main_litedramcore_phaseinjector3_address_storage[13:0] <= builder_csrbank2_dfii_pi3_address0_r;
     end
-    litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
-    if (csrbank2_dfii_pi3_baddress0_re) begin
-        litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
+    main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re;
+    if (builder_csrbank2_dfii_pi3_baddress0_re) begin
+        main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r;
     end
-    litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
-    if (csrbank2_dfii_pi3_wrdata0_re) begin
-        litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
+    main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re;
+    if (builder_csrbank2_dfii_pi3_wrdata0_re) begin
+        main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r;
     end
-    litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
-    litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re;
+    main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re;
+    main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re;
     if (sys_rst) begin
-        a7ddrphy_rst_storage <= 1'd0;
-        a7ddrphy_rst_re <= 1'd0;
-        a7ddrphy_dly_sel_storage <= 2'd0;
-        a7ddrphy_dly_sel_re <= 1'd0;
-        a7ddrphy_half_sys8x_taps_storage <= 5'd8;
-        a7ddrphy_half_sys8x_taps_re <= 1'd0;
-        a7ddrphy_wlevel_en_storage <= 1'd0;
-        a7ddrphy_wlevel_en_re <= 1'd0;
-        a7ddrphy_rdphase_storage <= 2'd2;
-        a7ddrphy_rdphase_re <= 1'd0;
-        a7ddrphy_wrphase_storage <= 2'd3;
-        a7ddrphy_wrphase_re <= 1'd0;
-        a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
-        a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
-        a7ddrphy_dqspattern_o1 <= 8'd0;
-        a7ddrphy_bitslip0_value0 <= 3'd7;
-        a7ddrphy_bitslip1_value0 <= 3'd7;
-        a7ddrphy_bitslip0_value1 <= 3'd7;
-        a7ddrphy_bitslip1_value1 <= 3'd7;
-        a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
-        a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
-        a7ddrphy_bitslip0_value2 <= 3'd7;
-        a7ddrphy_bitslip0_value3 <= 3'd7;
-        a7ddrphy_bitslip1_value2 <= 3'd7;
-        a7ddrphy_bitslip1_value3 <= 3'd7;
-        a7ddrphy_bitslip2_value0 <= 3'd7;
-        a7ddrphy_bitslip2_value1 <= 3'd7;
-        a7ddrphy_bitslip3_value0 <= 3'd7;
-        a7ddrphy_bitslip3_value1 <= 3'd7;
-        a7ddrphy_bitslip4_value0 <= 3'd7;
-        a7ddrphy_bitslip4_value1 <= 3'd7;
-        a7ddrphy_bitslip5_value0 <= 3'd7;
-        a7ddrphy_bitslip5_value1 <= 3'd7;
-        a7ddrphy_bitslip6_value0 <= 3'd7;
-        a7ddrphy_bitslip6_value1 <= 3'd7;
-        a7ddrphy_bitslip7_value0 <= 3'd7;
-        a7ddrphy_bitslip7_value1 <= 3'd7;
-        a7ddrphy_bitslip8_value0 <= 3'd7;
-        a7ddrphy_bitslip8_value1 <= 3'd7;
-        a7ddrphy_bitslip9_value0 <= 3'd7;
-        a7ddrphy_bitslip9_value1 <= 3'd7;
-        a7ddrphy_bitslip10_value0 <= 3'd7;
-        a7ddrphy_bitslip10_value1 <= 3'd7;
-        a7ddrphy_bitslip11_value0 <= 3'd7;
-        a7ddrphy_bitslip11_value1 <= 3'd7;
-        a7ddrphy_bitslip12_value0 <= 3'd7;
-        a7ddrphy_bitslip12_value1 <= 3'd7;
-        a7ddrphy_bitslip13_value0 <= 3'd7;
-        a7ddrphy_bitslip13_value1 <= 3'd7;
-        a7ddrphy_bitslip14_value0 <= 3'd7;
-        a7ddrphy_bitslip14_value1 <= 3'd7;
-        a7ddrphy_bitslip15_value0 <= 3'd7;
-        a7ddrphy_bitslip15_value1 <= 3'd7;
-        a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
-        a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
-        a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
-        a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
-        litedramcore_storage <= 4'd1;
-        litedramcore_re <= 1'd0;
-        litedramcore_phaseinjector0_command_storage <= 6'd0;
-        litedramcore_phaseinjector0_command_re <= 1'd0;
-        litedramcore_phaseinjector0_address_re <= 1'd0;
-        litedramcore_phaseinjector0_baddress_re <= 1'd0;
-        litedramcore_phaseinjector0_wrdata_re <= 1'd0;
-        litedramcore_phaseinjector0_rddata_status <= 32'd0;
-        litedramcore_phaseinjector0_rddata_re <= 1'd0;
-        litedramcore_phaseinjector1_command_storage <= 6'd0;
-        litedramcore_phaseinjector1_command_re <= 1'd0;
-        litedramcore_phaseinjector1_address_re <= 1'd0;
-        litedramcore_phaseinjector1_baddress_re <= 1'd0;
-        litedramcore_phaseinjector1_wrdata_re <= 1'd0;
-        litedramcore_phaseinjector1_rddata_status <= 32'd0;
-        litedramcore_phaseinjector1_rddata_re <= 1'd0;
-        litedramcore_phaseinjector2_command_storage <= 6'd0;
-        litedramcore_phaseinjector2_command_re <= 1'd0;
-        litedramcore_phaseinjector2_address_re <= 1'd0;
-        litedramcore_phaseinjector2_baddress_re <= 1'd0;
-        litedramcore_phaseinjector2_wrdata_re <= 1'd0;
-        litedramcore_phaseinjector2_rddata_status <= 32'd0;
-        litedramcore_phaseinjector2_rddata_re <= 1'd0;
-        litedramcore_phaseinjector3_command_storage <= 6'd0;
-        litedramcore_phaseinjector3_command_re <= 1'd0;
-        litedramcore_phaseinjector3_address_re <= 1'd0;
-        litedramcore_phaseinjector3_baddress_re <= 1'd0;
-        litedramcore_phaseinjector3_wrdata_re <= 1'd0;
-        litedramcore_phaseinjector3_rddata_status <= 32'd0;
-        litedramcore_phaseinjector3_rddata_re <= 1'd0;
-        litedramcore_dfi_p0_address <= 14'd0;
-        litedramcore_dfi_p0_bank <= 3'd0;
-        litedramcore_dfi_p0_cas_n <= 1'd1;
-        litedramcore_dfi_p0_cs_n <= 1'd1;
-        litedramcore_dfi_p0_ras_n <= 1'd1;
-        litedramcore_dfi_p0_we_n <= 1'd1;
-        litedramcore_dfi_p0_wrdata_en <= 1'd0;
-        litedramcore_dfi_p0_rddata_en <= 1'd0;
-        litedramcore_dfi_p1_address <= 14'd0;
-        litedramcore_dfi_p1_bank <= 3'd0;
-        litedramcore_dfi_p1_cas_n <= 1'd1;
-        litedramcore_dfi_p1_cs_n <= 1'd1;
-        litedramcore_dfi_p1_ras_n <= 1'd1;
-        litedramcore_dfi_p1_we_n <= 1'd1;
-        litedramcore_dfi_p1_wrdata_en <= 1'd0;
-        litedramcore_dfi_p1_rddata_en <= 1'd0;
-        litedramcore_dfi_p2_address <= 14'd0;
-        litedramcore_dfi_p2_bank <= 3'd0;
-        litedramcore_dfi_p2_cas_n <= 1'd1;
-        litedramcore_dfi_p2_cs_n <= 1'd1;
-        litedramcore_dfi_p2_ras_n <= 1'd1;
-        litedramcore_dfi_p2_we_n <= 1'd1;
-        litedramcore_dfi_p2_wrdata_en <= 1'd0;
-        litedramcore_dfi_p2_rddata_en <= 1'd0;
-        litedramcore_dfi_p3_address <= 14'd0;
-        litedramcore_dfi_p3_bank <= 3'd0;
-        litedramcore_dfi_p3_cas_n <= 1'd1;
-        litedramcore_dfi_p3_cs_n <= 1'd1;
-        litedramcore_dfi_p3_ras_n <= 1'd1;
-        litedramcore_dfi_p3_we_n <= 1'd1;
-        litedramcore_dfi_p3_wrdata_en <= 1'd0;
-        litedramcore_dfi_p3_rddata_en <= 1'd0;
-        litedramcore_cmd_payload_a <= 14'd0;
-        litedramcore_cmd_payload_ba <= 3'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd0;
-        litedramcore_cmd_payload_we <= 1'd0;
-        litedramcore_timer_count1 <= 10'd781;
-        litedramcore_postponer_req_o <= 1'd0;
-        litedramcore_postponer_count <= 1'd0;
-        litedramcore_sequencer_done1 <= 1'd0;
-        litedramcore_sequencer_counter <= 6'd0;
-        litedramcore_sequencer_count <= 1'd0;
-        litedramcore_zqcs_timer_count1 <= 27'd99999999;
-        litedramcore_zqcs_executer_done <= 1'd0;
-        litedramcore_zqcs_executer_counter <= 5'd0;
-        litedramcore_bankmachine0_level <= 5'd0;
-        litedramcore_bankmachine0_produce <= 4'd0;
-        litedramcore_bankmachine0_consume <= 4'd0;
-        litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 21'd0;
-        litedramcore_bankmachine0_row <= 14'd0;
-        litedramcore_bankmachine0_row_opened <= 1'd0;
-        litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine0_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine0_trccon_ready <= 1'd0;
-        litedramcore_bankmachine0_trccon_count <= 3'd0;
-        litedramcore_bankmachine0_trascon_ready <= 1'd0;
-        litedramcore_bankmachine0_trascon_count <= 3'd0;
-        litedramcore_bankmachine1_level <= 5'd0;
-        litedramcore_bankmachine1_produce <= 4'd0;
-        litedramcore_bankmachine1_consume <= 4'd0;
-        litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 21'd0;
-        litedramcore_bankmachine1_row <= 14'd0;
-        litedramcore_bankmachine1_row_opened <= 1'd0;
-        litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine1_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine1_trccon_ready <= 1'd0;
-        litedramcore_bankmachine1_trccon_count <= 3'd0;
-        litedramcore_bankmachine1_trascon_ready <= 1'd0;
-        litedramcore_bankmachine1_trascon_count <= 3'd0;
-        litedramcore_bankmachine2_level <= 5'd0;
-        litedramcore_bankmachine2_produce <= 4'd0;
-        litedramcore_bankmachine2_consume <= 4'd0;
-        litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 21'd0;
-        litedramcore_bankmachine2_row <= 14'd0;
-        litedramcore_bankmachine2_row_opened <= 1'd0;
-        litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine2_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine2_trccon_ready <= 1'd0;
-        litedramcore_bankmachine2_trccon_count <= 3'd0;
-        litedramcore_bankmachine2_trascon_ready <= 1'd0;
-        litedramcore_bankmachine2_trascon_count <= 3'd0;
-        litedramcore_bankmachine3_level <= 5'd0;
-        litedramcore_bankmachine3_produce <= 4'd0;
-        litedramcore_bankmachine3_consume <= 4'd0;
-        litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 21'd0;
-        litedramcore_bankmachine3_row <= 14'd0;
-        litedramcore_bankmachine3_row_opened <= 1'd0;
-        litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine3_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine3_trccon_ready <= 1'd0;
-        litedramcore_bankmachine3_trccon_count <= 3'd0;
-        litedramcore_bankmachine3_trascon_ready <= 1'd0;
-        litedramcore_bankmachine3_trascon_count <= 3'd0;
-        litedramcore_bankmachine4_level <= 5'd0;
-        litedramcore_bankmachine4_produce <= 4'd0;
-        litedramcore_bankmachine4_consume <= 4'd0;
-        litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 21'd0;
-        litedramcore_bankmachine4_row <= 14'd0;
-        litedramcore_bankmachine4_row_opened <= 1'd0;
-        litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine4_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine4_trccon_ready <= 1'd0;
-        litedramcore_bankmachine4_trccon_count <= 3'd0;
-        litedramcore_bankmachine4_trascon_ready <= 1'd0;
-        litedramcore_bankmachine4_trascon_count <= 3'd0;
-        litedramcore_bankmachine5_level <= 5'd0;
-        litedramcore_bankmachine5_produce <= 4'd0;
-        litedramcore_bankmachine5_consume <= 4'd0;
-        litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 21'd0;
-        litedramcore_bankmachine5_row <= 14'd0;
-        litedramcore_bankmachine5_row_opened <= 1'd0;
-        litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine5_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine5_trccon_ready <= 1'd0;
-        litedramcore_bankmachine5_trccon_count <= 3'd0;
-        litedramcore_bankmachine5_trascon_ready <= 1'd0;
-        litedramcore_bankmachine5_trascon_count <= 3'd0;
-        litedramcore_bankmachine6_level <= 5'd0;
-        litedramcore_bankmachine6_produce <= 4'd0;
-        litedramcore_bankmachine6_consume <= 4'd0;
-        litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 21'd0;
-        litedramcore_bankmachine6_row <= 14'd0;
-        litedramcore_bankmachine6_row_opened <= 1'd0;
-        litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine6_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine6_trccon_ready <= 1'd0;
-        litedramcore_bankmachine6_trccon_count <= 3'd0;
-        litedramcore_bankmachine6_trascon_ready <= 1'd0;
-        litedramcore_bankmachine6_trascon_count <= 3'd0;
-        litedramcore_bankmachine7_level <= 5'd0;
-        litedramcore_bankmachine7_produce <= 4'd0;
-        litedramcore_bankmachine7_consume <= 4'd0;
-        litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 21'd0;
-        litedramcore_bankmachine7_row <= 14'd0;
-        litedramcore_bankmachine7_row_opened <= 1'd0;
-        litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine7_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine7_trccon_ready <= 1'd0;
-        litedramcore_bankmachine7_trccon_count <= 3'd0;
-        litedramcore_bankmachine7_trascon_ready <= 1'd0;
-        litedramcore_bankmachine7_trascon_count <= 3'd0;
-        litedramcore_choose_cmd_grant <= 3'd0;
-        litedramcore_choose_req_grant <= 3'd0;
-        litedramcore_trrdcon_ready <= 1'd0;
-        litedramcore_trrdcon_count <= 1'd0;
-        litedramcore_tfawcon_ready <= 1'd1;
-        litedramcore_tfawcon_window <= 5'd0;
-        litedramcore_tccdcon_ready <= 1'd0;
-        litedramcore_tccdcon_count <= 1'd0;
-        litedramcore_twtrcon_ready <= 1'd0;
-        litedramcore_twtrcon_count <= 3'd0;
-        litedramcore_time0 <= 5'd0;
-        litedramcore_time1 <= 4'd0;
-        init_done_storage <= 1'd0;
-        init_done_re <= 1'd0;
-        init_error_storage <= 1'd0;
-        init_error_re <= 1'd0;
-        litedramcore_we <= 1'd0;
-        litedramcore_refresher_state <= 2'd0;
-        litedramcore_bankmachine0_state <= 4'd0;
-        litedramcore_bankmachine1_state <= 4'd0;
-        litedramcore_bankmachine2_state <= 4'd0;
-        litedramcore_bankmachine3_state <= 4'd0;
-        litedramcore_bankmachine4_state <= 4'd0;
-        litedramcore_bankmachine5_state <= 4'd0;
-        litedramcore_bankmachine6_state <= 4'd0;
-        litedramcore_bankmachine7_state <= 4'd0;
-        litedramcore_multiplexer_state <= 4'd0;
-        litedramcore_new_master_wdata_ready0 <= 1'd0;
-        litedramcore_new_master_wdata_ready1 <= 1'd0;
-        litedramcore_new_master_rdata_valid0 <= 1'd0;
-        litedramcore_new_master_rdata_valid1 <= 1'd0;
-        litedramcore_new_master_rdata_valid2 <= 1'd0;
-        litedramcore_new_master_rdata_valid3 <= 1'd0;
-        litedramcore_new_master_rdata_valid4 <= 1'd0;
-        litedramcore_new_master_rdata_valid5 <= 1'd0;
-        litedramcore_new_master_rdata_valid6 <= 1'd0;
-        litedramcore_new_master_rdata_valid7 <= 1'd0;
-        litedramcore_new_master_rdata_valid8 <= 1'd0;
-        litedramcore_state <= 2'd0;
+        main_a7ddrphy_rst_storage <= 1'd0;
+        main_a7ddrphy_rst_re <= 1'd0;
+        main_a7ddrphy_dly_sel_storage <= 2'd0;
+        main_a7ddrphy_dly_sel_re <= 1'd0;
+        main_a7ddrphy_half_sys8x_taps_storage <= 5'd8;
+        main_a7ddrphy_half_sys8x_taps_re <= 1'd0;
+        main_a7ddrphy_wlevel_en_storage <= 1'd0;
+        main_a7ddrphy_wlevel_en_re <= 1'd0;
+        main_a7ddrphy_rdphase_storage <= 2'd2;
+        main_a7ddrphy_rdphase_re <= 1'd0;
+        main_a7ddrphy_wrphase_storage <= 2'd3;
+        main_a7ddrphy_wrphase_re <= 1'd0;
+        main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+        main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+        main_a7ddrphy_dqspattern_o1 <= 8'd0;
+        main_a7ddrphy_bitslip0_value0 <= 3'd7;
+        main_a7ddrphy_bitslip1_value0 <= 3'd7;
+        main_a7ddrphy_bitslip0_value1 <= 3'd7;
+        main_a7ddrphy_bitslip1_value1 <= 3'd7;
+        main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+        main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+        main_a7ddrphy_bitslip0_value2 <= 3'd7;
+        main_a7ddrphy_bitslip0_value3 <= 3'd7;
+        main_a7ddrphy_bitslip1_value2 <= 3'd7;
+        main_a7ddrphy_bitslip1_value3 <= 3'd7;
+        main_a7ddrphy_bitslip2_value0 <= 3'd7;
+        main_a7ddrphy_bitslip2_value1 <= 3'd7;
+        main_a7ddrphy_bitslip3_value0 <= 3'd7;
+        main_a7ddrphy_bitslip3_value1 <= 3'd7;
+        main_a7ddrphy_bitslip4_value0 <= 3'd7;
+        main_a7ddrphy_bitslip4_value1 <= 3'd7;
+        main_a7ddrphy_bitslip5_value0 <= 3'd7;
+        main_a7ddrphy_bitslip5_value1 <= 3'd7;
+        main_a7ddrphy_bitslip6_value0 <= 3'd7;
+        main_a7ddrphy_bitslip6_value1 <= 3'd7;
+        main_a7ddrphy_bitslip7_value0 <= 3'd7;
+        main_a7ddrphy_bitslip7_value1 <= 3'd7;
+        main_a7ddrphy_bitslip8_value0 <= 3'd7;
+        main_a7ddrphy_bitslip8_value1 <= 3'd7;
+        main_a7ddrphy_bitslip9_value0 <= 3'd7;
+        main_a7ddrphy_bitslip9_value1 <= 3'd7;
+        main_a7ddrphy_bitslip10_value0 <= 3'd7;
+        main_a7ddrphy_bitslip10_value1 <= 3'd7;
+        main_a7ddrphy_bitslip11_value0 <= 3'd7;
+        main_a7ddrphy_bitslip11_value1 <= 3'd7;
+        main_a7ddrphy_bitslip12_value0 <= 3'd7;
+        main_a7ddrphy_bitslip12_value1 <= 3'd7;
+        main_a7ddrphy_bitslip13_value0 <= 3'd7;
+        main_a7ddrphy_bitslip13_value1 <= 3'd7;
+        main_a7ddrphy_bitslip14_value0 <= 3'd7;
+        main_a7ddrphy_bitslip14_value1 <= 3'd7;
+        main_a7ddrphy_bitslip15_value0 <= 3'd7;
+        main_a7ddrphy_bitslip15_value1 <= 3'd7;
+        main_a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
+        main_a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
+        main_a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
+        main_a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
+        main_litedramcore_storage <= 4'd1;
+        main_litedramcore_re <= 1'd0;
+        main_litedramcore_phaseinjector0_command_storage <= 8'd0;
+        main_litedramcore_phaseinjector0_command_re <= 1'd0;
+        main_litedramcore_phaseinjector0_address_re <= 1'd0;
+        main_litedramcore_phaseinjector0_baddress_re <= 1'd0;
+        main_litedramcore_phaseinjector0_wrdata_re <= 1'd0;
+        main_litedramcore_phaseinjector0_rddata_status <= 32'd0;
+        main_litedramcore_phaseinjector0_rddata_re <= 1'd0;
+        main_litedramcore_phaseinjector1_command_storage <= 8'd0;
+        main_litedramcore_phaseinjector1_command_re <= 1'd0;
+        main_litedramcore_phaseinjector1_address_re <= 1'd0;
+        main_litedramcore_phaseinjector1_baddress_re <= 1'd0;
+        main_litedramcore_phaseinjector1_wrdata_re <= 1'd0;
+        main_litedramcore_phaseinjector1_rddata_status <= 32'd0;
+        main_litedramcore_phaseinjector1_rddata_re <= 1'd0;
+        main_litedramcore_phaseinjector2_command_storage <= 8'd0;
+        main_litedramcore_phaseinjector2_command_re <= 1'd0;
+        main_litedramcore_phaseinjector2_address_re <= 1'd0;
+        main_litedramcore_phaseinjector2_baddress_re <= 1'd0;
+        main_litedramcore_phaseinjector2_wrdata_re <= 1'd0;
+        main_litedramcore_phaseinjector2_rddata_status <= 32'd0;
+        main_litedramcore_phaseinjector2_rddata_re <= 1'd0;
+        main_litedramcore_phaseinjector3_command_storage <= 8'd0;
+        main_litedramcore_phaseinjector3_command_re <= 1'd0;
+        main_litedramcore_phaseinjector3_address_re <= 1'd0;
+        main_litedramcore_phaseinjector3_baddress_re <= 1'd0;
+        main_litedramcore_phaseinjector3_wrdata_re <= 1'd0;
+        main_litedramcore_phaseinjector3_rddata_status <= 32'd0;
+        main_litedramcore_phaseinjector3_rddata_re <= 1'd0;
+        main_litedramcore_dfi_p0_address <= 14'd0;
+        main_litedramcore_dfi_p0_bank <= 3'd0;
+        main_litedramcore_dfi_p0_cas_n <= 1'd1;
+        main_litedramcore_dfi_p0_cs_n <= 1'd1;
+        main_litedramcore_dfi_p0_ras_n <= 1'd1;
+        main_litedramcore_dfi_p0_we_n <= 1'd1;
+        main_litedramcore_dfi_p0_wrdata_en <= 1'd0;
+        main_litedramcore_dfi_p0_rddata_en <= 1'd0;
+        main_litedramcore_dfi_p1_address <= 14'd0;
+        main_litedramcore_dfi_p1_bank <= 3'd0;
+        main_litedramcore_dfi_p1_cas_n <= 1'd1;
+        main_litedramcore_dfi_p1_cs_n <= 1'd1;
+        main_litedramcore_dfi_p1_ras_n <= 1'd1;
+        main_litedramcore_dfi_p1_we_n <= 1'd1;
+        main_litedramcore_dfi_p1_wrdata_en <= 1'd0;
+        main_litedramcore_dfi_p1_rddata_en <= 1'd0;
+        main_litedramcore_dfi_p2_address <= 14'd0;
+        main_litedramcore_dfi_p2_bank <= 3'd0;
+        main_litedramcore_dfi_p2_cas_n <= 1'd1;
+        main_litedramcore_dfi_p2_cs_n <= 1'd1;
+        main_litedramcore_dfi_p2_ras_n <= 1'd1;
+        main_litedramcore_dfi_p2_we_n <= 1'd1;
+        main_litedramcore_dfi_p2_wrdata_en <= 1'd0;
+        main_litedramcore_dfi_p2_rddata_en <= 1'd0;
+        main_litedramcore_dfi_p3_address <= 14'd0;
+        main_litedramcore_dfi_p3_bank <= 3'd0;
+        main_litedramcore_dfi_p3_cas_n <= 1'd1;
+        main_litedramcore_dfi_p3_cs_n <= 1'd1;
+        main_litedramcore_dfi_p3_ras_n <= 1'd1;
+        main_litedramcore_dfi_p3_we_n <= 1'd1;
+        main_litedramcore_dfi_p3_wrdata_en <= 1'd0;
+        main_litedramcore_dfi_p3_rddata_en <= 1'd0;
+        main_litedramcore_cmd_payload_a <= 14'd0;
+        main_litedramcore_cmd_payload_ba <= 3'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd0;
+        main_litedramcore_cmd_payload_we <= 1'd0;
+        main_litedramcore_timer_count1 <= 10'd781;
+        main_litedramcore_postponer_req_o <= 1'd0;
+        main_litedramcore_postponer_count <= 1'd0;
+        main_litedramcore_sequencer_done1 <= 1'd0;
+        main_litedramcore_sequencer_trigger <= 6'd0;
+        main_litedramcore_sequencer_count <= 1'd0;
+        main_litedramcore_zqcs_timer_count1 <= 27'd99999999;
+        main_litedramcore_zqcs_executer_done <= 1'd0;
+        main_litedramcore_zqcs_executer_trigger <= 5'd0;
+        main_litedramcore_bankmachine0_level <= 5'd0;
+        main_litedramcore_bankmachine0_produce <= 4'd0;
+        main_litedramcore_bankmachine0_consume <= 4'd0;
+        main_litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 21'd0;
+        main_litedramcore_bankmachine0_row <= 14'd0;
+        main_litedramcore_bankmachine0_row_opened <= 1'd0;
+        main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine0_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine0_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine0_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine0_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine0_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine1_level <= 5'd0;
+        main_litedramcore_bankmachine1_produce <= 4'd0;
+        main_litedramcore_bankmachine1_consume <= 4'd0;
+        main_litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 21'd0;
+        main_litedramcore_bankmachine1_row <= 14'd0;
+        main_litedramcore_bankmachine1_row_opened <= 1'd0;
+        main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine1_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine1_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine1_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine1_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine1_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine2_level <= 5'd0;
+        main_litedramcore_bankmachine2_produce <= 4'd0;
+        main_litedramcore_bankmachine2_consume <= 4'd0;
+        main_litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 21'd0;
+        main_litedramcore_bankmachine2_row <= 14'd0;
+        main_litedramcore_bankmachine2_row_opened <= 1'd0;
+        main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine2_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine2_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine2_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine2_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine2_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine3_level <= 5'd0;
+        main_litedramcore_bankmachine3_produce <= 4'd0;
+        main_litedramcore_bankmachine3_consume <= 4'd0;
+        main_litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 21'd0;
+        main_litedramcore_bankmachine3_row <= 14'd0;
+        main_litedramcore_bankmachine3_row_opened <= 1'd0;
+        main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine3_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine3_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine3_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine3_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine3_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine4_level <= 5'd0;
+        main_litedramcore_bankmachine4_produce <= 4'd0;
+        main_litedramcore_bankmachine4_consume <= 4'd0;
+        main_litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 21'd0;
+        main_litedramcore_bankmachine4_row <= 14'd0;
+        main_litedramcore_bankmachine4_row_opened <= 1'd0;
+        main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine4_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine4_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine4_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine4_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine4_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine5_level <= 5'd0;
+        main_litedramcore_bankmachine5_produce <= 4'd0;
+        main_litedramcore_bankmachine5_consume <= 4'd0;
+        main_litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 21'd0;
+        main_litedramcore_bankmachine5_row <= 14'd0;
+        main_litedramcore_bankmachine5_row_opened <= 1'd0;
+        main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine5_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine5_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine5_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine5_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine5_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine6_level <= 5'd0;
+        main_litedramcore_bankmachine6_produce <= 4'd0;
+        main_litedramcore_bankmachine6_consume <= 4'd0;
+        main_litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 21'd0;
+        main_litedramcore_bankmachine6_row <= 14'd0;
+        main_litedramcore_bankmachine6_row_opened <= 1'd0;
+        main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine6_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine6_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine6_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine6_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine6_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine7_level <= 5'd0;
+        main_litedramcore_bankmachine7_produce <= 4'd0;
+        main_litedramcore_bankmachine7_consume <= 4'd0;
+        main_litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 21'd0;
+        main_litedramcore_bankmachine7_row <= 14'd0;
+        main_litedramcore_bankmachine7_row_opened <= 1'd0;
+        main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine7_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine7_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine7_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine7_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine7_trascon_count <= 3'd0;
+        main_litedramcore_choose_cmd_grant <= 3'd0;
+        main_litedramcore_choose_req_grant <= 3'd0;
+        main_litedramcore_trrdcon_ready <= 1'd0;
+        main_litedramcore_trrdcon_count <= 1'd0;
+        main_litedramcore_tfawcon_ready <= 1'd1;
+        main_litedramcore_tfawcon_window <= 5'd0;
+        main_litedramcore_tccdcon_ready <= 1'd0;
+        main_litedramcore_tccdcon_count <= 1'd0;
+        main_litedramcore_twtrcon_ready <= 1'd0;
+        main_litedramcore_twtrcon_count <= 3'd0;
+        main_litedramcore_time0 <= 5'd0;
+        main_litedramcore_time1 <= 4'd0;
+        main_init_done_storage <= 1'd0;
+        main_init_done_re <= 1'd0;
+        main_init_error_storage <= 1'd0;
+        main_init_error_re <= 1'd0;
+        builder_interface1_we <= 1'd0;
+        builder_refresher_state <= 2'd0;
+        builder_bankmachine0_state <= 4'd0;
+        builder_bankmachine1_state <= 4'd0;
+        builder_bankmachine2_state <= 4'd0;
+        builder_bankmachine3_state <= 4'd0;
+        builder_bankmachine4_state <= 4'd0;
+        builder_bankmachine5_state <= 4'd0;
+        builder_bankmachine6_state <= 4'd0;
+        builder_bankmachine7_state <= 4'd0;
+        builder_multiplexer_state <= 4'd0;
+        builder_new_master_wdata_ready0 <= 1'd0;
+        builder_new_master_wdata_ready1 <= 1'd0;
+        builder_new_master_rdata_valid0 <= 1'd0;
+        builder_new_master_rdata_valid1 <= 1'd0;
+        builder_new_master_rdata_valid2 <= 1'd0;
+        builder_new_master_rdata_valid3 <= 1'd0;
+        builder_new_master_rdata_valid4 <= 1'd0;
+        builder_new_master_rdata_valid5 <= 1'd0;
+        builder_new_master_rdata_valid6 <= 1'd0;
+        builder_new_master_rdata_valid7 <= 1'd0;
+        builder_new_master_rdata_valid8 <= 1'd0;
+        builder_state <= 2'd0;
     end
 end
 
@@ -14116,1911 +14531,2624 @@ end
 // Specialized Logic
 //------------------------------------------------------------------------------
 
+//------------------------------------------------------------------------------
+// Instance BUFG of BUFG Module.
+//------------------------------------------------------------------------------
 BUFG BUFG(
-	.I(clkout0),
-	.O(clkout_buf0)
+	// Inputs.
+	.I (main_clkout0),
+
+	// Outputs.
+	.O (main_clkout_buf0)
 );
 
+//------------------------------------------------------------------------------
+// Instance BUFG_1 of BUFG Module.
+//------------------------------------------------------------------------------
 BUFG BUFG_1(
-	.I(clkout1),
-	.O(clkout_buf1)
+	// Inputs.
+	.I (main_clkout1),
+
+	// Outputs.
+	.O (main_clkout_buf1)
 );
 
+//------------------------------------------------------------------------------
+// Instance BUFG_2 of BUFG Module.
+//------------------------------------------------------------------------------
 BUFG BUFG_2(
-	.I(clkout2),
-	.O(clkout_buf2)
+	// Inputs.
+	.I (main_clkout2),
+
+	// Outputs.
+	.O (main_clkout_buf2)
 );
 
+//------------------------------------------------------------------------------
+// Instance BUFG_3 of BUFG Module.
+//------------------------------------------------------------------------------
 BUFG BUFG_3(
-	.I(clkout3),
-	.O(clkout_buf3)
+	// Inputs.
+	.I (main_clkout3),
+
+	// Outputs.
+	.O (main_clkout_buf3)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYCTRL of IDELAYCTRL Module.
+//------------------------------------------------------------------------------
 IDELAYCTRL IDELAYCTRL(
-	.REFCLK(iodelay_clk),
-	.RST(ic_reset)
+	// Inputs.
+	.REFCLK (iodelay_clk),
+	.RST    (main_ic_reset)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(1'd0),
-	.D2(1'd1),
-	.D3(1'd0),
-	.D4(1'd1),
-	.D5(1'd0),
-	.D6(1'd1),
-	.D7(1'd0),
-	.D8(1'd1),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(a7ddrphy_sd_clk_se_nodelay)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (1'd0),
+	.D2     (1'd1),
+	.D3     (1'd0),
+	.D4     (1'd1),
+	.D5     (1'd0),
+	.D6     (1'd1),
+	.D7     (1'd0),
+	.D8     (1'd1),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_sd_clk_se_nodelay)
 );
 
+//------------------------------------------------------------------------------
+// Instance OBUFDS of OBUFDS Module.
+//------------------------------------------------------------------------------
 OBUFDS OBUFDS(
-	.I(a7ddrphy_sd_clk_se_nodelay),
-	.O(ddram_clk_p),
-	.OB(ddram_clk_n)
+	// Inputs.
+	.I  (main_a7ddrphy_sd_clk_se_nodelay),
+
+	// Outputs.
+	.O  (ddram_clk_p),
+	.OB (ddram_clk_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_1 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_1 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_reset_n),
-	.D2(a7ddrphy_dfi_p0_reset_n),
-	.D3(a7ddrphy_dfi_p1_reset_n),
-	.D4(a7ddrphy_dfi_p1_reset_n),
-	.D5(a7ddrphy_dfi_p2_reset_n),
-	.D6(a7ddrphy_dfi_p2_reset_n),
-	.D7(a7ddrphy_dfi_p3_reset_n),
-	.D8(a7ddrphy_dfi_p3_reset_n),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_reset_n)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_reset_n),
+	.D2     (main_a7ddrphy_dfi_p0_reset_n),
+	.D3     (main_a7ddrphy_dfi_p1_reset_n),
+	.D4     (main_a7ddrphy_dfi_p1_reset_n),
+	.D5     (main_a7ddrphy_dfi_p2_reset_n),
+	.D6     (main_a7ddrphy_dfi_p2_reset_n),
+	.D7     (main_a7ddrphy_dfi_p3_reset_n),
+	.D8     (main_a7ddrphy_dfi_p3_reset_n),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_reset_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_2 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_2 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_cs_n),
-	.D2(a7ddrphy_dfi_p0_cs_n),
-	.D3(a7ddrphy_dfi_p1_cs_n),
-	.D4(a7ddrphy_dfi_p1_cs_n),
-	.D5(a7ddrphy_dfi_p2_cs_n),
-	.D6(a7ddrphy_dfi_p2_cs_n),
-	.D7(a7ddrphy_dfi_p3_cs_n),
-	.D8(a7ddrphy_dfi_p3_cs_n),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_cs_n)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_cs_n),
+	.D2     (main_a7ddrphy_dfi_p0_cs_n),
+	.D3     (main_a7ddrphy_dfi_p1_cs_n),
+	.D4     (main_a7ddrphy_dfi_p1_cs_n),
+	.D5     (main_a7ddrphy_dfi_p2_cs_n),
+	.D6     (main_a7ddrphy_dfi_p2_cs_n),
+	.D7     (main_a7ddrphy_dfi_p3_cs_n),
+	.D8     (main_a7ddrphy_dfi_p3_cs_n),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_cs_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_3 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_3 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[0]),
-	.D2(a7ddrphy_dfi_p0_address[0]),
-	.D3(a7ddrphy_dfi_p1_address[0]),
-	.D4(a7ddrphy_dfi_p1_address[0]),
-	.D5(a7ddrphy_dfi_p2_address[0]),
-	.D6(a7ddrphy_dfi_p2_address[0]),
-	.D7(a7ddrphy_dfi_p3_address[0]),
-	.D8(a7ddrphy_dfi_p3_address[0]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[0])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[0]),
+	.D2     (main_a7ddrphy_dfi_p0_address[0]),
+	.D3     (main_a7ddrphy_dfi_p1_address[0]),
+	.D4     (main_a7ddrphy_dfi_p1_address[0]),
+	.D5     (main_a7ddrphy_dfi_p2_address[0]),
+	.D6     (main_a7ddrphy_dfi_p2_address[0]),
+	.D7     (main_a7ddrphy_dfi_p3_address[0]),
+	.D8     (main_a7ddrphy_dfi_p3_address[0]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_4 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_4 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[1]),
-	.D2(a7ddrphy_dfi_p0_address[1]),
-	.D3(a7ddrphy_dfi_p1_address[1]),
-	.D4(a7ddrphy_dfi_p1_address[1]),
-	.D5(a7ddrphy_dfi_p2_address[1]),
-	.D6(a7ddrphy_dfi_p2_address[1]),
-	.D7(a7ddrphy_dfi_p3_address[1]),
-	.D8(a7ddrphy_dfi_p3_address[1]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[1])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[1]),
+	.D2     (main_a7ddrphy_dfi_p0_address[1]),
+	.D3     (main_a7ddrphy_dfi_p1_address[1]),
+	.D4     (main_a7ddrphy_dfi_p1_address[1]),
+	.D5     (main_a7ddrphy_dfi_p2_address[1]),
+	.D6     (main_a7ddrphy_dfi_p2_address[1]),
+	.D7     (main_a7ddrphy_dfi_p3_address[1]),
+	.D8     (main_a7ddrphy_dfi_p3_address[1]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[1])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_5 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_5 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[2]),
-	.D2(a7ddrphy_dfi_p0_address[2]),
-	.D3(a7ddrphy_dfi_p1_address[2]),
-	.D4(a7ddrphy_dfi_p1_address[2]),
-	.D5(a7ddrphy_dfi_p2_address[2]),
-	.D6(a7ddrphy_dfi_p2_address[2]),
-	.D7(a7ddrphy_dfi_p3_address[2]),
-	.D8(a7ddrphy_dfi_p3_address[2]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[2])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[2]),
+	.D2     (main_a7ddrphy_dfi_p0_address[2]),
+	.D3     (main_a7ddrphy_dfi_p1_address[2]),
+	.D4     (main_a7ddrphy_dfi_p1_address[2]),
+	.D5     (main_a7ddrphy_dfi_p2_address[2]),
+	.D6     (main_a7ddrphy_dfi_p2_address[2]),
+	.D7     (main_a7ddrphy_dfi_p3_address[2]),
+	.D8     (main_a7ddrphy_dfi_p3_address[2]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[2])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_6 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_6 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[3]),
-	.D2(a7ddrphy_dfi_p0_address[3]),
-	.D3(a7ddrphy_dfi_p1_address[3]),
-	.D4(a7ddrphy_dfi_p1_address[3]),
-	.D5(a7ddrphy_dfi_p2_address[3]),
-	.D6(a7ddrphy_dfi_p2_address[3]),
-	.D7(a7ddrphy_dfi_p3_address[3]),
-	.D8(a7ddrphy_dfi_p3_address[3]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[3])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[3]),
+	.D2     (main_a7ddrphy_dfi_p0_address[3]),
+	.D3     (main_a7ddrphy_dfi_p1_address[3]),
+	.D4     (main_a7ddrphy_dfi_p1_address[3]),
+	.D5     (main_a7ddrphy_dfi_p2_address[3]),
+	.D6     (main_a7ddrphy_dfi_p2_address[3]),
+	.D7     (main_a7ddrphy_dfi_p3_address[3]),
+	.D8     (main_a7ddrphy_dfi_p3_address[3]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_7 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_7 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[4]),
-	.D2(a7ddrphy_dfi_p0_address[4]),
-	.D3(a7ddrphy_dfi_p1_address[4]),
-	.D4(a7ddrphy_dfi_p1_address[4]),
-	.D5(a7ddrphy_dfi_p2_address[4]),
-	.D6(a7ddrphy_dfi_p2_address[4]),
-	.D7(a7ddrphy_dfi_p3_address[4]),
-	.D8(a7ddrphy_dfi_p3_address[4]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[4])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[4]),
+	.D2     (main_a7ddrphy_dfi_p0_address[4]),
+	.D3     (main_a7ddrphy_dfi_p1_address[4]),
+	.D4     (main_a7ddrphy_dfi_p1_address[4]),
+	.D5     (main_a7ddrphy_dfi_p2_address[4]),
+	.D6     (main_a7ddrphy_dfi_p2_address[4]),
+	.D7     (main_a7ddrphy_dfi_p3_address[4]),
+	.D8     (main_a7ddrphy_dfi_p3_address[4]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[4])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_8 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_8 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[5]),
-	.D2(a7ddrphy_dfi_p0_address[5]),
-	.D3(a7ddrphy_dfi_p1_address[5]),
-	.D4(a7ddrphy_dfi_p1_address[5]),
-	.D5(a7ddrphy_dfi_p2_address[5]),
-	.D6(a7ddrphy_dfi_p2_address[5]),
-	.D7(a7ddrphy_dfi_p3_address[5]),
-	.D8(a7ddrphy_dfi_p3_address[5]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[5])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[5]),
+	.D2     (main_a7ddrphy_dfi_p0_address[5]),
+	.D3     (main_a7ddrphy_dfi_p1_address[5]),
+	.D4     (main_a7ddrphy_dfi_p1_address[5]),
+	.D5     (main_a7ddrphy_dfi_p2_address[5]),
+	.D6     (main_a7ddrphy_dfi_p2_address[5]),
+	.D7     (main_a7ddrphy_dfi_p3_address[5]),
+	.D8     (main_a7ddrphy_dfi_p3_address[5]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[5])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_9 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_9 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[6]),
-	.D2(a7ddrphy_dfi_p0_address[6]),
-	.D3(a7ddrphy_dfi_p1_address[6]),
-	.D4(a7ddrphy_dfi_p1_address[6]),
-	.D5(a7ddrphy_dfi_p2_address[6]),
-	.D6(a7ddrphy_dfi_p2_address[6]),
-	.D7(a7ddrphy_dfi_p3_address[6]),
-	.D8(a7ddrphy_dfi_p3_address[6]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[6])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[6]),
+	.D2     (main_a7ddrphy_dfi_p0_address[6]),
+	.D3     (main_a7ddrphy_dfi_p1_address[6]),
+	.D4     (main_a7ddrphy_dfi_p1_address[6]),
+	.D5     (main_a7ddrphy_dfi_p2_address[6]),
+	.D6     (main_a7ddrphy_dfi_p2_address[6]),
+	.D7     (main_a7ddrphy_dfi_p3_address[6]),
+	.D8     (main_a7ddrphy_dfi_p3_address[6]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[6])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_10 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_10 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[7]),
-	.D2(a7ddrphy_dfi_p0_address[7]),
-	.D3(a7ddrphy_dfi_p1_address[7]),
-	.D4(a7ddrphy_dfi_p1_address[7]),
-	.D5(a7ddrphy_dfi_p2_address[7]),
-	.D6(a7ddrphy_dfi_p2_address[7]),
-	.D7(a7ddrphy_dfi_p3_address[7]),
-	.D8(a7ddrphy_dfi_p3_address[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[7])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[7]),
+	.D2     (main_a7ddrphy_dfi_p0_address[7]),
+	.D3     (main_a7ddrphy_dfi_p1_address[7]),
+	.D4     (main_a7ddrphy_dfi_p1_address[7]),
+	.D5     (main_a7ddrphy_dfi_p2_address[7]),
+	.D6     (main_a7ddrphy_dfi_p2_address[7]),
+	.D7     (main_a7ddrphy_dfi_p3_address[7]),
+	.D8     (main_a7ddrphy_dfi_p3_address[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[7])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_11 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_11 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[8]),
-	.D2(a7ddrphy_dfi_p0_address[8]),
-	.D3(a7ddrphy_dfi_p1_address[8]),
-	.D4(a7ddrphy_dfi_p1_address[8]),
-	.D5(a7ddrphy_dfi_p2_address[8]),
-	.D6(a7ddrphy_dfi_p2_address[8]),
-	.D7(a7ddrphy_dfi_p3_address[8]),
-	.D8(a7ddrphy_dfi_p3_address[8]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[8])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[8]),
+	.D2     (main_a7ddrphy_dfi_p0_address[8]),
+	.D3     (main_a7ddrphy_dfi_p1_address[8]),
+	.D4     (main_a7ddrphy_dfi_p1_address[8]),
+	.D5     (main_a7ddrphy_dfi_p2_address[8]),
+	.D6     (main_a7ddrphy_dfi_p2_address[8]),
+	.D7     (main_a7ddrphy_dfi_p3_address[8]),
+	.D8     (main_a7ddrphy_dfi_p3_address[8]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[8])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_12 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_12 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[9]),
-	.D2(a7ddrphy_dfi_p0_address[9]),
-	.D3(a7ddrphy_dfi_p1_address[9]),
-	.D4(a7ddrphy_dfi_p1_address[9]),
-	.D5(a7ddrphy_dfi_p2_address[9]),
-	.D6(a7ddrphy_dfi_p2_address[9]),
-	.D7(a7ddrphy_dfi_p3_address[9]),
-	.D8(a7ddrphy_dfi_p3_address[9]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[9])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[9]),
+	.D2     (main_a7ddrphy_dfi_p0_address[9]),
+	.D3     (main_a7ddrphy_dfi_p1_address[9]),
+	.D4     (main_a7ddrphy_dfi_p1_address[9]),
+	.D5     (main_a7ddrphy_dfi_p2_address[9]),
+	.D6     (main_a7ddrphy_dfi_p2_address[9]),
+	.D7     (main_a7ddrphy_dfi_p3_address[9]),
+	.D8     (main_a7ddrphy_dfi_p3_address[9]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[9])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_13 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_13 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[10]),
-	.D2(a7ddrphy_dfi_p0_address[10]),
-	.D3(a7ddrphy_dfi_p1_address[10]),
-	.D4(a7ddrphy_dfi_p1_address[10]),
-	.D5(a7ddrphy_dfi_p2_address[10]),
-	.D6(a7ddrphy_dfi_p2_address[10]),
-	.D7(a7ddrphy_dfi_p3_address[10]),
-	.D8(a7ddrphy_dfi_p3_address[10]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[10])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[10]),
+	.D2     (main_a7ddrphy_dfi_p0_address[10]),
+	.D3     (main_a7ddrphy_dfi_p1_address[10]),
+	.D4     (main_a7ddrphy_dfi_p1_address[10]),
+	.D5     (main_a7ddrphy_dfi_p2_address[10]),
+	.D6     (main_a7ddrphy_dfi_p2_address[10]),
+	.D7     (main_a7ddrphy_dfi_p3_address[10]),
+	.D8     (main_a7ddrphy_dfi_p3_address[10]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[10])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_14 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_14 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[11]),
-	.D2(a7ddrphy_dfi_p0_address[11]),
-	.D3(a7ddrphy_dfi_p1_address[11]),
-	.D4(a7ddrphy_dfi_p1_address[11]),
-	.D5(a7ddrphy_dfi_p2_address[11]),
-	.D6(a7ddrphy_dfi_p2_address[11]),
-	.D7(a7ddrphy_dfi_p3_address[11]),
-	.D8(a7ddrphy_dfi_p3_address[11]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[11])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[11]),
+	.D2     (main_a7ddrphy_dfi_p0_address[11]),
+	.D3     (main_a7ddrphy_dfi_p1_address[11]),
+	.D4     (main_a7ddrphy_dfi_p1_address[11]),
+	.D5     (main_a7ddrphy_dfi_p2_address[11]),
+	.D6     (main_a7ddrphy_dfi_p2_address[11]),
+	.D7     (main_a7ddrphy_dfi_p3_address[11]),
+	.D8     (main_a7ddrphy_dfi_p3_address[11]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[11])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_15 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_15 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[12]),
-	.D2(a7ddrphy_dfi_p0_address[12]),
-	.D3(a7ddrphy_dfi_p1_address[12]),
-	.D4(a7ddrphy_dfi_p1_address[12]),
-	.D5(a7ddrphy_dfi_p2_address[12]),
-	.D6(a7ddrphy_dfi_p2_address[12]),
-	.D7(a7ddrphy_dfi_p3_address[12]),
-	.D8(a7ddrphy_dfi_p3_address[12]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[12])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[12]),
+	.D2     (main_a7ddrphy_dfi_p0_address[12]),
+	.D3     (main_a7ddrphy_dfi_p1_address[12]),
+	.D4     (main_a7ddrphy_dfi_p1_address[12]),
+	.D5     (main_a7ddrphy_dfi_p2_address[12]),
+	.D6     (main_a7ddrphy_dfi_p2_address[12]),
+	.D7     (main_a7ddrphy_dfi_p3_address[12]),
+	.D8     (main_a7ddrphy_dfi_p3_address[12]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[12])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_16 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_16 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[13]),
-	.D2(a7ddrphy_dfi_p0_address[13]),
-	.D3(a7ddrphy_dfi_p1_address[13]),
-	.D4(a7ddrphy_dfi_p1_address[13]),
-	.D5(a7ddrphy_dfi_p2_address[13]),
-	.D6(a7ddrphy_dfi_p2_address[13]),
-	.D7(a7ddrphy_dfi_p3_address[13]),
-	.D8(a7ddrphy_dfi_p3_address[13]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[13])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[13]),
+	.D2     (main_a7ddrphy_dfi_p0_address[13]),
+	.D3     (main_a7ddrphy_dfi_p1_address[13]),
+	.D4     (main_a7ddrphy_dfi_p1_address[13]),
+	.D5     (main_a7ddrphy_dfi_p2_address[13]),
+	.D6     (main_a7ddrphy_dfi_p2_address[13]),
+	.D7     (main_a7ddrphy_dfi_p3_address[13]),
+	.D8     (main_a7ddrphy_dfi_p3_address[13]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[13])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_17 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_17 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_bank[0]),
-	.D2(a7ddrphy_dfi_p0_bank[0]),
-	.D3(a7ddrphy_dfi_p1_bank[0]),
-	.D4(a7ddrphy_dfi_p1_bank[0]),
-	.D5(a7ddrphy_dfi_p2_bank[0]),
-	.D6(a7ddrphy_dfi_p2_bank[0]),
-	.D7(a7ddrphy_dfi_p3_bank[0]),
-	.D8(a7ddrphy_dfi_p3_bank[0]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(a7ddrphy_pads_ba[0])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_bank[0]),
+	.D2     (main_a7ddrphy_dfi_p0_bank[0]),
+	.D3     (main_a7ddrphy_dfi_p1_bank[0]),
+	.D4     (main_a7ddrphy_dfi_p1_bank[0]),
+	.D5     (main_a7ddrphy_dfi_p2_bank[0]),
+	.D6     (main_a7ddrphy_dfi_p2_bank[0]),
+	.D7     (main_a7ddrphy_dfi_p3_bank[0]),
+	.D8     (main_a7ddrphy_dfi_p3_bank[0]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_pads_ba[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_18 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_18 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_bank[1]),
-	.D2(a7ddrphy_dfi_p0_bank[1]),
-	.D3(a7ddrphy_dfi_p1_bank[1]),
-	.D4(a7ddrphy_dfi_p1_bank[1]),
-	.D5(a7ddrphy_dfi_p2_bank[1]),
-	.D6(a7ddrphy_dfi_p2_bank[1]),
-	.D7(a7ddrphy_dfi_p3_bank[1]),
-	.D8(a7ddrphy_dfi_p3_bank[1]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(a7ddrphy_pads_ba[1])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_bank[1]),
+	.D2     (main_a7ddrphy_dfi_p0_bank[1]),
+	.D3     (main_a7ddrphy_dfi_p1_bank[1]),
+	.D4     (main_a7ddrphy_dfi_p1_bank[1]),
+	.D5     (main_a7ddrphy_dfi_p2_bank[1]),
+	.D6     (main_a7ddrphy_dfi_p2_bank[1]),
+	.D7     (main_a7ddrphy_dfi_p3_bank[1]),
+	.D8     (main_a7ddrphy_dfi_p3_bank[1]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_pads_ba[1])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_19 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_19 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_bank[2]),
-	.D2(a7ddrphy_dfi_p0_bank[2]),
-	.D3(a7ddrphy_dfi_p1_bank[2]),
-	.D4(a7ddrphy_dfi_p1_bank[2]),
-	.D5(a7ddrphy_dfi_p2_bank[2]),
-	.D6(a7ddrphy_dfi_p2_bank[2]),
-	.D7(a7ddrphy_dfi_p3_bank[2]),
-	.D8(a7ddrphy_dfi_p3_bank[2]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(a7ddrphy_pads_ba[2])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_bank[2]),
+	.D2     (main_a7ddrphy_dfi_p0_bank[2]),
+	.D3     (main_a7ddrphy_dfi_p1_bank[2]),
+	.D4     (main_a7ddrphy_dfi_p1_bank[2]),
+	.D5     (main_a7ddrphy_dfi_p2_bank[2]),
+	.D6     (main_a7ddrphy_dfi_p2_bank[2]),
+	.D7     (main_a7ddrphy_dfi_p3_bank[2]),
+	.D8     (main_a7ddrphy_dfi_p3_bank[2]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_pads_ba[2])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_20 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_20 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_ras_n),
-	.D2(a7ddrphy_dfi_p0_ras_n),
-	.D3(a7ddrphy_dfi_p1_ras_n),
-	.D4(a7ddrphy_dfi_p1_ras_n),
-	.D5(a7ddrphy_dfi_p2_ras_n),
-	.D6(a7ddrphy_dfi_p2_ras_n),
-	.D7(a7ddrphy_dfi_p3_ras_n),
-	.D8(a7ddrphy_dfi_p3_ras_n),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_ras_n)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_ras_n),
+	.D2     (main_a7ddrphy_dfi_p0_ras_n),
+	.D3     (main_a7ddrphy_dfi_p1_ras_n),
+	.D4     (main_a7ddrphy_dfi_p1_ras_n),
+	.D5     (main_a7ddrphy_dfi_p2_ras_n),
+	.D6     (main_a7ddrphy_dfi_p2_ras_n),
+	.D7     (main_a7ddrphy_dfi_p3_ras_n),
+	.D8     (main_a7ddrphy_dfi_p3_ras_n),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_ras_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_21 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_21 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_cas_n),
-	.D2(a7ddrphy_dfi_p0_cas_n),
-	.D3(a7ddrphy_dfi_p1_cas_n),
-	.D4(a7ddrphy_dfi_p1_cas_n),
-	.D5(a7ddrphy_dfi_p2_cas_n),
-	.D6(a7ddrphy_dfi_p2_cas_n),
-	.D7(a7ddrphy_dfi_p3_cas_n),
-	.D8(a7ddrphy_dfi_p3_cas_n),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_cas_n)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_cas_n),
+	.D2     (main_a7ddrphy_dfi_p0_cas_n),
+	.D3     (main_a7ddrphy_dfi_p1_cas_n),
+	.D4     (main_a7ddrphy_dfi_p1_cas_n),
+	.D5     (main_a7ddrphy_dfi_p2_cas_n),
+	.D6     (main_a7ddrphy_dfi_p2_cas_n),
+	.D7     (main_a7ddrphy_dfi_p3_cas_n),
+	.D8     (main_a7ddrphy_dfi_p3_cas_n),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_cas_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_22 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_22 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_we_n),
-	.D2(a7ddrphy_dfi_p0_we_n),
-	.D3(a7ddrphy_dfi_p1_we_n),
-	.D4(a7ddrphy_dfi_p1_we_n),
-	.D5(a7ddrphy_dfi_p2_we_n),
-	.D6(a7ddrphy_dfi_p2_we_n),
-	.D7(a7ddrphy_dfi_p3_we_n),
-	.D8(a7ddrphy_dfi_p3_we_n),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_we_n)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_we_n),
+	.D2     (main_a7ddrphy_dfi_p0_we_n),
+	.D3     (main_a7ddrphy_dfi_p1_we_n),
+	.D4     (main_a7ddrphy_dfi_p1_we_n),
+	.D5     (main_a7ddrphy_dfi_p2_we_n),
+	.D6     (main_a7ddrphy_dfi_p2_we_n),
+	.D7     (main_a7ddrphy_dfi_p3_we_n),
+	.D8     (main_a7ddrphy_dfi_p3_we_n),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_we_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_23 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_23 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_cke),
-	.D2(a7ddrphy_dfi_p0_cke),
-	.D3(a7ddrphy_dfi_p1_cke),
-	.D4(a7ddrphy_dfi_p1_cke),
-	.D5(a7ddrphy_dfi_p2_cke),
-	.D6(a7ddrphy_dfi_p2_cke),
-	.D7(a7ddrphy_dfi_p3_cke),
-	.D8(a7ddrphy_dfi_p3_cke),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_cke)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_cke),
+	.D2     (main_a7ddrphy_dfi_p0_cke),
+	.D3     (main_a7ddrphy_dfi_p1_cke),
+	.D4     (main_a7ddrphy_dfi_p1_cke),
+	.D5     (main_a7ddrphy_dfi_p2_cke),
+	.D6     (main_a7ddrphy_dfi_p2_cke),
+	.D7     (main_a7ddrphy_dfi_p3_cke),
+	.D8     (main_a7ddrphy_dfi_p3_cke),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_cke)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_24 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_24 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_odt),
-	.D2(a7ddrphy_dfi_p0_odt),
-	.D3(a7ddrphy_dfi_p1_odt),
-	.D4(a7ddrphy_dfi_p1_odt),
-	.D5(a7ddrphy_dfi_p2_odt),
-	.D6(a7ddrphy_dfi_p2_odt),
-	.D7(a7ddrphy_dfi_p3_odt),
-	.D8(a7ddrphy_dfi_p3_odt),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_odt)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_odt),
+	.D2     (main_a7ddrphy_dfi_p0_odt),
+	.D3     (main_a7ddrphy_dfi_p1_odt),
+	.D4     (main_a7ddrphy_dfi_p1_odt),
+	.D5     (main_a7ddrphy_dfi_p2_odt),
+	.D6     (main_a7ddrphy_dfi_p2_odt),
+	.D7     (main_a7ddrphy_dfi_p3_odt),
+	.D8     (main_a7ddrphy_dfi_p3_odt),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_odt)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_25 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_25 (
-	.CLK(sys4x_dqs_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip00[0]),
-	.D2(a7ddrphy_bitslip00[1]),
-	.D3(a7ddrphy_bitslip00[2]),
-	.D4(a7ddrphy_bitslip00[3]),
-	.D5(a7ddrphy_bitslip00[4]),
-	.D6(a7ddrphy_bitslip00[5]),
-	.D7(a7ddrphy_bitslip00[6]),
-	.D8(a7ddrphy_bitslip00[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OFB(a7ddrphy0),
-	.OQ(a7ddrphy_dqs_o_no_delay0),
-	.TQ(a7ddrphy_dqs_t0)
+	// Inputs.
+	.CLK    (sys4x_dqs_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip00[0]),
+	.D2     (main_a7ddrphy_bitslip00[1]),
+	.D3     (main_a7ddrphy_bitslip00[2]),
+	.D4     (main_a7ddrphy_bitslip00[3]),
+	.D5     (main_a7ddrphy_bitslip00[4]),
+	.D6     (main_a7ddrphy_bitslip00[5]),
+	.D7     (main_a7ddrphy_bitslip00[6]),
+	.D8     (main_a7ddrphy_bitslip00[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OFB    (main_a7ddrphy0),
+	.OQ     (main_a7ddrphy_dqs_o_no_delay0),
+	.TQ     (main_a7ddrphy_dqs_t0)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUFDS of IOBUFDS Module.
+//------------------------------------------------------------------------------
 IOBUFDS IOBUFDS(
-	.I(a7ddrphy_dqs_o_no_delay0),
-	.T(a7ddrphy_dqs_t0),
-	.IO(ddram_dqs_p[0]),
-	.IOB(ddram_dqs_n[0])
+	// Inputs.
+	.I   (main_a7ddrphy_dqs_o_no_delay0),
+	.T   (main_a7ddrphy_dqs_t0),
+
+	// InOuts.
+	.IO  (ddram_dqs_p[0]),
+	.IOB (ddram_dqs_n[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_26 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_26 (
-	.CLK(sys4x_dqs_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip10[0]),
-	.D2(a7ddrphy_bitslip10[1]),
-	.D3(a7ddrphy_bitslip10[2]),
-	.D4(a7ddrphy_bitslip10[3]),
-	.D5(a7ddrphy_bitslip10[4]),
-	.D6(a7ddrphy_bitslip10[5]),
-	.D7(a7ddrphy_bitslip10[6]),
-	.D8(a7ddrphy_bitslip10[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OFB(a7ddrphy1),
-	.OQ(a7ddrphy_dqs_o_no_delay1),
-	.TQ(a7ddrphy_dqs_t1)
+	// Inputs.
+	.CLK    (sys4x_dqs_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip10[0]),
+	.D2     (main_a7ddrphy_bitslip10[1]),
+	.D3     (main_a7ddrphy_bitslip10[2]),
+	.D4     (main_a7ddrphy_bitslip10[3]),
+	.D5     (main_a7ddrphy_bitslip10[4]),
+	.D6     (main_a7ddrphy_bitslip10[5]),
+	.D7     (main_a7ddrphy_bitslip10[6]),
+	.D8     (main_a7ddrphy_bitslip10[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OFB    (main_a7ddrphy1),
+	.OQ     (main_a7ddrphy_dqs_o_no_delay1),
+	.TQ     (main_a7ddrphy_dqs_t1)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUFDS_1 of IOBUFDS Module.
+//------------------------------------------------------------------------------
 IOBUFDS IOBUFDS_1(
-	.I(a7ddrphy_dqs_o_no_delay1),
-	.T(a7ddrphy_dqs_t1),
-	.IO(ddram_dqs_p[1]),
-	.IOB(ddram_dqs_n[1])
+	// Inputs.
+	.I   (main_a7ddrphy_dqs_o_no_delay1),
+	.T   (main_a7ddrphy_dqs_t1),
+
+	// InOuts.
+	.IO  (ddram_dqs_p[1]),
+	.IOB (ddram_dqs_n[1])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_27 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_27 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip01[0]),
-	.D2(a7ddrphy_bitslip01[1]),
-	.D3(a7ddrphy_bitslip01[2]),
-	.D4(a7ddrphy_bitslip01[3]),
-	.D5(a7ddrphy_bitslip01[4]),
-	.D6(a7ddrphy_bitslip01[5]),
-	.D7(a7ddrphy_bitslip01[6]),
-	.D8(a7ddrphy_bitslip01[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_dm[0])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip01[0]),
+	.D2     (main_a7ddrphy_bitslip01[1]),
+	.D3     (main_a7ddrphy_bitslip01[2]),
+	.D4     (main_a7ddrphy_bitslip01[3]),
+	.D5     (main_a7ddrphy_bitslip01[4]),
+	.D6     (main_a7ddrphy_bitslip01[5]),
+	.D7     (main_a7ddrphy_bitslip01[6]),
+	.D8     (main_a7ddrphy_bitslip01[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_dm[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_28 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_28 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip11[0]),
-	.D2(a7ddrphy_bitslip11[1]),
-	.D3(a7ddrphy_bitslip11[2]),
-	.D4(a7ddrphy_bitslip11[3]),
-	.D5(a7ddrphy_bitslip11[4]),
-	.D6(a7ddrphy_bitslip11[5]),
-	.D7(a7ddrphy_bitslip11[6]),
-	.D8(a7ddrphy_bitslip11[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_dm[1])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip11[0]),
+	.D2     (main_a7ddrphy_bitslip11[1]),
+	.D3     (main_a7ddrphy_bitslip11[2]),
+	.D4     (main_a7ddrphy_bitslip11[3]),
+	.D5     (main_a7ddrphy_bitslip11[4]),
+	.D6     (main_a7ddrphy_bitslip11[5]),
+	.D7     (main_a7ddrphy_bitslip11[6]),
+	.D8     (main_a7ddrphy_bitslip11[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_dm[1])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_29 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_29 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip02[0]),
-	.D2(a7ddrphy_bitslip02[1]),
-	.D3(a7ddrphy_bitslip02[2]),
-	.D4(a7ddrphy_bitslip02[3]),
-	.D5(a7ddrphy_bitslip02[4]),
-	.D6(a7ddrphy_bitslip02[5]),
-	.D7(a7ddrphy_bitslip02[6]),
-	.D8(a7ddrphy_bitslip02[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay0),
-	.TQ(a7ddrphy_dq_t0)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip02[0]),
+	.D2     (main_a7ddrphy_bitslip02[1]),
+	.D3     (main_a7ddrphy_bitslip02[2]),
+	.D4     (main_a7ddrphy_bitslip02[3]),
+	.D5     (main_a7ddrphy_bitslip02[4]),
+	.D6     (main_a7ddrphy_bitslip02[5]),
+	.D7     (main_a7ddrphy_bitslip02[6]),
+	.D8     (main_a7ddrphy_bitslip02[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay0),
+	.TQ     (main_a7ddrphy_dq_t0)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed0),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip03[7]),
-	.Q2(a7ddrphy_bitslip03[6]),
-	.Q3(a7ddrphy_bitslip03[5]),
-	.Q4(a7ddrphy_bitslip03[4]),
-	.Q5(a7ddrphy_bitslip03[3]),
-	.Q6(a7ddrphy_bitslip03[2]),
-	.Q7(a7ddrphy_bitslip03[1]),
-	.Q8(a7ddrphy_bitslip03[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed0),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip03[7]),
+	.Q2      (main_a7ddrphy_bitslip03[6]),
+	.Q3      (main_a7ddrphy_bitslip03[5]),
+	.Q4      (main_a7ddrphy_bitslip03[4]),
+	.Q5      (main_a7ddrphy_bitslip03[3]),
+	.Q6      (main_a7ddrphy_bitslip03[2]),
+	.Q7      (main_a7ddrphy_bitslip03[1]),
+	.Q8      (main_a7ddrphy_bitslip03[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay0),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed0)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay0),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed0)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF(
-	.I(a7ddrphy_dq_o_nodelay0),
-	.T(a7ddrphy_dq_t0),
-	.IO(ddram_dq[0]),
-	.O(a7ddrphy_dq_i_nodelay0)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay0),
+	.T  (main_a7ddrphy_dq_t0),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay0),
+
+	// InOuts.
+	.IO (ddram_dq[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_30 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_30 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip12[0]),
-	.D2(a7ddrphy_bitslip12[1]),
-	.D3(a7ddrphy_bitslip12[2]),
-	.D4(a7ddrphy_bitslip12[3]),
-	.D5(a7ddrphy_bitslip12[4]),
-	.D6(a7ddrphy_bitslip12[5]),
-	.D7(a7ddrphy_bitslip12[6]),
-	.D8(a7ddrphy_bitslip12[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay1),
-	.TQ(a7ddrphy_dq_t1)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip12[0]),
+	.D2     (main_a7ddrphy_bitslip12[1]),
+	.D3     (main_a7ddrphy_bitslip12[2]),
+	.D4     (main_a7ddrphy_bitslip12[3]),
+	.D5     (main_a7ddrphy_bitslip12[4]),
+	.D6     (main_a7ddrphy_bitslip12[5]),
+	.D7     (main_a7ddrphy_bitslip12[6]),
+	.D8     (main_a7ddrphy_bitslip12[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay1),
+	.TQ     (main_a7ddrphy_dq_t1)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_1 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_1 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip13[7]),
-	.Q2(a7ddrphy_bitslip13[6]),
-	.Q3(a7ddrphy_bitslip13[5]),
-	.Q4(a7ddrphy_bitslip13[4]),
-	.Q5(a7ddrphy_bitslip13[3]),
-	.Q6(a7ddrphy_bitslip13[2]),
-	.Q7(a7ddrphy_bitslip13[1]),
-	.Q8(a7ddrphy_bitslip13[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed1),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip13[7]),
+	.Q2      (main_a7ddrphy_bitslip13[6]),
+	.Q3      (main_a7ddrphy_bitslip13[5]),
+	.Q4      (main_a7ddrphy_bitslip13[4]),
+	.Q5      (main_a7ddrphy_bitslip13[3]),
+	.Q6      (main_a7ddrphy_bitslip13[2]),
+	.Q7      (main_a7ddrphy_bitslip13[1]),
+	.Q8      (main_a7ddrphy_bitslip13[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_1 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_1 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay1),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed1)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay1),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed1)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_1 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_1(
-	.I(a7ddrphy_dq_o_nodelay1),
-	.T(a7ddrphy_dq_t1),
-	.IO(ddram_dq[1]),
-	.O(a7ddrphy_dq_i_nodelay1)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay1),
+	.T  (main_a7ddrphy_dq_t1),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay1),
+
+	// InOuts.
+	.IO (ddram_dq[1])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_31 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_31 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip20[0]),
-	.D2(a7ddrphy_bitslip20[1]),
-	.D3(a7ddrphy_bitslip20[2]),
-	.D4(a7ddrphy_bitslip20[3]),
-	.D5(a7ddrphy_bitslip20[4]),
-	.D6(a7ddrphy_bitslip20[5]),
-	.D7(a7ddrphy_bitslip20[6]),
-	.D8(a7ddrphy_bitslip20[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay2),
-	.TQ(a7ddrphy_dq_t2)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip20[0]),
+	.D2     (main_a7ddrphy_bitslip20[1]),
+	.D3     (main_a7ddrphy_bitslip20[2]),
+	.D4     (main_a7ddrphy_bitslip20[3]),
+	.D5     (main_a7ddrphy_bitslip20[4]),
+	.D6     (main_a7ddrphy_bitslip20[5]),
+	.D7     (main_a7ddrphy_bitslip20[6]),
+	.D8     (main_a7ddrphy_bitslip20[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay2),
+	.TQ     (main_a7ddrphy_dq_t2)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_2 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_2 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed2),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip21[7]),
-	.Q2(a7ddrphy_bitslip21[6]),
-	.Q3(a7ddrphy_bitslip21[5]),
-	.Q4(a7ddrphy_bitslip21[4]),
-	.Q5(a7ddrphy_bitslip21[3]),
-	.Q6(a7ddrphy_bitslip21[2]),
-	.Q7(a7ddrphy_bitslip21[1]),
-	.Q8(a7ddrphy_bitslip21[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed2),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip21[7]),
+	.Q2      (main_a7ddrphy_bitslip21[6]),
+	.Q3      (main_a7ddrphy_bitslip21[5]),
+	.Q4      (main_a7ddrphy_bitslip21[4]),
+	.Q5      (main_a7ddrphy_bitslip21[3]),
+	.Q6      (main_a7ddrphy_bitslip21[2]),
+	.Q7      (main_a7ddrphy_bitslip21[1]),
+	.Q8      (main_a7ddrphy_bitslip21[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_2 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_2 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay2),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed2)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay2),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed2)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_2 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_2(
-	.I(a7ddrphy_dq_o_nodelay2),
-	.T(a7ddrphy_dq_t2),
-	.IO(ddram_dq[2]),
-	.O(a7ddrphy_dq_i_nodelay2)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay2),
+	.T  (main_a7ddrphy_dq_t2),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay2),
+
+	// InOuts.
+	.IO (ddram_dq[2])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_32 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_32 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip30[0]),
-	.D2(a7ddrphy_bitslip30[1]),
-	.D3(a7ddrphy_bitslip30[2]),
-	.D4(a7ddrphy_bitslip30[3]),
-	.D5(a7ddrphy_bitslip30[4]),
-	.D6(a7ddrphy_bitslip30[5]),
-	.D7(a7ddrphy_bitslip30[6]),
-	.D8(a7ddrphy_bitslip30[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay3),
-	.TQ(a7ddrphy_dq_t3)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip30[0]),
+	.D2     (main_a7ddrphy_bitslip30[1]),
+	.D3     (main_a7ddrphy_bitslip30[2]),
+	.D4     (main_a7ddrphy_bitslip30[3]),
+	.D5     (main_a7ddrphy_bitslip30[4]),
+	.D6     (main_a7ddrphy_bitslip30[5]),
+	.D7     (main_a7ddrphy_bitslip30[6]),
+	.D8     (main_a7ddrphy_bitslip30[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay3),
+	.TQ     (main_a7ddrphy_dq_t3)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_3 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_3 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed3),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip31[7]),
-	.Q2(a7ddrphy_bitslip31[6]),
-	.Q3(a7ddrphy_bitslip31[5]),
-	.Q4(a7ddrphy_bitslip31[4]),
-	.Q5(a7ddrphy_bitslip31[3]),
-	.Q6(a7ddrphy_bitslip31[2]),
-	.Q7(a7ddrphy_bitslip31[1]),
-	.Q8(a7ddrphy_bitslip31[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed3),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip31[7]),
+	.Q2      (main_a7ddrphy_bitslip31[6]),
+	.Q3      (main_a7ddrphy_bitslip31[5]),
+	.Q4      (main_a7ddrphy_bitslip31[4]),
+	.Q5      (main_a7ddrphy_bitslip31[3]),
+	.Q6      (main_a7ddrphy_bitslip31[2]),
+	.Q7      (main_a7ddrphy_bitslip31[1]),
+	.Q8      (main_a7ddrphy_bitslip31[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_3 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_3 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay3),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed3)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay3),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed3)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_3 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_3(
-	.I(a7ddrphy_dq_o_nodelay3),
-	.T(a7ddrphy_dq_t3),
-	.IO(ddram_dq[3]),
-	.O(a7ddrphy_dq_i_nodelay3)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay3),
+	.T  (main_a7ddrphy_dq_t3),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay3),
+
+	// InOuts.
+	.IO (ddram_dq[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_33 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_33 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip40[0]),
-	.D2(a7ddrphy_bitslip40[1]),
-	.D3(a7ddrphy_bitslip40[2]),
-	.D4(a7ddrphy_bitslip40[3]),
-	.D5(a7ddrphy_bitslip40[4]),
-	.D6(a7ddrphy_bitslip40[5]),
-	.D7(a7ddrphy_bitslip40[6]),
-	.D8(a7ddrphy_bitslip40[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay4),
-	.TQ(a7ddrphy_dq_t4)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip40[0]),
+	.D2     (main_a7ddrphy_bitslip40[1]),
+	.D3     (main_a7ddrphy_bitslip40[2]),
+	.D4     (main_a7ddrphy_bitslip40[3]),
+	.D5     (main_a7ddrphy_bitslip40[4]),
+	.D6     (main_a7ddrphy_bitslip40[5]),
+	.D7     (main_a7ddrphy_bitslip40[6]),
+	.D8     (main_a7ddrphy_bitslip40[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay4),
+	.TQ     (main_a7ddrphy_dq_t4)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_4 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_4 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed4),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip41[7]),
-	.Q2(a7ddrphy_bitslip41[6]),
-	.Q3(a7ddrphy_bitslip41[5]),
-	.Q4(a7ddrphy_bitslip41[4]),
-	.Q5(a7ddrphy_bitslip41[3]),
-	.Q6(a7ddrphy_bitslip41[2]),
-	.Q7(a7ddrphy_bitslip41[1]),
-	.Q8(a7ddrphy_bitslip41[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed4),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip41[7]),
+	.Q2      (main_a7ddrphy_bitslip41[6]),
+	.Q3      (main_a7ddrphy_bitslip41[5]),
+	.Q4      (main_a7ddrphy_bitslip41[4]),
+	.Q5      (main_a7ddrphy_bitslip41[3]),
+	.Q6      (main_a7ddrphy_bitslip41[2]),
+	.Q7      (main_a7ddrphy_bitslip41[1]),
+	.Q8      (main_a7ddrphy_bitslip41[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_4 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_4 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay4),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed4)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay4),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed4)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_4 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_4(
-	.I(a7ddrphy_dq_o_nodelay4),
-	.T(a7ddrphy_dq_t4),
-	.IO(ddram_dq[4]),
-	.O(a7ddrphy_dq_i_nodelay4)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay4),
+	.T  (main_a7ddrphy_dq_t4),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay4),
+
+	// InOuts.
+	.IO (ddram_dq[4])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_34 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_34 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip50[0]),
-	.D2(a7ddrphy_bitslip50[1]),
-	.D3(a7ddrphy_bitslip50[2]),
-	.D4(a7ddrphy_bitslip50[3]),
-	.D5(a7ddrphy_bitslip50[4]),
-	.D6(a7ddrphy_bitslip50[5]),
-	.D7(a7ddrphy_bitslip50[6]),
-	.D8(a7ddrphy_bitslip50[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay5),
-	.TQ(a7ddrphy_dq_t5)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip50[0]),
+	.D2     (main_a7ddrphy_bitslip50[1]),
+	.D3     (main_a7ddrphy_bitslip50[2]),
+	.D4     (main_a7ddrphy_bitslip50[3]),
+	.D5     (main_a7ddrphy_bitslip50[4]),
+	.D6     (main_a7ddrphy_bitslip50[5]),
+	.D7     (main_a7ddrphy_bitslip50[6]),
+	.D8     (main_a7ddrphy_bitslip50[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay5),
+	.TQ     (main_a7ddrphy_dq_t5)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_5 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_5 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed5),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip51[7]),
-	.Q2(a7ddrphy_bitslip51[6]),
-	.Q3(a7ddrphy_bitslip51[5]),
-	.Q4(a7ddrphy_bitslip51[4]),
-	.Q5(a7ddrphy_bitslip51[3]),
-	.Q6(a7ddrphy_bitslip51[2]),
-	.Q7(a7ddrphy_bitslip51[1]),
-	.Q8(a7ddrphy_bitslip51[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed5),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip51[7]),
+	.Q2      (main_a7ddrphy_bitslip51[6]),
+	.Q3      (main_a7ddrphy_bitslip51[5]),
+	.Q4      (main_a7ddrphy_bitslip51[4]),
+	.Q5      (main_a7ddrphy_bitslip51[3]),
+	.Q6      (main_a7ddrphy_bitslip51[2]),
+	.Q7      (main_a7ddrphy_bitslip51[1]),
+	.Q8      (main_a7ddrphy_bitslip51[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_5 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_5 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay5),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed5)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay5),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed5)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_5 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_5(
-	.I(a7ddrphy_dq_o_nodelay5),
-	.T(a7ddrphy_dq_t5),
-	.IO(ddram_dq[5]),
-	.O(a7ddrphy_dq_i_nodelay5)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay5),
+	.T  (main_a7ddrphy_dq_t5),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay5),
+
+	// InOuts.
+	.IO (ddram_dq[5])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_35 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_35 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip60[0]),
-	.D2(a7ddrphy_bitslip60[1]),
-	.D3(a7ddrphy_bitslip60[2]),
-	.D4(a7ddrphy_bitslip60[3]),
-	.D5(a7ddrphy_bitslip60[4]),
-	.D6(a7ddrphy_bitslip60[5]),
-	.D7(a7ddrphy_bitslip60[6]),
-	.D8(a7ddrphy_bitslip60[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay6),
-	.TQ(a7ddrphy_dq_t6)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip60[0]),
+	.D2     (main_a7ddrphy_bitslip60[1]),
+	.D3     (main_a7ddrphy_bitslip60[2]),
+	.D4     (main_a7ddrphy_bitslip60[3]),
+	.D5     (main_a7ddrphy_bitslip60[4]),
+	.D6     (main_a7ddrphy_bitslip60[5]),
+	.D7     (main_a7ddrphy_bitslip60[6]),
+	.D8     (main_a7ddrphy_bitslip60[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay6),
+	.TQ     (main_a7ddrphy_dq_t6)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_6 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_6 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed6),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip61[7]),
-	.Q2(a7ddrphy_bitslip61[6]),
-	.Q3(a7ddrphy_bitslip61[5]),
-	.Q4(a7ddrphy_bitslip61[4]),
-	.Q5(a7ddrphy_bitslip61[3]),
-	.Q6(a7ddrphy_bitslip61[2]),
-	.Q7(a7ddrphy_bitslip61[1]),
-	.Q8(a7ddrphy_bitslip61[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed6),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip61[7]),
+	.Q2      (main_a7ddrphy_bitslip61[6]),
+	.Q3      (main_a7ddrphy_bitslip61[5]),
+	.Q4      (main_a7ddrphy_bitslip61[4]),
+	.Q5      (main_a7ddrphy_bitslip61[3]),
+	.Q6      (main_a7ddrphy_bitslip61[2]),
+	.Q7      (main_a7ddrphy_bitslip61[1]),
+	.Q8      (main_a7ddrphy_bitslip61[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_6 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_6 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay6),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed6)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay6),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed6)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_6 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_6(
-	.I(a7ddrphy_dq_o_nodelay6),
-	.T(a7ddrphy_dq_t6),
-	.IO(ddram_dq[6]),
-	.O(a7ddrphy_dq_i_nodelay6)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay6),
+	.T  (main_a7ddrphy_dq_t6),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay6),
+
+	// InOuts.
+	.IO (ddram_dq[6])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_36 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_36 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip70[0]),
-	.D2(a7ddrphy_bitslip70[1]),
-	.D3(a7ddrphy_bitslip70[2]),
-	.D4(a7ddrphy_bitslip70[3]),
-	.D5(a7ddrphy_bitslip70[4]),
-	.D6(a7ddrphy_bitslip70[5]),
-	.D7(a7ddrphy_bitslip70[6]),
-	.D8(a7ddrphy_bitslip70[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay7),
-	.TQ(a7ddrphy_dq_t7)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip70[0]),
+	.D2     (main_a7ddrphy_bitslip70[1]),
+	.D3     (main_a7ddrphy_bitslip70[2]),
+	.D4     (main_a7ddrphy_bitslip70[3]),
+	.D5     (main_a7ddrphy_bitslip70[4]),
+	.D6     (main_a7ddrphy_bitslip70[5]),
+	.D7     (main_a7ddrphy_bitslip70[6]),
+	.D8     (main_a7ddrphy_bitslip70[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay7),
+	.TQ     (main_a7ddrphy_dq_t7)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_7 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_7 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed7),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip71[7]),
-	.Q2(a7ddrphy_bitslip71[6]),
-	.Q3(a7ddrphy_bitslip71[5]),
-	.Q4(a7ddrphy_bitslip71[4]),
-	.Q5(a7ddrphy_bitslip71[3]),
-	.Q6(a7ddrphy_bitslip71[2]),
-	.Q7(a7ddrphy_bitslip71[1]),
-	.Q8(a7ddrphy_bitslip71[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed7),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip71[7]),
+	.Q2      (main_a7ddrphy_bitslip71[6]),
+	.Q3      (main_a7ddrphy_bitslip71[5]),
+	.Q4      (main_a7ddrphy_bitslip71[4]),
+	.Q5      (main_a7ddrphy_bitslip71[3]),
+	.Q6      (main_a7ddrphy_bitslip71[2]),
+	.Q7      (main_a7ddrphy_bitslip71[1]),
+	.Q8      (main_a7ddrphy_bitslip71[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_7 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_7 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay7),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed7)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay7),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed7)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_7 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_7(
-	.I(a7ddrphy_dq_o_nodelay7),
-	.T(a7ddrphy_dq_t7),
-	.IO(ddram_dq[7]),
-	.O(a7ddrphy_dq_i_nodelay7)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay7),
+	.T  (main_a7ddrphy_dq_t7),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay7),
+
+	// InOuts.
+	.IO (ddram_dq[7])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_37 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_37 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip80[0]),
-	.D2(a7ddrphy_bitslip80[1]),
-	.D3(a7ddrphy_bitslip80[2]),
-	.D4(a7ddrphy_bitslip80[3]),
-	.D5(a7ddrphy_bitslip80[4]),
-	.D6(a7ddrphy_bitslip80[5]),
-	.D7(a7ddrphy_bitslip80[6]),
-	.D8(a7ddrphy_bitslip80[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay8),
-	.TQ(a7ddrphy_dq_t8)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip80[0]),
+	.D2     (main_a7ddrphy_bitslip80[1]),
+	.D3     (main_a7ddrphy_bitslip80[2]),
+	.D4     (main_a7ddrphy_bitslip80[3]),
+	.D5     (main_a7ddrphy_bitslip80[4]),
+	.D6     (main_a7ddrphy_bitslip80[5]),
+	.D7     (main_a7ddrphy_bitslip80[6]),
+	.D8     (main_a7ddrphy_bitslip80[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay8),
+	.TQ     (main_a7ddrphy_dq_t8)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_8 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_8 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed8),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip81[7]),
-	.Q2(a7ddrphy_bitslip81[6]),
-	.Q3(a7ddrphy_bitslip81[5]),
-	.Q4(a7ddrphy_bitslip81[4]),
-	.Q5(a7ddrphy_bitslip81[3]),
-	.Q6(a7ddrphy_bitslip81[2]),
-	.Q7(a7ddrphy_bitslip81[1]),
-	.Q8(a7ddrphy_bitslip81[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed8),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip81[7]),
+	.Q2      (main_a7ddrphy_bitslip81[6]),
+	.Q3      (main_a7ddrphy_bitslip81[5]),
+	.Q4      (main_a7ddrphy_bitslip81[4]),
+	.Q5      (main_a7ddrphy_bitslip81[3]),
+	.Q6      (main_a7ddrphy_bitslip81[2]),
+	.Q7      (main_a7ddrphy_bitslip81[1]),
+	.Q8      (main_a7ddrphy_bitslip81[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_8 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_8 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay8),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed8)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay8),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed8)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_8 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_8(
-	.I(a7ddrphy_dq_o_nodelay8),
-	.T(a7ddrphy_dq_t8),
-	.IO(ddram_dq[8]),
-	.O(a7ddrphy_dq_i_nodelay8)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay8),
+	.T  (main_a7ddrphy_dq_t8),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay8),
+
+	// InOuts.
+	.IO (ddram_dq[8])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_38 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_38 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip90[0]),
-	.D2(a7ddrphy_bitslip90[1]),
-	.D3(a7ddrphy_bitslip90[2]),
-	.D4(a7ddrphy_bitslip90[3]),
-	.D5(a7ddrphy_bitslip90[4]),
-	.D6(a7ddrphy_bitslip90[5]),
-	.D7(a7ddrphy_bitslip90[6]),
-	.D8(a7ddrphy_bitslip90[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay9),
-	.TQ(a7ddrphy_dq_t9)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip90[0]),
+	.D2     (main_a7ddrphy_bitslip90[1]),
+	.D3     (main_a7ddrphy_bitslip90[2]),
+	.D4     (main_a7ddrphy_bitslip90[3]),
+	.D5     (main_a7ddrphy_bitslip90[4]),
+	.D6     (main_a7ddrphy_bitslip90[5]),
+	.D7     (main_a7ddrphy_bitslip90[6]),
+	.D8     (main_a7ddrphy_bitslip90[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay9),
+	.TQ     (main_a7ddrphy_dq_t9)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_9 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_9 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed9),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip91[7]),
-	.Q2(a7ddrphy_bitslip91[6]),
-	.Q3(a7ddrphy_bitslip91[5]),
-	.Q4(a7ddrphy_bitslip91[4]),
-	.Q5(a7ddrphy_bitslip91[3]),
-	.Q6(a7ddrphy_bitslip91[2]),
-	.Q7(a7ddrphy_bitslip91[1]),
-	.Q8(a7ddrphy_bitslip91[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed9),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip91[7]),
+	.Q2      (main_a7ddrphy_bitslip91[6]),
+	.Q3      (main_a7ddrphy_bitslip91[5]),
+	.Q4      (main_a7ddrphy_bitslip91[4]),
+	.Q5      (main_a7ddrphy_bitslip91[3]),
+	.Q6      (main_a7ddrphy_bitslip91[2]),
+	.Q7      (main_a7ddrphy_bitslip91[1]),
+	.Q8      (main_a7ddrphy_bitslip91[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_9 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_9 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay9),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed9)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay9),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed9)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_9 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_9(
-	.I(a7ddrphy_dq_o_nodelay9),
-	.T(a7ddrphy_dq_t9),
-	.IO(ddram_dq[9]),
-	.O(a7ddrphy_dq_i_nodelay9)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay9),
+	.T  (main_a7ddrphy_dq_t9),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay9),
+
+	// InOuts.
+	.IO (ddram_dq[9])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_39 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_39 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip100[0]),
-	.D2(a7ddrphy_bitslip100[1]),
-	.D3(a7ddrphy_bitslip100[2]),
-	.D4(a7ddrphy_bitslip100[3]),
-	.D5(a7ddrphy_bitslip100[4]),
-	.D6(a7ddrphy_bitslip100[5]),
-	.D7(a7ddrphy_bitslip100[6]),
-	.D8(a7ddrphy_bitslip100[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay10),
-	.TQ(a7ddrphy_dq_t10)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip100[0]),
+	.D2     (main_a7ddrphy_bitslip100[1]),
+	.D3     (main_a7ddrphy_bitslip100[2]),
+	.D4     (main_a7ddrphy_bitslip100[3]),
+	.D5     (main_a7ddrphy_bitslip100[4]),
+	.D6     (main_a7ddrphy_bitslip100[5]),
+	.D7     (main_a7ddrphy_bitslip100[6]),
+	.D8     (main_a7ddrphy_bitslip100[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay10),
+	.TQ     (main_a7ddrphy_dq_t10)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_10 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_10 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed10),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip101[7]),
-	.Q2(a7ddrphy_bitslip101[6]),
-	.Q3(a7ddrphy_bitslip101[5]),
-	.Q4(a7ddrphy_bitslip101[4]),
-	.Q5(a7ddrphy_bitslip101[3]),
-	.Q6(a7ddrphy_bitslip101[2]),
-	.Q7(a7ddrphy_bitslip101[1]),
-	.Q8(a7ddrphy_bitslip101[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed10),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip101[7]),
+	.Q2      (main_a7ddrphy_bitslip101[6]),
+	.Q3      (main_a7ddrphy_bitslip101[5]),
+	.Q4      (main_a7ddrphy_bitslip101[4]),
+	.Q5      (main_a7ddrphy_bitslip101[3]),
+	.Q6      (main_a7ddrphy_bitslip101[2]),
+	.Q7      (main_a7ddrphy_bitslip101[1]),
+	.Q8      (main_a7ddrphy_bitslip101[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_10 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_10 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay10),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed10)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay10),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed10)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_10 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_10(
-	.I(a7ddrphy_dq_o_nodelay10),
-	.T(a7ddrphy_dq_t10),
-	.IO(ddram_dq[10]),
-	.O(a7ddrphy_dq_i_nodelay10)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay10),
+	.T  (main_a7ddrphy_dq_t10),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay10),
+
+	// InOuts.
+	.IO (ddram_dq[10])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_40 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_40 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip110[0]),
-	.D2(a7ddrphy_bitslip110[1]),
-	.D3(a7ddrphy_bitslip110[2]),
-	.D4(a7ddrphy_bitslip110[3]),
-	.D5(a7ddrphy_bitslip110[4]),
-	.D6(a7ddrphy_bitslip110[5]),
-	.D7(a7ddrphy_bitslip110[6]),
-	.D8(a7ddrphy_bitslip110[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay11),
-	.TQ(a7ddrphy_dq_t11)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip110[0]),
+	.D2     (main_a7ddrphy_bitslip110[1]),
+	.D3     (main_a7ddrphy_bitslip110[2]),
+	.D4     (main_a7ddrphy_bitslip110[3]),
+	.D5     (main_a7ddrphy_bitslip110[4]),
+	.D6     (main_a7ddrphy_bitslip110[5]),
+	.D7     (main_a7ddrphy_bitslip110[6]),
+	.D8     (main_a7ddrphy_bitslip110[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay11),
+	.TQ     (main_a7ddrphy_dq_t11)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_11 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_11 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed11),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip111[7]),
-	.Q2(a7ddrphy_bitslip111[6]),
-	.Q3(a7ddrphy_bitslip111[5]),
-	.Q4(a7ddrphy_bitslip111[4]),
-	.Q5(a7ddrphy_bitslip111[3]),
-	.Q6(a7ddrphy_bitslip111[2]),
-	.Q7(a7ddrphy_bitslip111[1]),
-	.Q8(a7ddrphy_bitslip111[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed11),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip111[7]),
+	.Q2      (main_a7ddrphy_bitslip111[6]),
+	.Q3      (main_a7ddrphy_bitslip111[5]),
+	.Q4      (main_a7ddrphy_bitslip111[4]),
+	.Q5      (main_a7ddrphy_bitslip111[3]),
+	.Q6      (main_a7ddrphy_bitslip111[2]),
+	.Q7      (main_a7ddrphy_bitslip111[1]),
+	.Q8      (main_a7ddrphy_bitslip111[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_11 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_11 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay11),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed11)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay11),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed11)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_11 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_11(
-	.I(a7ddrphy_dq_o_nodelay11),
-	.T(a7ddrphy_dq_t11),
-	.IO(ddram_dq[11]),
-	.O(a7ddrphy_dq_i_nodelay11)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay11),
+	.T  (main_a7ddrphy_dq_t11),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay11),
+
+	// InOuts.
+	.IO (ddram_dq[11])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_41 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_41 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip120[0]),
-	.D2(a7ddrphy_bitslip120[1]),
-	.D3(a7ddrphy_bitslip120[2]),
-	.D4(a7ddrphy_bitslip120[3]),
-	.D5(a7ddrphy_bitslip120[4]),
-	.D6(a7ddrphy_bitslip120[5]),
-	.D7(a7ddrphy_bitslip120[6]),
-	.D8(a7ddrphy_bitslip120[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay12),
-	.TQ(a7ddrphy_dq_t12)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip120[0]),
+	.D2     (main_a7ddrphy_bitslip120[1]),
+	.D3     (main_a7ddrphy_bitslip120[2]),
+	.D4     (main_a7ddrphy_bitslip120[3]),
+	.D5     (main_a7ddrphy_bitslip120[4]),
+	.D6     (main_a7ddrphy_bitslip120[5]),
+	.D7     (main_a7ddrphy_bitslip120[6]),
+	.D8     (main_a7ddrphy_bitslip120[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay12),
+	.TQ     (main_a7ddrphy_dq_t12)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_12 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_12 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed12),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip121[7]),
-	.Q2(a7ddrphy_bitslip121[6]),
-	.Q3(a7ddrphy_bitslip121[5]),
-	.Q4(a7ddrphy_bitslip121[4]),
-	.Q5(a7ddrphy_bitslip121[3]),
-	.Q6(a7ddrphy_bitslip121[2]),
-	.Q7(a7ddrphy_bitslip121[1]),
-	.Q8(a7ddrphy_bitslip121[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed12),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip121[7]),
+	.Q2      (main_a7ddrphy_bitslip121[6]),
+	.Q3      (main_a7ddrphy_bitslip121[5]),
+	.Q4      (main_a7ddrphy_bitslip121[4]),
+	.Q5      (main_a7ddrphy_bitslip121[3]),
+	.Q6      (main_a7ddrphy_bitslip121[2]),
+	.Q7      (main_a7ddrphy_bitslip121[1]),
+	.Q8      (main_a7ddrphy_bitslip121[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_12 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_12 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay12),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed12)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay12),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed12)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_12 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_12(
-	.I(a7ddrphy_dq_o_nodelay12),
-	.T(a7ddrphy_dq_t12),
-	.IO(ddram_dq[12]),
-	.O(a7ddrphy_dq_i_nodelay12)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay12),
+	.T  (main_a7ddrphy_dq_t12),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay12),
+
+	// InOuts.
+	.IO (ddram_dq[12])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_42 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_42 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip130[0]),
-	.D2(a7ddrphy_bitslip130[1]),
-	.D3(a7ddrphy_bitslip130[2]),
-	.D4(a7ddrphy_bitslip130[3]),
-	.D5(a7ddrphy_bitslip130[4]),
-	.D6(a7ddrphy_bitslip130[5]),
-	.D7(a7ddrphy_bitslip130[6]),
-	.D8(a7ddrphy_bitslip130[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay13),
-	.TQ(a7ddrphy_dq_t13)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip130[0]),
+	.D2     (main_a7ddrphy_bitslip130[1]),
+	.D3     (main_a7ddrphy_bitslip130[2]),
+	.D4     (main_a7ddrphy_bitslip130[3]),
+	.D5     (main_a7ddrphy_bitslip130[4]),
+	.D6     (main_a7ddrphy_bitslip130[5]),
+	.D7     (main_a7ddrphy_bitslip130[6]),
+	.D8     (main_a7ddrphy_bitslip130[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay13),
+	.TQ     (main_a7ddrphy_dq_t13)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_13 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_13 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed13),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip131[7]),
-	.Q2(a7ddrphy_bitslip131[6]),
-	.Q3(a7ddrphy_bitslip131[5]),
-	.Q4(a7ddrphy_bitslip131[4]),
-	.Q5(a7ddrphy_bitslip131[3]),
-	.Q6(a7ddrphy_bitslip131[2]),
-	.Q7(a7ddrphy_bitslip131[1]),
-	.Q8(a7ddrphy_bitslip131[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed13),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip131[7]),
+	.Q2      (main_a7ddrphy_bitslip131[6]),
+	.Q3      (main_a7ddrphy_bitslip131[5]),
+	.Q4      (main_a7ddrphy_bitslip131[4]),
+	.Q5      (main_a7ddrphy_bitslip131[3]),
+	.Q6      (main_a7ddrphy_bitslip131[2]),
+	.Q7      (main_a7ddrphy_bitslip131[1]),
+	.Q8      (main_a7ddrphy_bitslip131[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_13 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_13 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay13),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed13)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay13),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed13)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_13 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_13(
-	.I(a7ddrphy_dq_o_nodelay13),
-	.T(a7ddrphy_dq_t13),
-	.IO(ddram_dq[13]),
-	.O(a7ddrphy_dq_i_nodelay13)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay13),
+	.T  (main_a7ddrphy_dq_t13),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay13),
+
+	// InOuts.
+	.IO (ddram_dq[13])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_43 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_43 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip140[0]),
-	.D2(a7ddrphy_bitslip140[1]),
-	.D3(a7ddrphy_bitslip140[2]),
-	.D4(a7ddrphy_bitslip140[3]),
-	.D5(a7ddrphy_bitslip140[4]),
-	.D6(a7ddrphy_bitslip140[5]),
-	.D7(a7ddrphy_bitslip140[6]),
-	.D8(a7ddrphy_bitslip140[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay14),
-	.TQ(a7ddrphy_dq_t14)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip140[0]),
+	.D2     (main_a7ddrphy_bitslip140[1]),
+	.D3     (main_a7ddrphy_bitslip140[2]),
+	.D4     (main_a7ddrphy_bitslip140[3]),
+	.D5     (main_a7ddrphy_bitslip140[4]),
+	.D6     (main_a7ddrphy_bitslip140[5]),
+	.D7     (main_a7ddrphy_bitslip140[6]),
+	.D8     (main_a7ddrphy_bitslip140[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay14),
+	.TQ     (main_a7ddrphy_dq_t14)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_14 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_14 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed14),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip141[7]),
-	.Q2(a7ddrphy_bitslip141[6]),
-	.Q3(a7ddrphy_bitslip141[5]),
-	.Q4(a7ddrphy_bitslip141[4]),
-	.Q5(a7ddrphy_bitslip141[3]),
-	.Q6(a7ddrphy_bitslip141[2]),
-	.Q7(a7ddrphy_bitslip141[1]),
-	.Q8(a7ddrphy_bitslip141[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed14),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip141[7]),
+	.Q2      (main_a7ddrphy_bitslip141[6]),
+	.Q3      (main_a7ddrphy_bitslip141[5]),
+	.Q4      (main_a7ddrphy_bitslip141[4]),
+	.Q5      (main_a7ddrphy_bitslip141[3]),
+	.Q6      (main_a7ddrphy_bitslip141[2]),
+	.Q7      (main_a7ddrphy_bitslip141[1]),
+	.Q8      (main_a7ddrphy_bitslip141[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_14 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_14 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay14),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed14)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay14),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed14)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_14 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_14(
-	.I(a7ddrphy_dq_o_nodelay14),
-	.T(a7ddrphy_dq_t14),
-	.IO(ddram_dq[14]),
-	.O(a7ddrphy_dq_i_nodelay14)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay14),
+	.T  (main_a7ddrphy_dq_t14),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay14),
+
+	// InOuts.
+	.IO (ddram_dq[14])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_44 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_44 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip150[0]),
-	.D2(a7ddrphy_bitslip150[1]),
-	.D3(a7ddrphy_bitslip150[2]),
-	.D4(a7ddrphy_bitslip150[3]),
-	.D5(a7ddrphy_bitslip150[4]),
-	.D6(a7ddrphy_bitslip150[5]),
-	.D7(a7ddrphy_bitslip150[6]),
-	.D8(a7ddrphy_bitslip150[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay15),
-	.TQ(a7ddrphy_dq_t15)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip150[0]),
+	.D2     (main_a7ddrphy_bitslip150[1]),
+	.D3     (main_a7ddrphy_bitslip150[2]),
+	.D4     (main_a7ddrphy_bitslip150[3]),
+	.D5     (main_a7ddrphy_bitslip150[4]),
+	.D6     (main_a7ddrphy_bitslip150[5]),
+	.D7     (main_a7ddrphy_bitslip150[6]),
+	.D8     (main_a7ddrphy_bitslip150[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay15),
+	.TQ     (main_a7ddrphy_dq_t15)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_15 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_15 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed15),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip151[7]),
-	.Q2(a7ddrphy_bitslip151[6]),
-	.Q3(a7ddrphy_bitslip151[5]),
-	.Q4(a7ddrphy_bitslip151[4]),
-	.Q5(a7ddrphy_bitslip151[3]),
-	.Q6(a7ddrphy_bitslip151[2]),
-	.Q7(a7ddrphy_bitslip151[1]),
-	.Q8(a7ddrphy_bitslip151[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed15),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip151[7]),
+	.Q2      (main_a7ddrphy_bitslip151[6]),
+	.Q3      (main_a7ddrphy_bitslip151[5]),
+	.Q4      (main_a7ddrphy_bitslip151[4]),
+	.Q5      (main_a7ddrphy_bitslip151[3]),
+	.Q6      (main_a7ddrphy_bitslip151[2]),
+	.Q7      (main_a7ddrphy_bitslip151[1]),
+	.Q8      (main_a7ddrphy_bitslip151[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_15 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_15 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay15),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed15)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay15),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed15)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_15 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_15(
-	.I(a7ddrphy_dq_o_nodelay15),
-	.T(a7ddrphy_dq_t15),
-	.IO(ddram_dq[15]),
-	.O(a7ddrphy_dq_i_nodelay15)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay15),
+	.T  (main_a7ddrphy_dq_t15),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay15),
+
+	// InOuts.
+	.IO (ddram_dq[15])
 );
 
 //------------------------------------------------------------------------------
@@ -16031,14 +17159,14 @@ IOBUF IOBUF_15(
 reg [23:0] storage[0:15];
 reg [23:0] storage_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine0_wrport_we)
-		storage[litedramcore_bankmachine0_wrport_adr] <= litedramcore_bankmachine0_wrport_dat_w;
-	storage_dat0 <= storage[litedramcore_bankmachine0_wrport_adr];
+	if (main_litedramcore_bankmachine0_wrport_we)
+		storage[main_litedramcore_bankmachine0_wrport_adr] <= main_litedramcore_bankmachine0_wrport_dat_w;
+	storage_dat0 <= storage[main_litedramcore_bankmachine0_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine0_wrport_dat_r = storage_dat0;
-assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine0_rdport_adr];
+assign main_litedramcore_bankmachine0_wrport_dat_r = storage_dat0;
+assign main_litedramcore_bankmachine0_rdport_dat_r = storage[main_litedramcore_bankmachine0_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16049,14 +17177,14 @@ assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine
 reg [23:0] storage_1[0:15];
 reg [23:0] storage_1_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine1_wrport_we)
-		storage_1[litedramcore_bankmachine1_wrport_adr] <= litedramcore_bankmachine1_wrport_dat_w;
-	storage_1_dat0 <= storage_1[litedramcore_bankmachine1_wrport_adr];
+	if (main_litedramcore_bankmachine1_wrport_we)
+		storage_1[main_litedramcore_bankmachine1_wrport_adr] <= main_litedramcore_bankmachine1_wrport_dat_w;
+	storage_1_dat0 <= storage_1[main_litedramcore_bankmachine1_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0;
-assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachine1_rdport_adr];
+assign main_litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0;
+assign main_litedramcore_bankmachine1_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16067,14 +17195,14 @@ assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachi
 reg [23:0] storage_2[0:15];
 reg [23:0] storage_2_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine2_wrport_we)
-		storage_2[litedramcore_bankmachine2_wrport_adr] <= litedramcore_bankmachine2_wrport_dat_w;
-	storage_2_dat0 <= storage_2[litedramcore_bankmachine2_wrport_adr];
+	if (main_litedramcore_bankmachine2_wrport_we)
+		storage_2[main_litedramcore_bankmachine2_wrport_adr] <= main_litedramcore_bankmachine2_wrport_dat_w;
+	storage_2_dat0 <= storage_2[main_litedramcore_bankmachine2_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0;
-assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachine2_rdport_adr];
+assign main_litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0;
+assign main_litedramcore_bankmachine2_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16085,14 +17213,14 @@ assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachi
 reg [23:0] storage_3[0:15];
 reg [23:0] storage_3_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine3_wrport_we)
-		storage_3[litedramcore_bankmachine3_wrport_adr] <= litedramcore_bankmachine3_wrport_dat_w;
-	storage_3_dat0 <= storage_3[litedramcore_bankmachine3_wrport_adr];
+	if (main_litedramcore_bankmachine3_wrport_we)
+		storage_3[main_litedramcore_bankmachine3_wrport_adr] <= main_litedramcore_bankmachine3_wrport_dat_w;
+	storage_3_dat0 <= storage_3[main_litedramcore_bankmachine3_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0;
-assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachine3_rdport_adr];
+assign main_litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0;
+assign main_litedramcore_bankmachine3_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16103,14 +17231,14 @@ assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachi
 reg [23:0] storage_4[0:15];
 reg [23:0] storage_4_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine4_wrport_we)
-		storage_4[litedramcore_bankmachine4_wrport_adr] <= litedramcore_bankmachine4_wrport_dat_w;
-	storage_4_dat0 <= storage_4[litedramcore_bankmachine4_wrport_adr];
+	if (main_litedramcore_bankmachine4_wrport_we)
+		storage_4[main_litedramcore_bankmachine4_wrport_adr] <= main_litedramcore_bankmachine4_wrport_dat_w;
+	storage_4_dat0 <= storage_4[main_litedramcore_bankmachine4_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0;
-assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachine4_rdport_adr];
+assign main_litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0;
+assign main_litedramcore_bankmachine4_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16121,14 +17249,14 @@ assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachi
 reg [23:0] storage_5[0:15];
 reg [23:0] storage_5_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine5_wrport_we)
-		storage_5[litedramcore_bankmachine5_wrport_adr] <= litedramcore_bankmachine5_wrport_dat_w;
-	storage_5_dat0 <= storage_5[litedramcore_bankmachine5_wrport_adr];
+	if (main_litedramcore_bankmachine5_wrport_we)
+		storage_5[main_litedramcore_bankmachine5_wrport_adr] <= main_litedramcore_bankmachine5_wrport_dat_w;
+	storage_5_dat0 <= storage_5[main_litedramcore_bankmachine5_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0;
-assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachine5_rdport_adr];
+assign main_litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0;
+assign main_litedramcore_bankmachine5_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16139,14 +17267,14 @@ assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachi
 reg [23:0] storage_6[0:15];
 reg [23:0] storage_6_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine6_wrport_we)
-		storage_6[litedramcore_bankmachine6_wrport_adr] <= litedramcore_bankmachine6_wrport_dat_w;
-	storage_6_dat0 <= storage_6[litedramcore_bankmachine6_wrport_adr];
+	if (main_litedramcore_bankmachine6_wrport_we)
+		storage_6[main_litedramcore_bankmachine6_wrport_adr] <= main_litedramcore_bankmachine6_wrport_dat_w;
+	storage_6_dat0 <= storage_6[main_litedramcore_bankmachine6_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0;
-assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachine6_rdport_adr];
+assign main_litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0;
+assign main_litedramcore_bankmachine6_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16157,197 +17285,308 @@ assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachi
 reg [23:0] storage_7[0:15];
 reg [23:0] storage_7_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine7_wrport_we)
-		storage_7[litedramcore_bankmachine7_wrport_adr] <= litedramcore_bankmachine7_wrport_dat_w;
-	storage_7_dat0 <= storage_7[litedramcore_bankmachine7_wrport_adr];
+	if (main_litedramcore_bankmachine7_wrport_we)
+		storage_7[main_litedramcore_bankmachine7_wrport_adr] <= main_litedramcore_bankmachine7_wrport_dat_w;
+	storage_7_dat0 <= storage_7[main_litedramcore_bankmachine7_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0;
-assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachine7_rdport_adr];
+assign main_litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0;
+assign main_litedramcore_bankmachine7_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_rdport_adr];
 
 
+//------------------------------------------------------------------------------
+// Instance FDCE of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(reset),
-	.Q(litedramcore_reset0)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (main_reset),
+
+	// Outputs.
+	.Q   (builder_reset0)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_1 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_1(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset0),
-	.Q(litedramcore_reset1)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset0),
+
+	// Outputs.
+	.Q   (builder_reset1)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_2 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_2(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset1),
-	.Q(litedramcore_reset2)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset1),
+
+	// Outputs.
+	.Q   (builder_reset2)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_3 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_3(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset2),
-	.Q(litedramcore_reset3)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset2),
+
+	// Outputs.
+	.Q   (builder_reset3)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_4 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_4(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset3),
-	.Q(litedramcore_reset4)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset3),
+
+	// Outputs.
+	.Q   (builder_reset4)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_5 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_5(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset4),
-	.Q(litedramcore_reset5)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset4),
+
+	// Outputs.
+	.Q   (builder_reset5)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_6 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_6(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset5),
-	.Q(litedramcore_reset6)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset5),
+
+	// Outputs.
+	.Q   (builder_reset6)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_7 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_7(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset6),
-	.Q(litedramcore_reset7)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset6),
+
+	// Outputs.
+	.Q   (builder_reset7)
 );
 
+//------------------------------------------------------------------------------
+// Instance PLLE2_ADV of PLLE2_ADV Module.
+//------------------------------------------------------------------------------
 PLLE2_ADV #(
-	.CLKFBOUT_MULT(5'd16),
-	.CLKIN1_PERIOD(10.0),
-	.CLKOUT0_DIVIDE(4'd8),
-	.CLKOUT0_PHASE(1'd0),
-	.CLKOUT1_DIVIDE(5'd16),
-	.CLKOUT1_PHASE(1'd0),
-	.CLKOUT2_DIVIDE(3'd4),
-	.CLKOUT2_PHASE(1'd0),
-	.CLKOUT3_DIVIDE(3'd4),
-	.CLKOUT3_PHASE(7'd90),
-	.DIVCLK_DIVIDE(1'd1),
-	.REF_JITTER1(0.01),
-	.STARTUP_WAIT("FALSE")
+	// Parameters.
+	.CLKFBOUT_MULT  (5'd16),
+	.CLKIN1_PERIOD  (10.0),
+	.CLKOUT0_DIVIDE (4'd8),
+	.CLKOUT0_PHASE  (1'd0),
+	.CLKOUT1_DIVIDE (5'd16),
+	.CLKOUT1_PHASE  (1'd0),
+	.CLKOUT2_DIVIDE (3'd4),
+	.CLKOUT2_PHASE  (1'd0),
+	.CLKOUT3_DIVIDE (3'd4),
+	.CLKOUT3_PHASE  (7'd90),
+	.DIVCLK_DIVIDE  (1'd1),
+	.REF_JITTER1    (0.01),
+	.STARTUP_WAIT   ("FALSE")
 ) PLLE2_ADV (
-	.CLKFBIN(litedramcore_pll_fb),
-	.CLKIN1(clkin),
-	.PWRDWN(power_down),
-	.RST(litedramcore_reset7),
-	.CLKFBOUT(litedramcore_pll_fb),
-	.CLKOUT0(clkout0),
-	.CLKOUT1(clkout1),
-	.CLKOUT2(clkout2),
-	.CLKOUT3(clkout3),
-	.LOCKED(locked)
+	// Inputs.
+	.CLKFBIN  (builder_pll_fb),
+	.CLKIN1   (main_clkin),
+	.PWRDWN   (main_power_down),
+	.RST      (builder_reset7),
+
+	// Outputs.
+	.CLKFBOUT (builder_pll_fb),
+	.CLKOUT0  (main_clkout0),
+	.CLKOUT1  (main_clkout1),
+	.CLKOUT2  (main_clkout2),
+	.CLKOUT3  (main_clkout3),
+	.LOCKED   (main_locked)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE (
-	.C(iodelay_clk),
-	.CE(1'd1),
-	.D(1'd0),
-	.PRE(xilinxasyncresetsynchronizerimpl0),
-	.Q(xilinxasyncresetsynchronizerimpl0_rst_meta)
+	// Inputs.
+	.C   (iodelay_clk),
+	.CE  (1'd1),
+	.D   (1'd0),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl0_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_1 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_1 (
-	.C(iodelay_clk),
-	.CE(1'd1),
-	.D(xilinxasyncresetsynchronizerimpl0_rst_meta),
-	.PRE(xilinxasyncresetsynchronizerimpl0),
-	.Q(iodelay_rst)
+	// Inputs.
+	.C   (iodelay_clk),
+	.CE  (1'd1),
+	.D   (builder_xilinxasyncresetsynchronizerimpl0_rst_meta),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset),
+
+	// Outputs.
+	.Q   (iodelay_rst)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_2 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_2 (
-	.C(sys_clk),
-	.CE(1'd1),
-	.D(1'd0),
-	.PRE(xilinxasyncresetsynchronizerimpl1),
-	.Q(xilinxasyncresetsynchronizerimpl1_rst_meta)
+	// Inputs.
+	.C   (sys_clk),
+	.CE  (1'd1),
+	.D   (1'd0),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl1_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_3 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_3 (
-	.C(sys_clk),
-	.CE(1'd1),
-	.D(xilinxasyncresetsynchronizerimpl1_rst_meta),
-	.PRE(xilinxasyncresetsynchronizerimpl1),
-	.Q(sys_rst)
+	// Inputs.
+	.C   (sys_clk),
+	.CE  (1'd1),
+	.D   (builder_xilinxasyncresetsynchronizerimpl1_rst_meta),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset),
+
+	// Outputs.
+	.Q   (sys_rst)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_4 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_4 (
-	.C(sys4x_clk),
-	.CE(1'd1),
-	.D(1'd0),
-	.PRE(xilinxasyncresetsynchronizerimpl2),
-	.Q(xilinxasyncresetsynchronizerimpl2_rst_meta)
+	// Inputs.
+	.C   (sys4x_clk),
+	.CE  (1'd1),
+	.D   (1'd0),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl2_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_5 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_5 (
-	.C(sys4x_clk),
-	.CE(1'd1),
-	.D(xilinxasyncresetsynchronizerimpl2_rst_meta),
-	.PRE(xilinxasyncresetsynchronizerimpl2),
-	.Q(xilinxasyncresetsynchronizerimpl2_expr)
+	// Inputs.
+	.C   (sys4x_clk),
+	.CE  (1'd1),
+	.D   (builder_xilinxasyncresetsynchronizerimpl2_rst_meta),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl2_expr)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_6 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_6 (
-	.C(sys4x_dqs_clk),
-	.CE(1'd1),
-	.D(1'd0),
-	.PRE(xilinxasyncresetsynchronizerimpl3),
-	.Q(xilinxasyncresetsynchronizerimpl3_rst_meta)
+	// Inputs.
+	.C   (sys4x_dqs_clk),
+	.CE  (1'd1),
+	.D   (1'd0),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl3_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_7 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_7 (
-	.C(sys4x_dqs_clk),
-	.CE(1'd1),
-	.D(xilinxasyncresetsynchronizerimpl3_rst_meta),
-	.PRE(xilinxasyncresetsynchronizerimpl3),
-	.Q(xilinxasyncresetsynchronizerimpl3_expr)
+	// Inputs.
+	.C   (sys4x_dqs_clk),
+	.CE  (1'd1),
+	.D   (builder_xilinxasyncresetsynchronizerimpl3_rst_meta),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl3_expr)
 );
 
 endmodule
 
 // -----------------------------------------------------------------------------
-//  Auto-Generated by LiteX on 2022-10-28 19:01:19.
+//  Auto-Generated by LiteX on 2024-04-01 10:12:06.
 //------------------------------------------------------------------------------
diff --git a/litedram/generated/genesys2/litedram_core.init b/litedram/generated/genesys2/litedram_core.init
index a0de849..33ac9e8 100644
--- a/litedram/generated/genesys2/litedram_core.init
+++ b/litedram/generated/genesys2/litedram_core.init
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@@ -1982,36 +2017,36 @@ e93e00007d2903a6
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@@ -2019,232 +2054,210 @@ e922803060000000
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@@ -2319,7 +2332,7 @@ ebe1fff8e8010010
 203a46464f204853
 7479622078257830
 00000000000a7365
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 0000000000000000
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@@ -2360,16 +2373,9 @@ ebe1fff8e8010010
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 000000000000207c
 00007c203a64256d
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@@ -2387,6 +2393,13 @@ ebe1fff8e8010010
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@@ -2425,6 +2438,17 @@ ebe1fff8e8010010
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 0000000042756c25
 4b756c252e756c25
 0000000000004269
diff --git a/litedram/generated/genesys2/litedram_core.v b/litedram/generated/genesys2/litedram_core.v
index 9f8030a..b6d2e37 100644
--- a/litedram/generated/genesys2/litedram_core.v
+++ b/litedram/generated/genesys2/litedram_core.v
@@ -8,10 +8,11 @@
 //
 // Filename   : litedram_core.v
 // Device     : 
-// LiteX sha1 : --------
-// Date       : 2022-10-28 19:01:21
+// LiteX sha1 : 87137c30
+// Date       : 2024-04-01 10:12:08
 //------------------------------------------------------------------------------
 
+`timescale 1ns / 1ps
 
 //------------------------------------------------------------------------------
 // Module
@@ -19,6355 +20,6945 @@
 
 module litedram_core (
     input  wire          clk,
-    input  wire          rst,
-    output wire          pll_locked,
     output wire   [14:0] ddram_a,
     output wire    [2:0] ddram_ba,
-    output wire          ddram_ras_n,
     output wire          ddram_cas_n,
-    output wire          ddram_we_n,
+    output wire          ddram_cke,
+    output wire          ddram_clk_n,
+    output wire          ddram_clk_p,
     output wire          ddram_cs_n,
     output wire    [3:0] ddram_dm,
     inout  wire   [31:0] ddram_dq,
-    inout  wire    [3:0] ddram_dqs_p,
     inout  wire    [3:0] ddram_dqs_n,
-    output wire          ddram_clk_p,
-    output wire          ddram_clk_n,
-    output wire          ddram_cke,
+    inout  wire    [3:0] ddram_dqs_p,
     output wire          ddram_odt,
+    output wire          ddram_ras_n,
     output wire          ddram_reset_n,
+    output wire          ddram_we_n,
     output wire          init_done,
     output wire          init_error,
-    input  wire   [29:0] wb_ctrl_adr,
-    input  wire   [31:0] wb_ctrl_dat_w,
-    output wire   [31:0] wb_ctrl_dat_r,
-    input  wire    [3:0] wb_ctrl_sel,
-    input  wire          wb_ctrl_cyc,
-    input  wire          wb_ctrl_stb,
-    output wire          wb_ctrl_ack,
-    input  wire          wb_ctrl_we,
-    input  wire    [2:0] wb_ctrl_cti,
-    input  wire    [1:0] wb_ctrl_bte,
-    output wire          wb_ctrl_err,
+    output wire          pll_locked,
+    input  wire          rst,
     output wire          user_clk,
-    output wire          user_rst,
-    input  wire          user_port_native_0_cmd_valid,
+    input  wire   [24:0] user_port_native_0_cmd_addr,
     output wire          user_port_native_0_cmd_ready,
+    input  wire          user_port_native_0_cmd_valid,
     input  wire          user_port_native_0_cmd_we,
-    input  wire   [24:0] user_port_native_0_cmd_addr,
-    input  wire          user_port_native_0_wdata_valid,
+    output wire  [255:0] user_port_native_0_rdata_data,
+    input  wire          user_port_native_0_rdata_ready,
+    output wire          user_port_native_0_rdata_valid,
+    input  wire  [255:0] user_port_native_0_wdata_data,
     output wire          user_port_native_0_wdata_ready,
+    input  wire          user_port_native_0_wdata_valid,
     input  wire   [31:0] user_port_native_0_wdata_we,
-    input  wire  [255:0] user_port_native_0_wdata_data,
-    output wire          user_port_native_0_rdata_valid,
-    input  wire          user_port_native_0_rdata_ready,
-    output wire  [255:0] user_port_native_0_rdata_data
+    output wire          user_rst,
+    output wire          wb_ctrl_ack,
+    input  wire   [29:0] wb_ctrl_adr,
+    input  wire    [1:0] wb_ctrl_bte,
+    input  wire    [2:0] wb_ctrl_cti,
+    input  wire          wb_ctrl_cyc,
+    output wire   [31:0] wb_ctrl_dat_r,
+    input  wire   [31:0] wb_ctrl_dat_w,
+    output wire          wb_ctrl_err,
+    input  wire    [3:0] wb_ctrl_sel,
+    input  wire          wb_ctrl_stb,
+    input  wire          wb_ctrl_we
 );
 
 
+//------------------------------------------------------------------------------
+// Hierarchy
+//------------------------------------------------------------------------------
+
+/*
+LiteDRAMCore
+└─── bus (SoCBusHandler)
+│    └─── _interconnect (InterconnectPointToPoint)
+└─── csr (SoCCSRHandler)
+└─── irq (SoCIRQHandler)
+└─── cpu (CPUNone)
+└─── crg (LiteDRAMS7DDRPHYCRG)
+│    └─── pll (S7PLL)
+│    │    └─── [FDCE]
+│    │    └─── [BUFG]
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [BUFG]
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [BUFG]
+│    │    └─── [FDCE]
+│    │    └─── [BUFG]
+│    │    └─── [PLLE2_ADV]
+│    └─── idelayctrl (S7IDELAYCTRL)
+│    │    └─── [IDELAYCTRL]
+└─── ddrphy (K7DDRPHY)
+│    └─── tappeddelayline_0* (TappedDelayLine)
+│    └─── dqspattern_0* (DQSPattern)
+│    └─── bitslip_0* (BitSlip)
+│    └─── bitslip_1* (BitSlip)
+│    └─── bitslip_2* (BitSlip)
+│    └─── bitslip_3* (BitSlip)
+│    └─── bitslip_4* (BitSlip)
+│    └─── bitslip_5* (BitSlip)
+│    └─── bitslip_6* (BitSlip)
+│    └─── bitslip_7* (BitSlip)
+│    └─── tappeddelayline_1* (TappedDelayLine)
+│    └─── bitslip_8* (BitSlip)
+│    └─── bitslip_9* (BitSlip)
+│    └─── bitslip_10* (BitSlip)
+│    └─── bitslip_11* (BitSlip)
+│    └─── bitslip_12* (BitSlip)
+│    └─── bitslip_13* (BitSlip)
+│    └─── bitslip_14* (BitSlip)
+│    └─── bitslip_15* (BitSlip)
+│    └─── bitslip_16* (BitSlip)
+│    └─── bitslip_17* (BitSlip)
+│    └─── bitslip_18* (BitSlip)
+│    └─── bitslip_19* (BitSlip)
+│    └─── bitslip_20* (BitSlip)
+│    └─── bitslip_21* (BitSlip)
+│    └─── bitslip_22* (BitSlip)
+│    └─── bitslip_23* (BitSlip)
+│    └─── bitslip_24* (BitSlip)
+│    └─── bitslip_25* (BitSlip)
+│    └─── bitslip_26* (BitSlip)
+│    └─── bitslip_27* (BitSlip)
+│    └─── bitslip_28* (BitSlip)
+│    └─── bitslip_29* (BitSlip)
+│    └─── bitslip_30* (BitSlip)
+│    └─── bitslip_31* (BitSlip)
+│    └─── bitslip_32* (BitSlip)
+│    └─── bitslip_33* (BitSlip)
+│    └─── bitslip_34* (BitSlip)
+│    └─── bitslip_35* (BitSlip)
+│    └─── bitslip_36* (BitSlip)
+│    └─── bitslip_37* (BitSlip)
+│    └─── bitslip_38* (BitSlip)
+│    └─── bitslip_39* (BitSlip)
+│    └─── bitslip_40* (BitSlip)
+│    └─── bitslip_41* (BitSlip)
+│    └─── bitslip_42* (BitSlip)
+│    └─── bitslip_43* (BitSlip)
+│    └─── bitslip_44* (BitSlip)
+│    └─── bitslip_45* (BitSlip)
+│    └─── bitslip_46* (BitSlip)
+│    └─── bitslip_47* (BitSlip)
+│    └─── bitslip_48* (BitSlip)
+│    └─── bitslip_49* (BitSlip)
+│    └─── bitslip_50* (BitSlip)
+│    └─── bitslip_51* (BitSlip)
+│    └─── bitslip_52* (BitSlip)
+│    └─── bitslip_53* (BitSlip)
+│    └─── bitslip_54* (BitSlip)
+│    └─── bitslip_55* (BitSlip)
+│    └─── bitslip_56* (BitSlip)
+│    └─── bitslip_57* (BitSlip)
+│    └─── bitslip_58* (BitSlip)
+│    └─── bitslip_59* (BitSlip)
+│    └─── bitslip_60* (BitSlip)
+│    └─── bitslip_61* (BitSlip)
+│    └─── bitslip_62* (BitSlip)
+│    └─── bitslip_63* (BitSlip)
+│    └─── bitslip_64* (BitSlip)
+│    └─── bitslip_65* (BitSlip)
+│    └─── bitslip_66* (BitSlip)
+│    └─── bitslip_67* (BitSlip)
+│    └─── bitslip_68* (BitSlip)
+│    └─── bitslip_69* (BitSlip)
+│    └─── bitslip_70* (BitSlip)
+│    └─── bitslip_71* (BitSlip)
+│    └─── tappeddelayline_2* (TappedDelayLine)
+│    └─── tappeddelayline_3* (TappedDelayLine)
+│    └─── [ODELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [IDELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [IDELAYE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [ODELAYE2]
+│    └─── [IOBUF]
+│    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IOBUFDS]
+│    └─── [IDELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [IDELAYE2]
+│    └─── [IDELAYE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [IDELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [IOBUF]
+│    └─── [IOBUF]
+│    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [ODELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [IOBUF]
+│    └─── [ISERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [IOBUF]
+│    └─── [ODELAYE2]
+│    └─── [IDELAYE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [ODELAYE2]
+│    └─── [IOBUF]
+│    └─── [IOBUFDS]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [OBUFDS]
+│    └─── [ODELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [IOBUF]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUFDS]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [ODELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [ISERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [ODELAYE2]
+│    └─── [IOBUF]
+│    └─── [IDELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [ODELAYE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUFDS]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+└─── sdram (LiteDRAMCore)
+│    └─── dfii (DFIInjector)
+│    │    └─── pi0 (PhaseInjector)
+│    │    └─── pi1 (PhaseInjector)
+│    │    └─── pi2 (PhaseInjector)
+│    │    └─── pi3 (PhaseInjector)
+│    └─── controller (LiteDRAMController)
+│    │    └─── refresher (Refresher)
+│    │    │    └─── timer (RefreshTimer)
+│    │    │    └─── postponer (RefreshPostponer)
+│    │    │    └─── sequencer (RefreshSequencer)
+│    │    │    │    └─── refreshexecuter_0* (RefreshExecuter)
+│    │    │    └─── zqcs_timer (RefreshTimer)
+│    │    │    └─── zqs_executer (ZQCSExecuter)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_0* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_1* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_2* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_3* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_4* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_5* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_6* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_7* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── multiplexer (Multiplexer)
+│    │    │    └─── choose_cmd (_CommandChooser)
+│    │    │    │    └─── roundrobin_0* (RoundRobin)
+│    │    │    └─── choose_req (_CommandChooser)
+│    │    │    │    └─── roundrobin_0* (RoundRobin)
+│    │    │    └─── _steerer_0* (_Steerer)
+│    │    │    └─── trrdcon (tXXDController)
+│    │    │    └─── tfawcon (tFAWController)
+│    │    │    └─── tccdcon (tXXDController)
+│    │    │    └─── twtrcon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    └─── crossbar (LiteDRAMCrossbar)
+│    │    └─── roundrobin_0* (RoundRobin)
+│    │    └─── roundrobin_1* (RoundRobin)
+│    │    └─── roundrobin_2* (RoundRobin)
+│    │    └─── roundrobin_3* (RoundRobin)
+│    │    └─── roundrobin_4* (RoundRobin)
+│    │    └─── roundrobin_5* (RoundRobin)
+│    │    └─── roundrobin_6* (RoundRobin)
+│    │    └─── roundrobin_7* (RoundRobin)
+└─── ddrctrl (LiteDRAMCoreControl)
+└─── csr_bridge (Wishbone2CSR)
+│    └─── fsm (FSM)
+└─── csr_bankarray (CSRBankArray)
+│    └─── csrbank_0* (CSRBank)
+│    │    └─── csrstorage_0* (CSRStorage)
+│    │    └─── csrstorage_1* (CSRStorage)
+│    └─── csrbank_1* (CSRBank)
+│    │    └─── csrstorage_0* (CSRStorage)
+│    │    └─── csrstorage_1* (CSRStorage)
+│    │    └─── csrstorage_2* (CSRStorage)
+│    │    └─── csrstorage_3* (CSRStorage)
+│    │    └─── csrstorage_4* (CSRStorage)
+│    │    └─── csrstorage_5* (CSRStorage)
+│    └─── csrbank_2* (CSRBank)
+│    │    └─── csrstorage_0* (CSRStorage)
+│    │    └─── csrstorage_1* (CSRStorage)
+│    │    └─── csrstorage_2* (CSRStorage)
+│    │    └─── csrstorage_3* (CSRStorage)
+│    │    └─── csrstorage_4* (CSRStorage)
+│    │    └─── csrstatus_0* (CSRStatus)
+│    │    └─── csrstorage_5* (CSRStorage)
+│    │    └─── csrstorage_6* (CSRStorage)
+│    │    └─── csrstorage_7* (CSRStorage)
+│    │    └─── csrstorage_8* (CSRStorage)
+│    │    └─── csrstatus_1* (CSRStatus)
+│    │    └─── csrstorage_9* (CSRStorage)
+│    │    └─── csrstorage_10* (CSRStorage)
+│    │    └─── csrstorage_11* (CSRStorage)
+│    │    └─── csrstorage_12* (CSRStorage)
+│    │    └─── csrstatus_2* (CSRStatus)
+│    │    └─── csrstorage_13* (CSRStorage)
+│    │    └─── csrstorage_14* (CSRStorage)
+│    │    └─── csrstorage_15* (CSRStorage)
+│    │    └─── csrstorage_16* (CSRStorage)
+│    │    └─── csrstatus_3* (CSRStatus)
+└─── csr_interconnect (InterconnectShared)
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+* : Generated name.
+[]: BlackBox.
+*/
+
 //------------------------------------------------------------------------------
 // Signals
 //------------------------------------------------------------------------------
 
-reg           rst_1 = 1'd0;
-wire          sys_clk;
-wire          sys_rst;
-wire          sys4x_clk;
-wire          sys4x_dqs_clk;
+wire   [13:0] builder_adr;
+reg     [3:0] builder_bankmachine0_next_state = 4'd0;
+reg     [3:0] builder_bankmachine0_state = 4'd0;
+reg     [3:0] builder_bankmachine1_next_state = 4'd0;
+reg     [3:0] builder_bankmachine1_state = 4'd0;
+reg     [3:0] builder_bankmachine2_next_state = 4'd0;
+reg     [3:0] builder_bankmachine2_state = 4'd0;
+reg     [3:0] builder_bankmachine3_next_state = 4'd0;
+reg     [3:0] builder_bankmachine3_state = 4'd0;
+reg     [3:0] builder_bankmachine4_next_state = 4'd0;
+reg     [3:0] builder_bankmachine4_state = 4'd0;
+reg     [3:0] builder_bankmachine5_next_state = 4'd0;
+reg     [3:0] builder_bankmachine5_state = 4'd0;
+reg     [3:0] builder_bankmachine6_next_state = 4'd0;
+reg     [3:0] builder_bankmachine6_state = 4'd0;
+reg     [3:0] builder_bankmachine7_next_state = 4'd0;
+reg     [3:0] builder_bankmachine7_state = 4'd0;
+wire          builder_csrbank0_init_done0_r;
+reg           builder_csrbank0_init_done0_re = 1'd0;
+wire          builder_csrbank0_init_done0_w;
+reg           builder_csrbank0_init_done0_we = 1'd0;
+wire          builder_csrbank0_init_error0_r;
+reg           builder_csrbank0_init_error0_re = 1'd0;
+wire          builder_csrbank0_init_error0_w;
+reg           builder_csrbank0_init_error0_we = 1'd0;
+wire          builder_csrbank0_sel;
+wire    [3:0] builder_csrbank1_dly_sel0_r;
+reg           builder_csrbank1_dly_sel0_re = 1'd0;
+wire    [3:0] builder_csrbank1_dly_sel0_w;
+reg           builder_csrbank1_dly_sel0_we = 1'd0;
+wire    [4:0] builder_csrbank1_half_sys8x_taps0_r;
+reg           builder_csrbank1_half_sys8x_taps0_re = 1'd0;
+wire    [4:0] builder_csrbank1_half_sys8x_taps0_w;
+reg           builder_csrbank1_half_sys8x_taps0_we = 1'd0;
+wire    [1:0] builder_csrbank1_rdphase0_r;
+reg           builder_csrbank1_rdphase0_re = 1'd0;
+wire    [1:0] builder_csrbank1_rdphase0_w;
+reg           builder_csrbank1_rdphase0_we = 1'd0;
+wire          builder_csrbank1_rst0_r;
+reg           builder_csrbank1_rst0_re = 1'd0;
+wire          builder_csrbank1_rst0_w;
+reg           builder_csrbank1_rst0_we = 1'd0;
+wire          builder_csrbank1_sel;
+wire          builder_csrbank1_wlevel_en0_r;
+reg           builder_csrbank1_wlevel_en0_re = 1'd0;
+wire          builder_csrbank1_wlevel_en0_w;
+reg           builder_csrbank1_wlevel_en0_we = 1'd0;
+wire    [1:0] builder_csrbank1_wrphase0_r;
+reg           builder_csrbank1_wrphase0_re = 1'd0;
+wire    [1:0] builder_csrbank1_wrphase0_w;
+reg           builder_csrbank1_wrphase0_we = 1'd0;
+wire    [3:0] builder_csrbank2_dfii_control0_r;
+reg           builder_csrbank2_dfii_control0_re = 1'd0;
+wire    [3:0] builder_csrbank2_dfii_control0_w;
+reg           builder_csrbank2_dfii_control0_we = 1'd0;
+wire   [14:0] builder_csrbank2_dfii_pi0_address0_r;
+reg           builder_csrbank2_dfii_pi0_address0_re = 1'd0;
+wire   [14:0] builder_csrbank2_dfii_pi0_address0_w;
+reg           builder_csrbank2_dfii_pi0_address0_we = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi0_baddress0_r;
+reg           builder_csrbank2_dfii_pi0_baddress0_re = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi0_baddress0_w;
+reg           builder_csrbank2_dfii_pi0_baddress0_we = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi0_command0_r;
+reg           builder_csrbank2_dfii_pi0_command0_re = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi0_command0_w;
+reg           builder_csrbank2_dfii_pi0_command0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi0_rddata0_r;
+reg           builder_csrbank2_dfii_pi0_rddata0_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi0_rddata0_w;
+reg           builder_csrbank2_dfii_pi0_rddata0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi0_rddata1_r;
+reg           builder_csrbank2_dfii_pi0_rddata1_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi0_rddata1_w;
+reg           builder_csrbank2_dfii_pi0_rddata1_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi0_wrdata0_r;
+reg           builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi0_wrdata0_w;
+reg           builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi0_wrdata1_r;
+reg           builder_csrbank2_dfii_pi0_wrdata1_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi0_wrdata1_w;
+reg           builder_csrbank2_dfii_pi0_wrdata1_we = 1'd0;
+wire   [14:0] builder_csrbank2_dfii_pi1_address0_r;
+reg           builder_csrbank2_dfii_pi1_address0_re = 1'd0;
+wire   [14:0] builder_csrbank2_dfii_pi1_address0_w;
+reg           builder_csrbank2_dfii_pi1_address0_we = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi1_baddress0_r;
+reg           builder_csrbank2_dfii_pi1_baddress0_re = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi1_baddress0_w;
+reg           builder_csrbank2_dfii_pi1_baddress0_we = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi1_command0_r;
+reg           builder_csrbank2_dfii_pi1_command0_re = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi1_command0_w;
+reg           builder_csrbank2_dfii_pi1_command0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi1_rddata0_r;
+reg           builder_csrbank2_dfii_pi1_rddata0_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi1_rddata0_w;
+reg           builder_csrbank2_dfii_pi1_rddata0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi1_rddata1_r;
+reg           builder_csrbank2_dfii_pi1_rddata1_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi1_rddata1_w;
+reg           builder_csrbank2_dfii_pi1_rddata1_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi1_wrdata0_r;
+reg           builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi1_wrdata0_w;
+reg           builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi1_wrdata1_r;
+reg           builder_csrbank2_dfii_pi1_wrdata1_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi1_wrdata1_w;
+reg           builder_csrbank2_dfii_pi1_wrdata1_we = 1'd0;
+wire   [14:0] builder_csrbank2_dfii_pi2_address0_r;
+reg           builder_csrbank2_dfii_pi2_address0_re = 1'd0;
+wire   [14:0] builder_csrbank2_dfii_pi2_address0_w;
+reg           builder_csrbank2_dfii_pi2_address0_we = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi2_baddress0_r;
+reg           builder_csrbank2_dfii_pi2_baddress0_re = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi2_baddress0_w;
+reg           builder_csrbank2_dfii_pi2_baddress0_we = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi2_command0_r;
+reg           builder_csrbank2_dfii_pi2_command0_re = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi2_command0_w;
+reg           builder_csrbank2_dfii_pi2_command0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi2_rddata0_r;
+reg           builder_csrbank2_dfii_pi2_rddata0_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi2_rddata0_w;
+reg           builder_csrbank2_dfii_pi2_rddata0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi2_rddata1_r;
+reg           builder_csrbank2_dfii_pi2_rddata1_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi2_rddata1_w;
+reg           builder_csrbank2_dfii_pi2_rddata1_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi2_wrdata0_r;
+reg           builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi2_wrdata0_w;
+reg           builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi2_wrdata1_r;
+reg           builder_csrbank2_dfii_pi2_wrdata1_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi2_wrdata1_w;
+reg           builder_csrbank2_dfii_pi2_wrdata1_we = 1'd0;
+wire   [14:0] builder_csrbank2_dfii_pi3_address0_r;
+reg           builder_csrbank2_dfii_pi3_address0_re = 1'd0;
+wire   [14:0] builder_csrbank2_dfii_pi3_address0_w;
+reg           builder_csrbank2_dfii_pi3_address0_we = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi3_baddress0_r;
+reg           builder_csrbank2_dfii_pi3_baddress0_re = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi3_baddress0_w;
+reg           builder_csrbank2_dfii_pi3_baddress0_we = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi3_command0_r;
+reg           builder_csrbank2_dfii_pi3_command0_re = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi3_command0_w;
+reg           builder_csrbank2_dfii_pi3_command0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi3_rddata0_r;
+reg           builder_csrbank2_dfii_pi3_rddata0_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi3_rddata0_w;
+reg           builder_csrbank2_dfii_pi3_rddata0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi3_rddata1_r;
+reg           builder_csrbank2_dfii_pi3_rddata1_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi3_rddata1_w;
+reg           builder_csrbank2_dfii_pi3_rddata1_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi3_wrdata0_r;
+reg           builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi3_wrdata0_w;
+reg           builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi3_wrdata1_r;
+reg           builder_csrbank2_dfii_pi3_wrdata1_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi3_wrdata1_w;
+reg           builder_csrbank2_dfii_pi3_wrdata1_we = 1'd0;
+wire          builder_csrbank2_sel;
+wire   [31:0] builder_dat_r;
+wire   [31:0] builder_dat_w;
+reg           builder_interface0_ack = 1'd0;
+wire   [29:0] builder_interface0_adr;
+wire   [13:0] builder_interface0_bank_bus_adr;
+reg    [31:0] builder_interface0_bank_bus_dat_r = 32'd0;
+wire   [31:0] builder_interface0_bank_bus_dat_w;
+wire          builder_interface0_bank_bus_we;
+wire    [1:0] builder_interface0_bte;
+wire    [2:0] builder_interface0_cti;
+wire          builder_interface0_cyc;
+reg    [31:0] builder_interface0_dat_r = 32'd0;
+wire   [31:0] builder_interface0_dat_w;
+reg           builder_interface0_err = 1'd0;
+wire    [3:0] builder_interface0_sel;
+wire          builder_interface0_stb;
+wire          builder_interface0_we;
+reg    [13:0] builder_interface1_adr = 14'd0;
+reg    [13:0] builder_interface1_adr_next_value1 = 14'd0;
+reg           builder_interface1_adr_next_value_ce1 = 1'd0;
+wire   [13:0] builder_interface1_bank_bus_adr;
+reg    [31:0] builder_interface1_bank_bus_dat_r = 32'd0;
+wire   [31:0] builder_interface1_bank_bus_dat_w;
+wire          builder_interface1_bank_bus_we;
+wire   [31:0] builder_interface1_dat_r;
+reg    [31:0] builder_interface1_dat_w = 32'd0;
+reg    [31:0] builder_interface1_dat_w_next_value0 = 32'd0;
+reg           builder_interface1_dat_w_next_value_ce0 = 1'd0;
+reg           builder_interface1_we = 1'd0;
+reg           builder_interface1_we_next_value2 = 1'd0;
+reg           builder_interface1_we_next_value_ce2 = 1'd0;
+wire   [13:0] builder_interface2_bank_bus_adr;
+reg    [31:0] builder_interface2_bank_bus_dat_r = 32'd0;
+wire   [31:0] builder_interface2_bank_bus_dat_w;
+wire          builder_interface2_bank_bus_we;
+reg           builder_locked0 = 1'd0;
+reg           builder_locked1 = 1'd0;
+reg           builder_locked2 = 1'd0;
+reg           builder_locked3 = 1'd0;
+reg           builder_locked4 = 1'd0;
+reg           builder_locked5 = 1'd0;
+reg           builder_locked6 = 1'd0;
+reg           builder_locked7 = 1'd0;
+reg     [3:0] builder_multiplexer_next_state = 4'd0;
+reg     [3:0] builder_multiplexer_state = 4'd0;
+reg           builder_new_master_rdata_valid0 = 1'd0;
+reg           builder_new_master_rdata_valid1 = 1'd0;
+reg           builder_new_master_rdata_valid2 = 1'd0;
+reg           builder_new_master_rdata_valid3 = 1'd0;
+reg           builder_new_master_rdata_valid4 = 1'd0;
+reg           builder_new_master_rdata_valid5 = 1'd0;
+reg           builder_new_master_rdata_valid6 = 1'd0;
+reg           builder_new_master_rdata_valid7 = 1'd0;
+reg           builder_new_master_rdata_valid8 = 1'd0;
+reg           builder_new_master_wdata_ready0 = 1'd0;
+reg           builder_new_master_wdata_ready1 = 1'd0;
+reg     [1:0] builder_next_state = 2'd0;
+wire          builder_pll_fb;
+reg     [1:0] builder_refresher_next_state = 2'd0;
+reg     [1:0] builder_refresher_state = 2'd0;
+wire          builder_reset0;
+wire          builder_reset1;
+wire          builder_reset2;
+wire          builder_reset3;
+wire          builder_reset4;
+wire          builder_reset5;
+wire          builder_reset6;
+wire          builder_reset7;
+reg           builder_rhs_self0 = 1'd0;
+reg    [14:0] builder_rhs_self1 = 15'd0;
+reg           builder_rhs_self10 = 1'd0;
+reg           builder_rhs_self11 = 1'd0;
+reg    [21:0] builder_rhs_self12 = 22'd0;
+reg           builder_rhs_self13 = 1'd0;
+reg           builder_rhs_self14 = 1'd0;
+reg    [21:0] builder_rhs_self15 = 22'd0;
+reg           builder_rhs_self16 = 1'd0;
+reg           builder_rhs_self17 = 1'd0;
+reg    [21:0] builder_rhs_self18 = 22'd0;
+reg           builder_rhs_self19 = 1'd0;
+reg     [2:0] builder_rhs_self2 = 3'd0;
+reg           builder_rhs_self20 = 1'd0;
+reg    [21:0] builder_rhs_self21 = 22'd0;
+reg           builder_rhs_self22 = 1'd0;
+reg           builder_rhs_self23 = 1'd0;
+reg    [21:0] builder_rhs_self24 = 22'd0;
+reg           builder_rhs_self25 = 1'd0;
+reg           builder_rhs_self26 = 1'd0;
+reg    [21:0] builder_rhs_self27 = 22'd0;
+reg           builder_rhs_self28 = 1'd0;
+reg           builder_rhs_self29 = 1'd0;
+reg           builder_rhs_self3 = 1'd0;
+reg    [21:0] builder_rhs_self30 = 22'd0;
+reg           builder_rhs_self31 = 1'd0;
+reg           builder_rhs_self32 = 1'd0;
+reg    [21:0] builder_rhs_self33 = 22'd0;
+reg           builder_rhs_self34 = 1'd0;
+reg           builder_rhs_self35 = 1'd0;
+reg           builder_rhs_self4 = 1'd0;
+reg           builder_rhs_self5 = 1'd0;
+reg           builder_rhs_self6 = 1'd0;
+reg    [14:0] builder_rhs_self7 = 15'd0;
+reg     [2:0] builder_rhs_self8 = 3'd0;
+reg           builder_rhs_self9 = 1'd0;
+wire          builder_roundrobin0_ce;
+wire          builder_roundrobin0_grant;
+wire          builder_roundrobin0_request;
+wire          builder_roundrobin1_ce;
+wire          builder_roundrobin1_grant;
+wire          builder_roundrobin1_request;
+wire          builder_roundrobin2_ce;
+wire          builder_roundrobin2_grant;
+wire          builder_roundrobin2_request;
+wire          builder_roundrobin3_ce;
+wire          builder_roundrobin3_grant;
+wire          builder_roundrobin3_request;
+wire          builder_roundrobin4_ce;
+wire          builder_roundrobin4_grant;
+wire          builder_roundrobin4_request;
+wire          builder_roundrobin5_ce;
+wire          builder_roundrobin5_grant;
+wire          builder_roundrobin5_request;
+wire          builder_roundrobin6_ce;
+wire          builder_roundrobin6_grant;
+wire          builder_roundrobin6_request;
+wire          builder_roundrobin7_ce;
+wire          builder_roundrobin7_grant;
+wire          builder_roundrobin7_request;
+reg     [2:0] builder_self0 = 3'd0;
+reg    [14:0] builder_self1 = 15'd0;
+reg           builder_self10 = 1'd0;
+reg           builder_self11 = 1'd0;
+reg           builder_self12 = 1'd0;
+reg           builder_self13 = 1'd0;
+reg     [2:0] builder_self14 = 3'd0;
+reg    [14:0] builder_self15 = 15'd0;
+reg           builder_self16 = 1'd0;
+reg           builder_self17 = 1'd0;
+reg           builder_self18 = 1'd0;
+reg           builder_self19 = 1'd0;
+reg           builder_self2 = 1'd0;
+reg           builder_self20 = 1'd0;
+reg     [2:0] builder_self21 = 3'd0;
+reg    [14:0] builder_self22 = 15'd0;
+reg           builder_self23 = 1'd0;
+reg           builder_self24 = 1'd0;
+reg           builder_self25 = 1'd0;
+reg           builder_self26 = 1'd0;
+reg           builder_self27 = 1'd0;
+reg           builder_self3 = 1'd0;
+reg           builder_self4 = 1'd0;
+reg           builder_self5 = 1'd0;
+reg           builder_self6 = 1'd0;
+reg     [2:0] builder_self7 = 3'd0;
+reg    [14:0] builder_self8 = 15'd0;
+reg           builder_self9 = 1'd0;
+reg     [1:0] builder_state = 2'd0;
+reg           builder_t_self0 = 1'd0;
+reg           builder_t_self1 = 1'd0;
+reg           builder_t_self2 = 1'd0;
+reg           builder_t_self3 = 1'd0;
+reg           builder_t_self4 = 1'd0;
+reg           builder_t_self5 = 1'd0;
+wire          builder_we;
+wire          builder_xilinxasyncresetsynchronizerimpl0_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl0_rst_meta;
+wire          builder_xilinxasyncresetsynchronizerimpl1_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl1_rst_meta;
+wire          builder_xilinxasyncresetsynchronizerimpl2_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl2_expr;
+wire          builder_xilinxasyncresetsynchronizerimpl2_rst_meta;
+wire          builder_xilinxasyncresetsynchronizerimpl3_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl3_expr;
+wire          builder_xilinxasyncresetsynchronizerimpl3_rst_meta;
 wire          iodelay_clk;
 wire          iodelay_rst;
-wire          reset;
-reg           power_down = 1'd0;
-wire          locked;
-wire          clkin;
-wire          clkout0;
-wire          clkout_buf0;
-wire          clkout1;
-wire          clkout_buf1;
-wire          clkout2;
-wire          clkout_buf2;
-wire          clkout3;
-wire          clkout_buf3;
-reg     [3:0] reset_counter = 4'd15;
-reg           ic_reset = 1'd1;
-reg           k7ddrphy_rst_storage = 1'd0;
-reg           k7ddrphy_rst_re = 1'd0;
-reg     [3:0] k7ddrphy_dly_sel_storage = 4'd0;
-reg           k7ddrphy_dly_sel_re = 1'd0;
-reg     [4:0] k7ddrphy_half_sys8x_taps_storage = 5'd8;
-reg           k7ddrphy_half_sys8x_taps_re = 1'd0;
-reg           k7ddrphy_wlevel_en_storage = 1'd0;
-reg           k7ddrphy_wlevel_en_re = 1'd0;
-reg           k7ddrphy_wlevel_strobe_re = 1'd0;
-wire          k7ddrphy_wlevel_strobe_r;
-reg           k7ddrphy_wlevel_strobe_we = 1'd0;
-reg           k7ddrphy_wlevel_strobe_w = 1'd0;
-reg           k7ddrphy_cdly_rst_re = 1'd0;
-wire          k7ddrphy_cdly_rst_r;
-reg           k7ddrphy_cdly_rst_we = 1'd0;
-reg           k7ddrphy_cdly_rst_w = 1'd0;
-reg           k7ddrphy_cdly_inc_re = 1'd0;
-wire          k7ddrphy_cdly_inc_r;
-reg           k7ddrphy_cdly_inc_we = 1'd0;
-reg           k7ddrphy_cdly_inc_w = 1'd0;
-reg           k7ddrphy_rdly_dq_rst_re = 1'd0;
-wire          k7ddrphy_rdly_dq_rst_r;
-reg           k7ddrphy_rdly_dq_rst_we = 1'd0;
-reg           k7ddrphy_rdly_dq_rst_w = 1'd0;
-reg           k7ddrphy_rdly_dq_inc_re = 1'd0;
-wire          k7ddrphy_rdly_dq_inc_r;
-reg           k7ddrphy_rdly_dq_inc_we = 1'd0;
-reg           k7ddrphy_rdly_dq_inc_w = 1'd0;
-reg           k7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
-wire          k7ddrphy_rdly_dq_bitslip_rst_r;
-reg           k7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
-reg           k7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-reg           k7ddrphy_rdly_dq_bitslip_re = 1'd0;
-wire          k7ddrphy_rdly_dq_bitslip_r;
-reg           k7ddrphy_rdly_dq_bitslip_we = 1'd0;
-reg           k7ddrphy_rdly_dq_bitslip_w = 1'd0;
-reg           k7ddrphy_wdly_dq_rst_re = 1'd0;
-wire          k7ddrphy_wdly_dq_rst_r;
-reg           k7ddrphy_wdly_dq_rst_we = 1'd0;
-reg           k7ddrphy_wdly_dq_rst_w = 1'd0;
-reg           k7ddrphy_wdly_dq_inc_re = 1'd0;
-wire          k7ddrphy_wdly_dq_inc_r;
-reg           k7ddrphy_wdly_dq_inc_we = 1'd0;
-reg           k7ddrphy_wdly_dq_inc_w = 1'd0;
-reg           k7ddrphy_wdly_dqs_rst_re = 1'd0;
-wire          k7ddrphy_wdly_dqs_rst_r;
-reg           k7ddrphy_wdly_dqs_rst_we = 1'd0;
-reg           k7ddrphy_wdly_dqs_rst_w = 1'd0;
-reg           k7ddrphy_wdly_dqs_inc_re = 1'd0;
-wire          k7ddrphy_wdly_dqs_inc_r;
-reg           k7ddrphy_wdly_dqs_inc_we = 1'd0;
-reg           k7ddrphy_wdly_dqs_inc_w = 1'd0;
-reg           k7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
-wire          k7ddrphy_wdly_dq_bitslip_rst_r;
-reg           k7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
-reg           k7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
-reg           k7ddrphy_wdly_dq_bitslip_re = 1'd0;
-wire          k7ddrphy_wdly_dq_bitslip_r;
-reg           k7ddrphy_wdly_dq_bitslip_we = 1'd0;
-reg           k7ddrphy_wdly_dq_bitslip_w = 1'd0;
-reg     [1:0] k7ddrphy_rdphase_storage = 2'd1;
-reg           k7ddrphy_rdphase_re = 1'd0;
-reg     [1:0] k7ddrphy_wrphase_storage = 2'd2;
-reg           k7ddrphy_wrphase_re = 1'd0;
-wire   [14:0] k7ddrphy_dfi_p0_address;
-wire    [2:0] k7ddrphy_dfi_p0_bank;
-wire          k7ddrphy_dfi_p0_cas_n;
-wire          k7ddrphy_dfi_p0_cs_n;
-wire          k7ddrphy_dfi_p0_ras_n;
-wire          k7ddrphy_dfi_p0_we_n;
-wire          k7ddrphy_dfi_p0_cke;
-wire          k7ddrphy_dfi_p0_odt;
-wire          k7ddrphy_dfi_p0_reset_n;
-wire          k7ddrphy_dfi_p0_act_n;
-wire   [63:0] k7ddrphy_dfi_p0_wrdata;
-wire          k7ddrphy_dfi_p0_wrdata_en;
-wire    [7:0] k7ddrphy_dfi_p0_wrdata_mask;
-wire          k7ddrphy_dfi_p0_rddata_en;
-reg    [63:0] k7ddrphy_dfi_p0_rddata = 64'd0;
-wire          k7ddrphy_dfi_p0_rddata_valid;
-wire   [14:0] k7ddrphy_dfi_p1_address;
-wire    [2:0] k7ddrphy_dfi_p1_bank;
-wire          k7ddrphy_dfi_p1_cas_n;
-wire          k7ddrphy_dfi_p1_cs_n;
-wire          k7ddrphy_dfi_p1_ras_n;
-wire          k7ddrphy_dfi_p1_we_n;
-wire          k7ddrphy_dfi_p1_cke;
-wire          k7ddrphy_dfi_p1_odt;
-wire          k7ddrphy_dfi_p1_reset_n;
-wire          k7ddrphy_dfi_p1_act_n;
-wire   [63:0] k7ddrphy_dfi_p1_wrdata;
-wire          k7ddrphy_dfi_p1_wrdata_en;
-wire    [7:0] k7ddrphy_dfi_p1_wrdata_mask;
-wire          k7ddrphy_dfi_p1_rddata_en;
-reg    [63:0] k7ddrphy_dfi_p1_rddata = 64'd0;
-wire          k7ddrphy_dfi_p1_rddata_valid;
-wire   [14:0] k7ddrphy_dfi_p2_address;
-wire    [2:0] k7ddrphy_dfi_p2_bank;
-wire          k7ddrphy_dfi_p2_cas_n;
-wire          k7ddrphy_dfi_p2_cs_n;
-wire          k7ddrphy_dfi_p2_ras_n;
-wire          k7ddrphy_dfi_p2_we_n;
-wire          k7ddrphy_dfi_p2_cke;
-wire          k7ddrphy_dfi_p2_odt;
-wire          k7ddrphy_dfi_p2_reset_n;
-wire          k7ddrphy_dfi_p2_act_n;
-wire   [63:0] k7ddrphy_dfi_p2_wrdata;
-wire          k7ddrphy_dfi_p2_wrdata_en;
-wire    [7:0] k7ddrphy_dfi_p2_wrdata_mask;
-wire          k7ddrphy_dfi_p2_rddata_en;
-reg    [63:0] k7ddrphy_dfi_p2_rddata = 64'd0;
-wire          k7ddrphy_dfi_p2_rddata_valid;
-wire   [14:0] k7ddrphy_dfi_p3_address;
-wire    [2:0] k7ddrphy_dfi_p3_bank;
-wire          k7ddrphy_dfi_p3_cas_n;
-wire          k7ddrphy_dfi_p3_cs_n;
-wire          k7ddrphy_dfi_p3_ras_n;
-wire          k7ddrphy_dfi_p3_we_n;
-wire          k7ddrphy_dfi_p3_cke;
-wire          k7ddrphy_dfi_p3_odt;
-wire          k7ddrphy_dfi_p3_reset_n;
-wire          k7ddrphy_dfi_p3_act_n;
-wire   [63:0] k7ddrphy_dfi_p3_wrdata;
-wire          k7ddrphy_dfi_p3_wrdata_en;
-wire    [7:0] k7ddrphy_dfi_p3_wrdata_mask;
-wire          k7ddrphy_dfi_p3_rddata_en;
-reg    [63:0] k7ddrphy_dfi_p3_rddata = 64'd0;
-wire          k7ddrphy_dfi_p3_rddata_valid;
-wire          k7ddrphy_sd_clk_se_nodelay;
-wire          k7ddrphy_sd_clk_se_delayed;
-wire    [2:0] k7ddrphy_pads_ba;
-wire          k7ddrphy_oq0;
-wire          k7ddrphy_oq1;
-wire          k7ddrphy_oq2;
-wire          k7ddrphy_oq3;
-wire          k7ddrphy_oq4;
-wire          k7ddrphy_oq5;
-wire          k7ddrphy_oq6;
-wire          k7ddrphy_oq7;
-wire          k7ddrphy_oq8;
-wire          k7ddrphy_oq9;
-wire          k7ddrphy_oq10;
-wire          k7ddrphy_oq11;
-wire          k7ddrphy_oq12;
-wire          k7ddrphy_oq13;
-wire          k7ddrphy_oq14;
-wire          k7ddrphy_oq15;
-wire          k7ddrphy_oq16;
-wire          k7ddrphy_oq17;
-wire          k7ddrphy_oq18;
-wire          k7ddrphy_oq19;
-wire          k7ddrphy_oq20;
-wire          k7ddrphy_oq21;
-wire          k7ddrphy_oq22;
-wire          k7ddrphy_oq23;
-wire          k7ddrphy_oq24;
-reg           k7ddrphy_dqs_oe = 1'd0;
-wire          k7ddrphy_dqs_preamble;
-wire          k7ddrphy_dqs_postamble;
-wire          k7ddrphy_dqs_oe_delay_tappeddelayline;
-reg           k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg           k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-reg           k7ddrphy_dqspattern0 = 1'd0;
-reg           k7ddrphy_dqspattern1 = 1'd0;
-reg     [7:0] k7ddrphy_dqspattern_o = 8'd0;
-wire          k7ddrphy_dqs_o_no_delay0;
-wire          k7ddrphy_dqs_o_delayed0;
-wire          k7ddrphy_dqs_t0;
-reg     [7:0] k7ddrphy_bitslip00 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip0_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip0_r0 = 16'd0;
-wire          k7ddrphy0;
-wire          k7ddrphy_dqs_o_no_delay1;
-wire          k7ddrphy_dqs_o_delayed1;
-wire          k7ddrphy_dqs_t1;
-reg     [7:0] k7ddrphy_bitslip10 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip1_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip1_r0 = 16'd0;
-wire          k7ddrphy1;
-wire          k7ddrphy_dqs_o_no_delay2;
-wire          k7ddrphy_dqs_o_delayed2;
-wire          k7ddrphy_dqs_t2;
-reg     [7:0] k7ddrphy_bitslip20 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip2_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip2_r0 = 16'd0;
-wire          k7ddrphy2;
-wire          k7ddrphy_dqs_o_no_delay3;
-wire          k7ddrphy_dqs_o_delayed3;
-wire          k7ddrphy_dqs_t3;
-reg     [7:0] k7ddrphy_bitslip30 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip3_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip3_r0 = 16'd0;
-wire          k7ddrphy3;
-wire          k7ddrphy_dm_o_nodelay0;
-reg     [7:0] k7ddrphy_bitslip01 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip0_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip0_r1 = 16'd0;
-wire          k7ddrphy_dm_o_nodelay1;
-reg     [7:0] k7ddrphy_bitslip11 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip1_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip1_r1 = 16'd0;
-wire          k7ddrphy_dm_o_nodelay2;
-reg     [7:0] k7ddrphy_bitslip21 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip2_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip2_r1 = 16'd0;
-wire          k7ddrphy_dm_o_nodelay3;
-reg     [7:0] k7ddrphy_bitslip31 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip3_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip3_r1 = 16'd0;
-wire          k7ddrphy_dq_oe;
-wire          k7ddrphy_dq_oe_delay_tappeddelayline;
-reg           k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg           k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-wire          k7ddrphy_dq_o_nodelay0;
-wire          k7ddrphy_dq_o_delayed0;
-wire          k7ddrphy_dq_i_nodelay0;
-wire          k7ddrphy_dq_i_delayed0;
-wire          k7ddrphy_dq_t0;
-reg     [7:0] k7ddrphy_bitslip02 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip0_value2 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip0_r2 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip03;
-reg     [7:0] k7ddrphy_bitslip04 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip0_value3 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip0_r3 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay1;
-wire          k7ddrphy_dq_o_delayed1;
-wire          k7ddrphy_dq_i_nodelay1;
-wire          k7ddrphy_dq_i_delayed1;
-wire          k7ddrphy_dq_t1;
-reg     [7:0] k7ddrphy_bitslip12 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip1_value2 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip1_r2 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip13;
-reg     [7:0] k7ddrphy_bitslip14 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip1_value3 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip1_r3 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay2;
-wire          k7ddrphy_dq_o_delayed2;
-wire          k7ddrphy_dq_i_nodelay2;
-wire          k7ddrphy_dq_i_delayed2;
-wire          k7ddrphy_dq_t2;
-reg     [7:0] k7ddrphy_bitslip22 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip2_value2 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip2_r2 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip23;
-reg     [7:0] k7ddrphy_bitslip24 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip2_value3 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip2_r3 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay3;
-wire          k7ddrphy_dq_o_delayed3;
-wire          k7ddrphy_dq_i_nodelay3;
-wire          k7ddrphy_dq_i_delayed3;
-wire          k7ddrphy_dq_t3;
-reg     [7:0] k7ddrphy_bitslip32 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip3_value2 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip3_r2 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip33;
-reg     [7:0] k7ddrphy_bitslip34 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip3_value3 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip3_r3 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay4;
-wire          k7ddrphy_dq_o_delayed4;
-wire          k7ddrphy_dq_i_nodelay4;
-wire          k7ddrphy_dq_i_delayed4;
-wire          k7ddrphy_dq_t4;
-reg     [7:0] k7ddrphy_bitslip40 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip4_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip4_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip41;
-reg     [7:0] k7ddrphy_bitslip42 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip4_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip4_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay5;
-wire          k7ddrphy_dq_o_delayed5;
-wire          k7ddrphy_dq_i_nodelay5;
-wire          k7ddrphy_dq_i_delayed5;
-wire          k7ddrphy_dq_t5;
-reg     [7:0] k7ddrphy_bitslip50 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip5_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip5_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip51;
-reg     [7:0] k7ddrphy_bitslip52 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip5_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip5_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay6;
-wire          k7ddrphy_dq_o_delayed6;
-wire          k7ddrphy_dq_i_nodelay6;
-wire          k7ddrphy_dq_i_delayed6;
-wire          k7ddrphy_dq_t6;
-reg     [7:0] k7ddrphy_bitslip60 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip6_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip6_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip61;
-reg     [7:0] k7ddrphy_bitslip62 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip6_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip6_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay7;
-wire          k7ddrphy_dq_o_delayed7;
-wire          k7ddrphy_dq_i_nodelay7;
-wire          k7ddrphy_dq_i_delayed7;
-wire          k7ddrphy_dq_t7;
-reg     [7:0] k7ddrphy_bitslip70 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip7_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip7_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip71;
-reg     [7:0] k7ddrphy_bitslip72 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip7_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip7_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay8;
-wire          k7ddrphy_dq_o_delayed8;
-wire          k7ddrphy_dq_i_nodelay8;
-wire          k7ddrphy_dq_i_delayed8;
-wire          k7ddrphy_dq_t8;
-reg     [7:0] k7ddrphy_bitslip80 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip8_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip8_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip81;
-reg     [7:0] k7ddrphy_bitslip82 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip8_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip8_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay9;
-wire          k7ddrphy_dq_o_delayed9;
-wire          k7ddrphy_dq_i_nodelay9;
-wire          k7ddrphy_dq_i_delayed9;
-wire          k7ddrphy_dq_t9;
-reg     [7:0] k7ddrphy_bitslip90 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip9_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip9_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip91;
-reg     [7:0] k7ddrphy_bitslip92 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip9_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip9_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay10;
-wire          k7ddrphy_dq_o_delayed10;
-wire          k7ddrphy_dq_i_nodelay10;
-wire          k7ddrphy_dq_i_delayed10;
-wire          k7ddrphy_dq_t10;
-reg     [7:0] k7ddrphy_bitslip100 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip10_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip10_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip101;
-reg     [7:0] k7ddrphy_bitslip102 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip10_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip10_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay11;
-wire          k7ddrphy_dq_o_delayed11;
-wire          k7ddrphy_dq_i_nodelay11;
-wire          k7ddrphy_dq_i_delayed11;
-wire          k7ddrphy_dq_t11;
-reg     [7:0] k7ddrphy_bitslip110 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip11_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip11_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip111;
-reg     [7:0] k7ddrphy_bitslip112 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip11_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip11_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay12;
-wire          k7ddrphy_dq_o_delayed12;
-wire          k7ddrphy_dq_i_nodelay12;
-wire          k7ddrphy_dq_i_delayed12;
-wire          k7ddrphy_dq_t12;
-reg     [7:0] k7ddrphy_bitslip120 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip12_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip12_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip121;
-reg     [7:0] k7ddrphy_bitslip122 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip12_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip12_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay13;
-wire          k7ddrphy_dq_o_delayed13;
-wire          k7ddrphy_dq_i_nodelay13;
-wire          k7ddrphy_dq_i_delayed13;
-wire          k7ddrphy_dq_t13;
-reg     [7:0] k7ddrphy_bitslip130 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip13_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip13_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip131;
-reg     [7:0] k7ddrphy_bitslip132 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip13_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip13_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay14;
-wire          k7ddrphy_dq_o_delayed14;
-wire          k7ddrphy_dq_i_nodelay14;
-wire          k7ddrphy_dq_i_delayed14;
-wire          k7ddrphy_dq_t14;
-reg     [7:0] k7ddrphy_bitslip140 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip14_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip14_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip141;
-reg     [7:0] k7ddrphy_bitslip142 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip14_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip14_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay15;
-wire          k7ddrphy_dq_o_delayed15;
-wire          k7ddrphy_dq_i_nodelay15;
-wire          k7ddrphy_dq_i_delayed15;
-wire          k7ddrphy_dq_t15;
-reg     [7:0] k7ddrphy_bitslip150 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip15_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip15_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip151;
-reg     [7:0] k7ddrphy_bitslip152 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip15_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip15_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay16;
-wire          k7ddrphy_dq_o_delayed16;
-wire          k7ddrphy_dq_i_nodelay16;
-wire          k7ddrphy_dq_i_delayed16;
-wire          k7ddrphy_dq_t16;
-reg     [7:0] k7ddrphy_bitslip160 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip16_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip16_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip161;
-reg     [7:0] k7ddrphy_bitslip162 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip16_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip16_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay17;
-wire          k7ddrphy_dq_o_delayed17;
-wire          k7ddrphy_dq_i_nodelay17;
-wire          k7ddrphy_dq_i_delayed17;
-wire          k7ddrphy_dq_t17;
-reg     [7:0] k7ddrphy_bitslip170 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip17_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip17_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip171;
-reg     [7:0] k7ddrphy_bitslip172 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip17_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip17_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay18;
-wire          k7ddrphy_dq_o_delayed18;
-wire          k7ddrphy_dq_i_nodelay18;
-wire          k7ddrphy_dq_i_delayed18;
-wire          k7ddrphy_dq_t18;
-reg     [7:0] k7ddrphy_bitslip180 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip18_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip18_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip181;
-reg     [7:0] k7ddrphy_bitslip182 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip18_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip18_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay19;
-wire          k7ddrphy_dq_o_delayed19;
-wire          k7ddrphy_dq_i_nodelay19;
-wire          k7ddrphy_dq_i_delayed19;
-wire          k7ddrphy_dq_t19;
-reg     [7:0] k7ddrphy_bitslip190 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip19_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip19_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip191;
-reg     [7:0] k7ddrphy_bitslip192 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip19_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip19_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay20;
-wire          k7ddrphy_dq_o_delayed20;
-wire          k7ddrphy_dq_i_nodelay20;
-wire          k7ddrphy_dq_i_delayed20;
-wire          k7ddrphy_dq_t20;
-reg     [7:0] k7ddrphy_bitslip200 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip20_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip20_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip201;
-reg     [7:0] k7ddrphy_bitslip202 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip20_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip20_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay21;
-wire          k7ddrphy_dq_o_delayed21;
-wire          k7ddrphy_dq_i_nodelay21;
-wire          k7ddrphy_dq_i_delayed21;
-wire          k7ddrphy_dq_t21;
-reg     [7:0] k7ddrphy_bitslip210 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip21_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip21_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip211;
-reg     [7:0] k7ddrphy_bitslip212 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip21_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip21_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay22;
-wire          k7ddrphy_dq_o_delayed22;
-wire          k7ddrphy_dq_i_nodelay22;
-wire          k7ddrphy_dq_i_delayed22;
-wire          k7ddrphy_dq_t22;
-reg     [7:0] k7ddrphy_bitslip220 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip22_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip22_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip221;
-reg     [7:0] k7ddrphy_bitslip222 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip22_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip22_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay23;
-wire          k7ddrphy_dq_o_delayed23;
-wire          k7ddrphy_dq_i_nodelay23;
-wire          k7ddrphy_dq_i_delayed23;
-wire          k7ddrphy_dq_t23;
-reg     [7:0] k7ddrphy_bitslip230 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip23_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip23_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip231;
-reg     [7:0] k7ddrphy_bitslip232 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip23_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip23_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay24;
-wire          k7ddrphy_dq_o_delayed24;
-wire          k7ddrphy_dq_i_nodelay24;
-wire          k7ddrphy_dq_i_delayed24;
-wire          k7ddrphy_dq_t24;
-reg     [7:0] k7ddrphy_bitslip240 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip24_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip24_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip241;
-reg     [7:0] k7ddrphy_bitslip242 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip24_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip24_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay25;
-wire          k7ddrphy_dq_o_delayed25;
-wire          k7ddrphy_dq_i_nodelay25;
-wire          k7ddrphy_dq_i_delayed25;
-wire          k7ddrphy_dq_t25;
-reg     [7:0] k7ddrphy_bitslip250 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip25_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip25_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip251;
-reg     [7:0] k7ddrphy_bitslip252 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip25_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip25_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay26;
-wire          k7ddrphy_dq_o_delayed26;
-wire          k7ddrphy_dq_i_nodelay26;
-wire          k7ddrphy_dq_i_delayed26;
-wire          k7ddrphy_dq_t26;
-reg     [7:0] k7ddrphy_bitslip260 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip26_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip26_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip261;
-reg     [7:0] k7ddrphy_bitslip262 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip26_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip26_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay27;
-wire          k7ddrphy_dq_o_delayed27;
-wire          k7ddrphy_dq_i_nodelay27;
-wire          k7ddrphy_dq_i_delayed27;
-wire          k7ddrphy_dq_t27;
-reg     [7:0] k7ddrphy_bitslip270 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip27_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip27_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip271;
-reg     [7:0] k7ddrphy_bitslip272 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip27_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip27_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay28;
-wire          k7ddrphy_dq_o_delayed28;
-wire          k7ddrphy_dq_i_nodelay28;
-wire          k7ddrphy_dq_i_delayed28;
-wire          k7ddrphy_dq_t28;
-reg     [7:0] k7ddrphy_bitslip280 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip28_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip28_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip281;
-reg     [7:0] k7ddrphy_bitslip282 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip28_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip28_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay29;
-wire          k7ddrphy_dq_o_delayed29;
-wire          k7ddrphy_dq_i_nodelay29;
-wire          k7ddrphy_dq_i_delayed29;
-wire          k7ddrphy_dq_t29;
-reg     [7:0] k7ddrphy_bitslip290 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip29_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip29_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip291;
-reg     [7:0] k7ddrphy_bitslip292 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip29_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip29_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay30;
-wire          k7ddrphy_dq_o_delayed30;
-wire          k7ddrphy_dq_i_nodelay30;
-wire          k7ddrphy_dq_i_delayed30;
-wire          k7ddrphy_dq_t30;
-reg     [7:0] k7ddrphy_bitslip300 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip30_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip30_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip301;
-reg     [7:0] k7ddrphy_bitslip302 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip30_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip30_r1 = 16'd0;
-wire          k7ddrphy_dq_o_nodelay31;
-wire          k7ddrphy_dq_o_delayed31;
-wire          k7ddrphy_dq_i_nodelay31;
-wire          k7ddrphy_dq_i_delayed31;
-wire          k7ddrphy_dq_t31;
-reg     [7:0] k7ddrphy_bitslip310 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip31_value0 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip31_r0 = 16'd0;
-wire    [7:0] k7ddrphy_bitslip311;
-reg     [7:0] k7ddrphy_bitslip312 = 8'd0;
-reg     [2:0] k7ddrphy_bitslip31_value1 = 3'd7;
-reg    [15:0] k7ddrphy_bitslip31_r1 = 16'd0;
-reg           k7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
-reg           k7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
-reg           k7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
-reg           k7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
-reg           k7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
-reg           k7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
-reg           k7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
-reg           k7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
-reg           k7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
-reg           k7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
-reg           k7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
-wire   [14:0] litedramcore_slave_p0_address;
-wire    [2:0] litedramcore_slave_p0_bank;
-wire          litedramcore_slave_p0_cas_n;
-wire          litedramcore_slave_p0_cs_n;
-wire          litedramcore_slave_p0_ras_n;
-wire          litedramcore_slave_p0_we_n;
-wire          litedramcore_slave_p0_cke;
-wire          litedramcore_slave_p0_odt;
-wire          litedramcore_slave_p0_reset_n;
-wire          litedramcore_slave_p0_act_n;
-wire   [63:0] litedramcore_slave_p0_wrdata;
-wire          litedramcore_slave_p0_wrdata_en;
-wire    [7:0] litedramcore_slave_p0_wrdata_mask;
-wire          litedramcore_slave_p0_rddata_en;
-reg    [63:0] litedramcore_slave_p0_rddata = 64'd0;
-reg           litedramcore_slave_p0_rddata_valid = 1'd0;
-wire   [14:0] litedramcore_slave_p1_address;
-wire    [2:0] litedramcore_slave_p1_bank;
-wire          litedramcore_slave_p1_cas_n;
-wire          litedramcore_slave_p1_cs_n;
-wire          litedramcore_slave_p1_ras_n;
-wire          litedramcore_slave_p1_we_n;
-wire          litedramcore_slave_p1_cke;
-wire          litedramcore_slave_p1_odt;
-wire          litedramcore_slave_p1_reset_n;
-wire          litedramcore_slave_p1_act_n;
-wire   [63:0] litedramcore_slave_p1_wrdata;
-wire          litedramcore_slave_p1_wrdata_en;
-wire    [7:0] litedramcore_slave_p1_wrdata_mask;
-wire          litedramcore_slave_p1_rddata_en;
-reg    [63:0] litedramcore_slave_p1_rddata = 64'd0;
-reg           litedramcore_slave_p1_rddata_valid = 1'd0;
-wire   [14:0] litedramcore_slave_p2_address;
-wire    [2:0] litedramcore_slave_p2_bank;
-wire          litedramcore_slave_p2_cas_n;
-wire          litedramcore_slave_p2_cs_n;
-wire          litedramcore_slave_p2_ras_n;
-wire          litedramcore_slave_p2_we_n;
-wire          litedramcore_slave_p2_cke;
-wire          litedramcore_slave_p2_odt;
-wire          litedramcore_slave_p2_reset_n;
-wire          litedramcore_slave_p2_act_n;
-wire   [63:0] litedramcore_slave_p2_wrdata;
-wire          litedramcore_slave_p2_wrdata_en;
-wire    [7:0] litedramcore_slave_p2_wrdata_mask;
-wire          litedramcore_slave_p2_rddata_en;
-reg    [63:0] litedramcore_slave_p2_rddata = 64'd0;
-reg           litedramcore_slave_p2_rddata_valid = 1'd0;
-wire   [14:0] litedramcore_slave_p3_address;
-wire    [2:0] litedramcore_slave_p3_bank;
-wire          litedramcore_slave_p3_cas_n;
-wire          litedramcore_slave_p3_cs_n;
-wire          litedramcore_slave_p3_ras_n;
-wire          litedramcore_slave_p3_we_n;
-wire          litedramcore_slave_p3_cke;
-wire          litedramcore_slave_p3_odt;
-wire          litedramcore_slave_p3_reset_n;
-wire          litedramcore_slave_p3_act_n;
-wire   [63:0] litedramcore_slave_p3_wrdata;
-wire          litedramcore_slave_p3_wrdata_en;
-wire    [7:0] litedramcore_slave_p3_wrdata_mask;
-wire          litedramcore_slave_p3_rddata_en;
-reg    [63:0] litedramcore_slave_p3_rddata = 64'd0;
-reg           litedramcore_slave_p3_rddata_valid = 1'd0;
-reg    [14:0] litedramcore_master_p0_address = 15'd0;
-reg     [2:0] litedramcore_master_p0_bank = 3'd0;
-reg           litedramcore_master_p0_cas_n = 1'd1;
-reg           litedramcore_master_p0_cs_n = 1'd1;
-reg           litedramcore_master_p0_ras_n = 1'd1;
-reg           litedramcore_master_p0_we_n = 1'd1;
-reg           litedramcore_master_p0_cke = 1'd0;
-reg           litedramcore_master_p0_odt = 1'd0;
-reg           litedramcore_master_p0_reset_n = 1'd0;
-reg           litedramcore_master_p0_act_n = 1'd1;
-reg    [63:0] litedramcore_master_p0_wrdata = 64'd0;
-reg           litedramcore_master_p0_wrdata_en = 1'd0;
-reg     [7:0] litedramcore_master_p0_wrdata_mask = 8'd0;
-reg           litedramcore_master_p0_rddata_en = 1'd0;
-wire   [63:0] litedramcore_master_p0_rddata;
-wire          litedramcore_master_p0_rddata_valid;
-reg    [14:0] litedramcore_master_p1_address = 15'd0;
-reg     [2:0] litedramcore_master_p1_bank = 3'd0;
-reg           litedramcore_master_p1_cas_n = 1'd1;
-reg           litedramcore_master_p1_cs_n = 1'd1;
-reg           litedramcore_master_p1_ras_n = 1'd1;
-reg           litedramcore_master_p1_we_n = 1'd1;
-reg           litedramcore_master_p1_cke = 1'd0;
-reg           litedramcore_master_p1_odt = 1'd0;
-reg           litedramcore_master_p1_reset_n = 1'd0;
-reg           litedramcore_master_p1_act_n = 1'd1;
-reg    [63:0] litedramcore_master_p1_wrdata = 64'd0;
-reg           litedramcore_master_p1_wrdata_en = 1'd0;
-reg     [7:0] litedramcore_master_p1_wrdata_mask = 8'd0;
-reg           litedramcore_master_p1_rddata_en = 1'd0;
-wire   [63:0] litedramcore_master_p1_rddata;
-wire          litedramcore_master_p1_rddata_valid;
-reg    [14:0] litedramcore_master_p2_address = 15'd0;
-reg     [2:0] litedramcore_master_p2_bank = 3'd0;
-reg           litedramcore_master_p2_cas_n = 1'd1;
-reg           litedramcore_master_p2_cs_n = 1'd1;
-reg           litedramcore_master_p2_ras_n = 1'd1;
-reg           litedramcore_master_p2_we_n = 1'd1;
-reg           litedramcore_master_p2_cke = 1'd0;
-reg           litedramcore_master_p2_odt = 1'd0;
-reg           litedramcore_master_p2_reset_n = 1'd0;
-reg           litedramcore_master_p2_act_n = 1'd1;
-reg    [63:0] litedramcore_master_p2_wrdata = 64'd0;
-reg           litedramcore_master_p2_wrdata_en = 1'd0;
-reg     [7:0] litedramcore_master_p2_wrdata_mask = 8'd0;
-reg           litedramcore_master_p2_rddata_en = 1'd0;
-wire   [63:0] litedramcore_master_p2_rddata;
-wire          litedramcore_master_p2_rddata_valid;
-reg    [14:0] litedramcore_master_p3_address = 15'd0;
-reg     [2:0] litedramcore_master_p3_bank = 3'd0;
-reg           litedramcore_master_p3_cas_n = 1'd1;
-reg           litedramcore_master_p3_cs_n = 1'd1;
-reg           litedramcore_master_p3_ras_n = 1'd1;
-reg           litedramcore_master_p3_we_n = 1'd1;
-reg           litedramcore_master_p3_cke = 1'd0;
-reg           litedramcore_master_p3_odt = 1'd0;
-reg           litedramcore_master_p3_reset_n = 1'd0;
-reg           litedramcore_master_p3_act_n = 1'd1;
-reg    [63:0] litedramcore_master_p3_wrdata = 64'd0;
-reg           litedramcore_master_p3_wrdata_en = 1'd0;
-reg     [7:0] litedramcore_master_p3_wrdata_mask = 8'd0;
-reg           litedramcore_master_p3_rddata_en = 1'd0;
-wire   [63:0] litedramcore_master_p3_rddata;
-wire          litedramcore_master_p3_rddata_valid;
-wire   [14:0] litedramcore_csr_dfi_p0_address;
-wire    [2:0] litedramcore_csr_dfi_p0_bank;
-reg           litedramcore_csr_dfi_p0_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p0_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p0_ras_n = 1'd1;
-reg           litedramcore_csr_dfi_p0_we_n = 1'd1;
-wire          litedramcore_csr_dfi_p0_cke;
-wire          litedramcore_csr_dfi_p0_odt;
-wire          litedramcore_csr_dfi_p0_reset_n;
-reg           litedramcore_csr_dfi_p0_act_n = 1'd1;
-wire   [63:0] litedramcore_csr_dfi_p0_wrdata;
-wire          litedramcore_csr_dfi_p0_wrdata_en;
-wire    [7:0] litedramcore_csr_dfi_p0_wrdata_mask;
-wire          litedramcore_csr_dfi_p0_rddata_en;
-reg    [63:0] litedramcore_csr_dfi_p0_rddata = 64'd0;
-reg           litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
-wire   [14:0] litedramcore_csr_dfi_p1_address;
-wire    [2:0] litedramcore_csr_dfi_p1_bank;
-reg           litedramcore_csr_dfi_p1_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p1_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p1_ras_n = 1'd1;
-reg           litedramcore_csr_dfi_p1_we_n = 1'd1;
-wire          litedramcore_csr_dfi_p1_cke;
-wire          litedramcore_csr_dfi_p1_odt;
-wire          litedramcore_csr_dfi_p1_reset_n;
-reg           litedramcore_csr_dfi_p1_act_n = 1'd1;
-wire   [63:0] litedramcore_csr_dfi_p1_wrdata;
-wire          litedramcore_csr_dfi_p1_wrdata_en;
-wire    [7:0] litedramcore_csr_dfi_p1_wrdata_mask;
-wire          litedramcore_csr_dfi_p1_rddata_en;
-reg    [63:0] litedramcore_csr_dfi_p1_rddata = 64'd0;
-reg           litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
-wire   [14:0] litedramcore_csr_dfi_p2_address;
-wire    [2:0] litedramcore_csr_dfi_p2_bank;
-reg           litedramcore_csr_dfi_p2_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p2_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p2_ras_n = 1'd1;
-reg           litedramcore_csr_dfi_p2_we_n = 1'd1;
-wire          litedramcore_csr_dfi_p2_cke;
-wire          litedramcore_csr_dfi_p2_odt;
-wire          litedramcore_csr_dfi_p2_reset_n;
-reg           litedramcore_csr_dfi_p2_act_n = 1'd1;
-wire   [63:0] litedramcore_csr_dfi_p2_wrdata;
-wire          litedramcore_csr_dfi_p2_wrdata_en;
-wire    [7:0] litedramcore_csr_dfi_p2_wrdata_mask;
-wire          litedramcore_csr_dfi_p2_rddata_en;
-reg    [63:0] litedramcore_csr_dfi_p2_rddata = 64'd0;
-reg           litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
-wire   [14:0] litedramcore_csr_dfi_p3_address;
-wire    [2:0] litedramcore_csr_dfi_p3_bank;
-reg           litedramcore_csr_dfi_p3_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p3_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p3_ras_n = 1'd1;
-reg           litedramcore_csr_dfi_p3_we_n = 1'd1;
-wire          litedramcore_csr_dfi_p3_cke;
-wire          litedramcore_csr_dfi_p3_odt;
-wire          litedramcore_csr_dfi_p3_reset_n;
-reg           litedramcore_csr_dfi_p3_act_n = 1'd1;
-wire   [63:0] litedramcore_csr_dfi_p3_wrdata;
-wire          litedramcore_csr_dfi_p3_wrdata_en;
-wire    [7:0] litedramcore_csr_dfi_p3_wrdata_mask;
-wire          litedramcore_csr_dfi_p3_rddata_en;
-reg    [63:0] litedramcore_csr_dfi_p3_rddata = 64'd0;
-reg           litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
-reg    [14:0] litedramcore_ext_dfi_p0_address = 15'd0;
-reg     [2:0] litedramcore_ext_dfi_p0_bank = 3'd0;
-reg           litedramcore_ext_dfi_p0_cas_n = 1'd1;
-reg           litedramcore_ext_dfi_p0_cs_n = 1'd1;
-reg           litedramcore_ext_dfi_p0_ras_n = 1'd1;
-reg           litedramcore_ext_dfi_p0_we_n = 1'd1;
-reg           litedramcore_ext_dfi_p0_cke = 1'd0;
-reg           litedramcore_ext_dfi_p0_odt = 1'd0;
-reg           litedramcore_ext_dfi_p0_reset_n = 1'd0;
-reg           litedramcore_ext_dfi_p0_act_n = 1'd1;
-reg    [63:0] litedramcore_ext_dfi_p0_wrdata = 64'd0;
-reg           litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
-reg     [7:0] litedramcore_ext_dfi_p0_wrdata_mask = 8'd0;
-reg           litedramcore_ext_dfi_p0_rddata_en = 1'd0;
-reg    [63:0] litedramcore_ext_dfi_p0_rddata = 64'd0;
-reg           litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
-reg    [14:0] litedramcore_ext_dfi_p1_address = 15'd0;
-reg     [2:0] litedramcore_ext_dfi_p1_bank = 3'd0;
-reg           litedramcore_ext_dfi_p1_cas_n = 1'd1;
-reg           litedramcore_ext_dfi_p1_cs_n = 1'd1;
-reg           litedramcore_ext_dfi_p1_ras_n = 1'd1;
-reg           litedramcore_ext_dfi_p1_we_n = 1'd1;
-reg           litedramcore_ext_dfi_p1_cke = 1'd0;
-reg           litedramcore_ext_dfi_p1_odt = 1'd0;
-reg           litedramcore_ext_dfi_p1_reset_n = 1'd0;
-reg           litedramcore_ext_dfi_p1_act_n = 1'd1;
-reg    [63:0] litedramcore_ext_dfi_p1_wrdata = 64'd0;
-reg           litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
-reg     [7:0] litedramcore_ext_dfi_p1_wrdata_mask = 8'd0;
-reg           litedramcore_ext_dfi_p1_rddata_en = 1'd0;
-reg    [63:0] litedramcore_ext_dfi_p1_rddata = 64'd0;
-reg           litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
-reg    [14:0] litedramcore_ext_dfi_p2_address = 15'd0;
-reg     [2:0] litedramcore_ext_dfi_p2_bank = 3'd0;
-reg           litedramcore_ext_dfi_p2_cas_n = 1'd1;
-reg           litedramcore_ext_dfi_p2_cs_n = 1'd1;
-reg           litedramcore_ext_dfi_p2_ras_n = 1'd1;
-reg           litedramcore_ext_dfi_p2_we_n = 1'd1;
-reg           litedramcore_ext_dfi_p2_cke = 1'd0;
-reg           litedramcore_ext_dfi_p2_odt = 1'd0;
-reg           litedramcore_ext_dfi_p2_reset_n = 1'd0;
-reg           litedramcore_ext_dfi_p2_act_n = 1'd1;
-reg    [63:0] litedramcore_ext_dfi_p2_wrdata = 64'd0;
-reg           litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
-reg     [7:0] litedramcore_ext_dfi_p2_wrdata_mask = 8'd0;
-reg           litedramcore_ext_dfi_p2_rddata_en = 1'd0;
-reg    [63:0] litedramcore_ext_dfi_p2_rddata = 64'd0;
-reg           litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
-reg    [14:0] litedramcore_ext_dfi_p3_address = 15'd0;
-reg     [2:0] litedramcore_ext_dfi_p3_bank = 3'd0;
-reg           litedramcore_ext_dfi_p3_cas_n = 1'd1;
-reg           litedramcore_ext_dfi_p3_cs_n = 1'd1;
-reg           litedramcore_ext_dfi_p3_ras_n = 1'd1;
-reg           litedramcore_ext_dfi_p3_we_n = 1'd1;
-reg           litedramcore_ext_dfi_p3_cke = 1'd0;
-reg           litedramcore_ext_dfi_p3_odt = 1'd0;
-reg           litedramcore_ext_dfi_p3_reset_n = 1'd0;
-reg           litedramcore_ext_dfi_p3_act_n = 1'd1;
-reg    [63:0] litedramcore_ext_dfi_p3_wrdata = 64'd0;
-reg           litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
-reg     [7:0] litedramcore_ext_dfi_p3_wrdata_mask = 8'd0;
-reg           litedramcore_ext_dfi_p3_rddata_en = 1'd0;
-reg    [63:0] litedramcore_ext_dfi_p3_rddata = 64'd0;
-reg           litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
-reg           litedramcore_ext_dfi_sel = 1'd0;
-wire          litedramcore_sel;
-wire          litedramcore_cke;
-wire          litedramcore_odt;
-wire          litedramcore_reset_n;
-reg     [3:0] litedramcore_storage = 4'd1;
-reg           litedramcore_re = 1'd0;
-wire          litedramcore_phaseinjector0_csrfield_cs;
-wire          litedramcore_phaseinjector0_csrfield_we;
-wire          litedramcore_phaseinjector0_csrfield_cas;
-wire          litedramcore_phaseinjector0_csrfield_ras;
-wire          litedramcore_phaseinjector0_csrfield_wren;
-wire          litedramcore_phaseinjector0_csrfield_rden;
-reg     [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
-reg           litedramcore_phaseinjector0_command_re = 1'd0;
-reg           litedramcore_phaseinjector0_command_issue_re = 1'd0;
-wire          litedramcore_phaseinjector0_command_issue_r;
-reg           litedramcore_phaseinjector0_command_issue_we = 1'd0;
-reg           litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg    [14:0] litedramcore_phaseinjector0_address_storage = 15'd0;
-reg           litedramcore_phaseinjector0_address_re = 1'd0;
-reg     [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg           litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg    [63:0] litedramcore_phaseinjector0_wrdata_storage = 64'd0;
-reg           litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg    [63:0] litedramcore_phaseinjector0_rddata_status = 64'd0;
-wire          litedramcore_phaseinjector0_rddata_we;
-reg           litedramcore_phaseinjector0_rddata_re = 1'd0;
-wire          litedramcore_phaseinjector1_csrfield_cs;
-wire          litedramcore_phaseinjector1_csrfield_we;
-wire          litedramcore_phaseinjector1_csrfield_cas;
-wire          litedramcore_phaseinjector1_csrfield_ras;
-wire          litedramcore_phaseinjector1_csrfield_wren;
-wire          litedramcore_phaseinjector1_csrfield_rden;
-reg     [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
-reg           litedramcore_phaseinjector1_command_re = 1'd0;
-reg           litedramcore_phaseinjector1_command_issue_re = 1'd0;
-wire          litedramcore_phaseinjector1_command_issue_r;
-reg           litedramcore_phaseinjector1_command_issue_we = 1'd0;
-reg           litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg    [14:0] litedramcore_phaseinjector1_address_storage = 15'd0;
-reg           litedramcore_phaseinjector1_address_re = 1'd0;
-reg     [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg           litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg    [63:0] litedramcore_phaseinjector1_wrdata_storage = 64'd0;
-reg           litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg    [63:0] litedramcore_phaseinjector1_rddata_status = 64'd0;
-wire          litedramcore_phaseinjector1_rddata_we;
-reg           litedramcore_phaseinjector1_rddata_re = 1'd0;
-wire          litedramcore_phaseinjector2_csrfield_cs;
-wire          litedramcore_phaseinjector2_csrfield_we;
-wire          litedramcore_phaseinjector2_csrfield_cas;
-wire          litedramcore_phaseinjector2_csrfield_ras;
-wire          litedramcore_phaseinjector2_csrfield_wren;
-wire          litedramcore_phaseinjector2_csrfield_rden;
-reg     [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
-reg           litedramcore_phaseinjector2_command_re = 1'd0;
-reg           litedramcore_phaseinjector2_command_issue_re = 1'd0;
-wire          litedramcore_phaseinjector2_command_issue_r;
-reg           litedramcore_phaseinjector2_command_issue_we = 1'd0;
-reg           litedramcore_phaseinjector2_command_issue_w = 1'd0;
-reg    [14:0] litedramcore_phaseinjector2_address_storage = 15'd0;
-reg           litedramcore_phaseinjector2_address_re = 1'd0;
-reg     [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
-reg           litedramcore_phaseinjector2_baddress_re = 1'd0;
-reg    [63:0] litedramcore_phaseinjector2_wrdata_storage = 64'd0;
-reg           litedramcore_phaseinjector2_wrdata_re = 1'd0;
-reg    [63:0] litedramcore_phaseinjector2_rddata_status = 64'd0;
-wire          litedramcore_phaseinjector2_rddata_we;
-reg           litedramcore_phaseinjector2_rddata_re = 1'd0;
-wire          litedramcore_phaseinjector3_csrfield_cs;
-wire          litedramcore_phaseinjector3_csrfield_we;
-wire          litedramcore_phaseinjector3_csrfield_cas;
-wire          litedramcore_phaseinjector3_csrfield_ras;
-wire          litedramcore_phaseinjector3_csrfield_wren;
-wire          litedramcore_phaseinjector3_csrfield_rden;
-reg     [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
-reg           litedramcore_phaseinjector3_command_re = 1'd0;
-reg           litedramcore_phaseinjector3_command_issue_re = 1'd0;
-wire          litedramcore_phaseinjector3_command_issue_r;
-reg           litedramcore_phaseinjector3_command_issue_we = 1'd0;
-reg           litedramcore_phaseinjector3_command_issue_w = 1'd0;
-reg    [14:0] litedramcore_phaseinjector3_address_storage = 15'd0;
-reg           litedramcore_phaseinjector3_address_re = 1'd0;
-reg     [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
-reg           litedramcore_phaseinjector3_baddress_re = 1'd0;
-reg    [63:0] litedramcore_phaseinjector3_wrdata_storage = 64'd0;
-reg           litedramcore_phaseinjector3_wrdata_re = 1'd0;
-reg    [63:0] litedramcore_phaseinjector3_rddata_status = 64'd0;
-wire          litedramcore_phaseinjector3_rddata_we;
-reg           litedramcore_phaseinjector3_rddata_re = 1'd0;
-wire          litedramcore_interface_bank0_valid;
-wire          litedramcore_interface_bank0_ready;
-wire          litedramcore_interface_bank0_we;
-wire   [21:0] litedramcore_interface_bank0_addr;
-wire          litedramcore_interface_bank0_lock;
-wire          litedramcore_interface_bank0_wdata_ready;
-wire          litedramcore_interface_bank0_rdata_valid;
-wire          litedramcore_interface_bank1_valid;
-wire          litedramcore_interface_bank1_ready;
-wire          litedramcore_interface_bank1_we;
-wire   [21:0] litedramcore_interface_bank1_addr;
-wire          litedramcore_interface_bank1_lock;
-wire          litedramcore_interface_bank1_wdata_ready;
-wire          litedramcore_interface_bank1_rdata_valid;
-wire          litedramcore_interface_bank2_valid;
-wire          litedramcore_interface_bank2_ready;
-wire          litedramcore_interface_bank2_we;
-wire   [21:0] litedramcore_interface_bank2_addr;
-wire          litedramcore_interface_bank2_lock;
-wire          litedramcore_interface_bank2_wdata_ready;
-wire          litedramcore_interface_bank2_rdata_valid;
-wire          litedramcore_interface_bank3_valid;
-wire          litedramcore_interface_bank3_ready;
-wire          litedramcore_interface_bank3_we;
-wire   [21:0] litedramcore_interface_bank3_addr;
-wire          litedramcore_interface_bank3_lock;
-wire          litedramcore_interface_bank3_wdata_ready;
-wire          litedramcore_interface_bank3_rdata_valid;
-wire          litedramcore_interface_bank4_valid;
-wire          litedramcore_interface_bank4_ready;
-wire          litedramcore_interface_bank4_we;
-wire   [21:0] litedramcore_interface_bank4_addr;
-wire          litedramcore_interface_bank4_lock;
-wire          litedramcore_interface_bank4_wdata_ready;
-wire          litedramcore_interface_bank4_rdata_valid;
-wire          litedramcore_interface_bank5_valid;
-wire          litedramcore_interface_bank5_ready;
-wire          litedramcore_interface_bank5_we;
-wire   [21:0] litedramcore_interface_bank5_addr;
-wire          litedramcore_interface_bank5_lock;
-wire          litedramcore_interface_bank5_wdata_ready;
-wire          litedramcore_interface_bank5_rdata_valid;
-wire          litedramcore_interface_bank6_valid;
-wire          litedramcore_interface_bank6_ready;
-wire          litedramcore_interface_bank6_we;
-wire   [21:0] litedramcore_interface_bank6_addr;
-wire          litedramcore_interface_bank6_lock;
-wire          litedramcore_interface_bank6_wdata_ready;
-wire          litedramcore_interface_bank6_rdata_valid;
-wire          litedramcore_interface_bank7_valid;
-wire          litedramcore_interface_bank7_ready;
-wire          litedramcore_interface_bank7_we;
-wire   [21:0] litedramcore_interface_bank7_addr;
-wire          litedramcore_interface_bank7_lock;
-wire          litedramcore_interface_bank7_wdata_ready;
-wire          litedramcore_interface_bank7_rdata_valid;
-reg   [255:0] litedramcore_interface_wdata = 256'd0;
-reg    [31:0] litedramcore_interface_wdata_we = 32'd0;
-wire  [255:0] litedramcore_interface_rdata;
-reg    [14:0] litedramcore_dfi_p0_address = 15'd0;
-reg     [2:0] litedramcore_dfi_p0_bank = 3'd0;
-reg           litedramcore_dfi_p0_cas_n = 1'd1;
-reg           litedramcore_dfi_p0_cs_n = 1'd1;
-reg           litedramcore_dfi_p0_ras_n = 1'd1;
-reg           litedramcore_dfi_p0_we_n = 1'd1;
-wire          litedramcore_dfi_p0_cke;
-wire          litedramcore_dfi_p0_odt;
-wire          litedramcore_dfi_p0_reset_n;
-reg           litedramcore_dfi_p0_act_n = 1'd1;
-wire   [63:0] litedramcore_dfi_p0_wrdata;
-reg           litedramcore_dfi_p0_wrdata_en = 1'd0;
-wire    [7:0] litedramcore_dfi_p0_wrdata_mask;
-reg           litedramcore_dfi_p0_rddata_en = 1'd0;
-wire   [63:0] litedramcore_dfi_p0_rddata;
-wire          litedramcore_dfi_p0_rddata_valid;
-reg    [14:0] litedramcore_dfi_p1_address = 15'd0;
-reg     [2:0] litedramcore_dfi_p1_bank = 3'd0;
-reg           litedramcore_dfi_p1_cas_n = 1'd1;
-reg           litedramcore_dfi_p1_cs_n = 1'd1;
-reg           litedramcore_dfi_p1_ras_n = 1'd1;
-reg           litedramcore_dfi_p1_we_n = 1'd1;
-wire          litedramcore_dfi_p1_cke;
-wire          litedramcore_dfi_p1_odt;
-wire          litedramcore_dfi_p1_reset_n;
-reg           litedramcore_dfi_p1_act_n = 1'd1;
-wire   [63:0] litedramcore_dfi_p1_wrdata;
-reg           litedramcore_dfi_p1_wrdata_en = 1'd0;
-wire    [7:0] litedramcore_dfi_p1_wrdata_mask;
-reg           litedramcore_dfi_p1_rddata_en = 1'd0;
-wire   [63:0] litedramcore_dfi_p1_rddata;
-wire          litedramcore_dfi_p1_rddata_valid;
-reg    [14:0] litedramcore_dfi_p2_address = 15'd0;
-reg     [2:0] litedramcore_dfi_p2_bank = 3'd0;
-reg           litedramcore_dfi_p2_cas_n = 1'd1;
-reg           litedramcore_dfi_p2_cs_n = 1'd1;
-reg           litedramcore_dfi_p2_ras_n = 1'd1;
-reg           litedramcore_dfi_p2_we_n = 1'd1;
-wire          litedramcore_dfi_p2_cke;
-wire          litedramcore_dfi_p2_odt;
-wire          litedramcore_dfi_p2_reset_n;
-reg           litedramcore_dfi_p2_act_n = 1'd1;
-wire   [63:0] litedramcore_dfi_p2_wrdata;
-reg           litedramcore_dfi_p2_wrdata_en = 1'd0;
-wire    [7:0] litedramcore_dfi_p2_wrdata_mask;
-reg           litedramcore_dfi_p2_rddata_en = 1'd0;
-wire   [63:0] litedramcore_dfi_p2_rddata;
-wire          litedramcore_dfi_p2_rddata_valid;
-reg    [14:0] litedramcore_dfi_p3_address = 15'd0;
-reg     [2:0] litedramcore_dfi_p3_bank = 3'd0;
-reg           litedramcore_dfi_p3_cas_n = 1'd1;
-reg           litedramcore_dfi_p3_cs_n = 1'd1;
-reg           litedramcore_dfi_p3_ras_n = 1'd1;
-reg           litedramcore_dfi_p3_we_n = 1'd1;
-wire          litedramcore_dfi_p3_cke;
-wire          litedramcore_dfi_p3_odt;
-wire          litedramcore_dfi_p3_reset_n;
-reg           litedramcore_dfi_p3_act_n = 1'd1;
-wire   [63:0] litedramcore_dfi_p3_wrdata;
-reg           litedramcore_dfi_p3_wrdata_en = 1'd0;
-wire    [7:0] litedramcore_dfi_p3_wrdata_mask;
-reg           litedramcore_dfi_p3_rddata_en = 1'd0;
-wire   [63:0] litedramcore_dfi_p3_rddata;
-wire          litedramcore_dfi_p3_rddata_valid;
-reg           litedramcore_cmd_valid = 1'd0;
-reg           litedramcore_cmd_ready = 1'd0;
-reg           litedramcore_cmd_last = 1'd0;
-reg    [14:0] litedramcore_cmd_payload_a = 15'd0;
-reg     [2:0] litedramcore_cmd_payload_ba = 3'd0;
-reg           litedramcore_cmd_payload_cas = 1'd0;
-reg           litedramcore_cmd_payload_ras = 1'd0;
-reg           litedramcore_cmd_payload_we = 1'd0;
-reg           litedramcore_cmd_payload_is_read = 1'd0;
-reg           litedramcore_cmd_payload_is_write = 1'd0;
-wire          litedramcore_wants_refresh;
-wire          litedramcore_wants_zqcs;
-wire          litedramcore_timer_wait;
-wire          litedramcore_timer_done0;
-wire    [9:0] litedramcore_timer_count0;
-wire          litedramcore_timer_done1;
-reg     [9:0] litedramcore_timer_count1 = 10'd781;
-wire          litedramcore_postponer_req_i;
-reg           litedramcore_postponer_req_o = 1'd0;
-reg           litedramcore_postponer_count = 1'd0;
-reg           litedramcore_sequencer_start0 = 1'd0;
-wire          litedramcore_sequencer_done0;
-wire          litedramcore_sequencer_start1;
-reg           litedramcore_sequencer_done1 = 1'd0;
-reg     [5:0] litedramcore_sequencer_counter = 6'd0;
-reg           litedramcore_sequencer_count = 1'd0;
-wire          litedramcore_zqcs_timer_wait;
-wire          litedramcore_zqcs_timer_done0;
-wire   [26:0] litedramcore_zqcs_timer_count0;
-wire          litedramcore_zqcs_timer_done1;
-reg    [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
-reg           litedramcore_zqcs_executer_start = 1'd0;
-reg           litedramcore_zqcs_executer_done = 1'd0;
-reg     [4:0] litedramcore_zqcs_executer_counter = 5'd0;
-wire          litedramcore_bankmachine0_req_valid;
-wire          litedramcore_bankmachine0_req_ready;
-wire          litedramcore_bankmachine0_req_we;
-wire   [21:0] litedramcore_bankmachine0_req_addr;
-wire          litedramcore_bankmachine0_req_lock;
-reg           litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine0_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine0_refresh_req;
-reg           litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg    [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0;
-wire    [2:0] litedramcore_bankmachine0_cmd_payload_ba;
-reg           litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine0_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine0_sink_valid;
-wire          litedramcore_bankmachine0_sink_ready;
-reg           litedramcore_bankmachine0_sink_first = 1'd0;
-reg           litedramcore_bankmachine0_sink_last = 1'd0;
-wire          litedramcore_bankmachine0_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine0_sink_payload_addr;
-wire          litedramcore_bankmachine0_source_valid;
-wire          litedramcore_bankmachine0_source_ready;
-wire          litedramcore_bankmachine0_source_first;
-wire          litedramcore_bankmachine0_source_last;
-wire          litedramcore_bankmachine0_source_payload_we;
-wire   [21:0] litedramcore_bankmachine0_source_payload_addr;
-wire          litedramcore_bankmachine0_syncfifo0_we;
-wire          litedramcore_bankmachine0_syncfifo0_writable;
-wire          litedramcore_bankmachine0_syncfifo0_re;
-wire          litedramcore_bankmachine0_syncfifo0_readable;
-wire   [24:0] litedramcore_bankmachine0_syncfifo0_din;
-wire   [24:0] litedramcore_bankmachine0_syncfifo0_dout;
-reg     [4:0] litedramcore_bankmachine0_level = 5'd0;
-reg           litedramcore_bankmachine0_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine0_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine0_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0;
-wire   [24:0] litedramcore_bankmachine0_wrport_dat_r;
-wire          litedramcore_bankmachine0_wrport_we;
-wire   [24:0] litedramcore_bankmachine0_wrport_dat_w;
-wire          litedramcore_bankmachine0_do_read;
-wire    [3:0] litedramcore_bankmachine0_rdport_adr;
-wire   [24:0] litedramcore_bankmachine0_rdport_dat_r;
-wire          litedramcore_bankmachine0_fifo_in_payload_we;
-wire   [21:0] litedramcore_bankmachine0_fifo_in_payload_addr;
-wire          litedramcore_bankmachine0_fifo_in_first;
-wire          litedramcore_bankmachine0_fifo_in_last;
-wire          litedramcore_bankmachine0_fifo_out_payload_we;
-wire   [21:0] litedramcore_bankmachine0_fifo_out_payload_addr;
-wire          litedramcore_bankmachine0_fifo_out_first;
-wire          litedramcore_bankmachine0_fifo_out_last;
-wire          litedramcore_bankmachine0_sink_sink_valid;
-wire          litedramcore_bankmachine0_sink_sink_ready;
-wire          litedramcore_bankmachine0_sink_sink_first;
-wire          litedramcore_bankmachine0_sink_sink_last;
-wire          litedramcore_bankmachine0_sink_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine0_sink_sink_payload_addr;
-wire          litedramcore_bankmachine0_source_source_valid;
-wire          litedramcore_bankmachine0_source_source_ready;
-wire          litedramcore_bankmachine0_source_source_first;
-wire          litedramcore_bankmachine0_source_source_last;
-wire          litedramcore_bankmachine0_source_source_payload_we;
-wire   [21:0] litedramcore_bankmachine0_source_source_payload_addr;
-wire          litedramcore_bankmachine0_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine0_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine0_pipe_valid_sink_first;
-wire          litedramcore_bankmachine0_pipe_valid_sink_last;
-wire          litedramcore_bankmachine0_pipe_valid_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine0_pipe_valid_source_ready;
-reg           litedramcore_bankmachine0_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine0_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0;
-reg    [21:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 22'd0;
-reg    [14:0] litedramcore_bankmachine0_row = 15'd0;
-reg           litedramcore_bankmachine0_row_opened = 1'd0;
-wire          litedramcore_bankmachine0_row_hit;
-reg           litedramcore_bankmachine0_row_open = 1'd0;
-reg           litedramcore_bankmachine0_row_close = 1'd0;
-reg           litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine0_twtpcon_valid;
+wire          main_clkin;
+wire          main_clkout0;
+wire          main_clkout1;
+wire          main_clkout2;
+wire          main_clkout3;
+wire          main_clkout_buf0;
+wire          main_clkout_buf1;
+wire          main_clkout_buf2;
+wire          main_clkout_buf3;
+reg           main_ic_reset = 1'd1;
+reg           main_init_done_re = 1'd0;
+reg           main_init_done_storage = 1'd0;
+reg           main_init_error_re = 1'd0;
+reg           main_init_error_storage = 1'd0;
+wire          main_k7ddrphy0;
+wire          main_k7ddrphy1;
+wire          main_k7ddrphy2;
+wire          main_k7ddrphy3;
+reg     [7:0] main_k7ddrphy_bitslip00 = 8'd0;
+reg     [7:0] main_k7ddrphy_bitslip01 = 8'd0;
+reg     [7:0] main_k7ddrphy_bitslip02 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip03;
+reg     [7:0] main_k7ddrphy_bitslip04 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip0_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip0_r1 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip0_r2 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip0_r3 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip0_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip0_value1 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip0_value2 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip0_value3 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip10 = 8'd0;
+reg     [7:0] main_k7ddrphy_bitslip100 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip101;
+reg     [7:0] main_k7ddrphy_bitslip102 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip10_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip10_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip10_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip10_value1 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip11 = 8'd0;
+reg     [7:0] main_k7ddrphy_bitslip110 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip111;
+reg     [7:0] main_k7ddrphy_bitslip112 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip11_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip11_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip11_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip11_value1 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip12 = 8'd0;
+reg     [7:0] main_k7ddrphy_bitslip120 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip121;
+reg     [7:0] main_k7ddrphy_bitslip122 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip12_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip12_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip12_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip12_value1 = 3'd7;
+wire    [7:0] main_k7ddrphy_bitslip13;
+reg     [7:0] main_k7ddrphy_bitslip130 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip131;
+reg     [7:0] main_k7ddrphy_bitslip132 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip13_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip13_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip13_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip13_value1 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip14 = 8'd0;
+reg     [7:0] main_k7ddrphy_bitslip140 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip141;
+reg     [7:0] main_k7ddrphy_bitslip142 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip14_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip14_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip14_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip14_value1 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip150 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip151;
+reg     [7:0] main_k7ddrphy_bitslip152 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip15_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip15_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip15_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip15_value1 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip160 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip161;
+reg     [7:0] main_k7ddrphy_bitslip162 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip16_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip16_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip16_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip16_value1 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip170 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip171;
+reg     [7:0] main_k7ddrphy_bitslip172 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip17_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip17_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip17_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip17_value1 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip180 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip181;
+reg     [7:0] main_k7ddrphy_bitslip182 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip18_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip18_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip18_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip18_value1 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip190 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip191;
+reg     [7:0] main_k7ddrphy_bitslip192 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip19_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip19_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip19_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip19_value1 = 3'd7;
+reg    [15:0] main_k7ddrphy_bitslip1_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip1_r1 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip1_r2 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip1_r3 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip1_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip1_value1 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip1_value2 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip1_value3 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip20 = 8'd0;
+reg     [7:0] main_k7ddrphy_bitslip200 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip201;
+reg     [7:0] main_k7ddrphy_bitslip202 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip20_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip20_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip20_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip20_value1 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip21 = 8'd0;
+reg     [7:0] main_k7ddrphy_bitslip210 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip211;
+reg     [7:0] main_k7ddrphy_bitslip212 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip21_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip21_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip21_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip21_value1 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip22 = 8'd0;
+reg     [7:0] main_k7ddrphy_bitslip220 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip221;
+reg     [7:0] main_k7ddrphy_bitslip222 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip22_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip22_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip22_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip22_value1 = 3'd7;
+wire    [7:0] main_k7ddrphy_bitslip23;
+reg     [7:0] main_k7ddrphy_bitslip230 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip231;
+reg     [7:0] main_k7ddrphy_bitslip232 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip23_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip23_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip23_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip23_value1 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip24 = 8'd0;
+reg     [7:0] main_k7ddrphy_bitslip240 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip241;
+reg     [7:0] main_k7ddrphy_bitslip242 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip24_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip24_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip24_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip24_value1 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip250 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip251;
+reg     [7:0] main_k7ddrphy_bitslip252 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip25_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip25_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip25_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip25_value1 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip260 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip261;
+reg     [7:0] main_k7ddrphy_bitslip262 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip26_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip26_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip26_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip26_value1 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip270 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip271;
+reg     [7:0] main_k7ddrphy_bitslip272 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip27_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip27_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip27_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip27_value1 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip280 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip281;
+reg     [7:0] main_k7ddrphy_bitslip282 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip28_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip28_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip28_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip28_value1 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip290 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip291;
+reg     [7:0] main_k7ddrphy_bitslip292 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip29_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip29_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip29_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip29_value1 = 3'd7;
+reg    [15:0] main_k7ddrphy_bitslip2_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip2_r1 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip2_r2 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip2_r3 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip2_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip2_value1 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip2_value2 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip2_value3 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip30 = 8'd0;
+reg     [7:0] main_k7ddrphy_bitslip300 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip301;
+reg     [7:0] main_k7ddrphy_bitslip302 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip30_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip30_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip30_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip30_value1 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip31 = 8'd0;
+reg     [7:0] main_k7ddrphy_bitslip310 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip311;
+reg     [7:0] main_k7ddrphy_bitslip312 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip31_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip31_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip31_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip31_value1 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip32 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip33;
+reg     [7:0] main_k7ddrphy_bitslip34 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip3_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip3_r1 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip3_r2 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip3_r3 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip3_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip3_value1 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip3_value2 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip3_value3 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip40 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip41;
+reg     [7:0] main_k7ddrphy_bitslip42 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip4_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip4_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip4_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip4_value1 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip50 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip51;
+reg     [7:0] main_k7ddrphy_bitslip52 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip5_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip5_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip5_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip5_value1 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip60 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip61;
+reg     [7:0] main_k7ddrphy_bitslip62 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip6_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip6_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip6_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip6_value1 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip70 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip71;
+reg     [7:0] main_k7ddrphy_bitslip72 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip7_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip7_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip7_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip7_value1 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip80 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip81;
+reg     [7:0] main_k7ddrphy_bitslip82 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip8_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip8_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip8_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip8_value1 = 3'd7;
+reg     [7:0] main_k7ddrphy_bitslip90 = 8'd0;
+wire    [7:0] main_k7ddrphy_bitslip91;
+reg     [7:0] main_k7ddrphy_bitslip92 = 8'd0;
+reg    [15:0] main_k7ddrphy_bitslip9_r0 = 16'd0;
+reg    [15:0] main_k7ddrphy_bitslip9_r1 = 16'd0;
+reg     [2:0] main_k7ddrphy_bitslip9_value0 = 3'd7;
+reg     [2:0] main_k7ddrphy_bitslip9_value1 = 3'd7;
+wire          main_k7ddrphy_cdly_inc_r;
+reg           main_k7ddrphy_cdly_inc_re = 1'd0;
+reg           main_k7ddrphy_cdly_inc_w = 1'd0;
+reg           main_k7ddrphy_cdly_inc_we = 1'd0;
+wire          main_k7ddrphy_cdly_rst_r;
+reg           main_k7ddrphy_cdly_rst_re = 1'd0;
+reg           main_k7ddrphy_cdly_rst_w = 1'd0;
+reg           main_k7ddrphy_cdly_rst_we = 1'd0;
+wire          main_k7ddrphy_dfi_p0_act_n;
+wire   [14:0] main_k7ddrphy_dfi_p0_address;
+wire    [2:0] main_k7ddrphy_dfi_p0_bank;
+wire          main_k7ddrphy_dfi_p0_cas_n;
+wire          main_k7ddrphy_dfi_p0_cke;
+wire          main_k7ddrphy_dfi_p0_cs_n;
+wire          main_k7ddrphy_dfi_p0_odt;
+wire          main_k7ddrphy_dfi_p0_ras_n;
+reg    [63:0] main_k7ddrphy_dfi_p0_rddata = 64'd0;
+wire          main_k7ddrphy_dfi_p0_rddata_en;
+wire          main_k7ddrphy_dfi_p0_rddata_valid;
+wire          main_k7ddrphy_dfi_p0_reset_n;
+wire          main_k7ddrphy_dfi_p0_we_n;
+wire   [63:0] main_k7ddrphy_dfi_p0_wrdata;
+wire          main_k7ddrphy_dfi_p0_wrdata_en;
+wire    [7:0] main_k7ddrphy_dfi_p0_wrdata_mask;
+wire          main_k7ddrphy_dfi_p1_act_n;
+wire   [14:0] main_k7ddrphy_dfi_p1_address;
+wire    [2:0] main_k7ddrphy_dfi_p1_bank;
+wire          main_k7ddrphy_dfi_p1_cas_n;
+wire          main_k7ddrphy_dfi_p1_cke;
+wire          main_k7ddrphy_dfi_p1_cs_n;
+wire          main_k7ddrphy_dfi_p1_odt;
+wire          main_k7ddrphy_dfi_p1_ras_n;
+reg    [63:0] main_k7ddrphy_dfi_p1_rddata = 64'd0;
+wire          main_k7ddrphy_dfi_p1_rddata_en;
+wire          main_k7ddrphy_dfi_p1_rddata_valid;
+wire          main_k7ddrphy_dfi_p1_reset_n;
+wire          main_k7ddrphy_dfi_p1_we_n;
+wire   [63:0] main_k7ddrphy_dfi_p1_wrdata;
+wire          main_k7ddrphy_dfi_p1_wrdata_en;
+wire    [7:0] main_k7ddrphy_dfi_p1_wrdata_mask;
+wire          main_k7ddrphy_dfi_p2_act_n;
+wire   [14:0] main_k7ddrphy_dfi_p2_address;
+wire    [2:0] main_k7ddrphy_dfi_p2_bank;
+wire          main_k7ddrphy_dfi_p2_cas_n;
+wire          main_k7ddrphy_dfi_p2_cke;
+wire          main_k7ddrphy_dfi_p2_cs_n;
+wire          main_k7ddrphy_dfi_p2_odt;
+wire          main_k7ddrphy_dfi_p2_ras_n;
+reg    [63:0] main_k7ddrphy_dfi_p2_rddata = 64'd0;
+wire          main_k7ddrphy_dfi_p2_rddata_en;
+wire          main_k7ddrphy_dfi_p2_rddata_valid;
+wire          main_k7ddrphy_dfi_p2_reset_n;
+wire          main_k7ddrphy_dfi_p2_we_n;
+wire   [63:0] main_k7ddrphy_dfi_p2_wrdata;
+wire          main_k7ddrphy_dfi_p2_wrdata_en;
+wire    [7:0] main_k7ddrphy_dfi_p2_wrdata_mask;
+wire          main_k7ddrphy_dfi_p3_act_n;
+wire   [14:0] main_k7ddrphy_dfi_p3_address;
+wire    [2:0] main_k7ddrphy_dfi_p3_bank;
+wire          main_k7ddrphy_dfi_p3_cas_n;
+wire          main_k7ddrphy_dfi_p3_cke;
+wire          main_k7ddrphy_dfi_p3_cs_n;
+wire          main_k7ddrphy_dfi_p3_odt;
+wire          main_k7ddrphy_dfi_p3_ras_n;
+reg    [63:0] main_k7ddrphy_dfi_p3_rddata = 64'd0;
+wire          main_k7ddrphy_dfi_p3_rddata_en;
+wire          main_k7ddrphy_dfi_p3_rddata_valid;
+wire          main_k7ddrphy_dfi_p3_reset_n;
+wire          main_k7ddrphy_dfi_p3_we_n;
+wire   [63:0] main_k7ddrphy_dfi_p3_wrdata;
+wire          main_k7ddrphy_dfi_p3_wrdata_en;
+wire    [7:0] main_k7ddrphy_dfi_p3_wrdata_mask;
+reg           main_k7ddrphy_dly_sel_re = 1'd0;
+reg     [3:0] main_k7ddrphy_dly_sel_storage = 4'd0;
+wire          main_k7ddrphy_dm_o_nodelay0;
+wire          main_k7ddrphy_dm_o_nodelay1;
+wire          main_k7ddrphy_dm_o_nodelay2;
+wire          main_k7ddrphy_dm_o_nodelay3;
+wire          main_k7ddrphy_dq_i_delayed0;
+wire          main_k7ddrphy_dq_i_delayed1;
+wire          main_k7ddrphy_dq_i_delayed10;
+wire          main_k7ddrphy_dq_i_delayed11;
+wire          main_k7ddrphy_dq_i_delayed12;
+wire          main_k7ddrphy_dq_i_delayed13;
+wire          main_k7ddrphy_dq_i_delayed14;
+wire          main_k7ddrphy_dq_i_delayed15;
+wire          main_k7ddrphy_dq_i_delayed16;
+wire          main_k7ddrphy_dq_i_delayed17;
+wire          main_k7ddrphy_dq_i_delayed18;
+wire          main_k7ddrphy_dq_i_delayed19;
+wire          main_k7ddrphy_dq_i_delayed2;
+wire          main_k7ddrphy_dq_i_delayed20;
+wire          main_k7ddrphy_dq_i_delayed21;
+wire          main_k7ddrphy_dq_i_delayed22;
+wire          main_k7ddrphy_dq_i_delayed23;
+wire          main_k7ddrphy_dq_i_delayed24;
+wire          main_k7ddrphy_dq_i_delayed25;
+wire          main_k7ddrphy_dq_i_delayed26;
+wire          main_k7ddrphy_dq_i_delayed27;
+wire          main_k7ddrphy_dq_i_delayed28;
+wire          main_k7ddrphy_dq_i_delayed29;
+wire          main_k7ddrphy_dq_i_delayed3;
+wire          main_k7ddrphy_dq_i_delayed30;
+wire          main_k7ddrphy_dq_i_delayed31;
+wire          main_k7ddrphy_dq_i_delayed4;
+wire          main_k7ddrphy_dq_i_delayed5;
+wire          main_k7ddrphy_dq_i_delayed6;
+wire          main_k7ddrphy_dq_i_delayed7;
+wire          main_k7ddrphy_dq_i_delayed8;
+wire          main_k7ddrphy_dq_i_delayed9;
+wire          main_k7ddrphy_dq_i_nodelay0;
+wire          main_k7ddrphy_dq_i_nodelay1;
+wire          main_k7ddrphy_dq_i_nodelay10;
+wire          main_k7ddrphy_dq_i_nodelay11;
+wire          main_k7ddrphy_dq_i_nodelay12;
+wire          main_k7ddrphy_dq_i_nodelay13;
+wire          main_k7ddrphy_dq_i_nodelay14;
+wire          main_k7ddrphy_dq_i_nodelay15;
+wire          main_k7ddrphy_dq_i_nodelay16;
+wire          main_k7ddrphy_dq_i_nodelay17;
+wire          main_k7ddrphy_dq_i_nodelay18;
+wire          main_k7ddrphy_dq_i_nodelay19;
+wire          main_k7ddrphy_dq_i_nodelay2;
+wire          main_k7ddrphy_dq_i_nodelay20;
+wire          main_k7ddrphy_dq_i_nodelay21;
+wire          main_k7ddrphy_dq_i_nodelay22;
+wire          main_k7ddrphy_dq_i_nodelay23;
+wire          main_k7ddrphy_dq_i_nodelay24;
+wire          main_k7ddrphy_dq_i_nodelay25;
+wire          main_k7ddrphy_dq_i_nodelay26;
+wire          main_k7ddrphy_dq_i_nodelay27;
+wire          main_k7ddrphy_dq_i_nodelay28;
+wire          main_k7ddrphy_dq_i_nodelay29;
+wire          main_k7ddrphy_dq_i_nodelay3;
+wire          main_k7ddrphy_dq_i_nodelay30;
+wire          main_k7ddrphy_dq_i_nodelay31;
+wire          main_k7ddrphy_dq_i_nodelay4;
+wire          main_k7ddrphy_dq_i_nodelay5;
+wire          main_k7ddrphy_dq_i_nodelay6;
+wire          main_k7ddrphy_dq_i_nodelay7;
+wire          main_k7ddrphy_dq_i_nodelay8;
+wire          main_k7ddrphy_dq_i_nodelay9;
+wire          main_k7ddrphy_dq_o_delayed0;
+wire          main_k7ddrphy_dq_o_delayed1;
+wire          main_k7ddrphy_dq_o_delayed10;
+wire          main_k7ddrphy_dq_o_delayed11;
+wire          main_k7ddrphy_dq_o_delayed12;
+wire          main_k7ddrphy_dq_o_delayed13;
+wire          main_k7ddrphy_dq_o_delayed14;
+wire          main_k7ddrphy_dq_o_delayed15;
+wire          main_k7ddrphy_dq_o_delayed16;
+wire          main_k7ddrphy_dq_o_delayed17;
+wire          main_k7ddrphy_dq_o_delayed18;
+wire          main_k7ddrphy_dq_o_delayed19;
+wire          main_k7ddrphy_dq_o_delayed2;
+wire          main_k7ddrphy_dq_o_delayed20;
+wire          main_k7ddrphy_dq_o_delayed21;
+wire          main_k7ddrphy_dq_o_delayed22;
+wire          main_k7ddrphy_dq_o_delayed23;
+wire          main_k7ddrphy_dq_o_delayed24;
+wire          main_k7ddrphy_dq_o_delayed25;
+wire          main_k7ddrphy_dq_o_delayed26;
+wire          main_k7ddrphy_dq_o_delayed27;
+wire          main_k7ddrphy_dq_o_delayed28;
+wire          main_k7ddrphy_dq_o_delayed29;
+wire          main_k7ddrphy_dq_o_delayed3;
+wire          main_k7ddrphy_dq_o_delayed30;
+wire          main_k7ddrphy_dq_o_delayed31;
+wire          main_k7ddrphy_dq_o_delayed4;
+wire          main_k7ddrphy_dq_o_delayed5;
+wire          main_k7ddrphy_dq_o_delayed6;
+wire          main_k7ddrphy_dq_o_delayed7;
+wire          main_k7ddrphy_dq_o_delayed8;
+wire          main_k7ddrphy_dq_o_delayed9;
+wire          main_k7ddrphy_dq_o_nodelay0;
+wire          main_k7ddrphy_dq_o_nodelay1;
+wire          main_k7ddrphy_dq_o_nodelay10;
+wire          main_k7ddrphy_dq_o_nodelay11;
+wire          main_k7ddrphy_dq_o_nodelay12;
+wire          main_k7ddrphy_dq_o_nodelay13;
+wire          main_k7ddrphy_dq_o_nodelay14;
+wire          main_k7ddrphy_dq_o_nodelay15;
+wire          main_k7ddrphy_dq_o_nodelay16;
+wire          main_k7ddrphy_dq_o_nodelay17;
+wire          main_k7ddrphy_dq_o_nodelay18;
+wire          main_k7ddrphy_dq_o_nodelay19;
+wire          main_k7ddrphy_dq_o_nodelay2;
+wire          main_k7ddrphy_dq_o_nodelay20;
+wire          main_k7ddrphy_dq_o_nodelay21;
+wire          main_k7ddrphy_dq_o_nodelay22;
+wire          main_k7ddrphy_dq_o_nodelay23;
+wire          main_k7ddrphy_dq_o_nodelay24;
+wire          main_k7ddrphy_dq_o_nodelay25;
+wire          main_k7ddrphy_dq_o_nodelay26;
+wire          main_k7ddrphy_dq_o_nodelay27;
+wire          main_k7ddrphy_dq_o_nodelay28;
+wire          main_k7ddrphy_dq_o_nodelay29;
+wire          main_k7ddrphy_dq_o_nodelay3;
+wire          main_k7ddrphy_dq_o_nodelay30;
+wire          main_k7ddrphy_dq_o_nodelay31;
+wire          main_k7ddrphy_dq_o_nodelay4;
+wire          main_k7ddrphy_dq_o_nodelay5;
+wire          main_k7ddrphy_dq_o_nodelay6;
+wire          main_k7ddrphy_dq_o_nodelay7;
+wire          main_k7ddrphy_dq_o_nodelay8;
+wire          main_k7ddrphy_dq_o_nodelay9;
+wire          main_k7ddrphy_dq_oe;
+wire          main_k7ddrphy_dq_oe_delay_tappeddelayline;
+reg           main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg           main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+wire          main_k7ddrphy_dq_t0;
+wire          main_k7ddrphy_dq_t1;
+wire          main_k7ddrphy_dq_t10;
+wire          main_k7ddrphy_dq_t11;
+wire          main_k7ddrphy_dq_t12;
+wire          main_k7ddrphy_dq_t13;
+wire          main_k7ddrphy_dq_t14;
+wire          main_k7ddrphy_dq_t15;
+wire          main_k7ddrphy_dq_t16;
+wire          main_k7ddrphy_dq_t17;
+wire          main_k7ddrphy_dq_t18;
+wire          main_k7ddrphy_dq_t19;
+wire          main_k7ddrphy_dq_t2;
+wire          main_k7ddrphy_dq_t20;
+wire          main_k7ddrphy_dq_t21;
+wire          main_k7ddrphy_dq_t22;
+wire          main_k7ddrphy_dq_t23;
+wire          main_k7ddrphy_dq_t24;
+wire          main_k7ddrphy_dq_t25;
+wire          main_k7ddrphy_dq_t26;
+wire          main_k7ddrphy_dq_t27;
+wire          main_k7ddrphy_dq_t28;
+wire          main_k7ddrphy_dq_t29;
+wire          main_k7ddrphy_dq_t3;
+wire          main_k7ddrphy_dq_t30;
+wire          main_k7ddrphy_dq_t31;
+wire          main_k7ddrphy_dq_t4;
+wire          main_k7ddrphy_dq_t5;
+wire          main_k7ddrphy_dq_t6;
+wire          main_k7ddrphy_dq_t7;
+wire          main_k7ddrphy_dq_t8;
+wire          main_k7ddrphy_dq_t9;
+wire          main_k7ddrphy_dqs_o_delayed0;
+wire          main_k7ddrphy_dqs_o_delayed1;
+wire          main_k7ddrphy_dqs_o_delayed2;
+wire          main_k7ddrphy_dqs_o_delayed3;
+wire          main_k7ddrphy_dqs_o_no_delay0;
+wire          main_k7ddrphy_dqs_o_no_delay1;
+wire          main_k7ddrphy_dqs_o_no_delay2;
+wire          main_k7ddrphy_dqs_o_no_delay3;
+reg           main_k7ddrphy_dqs_oe = 1'd0;
+wire          main_k7ddrphy_dqs_oe_delay_tappeddelayline;
+reg           main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg           main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+wire          main_k7ddrphy_dqs_postamble;
+wire          main_k7ddrphy_dqs_preamble;
+wire          main_k7ddrphy_dqs_t0;
+wire          main_k7ddrphy_dqs_t1;
+wire          main_k7ddrphy_dqs_t2;
+wire          main_k7ddrphy_dqs_t3;
+reg           main_k7ddrphy_dqspattern0 = 1'd0;
+reg           main_k7ddrphy_dqspattern1 = 1'd0;
+reg     [7:0] main_k7ddrphy_dqspattern_o = 8'd0;
+reg           main_k7ddrphy_half_sys8x_taps_re = 1'd0;
+reg     [4:0] main_k7ddrphy_half_sys8x_taps_storage = 5'd8;
+wire          main_k7ddrphy_oq0;
+wire          main_k7ddrphy_oq1;
+wire          main_k7ddrphy_oq10;
+wire          main_k7ddrphy_oq11;
+wire          main_k7ddrphy_oq12;
+wire          main_k7ddrphy_oq13;
+wire          main_k7ddrphy_oq14;
+wire          main_k7ddrphy_oq15;
+wire          main_k7ddrphy_oq16;
+wire          main_k7ddrphy_oq17;
+wire          main_k7ddrphy_oq18;
+wire          main_k7ddrphy_oq19;
+wire          main_k7ddrphy_oq2;
+wire          main_k7ddrphy_oq20;
+wire          main_k7ddrphy_oq21;
+wire          main_k7ddrphy_oq22;
+wire          main_k7ddrphy_oq23;
+wire          main_k7ddrphy_oq24;
+wire          main_k7ddrphy_oq3;
+wire          main_k7ddrphy_oq4;
+wire          main_k7ddrphy_oq5;
+wire          main_k7ddrphy_oq6;
+wire          main_k7ddrphy_oq7;
+wire          main_k7ddrphy_oq8;
+wire          main_k7ddrphy_oq9;
+wire    [2:0] main_k7ddrphy_pads_ba;
+reg           main_k7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
+reg           main_k7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
+reg           main_k7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
+reg           main_k7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
+reg           main_k7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
+reg           main_k7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
+reg           main_k7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
+reg           main_k7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
+wire          main_k7ddrphy_rdly_dq_bitslip_r;
+reg           main_k7ddrphy_rdly_dq_bitslip_re = 1'd0;
+wire          main_k7ddrphy_rdly_dq_bitslip_rst_r;
+reg           main_k7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
+reg           main_k7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+reg           main_k7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
+reg           main_k7ddrphy_rdly_dq_bitslip_w = 1'd0;
+reg           main_k7ddrphy_rdly_dq_bitslip_we = 1'd0;
+wire          main_k7ddrphy_rdly_dq_inc_r;
+reg           main_k7ddrphy_rdly_dq_inc_re = 1'd0;
+reg           main_k7ddrphy_rdly_dq_inc_w = 1'd0;
+reg           main_k7ddrphy_rdly_dq_inc_we = 1'd0;
+wire          main_k7ddrphy_rdly_dq_rst_r;
+reg           main_k7ddrphy_rdly_dq_rst_re = 1'd0;
+reg           main_k7ddrphy_rdly_dq_rst_w = 1'd0;
+reg           main_k7ddrphy_rdly_dq_rst_we = 1'd0;
+reg           main_k7ddrphy_rdphase_re = 1'd0;
+reg     [1:0] main_k7ddrphy_rdphase_storage = 2'd1;
+reg           main_k7ddrphy_rst_re = 1'd0;
+reg           main_k7ddrphy_rst_storage = 1'd0;
+wire          main_k7ddrphy_sd_clk_se_delayed;
+wire          main_k7ddrphy_sd_clk_se_nodelay;
+wire          main_k7ddrphy_wdly_dq_bitslip_r;
+reg           main_k7ddrphy_wdly_dq_bitslip_re = 1'd0;
+wire          main_k7ddrphy_wdly_dq_bitslip_rst_r;
+reg           main_k7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
+reg           main_k7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
+reg           main_k7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
+reg           main_k7ddrphy_wdly_dq_bitslip_w = 1'd0;
+reg           main_k7ddrphy_wdly_dq_bitslip_we = 1'd0;
+wire          main_k7ddrphy_wdly_dq_inc_r;
+reg           main_k7ddrphy_wdly_dq_inc_re = 1'd0;
+reg           main_k7ddrphy_wdly_dq_inc_w = 1'd0;
+reg           main_k7ddrphy_wdly_dq_inc_we = 1'd0;
+wire          main_k7ddrphy_wdly_dq_rst_r;
+reg           main_k7ddrphy_wdly_dq_rst_re = 1'd0;
+reg           main_k7ddrphy_wdly_dq_rst_w = 1'd0;
+reg           main_k7ddrphy_wdly_dq_rst_we = 1'd0;
+wire          main_k7ddrphy_wdly_dqs_inc_r;
+reg           main_k7ddrphy_wdly_dqs_inc_re = 1'd0;
+reg           main_k7ddrphy_wdly_dqs_inc_w = 1'd0;
+reg           main_k7ddrphy_wdly_dqs_inc_we = 1'd0;
+wire          main_k7ddrphy_wdly_dqs_rst_r;
+reg           main_k7ddrphy_wdly_dqs_rst_re = 1'd0;
+reg           main_k7ddrphy_wdly_dqs_rst_w = 1'd0;
+reg           main_k7ddrphy_wdly_dqs_rst_we = 1'd0;
+reg           main_k7ddrphy_wlevel_en_re = 1'd0;
+reg           main_k7ddrphy_wlevel_en_storage = 1'd0;
+wire          main_k7ddrphy_wlevel_strobe_r;
+reg           main_k7ddrphy_wlevel_strobe_re = 1'd0;
+reg           main_k7ddrphy_wlevel_strobe_w = 1'd0;
+reg           main_k7ddrphy_wlevel_strobe_we = 1'd0;
+reg           main_k7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
+reg           main_k7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
+reg           main_k7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
+reg           main_k7ddrphy_wrphase_re = 1'd0;
+reg     [1:0] main_k7ddrphy_wrphase_storage = 2'd2;
+reg           main_litedramcore_bankmachine0_auto_precharge = 1'd0;
+reg    [14:0] main_litedramcore_bankmachine0_cmd_payload_a = 15'd0;
+wire    [2:0] main_litedramcore_bankmachine0_cmd_payload_ba;
+reg           main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine0_consume = 4'd0;
+wire          main_litedramcore_bankmachine0_do_read;
+wire          main_litedramcore_bankmachine0_fifo_in_first;
+wire          main_litedramcore_bankmachine0_fifo_in_last;
+wire   [21:0] main_litedramcore_bankmachine0_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine0_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine0_fifo_out_first;
+wire          main_litedramcore_bankmachine0_fifo_out_last;
+wire   [21:0] main_litedramcore_bankmachine0_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine0_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine0_level = 5'd0;
+wire          main_litedramcore_bankmachine0_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine0_pipe_valid_sink_last;
+wire   [21:0] main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine0_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine0_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine0_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine0_pipe_valid_source_last = 1'd0;
+reg    [21:0] main_litedramcore_bankmachine0_pipe_valid_source_payload_addr = 22'd0;
+reg           main_litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine0_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine0_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine0_rdport_adr;
+wire   [24:0] main_litedramcore_bankmachine0_rdport_dat_r;
+reg           main_litedramcore_bankmachine0_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine0_refresh_req;
+reg           main_litedramcore_bankmachine0_replace = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine0_req_addr;
+wire          main_litedramcore_bankmachine0_req_lock;
+reg           main_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine0_req_ready;
+wire          main_litedramcore_bankmachine0_req_valid;
+reg           main_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine0_req_we;
+reg    [14:0] main_litedramcore_bankmachine0_row = 15'd0;
+reg           main_litedramcore_bankmachine0_row_close = 1'd0;
+reg           main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine0_row_hit;
+reg           main_litedramcore_bankmachine0_row_open = 1'd0;
+reg           main_litedramcore_bankmachine0_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine0_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine0_sink_last = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine0_sink_payload_addr;
+wire          main_litedramcore_bankmachine0_sink_payload_we;
+wire          main_litedramcore_bankmachine0_sink_ready;
+wire          main_litedramcore_bankmachine0_sink_sink_first;
+wire          main_litedramcore_bankmachine0_sink_sink_last;
+wire   [21:0] main_litedramcore_bankmachine0_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine0_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine0_sink_sink_ready;
+wire          main_litedramcore_bankmachine0_sink_sink_valid;
+wire          main_litedramcore_bankmachine0_sink_valid;
+wire          main_litedramcore_bankmachine0_source_first;
+wire          main_litedramcore_bankmachine0_source_last;
+wire   [21:0] main_litedramcore_bankmachine0_source_payload_addr;
+wire          main_litedramcore_bankmachine0_source_payload_we;
+wire          main_litedramcore_bankmachine0_source_ready;
+wire          main_litedramcore_bankmachine0_source_source_first;
+wire          main_litedramcore_bankmachine0_source_source_last;
+wire   [21:0] main_litedramcore_bankmachine0_source_source_payload_addr;
+wire          main_litedramcore_bankmachine0_source_source_payload_we;
+wire          main_litedramcore_bankmachine0_source_source_ready;
+wire          main_litedramcore_bankmachine0_source_source_valid;
+wire          main_litedramcore_bankmachine0_source_valid;
+wire   [24:0] main_litedramcore_bankmachine0_syncfifo0_din;
+wire   [24:0] main_litedramcore_bankmachine0_syncfifo0_dout;
+wire          main_litedramcore_bankmachine0_syncfifo0_re;
+wire          main_litedramcore_bankmachine0_syncfifo0_readable;
+wire          main_litedramcore_bankmachine0_syncfifo0_we;
+wire          main_litedramcore_bankmachine0_syncfifo0_writable;
+reg     [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine0_trccon_valid;
+reg           main_litedramcore_bankmachine0_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine0_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
-wire          litedramcore_bankmachine0_trascon_valid;
+reg           main_litedramcore_bankmachine0_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine0_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine0_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
-wire          litedramcore_bankmachine1_req_valid;
-wire          litedramcore_bankmachine1_req_ready;
-wire          litedramcore_bankmachine1_req_we;
-wire   [21:0] litedramcore_bankmachine1_req_addr;
-wire          litedramcore_bankmachine1_req_lock;
-reg           litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine1_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine1_refresh_req;
-reg           litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine1_cmd_ready = 1'd0;
-reg    [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0;
-wire    [2:0] litedramcore_bankmachine1_cmd_payload_ba;
-reg           litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine1_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine1_sink_valid;
-wire          litedramcore_bankmachine1_sink_ready;
-reg           litedramcore_bankmachine1_sink_first = 1'd0;
-reg           litedramcore_bankmachine1_sink_last = 1'd0;
-wire          litedramcore_bankmachine1_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine1_sink_payload_addr;
-wire          litedramcore_bankmachine1_source_valid;
-wire          litedramcore_bankmachine1_source_ready;
-wire          litedramcore_bankmachine1_source_first;
-wire          litedramcore_bankmachine1_source_last;
-wire          litedramcore_bankmachine1_source_payload_we;
-wire   [21:0] litedramcore_bankmachine1_source_payload_addr;
-wire          litedramcore_bankmachine1_syncfifo1_we;
-wire          litedramcore_bankmachine1_syncfifo1_writable;
-wire          litedramcore_bankmachine1_syncfifo1_re;
-wire          litedramcore_bankmachine1_syncfifo1_readable;
-wire   [24:0] litedramcore_bankmachine1_syncfifo1_din;
-wire   [24:0] litedramcore_bankmachine1_syncfifo1_dout;
-reg     [4:0] litedramcore_bankmachine1_level = 5'd0;
-reg           litedramcore_bankmachine1_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine1_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine1_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0;
-wire   [24:0] litedramcore_bankmachine1_wrport_dat_r;
-wire          litedramcore_bankmachine1_wrport_we;
-wire   [24:0] litedramcore_bankmachine1_wrport_dat_w;
-wire          litedramcore_bankmachine1_do_read;
-wire    [3:0] litedramcore_bankmachine1_rdport_adr;
-wire   [24:0] litedramcore_bankmachine1_rdport_dat_r;
-wire          litedramcore_bankmachine1_fifo_in_payload_we;
-wire   [21:0] litedramcore_bankmachine1_fifo_in_payload_addr;
-wire          litedramcore_bankmachine1_fifo_in_first;
-wire          litedramcore_bankmachine1_fifo_in_last;
-wire          litedramcore_bankmachine1_fifo_out_payload_we;
-wire   [21:0] litedramcore_bankmachine1_fifo_out_payload_addr;
-wire          litedramcore_bankmachine1_fifo_out_first;
-wire          litedramcore_bankmachine1_fifo_out_last;
-wire          litedramcore_bankmachine1_sink_sink_valid;
-wire          litedramcore_bankmachine1_sink_sink_ready;
-wire          litedramcore_bankmachine1_sink_sink_first;
-wire          litedramcore_bankmachine1_sink_sink_last;
-wire          litedramcore_bankmachine1_sink_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine1_sink_sink_payload_addr;
-wire          litedramcore_bankmachine1_source_source_valid;
-wire          litedramcore_bankmachine1_source_source_ready;
-wire          litedramcore_bankmachine1_source_source_first;
-wire          litedramcore_bankmachine1_source_source_last;
-wire          litedramcore_bankmachine1_source_source_payload_we;
-wire   [21:0] litedramcore_bankmachine1_source_source_payload_addr;
-wire          litedramcore_bankmachine1_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine1_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine1_pipe_valid_sink_first;
-wire          litedramcore_bankmachine1_pipe_valid_sink_last;
-wire          litedramcore_bankmachine1_pipe_valid_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine1_pipe_valid_source_ready;
-reg           litedramcore_bankmachine1_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine1_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0;
-reg    [21:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 22'd0;
-reg    [14:0] litedramcore_bankmachine1_row = 15'd0;
-reg           litedramcore_bankmachine1_row_opened = 1'd0;
-wire          litedramcore_bankmachine1_row_hit;
-reg           litedramcore_bankmachine1_row_open = 1'd0;
-reg           litedramcore_bankmachine1_row_close = 1'd0;
-reg           litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine1_twtpcon_valid;
+reg           main_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine0_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine0_wrport_adr = 4'd0;
+wire   [24:0] main_litedramcore_bankmachine0_wrport_dat_r;
+wire   [24:0] main_litedramcore_bankmachine0_wrport_dat_w;
+wire          main_litedramcore_bankmachine0_wrport_we;
+reg           main_litedramcore_bankmachine1_auto_precharge = 1'd0;
+reg    [14:0] main_litedramcore_bankmachine1_cmd_payload_a = 15'd0;
+wire    [2:0] main_litedramcore_bankmachine1_cmd_payload_ba;
+reg           main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine1_consume = 4'd0;
+wire          main_litedramcore_bankmachine1_do_read;
+wire          main_litedramcore_bankmachine1_fifo_in_first;
+wire          main_litedramcore_bankmachine1_fifo_in_last;
+wire   [21:0] main_litedramcore_bankmachine1_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine1_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine1_fifo_out_first;
+wire          main_litedramcore_bankmachine1_fifo_out_last;
+wire   [21:0] main_litedramcore_bankmachine1_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine1_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine1_level = 5'd0;
+wire          main_litedramcore_bankmachine1_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine1_pipe_valid_sink_last;
+wire   [21:0] main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine1_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine1_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine1_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine1_pipe_valid_source_last = 1'd0;
+reg    [21:0] main_litedramcore_bankmachine1_pipe_valid_source_payload_addr = 22'd0;
+reg           main_litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine1_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine1_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine1_rdport_adr;
+wire   [24:0] main_litedramcore_bankmachine1_rdport_dat_r;
+reg           main_litedramcore_bankmachine1_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine1_refresh_req;
+reg           main_litedramcore_bankmachine1_replace = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine1_req_addr;
+wire          main_litedramcore_bankmachine1_req_lock;
+reg           main_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine1_req_ready;
+wire          main_litedramcore_bankmachine1_req_valid;
+reg           main_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine1_req_we;
+reg    [14:0] main_litedramcore_bankmachine1_row = 15'd0;
+reg           main_litedramcore_bankmachine1_row_close = 1'd0;
+reg           main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine1_row_hit;
+reg           main_litedramcore_bankmachine1_row_open = 1'd0;
+reg           main_litedramcore_bankmachine1_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine1_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine1_sink_last = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine1_sink_payload_addr;
+wire          main_litedramcore_bankmachine1_sink_payload_we;
+wire          main_litedramcore_bankmachine1_sink_ready;
+wire          main_litedramcore_bankmachine1_sink_sink_first;
+wire          main_litedramcore_bankmachine1_sink_sink_last;
+wire   [21:0] main_litedramcore_bankmachine1_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine1_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine1_sink_sink_ready;
+wire          main_litedramcore_bankmachine1_sink_sink_valid;
+wire          main_litedramcore_bankmachine1_sink_valid;
+wire          main_litedramcore_bankmachine1_source_first;
+wire          main_litedramcore_bankmachine1_source_last;
+wire   [21:0] main_litedramcore_bankmachine1_source_payload_addr;
+wire          main_litedramcore_bankmachine1_source_payload_we;
+wire          main_litedramcore_bankmachine1_source_ready;
+wire          main_litedramcore_bankmachine1_source_source_first;
+wire          main_litedramcore_bankmachine1_source_source_last;
+wire   [21:0] main_litedramcore_bankmachine1_source_source_payload_addr;
+wire          main_litedramcore_bankmachine1_source_source_payload_we;
+wire          main_litedramcore_bankmachine1_source_source_ready;
+wire          main_litedramcore_bankmachine1_source_source_valid;
+wire          main_litedramcore_bankmachine1_source_valid;
+wire   [24:0] main_litedramcore_bankmachine1_syncfifo1_din;
+wire   [24:0] main_litedramcore_bankmachine1_syncfifo1_dout;
+wire          main_litedramcore_bankmachine1_syncfifo1_re;
+wire          main_litedramcore_bankmachine1_syncfifo1_readable;
+wire          main_litedramcore_bankmachine1_syncfifo1_we;
+wire          main_litedramcore_bankmachine1_syncfifo1_writable;
+reg     [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine1_trccon_valid;
+reg           main_litedramcore_bankmachine1_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine1_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
-wire          litedramcore_bankmachine1_trascon_valid;
+reg           main_litedramcore_bankmachine1_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine1_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine1_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
-wire          litedramcore_bankmachine2_req_valid;
-wire          litedramcore_bankmachine2_req_ready;
-wire          litedramcore_bankmachine2_req_we;
-wire   [21:0] litedramcore_bankmachine2_req_addr;
-wire          litedramcore_bankmachine2_req_lock;
-reg           litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine2_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine2_refresh_req;
-reg           litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine2_cmd_ready = 1'd0;
-reg    [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0;
-wire    [2:0] litedramcore_bankmachine2_cmd_payload_ba;
-reg           litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine2_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine2_sink_valid;
-wire          litedramcore_bankmachine2_sink_ready;
-reg           litedramcore_bankmachine2_sink_first = 1'd0;
-reg           litedramcore_bankmachine2_sink_last = 1'd0;
-wire          litedramcore_bankmachine2_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine2_sink_payload_addr;
-wire          litedramcore_bankmachine2_source_valid;
-wire          litedramcore_bankmachine2_source_ready;
-wire          litedramcore_bankmachine2_source_first;
-wire          litedramcore_bankmachine2_source_last;
-wire          litedramcore_bankmachine2_source_payload_we;
-wire   [21:0] litedramcore_bankmachine2_source_payload_addr;
-wire          litedramcore_bankmachine2_syncfifo2_we;
-wire          litedramcore_bankmachine2_syncfifo2_writable;
-wire          litedramcore_bankmachine2_syncfifo2_re;
-wire          litedramcore_bankmachine2_syncfifo2_readable;
-wire   [24:0] litedramcore_bankmachine2_syncfifo2_din;
-wire   [24:0] litedramcore_bankmachine2_syncfifo2_dout;
-reg     [4:0] litedramcore_bankmachine2_level = 5'd0;
-reg           litedramcore_bankmachine2_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine2_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine2_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0;
-wire   [24:0] litedramcore_bankmachine2_wrport_dat_r;
-wire          litedramcore_bankmachine2_wrport_we;
-wire   [24:0] litedramcore_bankmachine2_wrport_dat_w;
-wire          litedramcore_bankmachine2_do_read;
-wire    [3:0] litedramcore_bankmachine2_rdport_adr;
-wire   [24:0] litedramcore_bankmachine2_rdport_dat_r;
-wire          litedramcore_bankmachine2_fifo_in_payload_we;
-wire   [21:0] litedramcore_bankmachine2_fifo_in_payload_addr;
-wire          litedramcore_bankmachine2_fifo_in_first;
-wire          litedramcore_bankmachine2_fifo_in_last;
-wire          litedramcore_bankmachine2_fifo_out_payload_we;
-wire   [21:0] litedramcore_bankmachine2_fifo_out_payload_addr;
-wire          litedramcore_bankmachine2_fifo_out_first;
-wire          litedramcore_bankmachine2_fifo_out_last;
-wire          litedramcore_bankmachine2_sink_sink_valid;
-wire          litedramcore_bankmachine2_sink_sink_ready;
-wire          litedramcore_bankmachine2_sink_sink_first;
-wire          litedramcore_bankmachine2_sink_sink_last;
-wire          litedramcore_bankmachine2_sink_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine2_sink_sink_payload_addr;
-wire          litedramcore_bankmachine2_source_source_valid;
-wire          litedramcore_bankmachine2_source_source_ready;
-wire          litedramcore_bankmachine2_source_source_first;
-wire          litedramcore_bankmachine2_source_source_last;
-wire          litedramcore_bankmachine2_source_source_payload_we;
-wire   [21:0] litedramcore_bankmachine2_source_source_payload_addr;
-wire          litedramcore_bankmachine2_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine2_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine2_pipe_valid_sink_first;
-wire          litedramcore_bankmachine2_pipe_valid_sink_last;
-wire          litedramcore_bankmachine2_pipe_valid_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine2_pipe_valid_source_ready;
-reg           litedramcore_bankmachine2_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine2_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0;
-reg    [21:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 22'd0;
-reg    [14:0] litedramcore_bankmachine2_row = 15'd0;
-reg           litedramcore_bankmachine2_row_opened = 1'd0;
-wire          litedramcore_bankmachine2_row_hit;
-reg           litedramcore_bankmachine2_row_open = 1'd0;
-reg           litedramcore_bankmachine2_row_close = 1'd0;
-reg           litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine2_twtpcon_valid;
+reg           main_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine1_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine1_wrport_adr = 4'd0;
+wire   [24:0] main_litedramcore_bankmachine1_wrport_dat_r;
+wire   [24:0] main_litedramcore_bankmachine1_wrport_dat_w;
+wire          main_litedramcore_bankmachine1_wrport_we;
+reg           main_litedramcore_bankmachine2_auto_precharge = 1'd0;
+reg    [14:0] main_litedramcore_bankmachine2_cmd_payload_a = 15'd0;
+wire    [2:0] main_litedramcore_bankmachine2_cmd_payload_ba;
+reg           main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine2_consume = 4'd0;
+wire          main_litedramcore_bankmachine2_do_read;
+wire          main_litedramcore_bankmachine2_fifo_in_first;
+wire          main_litedramcore_bankmachine2_fifo_in_last;
+wire   [21:0] main_litedramcore_bankmachine2_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine2_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine2_fifo_out_first;
+wire          main_litedramcore_bankmachine2_fifo_out_last;
+wire   [21:0] main_litedramcore_bankmachine2_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine2_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine2_level = 5'd0;
+wire          main_litedramcore_bankmachine2_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine2_pipe_valid_sink_last;
+wire   [21:0] main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine2_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine2_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine2_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine2_pipe_valid_source_last = 1'd0;
+reg    [21:0] main_litedramcore_bankmachine2_pipe_valid_source_payload_addr = 22'd0;
+reg           main_litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine2_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine2_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine2_rdport_adr;
+wire   [24:0] main_litedramcore_bankmachine2_rdport_dat_r;
+reg           main_litedramcore_bankmachine2_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine2_refresh_req;
+reg           main_litedramcore_bankmachine2_replace = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine2_req_addr;
+wire          main_litedramcore_bankmachine2_req_lock;
+reg           main_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine2_req_ready;
+wire          main_litedramcore_bankmachine2_req_valid;
+reg           main_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine2_req_we;
+reg    [14:0] main_litedramcore_bankmachine2_row = 15'd0;
+reg           main_litedramcore_bankmachine2_row_close = 1'd0;
+reg           main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine2_row_hit;
+reg           main_litedramcore_bankmachine2_row_open = 1'd0;
+reg           main_litedramcore_bankmachine2_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine2_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine2_sink_last = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine2_sink_payload_addr;
+wire          main_litedramcore_bankmachine2_sink_payload_we;
+wire          main_litedramcore_bankmachine2_sink_ready;
+wire          main_litedramcore_bankmachine2_sink_sink_first;
+wire          main_litedramcore_bankmachine2_sink_sink_last;
+wire   [21:0] main_litedramcore_bankmachine2_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine2_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine2_sink_sink_ready;
+wire          main_litedramcore_bankmachine2_sink_sink_valid;
+wire          main_litedramcore_bankmachine2_sink_valid;
+wire          main_litedramcore_bankmachine2_source_first;
+wire          main_litedramcore_bankmachine2_source_last;
+wire   [21:0] main_litedramcore_bankmachine2_source_payload_addr;
+wire          main_litedramcore_bankmachine2_source_payload_we;
+wire          main_litedramcore_bankmachine2_source_ready;
+wire          main_litedramcore_bankmachine2_source_source_first;
+wire          main_litedramcore_bankmachine2_source_source_last;
+wire   [21:0] main_litedramcore_bankmachine2_source_source_payload_addr;
+wire          main_litedramcore_bankmachine2_source_source_payload_we;
+wire          main_litedramcore_bankmachine2_source_source_ready;
+wire          main_litedramcore_bankmachine2_source_source_valid;
+wire          main_litedramcore_bankmachine2_source_valid;
+wire   [24:0] main_litedramcore_bankmachine2_syncfifo2_din;
+wire   [24:0] main_litedramcore_bankmachine2_syncfifo2_dout;
+wire          main_litedramcore_bankmachine2_syncfifo2_re;
+wire          main_litedramcore_bankmachine2_syncfifo2_readable;
+wire          main_litedramcore_bankmachine2_syncfifo2_we;
+wire          main_litedramcore_bankmachine2_syncfifo2_writable;
+reg     [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine2_trccon_valid;
+reg           main_litedramcore_bankmachine2_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine2_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
-wire          litedramcore_bankmachine2_trascon_valid;
+reg           main_litedramcore_bankmachine2_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine2_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine2_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
-wire          litedramcore_bankmachine3_req_valid;
-wire          litedramcore_bankmachine3_req_ready;
-wire          litedramcore_bankmachine3_req_we;
-wire   [21:0] litedramcore_bankmachine3_req_addr;
-wire          litedramcore_bankmachine3_req_lock;
-reg           litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine3_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine3_refresh_req;
-reg           litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine3_cmd_ready = 1'd0;
-reg    [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0;
-wire    [2:0] litedramcore_bankmachine3_cmd_payload_ba;
-reg           litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine3_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine3_sink_valid;
-wire          litedramcore_bankmachine3_sink_ready;
-reg           litedramcore_bankmachine3_sink_first = 1'd0;
-reg           litedramcore_bankmachine3_sink_last = 1'd0;
-wire          litedramcore_bankmachine3_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine3_sink_payload_addr;
-wire          litedramcore_bankmachine3_source_valid;
-wire          litedramcore_bankmachine3_source_ready;
-wire          litedramcore_bankmachine3_source_first;
-wire          litedramcore_bankmachine3_source_last;
-wire          litedramcore_bankmachine3_source_payload_we;
-wire   [21:0] litedramcore_bankmachine3_source_payload_addr;
-wire          litedramcore_bankmachine3_syncfifo3_we;
-wire          litedramcore_bankmachine3_syncfifo3_writable;
-wire          litedramcore_bankmachine3_syncfifo3_re;
-wire          litedramcore_bankmachine3_syncfifo3_readable;
-wire   [24:0] litedramcore_bankmachine3_syncfifo3_din;
-wire   [24:0] litedramcore_bankmachine3_syncfifo3_dout;
-reg     [4:0] litedramcore_bankmachine3_level = 5'd0;
-reg           litedramcore_bankmachine3_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine3_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine3_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0;
-wire   [24:0] litedramcore_bankmachine3_wrport_dat_r;
-wire          litedramcore_bankmachine3_wrport_we;
-wire   [24:0] litedramcore_bankmachine3_wrport_dat_w;
-wire          litedramcore_bankmachine3_do_read;
-wire    [3:0] litedramcore_bankmachine3_rdport_adr;
-wire   [24:0] litedramcore_bankmachine3_rdport_dat_r;
-wire          litedramcore_bankmachine3_fifo_in_payload_we;
-wire   [21:0] litedramcore_bankmachine3_fifo_in_payload_addr;
-wire          litedramcore_bankmachine3_fifo_in_first;
-wire          litedramcore_bankmachine3_fifo_in_last;
-wire          litedramcore_bankmachine3_fifo_out_payload_we;
-wire   [21:0] litedramcore_bankmachine3_fifo_out_payload_addr;
-wire          litedramcore_bankmachine3_fifo_out_first;
-wire          litedramcore_bankmachine3_fifo_out_last;
-wire          litedramcore_bankmachine3_sink_sink_valid;
-wire          litedramcore_bankmachine3_sink_sink_ready;
-wire          litedramcore_bankmachine3_sink_sink_first;
-wire          litedramcore_bankmachine3_sink_sink_last;
-wire          litedramcore_bankmachine3_sink_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine3_sink_sink_payload_addr;
-wire          litedramcore_bankmachine3_source_source_valid;
-wire          litedramcore_bankmachine3_source_source_ready;
-wire          litedramcore_bankmachine3_source_source_first;
-wire          litedramcore_bankmachine3_source_source_last;
-wire          litedramcore_bankmachine3_source_source_payload_we;
-wire   [21:0] litedramcore_bankmachine3_source_source_payload_addr;
-wire          litedramcore_bankmachine3_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine3_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine3_pipe_valid_sink_first;
-wire          litedramcore_bankmachine3_pipe_valid_sink_last;
-wire          litedramcore_bankmachine3_pipe_valid_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine3_pipe_valid_source_ready;
-reg           litedramcore_bankmachine3_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine3_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0;
-reg    [21:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 22'd0;
-reg    [14:0] litedramcore_bankmachine3_row = 15'd0;
-reg           litedramcore_bankmachine3_row_opened = 1'd0;
-wire          litedramcore_bankmachine3_row_hit;
-reg           litedramcore_bankmachine3_row_open = 1'd0;
-reg           litedramcore_bankmachine3_row_close = 1'd0;
-reg           litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine3_twtpcon_valid;
+reg           main_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine2_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine2_wrport_adr = 4'd0;
+wire   [24:0] main_litedramcore_bankmachine2_wrport_dat_r;
+wire   [24:0] main_litedramcore_bankmachine2_wrport_dat_w;
+wire          main_litedramcore_bankmachine2_wrport_we;
+reg           main_litedramcore_bankmachine3_auto_precharge = 1'd0;
+reg    [14:0] main_litedramcore_bankmachine3_cmd_payload_a = 15'd0;
+wire    [2:0] main_litedramcore_bankmachine3_cmd_payload_ba;
+reg           main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine3_consume = 4'd0;
+wire          main_litedramcore_bankmachine3_do_read;
+wire          main_litedramcore_bankmachine3_fifo_in_first;
+wire          main_litedramcore_bankmachine3_fifo_in_last;
+wire   [21:0] main_litedramcore_bankmachine3_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine3_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine3_fifo_out_first;
+wire          main_litedramcore_bankmachine3_fifo_out_last;
+wire   [21:0] main_litedramcore_bankmachine3_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine3_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine3_level = 5'd0;
+wire          main_litedramcore_bankmachine3_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine3_pipe_valid_sink_last;
+wire   [21:0] main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine3_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine3_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine3_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine3_pipe_valid_source_last = 1'd0;
+reg    [21:0] main_litedramcore_bankmachine3_pipe_valid_source_payload_addr = 22'd0;
+reg           main_litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine3_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine3_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine3_rdport_adr;
+wire   [24:0] main_litedramcore_bankmachine3_rdport_dat_r;
+reg           main_litedramcore_bankmachine3_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine3_refresh_req;
+reg           main_litedramcore_bankmachine3_replace = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine3_req_addr;
+wire          main_litedramcore_bankmachine3_req_lock;
+reg           main_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine3_req_ready;
+wire          main_litedramcore_bankmachine3_req_valid;
+reg           main_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine3_req_we;
+reg    [14:0] main_litedramcore_bankmachine3_row = 15'd0;
+reg           main_litedramcore_bankmachine3_row_close = 1'd0;
+reg           main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine3_row_hit;
+reg           main_litedramcore_bankmachine3_row_open = 1'd0;
+reg           main_litedramcore_bankmachine3_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine3_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine3_sink_last = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine3_sink_payload_addr;
+wire          main_litedramcore_bankmachine3_sink_payload_we;
+wire          main_litedramcore_bankmachine3_sink_ready;
+wire          main_litedramcore_bankmachine3_sink_sink_first;
+wire          main_litedramcore_bankmachine3_sink_sink_last;
+wire   [21:0] main_litedramcore_bankmachine3_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine3_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine3_sink_sink_ready;
+wire          main_litedramcore_bankmachine3_sink_sink_valid;
+wire          main_litedramcore_bankmachine3_sink_valid;
+wire          main_litedramcore_bankmachine3_source_first;
+wire          main_litedramcore_bankmachine3_source_last;
+wire   [21:0] main_litedramcore_bankmachine3_source_payload_addr;
+wire          main_litedramcore_bankmachine3_source_payload_we;
+wire          main_litedramcore_bankmachine3_source_ready;
+wire          main_litedramcore_bankmachine3_source_source_first;
+wire          main_litedramcore_bankmachine3_source_source_last;
+wire   [21:0] main_litedramcore_bankmachine3_source_source_payload_addr;
+wire          main_litedramcore_bankmachine3_source_source_payload_we;
+wire          main_litedramcore_bankmachine3_source_source_ready;
+wire          main_litedramcore_bankmachine3_source_source_valid;
+wire          main_litedramcore_bankmachine3_source_valid;
+wire   [24:0] main_litedramcore_bankmachine3_syncfifo3_din;
+wire   [24:0] main_litedramcore_bankmachine3_syncfifo3_dout;
+wire          main_litedramcore_bankmachine3_syncfifo3_re;
+wire          main_litedramcore_bankmachine3_syncfifo3_readable;
+wire          main_litedramcore_bankmachine3_syncfifo3_we;
+wire          main_litedramcore_bankmachine3_syncfifo3_writable;
+reg     [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine3_trccon_valid;
+reg           main_litedramcore_bankmachine3_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine3_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
-wire          litedramcore_bankmachine3_trascon_valid;
+reg           main_litedramcore_bankmachine3_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine3_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine3_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
-wire          litedramcore_bankmachine4_req_valid;
-wire          litedramcore_bankmachine4_req_ready;
-wire          litedramcore_bankmachine4_req_we;
-wire   [21:0] litedramcore_bankmachine4_req_addr;
-wire          litedramcore_bankmachine4_req_lock;
-reg           litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine4_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine4_refresh_req;
-reg           litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine4_cmd_ready = 1'd0;
-reg    [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0;
-wire    [2:0] litedramcore_bankmachine4_cmd_payload_ba;
-reg           litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine4_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine4_sink_valid;
-wire          litedramcore_bankmachine4_sink_ready;
-reg           litedramcore_bankmachine4_sink_first = 1'd0;
-reg           litedramcore_bankmachine4_sink_last = 1'd0;
-wire          litedramcore_bankmachine4_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine4_sink_payload_addr;
-wire          litedramcore_bankmachine4_source_valid;
-wire          litedramcore_bankmachine4_source_ready;
-wire          litedramcore_bankmachine4_source_first;
-wire          litedramcore_bankmachine4_source_last;
-wire          litedramcore_bankmachine4_source_payload_we;
-wire   [21:0] litedramcore_bankmachine4_source_payload_addr;
-wire          litedramcore_bankmachine4_syncfifo4_we;
-wire          litedramcore_bankmachine4_syncfifo4_writable;
-wire          litedramcore_bankmachine4_syncfifo4_re;
-wire          litedramcore_bankmachine4_syncfifo4_readable;
-wire   [24:0] litedramcore_bankmachine4_syncfifo4_din;
-wire   [24:0] litedramcore_bankmachine4_syncfifo4_dout;
-reg     [4:0] litedramcore_bankmachine4_level = 5'd0;
-reg           litedramcore_bankmachine4_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine4_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine4_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0;
-wire   [24:0] litedramcore_bankmachine4_wrport_dat_r;
-wire          litedramcore_bankmachine4_wrport_we;
-wire   [24:0] litedramcore_bankmachine4_wrport_dat_w;
-wire          litedramcore_bankmachine4_do_read;
-wire    [3:0] litedramcore_bankmachine4_rdport_adr;
-wire   [24:0] litedramcore_bankmachine4_rdport_dat_r;
-wire          litedramcore_bankmachine4_fifo_in_payload_we;
-wire   [21:0] litedramcore_bankmachine4_fifo_in_payload_addr;
-wire          litedramcore_bankmachine4_fifo_in_first;
-wire          litedramcore_bankmachine4_fifo_in_last;
-wire          litedramcore_bankmachine4_fifo_out_payload_we;
-wire   [21:0] litedramcore_bankmachine4_fifo_out_payload_addr;
-wire          litedramcore_bankmachine4_fifo_out_first;
-wire          litedramcore_bankmachine4_fifo_out_last;
-wire          litedramcore_bankmachine4_sink_sink_valid;
-wire          litedramcore_bankmachine4_sink_sink_ready;
-wire          litedramcore_bankmachine4_sink_sink_first;
-wire          litedramcore_bankmachine4_sink_sink_last;
-wire          litedramcore_bankmachine4_sink_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine4_sink_sink_payload_addr;
-wire          litedramcore_bankmachine4_source_source_valid;
-wire          litedramcore_bankmachine4_source_source_ready;
-wire          litedramcore_bankmachine4_source_source_first;
-wire          litedramcore_bankmachine4_source_source_last;
-wire          litedramcore_bankmachine4_source_source_payload_we;
-wire   [21:0] litedramcore_bankmachine4_source_source_payload_addr;
-wire          litedramcore_bankmachine4_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine4_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine4_pipe_valid_sink_first;
-wire          litedramcore_bankmachine4_pipe_valid_sink_last;
-wire          litedramcore_bankmachine4_pipe_valid_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine4_pipe_valid_source_ready;
-reg           litedramcore_bankmachine4_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine4_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0;
-reg    [21:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 22'd0;
-reg    [14:0] litedramcore_bankmachine4_row = 15'd0;
-reg           litedramcore_bankmachine4_row_opened = 1'd0;
-wire          litedramcore_bankmachine4_row_hit;
-reg           litedramcore_bankmachine4_row_open = 1'd0;
-reg           litedramcore_bankmachine4_row_close = 1'd0;
-reg           litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine4_twtpcon_valid;
+reg           main_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine3_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine3_wrport_adr = 4'd0;
+wire   [24:0] main_litedramcore_bankmachine3_wrport_dat_r;
+wire   [24:0] main_litedramcore_bankmachine3_wrport_dat_w;
+wire          main_litedramcore_bankmachine3_wrport_we;
+reg           main_litedramcore_bankmachine4_auto_precharge = 1'd0;
+reg    [14:0] main_litedramcore_bankmachine4_cmd_payload_a = 15'd0;
+wire    [2:0] main_litedramcore_bankmachine4_cmd_payload_ba;
+reg           main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine4_consume = 4'd0;
+wire          main_litedramcore_bankmachine4_do_read;
+wire          main_litedramcore_bankmachine4_fifo_in_first;
+wire          main_litedramcore_bankmachine4_fifo_in_last;
+wire   [21:0] main_litedramcore_bankmachine4_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine4_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine4_fifo_out_first;
+wire          main_litedramcore_bankmachine4_fifo_out_last;
+wire   [21:0] main_litedramcore_bankmachine4_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine4_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine4_level = 5'd0;
+wire          main_litedramcore_bankmachine4_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine4_pipe_valid_sink_last;
+wire   [21:0] main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine4_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine4_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine4_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine4_pipe_valid_source_last = 1'd0;
+reg    [21:0] main_litedramcore_bankmachine4_pipe_valid_source_payload_addr = 22'd0;
+reg           main_litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine4_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine4_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine4_rdport_adr;
+wire   [24:0] main_litedramcore_bankmachine4_rdport_dat_r;
+reg           main_litedramcore_bankmachine4_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine4_refresh_req;
+reg           main_litedramcore_bankmachine4_replace = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine4_req_addr;
+wire          main_litedramcore_bankmachine4_req_lock;
+reg           main_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine4_req_ready;
+wire          main_litedramcore_bankmachine4_req_valid;
+reg           main_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine4_req_we;
+reg    [14:0] main_litedramcore_bankmachine4_row = 15'd0;
+reg           main_litedramcore_bankmachine4_row_close = 1'd0;
+reg           main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine4_row_hit;
+reg           main_litedramcore_bankmachine4_row_open = 1'd0;
+reg           main_litedramcore_bankmachine4_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine4_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine4_sink_last = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine4_sink_payload_addr;
+wire          main_litedramcore_bankmachine4_sink_payload_we;
+wire          main_litedramcore_bankmachine4_sink_ready;
+wire          main_litedramcore_bankmachine4_sink_sink_first;
+wire          main_litedramcore_bankmachine4_sink_sink_last;
+wire   [21:0] main_litedramcore_bankmachine4_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine4_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine4_sink_sink_ready;
+wire          main_litedramcore_bankmachine4_sink_sink_valid;
+wire          main_litedramcore_bankmachine4_sink_valid;
+wire          main_litedramcore_bankmachine4_source_first;
+wire          main_litedramcore_bankmachine4_source_last;
+wire   [21:0] main_litedramcore_bankmachine4_source_payload_addr;
+wire          main_litedramcore_bankmachine4_source_payload_we;
+wire          main_litedramcore_bankmachine4_source_ready;
+wire          main_litedramcore_bankmachine4_source_source_first;
+wire          main_litedramcore_bankmachine4_source_source_last;
+wire   [21:0] main_litedramcore_bankmachine4_source_source_payload_addr;
+wire          main_litedramcore_bankmachine4_source_source_payload_we;
+wire          main_litedramcore_bankmachine4_source_source_ready;
+wire          main_litedramcore_bankmachine4_source_source_valid;
+wire          main_litedramcore_bankmachine4_source_valid;
+wire   [24:0] main_litedramcore_bankmachine4_syncfifo4_din;
+wire   [24:0] main_litedramcore_bankmachine4_syncfifo4_dout;
+wire          main_litedramcore_bankmachine4_syncfifo4_re;
+wire          main_litedramcore_bankmachine4_syncfifo4_readable;
+wire          main_litedramcore_bankmachine4_syncfifo4_we;
+wire          main_litedramcore_bankmachine4_syncfifo4_writable;
+reg     [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine4_trccon_valid;
+reg           main_litedramcore_bankmachine4_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine4_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
-wire          litedramcore_bankmachine4_trascon_valid;
+reg           main_litedramcore_bankmachine4_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine4_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine4_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
-wire          litedramcore_bankmachine5_req_valid;
-wire          litedramcore_bankmachine5_req_ready;
-wire          litedramcore_bankmachine5_req_we;
-wire   [21:0] litedramcore_bankmachine5_req_addr;
-wire          litedramcore_bankmachine5_req_lock;
-reg           litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine5_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine5_refresh_req;
-reg           litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine5_cmd_ready = 1'd0;
-reg    [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0;
-wire    [2:0] litedramcore_bankmachine5_cmd_payload_ba;
-reg           litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine5_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine5_sink_valid;
-wire          litedramcore_bankmachine5_sink_ready;
-reg           litedramcore_bankmachine5_sink_first = 1'd0;
-reg           litedramcore_bankmachine5_sink_last = 1'd0;
-wire          litedramcore_bankmachine5_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine5_sink_payload_addr;
-wire          litedramcore_bankmachine5_source_valid;
-wire          litedramcore_bankmachine5_source_ready;
-wire          litedramcore_bankmachine5_source_first;
-wire          litedramcore_bankmachine5_source_last;
-wire          litedramcore_bankmachine5_source_payload_we;
-wire   [21:0] litedramcore_bankmachine5_source_payload_addr;
-wire          litedramcore_bankmachine5_syncfifo5_we;
-wire          litedramcore_bankmachine5_syncfifo5_writable;
-wire          litedramcore_bankmachine5_syncfifo5_re;
-wire          litedramcore_bankmachine5_syncfifo5_readable;
-wire   [24:0] litedramcore_bankmachine5_syncfifo5_din;
-wire   [24:0] litedramcore_bankmachine5_syncfifo5_dout;
-reg     [4:0] litedramcore_bankmachine5_level = 5'd0;
-reg           litedramcore_bankmachine5_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine5_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine5_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0;
-wire   [24:0] litedramcore_bankmachine5_wrport_dat_r;
-wire          litedramcore_bankmachine5_wrport_we;
-wire   [24:0] litedramcore_bankmachine5_wrport_dat_w;
-wire          litedramcore_bankmachine5_do_read;
-wire    [3:0] litedramcore_bankmachine5_rdport_adr;
-wire   [24:0] litedramcore_bankmachine5_rdport_dat_r;
-wire          litedramcore_bankmachine5_fifo_in_payload_we;
-wire   [21:0] litedramcore_bankmachine5_fifo_in_payload_addr;
-wire          litedramcore_bankmachine5_fifo_in_first;
-wire          litedramcore_bankmachine5_fifo_in_last;
-wire          litedramcore_bankmachine5_fifo_out_payload_we;
-wire   [21:0] litedramcore_bankmachine5_fifo_out_payload_addr;
-wire          litedramcore_bankmachine5_fifo_out_first;
-wire          litedramcore_bankmachine5_fifo_out_last;
-wire          litedramcore_bankmachine5_sink_sink_valid;
-wire          litedramcore_bankmachine5_sink_sink_ready;
-wire          litedramcore_bankmachine5_sink_sink_first;
-wire          litedramcore_bankmachine5_sink_sink_last;
-wire          litedramcore_bankmachine5_sink_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine5_sink_sink_payload_addr;
-wire          litedramcore_bankmachine5_source_source_valid;
-wire          litedramcore_bankmachine5_source_source_ready;
-wire          litedramcore_bankmachine5_source_source_first;
-wire          litedramcore_bankmachine5_source_source_last;
-wire          litedramcore_bankmachine5_source_source_payload_we;
-wire   [21:0] litedramcore_bankmachine5_source_source_payload_addr;
-wire          litedramcore_bankmachine5_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine5_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine5_pipe_valid_sink_first;
-wire          litedramcore_bankmachine5_pipe_valid_sink_last;
-wire          litedramcore_bankmachine5_pipe_valid_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine5_pipe_valid_source_ready;
-reg           litedramcore_bankmachine5_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine5_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0;
-reg    [21:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 22'd0;
-reg    [14:0] litedramcore_bankmachine5_row = 15'd0;
-reg           litedramcore_bankmachine5_row_opened = 1'd0;
-wire          litedramcore_bankmachine5_row_hit;
-reg           litedramcore_bankmachine5_row_open = 1'd0;
-reg           litedramcore_bankmachine5_row_close = 1'd0;
-reg           litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine5_twtpcon_valid;
+reg           main_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine4_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine4_wrport_adr = 4'd0;
+wire   [24:0] main_litedramcore_bankmachine4_wrport_dat_r;
+wire   [24:0] main_litedramcore_bankmachine4_wrport_dat_w;
+wire          main_litedramcore_bankmachine4_wrport_we;
+reg           main_litedramcore_bankmachine5_auto_precharge = 1'd0;
+reg    [14:0] main_litedramcore_bankmachine5_cmd_payload_a = 15'd0;
+wire    [2:0] main_litedramcore_bankmachine5_cmd_payload_ba;
+reg           main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine5_consume = 4'd0;
+wire          main_litedramcore_bankmachine5_do_read;
+wire          main_litedramcore_bankmachine5_fifo_in_first;
+wire          main_litedramcore_bankmachine5_fifo_in_last;
+wire   [21:0] main_litedramcore_bankmachine5_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine5_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine5_fifo_out_first;
+wire          main_litedramcore_bankmachine5_fifo_out_last;
+wire   [21:0] main_litedramcore_bankmachine5_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine5_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine5_level = 5'd0;
+wire          main_litedramcore_bankmachine5_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine5_pipe_valid_sink_last;
+wire   [21:0] main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine5_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine5_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine5_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine5_pipe_valid_source_last = 1'd0;
+reg    [21:0] main_litedramcore_bankmachine5_pipe_valid_source_payload_addr = 22'd0;
+reg           main_litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine5_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine5_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine5_rdport_adr;
+wire   [24:0] main_litedramcore_bankmachine5_rdport_dat_r;
+reg           main_litedramcore_bankmachine5_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine5_refresh_req;
+reg           main_litedramcore_bankmachine5_replace = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine5_req_addr;
+wire          main_litedramcore_bankmachine5_req_lock;
+reg           main_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine5_req_ready;
+wire          main_litedramcore_bankmachine5_req_valid;
+reg           main_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine5_req_we;
+reg    [14:0] main_litedramcore_bankmachine5_row = 15'd0;
+reg           main_litedramcore_bankmachine5_row_close = 1'd0;
+reg           main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine5_row_hit;
+reg           main_litedramcore_bankmachine5_row_open = 1'd0;
+reg           main_litedramcore_bankmachine5_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine5_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine5_sink_last = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine5_sink_payload_addr;
+wire          main_litedramcore_bankmachine5_sink_payload_we;
+wire          main_litedramcore_bankmachine5_sink_ready;
+wire          main_litedramcore_bankmachine5_sink_sink_first;
+wire          main_litedramcore_bankmachine5_sink_sink_last;
+wire   [21:0] main_litedramcore_bankmachine5_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine5_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine5_sink_sink_ready;
+wire          main_litedramcore_bankmachine5_sink_sink_valid;
+wire          main_litedramcore_bankmachine5_sink_valid;
+wire          main_litedramcore_bankmachine5_source_first;
+wire          main_litedramcore_bankmachine5_source_last;
+wire   [21:0] main_litedramcore_bankmachine5_source_payload_addr;
+wire          main_litedramcore_bankmachine5_source_payload_we;
+wire          main_litedramcore_bankmachine5_source_ready;
+wire          main_litedramcore_bankmachine5_source_source_first;
+wire          main_litedramcore_bankmachine5_source_source_last;
+wire   [21:0] main_litedramcore_bankmachine5_source_source_payload_addr;
+wire          main_litedramcore_bankmachine5_source_source_payload_we;
+wire          main_litedramcore_bankmachine5_source_source_ready;
+wire          main_litedramcore_bankmachine5_source_source_valid;
+wire          main_litedramcore_bankmachine5_source_valid;
+wire   [24:0] main_litedramcore_bankmachine5_syncfifo5_din;
+wire   [24:0] main_litedramcore_bankmachine5_syncfifo5_dout;
+wire          main_litedramcore_bankmachine5_syncfifo5_re;
+wire          main_litedramcore_bankmachine5_syncfifo5_readable;
+wire          main_litedramcore_bankmachine5_syncfifo5_we;
+wire          main_litedramcore_bankmachine5_syncfifo5_writable;
+reg     [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine5_trccon_valid;
+reg           main_litedramcore_bankmachine5_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine5_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
-wire          litedramcore_bankmachine5_trascon_valid;
+reg           main_litedramcore_bankmachine5_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine5_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine5_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
-wire          litedramcore_bankmachine6_req_valid;
-wire          litedramcore_bankmachine6_req_ready;
-wire          litedramcore_bankmachine6_req_we;
-wire   [21:0] litedramcore_bankmachine6_req_addr;
-wire          litedramcore_bankmachine6_req_lock;
-reg           litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine6_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine6_refresh_req;
-reg           litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine6_cmd_ready = 1'd0;
-reg    [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0;
-wire    [2:0] litedramcore_bankmachine6_cmd_payload_ba;
-reg           litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine6_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine6_sink_valid;
-wire          litedramcore_bankmachine6_sink_ready;
-reg           litedramcore_bankmachine6_sink_first = 1'd0;
-reg           litedramcore_bankmachine6_sink_last = 1'd0;
-wire          litedramcore_bankmachine6_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine6_sink_payload_addr;
-wire          litedramcore_bankmachine6_source_valid;
-wire          litedramcore_bankmachine6_source_ready;
-wire          litedramcore_bankmachine6_source_first;
-wire          litedramcore_bankmachine6_source_last;
-wire          litedramcore_bankmachine6_source_payload_we;
-wire   [21:0] litedramcore_bankmachine6_source_payload_addr;
-wire          litedramcore_bankmachine6_syncfifo6_we;
-wire          litedramcore_bankmachine6_syncfifo6_writable;
-wire          litedramcore_bankmachine6_syncfifo6_re;
-wire          litedramcore_bankmachine6_syncfifo6_readable;
-wire   [24:0] litedramcore_bankmachine6_syncfifo6_din;
-wire   [24:0] litedramcore_bankmachine6_syncfifo6_dout;
-reg     [4:0] litedramcore_bankmachine6_level = 5'd0;
-reg           litedramcore_bankmachine6_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine6_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine6_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0;
-wire   [24:0] litedramcore_bankmachine6_wrport_dat_r;
-wire          litedramcore_bankmachine6_wrport_we;
-wire   [24:0] litedramcore_bankmachine6_wrport_dat_w;
-wire          litedramcore_bankmachine6_do_read;
-wire    [3:0] litedramcore_bankmachine6_rdport_adr;
-wire   [24:0] litedramcore_bankmachine6_rdport_dat_r;
-wire          litedramcore_bankmachine6_fifo_in_payload_we;
-wire   [21:0] litedramcore_bankmachine6_fifo_in_payload_addr;
-wire          litedramcore_bankmachine6_fifo_in_first;
-wire          litedramcore_bankmachine6_fifo_in_last;
-wire          litedramcore_bankmachine6_fifo_out_payload_we;
-wire   [21:0] litedramcore_bankmachine6_fifo_out_payload_addr;
-wire          litedramcore_bankmachine6_fifo_out_first;
-wire          litedramcore_bankmachine6_fifo_out_last;
-wire          litedramcore_bankmachine6_sink_sink_valid;
-wire          litedramcore_bankmachine6_sink_sink_ready;
-wire          litedramcore_bankmachine6_sink_sink_first;
-wire          litedramcore_bankmachine6_sink_sink_last;
-wire          litedramcore_bankmachine6_sink_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine6_sink_sink_payload_addr;
-wire          litedramcore_bankmachine6_source_source_valid;
-wire          litedramcore_bankmachine6_source_source_ready;
-wire          litedramcore_bankmachine6_source_source_first;
-wire          litedramcore_bankmachine6_source_source_last;
-wire          litedramcore_bankmachine6_source_source_payload_we;
-wire   [21:0] litedramcore_bankmachine6_source_source_payload_addr;
-wire          litedramcore_bankmachine6_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine6_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine6_pipe_valid_sink_first;
-wire          litedramcore_bankmachine6_pipe_valid_sink_last;
-wire          litedramcore_bankmachine6_pipe_valid_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine6_pipe_valid_source_ready;
-reg           litedramcore_bankmachine6_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine6_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0;
-reg    [21:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 22'd0;
-reg    [14:0] litedramcore_bankmachine6_row = 15'd0;
-reg           litedramcore_bankmachine6_row_opened = 1'd0;
-wire          litedramcore_bankmachine6_row_hit;
-reg           litedramcore_bankmachine6_row_open = 1'd0;
-reg           litedramcore_bankmachine6_row_close = 1'd0;
-reg           litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine6_twtpcon_valid;
+reg           main_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine5_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine5_wrport_adr = 4'd0;
+wire   [24:0] main_litedramcore_bankmachine5_wrport_dat_r;
+wire   [24:0] main_litedramcore_bankmachine5_wrport_dat_w;
+wire          main_litedramcore_bankmachine5_wrport_we;
+reg           main_litedramcore_bankmachine6_auto_precharge = 1'd0;
+reg    [14:0] main_litedramcore_bankmachine6_cmd_payload_a = 15'd0;
+wire    [2:0] main_litedramcore_bankmachine6_cmd_payload_ba;
+reg           main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine6_consume = 4'd0;
+wire          main_litedramcore_bankmachine6_do_read;
+wire          main_litedramcore_bankmachine6_fifo_in_first;
+wire          main_litedramcore_bankmachine6_fifo_in_last;
+wire   [21:0] main_litedramcore_bankmachine6_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine6_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine6_fifo_out_first;
+wire          main_litedramcore_bankmachine6_fifo_out_last;
+wire   [21:0] main_litedramcore_bankmachine6_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine6_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine6_level = 5'd0;
+wire          main_litedramcore_bankmachine6_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine6_pipe_valid_sink_last;
+wire   [21:0] main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine6_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine6_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine6_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine6_pipe_valid_source_last = 1'd0;
+reg    [21:0] main_litedramcore_bankmachine6_pipe_valid_source_payload_addr = 22'd0;
+reg           main_litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine6_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine6_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine6_rdport_adr;
+wire   [24:0] main_litedramcore_bankmachine6_rdport_dat_r;
+reg           main_litedramcore_bankmachine6_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine6_refresh_req;
+reg           main_litedramcore_bankmachine6_replace = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine6_req_addr;
+wire          main_litedramcore_bankmachine6_req_lock;
+reg           main_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine6_req_ready;
+wire          main_litedramcore_bankmachine6_req_valid;
+reg           main_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine6_req_we;
+reg    [14:0] main_litedramcore_bankmachine6_row = 15'd0;
+reg           main_litedramcore_bankmachine6_row_close = 1'd0;
+reg           main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine6_row_hit;
+reg           main_litedramcore_bankmachine6_row_open = 1'd0;
+reg           main_litedramcore_bankmachine6_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine6_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine6_sink_last = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine6_sink_payload_addr;
+wire          main_litedramcore_bankmachine6_sink_payload_we;
+wire          main_litedramcore_bankmachine6_sink_ready;
+wire          main_litedramcore_bankmachine6_sink_sink_first;
+wire          main_litedramcore_bankmachine6_sink_sink_last;
+wire   [21:0] main_litedramcore_bankmachine6_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine6_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine6_sink_sink_ready;
+wire          main_litedramcore_bankmachine6_sink_sink_valid;
+wire          main_litedramcore_bankmachine6_sink_valid;
+wire          main_litedramcore_bankmachine6_source_first;
+wire          main_litedramcore_bankmachine6_source_last;
+wire   [21:0] main_litedramcore_bankmachine6_source_payload_addr;
+wire          main_litedramcore_bankmachine6_source_payload_we;
+wire          main_litedramcore_bankmachine6_source_ready;
+wire          main_litedramcore_bankmachine6_source_source_first;
+wire          main_litedramcore_bankmachine6_source_source_last;
+wire   [21:0] main_litedramcore_bankmachine6_source_source_payload_addr;
+wire          main_litedramcore_bankmachine6_source_source_payload_we;
+wire          main_litedramcore_bankmachine6_source_source_ready;
+wire          main_litedramcore_bankmachine6_source_source_valid;
+wire          main_litedramcore_bankmachine6_source_valid;
+wire   [24:0] main_litedramcore_bankmachine6_syncfifo6_din;
+wire   [24:0] main_litedramcore_bankmachine6_syncfifo6_dout;
+wire          main_litedramcore_bankmachine6_syncfifo6_re;
+wire          main_litedramcore_bankmachine6_syncfifo6_readable;
+wire          main_litedramcore_bankmachine6_syncfifo6_we;
+wire          main_litedramcore_bankmachine6_syncfifo6_writable;
+reg     [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine6_trccon_valid;
+reg           main_litedramcore_bankmachine6_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine6_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
-wire          litedramcore_bankmachine6_trascon_valid;
+reg           main_litedramcore_bankmachine6_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine6_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine6_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
-wire          litedramcore_bankmachine7_req_valid;
-wire          litedramcore_bankmachine7_req_ready;
-wire          litedramcore_bankmachine7_req_we;
-wire   [21:0] litedramcore_bankmachine7_req_addr;
-wire          litedramcore_bankmachine7_req_lock;
-reg           litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine7_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine7_refresh_req;
-reg           litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine7_cmd_ready = 1'd0;
-reg    [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0;
-wire    [2:0] litedramcore_bankmachine7_cmd_payload_ba;
-reg           litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine7_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine7_sink_valid;
-wire          litedramcore_bankmachine7_sink_ready;
-reg           litedramcore_bankmachine7_sink_first = 1'd0;
-reg           litedramcore_bankmachine7_sink_last = 1'd0;
-wire          litedramcore_bankmachine7_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine7_sink_payload_addr;
-wire          litedramcore_bankmachine7_source_valid;
-wire          litedramcore_bankmachine7_source_ready;
-wire          litedramcore_bankmachine7_source_first;
-wire          litedramcore_bankmachine7_source_last;
-wire          litedramcore_bankmachine7_source_payload_we;
-wire   [21:0] litedramcore_bankmachine7_source_payload_addr;
-wire          litedramcore_bankmachine7_syncfifo7_we;
-wire          litedramcore_bankmachine7_syncfifo7_writable;
-wire          litedramcore_bankmachine7_syncfifo7_re;
-wire          litedramcore_bankmachine7_syncfifo7_readable;
-wire   [24:0] litedramcore_bankmachine7_syncfifo7_din;
-wire   [24:0] litedramcore_bankmachine7_syncfifo7_dout;
-reg     [4:0] litedramcore_bankmachine7_level = 5'd0;
-reg           litedramcore_bankmachine7_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine7_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine7_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0;
-wire   [24:0] litedramcore_bankmachine7_wrport_dat_r;
-wire          litedramcore_bankmachine7_wrport_we;
-wire   [24:0] litedramcore_bankmachine7_wrport_dat_w;
-wire          litedramcore_bankmachine7_do_read;
-wire    [3:0] litedramcore_bankmachine7_rdport_adr;
-wire   [24:0] litedramcore_bankmachine7_rdport_dat_r;
-wire          litedramcore_bankmachine7_fifo_in_payload_we;
-wire   [21:0] litedramcore_bankmachine7_fifo_in_payload_addr;
-wire          litedramcore_bankmachine7_fifo_in_first;
-wire          litedramcore_bankmachine7_fifo_in_last;
-wire          litedramcore_bankmachine7_fifo_out_payload_we;
-wire   [21:0] litedramcore_bankmachine7_fifo_out_payload_addr;
-wire          litedramcore_bankmachine7_fifo_out_first;
-wire          litedramcore_bankmachine7_fifo_out_last;
-wire          litedramcore_bankmachine7_sink_sink_valid;
-wire          litedramcore_bankmachine7_sink_sink_ready;
-wire          litedramcore_bankmachine7_sink_sink_first;
-wire          litedramcore_bankmachine7_sink_sink_last;
-wire          litedramcore_bankmachine7_sink_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine7_sink_sink_payload_addr;
-wire          litedramcore_bankmachine7_source_source_valid;
-wire          litedramcore_bankmachine7_source_source_ready;
-wire          litedramcore_bankmachine7_source_source_first;
-wire          litedramcore_bankmachine7_source_source_last;
-wire          litedramcore_bankmachine7_source_source_payload_we;
-wire   [21:0] litedramcore_bankmachine7_source_source_payload_addr;
-wire          litedramcore_bankmachine7_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine7_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine7_pipe_valid_sink_first;
-wire          litedramcore_bankmachine7_pipe_valid_sink_last;
-wire          litedramcore_bankmachine7_pipe_valid_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine7_pipe_valid_source_ready;
-reg           litedramcore_bankmachine7_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine7_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0;
-reg    [21:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 22'd0;
-reg    [14:0] litedramcore_bankmachine7_row = 15'd0;
-reg           litedramcore_bankmachine7_row_opened = 1'd0;
-wire          litedramcore_bankmachine7_row_hit;
-reg           litedramcore_bankmachine7_row_open = 1'd0;
-reg           litedramcore_bankmachine7_row_close = 1'd0;
-reg           litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine7_twtpcon_valid;
+reg           main_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine6_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine6_wrport_adr = 4'd0;
+wire   [24:0] main_litedramcore_bankmachine6_wrport_dat_r;
+wire   [24:0] main_litedramcore_bankmachine6_wrport_dat_w;
+wire          main_litedramcore_bankmachine6_wrport_we;
+reg           main_litedramcore_bankmachine7_auto_precharge = 1'd0;
+reg    [14:0] main_litedramcore_bankmachine7_cmd_payload_a = 15'd0;
+wire    [2:0] main_litedramcore_bankmachine7_cmd_payload_ba;
+reg           main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine7_consume = 4'd0;
+wire          main_litedramcore_bankmachine7_do_read;
+wire          main_litedramcore_bankmachine7_fifo_in_first;
+wire          main_litedramcore_bankmachine7_fifo_in_last;
+wire   [21:0] main_litedramcore_bankmachine7_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine7_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine7_fifo_out_first;
+wire          main_litedramcore_bankmachine7_fifo_out_last;
+wire   [21:0] main_litedramcore_bankmachine7_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine7_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine7_level = 5'd0;
+wire          main_litedramcore_bankmachine7_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine7_pipe_valid_sink_last;
+wire   [21:0] main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine7_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine7_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine7_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine7_pipe_valid_source_last = 1'd0;
+reg    [21:0] main_litedramcore_bankmachine7_pipe_valid_source_payload_addr = 22'd0;
+reg           main_litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine7_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine7_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine7_rdport_adr;
+wire   [24:0] main_litedramcore_bankmachine7_rdport_dat_r;
+reg           main_litedramcore_bankmachine7_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine7_refresh_req;
+reg           main_litedramcore_bankmachine7_replace = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine7_req_addr;
+wire          main_litedramcore_bankmachine7_req_lock;
+reg           main_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine7_req_ready;
+wire          main_litedramcore_bankmachine7_req_valid;
+reg           main_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine7_req_we;
+reg    [14:0] main_litedramcore_bankmachine7_row = 15'd0;
+reg           main_litedramcore_bankmachine7_row_close = 1'd0;
+reg           main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine7_row_hit;
+reg           main_litedramcore_bankmachine7_row_open = 1'd0;
+reg           main_litedramcore_bankmachine7_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine7_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine7_sink_last = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine7_sink_payload_addr;
+wire          main_litedramcore_bankmachine7_sink_payload_we;
+wire          main_litedramcore_bankmachine7_sink_ready;
+wire          main_litedramcore_bankmachine7_sink_sink_first;
+wire          main_litedramcore_bankmachine7_sink_sink_last;
+wire   [21:0] main_litedramcore_bankmachine7_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine7_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine7_sink_sink_ready;
+wire          main_litedramcore_bankmachine7_sink_sink_valid;
+wire          main_litedramcore_bankmachine7_sink_valid;
+wire          main_litedramcore_bankmachine7_source_first;
+wire          main_litedramcore_bankmachine7_source_last;
+wire   [21:0] main_litedramcore_bankmachine7_source_payload_addr;
+wire          main_litedramcore_bankmachine7_source_payload_we;
+wire          main_litedramcore_bankmachine7_source_ready;
+wire          main_litedramcore_bankmachine7_source_source_first;
+wire          main_litedramcore_bankmachine7_source_source_last;
+wire   [21:0] main_litedramcore_bankmachine7_source_source_payload_addr;
+wire          main_litedramcore_bankmachine7_source_source_payload_we;
+wire          main_litedramcore_bankmachine7_source_source_ready;
+wire          main_litedramcore_bankmachine7_source_source_valid;
+wire          main_litedramcore_bankmachine7_source_valid;
+wire   [24:0] main_litedramcore_bankmachine7_syncfifo7_din;
+wire   [24:0] main_litedramcore_bankmachine7_syncfifo7_dout;
+wire          main_litedramcore_bankmachine7_syncfifo7_re;
+wire          main_litedramcore_bankmachine7_syncfifo7_readable;
+wire          main_litedramcore_bankmachine7_syncfifo7_we;
+wire          main_litedramcore_bankmachine7_syncfifo7_writable;
+reg     [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine7_trccon_valid;
+reg           main_litedramcore_bankmachine7_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine7_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
-wire          litedramcore_bankmachine7_trascon_valid;
+reg           main_litedramcore_bankmachine7_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine7_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine7_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
-wire          litedramcore_ras_allowed;
-wire          litedramcore_cas_allowed;
-wire    [1:0] litedramcore_rdcmdphase;
-wire    [1:0] litedramcore_wrcmdphase;
-reg           litedramcore_choose_cmd_want_reads = 1'd0;
-reg           litedramcore_choose_cmd_want_writes = 1'd0;
-reg           litedramcore_choose_cmd_want_cmds = 1'd0;
-reg           litedramcore_choose_cmd_want_activates = 1'd0;
-wire          litedramcore_choose_cmd_cmd_valid;
-reg           litedramcore_choose_cmd_cmd_ready = 1'd0;
-wire   [14:0] litedramcore_choose_cmd_cmd_payload_a;
-wire    [2:0] litedramcore_choose_cmd_cmd_payload_ba;
-reg           litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg           litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg           litedramcore_choose_cmd_cmd_payload_we = 1'd0;
-wire          litedramcore_choose_cmd_cmd_payload_is_cmd;
-wire          litedramcore_choose_cmd_cmd_payload_is_read;
-wire          litedramcore_choose_cmd_cmd_payload_is_write;
-reg     [7:0] litedramcore_choose_cmd_valids = 8'd0;
-wire    [7:0] litedramcore_choose_cmd_request;
-reg     [2:0] litedramcore_choose_cmd_grant = 3'd0;
-wire          litedramcore_choose_cmd_ce;
-reg           litedramcore_choose_req_want_reads = 1'd0;
-reg           litedramcore_choose_req_want_writes = 1'd0;
-reg           litedramcore_choose_req_want_cmds = 1'd0;
-reg           litedramcore_choose_req_want_activates = 1'd0;
-wire          litedramcore_choose_req_cmd_valid;
-reg           litedramcore_choose_req_cmd_ready = 1'd0;
-wire   [14:0] litedramcore_choose_req_cmd_payload_a;
-wire    [2:0] litedramcore_choose_req_cmd_payload_ba;
-reg           litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg           litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg           litedramcore_choose_req_cmd_payload_we = 1'd0;
-wire          litedramcore_choose_req_cmd_payload_is_cmd;
-wire          litedramcore_choose_req_cmd_payload_is_read;
-wire          litedramcore_choose_req_cmd_payload_is_write;
-reg     [7:0] litedramcore_choose_req_valids = 8'd0;
-wire    [7:0] litedramcore_choose_req_request;
-reg     [2:0] litedramcore_choose_req_grant = 3'd0;
-wire          litedramcore_choose_req_ce;
-reg    [14:0] litedramcore_nop_a = 15'd0;
-reg     [2:0] litedramcore_nop_ba = 3'd0;
-reg     [1:0] litedramcore_steerer_sel0 = 2'd0;
-reg     [1:0] litedramcore_steerer_sel1 = 2'd0;
-reg     [1:0] litedramcore_steerer_sel2 = 2'd0;
-reg     [1:0] litedramcore_steerer_sel3 = 2'd0;
-reg           litedramcore_steerer0 = 1'd1;
-reg           litedramcore_steerer1 = 1'd1;
-reg           litedramcore_steerer2 = 1'd1;
-reg           litedramcore_steerer3 = 1'd1;
-reg           litedramcore_steerer4 = 1'd1;
-reg           litedramcore_steerer5 = 1'd1;
-reg           litedramcore_steerer6 = 1'd1;
-reg           litedramcore_steerer7 = 1'd1;
-wire          litedramcore_trrdcon_valid;
+reg           main_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine7_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine7_wrport_adr = 4'd0;
+wire   [24:0] main_litedramcore_bankmachine7_wrport_dat_r;
+wire   [24:0] main_litedramcore_bankmachine7_wrport_dat_w;
+wire          main_litedramcore_bankmachine7_wrport_we;
+wire          main_litedramcore_cas_allowed;
+wire          main_litedramcore_choose_cmd_ce;
+wire   [14:0] main_litedramcore_choose_cmd_cmd_payload_a;
+wire    [2:0] main_litedramcore_choose_cmd_cmd_payload_ba;
+reg           main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+wire          main_litedramcore_choose_cmd_cmd_payload_is_cmd;
+wire          main_litedramcore_choose_cmd_cmd_payload_is_read;
+wire          main_litedramcore_choose_cmd_cmd_payload_is_write;
+reg           main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+reg           main_litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire          main_litedramcore_choose_cmd_cmd_valid;
+reg     [2:0] main_litedramcore_choose_cmd_grant = 3'd0;
+wire    [7:0] main_litedramcore_choose_cmd_request;
+reg     [7:0] main_litedramcore_choose_cmd_valids = 8'd0;
+reg           main_litedramcore_choose_cmd_want_activates = 1'd0;
+reg           main_litedramcore_choose_cmd_want_cmds = 1'd0;
+reg           main_litedramcore_choose_cmd_want_reads = 1'd0;
+reg           main_litedramcore_choose_cmd_want_writes = 1'd0;
+wire          main_litedramcore_choose_req_ce;
+wire   [14:0] main_litedramcore_choose_req_cmd_payload_a;
+wire    [2:0] main_litedramcore_choose_req_cmd_payload_ba;
+reg           main_litedramcore_choose_req_cmd_payload_cas = 1'd0;
+wire          main_litedramcore_choose_req_cmd_payload_is_cmd;
+wire          main_litedramcore_choose_req_cmd_payload_is_read;
+wire          main_litedramcore_choose_req_cmd_payload_is_write;
+reg           main_litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_choose_req_cmd_payload_we = 1'd0;
+reg           main_litedramcore_choose_req_cmd_ready = 1'd0;
+wire          main_litedramcore_choose_req_cmd_valid;
+reg     [2:0] main_litedramcore_choose_req_grant = 3'd0;
+wire    [7:0] main_litedramcore_choose_req_request;
+reg     [7:0] main_litedramcore_choose_req_valids = 8'd0;
+reg           main_litedramcore_choose_req_want_activates = 1'd0;
+reg           main_litedramcore_choose_req_want_cmds = 1'd0;
+reg           main_litedramcore_choose_req_want_reads = 1'd0;
+reg           main_litedramcore_choose_req_want_writes = 1'd0;
+wire          main_litedramcore_cke;
+reg           main_litedramcore_cmd_last = 1'd0;
+reg    [14:0] main_litedramcore_cmd_payload_a = 15'd0;
+reg     [2:0] main_litedramcore_cmd_payload_ba = 3'd0;
+reg           main_litedramcore_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_cmd_payload_we = 1'd0;
+reg           main_litedramcore_cmd_ready = 1'd0;
+reg           main_litedramcore_cmd_valid = 1'd0;
+reg           main_litedramcore_csr_dfi_p0_act_n = 1'd1;
+wire   [14:0] main_litedramcore_csr_dfi_p0_address;
+wire    [2:0] main_litedramcore_csr_dfi_p0_bank;
+reg           main_litedramcore_csr_dfi_p0_cas_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p0_cke = 1'd0;
+reg           main_litedramcore_csr_dfi_p0_cs_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p0_odt = 1'd0;
+reg           main_litedramcore_csr_dfi_p0_ras_n = 1'd1;
+reg    [63:0] main_litedramcore_csr_dfi_p0_rddata = 64'd0;
+wire          main_litedramcore_csr_dfi_p0_rddata_en;
+reg           main_litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
+wire          main_litedramcore_csr_dfi_p0_reset_n;
+reg           main_litedramcore_csr_dfi_p0_we_n = 1'd1;
+wire   [63:0] main_litedramcore_csr_dfi_p0_wrdata;
+wire          main_litedramcore_csr_dfi_p0_wrdata_en;
+wire    [7:0] main_litedramcore_csr_dfi_p0_wrdata_mask;
+reg           main_litedramcore_csr_dfi_p1_act_n = 1'd1;
+wire   [14:0] main_litedramcore_csr_dfi_p1_address;
+wire    [2:0] main_litedramcore_csr_dfi_p1_bank;
+reg           main_litedramcore_csr_dfi_p1_cas_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p1_cke = 1'd0;
+reg           main_litedramcore_csr_dfi_p1_cs_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p1_odt = 1'd0;
+reg           main_litedramcore_csr_dfi_p1_ras_n = 1'd1;
+reg    [63:0] main_litedramcore_csr_dfi_p1_rddata = 64'd0;
+wire          main_litedramcore_csr_dfi_p1_rddata_en;
+reg           main_litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
+wire          main_litedramcore_csr_dfi_p1_reset_n;
+reg           main_litedramcore_csr_dfi_p1_we_n = 1'd1;
+wire   [63:0] main_litedramcore_csr_dfi_p1_wrdata;
+wire          main_litedramcore_csr_dfi_p1_wrdata_en;
+wire    [7:0] main_litedramcore_csr_dfi_p1_wrdata_mask;
+reg           main_litedramcore_csr_dfi_p2_act_n = 1'd1;
+wire   [14:0] main_litedramcore_csr_dfi_p2_address;
+wire    [2:0] main_litedramcore_csr_dfi_p2_bank;
+reg           main_litedramcore_csr_dfi_p2_cas_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p2_cke = 1'd0;
+reg           main_litedramcore_csr_dfi_p2_cs_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p2_odt = 1'd0;
+reg           main_litedramcore_csr_dfi_p2_ras_n = 1'd1;
+reg    [63:0] main_litedramcore_csr_dfi_p2_rddata = 64'd0;
+wire          main_litedramcore_csr_dfi_p2_rddata_en;
+reg           main_litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
+wire          main_litedramcore_csr_dfi_p2_reset_n;
+reg           main_litedramcore_csr_dfi_p2_we_n = 1'd1;
+wire   [63:0] main_litedramcore_csr_dfi_p2_wrdata;
+wire          main_litedramcore_csr_dfi_p2_wrdata_en;
+wire    [7:0] main_litedramcore_csr_dfi_p2_wrdata_mask;
+reg           main_litedramcore_csr_dfi_p3_act_n = 1'd1;
+wire   [14:0] main_litedramcore_csr_dfi_p3_address;
+wire    [2:0] main_litedramcore_csr_dfi_p3_bank;
+reg           main_litedramcore_csr_dfi_p3_cas_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p3_cke = 1'd0;
+reg           main_litedramcore_csr_dfi_p3_cs_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p3_odt = 1'd0;
+reg           main_litedramcore_csr_dfi_p3_ras_n = 1'd1;
+reg    [63:0] main_litedramcore_csr_dfi_p3_rddata = 64'd0;
+wire          main_litedramcore_csr_dfi_p3_rddata_en;
+reg           main_litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
+wire          main_litedramcore_csr_dfi_p3_reset_n;
+reg           main_litedramcore_csr_dfi_p3_we_n = 1'd1;
+wire   [63:0] main_litedramcore_csr_dfi_p3_wrdata;
+wire          main_litedramcore_csr_dfi_p3_wrdata_en;
+wire    [7:0] main_litedramcore_csr_dfi_p3_wrdata_mask;
+reg           main_litedramcore_dfi_p0_act_n = 1'd1;
+reg    [14:0] main_litedramcore_dfi_p0_address = 15'd0;
+reg     [2:0] main_litedramcore_dfi_p0_bank = 3'd0;
+reg           main_litedramcore_dfi_p0_cas_n = 1'd1;
+wire          main_litedramcore_dfi_p0_cke;
+reg           main_litedramcore_dfi_p0_cs_n = 1'd1;
+wire          main_litedramcore_dfi_p0_odt;
+reg           main_litedramcore_dfi_p0_ras_n = 1'd1;
+wire   [63:0] main_litedramcore_dfi_p0_rddata;
+reg           main_litedramcore_dfi_p0_rddata_en = 1'd0;
+wire          main_litedramcore_dfi_p0_rddata_valid;
+wire          main_litedramcore_dfi_p0_reset_n;
+reg           main_litedramcore_dfi_p0_we_n = 1'd1;
+wire   [63:0] main_litedramcore_dfi_p0_wrdata;
+reg           main_litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire    [7:0] main_litedramcore_dfi_p0_wrdata_mask;
+reg           main_litedramcore_dfi_p1_act_n = 1'd1;
+reg    [14:0] main_litedramcore_dfi_p1_address = 15'd0;
+reg     [2:0] main_litedramcore_dfi_p1_bank = 3'd0;
+reg           main_litedramcore_dfi_p1_cas_n = 1'd1;
+wire          main_litedramcore_dfi_p1_cke;
+reg           main_litedramcore_dfi_p1_cs_n = 1'd1;
+wire          main_litedramcore_dfi_p1_odt;
+reg           main_litedramcore_dfi_p1_ras_n = 1'd1;
+wire   [63:0] main_litedramcore_dfi_p1_rddata;
+reg           main_litedramcore_dfi_p1_rddata_en = 1'd0;
+wire          main_litedramcore_dfi_p1_rddata_valid;
+wire          main_litedramcore_dfi_p1_reset_n;
+reg           main_litedramcore_dfi_p1_we_n = 1'd1;
+wire   [63:0] main_litedramcore_dfi_p1_wrdata;
+reg           main_litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire    [7:0] main_litedramcore_dfi_p1_wrdata_mask;
+reg           main_litedramcore_dfi_p2_act_n = 1'd1;
+reg    [14:0] main_litedramcore_dfi_p2_address = 15'd0;
+reg     [2:0] main_litedramcore_dfi_p2_bank = 3'd0;
+reg           main_litedramcore_dfi_p2_cas_n = 1'd1;
+wire          main_litedramcore_dfi_p2_cke;
+reg           main_litedramcore_dfi_p2_cs_n = 1'd1;
+wire          main_litedramcore_dfi_p2_odt;
+reg           main_litedramcore_dfi_p2_ras_n = 1'd1;
+wire   [63:0] main_litedramcore_dfi_p2_rddata;
+reg           main_litedramcore_dfi_p2_rddata_en = 1'd0;
+wire          main_litedramcore_dfi_p2_rddata_valid;
+wire          main_litedramcore_dfi_p2_reset_n;
+reg           main_litedramcore_dfi_p2_we_n = 1'd1;
+wire   [63:0] main_litedramcore_dfi_p2_wrdata;
+reg           main_litedramcore_dfi_p2_wrdata_en = 1'd0;
+wire    [7:0] main_litedramcore_dfi_p2_wrdata_mask;
+reg           main_litedramcore_dfi_p3_act_n = 1'd1;
+reg    [14:0] main_litedramcore_dfi_p3_address = 15'd0;
+reg     [2:0] main_litedramcore_dfi_p3_bank = 3'd0;
+reg           main_litedramcore_dfi_p3_cas_n = 1'd1;
+wire          main_litedramcore_dfi_p3_cke;
+reg           main_litedramcore_dfi_p3_cs_n = 1'd1;
+wire          main_litedramcore_dfi_p3_odt;
+reg           main_litedramcore_dfi_p3_ras_n = 1'd1;
+wire   [63:0] main_litedramcore_dfi_p3_rddata;
+reg           main_litedramcore_dfi_p3_rddata_en = 1'd0;
+wire          main_litedramcore_dfi_p3_rddata_valid;
+wire          main_litedramcore_dfi_p3_reset_n;
+reg           main_litedramcore_dfi_p3_we_n = 1'd1;
+wire   [63:0] main_litedramcore_dfi_p3_wrdata;
+reg           main_litedramcore_dfi_p3_wrdata_en = 1'd0;
+wire    [7:0] main_litedramcore_dfi_p3_wrdata_mask;
+reg           main_litedramcore_en0 = 1'd0;
+reg           main_litedramcore_en1 = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_act_n = 1'd1;
+reg    [14:0] main_litedramcore_ext_dfi_p0_address = 15'd0;
+reg     [2:0] main_litedramcore_ext_dfi_p0_bank = 3'd0;
+reg           main_litedramcore_ext_dfi_p0_cas_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p0_cke = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_cs_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p0_odt = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_ras_n = 1'd1;
+reg    [63:0] main_litedramcore_ext_dfi_p0_rddata = 64'd0;
+reg           main_litedramcore_ext_dfi_p0_rddata_en = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_reset_n = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_we_n = 1'd1;
+reg    [63:0] main_litedramcore_ext_dfi_p0_wrdata = 64'd0;
+reg           main_litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
+reg     [7:0] main_litedramcore_ext_dfi_p0_wrdata_mask = 8'd0;
+reg           main_litedramcore_ext_dfi_p1_act_n = 1'd1;
+reg    [14:0] main_litedramcore_ext_dfi_p1_address = 15'd0;
+reg     [2:0] main_litedramcore_ext_dfi_p1_bank = 3'd0;
+reg           main_litedramcore_ext_dfi_p1_cas_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p1_cke = 1'd0;
+reg           main_litedramcore_ext_dfi_p1_cs_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p1_odt = 1'd0;
+reg           main_litedramcore_ext_dfi_p1_ras_n = 1'd1;
+reg    [63:0] main_litedramcore_ext_dfi_p1_rddata = 64'd0;
+reg           main_litedramcore_ext_dfi_p1_rddata_en = 1'd0;
+reg           main_litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
+reg           main_litedramcore_ext_dfi_p1_reset_n = 1'd0;
+reg           main_litedramcore_ext_dfi_p1_we_n = 1'd1;
+reg    [63:0] main_litedramcore_ext_dfi_p1_wrdata = 64'd0;
+reg           main_litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
+reg     [7:0] main_litedramcore_ext_dfi_p1_wrdata_mask = 8'd0;
+reg           main_litedramcore_ext_dfi_p2_act_n = 1'd1;
+reg    [14:0] main_litedramcore_ext_dfi_p2_address = 15'd0;
+reg     [2:0] main_litedramcore_ext_dfi_p2_bank = 3'd0;
+reg           main_litedramcore_ext_dfi_p2_cas_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p2_cke = 1'd0;
+reg           main_litedramcore_ext_dfi_p2_cs_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p2_odt = 1'd0;
+reg           main_litedramcore_ext_dfi_p2_ras_n = 1'd1;
+reg    [63:0] main_litedramcore_ext_dfi_p2_rddata = 64'd0;
+reg           main_litedramcore_ext_dfi_p2_rddata_en = 1'd0;
+reg           main_litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
+reg           main_litedramcore_ext_dfi_p2_reset_n = 1'd0;
+reg           main_litedramcore_ext_dfi_p2_we_n = 1'd1;
+reg    [63:0] main_litedramcore_ext_dfi_p2_wrdata = 64'd0;
+reg           main_litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
+reg     [7:0] main_litedramcore_ext_dfi_p2_wrdata_mask = 8'd0;
+reg           main_litedramcore_ext_dfi_p3_act_n = 1'd1;
+reg    [14:0] main_litedramcore_ext_dfi_p3_address = 15'd0;
+reg     [2:0] main_litedramcore_ext_dfi_p3_bank = 3'd0;
+reg           main_litedramcore_ext_dfi_p3_cas_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p3_cke = 1'd0;
+reg           main_litedramcore_ext_dfi_p3_cs_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p3_odt = 1'd0;
+reg           main_litedramcore_ext_dfi_p3_ras_n = 1'd1;
+reg    [63:0] main_litedramcore_ext_dfi_p3_rddata = 64'd0;
+reg           main_litedramcore_ext_dfi_p3_rddata_en = 1'd0;
+reg           main_litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
+reg           main_litedramcore_ext_dfi_p3_reset_n = 1'd0;
+reg           main_litedramcore_ext_dfi_p3_we_n = 1'd1;
+reg    [63:0] main_litedramcore_ext_dfi_p3_wrdata = 64'd0;
+reg           main_litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
+reg     [7:0] main_litedramcore_ext_dfi_p3_wrdata_mask = 8'd0;
+reg           main_litedramcore_ext_dfi_sel = 1'd0;
+wire          main_litedramcore_go_to_refresh;
+wire   [21:0] main_litedramcore_interface_bank0_addr;
+wire          main_litedramcore_interface_bank0_lock;
+wire          main_litedramcore_interface_bank0_rdata_valid;
+wire          main_litedramcore_interface_bank0_ready;
+wire          main_litedramcore_interface_bank0_valid;
+wire          main_litedramcore_interface_bank0_wdata_ready;
+wire          main_litedramcore_interface_bank0_we;
+wire   [21:0] main_litedramcore_interface_bank1_addr;
+wire          main_litedramcore_interface_bank1_lock;
+wire          main_litedramcore_interface_bank1_rdata_valid;
+wire          main_litedramcore_interface_bank1_ready;
+wire          main_litedramcore_interface_bank1_valid;
+wire          main_litedramcore_interface_bank1_wdata_ready;
+wire          main_litedramcore_interface_bank1_we;
+wire   [21:0] main_litedramcore_interface_bank2_addr;
+wire          main_litedramcore_interface_bank2_lock;
+wire          main_litedramcore_interface_bank2_rdata_valid;
+wire          main_litedramcore_interface_bank2_ready;
+wire          main_litedramcore_interface_bank2_valid;
+wire          main_litedramcore_interface_bank2_wdata_ready;
+wire          main_litedramcore_interface_bank2_we;
+wire   [21:0] main_litedramcore_interface_bank3_addr;
+wire          main_litedramcore_interface_bank3_lock;
+wire          main_litedramcore_interface_bank3_rdata_valid;
+wire          main_litedramcore_interface_bank3_ready;
+wire          main_litedramcore_interface_bank3_valid;
+wire          main_litedramcore_interface_bank3_wdata_ready;
+wire          main_litedramcore_interface_bank3_we;
+wire   [21:0] main_litedramcore_interface_bank4_addr;
+wire          main_litedramcore_interface_bank4_lock;
+wire          main_litedramcore_interface_bank4_rdata_valid;
+wire          main_litedramcore_interface_bank4_ready;
+wire          main_litedramcore_interface_bank4_valid;
+wire          main_litedramcore_interface_bank4_wdata_ready;
+wire          main_litedramcore_interface_bank4_we;
+wire   [21:0] main_litedramcore_interface_bank5_addr;
+wire          main_litedramcore_interface_bank5_lock;
+wire          main_litedramcore_interface_bank5_rdata_valid;
+wire          main_litedramcore_interface_bank5_ready;
+wire          main_litedramcore_interface_bank5_valid;
+wire          main_litedramcore_interface_bank5_wdata_ready;
+wire          main_litedramcore_interface_bank5_we;
+wire   [21:0] main_litedramcore_interface_bank6_addr;
+wire          main_litedramcore_interface_bank6_lock;
+wire          main_litedramcore_interface_bank6_rdata_valid;
+wire          main_litedramcore_interface_bank6_ready;
+wire          main_litedramcore_interface_bank6_valid;
+wire          main_litedramcore_interface_bank6_wdata_ready;
+wire          main_litedramcore_interface_bank6_we;
+wire   [21:0] main_litedramcore_interface_bank7_addr;
+wire          main_litedramcore_interface_bank7_lock;
+wire          main_litedramcore_interface_bank7_rdata_valid;
+wire          main_litedramcore_interface_bank7_ready;
+wire          main_litedramcore_interface_bank7_valid;
+wire          main_litedramcore_interface_bank7_wdata_ready;
+wire          main_litedramcore_interface_bank7_we;
+wire  [255:0] main_litedramcore_interface_rdata;
+reg   [255:0] main_litedramcore_interface_wdata = 256'd0;
+reg    [31:0] main_litedramcore_interface_wdata_we = 32'd0;
+reg           main_litedramcore_master_p0_act_n = 1'd1;
+reg    [14:0] main_litedramcore_master_p0_address = 15'd0;
+reg     [2:0] main_litedramcore_master_p0_bank = 3'd0;
+reg           main_litedramcore_master_p0_cas_n = 1'd1;
+reg           main_litedramcore_master_p0_cke = 1'd0;
+reg           main_litedramcore_master_p0_cs_n = 1'd1;
+reg           main_litedramcore_master_p0_odt = 1'd0;
+reg           main_litedramcore_master_p0_ras_n = 1'd1;
+wire   [63:0] main_litedramcore_master_p0_rddata;
+reg           main_litedramcore_master_p0_rddata_en = 1'd0;
+wire          main_litedramcore_master_p0_rddata_valid;
+reg           main_litedramcore_master_p0_reset_n = 1'd0;
+reg           main_litedramcore_master_p0_we_n = 1'd1;
+reg    [63:0] main_litedramcore_master_p0_wrdata = 64'd0;
+reg           main_litedramcore_master_p0_wrdata_en = 1'd0;
+reg     [7:0] main_litedramcore_master_p0_wrdata_mask = 8'd0;
+reg           main_litedramcore_master_p1_act_n = 1'd1;
+reg    [14:0] main_litedramcore_master_p1_address = 15'd0;
+reg     [2:0] main_litedramcore_master_p1_bank = 3'd0;
+reg           main_litedramcore_master_p1_cas_n = 1'd1;
+reg           main_litedramcore_master_p1_cke = 1'd0;
+reg           main_litedramcore_master_p1_cs_n = 1'd1;
+reg           main_litedramcore_master_p1_odt = 1'd0;
+reg           main_litedramcore_master_p1_ras_n = 1'd1;
+wire   [63:0] main_litedramcore_master_p1_rddata;
+reg           main_litedramcore_master_p1_rddata_en = 1'd0;
+wire          main_litedramcore_master_p1_rddata_valid;
+reg           main_litedramcore_master_p1_reset_n = 1'd0;
+reg           main_litedramcore_master_p1_we_n = 1'd1;
+reg    [63:0] main_litedramcore_master_p1_wrdata = 64'd0;
+reg           main_litedramcore_master_p1_wrdata_en = 1'd0;
+reg     [7:0] main_litedramcore_master_p1_wrdata_mask = 8'd0;
+reg           main_litedramcore_master_p2_act_n = 1'd1;
+reg    [14:0] main_litedramcore_master_p2_address = 15'd0;
+reg     [2:0] main_litedramcore_master_p2_bank = 3'd0;
+reg           main_litedramcore_master_p2_cas_n = 1'd1;
+reg           main_litedramcore_master_p2_cke = 1'd0;
+reg           main_litedramcore_master_p2_cs_n = 1'd1;
+reg           main_litedramcore_master_p2_odt = 1'd0;
+reg           main_litedramcore_master_p2_ras_n = 1'd1;
+wire   [63:0] main_litedramcore_master_p2_rddata;
+reg           main_litedramcore_master_p2_rddata_en = 1'd0;
+wire          main_litedramcore_master_p2_rddata_valid;
+reg           main_litedramcore_master_p2_reset_n = 1'd0;
+reg           main_litedramcore_master_p2_we_n = 1'd1;
+reg    [63:0] main_litedramcore_master_p2_wrdata = 64'd0;
+reg           main_litedramcore_master_p2_wrdata_en = 1'd0;
+reg     [7:0] main_litedramcore_master_p2_wrdata_mask = 8'd0;
+reg           main_litedramcore_master_p3_act_n = 1'd1;
+reg    [14:0] main_litedramcore_master_p3_address = 15'd0;
+reg     [2:0] main_litedramcore_master_p3_bank = 3'd0;
+reg           main_litedramcore_master_p3_cas_n = 1'd1;
+reg           main_litedramcore_master_p3_cke = 1'd0;
+reg           main_litedramcore_master_p3_cs_n = 1'd1;
+reg           main_litedramcore_master_p3_odt = 1'd0;
+reg           main_litedramcore_master_p3_ras_n = 1'd1;
+wire   [63:0] main_litedramcore_master_p3_rddata;
+reg           main_litedramcore_master_p3_rddata_en = 1'd0;
+wire          main_litedramcore_master_p3_rddata_valid;
+reg           main_litedramcore_master_p3_reset_n = 1'd0;
+reg           main_litedramcore_master_p3_we_n = 1'd1;
+reg    [63:0] main_litedramcore_master_p3_wrdata = 64'd0;
+reg           main_litedramcore_master_p3_wrdata_en = 1'd0;
+reg     [7:0] main_litedramcore_master_p3_wrdata_mask = 8'd0;
+wire          main_litedramcore_max_time0;
+wire          main_litedramcore_max_time1;
+reg    [14:0] main_litedramcore_nop_a = 15'd0;
+reg     [2:0] main_litedramcore_nop_ba = 3'd0;
+wire    [1:0] main_litedramcore_nphases;
+wire          main_litedramcore_odt;
+reg           main_litedramcore_phaseinjector0_address_re = 1'd0;
+reg    [14:0] main_litedramcore_phaseinjector0_address_storage = 15'd0;
+reg           main_litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg     [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0;
+wire          main_litedramcore_phaseinjector0_command_issue_r;
+reg           main_litedramcore_phaseinjector0_command_issue_re = 1'd0;
+reg           main_litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg           main_litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg           main_litedramcore_phaseinjector0_command_re = 1'd0;
+reg     [7:0] main_litedramcore_phaseinjector0_command_storage = 8'd0;
+wire          main_litedramcore_phaseinjector0_csrfield_cas;
+wire          main_litedramcore_phaseinjector0_csrfield_cs;
+wire          main_litedramcore_phaseinjector0_csrfield_cs_bottom;
+wire          main_litedramcore_phaseinjector0_csrfield_cs_top;
+wire          main_litedramcore_phaseinjector0_csrfield_ras;
+wire          main_litedramcore_phaseinjector0_csrfield_rden;
+wire          main_litedramcore_phaseinjector0_csrfield_we;
+wire          main_litedramcore_phaseinjector0_csrfield_wren;
+reg           main_litedramcore_phaseinjector0_rddata_re = 1'd0;
+reg    [63:0] main_litedramcore_phaseinjector0_rddata_status = 64'd0;
+wire          main_litedramcore_phaseinjector0_rddata_we;
+reg           main_litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg    [63:0] main_litedramcore_phaseinjector0_wrdata_storage = 64'd0;
+reg           main_litedramcore_phaseinjector1_address_re = 1'd0;
+reg    [14:0] main_litedramcore_phaseinjector1_address_storage = 15'd0;
+reg           main_litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg     [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0;
+wire          main_litedramcore_phaseinjector1_command_issue_r;
+reg           main_litedramcore_phaseinjector1_command_issue_re = 1'd0;
+reg           main_litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg           main_litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg           main_litedramcore_phaseinjector1_command_re = 1'd0;
+reg     [7:0] main_litedramcore_phaseinjector1_command_storage = 8'd0;
+wire          main_litedramcore_phaseinjector1_csrfield_cas;
+wire          main_litedramcore_phaseinjector1_csrfield_cs;
+wire          main_litedramcore_phaseinjector1_csrfield_cs_bottom;
+wire          main_litedramcore_phaseinjector1_csrfield_cs_top;
+wire          main_litedramcore_phaseinjector1_csrfield_ras;
+wire          main_litedramcore_phaseinjector1_csrfield_rden;
+wire          main_litedramcore_phaseinjector1_csrfield_we;
+wire          main_litedramcore_phaseinjector1_csrfield_wren;
+reg           main_litedramcore_phaseinjector1_rddata_re = 1'd0;
+reg    [63:0] main_litedramcore_phaseinjector1_rddata_status = 64'd0;
+wire          main_litedramcore_phaseinjector1_rddata_we;
+reg           main_litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg    [63:0] main_litedramcore_phaseinjector1_wrdata_storage = 64'd0;
+reg           main_litedramcore_phaseinjector2_address_re = 1'd0;
+reg    [14:0] main_litedramcore_phaseinjector2_address_storage = 15'd0;
+reg           main_litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg     [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0;
+wire          main_litedramcore_phaseinjector2_command_issue_r;
+reg           main_litedramcore_phaseinjector2_command_issue_re = 1'd0;
+reg           main_litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg           main_litedramcore_phaseinjector2_command_issue_we = 1'd0;
+reg           main_litedramcore_phaseinjector2_command_re = 1'd0;
+reg     [7:0] main_litedramcore_phaseinjector2_command_storage = 8'd0;
+wire          main_litedramcore_phaseinjector2_csrfield_cas;
+wire          main_litedramcore_phaseinjector2_csrfield_cs;
+wire          main_litedramcore_phaseinjector2_csrfield_cs_bottom;
+wire          main_litedramcore_phaseinjector2_csrfield_cs_top;
+wire          main_litedramcore_phaseinjector2_csrfield_ras;
+wire          main_litedramcore_phaseinjector2_csrfield_rden;
+wire          main_litedramcore_phaseinjector2_csrfield_we;
+wire          main_litedramcore_phaseinjector2_csrfield_wren;
+reg           main_litedramcore_phaseinjector2_rddata_re = 1'd0;
+reg    [63:0] main_litedramcore_phaseinjector2_rddata_status = 64'd0;
+wire          main_litedramcore_phaseinjector2_rddata_we;
+reg           main_litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg    [63:0] main_litedramcore_phaseinjector2_wrdata_storage = 64'd0;
+reg           main_litedramcore_phaseinjector3_address_re = 1'd0;
+reg    [14:0] main_litedramcore_phaseinjector3_address_storage = 15'd0;
+reg           main_litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg     [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0;
+wire          main_litedramcore_phaseinjector3_command_issue_r;
+reg           main_litedramcore_phaseinjector3_command_issue_re = 1'd0;
+reg           main_litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg           main_litedramcore_phaseinjector3_command_issue_we = 1'd0;
+reg           main_litedramcore_phaseinjector3_command_re = 1'd0;
+reg     [7:0] main_litedramcore_phaseinjector3_command_storage = 8'd0;
+wire          main_litedramcore_phaseinjector3_csrfield_cas;
+wire          main_litedramcore_phaseinjector3_csrfield_cs;
+wire          main_litedramcore_phaseinjector3_csrfield_cs_bottom;
+wire          main_litedramcore_phaseinjector3_csrfield_cs_top;
+wire          main_litedramcore_phaseinjector3_csrfield_ras;
+wire          main_litedramcore_phaseinjector3_csrfield_rden;
+wire          main_litedramcore_phaseinjector3_csrfield_we;
+wire          main_litedramcore_phaseinjector3_csrfield_wren;
+reg           main_litedramcore_phaseinjector3_rddata_re = 1'd0;
+reg    [63:0] main_litedramcore_phaseinjector3_rddata_status = 64'd0;
+wire          main_litedramcore_phaseinjector3_rddata_we;
+reg           main_litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg    [63:0] main_litedramcore_phaseinjector3_wrdata_storage = 64'd0;
+reg           main_litedramcore_postponer_count = 1'd0;
+wire          main_litedramcore_postponer_req_i;
+reg           main_litedramcore_postponer_req_o = 1'd0;
+wire          main_litedramcore_ras_allowed;
+wire    [1:0] main_litedramcore_rdphase;
+reg           main_litedramcore_re = 1'd0;
+wire          main_litedramcore_read_available;
+wire          main_litedramcore_reset_n;
+wire          main_litedramcore_sel;
+reg           main_litedramcore_sequencer_count = 1'd0;
+wire          main_litedramcore_sequencer_done0;
+reg           main_litedramcore_sequencer_done1 = 1'd0;
+reg           main_litedramcore_sequencer_start0 = 1'd0;
+wire          main_litedramcore_sequencer_start1;
+reg     [5:0] main_litedramcore_sequencer_trigger = 6'd0;
+wire          main_litedramcore_slave_p0_act_n;
+wire   [14:0] main_litedramcore_slave_p0_address;
+wire    [2:0] main_litedramcore_slave_p0_bank;
+wire          main_litedramcore_slave_p0_cas_n;
+wire          main_litedramcore_slave_p0_cke;
+wire          main_litedramcore_slave_p0_cs_n;
+wire          main_litedramcore_slave_p0_odt;
+wire          main_litedramcore_slave_p0_ras_n;
+reg    [63:0] main_litedramcore_slave_p0_rddata = 64'd0;
+wire          main_litedramcore_slave_p0_rddata_en;
+reg           main_litedramcore_slave_p0_rddata_valid = 1'd0;
+wire          main_litedramcore_slave_p0_reset_n;
+wire          main_litedramcore_slave_p0_we_n;
+wire   [63:0] main_litedramcore_slave_p0_wrdata;
+wire          main_litedramcore_slave_p0_wrdata_en;
+wire    [7:0] main_litedramcore_slave_p0_wrdata_mask;
+wire          main_litedramcore_slave_p1_act_n;
+wire   [14:0] main_litedramcore_slave_p1_address;
+wire    [2:0] main_litedramcore_slave_p1_bank;
+wire          main_litedramcore_slave_p1_cas_n;
+wire          main_litedramcore_slave_p1_cke;
+wire          main_litedramcore_slave_p1_cs_n;
+wire          main_litedramcore_slave_p1_odt;
+wire          main_litedramcore_slave_p1_ras_n;
+reg    [63:0] main_litedramcore_slave_p1_rddata = 64'd0;
+wire          main_litedramcore_slave_p1_rddata_en;
+reg           main_litedramcore_slave_p1_rddata_valid = 1'd0;
+wire          main_litedramcore_slave_p1_reset_n;
+wire          main_litedramcore_slave_p1_we_n;
+wire   [63:0] main_litedramcore_slave_p1_wrdata;
+wire          main_litedramcore_slave_p1_wrdata_en;
+wire    [7:0] main_litedramcore_slave_p1_wrdata_mask;
+wire          main_litedramcore_slave_p2_act_n;
+wire   [14:0] main_litedramcore_slave_p2_address;
+wire    [2:0] main_litedramcore_slave_p2_bank;
+wire          main_litedramcore_slave_p2_cas_n;
+wire          main_litedramcore_slave_p2_cke;
+wire          main_litedramcore_slave_p2_cs_n;
+wire          main_litedramcore_slave_p2_odt;
+wire          main_litedramcore_slave_p2_ras_n;
+reg    [63:0] main_litedramcore_slave_p2_rddata = 64'd0;
+wire          main_litedramcore_slave_p2_rddata_en;
+reg           main_litedramcore_slave_p2_rddata_valid = 1'd0;
+wire          main_litedramcore_slave_p2_reset_n;
+wire          main_litedramcore_slave_p2_we_n;
+wire   [63:0] main_litedramcore_slave_p2_wrdata;
+wire          main_litedramcore_slave_p2_wrdata_en;
+wire    [7:0] main_litedramcore_slave_p2_wrdata_mask;
+wire          main_litedramcore_slave_p3_act_n;
+wire   [14:0] main_litedramcore_slave_p3_address;
+wire    [2:0] main_litedramcore_slave_p3_bank;
+wire          main_litedramcore_slave_p3_cas_n;
+wire          main_litedramcore_slave_p3_cke;
+wire          main_litedramcore_slave_p3_cs_n;
+wire          main_litedramcore_slave_p3_odt;
+wire          main_litedramcore_slave_p3_ras_n;
+reg    [63:0] main_litedramcore_slave_p3_rddata = 64'd0;
+wire          main_litedramcore_slave_p3_rddata_en;
+reg           main_litedramcore_slave_p3_rddata_valid = 1'd0;
+wire          main_litedramcore_slave_p3_reset_n;
+wire          main_litedramcore_slave_p3_we_n;
+wire   [63:0] main_litedramcore_slave_p3_wrdata;
+wire          main_litedramcore_slave_p3_wrdata_en;
+wire    [7:0] main_litedramcore_slave_p3_wrdata_mask;
+reg     [1:0] main_litedramcore_steerer0 = 2'd0;
+reg     [1:0] main_litedramcore_steerer1 = 2'd0;
+reg           main_litedramcore_steerer10 = 1'd1;
+reg           main_litedramcore_steerer11 = 1'd1;
+reg     [1:0] main_litedramcore_steerer2 = 2'd0;
+reg     [1:0] main_litedramcore_steerer3 = 2'd0;
+reg           main_litedramcore_steerer4 = 1'd1;
+reg           main_litedramcore_steerer5 = 1'd1;
+reg           main_litedramcore_steerer6 = 1'd1;
+reg           main_litedramcore_steerer7 = 1'd1;
+reg           main_litedramcore_steerer8 = 1'd1;
+reg           main_litedramcore_steerer9 = 1'd1;
+reg     [3:0] main_litedramcore_storage = 4'd1;
+reg           main_litedramcore_tccdcon_count = 1'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_trrdcon_ready = 1'd0;
-reg           litedramcore_trrdcon_count = 1'd0;
-wire          litedramcore_tfawcon_valid;
+reg           main_litedramcore_tccdcon_ready = 1'd0;
+wire          main_litedramcore_tccdcon_valid;
+wire    [2:0] main_litedramcore_tfawcon_count;
 (* dont_touch = "true" *)
-reg           litedramcore_tfawcon_ready = 1'd1;
-wire    [2:0] litedramcore_tfawcon_count;
-reg     [4:0] litedramcore_tfawcon_window = 5'd0;
-wire          litedramcore_tccdcon_valid;
+reg           main_litedramcore_tfawcon_ready = 1'd1;
+wire          main_litedramcore_tfawcon_valid;
+reg     [4:0] main_litedramcore_tfawcon_window = 5'd0;
+reg     [4:0] main_litedramcore_time0 = 5'd0;
+reg     [3:0] main_litedramcore_time1 = 4'd0;
+wire    [9:0] main_litedramcore_timer_count0;
+reg     [9:0] main_litedramcore_timer_count1 = 10'd781;
+wire          main_litedramcore_timer_done0;
+wire          main_litedramcore_timer_done1;
+wire          main_litedramcore_timer_wait;
+reg           main_litedramcore_trrdcon_count = 1'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_tccdcon_ready = 1'd0;
-reg           litedramcore_tccdcon_count = 1'd0;
-wire          litedramcore_twtrcon_valid;
+reg           main_litedramcore_trrdcon_ready = 1'd0;
+wire          main_litedramcore_trrdcon_valid;
+reg     [2:0] main_litedramcore_twtrcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_twtrcon_ready = 1'd0;
-reg     [2:0] litedramcore_twtrcon_count = 3'd0;
-wire          litedramcore_read_available;
-wire          litedramcore_write_available;
-reg           litedramcore_en0 = 1'd0;
-wire          litedramcore_max_time0;
-reg     [4:0] litedramcore_time0 = 5'd0;
-reg           litedramcore_en1 = 1'd0;
-wire          litedramcore_max_time1;
-reg     [3:0] litedramcore_time1 = 4'd0;
-wire          litedramcore_go_to_refresh;
-reg           init_done_storage = 1'd0;
-reg           init_done_re = 1'd0;
-reg           init_error_storage = 1'd0;
-reg           init_error_re = 1'd0;
-wire   [29:0] wb_bus_adr;
-wire   [31:0] wb_bus_dat_w;
-wire   [31:0] wb_bus_dat_r;
-wire    [3:0] wb_bus_sel;
-wire          wb_bus_cyc;
-wire          wb_bus_stb;
-wire          wb_bus_ack;
-wire          wb_bus_we;
-wire    [2:0] wb_bus_cti;
-wire    [1:0] wb_bus_bte;
-wire          wb_bus_err;
-wire          user_enable;
-wire          user_port_cmd_valid;
-wire          user_port_cmd_ready;
-wire          user_port_cmd_payload_we;
-wire   [24:0] user_port_cmd_payload_addr;
-wire          user_port_wdata_valid;
-wire          user_port_wdata_ready;
-wire  [255:0] user_port_wdata_payload_data;
-wire   [31:0] user_port_wdata_payload_we;
-wire          user_port_rdata_valid;
-wire          user_port_rdata_ready;
-wire  [255:0] user_port_rdata_payload_data;
-reg    [13:0] litedramcore_adr = 14'd0;
-reg           litedramcore_we = 1'd0;
-reg    [31:0] litedramcore_dat_w = 32'd0;
-wire   [31:0] litedramcore_dat_r;
-wire   [29:0] litedramcore_wishbone_adr;
-wire   [31:0] litedramcore_wishbone_dat_w;
-reg    [31:0] litedramcore_wishbone_dat_r = 32'd0;
-wire    [3:0] litedramcore_wishbone_sel;
-wire          litedramcore_wishbone_cyc;
-wire          litedramcore_wishbone_stb;
-reg           litedramcore_wishbone_ack = 1'd0;
-wire          litedramcore_wishbone_we;
-wire    [2:0] litedramcore_wishbone_cti;
-wire    [1:0] litedramcore_wishbone_bte;
-reg           litedramcore_wishbone_err = 1'd0;
-wire   [13:0] interface0_bank_bus_adr;
-wire          interface0_bank_bus_we;
-wire   [31:0] interface0_bank_bus_dat_w;
-reg    [31:0] interface0_bank_bus_dat_r = 32'd0;
-reg           csrbank0_init_done0_re = 1'd0;
-wire          csrbank0_init_done0_r;
-reg           csrbank0_init_done0_we = 1'd0;
-wire          csrbank0_init_done0_w;
-reg           csrbank0_init_error0_re = 1'd0;
-wire          csrbank0_init_error0_r;
-reg           csrbank0_init_error0_we = 1'd0;
-wire          csrbank0_init_error0_w;
-wire          csrbank0_sel;
-wire   [13:0] interface1_bank_bus_adr;
-wire          interface1_bank_bus_we;
-wire   [31:0] interface1_bank_bus_dat_w;
-reg    [31:0] interface1_bank_bus_dat_r = 32'd0;
-reg           csrbank1_rst0_re = 1'd0;
-wire          csrbank1_rst0_r;
-reg           csrbank1_rst0_we = 1'd0;
-wire          csrbank1_rst0_w;
-reg           csrbank1_dly_sel0_re = 1'd0;
-wire    [3:0] csrbank1_dly_sel0_r;
-reg           csrbank1_dly_sel0_we = 1'd0;
-wire    [3:0] csrbank1_dly_sel0_w;
-reg           csrbank1_half_sys8x_taps0_re = 1'd0;
-wire    [4:0] csrbank1_half_sys8x_taps0_r;
-reg           csrbank1_half_sys8x_taps0_we = 1'd0;
-wire    [4:0] csrbank1_half_sys8x_taps0_w;
-reg           csrbank1_wlevel_en0_re = 1'd0;
-wire          csrbank1_wlevel_en0_r;
-reg           csrbank1_wlevel_en0_we = 1'd0;
-wire          csrbank1_wlevel_en0_w;
-reg           csrbank1_rdphase0_re = 1'd0;
-wire    [1:0] csrbank1_rdphase0_r;
-reg           csrbank1_rdphase0_we = 1'd0;
-wire    [1:0] csrbank1_rdphase0_w;
-reg           csrbank1_wrphase0_re = 1'd0;
-wire    [1:0] csrbank1_wrphase0_r;
-reg           csrbank1_wrphase0_we = 1'd0;
-wire    [1:0] csrbank1_wrphase0_w;
-wire          csrbank1_sel;
-wire   [13:0] interface2_bank_bus_adr;
-wire          interface2_bank_bus_we;
-wire   [31:0] interface2_bank_bus_dat_w;
-reg    [31:0] interface2_bank_bus_dat_r = 32'd0;
-reg           csrbank2_dfii_control0_re = 1'd0;
-wire    [3:0] csrbank2_dfii_control0_r;
-reg           csrbank2_dfii_control0_we = 1'd0;
-wire    [3:0] csrbank2_dfii_control0_w;
-reg           csrbank2_dfii_pi0_command0_re = 1'd0;
-wire    [5:0] csrbank2_dfii_pi0_command0_r;
-reg           csrbank2_dfii_pi0_command0_we = 1'd0;
-wire    [5:0] csrbank2_dfii_pi0_command0_w;
-reg           csrbank2_dfii_pi0_address0_re = 1'd0;
-wire   [14:0] csrbank2_dfii_pi0_address0_r;
-reg           csrbank2_dfii_pi0_address0_we = 1'd0;
-wire   [14:0] csrbank2_dfii_pi0_address0_w;
-reg           csrbank2_dfii_pi0_baddress0_re = 1'd0;
-wire    [2:0] csrbank2_dfii_pi0_baddress0_r;
-reg           csrbank2_dfii_pi0_baddress0_we = 1'd0;
-wire    [2:0] csrbank2_dfii_pi0_baddress0_w;
-reg           csrbank2_dfii_pi0_wrdata1_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_wrdata1_r;
-reg           csrbank2_dfii_pi0_wrdata1_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_wrdata1_w;
-reg           csrbank2_dfii_pi0_wrdata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_wrdata0_r;
-reg           csrbank2_dfii_pi0_wrdata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_wrdata0_w;
-reg           csrbank2_dfii_pi0_rddata1_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_rddata1_r;
-reg           csrbank2_dfii_pi0_rddata1_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_rddata1_w;
-reg           csrbank2_dfii_pi0_rddata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_rddata0_r;
-reg           csrbank2_dfii_pi0_rddata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_rddata0_w;
-reg           csrbank2_dfii_pi1_command0_re = 1'd0;
-wire    [5:0] csrbank2_dfii_pi1_command0_r;
-reg           csrbank2_dfii_pi1_command0_we = 1'd0;
-wire    [5:0] csrbank2_dfii_pi1_command0_w;
-reg           csrbank2_dfii_pi1_address0_re = 1'd0;
-wire   [14:0] csrbank2_dfii_pi1_address0_r;
-reg           csrbank2_dfii_pi1_address0_we = 1'd0;
-wire   [14:0] csrbank2_dfii_pi1_address0_w;
-reg           csrbank2_dfii_pi1_baddress0_re = 1'd0;
-wire    [2:0] csrbank2_dfii_pi1_baddress0_r;
-reg           csrbank2_dfii_pi1_baddress0_we = 1'd0;
-wire    [2:0] csrbank2_dfii_pi1_baddress0_w;
-reg           csrbank2_dfii_pi1_wrdata1_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_wrdata1_r;
-reg           csrbank2_dfii_pi1_wrdata1_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_wrdata1_w;
-reg           csrbank2_dfii_pi1_wrdata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_wrdata0_r;
-reg           csrbank2_dfii_pi1_wrdata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_wrdata0_w;
-reg           csrbank2_dfii_pi1_rddata1_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_rddata1_r;
-reg           csrbank2_dfii_pi1_rddata1_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_rddata1_w;
-reg           csrbank2_dfii_pi1_rddata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_rddata0_r;
-reg           csrbank2_dfii_pi1_rddata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_rddata0_w;
-reg           csrbank2_dfii_pi2_command0_re = 1'd0;
-wire    [5:0] csrbank2_dfii_pi2_command0_r;
-reg           csrbank2_dfii_pi2_command0_we = 1'd0;
-wire    [5:0] csrbank2_dfii_pi2_command0_w;
-reg           csrbank2_dfii_pi2_address0_re = 1'd0;
-wire   [14:0] csrbank2_dfii_pi2_address0_r;
-reg           csrbank2_dfii_pi2_address0_we = 1'd0;
-wire   [14:0] csrbank2_dfii_pi2_address0_w;
-reg           csrbank2_dfii_pi2_baddress0_re = 1'd0;
-wire    [2:0] csrbank2_dfii_pi2_baddress0_r;
-reg           csrbank2_dfii_pi2_baddress0_we = 1'd0;
-wire    [2:0] csrbank2_dfii_pi2_baddress0_w;
-reg           csrbank2_dfii_pi2_wrdata1_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi2_wrdata1_r;
-reg           csrbank2_dfii_pi2_wrdata1_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi2_wrdata1_w;
-reg           csrbank2_dfii_pi2_wrdata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi2_wrdata0_r;
-reg           csrbank2_dfii_pi2_wrdata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi2_wrdata0_w;
-reg           csrbank2_dfii_pi2_rddata1_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi2_rddata1_r;
-reg           csrbank2_dfii_pi2_rddata1_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi2_rddata1_w;
-reg           csrbank2_dfii_pi2_rddata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi2_rddata0_r;
-reg           csrbank2_dfii_pi2_rddata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi2_rddata0_w;
-reg           csrbank2_dfii_pi3_command0_re = 1'd0;
-wire    [5:0] csrbank2_dfii_pi3_command0_r;
-reg           csrbank2_dfii_pi3_command0_we = 1'd0;
-wire    [5:0] csrbank2_dfii_pi3_command0_w;
-reg           csrbank2_dfii_pi3_address0_re = 1'd0;
-wire   [14:0] csrbank2_dfii_pi3_address0_r;
-reg           csrbank2_dfii_pi3_address0_we = 1'd0;
-wire   [14:0] csrbank2_dfii_pi3_address0_w;
-reg           csrbank2_dfii_pi3_baddress0_re = 1'd0;
-wire    [2:0] csrbank2_dfii_pi3_baddress0_r;
-reg           csrbank2_dfii_pi3_baddress0_we = 1'd0;
-wire    [2:0] csrbank2_dfii_pi3_baddress0_w;
-reg           csrbank2_dfii_pi3_wrdata1_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi3_wrdata1_r;
-reg           csrbank2_dfii_pi3_wrdata1_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi3_wrdata1_w;
-reg           csrbank2_dfii_pi3_wrdata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi3_wrdata0_r;
-reg           csrbank2_dfii_pi3_wrdata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi3_wrdata0_w;
-reg           csrbank2_dfii_pi3_rddata1_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi3_rddata1_r;
-reg           csrbank2_dfii_pi3_rddata1_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi3_rddata1_w;
-reg           csrbank2_dfii_pi3_rddata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi3_rddata0_r;
-reg           csrbank2_dfii_pi3_rddata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi3_rddata0_w;
-wire          csrbank2_sel;
-wire   [13:0] csr_interconnect_adr;
-wire          csr_interconnect_we;
-wire   [31:0] csr_interconnect_dat_w;
-wire   [31:0] csr_interconnect_dat_r;
-wire          litedramcore_reset0;
-wire          litedramcore_reset1;
-wire          litedramcore_reset2;
-wire          litedramcore_reset3;
-wire          litedramcore_reset4;
-wire          litedramcore_reset5;
-wire          litedramcore_reset6;
-wire          litedramcore_reset7;
-wire          litedramcore_pll_fb;
-reg     [1:0] litedramcore_refresher_state = 2'd0;
-reg     [1:0] litedramcore_refresher_next_state = 2'd0;
-reg     [3:0] litedramcore_bankmachine0_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine0_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine1_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine1_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine2_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine2_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine3_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine3_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine4_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine4_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine5_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine5_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine6_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine6_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine7_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine7_next_state = 4'd0;
-reg     [3:0] litedramcore_multiplexer_state = 4'd0;
-reg     [3:0] litedramcore_multiplexer_next_state = 4'd0;
-wire          litedramcore_roundrobin0_request;
-wire          litedramcore_roundrobin0_grant;
-wire          litedramcore_roundrobin0_ce;
-wire          litedramcore_roundrobin1_request;
-wire          litedramcore_roundrobin1_grant;
-wire          litedramcore_roundrobin1_ce;
-wire          litedramcore_roundrobin2_request;
-wire          litedramcore_roundrobin2_grant;
-wire          litedramcore_roundrobin2_ce;
-wire          litedramcore_roundrobin3_request;
-wire          litedramcore_roundrobin3_grant;
-wire          litedramcore_roundrobin3_ce;
-wire          litedramcore_roundrobin4_request;
-wire          litedramcore_roundrobin4_grant;
-wire          litedramcore_roundrobin4_ce;
-wire          litedramcore_roundrobin5_request;
-wire          litedramcore_roundrobin5_grant;
-wire          litedramcore_roundrobin5_ce;
-wire          litedramcore_roundrobin6_request;
-wire          litedramcore_roundrobin6_grant;
-wire          litedramcore_roundrobin6_ce;
-wire          litedramcore_roundrobin7_request;
-wire          litedramcore_roundrobin7_grant;
-wire          litedramcore_roundrobin7_ce;
-reg           litedramcore_locked0 = 1'd0;
-reg           litedramcore_locked1 = 1'd0;
-reg           litedramcore_locked2 = 1'd0;
-reg           litedramcore_locked3 = 1'd0;
-reg           litedramcore_locked4 = 1'd0;
-reg           litedramcore_locked5 = 1'd0;
-reg           litedramcore_locked6 = 1'd0;
-reg           litedramcore_locked7 = 1'd0;
-reg           litedramcore_new_master_wdata_ready0 = 1'd0;
-reg           litedramcore_new_master_wdata_ready1 = 1'd0;
-reg           litedramcore_new_master_rdata_valid0 = 1'd0;
-reg           litedramcore_new_master_rdata_valid1 = 1'd0;
-reg           litedramcore_new_master_rdata_valid2 = 1'd0;
-reg           litedramcore_new_master_rdata_valid3 = 1'd0;
-reg           litedramcore_new_master_rdata_valid4 = 1'd0;
-reg           litedramcore_new_master_rdata_valid5 = 1'd0;
-reg           litedramcore_new_master_rdata_valid6 = 1'd0;
-reg           litedramcore_new_master_rdata_valid7 = 1'd0;
-reg           litedramcore_new_master_rdata_valid8 = 1'd0;
-reg     [1:0] litedramcore_state = 2'd0;
-reg     [1:0] litedramcore_next_state = 2'd0;
-reg    [31:0] litedramcore_dat_w_next_value0 = 32'd0;
-reg           litedramcore_dat_w_next_value_ce0 = 1'd0;
-reg    [13:0] litedramcore_adr_next_value1 = 14'd0;
-reg           litedramcore_adr_next_value_ce1 = 1'd0;
-reg           litedramcore_we_next_value2 = 1'd0;
-reg           litedramcore_we_next_value_ce2 = 1'd0;
-reg           rhs_array_muxed0 = 1'd0;
-reg    [14:0] rhs_array_muxed1 = 15'd0;
-reg     [2:0] rhs_array_muxed2 = 3'd0;
-reg           rhs_array_muxed3 = 1'd0;
-reg           rhs_array_muxed4 = 1'd0;
-reg           rhs_array_muxed5 = 1'd0;
-reg           t_array_muxed0 = 1'd0;
-reg           t_array_muxed1 = 1'd0;
-reg           t_array_muxed2 = 1'd0;
-reg           rhs_array_muxed6 = 1'd0;
-reg    [14:0] rhs_array_muxed7 = 15'd0;
-reg     [2:0] rhs_array_muxed8 = 3'd0;
-reg           rhs_array_muxed9 = 1'd0;
-reg           rhs_array_muxed10 = 1'd0;
-reg           rhs_array_muxed11 = 1'd0;
-reg           t_array_muxed3 = 1'd0;
-reg           t_array_muxed4 = 1'd0;
-reg           t_array_muxed5 = 1'd0;
-reg    [21:0] rhs_array_muxed12 = 22'd0;
-reg           rhs_array_muxed13 = 1'd0;
-reg           rhs_array_muxed14 = 1'd0;
-reg    [21:0] rhs_array_muxed15 = 22'd0;
-reg           rhs_array_muxed16 = 1'd0;
-reg           rhs_array_muxed17 = 1'd0;
-reg    [21:0] rhs_array_muxed18 = 22'd0;
-reg           rhs_array_muxed19 = 1'd0;
-reg           rhs_array_muxed20 = 1'd0;
-reg    [21:0] rhs_array_muxed21 = 22'd0;
-reg           rhs_array_muxed22 = 1'd0;
-reg           rhs_array_muxed23 = 1'd0;
-reg    [21:0] rhs_array_muxed24 = 22'd0;
-reg           rhs_array_muxed25 = 1'd0;
-reg           rhs_array_muxed26 = 1'd0;
-reg    [21:0] rhs_array_muxed27 = 22'd0;
-reg           rhs_array_muxed28 = 1'd0;
-reg           rhs_array_muxed29 = 1'd0;
-reg    [21:0] rhs_array_muxed30 = 22'd0;
-reg           rhs_array_muxed31 = 1'd0;
-reg           rhs_array_muxed32 = 1'd0;
-reg    [21:0] rhs_array_muxed33 = 22'd0;
-reg           rhs_array_muxed34 = 1'd0;
-reg           rhs_array_muxed35 = 1'd0;
-reg     [2:0] array_muxed0 = 3'd0;
-reg    [14:0] array_muxed1 = 15'd0;
-reg           array_muxed2 = 1'd0;
-reg           array_muxed3 = 1'd0;
-reg           array_muxed4 = 1'd0;
-reg           array_muxed5 = 1'd0;
-reg           array_muxed6 = 1'd0;
-reg     [2:0] array_muxed7 = 3'd0;
-reg    [14:0] array_muxed8 = 15'd0;
-reg           array_muxed9 = 1'd0;
-reg           array_muxed10 = 1'd0;
-reg           array_muxed11 = 1'd0;
-reg           array_muxed12 = 1'd0;
-reg           array_muxed13 = 1'd0;
-reg     [2:0] array_muxed14 = 3'd0;
-reg    [14:0] array_muxed15 = 15'd0;
-reg           array_muxed16 = 1'd0;
-reg           array_muxed17 = 1'd0;
-reg           array_muxed18 = 1'd0;
-reg           array_muxed19 = 1'd0;
-reg           array_muxed20 = 1'd0;
-reg     [2:0] array_muxed21 = 3'd0;
-reg    [14:0] array_muxed22 = 15'd0;
-reg           array_muxed23 = 1'd0;
-reg           array_muxed24 = 1'd0;
-reg           array_muxed25 = 1'd0;
-reg           array_muxed26 = 1'd0;
-reg           array_muxed27 = 1'd0;
-wire          xilinxasyncresetsynchronizerimpl0;
-wire          xilinxasyncresetsynchronizerimpl0_rst_meta;
-wire          xilinxasyncresetsynchronizerimpl1;
-wire          xilinxasyncresetsynchronizerimpl1_rst_meta;
-wire          xilinxasyncresetsynchronizerimpl2;
-wire          xilinxasyncresetsynchronizerimpl2_rst_meta;
-wire          xilinxasyncresetsynchronizerimpl2_expr;
-wire          xilinxasyncresetsynchronizerimpl3;
-wire          xilinxasyncresetsynchronizerimpl3_rst_meta;
-wire          xilinxasyncresetsynchronizerimpl3_expr;
+reg           main_litedramcore_twtrcon_ready = 1'd0;
+wire          main_litedramcore_twtrcon_valid;
+wire          main_litedramcore_wants_refresh;
+wire          main_litedramcore_wants_zqcs;
+wire          main_litedramcore_write_available;
+reg           main_litedramcore_zqcs_executer_done = 1'd0;
+reg           main_litedramcore_zqcs_executer_start = 1'd0;
+reg     [4:0] main_litedramcore_zqcs_executer_trigger = 5'd0;
+wire   [26:0] main_litedramcore_zqcs_timer_count0;
+reg    [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999;
+wire          main_litedramcore_zqcs_timer_done0;
+wire          main_litedramcore_zqcs_timer_done1;
+wire          main_litedramcore_zqcs_timer_wait;
+wire          main_locked;
+reg           main_power_down = 1'd0;
+wire          main_reset;
+reg     [3:0] main_reset_counter = 4'd15;
+reg           main_rst = 1'd0;
+wire          main_user_enable;
+wire   [24:0] main_user_port_cmd_payload_addr;
+wire          main_user_port_cmd_payload_we;
+wire          main_user_port_cmd_ready;
+wire          main_user_port_cmd_valid;
+wire  [255:0] main_user_port_rdata_payload_data;
+wire          main_user_port_rdata_ready;
+wire          main_user_port_rdata_valid;
+wire  [255:0] main_user_port_wdata_payload_data;
+wire   [31:0] main_user_port_wdata_payload_we;
+wire          main_user_port_wdata_ready;
+wire          main_user_port_wdata_valid;
+wire          main_wb_bus_ack;
+wire   [29:0] main_wb_bus_adr;
+wire    [1:0] main_wb_bus_bte;
+wire    [2:0] main_wb_bus_cti;
+wire          main_wb_bus_cyc;
+wire   [31:0] main_wb_bus_dat_r;
+wire   [31:0] main_wb_bus_dat_w;
+wire          main_wb_bus_err;
+wire    [3:0] main_wb_bus_sel;
+wire          main_wb_bus_stb;
+wire          main_wb_bus_we;
+wire          sys4x_clk;
+wire          sys4x_dqs_clk;
+wire          sys_clk;
+wire          sys_rst;
 
 //------------------------------------------------------------------------------
 // Combinatorial Logic
 //------------------------------------------------------------------------------
 
-assign init_done = init_done_storage;
-assign init_error = init_error_storage;
-assign wb_bus_adr = wb_ctrl_adr;
-assign wb_bus_dat_w = wb_ctrl_dat_w;
-assign wb_ctrl_dat_r = wb_bus_dat_r;
-assign wb_bus_sel = wb_ctrl_sel;
-assign wb_bus_cyc = wb_ctrl_cyc;
-assign wb_bus_stb = wb_ctrl_stb;
-assign wb_ctrl_ack = wb_bus_ack;
-assign wb_bus_we = wb_ctrl_we;
-assign wb_bus_cti = wb_ctrl_cti;
-assign wb_bus_bte = wb_ctrl_bte;
-assign wb_ctrl_err = wb_bus_err;
+assign init_done = main_init_done_storage;
+assign init_error = main_init_error_storage;
+assign main_wb_bus_adr = wb_ctrl_adr;
+assign main_wb_bus_dat_w = wb_ctrl_dat_w;
+assign wb_ctrl_dat_r = main_wb_bus_dat_r;
+assign main_wb_bus_sel = wb_ctrl_sel;
+assign main_wb_bus_cyc = wb_ctrl_cyc;
+assign main_wb_bus_stb = wb_ctrl_stb;
+assign wb_ctrl_ack = main_wb_bus_ack;
+assign main_wb_bus_we = wb_ctrl_we;
+assign main_wb_bus_cti = wb_ctrl_cti;
+assign main_wb_bus_bte = wb_ctrl_bte;
+assign wb_ctrl_err = main_wb_bus_err;
 assign user_clk = sys_clk;
 assign user_rst = sys_rst;
-assign user_enable = 1'd1;
-assign user_port_cmd_valid = (user_port_native_0_cmd_valid & user_enable);
-assign user_port_native_0_cmd_ready = (user_port_cmd_ready & user_enable);
-assign user_port_cmd_payload_we = user_port_native_0_cmd_we;
-assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
-assign user_port_wdata_valid = (user_port_native_0_wdata_valid & user_enable);
-assign user_port_native_0_wdata_ready = (user_port_wdata_ready & user_enable);
-assign user_port_wdata_payload_we = user_port_native_0_wdata_we;
-assign user_port_wdata_payload_data = user_port_native_0_wdata_data;
-assign user_port_native_0_rdata_valid = (user_port_rdata_valid & user_enable);
-assign user_port_rdata_ready = (user_port_native_0_rdata_ready & user_enable);
-assign user_port_native_0_rdata_data = user_port_rdata_payload_data;
-assign reset = (rst | rst_1);
-assign pll_locked = locked;
-assign clkin = clk;
-assign iodelay_clk = clkout_buf0;
-assign sys_clk = clkout_buf1;
-assign sys4x_clk = clkout_buf2;
-assign sys4x_dqs_clk = clkout_buf3;
-assign ddram_ba = k7ddrphy_pads_ba;
-assign k7ddrphy_dqs_oe_delay_tappeddelayline = ((k7ddrphy_dqs_preamble | k7ddrphy_dqs_oe) | k7ddrphy_dqs_postamble);
-assign k7ddrphy_dq_oe_delay_tappeddelayline = ((k7ddrphy_dqs_preamble | k7ddrphy_dq_oe) | k7ddrphy_dqs_postamble);
-always @(*) begin
-    k7ddrphy_dfi_p0_rddata <= 64'd0;
-    k7ddrphy_dfi_p0_rddata[0] <= k7ddrphy_bitslip04[0];
-    k7ddrphy_dfi_p0_rddata[32] <= k7ddrphy_bitslip04[1];
-    k7ddrphy_dfi_p0_rddata[1] <= k7ddrphy_bitslip14[0];
-    k7ddrphy_dfi_p0_rddata[33] <= k7ddrphy_bitslip14[1];
-    k7ddrphy_dfi_p0_rddata[2] <= k7ddrphy_bitslip24[0];
-    k7ddrphy_dfi_p0_rddata[34] <= k7ddrphy_bitslip24[1];
-    k7ddrphy_dfi_p0_rddata[3] <= k7ddrphy_bitslip34[0];
-    k7ddrphy_dfi_p0_rddata[35] <= k7ddrphy_bitslip34[1];
-    k7ddrphy_dfi_p0_rddata[4] <= k7ddrphy_bitslip42[0];
-    k7ddrphy_dfi_p0_rddata[36] <= k7ddrphy_bitslip42[1];
-    k7ddrphy_dfi_p0_rddata[5] <= k7ddrphy_bitslip52[0];
-    k7ddrphy_dfi_p0_rddata[37] <= k7ddrphy_bitslip52[1];
-    k7ddrphy_dfi_p0_rddata[6] <= k7ddrphy_bitslip62[0];
-    k7ddrphy_dfi_p0_rddata[38] <= k7ddrphy_bitslip62[1];
-    k7ddrphy_dfi_p0_rddata[7] <= k7ddrphy_bitslip72[0];
-    k7ddrphy_dfi_p0_rddata[39] <= k7ddrphy_bitslip72[1];
-    k7ddrphy_dfi_p0_rddata[8] <= k7ddrphy_bitslip82[0];
-    k7ddrphy_dfi_p0_rddata[40] <= k7ddrphy_bitslip82[1];
-    k7ddrphy_dfi_p0_rddata[9] <= k7ddrphy_bitslip92[0];
-    k7ddrphy_dfi_p0_rddata[41] <= k7ddrphy_bitslip92[1];
-    k7ddrphy_dfi_p0_rddata[10] <= k7ddrphy_bitslip102[0];
-    k7ddrphy_dfi_p0_rddata[42] <= k7ddrphy_bitslip102[1];
-    k7ddrphy_dfi_p0_rddata[11] <= k7ddrphy_bitslip112[0];
-    k7ddrphy_dfi_p0_rddata[43] <= k7ddrphy_bitslip112[1];
-    k7ddrphy_dfi_p0_rddata[12] <= k7ddrphy_bitslip122[0];
-    k7ddrphy_dfi_p0_rddata[44] <= k7ddrphy_bitslip122[1];
-    k7ddrphy_dfi_p0_rddata[13] <= k7ddrphy_bitslip132[0];
-    k7ddrphy_dfi_p0_rddata[45] <= k7ddrphy_bitslip132[1];
-    k7ddrphy_dfi_p0_rddata[14] <= k7ddrphy_bitslip142[0];
-    k7ddrphy_dfi_p0_rddata[46] <= k7ddrphy_bitslip142[1];
-    k7ddrphy_dfi_p0_rddata[15] <= k7ddrphy_bitslip152[0];
-    k7ddrphy_dfi_p0_rddata[47] <= k7ddrphy_bitslip152[1];
-    k7ddrphy_dfi_p0_rddata[16] <= k7ddrphy_bitslip162[0];
-    k7ddrphy_dfi_p0_rddata[48] <= k7ddrphy_bitslip162[1];
-    k7ddrphy_dfi_p0_rddata[17] <= k7ddrphy_bitslip172[0];
-    k7ddrphy_dfi_p0_rddata[49] <= k7ddrphy_bitslip172[1];
-    k7ddrphy_dfi_p0_rddata[18] <= k7ddrphy_bitslip182[0];
-    k7ddrphy_dfi_p0_rddata[50] <= k7ddrphy_bitslip182[1];
-    k7ddrphy_dfi_p0_rddata[19] <= k7ddrphy_bitslip192[0];
-    k7ddrphy_dfi_p0_rddata[51] <= k7ddrphy_bitslip192[1];
-    k7ddrphy_dfi_p0_rddata[20] <= k7ddrphy_bitslip202[0];
-    k7ddrphy_dfi_p0_rddata[52] <= k7ddrphy_bitslip202[1];
-    k7ddrphy_dfi_p0_rddata[21] <= k7ddrphy_bitslip212[0];
-    k7ddrphy_dfi_p0_rddata[53] <= k7ddrphy_bitslip212[1];
-    k7ddrphy_dfi_p0_rddata[22] <= k7ddrphy_bitslip222[0];
-    k7ddrphy_dfi_p0_rddata[54] <= k7ddrphy_bitslip222[1];
-    k7ddrphy_dfi_p0_rddata[23] <= k7ddrphy_bitslip232[0];
-    k7ddrphy_dfi_p0_rddata[55] <= k7ddrphy_bitslip232[1];
-    k7ddrphy_dfi_p0_rddata[24] <= k7ddrphy_bitslip242[0];
-    k7ddrphy_dfi_p0_rddata[56] <= k7ddrphy_bitslip242[1];
-    k7ddrphy_dfi_p0_rddata[25] <= k7ddrphy_bitslip252[0];
-    k7ddrphy_dfi_p0_rddata[57] <= k7ddrphy_bitslip252[1];
-    k7ddrphy_dfi_p0_rddata[26] <= k7ddrphy_bitslip262[0];
-    k7ddrphy_dfi_p0_rddata[58] <= k7ddrphy_bitslip262[1];
-    k7ddrphy_dfi_p0_rddata[27] <= k7ddrphy_bitslip272[0];
-    k7ddrphy_dfi_p0_rddata[59] <= k7ddrphy_bitslip272[1];
-    k7ddrphy_dfi_p0_rddata[28] <= k7ddrphy_bitslip282[0];
-    k7ddrphy_dfi_p0_rddata[60] <= k7ddrphy_bitslip282[1];
-    k7ddrphy_dfi_p0_rddata[29] <= k7ddrphy_bitslip292[0];
-    k7ddrphy_dfi_p0_rddata[61] <= k7ddrphy_bitslip292[1];
-    k7ddrphy_dfi_p0_rddata[30] <= k7ddrphy_bitslip302[0];
-    k7ddrphy_dfi_p0_rddata[62] <= k7ddrphy_bitslip302[1];
-    k7ddrphy_dfi_p0_rddata[31] <= k7ddrphy_bitslip312[0];
-    k7ddrphy_dfi_p0_rddata[63] <= k7ddrphy_bitslip312[1];
-end
-always @(*) begin
-    k7ddrphy_dfi_p1_rddata <= 64'd0;
-    k7ddrphy_dfi_p1_rddata[0] <= k7ddrphy_bitslip04[2];
-    k7ddrphy_dfi_p1_rddata[32] <= k7ddrphy_bitslip04[3];
-    k7ddrphy_dfi_p1_rddata[1] <= k7ddrphy_bitslip14[2];
-    k7ddrphy_dfi_p1_rddata[33] <= k7ddrphy_bitslip14[3];
-    k7ddrphy_dfi_p1_rddata[2] <= k7ddrphy_bitslip24[2];
-    k7ddrphy_dfi_p1_rddata[34] <= k7ddrphy_bitslip24[3];
-    k7ddrphy_dfi_p1_rddata[3] <= k7ddrphy_bitslip34[2];
-    k7ddrphy_dfi_p1_rddata[35] <= k7ddrphy_bitslip34[3];
-    k7ddrphy_dfi_p1_rddata[4] <= k7ddrphy_bitslip42[2];
-    k7ddrphy_dfi_p1_rddata[36] <= k7ddrphy_bitslip42[3];
-    k7ddrphy_dfi_p1_rddata[5] <= k7ddrphy_bitslip52[2];
-    k7ddrphy_dfi_p1_rddata[37] <= k7ddrphy_bitslip52[3];
-    k7ddrphy_dfi_p1_rddata[6] <= k7ddrphy_bitslip62[2];
-    k7ddrphy_dfi_p1_rddata[38] <= k7ddrphy_bitslip62[3];
-    k7ddrphy_dfi_p1_rddata[7] <= k7ddrphy_bitslip72[2];
-    k7ddrphy_dfi_p1_rddata[39] <= k7ddrphy_bitslip72[3];
-    k7ddrphy_dfi_p1_rddata[8] <= k7ddrphy_bitslip82[2];
-    k7ddrphy_dfi_p1_rddata[40] <= k7ddrphy_bitslip82[3];
-    k7ddrphy_dfi_p1_rddata[9] <= k7ddrphy_bitslip92[2];
-    k7ddrphy_dfi_p1_rddata[41] <= k7ddrphy_bitslip92[3];
-    k7ddrphy_dfi_p1_rddata[10] <= k7ddrphy_bitslip102[2];
-    k7ddrphy_dfi_p1_rddata[42] <= k7ddrphy_bitslip102[3];
-    k7ddrphy_dfi_p1_rddata[11] <= k7ddrphy_bitslip112[2];
-    k7ddrphy_dfi_p1_rddata[43] <= k7ddrphy_bitslip112[3];
-    k7ddrphy_dfi_p1_rddata[12] <= k7ddrphy_bitslip122[2];
-    k7ddrphy_dfi_p1_rddata[44] <= k7ddrphy_bitslip122[3];
-    k7ddrphy_dfi_p1_rddata[13] <= k7ddrphy_bitslip132[2];
-    k7ddrphy_dfi_p1_rddata[45] <= k7ddrphy_bitslip132[3];
-    k7ddrphy_dfi_p1_rddata[14] <= k7ddrphy_bitslip142[2];
-    k7ddrphy_dfi_p1_rddata[46] <= k7ddrphy_bitslip142[3];
-    k7ddrphy_dfi_p1_rddata[15] <= k7ddrphy_bitslip152[2];
-    k7ddrphy_dfi_p1_rddata[47] <= k7ddrphy_bitslip152[3];
-    k7ddrphy_dfi_p1_rddata[16] <= k7ddrphy_bitslip162[2];
-    k7ddrphy_dfi_p1_rddata[48] <= k7ddrphy_bitslip162[3];
-    k7ddrphy_dfi_p1_rddata[17] <= k7ddrphy_bitslip172[2];
-    k7ddrphy_dfi_p1_rddata[49] <= k7ddrphy_bitslip172[3];
-    k7ddrphy_dfi_p1_rddata[18] <= k7ddrphy_bitslip182[2];
-    k7ddrphy_dfi_p1_rddata[50] <= k7ddrphy_bitslip182[3];
-    k7ddrphy_dfi_p1_rddata[19] <= k7ddrphy_bitslip192[2];
-    k7ddrphy_dfi_p1_rddata[51] <= k7ddrphy_bitslip192[3];
-    k7ddrphy_dfi_p1_rddata[20] <= k7ddrphy_bitslip202[2];
-    k7ddrphy_dfi_p1_rddata[52] <= k7ddrphy_bitslip202[3];
-    k7ddrphy_dfi_p1_rddata[21] <= k7ddrphy_bitslip212[2];
-    k7ddrphy_dfi_p1_rddata[53] <= k7ddrphy_bitslip212[3];
-    k7ddrphy_dfi_p1_rddata[22] <= k7ddrphy_bitslip222[2];
-    k7ddrphy_dfi_p1_rddata[54] <= k7ddrphy_bitslip222[3];
-    k7ddrphy_dfi_p1_rddata[23] <= k7ddrphy_bitslip232[2];
-    k7ddrphy_dfi_p1_rddata[55] <= k7ddrphy_bitslip232[3];
-    k7ddrphy_dfi_p1_rddata[24] <= k7ddrphy_bitslip242[2];
-    k7ddrphy_dfi_p1_rddata[56] <= k7ddrphy_bitslip242[3];
-    k7ddrphy_dfi_p1_rddata[25] <= k7ddrphy_bitslip252[2];
-    k7ddrphy_dfi_p1_rddata[57] <= k7ddrphy_bitslip252[3];
-    k7ddrphy_dfi_p1_rddata[26] <= k7ddrphy_bitslip262[2];
-    k7ddrphy_dfi_p1_rddata[58] <= k7ddrphy_bitslip262[3];
-    k7ddrphy_dfi_p1_rddata[27] <= k7ddrphy_bitslip272[2];
-    k7ddrphy_dfi_p1_rddata[59] <= k7ddrphy_bitslip272[3];
-    k7ddrphy_dfi_p1_rddata[28] <= k7ddrphy_bitslip282[2];
-    k7ddrphy_dfi_p1_rddata[60] <= k7ddrphy_bitslip282[3];
-    k7ddrphy_dfi_p1_rddata[29] <= k7ddrphy_bitslip292[2];
-    k7ddrphy_dfi_p1_rddata[61] <= k7ddrphy_bitslip292[3];
-    k7ddrphy_dfi_p1_rddata[30] <= k7ddrphy_bitslip302[2];
-    k7ddrphy_dfi_p1_rddata[62] <= k7ddrphy_bitslip302[3];
-    k7ddrphy_dfi_p1_rddata[31] <= k7ddrphy_bitslip312[2];
-    k7ddrphy_dfi_p1_rddata[63] <= k7ddrphy_bitslip312[3];
-end
-always @(*) begin
-    k7ddrphy_dfi_p2_rddata <= 64'd0;
-    k7ddrphy_dfi_p2_rddata[0] <= k7ddrphy_bitslip04[4];
-    k7ddrphy_dfi_p2_rddata[32] <= k7ddrphy_bitslip04[5];
-    k7ddrphy_dfi_p2_rddata[1] <= k7ddrphy_bitslip14[4];
-    k7ddrphy_dfi_p2_rddata[33] <= k7ddrphy_bitslip14[5];
-    k7ddrphy_dfi_p2_rddata[2] <= k7ddrphy_bitslip24[4];
-    k7ddrphy_dfi_p2_rddata[34] <= k7ddrphy_bitslip24[5];
-    k7ddrphy_dfi_p2_rddata[3] <= k7ddrphy_bitslip34[4];
-    k7ddrphy_dfi_p2_rddata[35] <= k7ddrphy_bitslip34[5];
-    k7ddrphy_dfi_p2_rddata[4] <= k7ddrphy_bitslip42[4];
-    k7ddrphy_dfi_p2_rddata[36] <= k7ddrphy_bitslip42[5];
-    k7ddrphy_dfi_p2_rddata[5] <= k7ddrphy_bitslip52[4];
-    k7ddrphy_dfi_p2_rddata[37] <= k7ddrphy_bitslip52[5];
-    k7ddrphy_dfi_p2_rddata[6] <= k7ddrphy_bitslip62[4];
-    k7ddrphy_dfi_p2_rddata[38] <= k7ddrphy_bitslip62[5];
-    k7ddrphy_dfi_p2_rddata[7] <= k7ddrphy_bitslip72[4];
-    k7ddrphy_dfi_p2_rddata[39] <= k7ddrphy_bitslip72[5];
-    k7ddrphy_dfi_p2_rddata[8] <= k7ddrphy_bitslip82[4];
-    k7ddrphy_dfi_p2_rddata[40] <= k7ddrphy_bitslip82[5];
-    k7ddrphy_dfi_p2_rddata[9] <= k7ddrphy_bitslip92[4];
-    k7ddrphy_dfi_p2_rddata[41] <= k7ddrphy_bitslip92[5];
-    k7ddrphy_dfi_p2_rddata[10] <= k7ddrphy_bitslip102[4];
-    k7ddrphy_dfi_p2_rddata[42] <= k7ddrphy_bitslip102[5];
-    k7ddrphy_dfi_p2_rddata[11] <= k7ddrphy_bitslip112[4];
-    k7ddrphy_dfi_p2_rddata[43] <= k7ddrphy_bitslip112[5];
-    k7ddrphy_dfi_p2_rddata[12] <= k7ddrphy_bitslip122[4];
-    k7ddrphy_dfi_p2_rddata[44] <= k7ddrphy_bitslip122[5];
-    k7ddrphy_dfi_p2_rddata[13] <= k7ddrphy_bitslip132[4];
-    k7ddrphy_dfi_p2_rddata[45] <= k7ddrphy_bitslip132[5];
-    k7ddrphy_dfi_p2_rddata[14] <= k7ddrphy_bitslip142[4];
-    k7ddrphy_dfi_p2_rddata[46] <= k7ddrphy_bitslip142[5];
-    k7ddrphy_dfi_p2_rddata[15] <= k7ddrphy_bitslip152[4];
-    k7ddrphy_dfi_p2_rddata[47] <= k7ddrphy_bitslip152[5];
-    k7ddrphy_dfi_p2_rddata[16] <= k7ddrphy_bitslip162[4];
-    k7ddrphy_dfi_p2_rddata[48] <= k7ddrphy_bitslip162[5];
-    k7ddrphy_dfi_p2_rddata[17] <= k7ddrphy_bitslip172[4];
-    k7ddrphy_dfi_p2_rddata[49] <= k7ddrphy_bitslip172[5];
-    k7ddrphy_dfi_p2_rddata[18] <= k7ddrphy_bitslip182[4];
-    k7ddrphy_dfi_p2_rddata[50] <= k7ddrphy_bitslip182[5];
-    k7ddrphy_dfi_p2_rddata[19] <= k7ddrphy_bitslip192[4];
-    k7ddrphy_dfi_p2_rddata[51] <= k7ddrphy_bitslip192[5];
-    k7ddrphy_dfi_p2_rddata[20] <= k7ddrphy_bitslip202[4];
-    k7ddrphy_dfi_p2_rddata[52] <= k7ddrphy_bitslip202[5];
-    k7ddrphy_dfi_p2_rddata[21] <= k7ddrphy_bitslip212[4];
-    k7ddrphy_dfi_p2_rddata[53] <= k7ddrphy_bitslip212[5];
-    k7ddrphy_dfi_p2_rddata[22] <= k7ddrphy_bitslip222[4];
-    k7ddrphy_dfi_p2_rddata[54] <= k7ddrphy_bitslip222[5];
-    k7ddrphy_dfi_p2_rddata[23] <= k7ddrphy_bitslip232[4];
-    k7ddrphy_dfi_p2_rddata[55] <= k7ddrphy_bitslip232[5];
-    k7ddrphy_dfi_p2_rddata[24] <= k7ddrphy_bitslip242[4];
-    k7ddrphy_dfi_p2_rddata[56] <= k7ddrphy_bitslip242[5];
-    k7ddrphy_dfi_p2_rddata[25] <= k7ddrphy_bitslip252[4];
-    k7ddrphy_dfi_p2_rddata[57] <= k7ddrphy_bitslip252[5];
-    k7ddrphy_dfi_p2_rddata[26] <= k7ddrphy_bitslip262[4];
-    k7ddrphy_dfi_p2_rddata[58] <= k7ddrphy_bitslip262[5];
-    k7ddrphy_dfi_p2_rddata[27] <= k7ddrphy_bitslip272[4];
-    k7ddrphy_dfi_p2_rddata[59] <= k7ddrphy_bitslip272[5];
-    k7ddrphy_dfi_p2_rddata[28] <= k7ddrphy_bitslip282[4];
-    k7ddrphy_dfi_p2_rddata[60] <= k7ddrphy_bitslip282[5];
-    k7ddrphy_dfi_p2_rddata[29] <= k7ddrphy_bitslip292[4];
-    k7ddrphy_dfi_p2_rddata[61] <= k7ddrphy_bitslip292[5];
-    k7ddrphy_dfi_p2_rddata[30] <= k7ddrphy_bitslip302[4];
-    k7ddrphy_dfi_p2_rddata[62] <= k7ddrphy_bitslip302[5];
-    k7ddrphy_dfi_p2_rddata[31] <= k7ddrphy_bitslip312[4];
-    k7ddrphy_dfi_p2_rddata[63] <= k7ddrphy_bitslip312[5];
-end
-always @(*) begin
-    k7ddrphy_dfi_p3_rddata <= 64'd0;
-    k7ddrphy_dfi_p3_rddata[0] <= k7ddrphy_bitslip04[6];
-    k7ddrphy_dfi_p3_rddata[32] <= k7ddrphy_bitslip04[7];
-    k7ddrphy_dfi_p3_rddata[1] <= k7ddrphy_bitslip14[6];
-    k7ddrphy_dfi_p3_rddata[33] <= k7ddrphy_bitslip14[7];
-    k7ddrphy_dfi_p3_rddata[2] <= k7ddrphy_bitslip24[6];
-    k7ddrphy_dfi_p3_rddata[34] <= k7ddrphy_bitslip24[7];
-    k7ddrphy_dfi_p3_rddata[3] <= k7ddrphy_bitslip34[6];
-    k7ddrphy_dfi_p3_rddata[35] <= k7ddrphy_bitslip34[7];
-    k7ddrphy_dfi_p3_rddata[4] <= k7ddrphy_bitslip42[6];
-    k7ddrphy_dfi_p3_rddata[36] <= k7ddrphy_bitslip42[7];
-    k7ddrphy_dfi_p3_rddata[5] <= k7ddrphy_bitslip52[6];
-    k7ddrphy_dfi_p3_rddata[37] <= k7ddrphy_bitslip52[7];
-    k7ddrphy_dfi_p3_rddata[6] <= k7ddrphy_bitslip62[6];
-    k7ddrphy_dfi_p3_rddata[38] <= k7ddrphy_bitslip62[7];
-    k7ddrphy_dfi_p3_rddata[7] <= k7ddrphy_bitslip72[6];
-    k7ddrphy_dfi_p3_rddata[39] <= k7ddrphy_bitslip72[7];
-    k7ddrphy_dfi_p3_rddata[8] <= k7ddrphy_bitslip82[6];
-    k7ddrphy_dfi_p3_rddata[40] <= k7ddrphy_bitslip82[7];
-    k7ddrphy_dfi_p3_rddata[9] <= k7ddrphy_bitslip92[6];
-    k7ddrphy_dfi_p3_rddata[41] <= k7ddrphy_bitslip92[7];
-    k7ddrphy_dfi_p3_rddata[10] <= k7ddrphy_bitslip102[6];
-    k7ddrphy_dfi_p3_rddata[42] <= k7ddrphy_bitslip102[7];
-    k7ddrphy_dfi_p3_rddata[11] <= k7ddrphy_bitslip112[6];
-    k7ddrphy_dfi_p3_rddata[43] <= k7ddrphy_bitslip112[7];
-    k7ddrphy_dfi_p3_rddata[12] <= k7ddrphy_bitslip122[6];
-    k7ddrphy_dfi_p3_rddata[44] <= k7ddrphy_bitslip122[7];
-    k7ddrphy_dfi_p3_rddata[13] <= k7ddrphy_bitslip132[6];
-    k7ddrphy_dfi_p3_rddata[45] <= k7ddrphy_bitslip132[7];
-    k7ddrphy_dfi_p3_rddata[14] <= k7ddrphy_bitslip142[6];
-    k7ddrphy_dfi_p3_rddata[46] <= k7ddrphy_bitslip142[7];
-    k7ddrphy_dfi_p3_rddata[15] <= k7ddrphy_bitslip152[6];
-    k7ddrphy_dfi_p3_rddata[47] <= k7ddrphy_bitslip152[7];
-    k7ddrphy_dfi_p3_rddata[16] <= k7ddrphy_bitslip162[6];
-    k7ddrphy_dfi_p3_rddata[48] <= k7ddrphy_bitslip162[7];
-    k7ddrphy_dfi_p3_rddata[17] <= k7ddrphy_bitslip172[6];
-    k7ddrphy_dfi_p3_rddata[49] <= k7ddrphy_bitslip172[7];
-    k7ddrphy_dfi_p3_rddata[18] <= k7ddrphy_bitslip182[6];
-    k7ddrphy_dfi_p3_rddata[50] <= k7ddrphy_bitslip182[7];
-    k7ddrphy_dfi_p3_rddata[19] <= k7ddrphy_bitslip192[6];
-    k7ddrphy_dfi_p3_rddata[51] <= k7ddrphy_bitslip192[7];
-    k7ddrphy_dfi_p3_rddata[20] <= k7ddrphy_bitslip202[6];
-    k7ddrphy_dfi_p3_rddata[52] <= k7ddrphy_bitslip202[7];
-    k7ddrphy_dfi_p3_rddata[21] <= k7ddrphy_bitslip212[6];
-    k7ddrphy_dfi_p3_rddata[53] <= k7ddrphy_bitslip212[7];
-    k7ddrphy_dfi_p3_rddata[22] <= k7ddrphy_bitslip222[6];
-    k7ddrphy_dfi_p3_rddata[54] <= k7ddrphy_bitslip222[7];
-    k7ddrphy_dfi_p3_rddata[23] <= k7ddrphy_bitslip232[6];
-    k7ddrphy_dfi_p3_rddata[55] <= k7ddrphy_bitslip232[7];
-    k7ddrphy_dfi_p3_rddata[24] <= k7ddrphy_bitslip242[6];
-    k7ddrphy_dfi_p3_rddata[56] <= k7ddrphy_bitslip242[7];
-    k7ddrphy_dfi_p3_rddata[25] <= k7ddrphy_bitslip252[6];
-    k7ddrphy_dfi_p3_rddata[57] <= k7ddrphy_bitslip252[7];
-    k7ddrphy_dfi_p3_rddata[26] <= k7ddrphy_bitslip262[6];
-    k7ddrphy_dfi_p3_rddata[58] <= k7ddrphy_bitslip262[7];
-    k7ddrphy_dfi_p3_rddata[27] <= k7ddrphy_bitslip272[6];
-    k7ddrphy_dfi_p3_rddata[59] <= k7ddrphy_bitslip272[7];
-    k7ddrphy_dfi_p3_rddata[28] <= k7ddrphy_bitslip282[6];
-    k7ddrphy_dfi_p3_rddata[60] <= k7ddrphy_bitslip282[7];
-    k7ddrphy_dfi_p3_rddata[29] <= k7ddrphy_bitslip292[6];
-    k7ddrphy_dfi_p3_rddata[61] <= k7ddrphy_bitslip292[7];
-    k7ddrphy_dfi_p3_rddata[30] <= k7ddrphy_bitslip302[6];
-    k7ddrphy_dfi_p3_rddata[62] <= k7ddrphy_bitslip302[7];
-    k7ddrphy_dfi_p3_rddata[31] <= k7ddrphy_bitslip312[6];
-    k7ddrphy_dfi_p3_rddata[63] <= k7ddrphy_bitslip312[7];
-end
-assign k7ddrphy_dfi_p0_rddata_valid = (k7ddrphy_rddata_en_tappeddelayline7 | k7ddrphy_wlevel_en_storage);
-assign k7ddrphy_dfi_p1_rddata_valid = (k7ddrphy_rddata_en_tappeddelayline7 | k7ddrphy_wlevel_en_storage);
-assign k7ddrphy_dfi_p2_rddata_valid = (k7ddrphy_rddata_en_tappeddelayline7 | k7ddrphy_wlevel_en_storage);
-assign k7ddrphy_dfi_p3_rddata_valid = (k7ddrphy_rddata_en_tappeddelayline7 | k7ddrphy_wlevel_en_storage);
-assign k7ddrphy_dq_oe = k7ddrphy_wrdata_en_tappeddelayline1;
-always @(*) begin
-    k7ddrphy_dqs_oe <= 1'd0;
-    if (k7ddrphy_wlevel_en_storage) begin
-        k7ddrphy_dqs_oe <= 1'd1;
+assign main_user_enable = 1'd1;
+assign main_user_port_cmd_valid = (user_port_native_0_cmd_valid & main_user_enable);
+assign user_port_native_0_cmd_ready = (main_user_port_cmd_ready & main_user_enable);
+assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we;
+assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
+assign main_user_port_wdata_valid = (user_port_native_0_wdata_valid & main_user_enable);
+assign user_port_native_0_wdata_ready = (main_user_port_wdata_ready & main_user_enable);
+assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we;
+assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data;
+assign user_port_native_0_rdata_valid = (main_user_port_rdata_valid & main_user_enable);
+assign main_user_port_rdata_ready = (user_port_native_0_rdata_ready & main_user_enable);
+assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data;
+assign builder_interface0_adr = main_wb_bus_adr;
+assign builder_interface0_dat_w = main_wb_bus_dat_w;
+assign main_wb_bus_dat_r = builder_interface0_dat_r;
+assign builder_interface0_sel = main_wb_bus_sel;
+assign builder_interface0_cyc = main_wb_bus_cyc;
+assign builder_interface0_stb = main_wb_bus_stb;
+assign main_wb_bus_ack = builder_interface0_ack;
+assign builder_interface0_we = main_wb_bus_we;
+assign builder_interface0_cti = main_wb_bus_cti;
+assign builder_interface0_bte = main_wb_bus_bte;
+assign main_wb_bus_err = builder_interface0_err;
+assign main_reset = (rst | main_rst);
+assign pll_locked = main_locked;
+assign main_clkin = clk;
+assign iodelay_clk = main_clkout_buf0;
+assign sys_clk = main_clkout_buf1;
+assign sys4x_clk = main_clkout_buf2;
+assign sys4x_dqs_clk = main_clkout_buf3;
+assign ddram_ba = main_k7ddrphy_pads_ba;
+assign main_k7ddrphy_dqs_oe_delay_tappeddelayline = ((main_k7ddrphy_dqs_preamble | main_k7ddrphy_dqs_oe) | main_k7ddrphy_dqs_postamble);
+assign main_k7ddrphy_dq_oe_delay_tappeddelayline = ((main_k7ddrphy_dqs_preamble | main_k7ddrphy_dq_oe) | main_k7ddrphy_dqs_postamble);
+always @(*) begin
+    main_k7ddrphy_dfi_p0_rddata <= 64'd0;
+    main_k7ddrphy_dfi_p0_rddata[0] <= main_k7ddrphy_bitslip04[0];
+    main_k7ddrphy_dfi_p0_rddata[32] <= main_k7ddrphy_bitslip04[1];
+    main_k7ddrphy_dfi_p0_rddata[1] <= main_k7ddrphy_bitslip14[0];
+    main_k7ddrphy_dfi_p0_rddata[33] <= main_k7ddrphy_bitslip14[1];
+    main_k7ddrphy_dfi_p0_rddata[2] <= main_k7ddrphy_bitslip24[0];
+    main_k7ddrphy_dfi_p0_rddata[34] <= main_k7ddrphy_bitslip24[1];
+    main_k7ddrphy_dfi_p0_rddata[3] <= main_k7ddrphy_bitslip34[0];
+    main_k7ddrphy_dfi_p0_rddata[35] <= main_k7ddrphy_bitslip34[1];
+    main_k7ddrphy_dfi_p0_rddata[4] <= main_k7ddrphy_bitslip42[0];
+    main_k7ddrphy_dfi_p0_rddata[36] <= main_k7ddrphy_bitslip42[1];
+    main_k7ddrphy_dfi_p0_rddata[5] <= main_k7ddrphy_bitslip52[0];
+    main_k7ddrphy_dfi_p0_rddata[37] <= main_k7ddrphy_bitslip52[1];
+    main_k7ddrphy_dfi_p0_rddata[6] <= main_k7ddrphy_bitslip62[0];
+    main_k7ddrphy_dfi_p0_rddata[38] <= main_k7ddrphy_bitslip62[1];
+    main_k7ddrphy_dfi_p0_rddata[7] <= main_k7ddrphy_bitslip72[0];
+    main_k7ddrphy_dfi_p0_rddata[39] <= main_k7ddrphy_bitslip72[1];
+    main_k7ddrphy_dfi_p0_rddata[8] <= main_k7ddrphy_bitslip82[0];
+    main_k7ddrphy_dfi_p0_rddata[40] <= main_k7ddrphy_bitslip82[1];
+    main_k7ddrphy_dfi_p0_rddata[9] <= main_k7ddrphy_bitslip92[0];
+    main_k7ddrphy_dfi_p0_rddata[41] <= main_k7ddrphy_bitslip92[1];
+    main_k7ddrphy_dfi_p0_rddata[10] <= main_k7ddrphy_bitslip102[0];
+    main_k7ddrphy_dfi_p0_rddata[42] <= main_k7ddrphy_bitslip102[1];
+    main_k7ddrphy_dfi_p0_rddata[11] <= main_k7ddrphy_bitslip112[0];
+    main_k7ddrphy_dfi_p0_rddata[43] <= main_k7ddrphy_bitslip112[1];
+    main_k7ddrphy_dfi_p0_rddata[12] <= main_k7ddrphy_bitslip122[0];
+    main_k7ddrphy_dfi_p0_rddata[44] <= main_k7ddrphy_bitslip122[1];
+    main_k7ddrphy_dfi_p0_rddata[13] <= main_k7ddrphy_bitslip132[0];
+    main_k7ddrphy_dfi_p0_rddata[45] <= main_k7ddrphy_bitslip132[1];
+    main_k7ddrphy_dfi_p0_rddata[14] <= main_k7ddrphy_bitslip142[0];
+    main_k7ddrphy_dfi_p0_rddata[46] <= main_k7ddrphy_bitslip142[1];
+    main_k7ddrphy_dfi_p0_rddata[15] <= main_k7ddrphy_bitslip152[0];
+    main_k7ddrphy_dfi_p0_rddata[47] <= main_k7ddrphy_bitslip152[1];
+    main_k7ddrphy_dfi_p0_rddata[16] <= main_k7ddrphy_bitslip162[0];
+    main_k7ddrphy_dfi_p0_rddata[48] <= main_k7ddrphy_bitslip162[1];
+    main_k7ddrphy_dfi_p0_rddata[17] <= main_k7ddrphy_bitslip172[0];
+    main_k7ddrphy_dfi_p0_rddata[49] <= main_k7ddrphy_bitslip172[1];
+    main_k7ddrphy_dfi_p0_rddata[18] <= main_k7ddrphy_bitslip182[0];
+    main_k7ddrphy_dfi_p0_rddata[50] <= main_k7ddrphy_bitslip182[1];
+    main_k7ddrphy_dfi_p0_rddata[19] <= main_k7ddrphy_bitslip192[0];
+    main_k7ddrphy_dfi_p0_rddata[51] <= main_k7ddrphy_bitslip192[1];
+    main_k7ddrphy_dfi_p0_rddata[20] <= main_k7ddrphy_bitslip202[0];
+    main_k7ddrphy_dfi_p0_rddata[52] <= main_k7ddrphy_bitslip202[1];
+    main_k7ddrphy_dfi_p0_rddata[21] <= main_k7ddrphy_bitslip212[0];
+    main_k7ddrphy_dfi_p0_rddata[53] <= main_k7ddrphy_bitslip212[1];
+    main_k7ddrphy_dfi_p0_rddata[22] <= main_k7ddrphy_bitslip222[0];
+    main_k7ddrphy_dfi_p0_rddata[54] <= main_k7ddrphy_bitslip222[1];
+    main_k7ddrphy_dfi_p0_rddata[23] <= main_k7ddrphy_bitslip232[0];
+    main_k7ddrphy_dfi_p0_rddata[55] <= main_k7ddrphy_bitslip232[1];
+    main_k7ddrphy_dfi_p0_rddata[24] <= main_k7ddrphy_bitslip242[0];
+    main_k7ddrphy_dfi_p0_rddata[56] <= main_k7ddrphy_bitslip242[1];
+    main_k7ddrphy_dfi_p0_rddata[25] <= main_k7ddrphy_bitslip252[0];
+    main_k7ddrphy_dfi_p0_rddata[57] <= main_k7ddrphy_bitslip252[1];
+    main_k7ddrphy_dfi_p0_rddata[26] <= main_k7ddrphy_bitslip262[0];
+    main_k7ddrphy_dfi_p0_rddata[58] <= main_k7ddrphy_bitslip262[1];
+    main_k7ddrphy_dfi_p0_rddata[27] <= main_k7ddrphy_bitslip272[0];
+    main_k7ddrphy_dfi_p0_rddata[59] <= main_k7ddrphy_bitslip272[1];
+    main_k7ddrphy_dfi_p0_rddata[28] <= main_k7ddrphy_bitslip282[0];
+    main_k7ddrphy_dfi_p0_rddata[60] <= main_k7ddrphy_bitslip282[1];
+    main_k7ddrphy_dfi_p0_rddata[29] <= main_k7ddrphy_bitslip292[0];
+    main_k7ddrphy_dfi_p0_rddata[61] <= main_k7ddrphy_bitslip292[1];
+    main_k7ddrphy_dfi_p0_rddata[30] <= main_k7ddrphy_bitslip302[0];
+    main_k7ddrphy_dfi_p0_rddata[62] <= main_k7ddrphy_bitslip302[1];
+    main_k7ddrphy_dfi_p0_rddata[31] <= main_k7ddrphy_bitslip312[0];
+    main_k7ddrphy_dfi_p0_rddata[63] <= main_k7ddrphy_bitslip312[1];
+end
+always @(*) begin
+    main_k7ddrphy_dfi_p1_rddata <= 64'd0;
+    main_k7ddrphy_dfi_p1_rddata[0] <= main_k7ddrphy_bitslip04[2];
+    main_k7ddrphy_dfi_p1_rddata[32] <= main_k7ddrphy_bitslip04[3];
+    main_k7ddrphy_dfi_p1_rddata[1] <= main_k7ddrphy_bitslip14[2];
+    main_k7ddrphy_dfi_p1_rddata[33] <= main_k7ddrphy_bitslip14[3];
+    main_k7ddrphy_dfi_p1_rddata[2] <= main_k7ddrphy_bitslip24[2];
+    main_k7ddrphy_dfi_p1_rddata[34] <= main_k7ddrphy_bitslip24[3];
+    main_k7ddrphy_dfi_p1_rddata[3] <= main_k7ddrphy_bitslip34[2];
+    main_k7ddrphy_dfi_p1_rddata[35] <= main_k7ddrphy_bitslip34[3];
+    main_k7ddrphy_dfi_p1_rddata[4] <= main_k7ddrphy_bitslip42[2];
+    main_k7ddrphy_dfi_p1_rddata[36] <= main_k7ddrphy_bitslip42[3];
+    main_k7ddrphy_dfi_p1_rddata[5] <= main_k7ddrphy_bitslip52[2];
+    main_k7ddrphy_dfi_p1_rddata[37] <= main_k7ddrphy_bitslip52[3];
+    main_k7ddrphy_dfi_p1_rddata[6] <= main_k7ddrphy_bitslip62[2];
+    main_k7ddrphy_dfi_p1_rddata[38] <= main_k7ddrphy_bitslip62[3];
+    main_k7ddrphy_dfi_p1_rddata[7] <= main_k7ddrphy_bitslip72[2];
+    main_k7ddrphy_dfi_p1_rddata[39] <= main_k7ddrphy_bitslip72[3];
+    main_k7ddrphy_dfi_p1_rddata[8] <= main_k7ddrphy_bitslip82[2];
+    main_k7ddrphy_dfi_p1_rddata[40] <= main_k7ddrphy_bitslip82[3];
+    main_k7ddrphy_dfi_p1_rddata[9] <= main_k7ddrphy_bitslip92[2];
+    main_k7ddrphy_dfi_p1_rddata[41] <= main_k7ddrphy_bitslip92[3];
+    main_k7ddrphy_dfi_p1_rddata[10] <= main_k7ddrphy_bitslip102[2];
+    main_k7ddrphy_dfi_p1_rddata[42] <= main_k7ddrphy_bitslip102[3];
+    main_k7ddrphy_dfi_p1_rddata[11] <= main_k7ddrphy_bitslip112[2];
+    main_k7ddrphy_dfi_p1_rddata[43] <= main_k7ddrphy_bitslip112[3];
+    main_k7ddrphy_dfi_p1_rddata[12] <= main_k7ddrphy_bitslip122[2];
+    main_k7ddrphy_dfi_p1_rddata[44] <= main_k7ddrphy_bitslip122[3];
+    main_k7ddrphy_dfi_p1_rddata[13] <= main_k7ddrphy_bitslip132[2];
+    main_k7ddrphy_dfi_p1_rddata[45] <= main_k7ddrphy_bitslip132[3];
+    main_k7ddrphy_dfi_p1_rddata[14] <= main_k7ddrphy_bitslip142[2];
+    main_k7ddrphy_dfi_p1_rddata[46] <= main_k7ddrphy_bitslip142[3];
+    main_k7ddrphy_dfi_p1_rddata[15] <= main_k7ddrphy_bitslip152[2];
+    main_k7ddrphy_dfi_p1_rddata[47] <= main_k7ddrphy_bitslip152[3];
+    main_k7ddrphy_dfi_p1_rddata[16] <= main_k7ddrphy_bitslip162[2];
+    main_k7ddrphy_dfi_p1_rddata[48] <= main_k7ddrphy_bitslip162[3];
+    main_k7ddrphy_dfi_p1_rddata[17] <= main_k7ddrphy_bitslip172[2];
+    main_k7ddrphy_dfi_p1_rddata[49] <= main_k7ddrphy_bitslip172[3];
+    main_k7ddrphy_dfi_p1_rddata[18] <= main_k7ddrphy_bitslip182[2];
+    main_k7ddrphy_dfi_p1_rddata[50] <= main_k7ddrphy_bitslip182[3];
+    main_k7ddrphy_dfi_p1_rddata[19] <= main_k7ddrphy_bitslip192[2];
+    main_k7ddrphy_dfi_p1_rddata[51] <= main_k7ddrphy_bitslip192[3];
+    main_k7ddrphy_dfi_p1_rddata[20] <= main_k7ddrphy_bitslip202[2];
+    main_k7ddrphy_dfi_p1_rddata[52] <= main_k7ddrphy_bitslip202[3];
+    main_k7ddrphy_dfi_p1_rddata[21] <= main_k7ddrphy_bitslip212[2];
+    main_k7ddrphy_dfi_p1_rddata[53] <= main_k7ddrphy_bitslip212[3];
+    main_k7ddrphy_dfi_p1_rddata[22] <= main_k7ddrphy_bitslip222[2];
+    main_k7ddrphy_dfi_p1_rddata[54] <= main_k7ddrphy_bitslip222[3];
+    main_k7ddrphy_dfi_p1_rddata[23] <= main_k7ddrphy_bitslip232[2];
+    main_k7ddrphy_dfi_p1_rddata[55] <= main_k7ddrphy_bitslip232[3];
+    main_k7ddrphy_dfi_p1_rddata[24] <= main_k7ddrphy_bitslip242[2];
+    main_k7ddrphy_dfi_p1_rddata[56] <= main_k7ddrphy_bitslip242[3];
+    main_k7ddrphy_dfi_p1_rddata[25] <= main_k7ddrphy_bitslip252[2];
+    main_k7ddrphy_dfi_p1_rddata[57] <= main_k7ddrphy_bitslip252[3];
+    main_k7ddrphy_dfi_p1_rddata[26] <= main_k7ddrphy_bitslip262[2];
+    main_k7ddrphy_dfi_p1_rddata[58] <= main_k7ddrphy_bitslip262[3];
+    main_k7ddrphy_dfi_p1_rddata[27] <= main_k7ddrphy_bitslip272[2];
+    main_k7ddrphy_dfi_p1_rddata[59] <= main_k7ddrphy_bitslip272[3];
+    main_k7ddrphy_dfi_p1_rddata[28] <= main_k7ddrphy_bitslip282[2];
+    main_k7ddrphy_dfi_p1_rddata[60] <= main_k7ddrphy_bitslip282[3];
+    main_k7ddrphy_dfi_p1_rddata[29] <= main_k7ddrphy_bitslip292[2];
+    main_k7ddrphy_dfi_p1_rddata[61] <= main_k7ddrphy_bitslip292[3];
+    main_k7ddrphy_dfi_p1_rddata[30] <= main_k7ddrphy_bitslip302[2];
+    main_k7ddrphy_dfi_p1_rddata[62] <= main_k7ddrphy_bitslip302[3];
+    main_k7ddrphy_dfi_p1_rddata[31] <= main_k7ddrphy_bitslip312[2];
+    main_k7ddrphy_dfi_p1_rddata[63] <= main_k7ddrphy_bitslip312[3];
+end
+always @(*) begin
+    main_k7ddrphy_dfi_p2_rddata <= 64'd0;
+    main_k7ddrphy_dfi_p2_rddata[0] <= main_k7ddrphy_bitslip04[4];
+    main_k7ddrphy_dfi_p2_rddata[32] <= main_k7ddrphy_bitslip04[5];
+    main_k7ddrphy_dfi_p2_rddata[1] <= main_k7ddrphy_bitslip14[4];
+    main_k7ddrphy_dfi_p2_rddata[33] <= main_k7ddrphy_bitslip14[5];
+    main_k7ddrphy_dfi_p2_rddata[2] <= main_k7ddrphy_bitslip24[4];
+    main_k7ddrphy_dfi_p2_rddata[34] <= main_k7ddrphy_bitslip24[5];
+    main_k7ddrphy_dfi_p2_rddata[3] <= main_k7ddrphy_bitslip34[4];
+    main_k7ddrphy_dfi_p2_rddata[35] <= main_k7ddrphy_bitslip34[5];
+    main_k7ddrphy_dfi_p2_rddata[4] <= main_k7ddrphy_bitslip42[4];
+    main_k7ddrphy_dfi_p2_rddata[36] <= main_k7ddrphy_bitslip42[5];
+    main_k7ddrphy_dfi_p2_rddata[5] <= main_k7ddrphy_bitslip52[4];
+    main_k7ddrphy_dfi_p2_rddata[37] <= main_k7ddrphy_bitslip52[5];
+    main_k7ddrphy_dfi_p2_rddata[6] <= main_k7ddrphy_bitslip62[4];
+    main_k7ddrphy_dfi_p2_rddata[38] <= main_k7ddrphy_bitslip62[5];
+    main_k7ddrphy_dfi_p2_rddata[7] <= main_k7ddrphy_bitslip72[4];
+    main_k7ddrphy_dfi_p2_rddata[39] <= main_k7ddrphy_bitslip72[5];
+    main_k7ddrphy_dfi_p2_rddata[8] <= main_k7ddrphy_bitslip82[4];
+    main_k7ddrphy_dfi_p2_rddata[40] <= main_k7ddrphy_bitslip82[5];
+    main_k7ddrphy_dfi_p2_rddata[9] <= main_k7ddrphy_bitslip92[4];
+    main_k7ddrphy_dfi_p2_rddata[41] <= main_k7ddrphy_bitslip92[5];
+    main_k7ddrphy_dfi_p2_rddata[10] <= main_k7ddrphy_bitslip102[4];
+    main_k7ddrphy_dfi_p2_rddata[42] <= main_k7ddrphy_bitslip102[5];
+    main_k7ddrphy_dfi_p2_rddata[11] <= main_k7ddrphy_bitslip112[4];
+    main_k7ddrphy_dfi_p2_rddata[43] <= main_k7ddrphy_bitslip112[5];
+    main_k7ddrphy_dfi_p2_rddata[12] <= main_k7ddrphy_bitslip122[4];
+    main_k7ddrphy_dfi_p2_rddata[44] <= main_k7ddrphy_bitslip122[5];
+    main_k7ddrphy_dfi_p2_rddata[13] <= main_k7ddrphy_bitslip132[4];
+    main_k7ddrphy_dfi_p2_rddata[45] <= main_k7ddrphy_bitslip132[5];
+    main_k7ddrphy_dfi_p2_rddata[14] <= main_k7ddrphy_bitslip142[4];
+    main_k7ddrphy_dfi_p2_rddata[46] <= main_k7ddrphy_bitslip142[5];
+    main_k7ddrphy_dfi_p2_rddata[15] <= main_k7ddrphy_bitslip152[4];
+    main_k7ddrphy_dfi_p2_rddata[47] <= main_k7ddrphy_bitslip152[5];
+    main_k7ddrphy_dfi_p2_rddata[16] <= main_k7ddrphy_bitslip162[4];
+    main_k7ddrphy_dfi_p2_rddata[48] <= main_k7ddrphy_bitslip162[5];
+    main_k7ddrphy_dfi_p2_rddata[17] <= main_k7ddrphy_bitslip172[4];
+    main_k7ddrphy_dfi_p2_rddata[49] <= main_k7ddrphy_bitslip172[5];
+    main_k7ddrphy_dfi_p2_rddata[18] <= main_k7ddrphy_bitslip182[4];
+    main_k7ddrphy_dfi_p2_rddata[50] <= main_k7ddrphy_bitslip182[5];
+    main_k7ddrphy_dfi_p2_rddata[19] <= main_k7ddrphy_bitslip192[4];
+    main_k7ddrphy_dfi_p2_rddata[51] <= main_k7ddrphy_bitslip192[5];
+    main_k7ddrphy_dfi_p2_rddata[20] <= main_k7ddrphy_bitslip202[4];
+    main_k7ddrphy_dfi_p2_rddata[52] <= main_k7ddrphy_bitslip202[5];
+    main_k7ddrphy_dfi_p2_rddata[21] <= main_k7ddrphy_bitslip212[4];
+    main_k7ddrphy_dfi_p2_rddata[53] <= main_k7ddrphy_bitslip212[5];
+    main_k7ddrphy_dfi_p2_rddata[22] <= main_k7ddrphy_bitslip222[4];
+    main_k7ddrphy_dfi_p2_rddata[54] <= main_k7ddrphy_bitslip222[5];
+    main_k7ddrphy_dfi_p2_rddata[23] <= main_k7ddrphy_bitslip232[4];
+    main_k7ddrphy_dfi_p2_rddata[55] <= main_k7ddrphy_bitslip232[5];
+    main_k7ddrphy_dfi_p2_rddata[24] <= main_k7ddrphy_bitslip242[4];
+    main_k7ddrphy_dfi_p2_rddata[56] <= main_k7ddrphy_bitslip242[5];
+    main_k7ddrphy_dfi_p2_rddata[25] <= main_k7ddrphy_bitslip252[4];
+    main_k7ddrphy_dfi_p2_rddata[57] <= main_k7ddrphy_bitslip252[5];
+    main_k7ddrphy_dfi_p2_rddata[26] <= main_k7ddrphy_bitslip262[4];
+    main_k7ddrphy_dfi_p2_rddata[58] <= main_k7ddrphy_bitslip262[5];
+    main_k7ddrphy_dfi_p2_rddata[27] <= main_k7ddrphy_bitslip272[4];
+    main_k7ddrphy_dfi_p2_rddata[59] <= main_k7ddrphy_bitslip272[5];
+    main_k7ddrphy_dfi_p2_rddata[28] <= main_k7ddrphy_bitslip282[4];
+    main_k7ddrphy_dfi_p2_rddata[60] <= main_k7ddrphy_bitslip282[5];
+    main_k7ddrphy_dfi_p2_rddata[29] <= main_k7ddrphy_bitslip292[4];
+    main_k7ddrphy_dfi_p2_rddata[61] <= main_k7ddrphy_bitslip292[5];
+    main_k7ddrphy_dfi_p2_rddata[30] <= main_k7ddrphy_bitslip302[4];
+    main_k7ddrphy_dfi_p2_rddata[62] <= main_k7ddrphy_bitslip302[5];
+    main_k7ddrphy_dfi_p2_rddata[31] <= main_k7ddrphy_bitslip312[4];
+    main_k7ddrphy_dfi_p2_rddata[63] <= main_k7ddrphy_bitslip312[5];
+end
+always @(*) begin
+    main_k7ddrphy_dfi_p3_rddata <= 64'd0;
+    main_k7ddrphy_dfi_p3_rddata[0] <= main_k7ddrphy_bitslip04[6];
+    main_k7ddrphy_dfi_p3_rddata[32] <= main_k7ddrphy_bitslip04[7];
+    main_k7ddrphy_dfi_p3_rddata[1] <= main_k7ddrphy_bitslip14[6];
+    main_k7ddrphy_dfi_p3_rddata[33] <= main_k7ddrphy_bitslip14[7];
+    main_k7ddrphy_dfi_p3_rddata[2] <= main_k7ddrphy_bitslip24[6];
+    main_k7ddrphy_dfi_p3_rddata[34] <= main_k7ddrphy_bitslip24[7];
+    main_k7ddrphy_dfi_p3_rddata[3] <= main_k7ddrphy_bitslip34[6];
+    main_k7ddrphy_dfi_p3_rddata[35] <= main_k7ddrphy_bitslip34[7];
+    main_k7ddrphy_dfi_p3_rddata[4] <= main_k7ddrphy_bitslip42[6];
+    main_k7ddrphy_dfi_p3_rddata[36] <= main_k7ddrphy_bitslip42[7];
+    main_k7ddrphy_dfi_p3_rddata[5] <= main_k7ddrphy_bitslip52[6];
+    main_k7ddrphy_dfi_p3_rddata[37] <= main_k7ddrphy_bitslip52[7];
+    main_k7ddrphy_dfi_p3_rddata[6] <= main_k7ddrphy_bitslip62[6];
+    main_k7ddrphy_dfi_p3_rddata[38] <= main_k7ddrphy_bitslip62[7];
+    main_k7ddrphy_dfi_p3_rddata[7] <= main_k7ddrphy_bitslip72[6];
+    main_k7ddrphy_dfi_p3_rddata[39] <= main_k7ddrphy_bitslip72[7];
+    main_k7ddrphy_dfi_p3_rddata[8] <= main_k7ddrphy_bitslip82[6];
+    main_k7ddrphy_dfi_p3_rddata[40] <= main_k7ddrphy_bitslip82[7];
+    main_k7ddrphy_dfi_p3_rddata[9] <= main_k7ddrphy_bitslip92[6];
+    main_k7ddrphy_dfi_p3_rddata[41] <= main_k7ddrphy_bitslip92[7];
+    main_k7ddrphy_dfi_p3_rddata[10] <= main_k7ddrphy_bitslip102[6];
+    main_k7ddrphy_dfi_p3_rddata[42] <= main_k7ddrphy_bitslip102[7];
+    main_k7ddrphy_dfi_p3_rddata[11] <= main_k7ddrphy_bitslip112[6];
+    main_k7ddrphy_dfi_p3_rddata[43] <= main_k7ddrphy_bitslip112[7];
+    main_k7ddrphy_dfi_p3_rddata[12] <= main_k7ddrphy_bitslip122[6];
+    main_k7ddrphy_dfi_p3_rddata[44] <= main_k7ddrphy_bitslip122[7];
+    main_k7ddrphy_dfi_p3_rddata[13] <= main_k7ddrphy_bitslip132[6];
+    main_k7ddrphy_dfi_p3_rddata[45] <= main_k7ddrphy_bitslip132[7];
+    main_k7ddrphy_dfi_p3_rddata[14] <= main_k7ddrphy_bitslip142[6];
+    main_k7ddrphy_dfi_p3_rddata[46] <= main_k7ddrphy_bitslip142[7];
+    main_k7ddrphy_dfi_p3_rddata[15] <= main_k7ddrphy_bitslip152[6];
+    main_k7ddrphy_dfi_p3_rddata[47] <= main_k7ddrphy_bitslip152[7];
+    main_k7ddrphy_dfi_p3_rddata[16] <= main_k7ddrphy_bitslip162[6];
+    main_k7ddrphy_dfi_p3_rddata[48] <= main_k7ddrphy_bitslip162[7];
+    main_k7ddrphy_dfi_p3_rddata[17] <= main_k7ddrphy_bitslip172[6];
+    main_k7ddrphy_dfi_p3_rddata[49] <= main_k7ddrphy_bitslip172[7];
+    main_k7ddrphy_dfi_p3_rddata[18] <= main_k7ddrphy_bitslip182[6];
+    main_k7ddrphy_dfi_p3_rddata[50] <= main_k7ddrphy_bitslip182[7];
+    main_k7ddrphy_dfi_p3_rddata[19] <= main_k7ddrphy_bitslip192[6];
+    main_k7ddrphy_dfi_p3_rddata[51] <= main_k7ddrphy_bitslip192[7];
+    main_k7ddrphy_dfi_p3_rddata[20] <= main_k7ddrphy_bitslip202[6];
+    main_k7ddrphy_dfi_p3_rddata[52] <= main_k7ddrphy_bitslip202[7];
+    main_k7ddrphy_dfi_p3_rddata[21] <= main_k7ddrphy_bitslip212[6];
+    main_k7ddrphy_dfi_p3_rddata[53] <= main_k7ddrphy_bitslip212[7];
+    main_k7ddrphy_dfi_p3_rddata[22] <= main_k7ddrphy_bitslip222[6];
+    main_k7ddrphy_dfi_p3_rddata[54] <= main_k7ddrphy_bitslip222[7];
+    main_k7ddrphy_dfi_p3_rddata[23] <= main_k7ddrphy_bitslip232[6];
+    main_k7ddrphy_dfi_p3_rddata[55] <= main_k7ddrphy_bitslip232[7];
+    main_k7ddrphy_dfi_p3_rddata[24] <= main_k7ddrphy_bitslip242[6];
+    main_k7ddrphy_dfi_p3_rddata[56] <= main_k7ddrphy_bitslip242[7];
+    main_k7ddrphy_dfi_p3_rddata[25] <= main_k7ddrphy_bitslip252[6];
+    main_k7ddrphy_dfi_p3_rddata[57] <= main_k7ddrphy_bitslip252[7];
+    main_k7ddrphy_dfi_p3_rddata[26] <= main_k7ddrphy_bitslip262[6];
+    main_k7ddrphy_dfi_p3_rddata[58] <= main_k7ddrphy_bitslip262[7];
+    main_k7ddrphy_dfi_p3_rddata[27] <= main_k7ddrphy_bitslip272[6];
+    main_k7ddrphy_dfi_p3_rddata[59] <= main_k7ddrphy_bitslip272[7];
+    main_k7ddrphy_dfi_p3_rddata[28] <= main_k7ddrphy_bitslip282[6];
+    main_k7ddrphy_dfi_p3_rddata[60] <= main_k7ddrphy_bitslip282[7];
+    main_k7ddrphy_dfi_p3_rddata[29] <= main_k7ddrphy_bitslip292[6];
+    main_k7ddrphy_dfi_p3_rddata[61] <= main_k7ddrphy_bitslip292[7];
+    main_k7ddrphy_dfi_p3_rddata[30] <= main_k7ddrphy_bitslip302[6];
+    main_k7ddrphy_dfi_p3_rddata[62] <= main_k7ddrphy_bitslip302[7];
+    main_k7ddrphy_dfi_p3_rddata[31] <= main_k7ddrphy_bitslip312[6];
+    main_k7ddrphy_dfi_p3_rddata[63] <= main_k7ddrphy_bitslip312[7];
+end
+assign main_k7ddrphy_dfi_p0_rddata_valid = (main_k7ddrphy_rddata_en_tappeddelayline7 | main_k7ddrphy_wlevel_en_storage);
+assign main_k7ddrphy_dfi_p1_rddata_valid = (main_k7ddrphy_rddata_en_tappeddelayline7 | main_k7ddrphy_wlevel_en_storage);
+assign main_k7ddrphy_dfi_p2_rddata_valid = (main_k7ddrphy_rddata_en_tappeddelayline7 | main_k7ddrphy_wlevel_en_storage);
+assign main_k7ddrphy_dfi_p3_rddata_valid = (main_k7ddrphy_rddata_en_tappeddelayline7 | main_k7ddrphy_wlevel_en_storage);
+assign main_k7ddrphy_dq_oe = main_k7ddrphy_wrdata_en_tappeddelayline1;
+always @(*) begin
+    main_k7ddrphy_dqs_oe <= 1'd0;
+    if (main_k7ddrphy_wlevel_en_storage) begin
+        main_k7ddrphy_dqs_oe <= 1'd1;
     end else begin
-        k7ddrphy_dqs_oe <= k7ddrphy_dq_oe;
+        main_k7ddrphy_dqs_oe <= main_k7ddrphy_dq_oe;
     end
 end
-assign k7ddrphy_dqs_preamble = (k7ddrphy_wrdata_en_tappeddelayline0 & (~k7ddrphy_wrdata_en_tappeddelayline1));
-assign k7ddrphy_dqs_postamble = (k7ddrphy_wrdata_en_tappeddelayline2 & (~k7ddrphy_wrdata_en_tappeddelayline1));
+assign main_k7ddrphy_dqs_preamble = (main_k7ddrphy_wrdata_en_tappeddelayline0 & (~main_k7ddrphy_wrdata_en_tappeddelayline1));
+assign main_k7ddrphy_dqs_postamble = (main_k7ddrphy_wrdata_en_tappeddelayline2 & (~main_k7ddrphy_wrdata_en_tappeddelayline1));
 always @(*) begin
-    k7ddrphy_dqspattern_o <= 8'd0;
-    k7ddrphy_dqspattern_o <= 7'd85;
-    if (k7ddrphy_dqspattern0) begin
-        k7ddrphy_dqspattern_o <= 5'd21;
+    main_k7ddrphy_dqspattern_o <= 8'd0;
+    main_k7ddrphy_dqspattern_o <= 7'd85;
+    if (main_k7ddrphy_dqspattern0) begin
+        main_k7ddrphy_dqspattern_o <= 5'd21;
     end
-    if (k7ddrphy_dqspattern1) begin
-        k7ddrphy_dqspattern_o <= 7'd84;
+    if (main_k7ddrphy_dqspattern1) begin
+        main_k7ddrphy_dqspattern_o <= 7'd84;
     end
-    if (k7ddrphy_wlevel_en_storage) begin
-        k7ddrphy_dqspattern_o <= 1'd0;
-        if (k7ddrphy_wlevel_strobe_re) begin
-            k7ddrphy_dqspattern_o <= 1'd1;
+    if (main_k7ddrphy_wlevel_en_storage) begin
+        main_k7ddrphy_dqspattern_o <= 1'd0;
+        if (main_k7ddrphy_wlevel_strobe_re) begin
+            main_k7ddrphy_dqspattern_o <= 1'd1;
         end
     end
 end
 always @(*) begin
-    k7ddrphy_bitslip00 <= 8'd0;
-    case (k7ddrphy_bitslip0_value0)
+    main_k7ddrphy_bitslip00 <= 8'd0;
+    case (main_k7ddrphy_bitslip0_value0)
         1'd0: begin
-            k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[8:1];
+            main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[9:2];
+            main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[10:3];
+            main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[11:4];
+            main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[12:5];
+            main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[13:6];
+            main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[14:7];
+            main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[15:8];
+            main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip10 <= 8'd0;
-    case (k7ddrphy_bitslip1_value0)
+    main_k7ddrphy_bitslip10 <= 8'd0;
+    case (main_k7ddrphy_bitslip1_value0)
         1'd0: begin
-            k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[8:1];
+            main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[9:2];
+            main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[10:3];
+            main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[11:4];
+            main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[12:5];
+            main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[13:6];
+            main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[14:7];
+            main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[15:8];
+            main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip20 <= 8'd0;
-    case (k7ddrphy_bitslip2_value0)
+    main_k7ddrphy_bitslip20 <= 8'd0;
+    case (main_k7ddrphy_bitslip2_value0)
         1'd0: begin
-            k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[8:1];
+            main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[9:2];
+            main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[10:3];
+            main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[11:4];
+            main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[12:5];
+            main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[13:6];
+            main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[14:7];
+            main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[15:8];
+            main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip30 <= 8'd0;
-    case (k7ddrphy_bitslip3_value0)
+    main_k7ddrphy_bitslip30 <= 8'd0;
+    case (main_k7ddrphy_bitslip3_value0)
         1'd0: begin
-            k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[8:1];
+            main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[9:2];
+            main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[10:3];
+            main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[11:4];
+            main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[12:5];
+            main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[13:6];
+            main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[14:7];
+            main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[15:8];
+            main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip01 <= 8'd0;
-    case (k7ddrphy_bitslip0_value1)
+    main_k7ddrphy_bitslip01 <= 8'd0;
+    case (main_k7ddrphy_bitslip0_value1)
         1'd0: begin
-            k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[8:1];
+            main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[9:2];
+            main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[10:3];
+            main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[11:4];
+            main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[12:5];
+            main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[13:6];
+            main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[14:7];
+            main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[15:8];
+            main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip11 <= 8'd0;
-    case (k7ddrphy_bitslip1_value1)
+    main_k7ddrphy_bitslip11 <= 8'd0;
+    case (main_k7ddrphy_bitslip1_value1)
         1'd0: begin
-            k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[8:1];
+            main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[9:2];
+            main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[10:3];
+            main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[11:4];
+            main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[12:5];
+            main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[13:6];
+            main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[14:7];
+            main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[15:8];
+            main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip21 <= 8'd0;
-    case (k7ddrphy_bitslip2_value1)
+    main_k7ddrphy_bitslip21 <= 8'd0;
+    case (main_k7ddrphy_bitslip2_value1)
         1'd0: begin
-            k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[8:1];
+            main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[9:2];
+            main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[10:3];
+            main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[11:4];
+            main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[12:5];
+            main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[13:6];
+            main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[14:7];
+            main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[15:8];
+            main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip31 <= 8'd0;
-    case (k7ddrphy_bitslip3_value1)
+    main_k7ddrphy_bitslip31 <= 8'd0;
+    case (main_k7ddrphy_bitslip3_value1)
         1'd0: begin
-            k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[8:1];
+            main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[9:2];
+            main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[10:3];
+            main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[11:4];
+            main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[12:5];
+            main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[13:6];
+            main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[14:7];
+            main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[15:8];
+            main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip02 <= 8'd0;
-    case (k7ddrphy_bitslip0_value2)
+    main_k7ddrphy_bitslip02 <= 8'd0;
+    case (main_k7ddrphy_bitslip0_value2)
         1'd0: begin
-            k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[8:1];
+            main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[9:2];
+            main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[10:3];
+            main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[11:4];
+            main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[12:5];
+            main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[13:6];
+            main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[14:7];
+            main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[15:8];
+            main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip04 <= 8'd0;
-    case (k7ddrphy_bitslip0_value3)
+    main_k7ddrphy_bitslip04 <= 8'd0;
+    case (main_k7ddrphy_bitslip0_value3)
         1'd0: begin
-            k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[8:1];
+            main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[9:2];
+            main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[10:3];
+            main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[11:4];
+            main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[12:5];
+            main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[13:6];
+            main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[14:7];
+            main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[15:8];
+            main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip12 <= 8'd0;
-    case (k7ddrphy_bitslip1_value2)
+    main_k7ddrphy_bitslip12 <= 8'd0;
+    case (main_k7ddrphy_bitslip1_value2)
         1'd0: begin
-            k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[8:1];
+            main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[9:2];
+            main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[10:3];
+            main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[11:4];
+            main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[12:5];
+            main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[13:6];
+            main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[14:7];
+            main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[15:8];
+            main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip14 <= 8'd0;
-    case (k7ddrphy_bitslip1_value3)
+    main_k7ddrphy_bitslip14 <= 8'd0;
+    case (main_k7ddrphy_bitslip1_value3)
         1'd0: begin
-            k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[8:1];
+            main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[9:2];
+            main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[10:3];
+            main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[11:4];
+            main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[12:5];
+            main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[13:6];
+            main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[14:7];
+            main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[15:8];
+            main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip22 <= 8'd0;
-    case (k7ddrphy_bitslip2_value2)
+    main_k7ddrphy_bitslip22 <= 8'd0;
+    case (main_k7ddrphy_bitslip2_value2)
         1'd0: begin
-            k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[8:1];
+            main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[9:2];
+            main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[10:3];
+            main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[11:4];
+            main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[12:5];
+            main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[13:6];
+            main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[14:7];
+            main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[15:8];
+            main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip24 <= 8'd0;
-    case (k7ddrphy_bitslip2_value3)
+    main_k7ddrphy_bitslip24 <= 8'd0;
+    case (main_k7ddrphy_bitslip2_value3)
         1'd0: begin
-            k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[8:1];
+            main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[9:2];
+            main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[10:3];
+            main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[11:4];
+            main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[12:5];
+            main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[13:6];
+            main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[14:7];
+            main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[15:8];
+            main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip32 <= 8'd0;
-    case (k7ddrphy_bitslip3_value2)
+    main_k7ddrphy_bitslip32 <= 8'd0;
+    case (main_k7ddrphy_bitslip3_value2)
         1'd0: begin
-            k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[8:1];
+            main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[9:2];
+            main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[10:3];
+            main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[11:4];
+            main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[12:5];
+            main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[13:6];
+            main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[14:7];
+            main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[15:8];
+            main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip34 <= 8'd0;
-    case (k7ddrphy_bitslip3_value3)
+    main_k7ddrphy_bitslip34 <= 8'd0;
+    case (main_k7ddrphy_bitslip3_value3)
         1'd0: begin
-            k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[8:1];
+            main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[9:2];
+            main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[10:3];
+            main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[11:4];
+            main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[12:5];
+            main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[13:6];
+            main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[14:7];
+            main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[15:8];
+            main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip40 <= 8'd0;
-    case (k7ddrphy_bitslip4_value0)
+    main_k7ddrphy_bitslip40 <= 8'd0;
+    case (main_k7ddrphy_bitslip4_value0)
         1'd0: begin
-            k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[8:1];
+            main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[9:2];
+            main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[10:3];
+            main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[11:4];
+            main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[12:5];
+            main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[13:6];
+            main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[14:7];
+            main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[15:8];
+            main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip42 <= 8'd0;
-    case (k7ddrphy_bitslip4_value1)
+    main_k7ddrphy_bitslip42 <= 8'd0;
+    case (main_k7ddrphy_bitslip4_value1)
         1'd0: begin
-            k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[8:1];
+            main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[9:2];
+            main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[10:3];
+            main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[11:4];
+            main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[12:5];
+            main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[13:6];
+            main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[14:7];
+            main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[15:8];
+            main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip50 <= 8'd0;
-    case (k7ddrphy_bitslip5_value0)
+    main_k7ddrphy_bitslip50 <= 8'd0;
+    case (main_k7ddrphy_bitslip5_value0)
         1'd0: begin
-            k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[8:1];
+            main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[9:2];
+            main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[10:3];
+            main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[11:4];
+            main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[12:5];
+            main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[13:6];
+            main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[14:7];
+            main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[15:8];
+            main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip52 <= 8'd0;
-    case (k7ddrphy_bitslip5_value1)
+    main_k7ddrphy_bitslip52 <= 8'd0;
+    case (main_k7ddrphy_bitslip5_value1)
         1'd0: begin
-            k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[8:1];
+            main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[9:2];
+            main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[10:3];
+            main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[11:4];
+            main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[12:5];
+            main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[13:6];
+            main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[14:7];
+            main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[15:8];
+            main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip60 <= 8'd0;
-    case (k7ddrphy_bitslip6_value0)
+    main_k7ddrphy_bitslip60 <= 8'd0;
+    case (main_k7ddrphy_bitslip6_value0)
         1'd0: begin
-            k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[8:1];
+            main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[9:2];
+            main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[10:3];
+            main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[11:4];
+            main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[12:5];
+            main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[13:6];
+            main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[14:7];
+            main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[15:8];
+            main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip62 <= 8'd0;
-    case (k7ddrphy_bitslip6_value1)
+    main_k7ddrphy_bitslip62 <= 8'd0;
+    case (main_k7ddrphy_bitslip6_value1)
         1'd0: begin
-            k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[8:1];
+            main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[9:2];
+            main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[10:3];
+            main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[11:4];
+            main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[12:5];
+            main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[13:6];
+            main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[14:7];
+            main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[15:8];
+            main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip70 <= 8'd0;
-    case (k7ddrphy_bitslip7_value0)
+    main_k7ddrphy_bitslip70 <= 8'd0;
+    case (main_k7ddrphy_bitslip7_value0)
         1'd0: begin
-            k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[8:1];
+            main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[9:2];
+            main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[10:3];
+            main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[11:4];
+            main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[12:5];
+            main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[13:6];
+            main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[14:7];
+            main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[15:8];
+            main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip72 <= 8'd0;
-    case (k7ddrphy_bitslip7_value1)
+    main_k7ddrphy_bitslip72 <= 8'd0;
+    case (main_k7ddrphy_bitslip7_value1)
         1'd0: begin
-            k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[8:1];
+            main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[9:2];
+            main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[10:3];
+            main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[11:4];
+            main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[12:5];
+            main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[13:6];
+            main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[14:7];
+            main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[15:8];
+            main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip80 <= 8'd0;
-    case (k7ddrphy_bitslip8_value0)
+    main_k7ddrphy_bitslip80 <= 8'd0;
+    case (main_k7ddrphy_bitslip8_value0)
         1'd0: begin
-            k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[8:1];
+            main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[9:2];
+            main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[10:3];
+            main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[11:4];
+            main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[12:5];
+            main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[13:6];
+            main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[14:7];
+            main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[15:8];
+            main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip82 <= 8'd0;
-    case (k7ddrphy_bitslip8_value1)
+    main_k7ddrphy_bitslip82 <= 8'd0;
+    case (main_k7ddrphy_bitslip8_value1)
         1'd0: begin
-            k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[8:1];
+            main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[9:2];
+            main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[10:3];
+            main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[11:4];
+            main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[12:5];
+            main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[13:6];
+            main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[14:7];
+            main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[15:8];
+            main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip90 <= 8'd0;
-    case (k7ddrphy_bitslip9_value0)
+    main_k7ddrphy_bitslip90 <= 8'd0;
+    case (main_k7ddrphy_bitslip9_value0)
         1'd0: begin
-            k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[8:1];
+            main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[9:2];
+            main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[10:3];
+            main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[11:4];
+            main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[12:5];
+            main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[13:6];
+            main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[14:7];
+            main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[15:8];
+            main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip92 <= 8'd0;
-    case (k7ddrphy_bitslip9_value1)
+    main_k7ddrphy_bitslip92 <= 8'd0;
+    case (main_k7ddrphy_bitslip9_value1)
         1'd0: begin
-            k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[8:1];
+            main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[9:2];
+            main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[10:3];
+            main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[11:4];
+            main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[12:5];
+            main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[13:6];
+            main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[14:7];
+            main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[15:8];
+            main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip100 <= 8'd0;
-    case (k7ddrphy_bitslip10_value0)
+    main_k7ddrphy_bitslip100 <= 8'd0;
+    case (main_k7ddrphy_bitslip10_value0)
         1'd0: begin
-            k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[8:1];
+            main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[9:2];
+            main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[10:3];
+            main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[11:4];
+            main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[12:5];
+            main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[13:6];
+            main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[14:7];
+            main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[15:8];
+            main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip102 <= 8'd0;
-    case (k7ddrphy_bitslip10_value1)
+    main_k7ddrphy_bitslip102 <= 8'd0;
+    case (main_k7ddrphy_bitslip10_value1)
         1'd0: begin
-            k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[8:1];
+            main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[9:2];
+            main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[10:3];
+            main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[11:4];
+            main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[12:5];
+            main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[13:6];
+            main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[14:7];
+            main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[15:8];
+            main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip110 <= 8'd0;
-    case (k7ddrphy_bitslip11_value0)
+    main_k7ddrphy_bitslip110 <= 8'd0;
+    case (main_k7ddrphy_bitslip11_value0)
         1'd0: begin
-            k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[8:1];
+            main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[9:2];
+            main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[10:3];
+            main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[11:4];
+            main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[12:5];
+            main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[13:6];
+            main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[14:7];
+            main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[15:8];
+            main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip112 <= 8'd0;
-    case (k7ddrphy_bitslip11_value1)
+    main_k7ddrphy_bitslip112 <= 8'd0;
+    case (main_k7ddrphy_bitslip11_value1)
         1'd0: begin
-            k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[8:1];
+            main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[9:2];
+            main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[10:3];
+            main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[11:4];
+            main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[12:5];
+            main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[13:6];
+            main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[14:7];
+            main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[15:8];
+            main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip120 <= 8'd0;
-    case (k7ddrphy_bitslip12_value0)
+    main_k7ddrphy_bitslip120 <= 8'd0;
+    case (main_k7ddrphy_bitslip12_value0)
         1'd0: begin
-            k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[8:1];
+            main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[9:2];
+            main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[10:3];
+            main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[11:4];
+            main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[12:5];
+            main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[13:6];
+            main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[14:7];
+            main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[15:8];
+            main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip122 <= 8'd0;
-    case (k7ddrphy_bitslip12_value1)
+    main_k7ddrphy_bitslip122 <= 8'd0;
+    case (main_k7ddrphy_bitslip12_value1)
         1'd0: begin
-            k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[8:1];
+            main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[9:2];
+            main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[10:3];
+            main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[11:4];
+            main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[12:5];
+            main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[13:6];
+            main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[14:7];
+            main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[15:8];
+            main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip130 <= 8'd0;
-    case (k7ddrphy_bitslip13_value0)
+    main_k7ddrphy_bitslip130 <= 8'd0;
+    case (main_k7ddrphy_bitslip13_value0)
         1'd0: begin
-            k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[8:1];
+            main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[9:2];
+            main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[10:3];
+            main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[11:4];
+            main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[12:5];
+            main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[13:6];
+            main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[14:7];
+            main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[15:8];
+            main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip132 <= 8'd0;
-    case (k7ddrphy_bitslip13_value1)
+    main_k7ddrphy_bitslip132 <= 8'd0;
+    case (main_k7ddrphy_bitslip13_value1)
         1'd0: begin
-            k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[8:1];
+            main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[9:2];
+            main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[10:3];
+            main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[11:4];
+            main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[12:5];
+            main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[13:6];
+            main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[14:7];
+            main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[15:8];
+            main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip140 <= 8'd0;
-    case (k7ddrphy_bitslip14_value0)
+    main_k7ddrphy_bitslip140 <= 8'd0;
+    case (main_k7ddrphy_bitslip14_value0)
         1'd0: begin
-            k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[8:1];
+            main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[9:2];
+            main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[10:3];
+            main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[11:4];
+            main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[12:5];
+            main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[13:6];
+            main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[14:7];
+            main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[15:8];
+            main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip142 <= 8'd0;
-    case (k7ddrphy_bitslip14_value1)
+    main_k7ddrphy_bitslip142 <= 8'd0;
+    case (main_k7ddrphy_bitslip14_value1)
         1'd0: begin
-            k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[8:1];
+            main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[9:2];
+            main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[10:3];
+            main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[11:4];
+            main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[12:5];
+            main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[13:6];
+            main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[14:7];
+            main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[15:8];
+            main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip150 <= 8'd0;
-    case (k7ddrphy_bitslip15_value0)
+    main_k7ddrphy_bitslip150 <= 8'd0;
+    case (main_k7ddrphy_bitslip15_value0)
         1'd0: begin
-            k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[8:1];
+            main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[9:2];
+            main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[10:3];
+            main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[11:4];
+            main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[12:5];
+            main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[13:6];
+            main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[14:7];
+            main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[15:8];
+            main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip152 <= 8'd0;
-    case (k7ddrphy_bitslip15_value1)
+    main_k7ddrphy_bitslip152 <= 8'd0;
+    case (main_k7ddrphy_bitslip15_value1)
         1'd0: begin
-            k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[8:1];
+            main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[9:2];
+            main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[10:3];
+            main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[11:4];
+            main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[12:5];
+            main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[13:6];
+            main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[14:7];
+            main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[15:8];
+            main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip160 <= 8'd0;
-    case (k7ddrphy_bitslip16_value0)
+    main_k7ddrphy_bitslip160 <= 8'd0;
+    case (main_k7ddrphy_bitslip16_value0)
         1'd0: begin
-            k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[8:1];
+            main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[9:2];
+            main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[10:3];
+            main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[11:4];
+            main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[12:5];
+            main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[13:6];
+            main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[14:7];
+            main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[15:8];
+            main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip162 <= 8'd0;
-    case (k7ddrphy_bitslip16_value1)
+    main_k7ddrphy_bitslip162 <= 8'd0;
+    case (main_k7ddrphy_bitslip16_value1)
         1'd0: begin
-            k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[8:1];
+            main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[9:2];
+            main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[10:3];
+            main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[11:4];
+            main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[12:5];
+            main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[13:6];
+            main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[14:7];
+            main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[15:8];
+            main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip170 <= 8'd0;
-    case (k7ddrphy_bitslip17_value0)
+    main_k7ddrphy_bitslip170 <= 8'd0;
+    case (main_k7ddrphy_bitslip17_value0)
         1'd0: begin
-            k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[8:1];
+            main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[9:2];
+            main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[10:3];
+            main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[11:4];
+            main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[12:5];
+            main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[13:6];
+            main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[14:7];
+            main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[15:8];
+            main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip172 <= 8'd0;
-    case (k7ddrphy_bitslip17_value1)
+    main_k7ddrphy_bitslip172 <= 8'd0;
+    case (main_k7ddrphy_bitslip17_value1)
         1'd0: begin
-            k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[8:1];
+            main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[9:2];
+            main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[10:3];
+            main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[11:4];
+            main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[12:5];
+            main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[13:6];
+            main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[14:7];
+            main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[15:8];
+            main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip180 <= 8'd0;
-    case (k7ddrphy_bitslip18_value0)
+    main_k7ddrphy_bitslip180 <= 8'd0;
+    case (main_k7ddrphy_bitslip18_value0)
         1'd0: begin
-            k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[8:1];
+            main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[9:2];
+            main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[10:3];
+            main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[11:4];
+            main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[12:5];
+            main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[13:6];
+            main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[14:7];
+            main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[15:8];
+            main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip182 <= 8'd0;
-    case (k7ddrphy_bitslip18_value1)
+    main_k7ddrphy_bitslip182 <= 8'd0;
+    case (main_k7ddrphy_bitslip18_value1)
         1'd0: begin
-            k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[8:1];
+            main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[9:2];
+            main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[10:3];
+            main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[11:4];
+            main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[12:5];
+            main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[13:6];
+            main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[14:7];
+            main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[15:8];
+            main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip190 <= 8'd0;
-    case (k7ddrphy_bitslip19_value0)
+    main_k7ddrphy_bitslip190 <= 8'd0;
+    case (main_k7ddrphy_bitslip19_value0)
         1'd0: begin
-            k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[8:1];
+            main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[9:2];
+            main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[10:3];
+            main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[11:4];
+            main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[12:5];
+            main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[13:6];
+            main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[14:7];
+            main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[15:8];
+            main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip192 <= 8'd0;
-    case (k7ddrphy_bitslip19_value1)
+    main_k7ddrphy_bitslip192 <= 8'd0;
+    case (main_k7ddrphy_bitslip19_value1)
         1'd0: begin
-            k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[8:1];
+            main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[9:2];
+            main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[10:3];
+            main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[11:4];
+            main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[12:5];
+            main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[13:6];
+            main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[14:7];
+            main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[15:8];
+            main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip200 <= 8'd0;
-    case (k7ddrphy_bitslip20_value0)
+    main_k7ddrphy_bitslip200 <= 8'd0;
+    case (main_k7ddrphy_bitslip20_value0)
         1'd0: begin
-            k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[8:1];
+            main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[9:2];
+            main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[10:3];
+            main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[11:4];
+            main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[12:5];
+            main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[13:6];
+            main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[14:7];
+            main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[15:8];
+            main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip202 <= 8'd0;
-    case (k7ddrphy_bitslip20_value1)
+    main_k7ddrphy_bitslip202 <= 8'd0;
+    case (main_k7ddrphy_bitslip20_value1)
         1'd0: begin
-            k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[8:1];
+            main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[9:2];
+            main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[10:3];
+            main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[11:4];
+            main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[12:5];
+            main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[13:6];
+            main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[14:7];
+            main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[15:8];
+            main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip210 <= 8'd0;
-    case (k7ddrphy_bitslip21_value0)
+    main_k7ddrphy_bitslip210 <= 8'd0;
+    case (main_k7ddrphy_bitslip21_value0)
         1'd0: begin
-            k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[8:1];
+            main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[9:2];
+            main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[10:3];
+            main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[11:4];
+            main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[12:5];
+            main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[13:6];
+            main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[14:7];
+            main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[15:8];
+            main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip212 <= 8'd0;
-    case (k7ddrphy_bitslip21_value1)
+    main_k7ddrphy_bitslip212 <= 8'd0;
+    case (main_k7ddrphy_bitslip21_value1)
         1'd0: begin
-            k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[8:1];
+            main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[9:2];
+            main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[10:3];
+            main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[11:4];
+            main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[12:5];
+            main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[13:6];
+            main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[14:7];
+            main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[15:8];
+            main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip220 <= 8'd0;
-    case (k7ddrphy_bitslip22_value0)
+    main_k7ddrphy_bitslip220 <= 8'd0;
+    case (main_k7ddrphy_bitslip22_value0)
         1'd0: begin
-            k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[8:1];
+            main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[9:2];
+            main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[10:3];
+            main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[11:4];
+            main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[12:5];
+            main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[13:6];
+            main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[14:7];
+            main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[15:8];
+            main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip222 <= 8'd0;
-    case (k7ddrphy_bitslip22_value1)
+    main_k7ddrphy_bitslip222 <= 8'd0;
+    case (main_k7ddrphy_bitslip22_value1)
         1'd0: begin
-            k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[8:1];
+            main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[9:2];
+            main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[10:3];
+            main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[11:4];
+            main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[12:5];
+            main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[13:6];
+            main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[14:7];
+            main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[15:8];
+            main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip230 <= 8'd0;
-    case (k7ddrphy_bitslip23_value0)
+    main_k7ddrphy_bitslip230 <= 8'd0;
+    case (main_k7ddrphy_bitslip23_value0)
         1'd0: begin
-            k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[8:1];
+            main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[9:2];
+            main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[10:3];
+            main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[11:4];
+            main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[12:5];
+            main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[13:6];
+            main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[14:7];
+            main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[15:8];
+            main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip232 <= 8'd0;
-    case (k7ddrphy_bitslip23_value1)
+    main_k7ddrphy_bitslip232 <= 8'd0;
+    case (main_k7ddrphy_bitslip23_value1)
         1'd0: begin
-            k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[8:1];
+            main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[9:2];
+            main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[10:3];
+            main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[11:4];
+            main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[12:5];
+            main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[13:6];
+            main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[14:7];
+            main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[15:8];
+            main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip240 <= 8'd0;
-    case (k7ddrphy_bitslip24_value0)
+    main_k7ddrphy_bitslip240 <= 8'd0;
+    case (main_k7ddrphy_bitslip24_value0)
         1'd0: begin
-            k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[8:1];
+            main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[9:2];
+            main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[10:3];
+            main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[11:4];
+            main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[12:5];
+            main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[13:6];
+            main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[14:7];
+            main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[15:8];
+            main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip242 <= 8'd0;
-    case (k7ddrphy_bitslip24_value1)
+    main_k7ddrphy_bitslip242 <= 8'd0;
+    case (main_k7ddrphy_bitslip24_value1)
         1'd0: begin
-            k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[8:1];
+            main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[9:2];
+            main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[10:3];
+            main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[11:4];
+            main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[12:5];
+            main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[13:6];
+            main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[14:7];
+            main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[15:8];
+            main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip250 <= 8'd0;
-    case (k7ddrphy_bitslip25_value0)
+    main_k7ddrphy_bitslip250 <= 8'd0;
+    case (main_k7ddrphy_bitslip25_value0)
         1'd0: begin
-            k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[8:1];
+            main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[9:2];
+            main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[10:3];
+            main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[11:4];
+            main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[12:5];
+            main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[13:6];
+            main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[14:7];
+            main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[15:8];
+            main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip252 <= 8'd0;
-    case (k7ddrphy_bitslip25_value1)
+    main_k7ddrphy_bitslip252 <= 8'd0;
+    case (main_k7ddrphy_bitslip25_value1)
         1'd0: begin
-            k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[8:1];
+            main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[9:2];
+            main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[10:3];
+            main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[11:4];
+            main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[12:5];
+            main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[13:6];
+            main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[14:7];
+            main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[15:8];
+            main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip260 <= 8'd0;
-    case (k7ddrphy_bitslip26_value0)
+    main_k7ddrphy_bitslip260 <= 8'd0;
+    case (main_k7ddrphy_bitslip26_value0)
         1'd0: begin
-            k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[8:1];
+            main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[9:2];
+            main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[10:3];
+            main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[11:4];
+            main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[12:5];
+            main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[13:6];
+            main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[14:7];
+            main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[15:8];
+            main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip262 <= 8'd0;
-    case (k7ddrphy_bitslip26_value1)
+    main_k7ddrphy_bitslip262 <= 8'd0;
+    case (main_k7ddrphy_bitslip26_value1)
         1'd0: begin
-            k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[8:1];
+            main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[9:2];
+            main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[10:3];
+            main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[11:4];
+            main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[12:5];
+            main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[13:6];
+            main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[14:7];
+            main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[15:8];
+            main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip270 <= 8'd0;
-    case (k7ddrphy_bitslip27_value0)
+    main_k7ddrphy_bitslip270 <= 8'd0;
+    case (main_k7ddrphy_bitslip27_value0)
         1'd0: begin
-            k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[8:1];
+            main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[9:2];
+            main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[10:3];
+            main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[11:4];
+            main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[12:5];
+            main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[13:6];
+            main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[14:7];
+            main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[15:8];
+            main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip272 <= 8'd0;
-    case (k7ddrphy_bitslip27_value1)
+    main_k7ddrphy_bitslip272 <= 8'd0;
+    case (main_k7ddrphy_bitslip27_value1)
         1'd0: begin
-            k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[8:1];
+            main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[9:2];
+            main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[10:3];
+            main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[11:4];
+            main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[12:5];
+            main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[13:6];
+            main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[14:7];
+            main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[15:8];
+            main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip280 <= 8'd0;
-    case (k7ddrphy_bitslip28_value0)
+    main_k7ddrphy_bitslip280 <= 8'd0;
+    case (main_k7ddrphy_bitslip28_value0)
         1'd0: begin
-            k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[8:1];
+            main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[9:2];
+            main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[10:3];
+            main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[11:4];
+            main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[12:5];
+            main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[13:6];
+            main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[14:7];
+            main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[15:8];
+            main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip282 <= 8'd0;
-    case (k7ddrphy_bitslip28_value1)
+    main_k7ddrphy_bitslip282 <= 8'd0;
+    case (main_k7ddrphy_bitslip28_value1)
         1'd0: begin
-            k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[8:1];
+            main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[9:2];
+            main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[10:3];
+            main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[11:4];
+            main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[12:5];
+            main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[13:6];
+            main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[14:7];
+            main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[15:8];
+            main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip290 <= 8'd0;
-    case (k7ddrphy_bitslip29_value0)
+    main_k7ddrphy_bitslip290 <= 8'd0;
+    case (main_k7ddrphy_bitslip29_value0)
         1'd0: begin
-            k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[8:1];
+            main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[9:2];
+            main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[10:3];
+            main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[11:4];
+            main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[12:5];
+            main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[13:6];
+            main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[14:7];
+            main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[15:8];
+            main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip292 <= 8'd0;
-    case (k7ddrphy_bitslip29_value1)
+    main_k7ddrphy_bitslip292 <= 8'd0;
+    case (main_k7ddrphy_bitslip29_value1)
         1'd0: begin
-            k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[8:1];
+            main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[9:2];
+            main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[10:3];
+            main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[11:4];
+            main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[12:5];
+            main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[13:6];
+            main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[14:7];
+            main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[15:8];
+            main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip300 <= 8'd0;
-    case (k7ddrphy_bitslip30_value0)
+    main_k7ddrphy_bitslip300 <= 8'd0;
+    case (main_k7ddrphy_bitslip30_value0)
         1'd0: begin
-            k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[8:1];
+            main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[9:2];
+            main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[10:3];
+            main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[11:4];
+            main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[12:5];
+            main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[13:6];
+            main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[14:7];
+            main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[15:8];
+            main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip302 <= 8'd0;
-    case (k7ddrphy_bitslip30_value1)
+    main_k7ddrphy_bitslip302 <= 8'd0;
+    case (main_k7ddrphy_bitslip30_value1)
         1'd0: begin
-            k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[8:1];
+            main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[9:2];
+            main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[10:3];
+            main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[11:4];
+            main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[12:5];
+            main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[13:6];
+            main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[14:7];
+            main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[15:8];
+            main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip310 <= 8'd0;
-    case (k7ddrphy_bitslip31_value0)
+    main_k7ddrphy_bitslip310 <= 8'd0;
+    case (main_k7ddrphy_bitslip31_value0)
         1'd0: begin
-            k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[8:1];
+            main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[9:2];
+            main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[10:3];
+            main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[11:4];
+            main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[12:5];
+            main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[13:6];
+            main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[14:7];
+            main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[15:8];
+            main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    k7ddrphy_bitslip312 <= 8'd0;
-    case (k7ddrphy_bitslip31_value1)
+    main_k7ddrphy_bitslip312 <= 8'd0;
+    case (main_k7ddrphy_bitslip31_value1)
         1'd0: begin
-            k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[8:1];
+            main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[8:1];
         end
         1'd1: begin
-            k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[9:2];
+            main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[9:2];
         end
         2'd2: begin
-            k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[10:3];
+            main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[10:3];
         end
         2'd3: begin
-            k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[11:4];
+            main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[11:4];
         end
         3'd4: begin
-            k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[12:5];
+            main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[12:5];
         end
         3'd5: begin
-            k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[13:6];
+            main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[13:6];
         end
         3'd6: begin
-            k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[14:7];
+            main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[14:7];
         end
         3'd7: begin
-            k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[15:8];
-        end
-    endcase
-end
-assign k7ddrphy_dfi_p0_address = litedramcore_master_p0_address;
-assign k7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
-assign k7ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n;
-assign k7ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n;
-assign k7ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n;
-assign k7ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n;
-assign k7ddrphy_dfi_p0_cke = litedramcore_master_p0_cke;
-assign k7ddrphy_dfi_p0_odt = litedramcore_master_p0_odt;
-assign k7ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n;
-assign k7ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n;
-assign k7ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata;
-assign k7ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en;
-assign k7ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask;
-assign k7ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en;
-assign litedramcore_master_p0_rddata = k7ddrphy_dfi_p0_rddata;
-assign litedramcore_master_p0_rddata_valid = k7ddrphy_dfi_p0_rddata_valid;
-assign k7ddrphy_dfi_p1_address = litedramcore_master_p1_address;
-assign k7ddrphy_dfi_p1_bank = litedramcore_master_p1_bank;
-assign k7ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n;
-assign k7ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n;
-assign k7ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n;
-assign k7ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n;
-assign k7ddrphy_dfi_p1_cke = litedramcore_master_p1_cke;
-assign k7ddrphy_dfi_p1_odt = litedramcore_master_p1_odt;
-assign k7ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n;
-assign k7ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n;
-assign k7ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata;
-assign k7ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en;
-assign k7ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask;
-assign k7ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en;
-assign litedramcore_master_p1_rddata = k7ddrphy_dfi_p1_rddata;
-assign litedramcore_master_p1_rddata_valid = k7ddrphy_dfi_p1_rddata_valid;
-assign k7ddrphy_dfi_p2_address = litedramcore_master_p2_address;
-assign k7ddrphy_dfi_p2_bank = litedramcore_master_p2_bank;
-assign k7ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n;
-assign k7ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n;
-assign k7ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n;
-assign k7ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n;
-assign k7ddrphy_dfi_p2_cke = litedramcore_master_p2_cke;
-assign k7ddrphy_dfi_p2_odt = litedramcore_master_p2_odt;
-assign k7ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n;
-assign k7ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n;
-assign k7ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata;
-assign k7ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en;
-assign k7ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask;
-assign k7ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en;
-assign litedramcore_master_p2_rddata = k7ddrphy_dfi_p2_rddata;
-assign litedramcore_master_p2_rddata_valid = k7ddrphy_dfi_p2_rddata_valid;
-assign k7ddrphy_dfi_p3_address = litedramcore_master_p3_address;
-assign k7ddrphy_dfi_p3_bank = litedramcore_master_p3_bank;
-assign k7ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n;
-assign k7ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n;
-assign k7ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n;
-assign k7ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n;
-assign k7ddrphy_dfi_p3_cke = litedramcore_master_p3_cke;
-assign k7ddrphy_dfi_p3_odt = litedramcore_master_p3_odt;
-assign k7ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n;
-assign k7ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n;
-assign k7ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata;
-assign k7ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en;
-assign k7ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask;
-assign k7ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en;
-assign litedramcore_master_p3_rddata = k7ddrphy_dfi_p3_rddata;
-assign litedramcore_master_p3_rddata_valid = k7ddrphy_dfi_p3_rddata_valid;
-assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address;
-assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank;
-assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n;
-assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n;
-assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n;
-assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n;
-assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke;
-assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt;
-assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n;
-assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n;
-assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata;
-assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en;
-assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask;
-assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en;
-assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata;
-assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid;
-assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address;
-assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank;
-assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n;
-assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n;
-assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n;
-assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n;
-assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke;
-assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt;
-assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n;
-assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n;
-assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata;
-assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en;
-assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask;
-assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en;
-assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata;
-assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid;
-assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address;
-assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank;
-assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n;
-assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n;
-assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n;
-assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n;
-assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke;
-assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt;
-assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n;
-assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n;
-assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata;
-assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en;
-assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask;
-assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en;
-assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata;
-assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid;
-assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address;
-assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank;
-assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n;
-assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n;
-assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n;
-assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n;
-assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke;
-assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt;
-assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n;
-assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n;
-assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata;
-assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en;
-assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask;
-assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en;
-assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
-assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;
-always @(*) begin
-    litedramcore_csr_dfi_p0_rddata <= 64'd0;
-    if (litedramcore_sel) begin
+            main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[15:8];
+        end
+    endcase
+end
+assign main_k7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address;
+assign main_k7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank;
+assign main_k7ddrphy_dfi_p0_cas_n = main_litedramcore_master_p0_cas_n;
+assign main_k7ddrphy_dfi_p0_cs_n = main_litedramcore_master_p0_cs_n;
+assign main_k7ddrphy_dfi_p0_ras_n = main_litedramcore_master_p0_ras_n;
+assign main_k7ddrphy_dfi_p0_we_n = main_litedramcore_master_p0_we_n;
+assign main_k7ddrphy_dfi_p0_cke = main_litedramcore_master_p0_cke;
+assign main_k7ddrphy_dfi_p0_odt = main_litedramcore_master_p0_odt;
+assign main_k7ddrphy_dfi_p0_reset_n = main_litedramcore_master_p0_reset_n;
+assign main_k7ddrphy_dfi_p0_act_n = main_litedramcore_master_p0_act_n;
+assign main_k7ddrphy_dfi_p0_wrdata = main_litedramcore_master_p0_wrdata;
+assign main_k7ddrphy_dfi_p0_wrdata_en = main_litedramcore_master_p0_wrdata_en;
+assign main_k7ddrphy_dfi_p0_wrdata_mask = main_litedramcore_master_p0_wrdata_mask;
+assign main_k7ddrphy_dfi_p0_rddata_en = main_litedramcore_master_p0_rddata_en;
+assign main_litedramcore_master_p0_rddata = main_k7ddrphy_dfi_p0_rddata;
+assign main_litedramcore_master_p0_rddata_valid = main_k7ddrphy_dfi_p0_rddata_valid;
+assign main_k7ddrphy_dfi_p1_address = main_litedramcore_master_p1_address;
+assign main_k7ddrphy_dfi_p1_bank = main_litedramcore_master_p1_bank;
+assign main_k7ddrphy_dfi_p1_cas_n = main_litedramcore_master_p1_cas_n;
+assign main_k7ddrphy_dfi_p1_cs_n = main_litedramcore_master_p1_cs_n;
+assign main_k7ddrphy_dfi_p1_ras_n = main_litedramcore_master_p1_ras_n;
+assign main_k7ddrphy_dfi_p1_we_n = main_litedramcore_master_p1_we_n;
+assign main_k7ddrphy_dfi_p1_cke = main_litedramcore_master_p1_cke;
+assign main_k7ddrphy_dfi_p1_odt = main_litedramcore_master_p1_odt;
+assign main_k7ddrphy_dfi_p1_reset_n = main_litedramcore_master_p1_reset_n;
+assign main_k7ddrphy_dfi_p1_act_n = main_litedramcore_master_p1_act_n;
+assign main_k7ddrphy_dfi_p1_wrdata = main_litedramcore_master_p1_wrdata;
+assign main_k7ddrphy_dfi_p1_wrdata_en = main_litedramcore_master_p1_wrdata_en;
+assign main_k7ddrphy_dfi_p1_wrdata_mask = main_litedramcore_master_p1_wrdata_mask;
+assign main_k7ddrphy_dfi_p1_rddata_en = main_litedramcore_master_p1_rddata_en;
+assign main_litedramcore_master_p1_rddata = main_k7ddrphy_dfi_p1_rddata;
+assign main_litedramcore_master_p1_rddata_valid = main_k7ddrphy_dfi_p1_rddata_valid;
+assign main_k7ddrphy_dfi_p2_address = main_litedramcore_master_p2_address;
+assign main_k7ddrphy_dfi_p2_bank = main_litedramcore_master_p2_bank;
+assign main_k7ddrphy_dfi_p2_cas_n = main_litedramcore_master_p2_cas_n;
+assign main_k7ddrphy_dfi_p2_cs_n = main_litedramcore_master_p2_cs_n;
+assign main_k7ddrphy_dfi_p2_ras_n = main_litedramcore_master_p2_ras_n;
+assign main_k7ddrphy_dfi_p2_we_n = main_litedramcore_master_p2_we_n;
+assign main_k7ddrphy_dfi_p2_cke = main_litedramcore_master_p2_cke;
+assign main_k7ddrphy_dfi_p2_odt = main_litedramcore_master_p2_odt;
+assign main_k7ddrphy_dfi_p2_reset_n = main_litedramcore_master_p2_reset_n;
+assign main_k7ddrphy_dfi_p2_act_n = main_litedramcore_master_p2_act_n;
+assign main_k7ddrphy_dfi_p2_wrdata = main_litedramcore_master_p2_wrdata;
+assign main_k7ddrphy_dfi_p2_wrdata_en = main_litedramcore_master_p2_wrdata_en;
+assign main_k7ddrphy_dfi_p2_wrdata_mask = main_litedramcore_master_p2_wrdata_mask;
+assign main_k7ddrphy_dfi_p2_rddata_en = main_litedramcore_master_p2_rddata_en;
+assign main_litedramcore_master_p2_rddata = main_k7ddrphy_dfi_p2_rddata;
+assign main_litedramcore_master_p2_rddata_valid = main_k7ddrphy_dfi_p2_rddata_valid;
+assign main_k7ddrphy_dfi_p3_address = main_litedramcore_master_p3_address;
+assign main_k7ddrphy_dfi_p3_bank = main_litedramcore_master_p3_bank;
+assign main_k7ddrphy_dfi_p3_cas_n = main_litedramcore_master_p3_cas_n;
+assign main_k7ddrphy_dfi_p3_cs_n = main_litedramcore_master_p3_cs_n;
+assign main_k7ddrphy_dfi_p3_ras_n = main_litedramcore_master_p3_ras_n;
+assign main_k7ddrphy_dfi_p3_we_n = main_litedramcore_master_p3_we_n;
+assign main_k7ddrphy_dfi_p3_cke = main_litedramcore_master_p3_cke;
+assign main_k7ddrphy_dfi_p3_odt = main_litedramcore_master_p3_odt;
+assign main_k7ddrphy_dfi_p3_reset_n = main_litedramcore_master_p3_reset_n;
+assign main_k7ddrphy_dfi_p3_act_n = main_litedramcore_master_p3_act_n;
+assign main_k7ddrphy_dfi_p3_wrdata = main_litedramcore_master_p3_wrdata;
+assign main_k7ddrphy_dfi_p3_wrdata_en = main_litedramcore_master_p3_wrdata_en;
+assign main_k7ddrphy_dfi_p3_wrdata_mask = main_litedramcore_master_p3_wrdata_mask;
+assign main_k7ddrphy_dfi_p3_rddata_en = main_litedramcore_master_p3_rddata_en;
+assign main_litedramcore_master_p3_rddata = main_k7ddrphy_dfi_p3_rddata;
+assign main_litedramcore_master_p3_rddata_valid = main_k7ddrphy_dfi_p3_rddata_valid;
+assign main_litedramcore_slave_p0_address = main_litedramcore_dfi_p0_address;
+assign main_litedramcore_slave_p0_bank = main_litedramcore_dfi_p0_bank;
+assign main_litedramcore_slave_p0_cas_n = main_litedramcore_dfi_p0_cas_n;
+assign main_litedramcore_slave_p0_cs_n = main_litedramcore_dfi_p0_cs_n;
+assign main_litedramcore_slave_p0_ras_n = main_litedramcore_dfi_p0_ras_n;
+assign main_litedramcore_slave_p0_we_n = main_litedramcore_dfi_p0_we_n;
+assign main_litedramcore_slave_p0_cke = main_litedramcore_dfi_p0_cke;
+assign main_litedramcore_slave_p0_odt = main_litedramcore_dfi_p0_odt;
+assign main_litedramcore_slave_p0_reset_n = main_litedramcore_dfi_p0_reset_n;
+assign main_litedramcore_slave_p0_act_n = main_litedramcore_dfi_p0_act_n;
+assign main_litedramcore_slave_p0_wrdata = main_litedramcore_dfi_p0_wrdata;
+assign main_litedramcore_slave_p0_wrdata_en = main_litedramcore_dfi_p0_wrdata_en;
+assign main_litedramcore_slave_p0_wrdata_mask = main_litedramcore_dfi_p0_wrdata_mask;
+assign main_litedramcore_slave_p0_rddata_en = main_litedramcore_dfi_p0_rddata_en;
+assign main_litedramcore_dfi_p0_rddata = main_litedramcore_slave_p0_rddata;
+assign main_litedramcore_dfi_p0_rddata_valid = main_litedramcore_slave_p0_rddata_valid;
+assign main_litedramcore_slave_p1_address = main_litedramcore_dfi_p1_address;
+assign main_litedramcore_slave_p1_bank = main_litedramcore_dfi_p1_bank;
+assign main_litedramcore_slave_p1_cas_n = main_litedramcore_dfi_p1_cas_n;
+assign main_litedramcore_slave_p1_cs_n = main_litedramcore_dfi_p1_cs_n;
+assign main_litedramcore_slave_p1_ras_n = main_litedramcore_dfi_p1_ras_n;
+assign main_litedramcore_slave_p1_we_n = main_litedramcore_dfi_p1_we_n;
+assign main_litedramcore_slave_p1_cke = main_litedramcore_dfi_p1_cke;
+assign main_litedramcore_slave_p1_odt = main_litedramcore_dfi_p1_odt;
+assign main_litedramcore_slave_p1_reset_n = main_litedramcore_dfi_p1_reset_n;
+assign main_litedramcore_slave_p1_act_n = main_litedramcore_dfi_p1_act_n;
+assign main_litedramcore_slave_p1_wrdata = main_litedramcore_dfi_p1_wrdata;
+assign main_litedramcore_slave_p1_wrdata_en = main_litedramcore_dfi_p1_wrdata_en;
+assign main_litedramcore_slave_p1_wrdata_mask = main_litedramcore_dfi_p1_wrdata_mask;
+assign main_litedramcore_slave_p1_rddata_en = main_litedramcore_dfi_p1_rddata_en;
+assign main_litedramcore_dfi_p1_rddata = main_litedramcore_slave_p1_rddata;
+assign main_litedramcore_dfi_p1_rddata_valid = main_litedramcore_slave_p1_rddata_valid;
+assign main_litedramcore_slave_p2_address = main_litedramcore_dfi_p2_address;
+assign main_litedramcore_slave_p2_bank = main_litedramcore_dfi_p2_bank;
+assign main_litedramcore_slave_p2_cas_n = main_litedramcore_dfi_p2_cas_n;
+assign main_litedramcore_slave_p2_cs_n = main_litedramcore_dfi_p2_cs_n;
+assign main_litedramcore_slave_p2_ras_n = main_litedramcore_dfi_p2_ras_n;
+assign main_litedramcore_slave_p2_we_n = main_litedramcore_dfi_p2_we_n;
+assign main_litedramcore_slave_p2_cke = main_litedramcore_dfi_p2_cke;
+assign main_litedramcore_slave_p2_odt = main_litedramcore_dfi_p2_odt;
+assign main_litedramcore_slave_p2_reset_n = main_litedramcore_dfi_p2_reset_n;
+assign main_litedramcore_slave_p2_act_n = main_litedramcore_dfi_p2_act_n;
+assign main_litedramcore_slave_p2_wrdata = main_litedramcore_dfi_p2_wrdata;
+assign main_litedramcore_slave_p2_wrdata_en = main_litedramcore_dfi_p2_wrdata_en;
+assign main_litedramcore_slave_p2_wrdata_mask = main_litedramcore_dfi_p2_wrdata_mask;
+assign main_litedramcore_slave_p2_rddata_en = main_litedramcore_dfi_p2_rddata_en;
+assign main_litedramcore_dfi_p2_rddata = main_litedramcore_slave_p2_rddata;
+assign main_litedramcore_dfi_p2_rddata_valid = main_litedramcore_slave_p2_rddata_valid;
+assign main_litedramcore_slave_p3_address = main_litedramcore_dfi_p3_address;
+assign main_litedramcore_slave_p3_bank = main_litedramcore_dfi_p3_bank;
+assign main_litedramcore_slave_p3_cas_n = main_litedramcore_dfi_p3_cas_n;
+assign main_litedramcore_slave_p3_cs_n = main_litedramcore_dfi_p3_cs_n;
+assign main_litedramcore_slave_p3_ras_n = main_litedramcore_dfi_p3_ras_n;
+assign main_litedramcore_slave_p3_we_n = main_litedramcore_dfi_p3_we_n;
+assign main_litedramcore_slave_p3_cke = main_litedramcore_dfi_p3_cke;
+assign main_litedramcore_slave_p3_odt = main_litedramcore_dfi_p3_odt;
+assign main_litedramcore_slave_p3_reset_n = main_litedramcore_dfi_p3_reset_n;
+assign main_litedramcore_slave_p3_act_n = main_litedramcore_dfi_p3_act_n;
+assign main_litedramcore_slave_p3_wrdata = main_litedramcore_dfi_p3_wrdata;
+assign main_litedramcore_slave_p3_wrdata_en = main_litedramcore_dfi_p3_wrdata_en;
+assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_mask;
+assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en;
+assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata;
+assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid;
+always @(*) begin
+    main_litedramcore_csr_dfi_p0_rddata <= 64'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata;
+        main_litedramcore_csr_dfi_p0_rddata <= main_litedramcore_master_p0_rddata;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+        main_litedramcore_csr_dfi_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p1_rddata <= 64'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p1_rddata <= 64'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+        main_litedramcore_csr_dfi_p1_rddata <= main_litedramcore_master_p1_rddata;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+        main_litedramcore_csr_dfi_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p2_rddata <= 64'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p2_rddata <= 64'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata;
+        main_litedramcore_csr_dfi_p2_rddata <= main_litedramcore_master_p2_rddata;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+        main_litedramcore_csr_dfi_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p3_rddata <= 64'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p3_rddata <= 64'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata;
+        main_litedramcore_csr_dfi_p3_rddata <= main_litedramcore_master_p3_rddata;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+        main_litedramcore_csr_dfi_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p0_rddata <= 64'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata;
+    main_litedramcore_ext_dfi_p0_rddata <= 64'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p0_rddata <= main_litedramcore_master_p0_rddata;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+    main_litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p1_rddata <= 64'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+    main_litedramcore_ext_dfi_p1_rddata <= 64'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p1_rddata <= main_litedramcore_master_p1_rddata;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+    main_litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p2_rddata <= 64'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata;
+    main_litedramcore_ext_dfi_p2_rddata <= 64'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p2_rddata <= main_litedramcore_master_p2_rddata;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+    main_litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p0_rddata <= 64'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p0_rddata <= 64'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
+            main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p0_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p0_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+            main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p3_rddata <= 64'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata;
+    main_litedramcore_ext_dfi_p3_rddata <= 64'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p3_rddata <= main_litedramcore_master_p3_rddata;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+    main_litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p1_rddata <= 64'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p1_rddata <= 64'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
+            main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p1_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p1_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+            main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p2_rddata <= 64'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p2_rddata <= 64'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
+            main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p2_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p2_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+            main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p3_rddata <= 64'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p3_rddata <= 64'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
+            main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p3_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p3_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+            main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_master_p0_address <= 15'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address;
+    main_litedramcore_master_p0_address <= 15'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_address <= main_litedramcore_ext_dfi_p0_address;
         end else begin
-            litedramcore_master_p0_address <= litedramcore_slave_p0_address;
+            main_litedramcore_master_p0_address <= main_litedramcore_slave_p0_address;
         end
     end else begin
-        litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address;
+        main_litedramcore_master_p0_address <= main_litedramcore_csr_dfi_p0_address;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_bank <= 3'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank;
+    main_litedramcore_master_p0_bank <= 3'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_bank <= main_litedramcore_ext_dfi_p0_bank;
         end else begin
-            litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
+            main_litedramcore_master_p0_bank <= main_litedramcore_slave_p0_bank;
         end
     end else begin
-        litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank;
+        main_litedramcore_master_p0_bank <= main_litedramcore_csr_dfi_p0_bank;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_cas_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n;
+    main_litedramcore_master_p0_cas_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_cas_n <= main_litedramcore_ext_dfi_p0_cas_n;
         end else begin
-            litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
+            main_litedramcore_master_p0_cas_n <= main_litedramcore_slave_p0_cas_n;
         end
     end else begin
-        litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n;
+        main_litedramcore_master_p0_cas_n <= main_litedramcore_csr_dfi_p0_cas_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_cs_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
+    main_litedramcore_master_p0_cs_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_cs_n <= main_litedramcore_ext_dfi_p0_cs_n;
         end else begin
-            litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+            main_litedramcore_master_p0_cs_n <= main_litedramcore_slave_p0_cs_n;
+            if (1'd0) begin
+                main_litedramcore_master_p0_cs_n <= {2{main_litedramcore_slave_p0_cs_n}};
+            end
         end
     end else begin
-        litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
+        main_litedramcore_master_p0_cs_n <= main_litedramcore_csr_dfi_p0_cs_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_ras_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
+    main_litedramcore_master_p0_ras_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_ras_n <= main_litedramcore_ext_dfi_p0_ras_n;
         end else begin
-            litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+            main_litedramcore_master_p0_ras_n <= main_litedramcore_slave_p0_ras_n;
         end
     end else begin
-        litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
+        main_litedramcore_master_p0_ras_n <= main_litedramcore_csr_dfi_p0_ras_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_we_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
+    main_litedramcore_master_p0_we_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_we_n <= main_litedramcore_ext_dfi_p0_we_n;
         end else begin
-            litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+            main_litedramcore_master_p0_we_n <= main_litedramcore_slave_p0_we_n;
         end
     end else begin
-        litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
+        main_litedramcore_master_p0_we_n <= main_litedramcore_csr_dfi_p0_we_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_cke <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke;
+    main_litedramcore_master_p0_cke <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_cke <= main_litedramcore_ext_dfi_p0_cke;
         end else begin
-            litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
+            main_litedramcore_master_p0_cke <= main_litedramcore_slave_p0_cke;
         end
     end else begin
-        litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke;
+        main_litedramcore_master_p0_cke <= main_litedramcore_csr_dfi_p0_cke;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_odt <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt;
+    main_litedramcore_master_p0_odt <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_odt <= main_litedramcore_ext_dfi_p0_odt;
         end else begin
-            litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
+            main_litedramcore_master_p0_odt <= main_litedramcore_slave_p0_odt;
         end
     end else begin
-        litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt;
+        main_litedramcore_master_p0_odt <= main_litedramcore_csr_dfi_p0_odt;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_reset_n <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n;
+    main_litedramcore_master_p0_reset_n <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_reset_n <= main_litedramcore_ext_dfi_p0_reset_n;
         end else begin
-            litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
+            main_litedramcore_master_p0_reset_n <= main_litedramcore_slave_p0_reset_n;
         end
     end else begin
-        litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n;
+        main_litedramcore_master_p0_reset_n <= main_litedramcore_csr_dfi_p0_reset_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_act_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n;
+    main_litedramcore_master_p0_act_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_act_n <= main_litedramcore_ext_dfi_p0_act_n;
         end else begin
-            litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
+            main_litedramcore_master_p0_act_n <= main_litedramcore_slave_p0_act_n;
         end
     end else begin
-        litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n;
+        main_litedramcore_master_p0_act_n <= main_litedramcore_csr_dfi_p0_act_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_wrdata <= 64'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata;
+    main_litedramcore_master_p0_wrdata <= 64'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_wrdata <= main_litedramcore_ext_dfi_p0_wrdata;
         end else begin
-            litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
+            main_litedramcore_master_p0_wrdata <= main_litedramcore_slave_p0_wrdata;
         end
     end else begin
-        litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata;
+        main_litedramcore_master_p0_wrdata <= main_litedramcore_csr_dfi_p0_wrdata;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_wrdata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en;
+    main_litedramcore_master_p0_wrdata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_wrdata_en <= main_litedramcore_ext_dfi_p0_wrdata_en;
         end else begin
-            litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
+            main_litedramcore_master_p0_wrdata_en <= main_litedramcore_slave_p0_wrdata_en;
         end
     end else begin
-        litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en;
+        main_litedramcore_master_p0_wrdata_en <= main_litedramcore_csr_dfi_p0_wrdata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_wrdata_mask <= 8'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask;
+    main_litedramcore_master_p0_wrdata_mask <= 8'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_ext_dfi_p0_wrdata_mask;
         end else begin
-            litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
+            main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_slave_p0_wrdata_mask;
         end
     end else begin
-        litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask;
+        main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_csr_dfi_p0_wrdata_mask;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_rddata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en;
+    main_litedramcore_master_p0_rddata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_rddata_en <= main_litedramcore_ext_dfi_p0_rddata_en;
         end else begin
-            litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
+            main_litedramcore_master_p0_rddata_en <= main_litedramcore_slave_p0_rddata_en;
         end
     end else begin
-        litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en;
+        main_litedramcore_master_p0_rddata_en <= main_litedramcore_csr_dfi_p0_rddata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_address <= 15'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address;
+    main_litedramcore_master_p1_address <= 15'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_address <= main_litedramcore_ext_dfi_p1_address;
         end else begin
-            litedramcore_master_p1_address <= litedramcore_slave_p1_address;
+            main_litedramcore_master_p1_address <= main_litedramcore_slave_p1_address;
         end
     end else begin
-        litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address;
+        main_litedramcore_master_p1_address <= main_litedramcore_csr_dfi_p1_address;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_bank <= 3'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank;
+    main_litedramcore_master_p1_bank <= 3'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_bank <= main_litedramcore_ext_dfi_p1_bank;
         end else begin
-            litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
+            main_litedramcore_master_p1_bank <= main_litedramcore_slave_p1_bank;
         end
     end else begin
-        litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank;
+        main_litedramcore_master_p1_bank <= main_litedramcore_csr_dfi_p1_bank;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_cas_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n;
+    main_litedramcore_master_p1_cas_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_cas_n <= main_litedramcore_ext_dfi_p1_cas_n;
         end else begin
-            litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
+            main_litedramcore_master_p1_cas_n <= main_litedramcore_slave_p1_cas_n;
         end
     end else begin
-        litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n;
+        main_litedramcore_master_p1_cas_n <= main_litedramcore_csr_dfi_p1_cas_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_cs_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n;
+    main_litedramcore_master_p1_cs_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_cs_n <= main_litedramcore_ext_dfi_p1_cs_n;
         end else begin
-            litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
+            main_litedramcore_master_p1_cs_n <= main_litedramcore_slave_p1_cs_n;
+            if (1'd0) begin
+                main_litedramcore_master_p1_cs_n <= {2{main_litedramcore_slave_p1_cs_n}};
+            end
         end
     end else begin
-        litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n;
+        main_litedramcore_master_p1_cs_n <= main_litedramcore_csr_dfi_p1_cs_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_ras_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n;
+    main_litedramcore_master_p1_ras_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_ras_n <= main_litedramcore_ext_dfi_p1_ras_n;
         end else begin
-            litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
+            main_litedramcore_master_p1_ras_n <= main_litedramcore_slave_p1_ras_n;
         end
     end else begin
-        litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n;
+        main_litedramcore_master_p1_ras_n <= main_litedramcore_csr_dfi_p1_ras_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_we_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n;
+    main_litedramcore_master_p1_we_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_we_n <= main_litedramcore_ext_dfi_p1_we_n;
         end else begin
-            litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
+            main_litedramcore_master_p1_we_n <= main_litedramcore_slave_p1_we_n;
         end
     end else begin
-        litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n;
+        main_litedramcore_master_p1_we_n <= main_litedramcore_csr_dfi_p1_we_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_cke <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke;
+    main_litedramcore_master_p1_cke <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_cke <= main_litedramcore_ext_dfi_p1_cke;
         end else begin
-            litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
+            main_litedramcore_master_p1_cke <= main_litedramcore_slave_p1_cke;
         end
     end else begin
-        litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke;
+        main_litedramcore_master_p1_cke <= main_litedramcore_csr_dfi_p1_cke;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_odt <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt;
+    main_litedramcore_master_p1_odt <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_odt <= main_litedramcore_ext_dfi_p1_odt;
         end else begin
-            litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
+            main_litedramcore_master_p1_odt <= main_litedramcore_slave_p1_odt;
         end
     end else begin
-        litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt;
+        main_litedramcore_master_p1_odt <= main_litedramcore_csr_dfi_p1_odt;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_reset_n <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n;
+    main_litedramcore_master_p1_reset_n <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_reset_n <= main_litedramcore_ext_dfi_p1_reset_n;
         end else begin
-            litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+            main_litedramcore_master_p1_reset_n <= main_litedramcore_slave_p1_reset_n;
         end
     end else begin
-        litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n;
+        main_litedramcore_master_p1_reset_n <= main_litedramcore_csr_dfi_p1_reset_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_act_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n;
+    main_litedramcore_master_p1_act_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_act_n <= main_litedramcore_ext_dfi_p1_act_n;
         end else begin
-            litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
+            main_litedramcore_master_p1_act_n <= main_litedramcore_slave_p1_act_n;
         end
     end else begin
-        litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n;
+        main_litedramcore_master_p1_act_n <= main_litedramcore_csr_dfi_p1_act_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_wrdata <= 64'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata;
+    main_litedramcore_master_p1_wrdata <= 64'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_wrdata <= main_litedramcore_ext_dfi_p1_wrdata;
         end else begin
-            litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
+            main_litedramcore_master_p1_wrdata <= main_litedramcore_slave_p1_wrdata;
         end
     end else begin
-        litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata;
+        main_litedramcore_master_p1_wrdata <= main_litedramcore_csr_dfi_p1_wrdata;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_wrdata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en;
+    main_litedramcore_master_p1_wrdata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_wrdata_en <= main_litedramcore_ext_dfi_p1_wrdata_en;
         end else begin
-            litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
+            main_litedramcore_master_p1_wrdata_en <= main_litedramcore_slave_p1_wrdata_en;
         end
     end else begin
-        litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en;
+        main_litedramcore_master_p1_wrdata_en <= main_litedramcore_csr_dfi_p1_wrdata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_wrdata_mask <= 8'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask;
+    main_litedramcore_master_p1_wrdata_mask <= 8'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_ext_dfi_p1_wrdata_mask;
         end else begin
-            litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
+            main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_slave_p1_wrdata_mask;
         end
     end else begin
-        litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask;
+        main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_csr_dfi_p1_wrdata_mask;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_rddata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en;
+    main_litedramcore_master_p1_rddata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_rddata_en <= main_litedramcore_ext_dfi_p1_rddata_en;
         end else begin
-            litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
+            main_litedramcore_master_p1_rddata_en <= main_litedramcore_slave_p1_rddata_en;
         end
     end else begin
-        litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en;
+        main_litedramcore_master_p1_rddata_en <= main_litedramcore_csr_dfi_p1_rddata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_address <= 15'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address;
+    main_litedramcore_master_p2_address <= 15'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_address <= main_litedramcore_ext_dfi_p2_address;
         end else begin
-            litedramcore_master_p2_address <= litedramcore_slave_p2_address;
+            main_litedramcore_master_p2_address <= main_litedramcore_slave_p2_address;
         end
     end else begin
-        litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address;
+        main_litedramcore_master_p2_address <= main_litedramcore_csr_dfi_p2_address;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_bank <= 3'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank;
+    main_litedramcore_master_p2_bank <= 3'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_bank <= main_litedramcore_ext_dfi_p2_bank;
         end else begin
-            litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
+            main_litedramcore_master_p2_bank <= main_litedramcore_slave_p2_bank;
         end
     end else begin
-        litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank;
+        main_litedramcore_master_p2_bank <= main_litedramcore_csr_dfi_p2_bank;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_cas_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n;
+    main_litedramcore_master_p2_cas_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_cas_n <= main_litedramcore_ext_dfi_p2_cas_n;
         end else begin
-            litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
+            main_litedramcore_master_p2_cas_n <= main_litedramcore_slave_p2_cas_n;
         end
     end else begin
-        litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n;
+        main_litedramcore_master_p2_cas_n <= main_litedramcore_csr_dfi_p2_cas_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_cs_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n;
+    main_litedramcore_master_p2_cs_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_cs_n <= main_litedramcore_ext_dfi_p2_cs_n;
         end else begin
-            litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
+            main_litedramcore_master_p2_cs_n <= main_litedramcore_slave_p2_cs_n;
+            if (1'd0) begin
+                main_litedramcore_master_p2_cs_n <= {2{main_litedramcore_slave_p2_cs_n}};
+            end
         end
     end else begin
-        litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n;
+        main_litedramcore_master_p2_cs_n <= main_litedramcore_csr_dfi_p2_cs_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_ras_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n;
+    main_litedramcore_master_p2_ras_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_ras_n <= main_litedramcore_ext_dfi_p2_ras_n;
         end else begin
-            litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
+            main_litedramcore_master_p2_ras_n <= main_litedramcore_slave_p2_ras_n;
         end
     end else begin
-        litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n;
+        main_litedramcore_master_p2_ras_n <= main_litedramcore_csr_dfi_p2_ras_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_we_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n;
+    main_litedramcore_master_p2_we_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_we_n <= main_litedramcore_ext_dfi_p2_we_n;
         end else begin
-            litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
+            main_litedramcore_master_p2_we_n <= main_litedramcore_slave_p2_we_n;
         end
     end else begin
-        litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n;
+        main_litedramcore_master_p2_we_n <= main_litedramcore_csr_dfi_p2_we_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_cke <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke;
+    main_litedramcore_master_p2_cke <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_cke <= main_litedramcore_ext_dfi_p2_cke;
         end else begin
-            litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
+            main_litedramcore_master_p2_cke <= main_litedramcore_slave_p2_cke;
         end
     end else begin
-        litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke;
+        main_litedramcore_master_p2_cke <= main_litedramcore_csr_dfi_p2_cke;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_odt <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt;
+    main_litedramcore_master_p2_odt <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_odt <= main_litedramcore_ext_dfi_p2_odt;
         end else begin
-            litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
+            main_litedramcore_master_p2_odt <= main_litedramcore_slave_p2_odt;
         end
     end else begin
-        litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt;
+        main_litedramcore_master_p2_odt <= main_litedramcore_csr_dfi_p2_odt;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_reset_n <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n;
+    main_litedramcore_master_p2_reset_n <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_reset_n <= main_litedramcore_ext_dfi_p2_reset_n;
         end else begin
-            litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
+            main_litedramcore_master_p2_reset_n <= main_litedramcore_slave_p2_reset_n;
         end
     end else begin
-        litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n;
+        main_litedramcore_master_p2_reset_n <= main_litedramcore_csr_dfi_p2_reset_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_act_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n;
+    main_litedramcore_master_p2_act_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_act_n <= main_litedramcore_ext_dfi_p2_act_n;
         end else begin
-            litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
+            main_litedramcore_master_p2_act_n <= main_litedramcore_slave_p2_act_n;
         end
     end else begin
-        litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n;
+        main_litedramcore_master_p2_act_n <= main_litedramcore_csr_dfi_p2_act_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_wrdata <= 64'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata;
+    main_litedramcore_master_p2_wrdata <= 64'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_wrdata <= main_litedramcore_ext_dfi_p2_wrdata;
         end else begin
-            litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
+            main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata;
         end
     end else begin
-        litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata;
+        main_litedramcore_master_p2_wrdata <= main_litedramcore_csr_dfi_p2_wrdata;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_wrdata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en;
+    main_litedramcore_master_p2_wrdata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_wrdata_en <= main_litedramcore_ext_dfi_p2_wrdata_en;
         end else begin
-            litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
+            main_litedramcore_master_p2_wrdata_en <= main_litedramcore_slave_p2_wrdata_en;
         end
     end else begin
-        litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en;
+        main_litedramcore_master_p2_wrdata_en <= main_litedramcore_csr_dfi_p2_wrdata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_wrdata_mask <= 8'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask;
+    main_litedramcore_master_p2_wrdata_mask <= 8'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_ext_dfi_p2_wrdata_mask;
         end else begin
-            litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
+            main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_slave_p2_wrdata_mask;
         end
     end else begin
-        litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask;
+        main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_csr_dfi_p2_wrdata_mask;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_rddata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en;
+    main_litedramcore_master_p2_rddata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_rddata_en <= main_litedramcore_ext_dfi_p2_rddata_en;
         end else begin
-            litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
+            main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en;
         end
     end else begin
-        litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en;
+        main_litedramcore_master_p2_rddata_en <= main_litedramcore_csr_dfi_p2_rddata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_address <= 15'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address;
+    main_litedramcore_master_p3_address <= 15'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_address <= main_litedramcore_ext_dfi_p3_address;
         end else begin
-            litedramcore_master_p3_address <= litedramcore_slave_p3_address;
+            main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address;
         end
     end else begin
-        litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address;
+        main_litedramcore_master_p3_address <= main_litedramcore_csr_dfi_p3_address;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_bank <= 3'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank;
+    main_litedramcore_master_p3_bank <= 3'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_bank <= main_litedramcore_ext_dfi_p3_bank;
         end else begin
-            litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
+            main_litedramcore_master_p3_bank <= main_litedramcore_slave_p3_bank;
         end
     end else begin
-        litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank;
+        main_litedramcore_master_p3_bank <= main_litedramcore_csr_dfi_p3_bank;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_cas_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n;
+    main_litedramcore_master_p3_cas_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_cas_n <= main_litedramcore_ext_dfi_p3_cas_n;
         end else begin
-            litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
+            main_litedramcore_master_p3_cas_n <= main_litedramcore_slave_p3_cas_n;
         end
     end else begin
-        litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n;
+        main_litedramcore_master_p3_cas_n <= main_litedramcore_csr_dfi_p3_cas_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_cs_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n;
+    main_litedramcore_master_p3_cs_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_cs_n <= main_litedramcore_ext_dfi_p3_cs_n;
         end else begin
-            litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
+            main_litedramcore_master_p3_cs_n <= main_litedramcore_slave_p3_cs_n;
+            if (1'd0) begin
+                main_litedramcore_master_p3_cs_n <= {2{main_litedramcore_slave_p3_cs_n}};
+            end
         end
     end else begin
-        litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n;
+        main_litedramcore_master_p3_cs_n <= main_litedramcore_csr_dfi_p3_cs_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_ras_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n;
+    main_litedramcore_master_p3_ras_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_ras_n <= main_litedramcore_ext_dfi_p3_ras_n;
         end else begin
-            litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
+            main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n;
         end
     end else begin
-        litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n;
+        main_litedramcore_master_p3_ras_n <= main_litedramcore_csr_dfi_p3_ras_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_we_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n;
+    main_litedramcore_master_p3_we_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_we_n <= main_litedramcore_ext_dfi_p3_we_n;
         end else begin
-            litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
+            main_litedramcore_master_p3_we_n <= main_litedramcore_slave_p3_we_n;
         end
     end else begin
-        litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n;
+        main_litedramcore_master_p3_we_n <= main_litedramcore_csr_dfi_p3_we_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_cke <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke;
+    main_litedramcore_master_p3_cke <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_cke <= main_litedramcore_ext_dfi_p3_cke;
         end else begin
-            litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
+            main_litedramcore_master_p3_cke <= main_litedramcore_slave_p3_cke;
         end
     end else begin
-        litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke;
+        main_litedramcore_master_p3_cke <= main_litedramcore_csr_dfi_p3_cke;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_odt <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt;
+    main_litedramcore_master_p3_odt <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_odt <= main_litedramcore_ext_dfi_p3_odt;
         end else begin
-            litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
+            main_litedramcore_master_p3_odt <= main_litedramcore_slave_p3_odt;
         end
     end else begin
-        litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt;
+        main_litedramcore_master_p3_odt <= main_litedramcore_csr_dfi_p3_odt;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_reset_n <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n;
+    main_litedramcore_master_p3_reset_n <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_reset_n <= main_litedramcore_ext_dfi_p3_reset_n;
         end else begin
-            litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
+            main_litedramcore_master_p3_reset_n <= main_litedramcore_slave_p3_reset_n;
         end
     end else begin
-        litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n;
+        main_litedramcore_master_p3_reset_n <= main_litedramcore_csr_dfi_p3_reset_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_act_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n;
+    main_litedramcore_master_p3_act_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_act_n <= main_litedramcore_ext_dfi_p3_act_n;
         end else begin
-            litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
+            main_litedramcore_master_p3_act_n <= main_litedramcore_slave_p3_act_n;
         end
     end else begin
-        litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n;
+        main_litedramcore_master_p3_act_n <= main_litedramcore_csr_dfi_p3_act_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_wrdata <= 64'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata;
+    main_litedramcore_master_p3_wrdata <= 64'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_wrdata <= main_litedramcore_ext_dfi_p3_wrdata;
         end else begin
-            litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
+            main_litedramcore_master_p3_wrdata <= main_litedramcore_slave_p3_wrdata;
         end
     end else begin
-        litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata;
+        main_litedramcore_master_p3_wrdata <= main_litedramcore_csr_dfi_p3_wrdata;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_wrdata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en;
+    main_litedramcore_master_p3_wrdata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_wrdata_en <= main_litedramcore_ext_dfi_p3_wrdata_en;
         end else begin
-            litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
+            main_litedramcore_master_p3_wrdata_en <= main_litedramcore_slave_p3_wrdata_en;
         end
     end else begin
-        litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en;
+        main_litedramcore_master_p3_wrdata_en <= main_litedramcore_csr_dfi_p3_wrdata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_wrdata_mask <= 8'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask;
+    main_litedramcore_master_p3_wrdata_mask <= 8'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_ext_dfi_p3_wrdata_mask;
         end else begin
-            litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
+            main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_slave_p3_wrdata_mask;
         end
     end else begin
-        litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask;
+        main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_csr_dfi_p3_wrdata_mask;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_rddata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en;
+    main_litedramcore_master_p3_rddata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_rddata_en <= main_litedramcore_ext_dfi_p3_rddata_en;
         end else begin
-            litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
+            main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en;
         end
     end else begin
-        litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en;
-    end
-end
-assign litedramcore_csr_dfi_p0_cke = litedramcore_cke;
-assign litedramcore_csr_dfi_p1_cke = litedramcore_cke;
-assign litedramcore_csr_dfi_p2_cke = litedramcore_cke;
-assign litedramcore_csr_dfi_p3_cke = litedramcore_cke;
-assign litedramcore_csr_dfi_p0_odt = litedramcore_odt;
-assign litedramcore_csr_dfi_p1_odt = litedramcore_odt;
-assign litedramcore_csr_dfi_p2_odt = litedramcore_odt;
-assign litedramcore_csr_dfi_p3_odt = litedramcore_odt;
-assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n;
-assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n;
-assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n;
-assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n;
-always @(*) begin
-    litedramcore_csr_dfi_p0_cs_n <= 1'd1;
-    if (litedramcore_phaseinjector0_command_issue_re) begin
-        litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}};
+        main_litedramcore_master_p3_rddata_en <= main_litedramcore_csr_dfi_p3_rddata_en;
+    end
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p0_cke <= 1'd0;
+    main_litedramcore_csr_dfi_p0_cke <= main_litedramcore_cke;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p1_cke <= 1'd0;
+    main_litedramcore_csr_dfi_p1_cke <= main_litedramcore_cke;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p2_cke <= 1'd0;
+    main_litedramcore_csr_dfi_p2_cke <= main_litedramcore_cke;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p3_cke <= 1'd0;
+    main_litedramcore_csr_dfi_p3_cke <= main_litedramcore_cke;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p0_odt <= 1'd0;
+    main_litedramcore_csr_dfi_p0_odt <= main_litedramcore_odt;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p1_odt <= 1'd0;
+    main_litedramcore_csr_dfi_p1_odt <= main_litedramcore_odt;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p2_odt <= 1'd0;
+    main_litedramcore_csr_dfi_p2_odt <= main_litedramcore_odt;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p3_odt <= 1'd0;
+    main_litedramcore_csr_dfi_p3_odt <= main_litedramcore_odt;
+end
+assign main_litedramcore_csr_dfi_p0_reset_n = main_litedramcore_reset_n;
+assign main_litedramcore_csr_dfi_p1_reset_n = main_litedramcore_reset_n;
+assign main_litedramcore_csr_dfi_p2_reset_n = main_litedramcore_reset_n;
+assign main_litedramcore_csr_dfi_p3_reset_n = main_litedramcore_reset_n;
+always @(*) begin
+    main_litedramcore_csr_dfi_p0_cs_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        if (main_litedramcore_phaseinjector0_csrfield_cs_top) begin
+            main_litedramcore_csr_dfi_p0_cs_n <= 2'd2;
+        end else begin
+            if (main_litedramcore_phaseinjector0_csrfield_cs_bottom) begin
+                main_litedramcore_csr_dfi_p0_cs_n <= 1'd1;
+            end else begin
+                main_litedramcore_csr_dfi_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_csrfield_cs)}};
+            end
+        end
     end else begin
-        litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
+        main_litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p0_ras_n <= 1'd1;
-    if (litedramcore_phaseinjector0_command_issue_re) begin
-        litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras);
+    main_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        main_litedramcore_csr_dfi_p0_ras_n <= (~main_litedramcore_phaseinjector0_csrfield_ras);
     end else begin
-        litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+        main_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p0_we_n <= 1'd1;
-    if (litedramcore_phaseinjector0_command_issue_re) begin
-        litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
+    main_litedramcore_csr_dfi_p0_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        main_litedramcore_csr_dfi_p0_we_n <= (~main_litedramcore_phaseinjector0_csrfield_we);
     end else begin
-        litedramcore_csr_dfi_p0_we_n <= 1'd1;
+        main_litedramcore_csr_dfi_p0_we_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p0_cas_n <= 1'd1;
-    if (litedramcore_phaseinjector0_command_issue_re) begin
-        litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas);
+    main_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        main_litedramcore_csr_dfi_p0_cas_n <= (~main_litedramcore_phaseinjector0_csrfield_cas);
     end else begin
-        litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+        main_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
     end
 end
-assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage;
-assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage;
-assign litedramcore_csr_dfi_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_wren);
-assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_rden);
-assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
-assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
+assign main_litedramcore_csr_dfi_p0_address = main_litedramcore_phaseinjector0_address_storage;
+assign main_litedramcore_csr_dfi_p0_bank = main_litedramcore_phaseinjector0_baddress_storage;
+assign main_litedramcore_csr_dfi_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_wren);
+assign main_litedramcore_csr_dfi_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_rden);
+assign main_litedramcore_csr_dfi_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage;
+assign main_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
 always @(*) begin
-    litedramcore_csr_dfi_p1_cs_n <= 1'd1;
-    if (litedramcore_phaseinjector1_command_issue_re) begin
-        litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}};
+    main_litedramcore_csr_dfi_p1_cs_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        if (main_litedramcore_phaseinjector1_csrfield_cs_top) begin
+            main_litedramcore_csr_dfi_p1_cs_n <= 2'd2;
+        end else begin
+            if (main_litedramcore_phaseinjector1_csrfield_cs_bottom) begin
+                main_litedramcore_csr_dfi_p1_cs_n <= 1'd1;
+            end else begin
+                main_litedramcore_csr_dfi_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_csrfield_cs)}};
+            end
+        end
     end else begin
-        litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
+        main_litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p1_ras_n <= 1'd1;
-    if (litedramcore_phaseinjector1_command_issue_re) begin
-        litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras);
+    main_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        main_litedramcore_csr_dfi_p1_ras_n <= (~main_litedramcore_phaseinjector1_csrfield_ras);
     end else begin
-        litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+        main_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p1_we_n <= 1'd1;
-    if (litedramcore_phaseinjector1_command_issue_re) begin
-        litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
+    main_litedramcore_csr_dfi_p1_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        main_litedramcore_csr_dfi_p1_we_n <= (~main_litedramcore_phaseinjector1_csrfield_we);
     end else begin
-        litedramcore_csr_dfi_p1_we_n <= 1'd1;
+        main_litedramcore_csr_dfi_p1_we_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p1_cas_n <= 1'd1;
-    if (litedramcore_phaseinjector1_command_issue_re) begin
-        litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas);
+    main_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        main_litedramcore_csr_dfi_p1_cas_n <= (~main_litedramcore_phaseinjector1_csrfield_cas);
     end else begin
-        litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+        main_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
     end
 end
-assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage;
-assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage;
-assign litedramcore_csr_dfi_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_wren);
-assign litedramcore_csr_dfi_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_rden);
-assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
-assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
+assign main_litedramcore_csr_dfi_p1_address = main_litedramcore_phaseinjector1_address_storage;
+assign main_litedramcore_csr_dfi_p1_bank = main_litedramcore_phaseinjector1_baddress_storage;
+assign main_litedramcore_csr_dfi_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_wren);
+assign main_litedramcore_csr_dfi_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_rden);
+assign main_litedramcore_csr_dfi_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage;
+assign main_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
 always @(*) begin
-    litedramcore_csr_dfi_p2_cs_n <= 1'd1;
-    if (litedramcore_phaseinjector2_command_issue_re) begin
-        litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}};
+    main_litedramcore_csr_dfi_p2_cs_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        if (main_litedramcore_phaseinjector2_csrfield_cs_top) begin
+            main_litedramcore_csr_dfi_p2_cs_n <= 2'd2;
+        end else begin
+            if (main_litedramcore_phaseinjector2_csrfield_cs_bottom) begin
+                main_litedramcore_csr_dfi_p2_cs_n <= 1'd1;
+            end else begin
+                main_litedramcore_csr_dfi_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_csrfield_cs)}};
+            end
+        end
     end else begin
-        litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
+        main_litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p2_ras_n <= 1'd1;
-    if (litedramcore_phaseinjector2_command_issue_re) begin
-        litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras);
+    main_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        main_litedramcore_csr_dfi_p2_ras_n <= (~main_litedramcore_phaseinjector2_csrfield_ras);
     end else begin
-        litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+        main_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p2_we_n <= 1'd1;
-    if (litedramcore_phaseinjector2_command_issue_re) begin
-        litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we);
+    main_litedramcore_csr_dfi_p2_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        main_litedramcore_csr_dfi_p2_we_n <= (~main_litedramcore_phaseinjector2_csrfield_we);
     end else begin
-        litedramcore_csr_dfi_p2_we_n <= 1'd1;
+        main_litedramcore_csr_dfi_p2_we_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p2_cas_n <= 1'd1;
-    if (litedramcore_phaseinjector2_command_issue_re) begin
-        litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas);
+    main_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        main_litedramcore_csr_dfi_p2_cas_n <= (~main_litedramcore_phaseinjector2_csrfield_cas);
     end else begin
-        litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+        main_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
     end
 end
-assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage;
-assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage;
-assign litedramcore_csr_dfi_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_wren);
-assign litedramcore_csr_dfi_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_rden);
-assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
-assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
+assign main_litedramcore_csr_dfi_p2_address = main_litedramcore_phaseinjector2_address_storage;
+assign main_litedramcore_csr_dfi_p2_bank = main_litedramcore_phaseinjector2_baddress_storage;
+assign main_litedramcore_csr_dfi_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_wren);
+assign main_litedramcore_csr_dfi_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_rden);
+assign main_litedramcore_csr_dfi_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage;
+assign main_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
 always @(*) begin
-    litedramcore_csr_dfi_p3_cs_n <= 1'd1;
-    if (litedramcore_phaseinjector3_command_issue_re) begin
-        litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}};
+    main_litedramcore_csr_dfi_p3_cs_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        if (main_litedramcore_phaseinjector3_csrfield_cs_top) begin
+            main_litedramcore_csr_dfi_p3_cs_n <= 2'd2;
+        end else begin
+            if (main_litedramcore_phaseinjector3_csrfield_cs_bottom) begin
+                main_litedramcore_csr_dfi_p3_cs_n <= 1'd1;
+            end else begin
+                main_litedramcore_csr_dfi_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_csrfield_cs)}};
+            end
+        end
     end else begin
-        litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
+        main_litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p3_ras_n <= 1'd1;
-    if (litedramcore_phaseinjector3_command_issue_re) begin
-        litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras);
+    main_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        main_litedramcore_csr_dfi_p3_ras_n <= (~main_litedramcore_phaseinjector3_csrfield_ras);
     end else begin
-        litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+        main_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p3_we_n <= 1'd1;
-    if (litedramcore_phaseinjector3_command_issue_re) begin
-        litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we);
+    main_litedramcore_csr_dfi_p3_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        main_litedramcore_csr_dfi_p3_we_n <= (~main_litedramcore_phaseinjector3_csrfield_we);
     end else begin
-        litedramcore_csr_dfi_p3_we_n <= 1'd1;
+        main_litedramcore_csr_dfi_p3_we_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p3_cas_n <= 1'd1;
-    if (litedramcore_phaseinjector3_command_issue_re) begin
-        litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas);
+    main_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        main_litedramcore_csr_dfi_p3_cas_n <= (~main_litedramcore_phaseinjector3_csrfield_cas);
     end else begin
-        litedramcore_csr_dfi_p3_cas_n <= 1'd1;
-    end
-end
-assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage;
-assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage;
-assign litedramcore_csr_dfi_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_wren);
-assign litedramcore_csr_dfi_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_rden);
-assign litedramcore_csr_dfi_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage;
-assign litedramcore_csr_dfi_p3_wrdata_mask = 1'd0;
-assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid;
-assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready;
-assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we;
-assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr;
-assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock;
-assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready;
-assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid;
-assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid;
-assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready;
-assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we;
-assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr;
-assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock;
-assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready;
-assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid;
-assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid;
-assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready;
-assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we;
-assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr;
-assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock;
-assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready;
-assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid;
-assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid;
-assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready;
-assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we;
-assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr;
-assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock;
-assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready;
-assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid;
-assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid;
-assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready;
-assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we;
-assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr;
-assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock;
-assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready;
-assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid;
-assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid;
-assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready;
-assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we;
-assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr;
-assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock;
-assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready;
-assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid;
-assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid;
-assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready;
-assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we;
-assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr;
-assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock;
-assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready;
-assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid;
-assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid;
-assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready;
-assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we;
-assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr;
-assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock;
-assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready;
-assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid;
-assign litedramcore_timer_wait = (~litedramcore_timer_done0);
-assign litedramcore_postponer_req_i = litedramcore_timer_done0;
-assign litedramcore_wants_refresh = litedramcore_postponer_req_o;
-assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0;
-assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done);
-assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0);
-assign litedramcore_timer_done0 = litedramcore_timer_done1;
-assign litedramcore_timer_count0 = litedramcore_timer_count1;
-assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0));
-assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0));
-assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0);
-assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
-assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
-always @(*) begin
-    litedramcore_refresher_next_state <= 2'd0;
-    litedramcore_refresher_next_state <= litedramcore_refresher_state;
-    case (litedramcore_refresher_state)
-        1'd1: begin
-            if (litedramcore_cmd_ready) begin
-                litedramcore_refresher_next_state <= 2'd2;
-            end
-        end
-        2'd2: begin
-            if (litedramcore_sequencer_done0) begin
-                if (litedramcore_wants_zqcs) begin
-                    litedramcore_refresher_next_state <= 2'd3;
+        main_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+    end
+end
+assign main_litedramcore_csr_dfi_p3_address = main_litedramcore_phaseinjector3_address_storage;
+assign main_litedramcore_csr_dfi_p3_bank = main_litedramcore_phaseinjector3_baddress_storage;
+assign main_litedramcore_csr_dfi_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_wren);
+assign main_litedramcore_csr_dfi_p3_rddata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_rden);
+assign main_litedramcore_csr_dfi_p3_wrdata = main_litedramcore_phaseinjector3_wrdata_storage;
+assign main_litedramcore_csr_dfi_p3_wrdata_mask = 1'd0;
+assign main_litedramcore_bankmachine0_req_valid = main_litedramcore_interface_bank0_valid;
+assign main_litedramcore_interface_bank0_ready = main_litedramcore_bankmachine0_req_ready;
+assign main_litedramcore_bankmachine0_req_we = main_litedramcore_interface_bank0_we;
+assign main_litedramcore_bankmachine0_req_addr = main_litedramcore_interface_bank0_addr;
+assign main_litedramcore_interface_bank0_lock = main_litedramcore_bankmachine0_req_lock;
+assign main_litedramcore_interface_bank0_wdata_ready = main_litedramcore_bankmachine0_req_wdata_ready;
+assign main_litedramcore_interface_bank0_rdata_valid = main_litedramcore_bankmachine0_req_rdata_valid;
+assign main_litedramcore_bankmachine1_req_valid = main_litedramcore_interface_bank1_valid;
+assign main_litedramcore_interface_bank1_ready = main_litedramcore_bankmachine1_req_ready;
+assign main_litedramcore_bankmachine1_req_we = main_litedramcore_interface_bank1_we;
+assign main_litedramcore_bankmachine1_req_addr = main_litedramcore_interface_bank1_addr;
+assign main_litedramcore_interface_bank1_lock = main_litedramcore_bankmachine1_req_lock;
+assign main_litedramcore_interface_bank1_wdata_ready = main_litedramcore_bankmachine1_req_wdata_ready;
+assign main_litedramcore_interface_bank1_rdata_valid = main_litedramcore_bankmachine1_req_rdata_valid;
+assign main_litedramcore_bankmachine2_req_valid = main_litedramcore_interface_bank2_valid;
+assign main_litedramcore_interface_bank2_ready = main_litedramcore_bankmachine2_req_ready;
+assign main_litedramcore_bankmachine2_req_we = main_litedramcore_interface_bank2_we;
+assign main_litedramcore_bankmachine2_req_addr = main_litedramcore_interface_bank2_addr;
+assign main_litedramcore_interface_bank2_lock = main_litedramcore_bankmachine2_req_lock;
+assign main_litedramcore_interface_bank2_wdata_ready = main_litedramcore_bankmachine2_req_wdata_ready;
+assign main_litedramcore_interface_bank2_rdata_valid = main_litedramcore_bankmachine2_req_rdata_valid;
+assign main_litedramcore_bankmachine3_req_valid = main_litedramcore_interface_bank3_valid;
+assign main_litedramcore_interface_bank3_ready = main_litedramcore_bankmachine3_req_ready;
+assign main_litedramcore_bankmachine3_req_we = main_litedramcore_interface_bank3_we;
+assign main_litedramcore_bankmachine3_req_addr = main_litedramcore_interface_bank3_addr;
+assign main_litedramcore_interface_bank3_lock = main_litedramcore_bankmachine3_req_lock;
+assign main_litedramcore_interface_bank3_wdata_ready = main_litedramcore_bankmachine3_req_wdata_ready;
+assign main_litedramcore_interface_bank3_rdata_valid = main_litedramcore_bankmachine3_req_rdata_valid;
+assign main_litedramcore_bankmachine4_req_valid = main_litedramcore_interface_bank4_valid;
+assign main_litedramcore_interface_bank4_ready = main_litedramcore_bankmachine4_req_ready;
+assign main_litedramcore_bankmachine4_req_we = main_litedramcore_interface_bank4_we;
+assign main_litedramcore_bankmachine4_req_addr = main_litedramcore_interface_bank4_addr;
+assign main_litedramcore_interface_bank4_lock = main_litedramcore_bankmachine4_req_lock;
+assign main_litedramcore_interface_bank4_wdata_ready = main_litedramcore_bankmachine4_req_wdata_ready;
+assign main_litedramcore_interface_bank4_rdata_valid = main_litedramcore_bankmachine4_req_rdata_valid;
+assign main_litedramcore_bankmachine5_req_valid = main_litedramcore_interface_bank5_valid;
+assign main_litedramcore_interface_bank5_ready = main_litedramcore_bankmachine5_req_ready;
+assign main_litedramcore_bankmachine5_req_we = main_litedramcore_interface_bank5_we;
+assign main_litedramcore_bankmachine5_req_addr = main_litedramcore_interface_bank5_addr;
+assign main_litedramcore_interface_bank5_lock = main_litedramcore_bankmachine5_req_lock;
+assign main_litedramcore_interface_bank5_wdata_ready = main_litedramcore_bankmachine5_req_wdata_ready;
+assign main_litedramcore_interface_bank5_rdata_valid = main_litedramcore_bankmachine5_req_rdata_valid;
+assign main_litedramcore_bankmachine6_req_valid = main_litedramcore_interface_bank6_valid;
+assign main_litedramcore_interface_bank6_ready = main_litedramcore_bankmachine6_req_ready;
+assign main_litedramcore_bankmachine6_req_we = main_litedramcore_interface_bank6_we;
+assign main_litedramcore_bankmachine6_req_addr = main_litedramcore_interface_bank6_addr;
+assign main_litedramcore_interface_bank6_lock = main_litedramcore_bankmachine6_req_lock;
+assign main_litedramcore_interface_bank6_wdata_ready = main_litedramcore_bankmachine6_req_wdata_ready;
+assign main_litedramcore_interface_bank6_rdata_valid = main_litedramcore_bankmachine6_req_rdata_valid;
+assign main_litedramcore_bankmachine7_req_valid = main_litedramcore_interface_bank7_valid;
+assign main_litedramcore_interface_bank7_ready = main_litedramcore_bankmachine7_req_ready;
+assign main_litedramcore_bankmachine7_req_we = main_litedramcore_interface_bank7_we;
+assign main_litedramcore_bankmachine7_req_addr = main_litedramcore_interface_bank7_addr;
+assign main_litedramcore_interface_bank7_lock = main_litedramcore_bankmachine7_req_lock;
+assign main_litedramcore_interface_bank7_wdata_ready = main_litedramcore_bankmachine7_req_wdata_ready;
+assign main_litedramcore_interface_bank7_rdata_valid = main_litedramcore_bankmachine7_req_rdata_valid;
+assign main_litedramcore_timer_wait = (~main_litedramcore_timer_done0);
+assign main_litedramcore_postponer_req_i = main_litedramcore_timer_done0;
+assign main_litedramcore_wants_refresh = main_litedramcore_postponer_req_o;
+assign main_litedramcore_wants_zqcs = main_litedramcore_zqcs_timer_done0;
+assign main_litedramcore_zqcs_timer_wait = (~main_litedramcore_zqcs_executer_done);
+assign main_litedramcore_timer_done1 = (main_litedramcore_timer_count1 == 1'd0);
+assign main_litedramcore_timer_done0 = main_litedramcore_timer_done1;
+assign main_litedramcore_timer_count0 = main_litedramcore_timer_count1;
+assign main_litedramcore_sequencer_start1 = (main_litedramcore_sequencer_start0 | (main_litedramcore_sequencer_count != 1'd0));
+assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 & (main_litedramcore_sequencer_count == 1'd0));
+assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0);
+assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1;
+assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1;
+always @(*) begin
+    builder_refresher_next_state <= 2'd0;
+    builder_refresher_next_state <= builder_refresher_state;
+    case (builder_refresher_state)
+        1'd1: begin
+            if (main_litedramcore_cmd_ready) begin
+                builder_refresher_next_state <= 2'd2;
+            end
+        end
+        2'd2: begin
+            if (main_litedramcore_sequencer_done0) begin
+                if (main_litedramcore_wants_zqcs) begin
+                    builder_refresher_next_state <= 2'd3;
                 end else begin
-                    litedramcore_refresher_next_state <= 1'd0;
+                    builder_refresher_next_state <= 1'd0;
                 end
             end
         end
         2'd3: begin
-            if (litedramcore_zqcs_executer_done) begin
-                litedramcore_refresher_next_state <= 1'd0;
+            if (main_litedramcore_zqcs_executer_done) begin
+                builder_refresher_next_state <= 1'd0;
             end
         end
         default: begin
             if (1'd1) begin
-                if (litedramcore_wants_refresh) begin
-                    litedramcore_refresher_next_state <= 1'd1;
+                if (main_litedramcore_wants_refresh) begin
+                    builder_refresher_next_state <= 1'd1;
                 end
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_cmd_valid <= 1'd0;
-    case (litedramcore_refresher_state)
+    main_litedramcore_sequencer_start0 <= 1'd0;
+    case (builder_refresher_state)
         1'd1: begin
-            litedramcore_cmd_valid <= 1'd1;
+            if (main_litedramcore_cmd_ready) begin
+                main_litedramcore_sequencer_start0 <= 1'd1;
+            end
         end
         2'd2: begin
-            litedramcore_cmd_valid <= 1'd1;
-            if (litedramcore_sequencer_done0) begin
-                if (litedramcore_wants_zqcs) begin
-                end else begin
-                    litedramcore_cmd_valid <= 1'd0;
-                end
-            end
         end
         2'd3: begin
-            litedramcore_cmd_valid <= 1'd1;
-            if (litedramcore_zqcs_executer_done) begin
-                litedramcore_cmd_valid <= 1'd0;
-            end
         end
         default: begin
         end
     endcase
 end
 always @(*) begin
-    litedramcore_zqcs_executer_start <= 1'd0;
-    case (litedramcore_refresher_state)
+    main_litedramcore_cmd_valid <= 1'd0;
+    case (builder_refresher_state)
         1'd1: begin
+            main_litedramcore_cmd_valid <= 1'd1;
         end
         2'd2: begin
-            if (litedramcore_sequencer_done0) begin
-                if (litedramcore_wants_zqcs) begin
-                    litedramcore_zqcs_executer_start <= 1'd1;
+            main_litedramcore_cmd_valid <= 1'd1;
+            if (main_litedramcore_sequencer_done0) begin
+                if (main_litedramcore_wants_zqcs) begin
                 end else begin
+                    main_litedramcore_cmd_valid <= 1'd0;
                 end
             end
         end
         2'd3: begin
+            main_litedramcore_cmd_valid <= 1'd1;
+            if (main_litedramcore_zqcs_executer_done) begin
+                main_litedramcore_cmd_valid <= 1'd0;
+            end
         end
         default: begin
         end
     endcase
 end
 always @(*) begin
-    litedramcore_cmd_last <= 1'd0;
-    case (litedramcore_refresher_state)
+    main_litedramcore_zqcs_executer_start <= 1'd0;
+    case (builder_refresher_state)
         1'd1: begin
         end
         2'd2: begin
-            if (litedramcore_sequencer_done0) begin
-                if (litedramcore_wants_zqcs) begin
+            if (main_litedramcore_sequencer_done0) begin
+                if (main_litedramcore_wants_zqcs) begin
+                    main_litedramcore_zqcs_executer_start <= 1'd1;
                 end else begin
-                    litedramcore_cmd_last <= 1'd1;
                 end
             end
         end
         2'd3: begin
-            if (litedramcore_zqcs_executer_done) begin
-                litedramcore_cmd_last <= 1'd1;
-            end
         end
         default: begin
         end
     endcase
 end
 always @(*) begin
-    litedramcore_sequencer_start0 <= 1'd0;
-    case (litedramcore_refresher_state)
+    main_litedramcore_cmd_last <= 1'd0;
+    case (builder_refresher_state)
         1'd1: begin
-            if (litedramcore_cmd_ready) begin
-                litedramcore_sequencer_start0 <= 1'd1;
-            end
         end
         2'd2: begin
+            if (main_litedramcore_sequencer_done0) begin
+                if (main_litedramcore_wants_zqcs) begin
+                end else begin
+                    main_litedramcore_cmd_last <= 1'd1;
+                end
+            end
         end
         2'd3: begin
+            if (main_litedramcore_zqcs_executer_done) begin
+                main_litedramcore_cmd_last <= 1'd1;
+            end
         end
         default: begin
         end
     endcase
 end
-assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid;
-assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready;
-assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we;
-assign litedramcore_bankmachine0_sink_payload_addr = litedramcore_bankmachine0_req_addr;
-assign litedramcore_bankmachine0_sink_sink_valid = litedramcore_bankmachine0_source_valid;
-assign litedramcore_bankmachine0_source_ready = litedramcore_bankmachine0_sink_sink_ready;
-assign litedramcore_bankmachine0_sink_sink_first = litedramcore_bankmachine0_source_first;
-assign litedramcore_bankmachine0_sink_sink_last = litedramcore_bankmachine0_source_last;
-assign litedramcore_bankmachine0_sink_sink_payload_we = litedramcore_bankmachine0_source_payload_we;
-assign litedramcore_bankmachine0_sink_sink_payload_addr = litedramcore_bankmachine0_source_payload_addr;
-assign litedramcore_bankmachine0_source_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
-assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_source_valid | litedramcore_bankmachine0_source_source_valid);
-assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_source_source_payload_addr[21:7]);
-assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
-always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_a <= 15'd0;
-    if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
-        litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_source_source_payload_addr[21:7];
+assign main_litedramcore_bankmachine0_sink_valid = main_litedramcore_bankmachine0_req_valid;
+assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_sink_ready;
+assign main_litedramcore_bankmachine0_sink_payload_we = main_litedramcore_bankmachine0_req_we;
+assign main_litedramcore_bankmachine0_sink_payload_addr = main_litedramcore_bankmachine0_req_addr;
+assign main_litedramcore_bankmachine0_sink_sink_valid = main_litedramcore_bankmachine0_source_valid;
+assign main_litedramcore_bankmachine0_source_ready = main_litedramcore_bankmachine0_sink_sink_ready;
+assign main_litedramcore_bankmachine0_sink_sink_first = main_litedramcore_bankmachine0_source_first;
+assign main_litedramcore_bankmachine0_sink_sink_last = main_litedramcore_bankmachine0_source_last;
+assign main_litedramcore_bankmachine0_sink_sink_payload_we = main_litedramcore_bankmachine0_source_payload_we;
+assign main_litedramcore_bankmachine0_sink_sink_payload_addr = main_litedramcore_bankmachine0_source_payload_addr;
+assign main_litedramcore_bankmachine0_source_source_ready = (main_litedramcore_bankmachine0_req_wdata_ready | main_litedramcore_bankmachine0_req_rdata_valid);
+assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_source_valid | main_litedramcore_bankmachine0_source_source_valid);
+assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_source_source_payload_addr[21:7]);
+assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
+always @(*) begin
+    main_litedramcore_bankmachine0_cmd_payload_a <= 15'd0;
+    if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine0_cmd_payload_a <= main_litedramcore_bankmachine0_source_source_payload_addr[21:7];
     end else begin
-        litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
-assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
-assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
-always @(*) begin
-    litedramcore_bankmachine0_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine0_source_valid & litedramcore_bankmachine0_source_source_valid)) begin
-        if ((litedramcore_bankmachine0_source_payload_addr[21:7] != litedramcore_bankmachine0_source_source_payload_addr[21:7])) begin
-            litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine0_syncfifo0_din = {litedramcore_bankmachine0_fifo_in_last, litedramcore_bankmachine0_fifo_in_first, litedramcore_bankmachine0_fifo_in_payload_addr, litedramcore_bankmachine0_fifo_in_payload_we};
-assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
-assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
-assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
-assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
-assign litedramcore_bankmachine0_sink_ready = litedramcore_bankmachine0_syncfifo0_writable;
-assign litedramcore_bankmachine0_syncfifo0_we = litedramcore_bankmachine0_sink_valid;
-assign litedramcore_bankmachine0_fifo_in_first = litedramcore_bankmachine0_sink_first;
-assign litedramcore_bankmachine0_fifo_in_last = litedramcore_bankmachine0_sink_last;
-assign litedramcore_bankmachine0_fifo_in_payload_we = litedramcore_bankmachine0_sink_payload_we;
-assign litedramcore_bankmachine0_fifo_in_payload_addr = litedramcore_bankmachine0_sink_payload_addr;
-assign litedramcore_bankmachine0_source_valid = litedramcore_bankmachine0_syncfifo0_readable;
-assign litedramcore_bankmachine0_source_first = litedramcore_bankmachine0_fifo_out_first;
-assign litedramcore_bankmachine0_source_last = litedramcore_bankmachine0_fifo_out_last;
-assign litedramcore_bankmachine0_source_payload_we = litedramcore_bankmachine0_fifo_out_payload_we;
-assign litedramcore_bankmachine0_source_payload_addr = litedramcore_bankmachine0_fifo_out_payload_addr;
-assign litedramcore_bankmachine0_syncfifo0_re = litedramcore_bankmachine0_source_ready;
-always @(*) begin
-    litedramcore_bankmachine0_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine0_replace) begin
-        litedramcore_bankmachine0_wrport_adr <= (litedramcore_bankmachine0_produce - 1'd1);
+        main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write);
+assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
+assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine0_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine0_source_valid & main_litedramcore_bankmachine0_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine0_source_payload_addr[21:7] != main_litedramcore_bankmachine0_source_source_payload_addr[21:7])) begin
+            main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine0_syncfifo0_din = {main_litedramcore_bankmachine0_fifo_in_last, main_litedramcore_bankmachine0_fifo_in_first, main_litedramcore_bankmachine0_fifo_in_payload_addr, main_litedramcore_bankmachine0_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout;
+assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout;
+assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout;
+assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout;
+assign main_litedramcore_bankmachine0_sink_ready = main_litedramcore_bankmachine0_syncfifo0_writable;
+assign main_litedramcore_bankmachine0_syncfifo0_we = main_litedramcore_bankmachine0_sink_valid;
+assign main_litedramcore_bankmachine0_fifo_in_first = main_litedramcore_bankmachine0_sink_first;
+assign main_litedramcore_bankmachine0_fifo_in_last = main_litedramcore_bankmachine0_sink_last;
+assign main_litedramcore_bankmachine0_fifo_in_payload_we = main_litedramcore_bankmachine0_sink_payload_we;
+assign main_litedramcore_bankmachine0_fifo_in_payload_addr = main_litedramcore_bankmachine0_sink_payload_addr;
+assign main_litedramcore_bankmachine0_source_valid = main_litedramcore_bankmachine0_syncfifo0_readable;
+assign main_litedramcore_bankmachine0_source_first = main_litedramcore_bankmachine0_fifo_out_first;
+assign main_litedramcore_bankmachine0_source_last = main_litedramcore_bankmachine0_fifo_out_last;
+assign main_litedramcore_bankmachine0_source_payload_we = main_litedramcore_bankmachine0_fifo_out_payload_we;
+assign main_litedramcore_bankmachine0_source_payload_addr = main_litedramcore_bankmachine0_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine0_syncfifo0_re = main_litedramcore_bankmachine0_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine0_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine0_replace) begin
+        main_litedramcore_bankmachine0_wrport_adr <= (main_litedramcore_bankmachine0_produce - 1'd1);
     end else begin
-        litedramcore_bankmachine0_wrport_adr <= litedramcore_bankmachine0_produce;
-    end
-end
-assign litedramcore_bankmachine0_wrport_dat_w = litedramcore_bankmachine0_syncfifo0_din;
-assign litedramcore_bankmachine0_wrport_we = (litedramcore_bankmachine0_syncfifo0_we & (litedramcore_bankmachine0_syncfifo0_writable | litedramcore_bankmachine0_replace));
-assign litedramcore_bankmachine0_do_read = (litedramcore_bankmachine0_syncfifo0_readable & litedramcore_bankmachine0_syncfifo0_re);
-assign litedramcore_bankmachine0_rdport_adr = litedramcore_bankmachine0_consume;
-assign litedramcore_bankmachine0_syncfifo0_dout = litedramcore_bankmachine0_rdport_dat_r;
-assign litedramcore_bankmachine0_syncfifo0_writable = (litedramcore_bankmachine0_level != 5'd16);
-assign litedramcore_bankmachine0_syncfifo0_readable = (litedramcore_bankmachine0_level != 1'd0);
-assign litedramcore_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready);
-assign litedramcore_bankmachine0_pipe_valid_sink_valid = litedramcore_bankmachine0_sink_sink_valid;
-assign litedramcore_bankmachine0_sink_sink_ready = litedramcore_bankmachine0_pipe_valid_sink_ready;
-assign litedramcore_bankmachine0_pipe_valid_sink_first = litedramcore_bankmachine0_sink_sink_first;
-assign litedramcore_bankmachine0_pipe_valid_sink_last = litedramcore_bankmachine0_sink_sink_last;
-assign litedramcore_bankmachine0_pipe_valid_sink_payload_we = litedramcore_bankmachine0_sink_sink_payload_we;
-assign litedramcore_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_bankmachine0_sink_sink_payload_addr;
-assign litedramcore_bankmachine0_source_source_valid = litedramcore_bankmachine0_pipe_valid_source_valid;
-assign litedramcore_bankmachine0_pipe_valid_source_ready = litedramcore_bankmachine0_source_source_ready;
-assign litedramcore_bankmachine0_source_source_first = litedramcore_bankmachine0_pipe_valid_source_first;
-assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_pipe_valid_source_last;
-assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine0_next_state <= 4'd0;
-    litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
-    case (litedramcore_bankmachine0_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                if (litedramcore_bankmachine0_cmd_ready) begin
-                    litedramcore_bankmachine0_next_state <= 3'd5;
+        main_litedramcore_bankmachine0_wrport_adr <= main_litedramcore_bankmachine0_produce;
+    end
+end
+assign main_litedramcore_bankmachine0_wrport_dat_w = main_litedramcore_bankmachine0_syncfifo0_din;
+assign main_litedramcore_bankmachine0_wrport_we = (main_litedramcore_bankmachine0_syncfifo0_we & (main_litedramcore_bankmachine0_syncfifo0_writable | main_litedramcore_bankmachine0_replace));
+assign main_litedramcore_bankmachine0_do_read = (main_litedramcore_bankmachine0_syncfifo0_readable & main_litedramcore_bankmachine0_syncfifo0_re);
+assign main_litedramcore_bankmachine0_rdport_adr = main_litedramcore_bankmachine0_consume;
+assign main_litedramcore_bankmachine0_syncfifo0_dout = main_litedramcore_bankmachine0_rdport_dat_r;
+assign main_litedramcore_bankmachine0_syncfifo0_writable = (main_litedramcore_bankmachine0_level != 5'd16);
+assign main_litedramcore_bankmachine0_syncfifo0_readable = (main_litedramcore_bankmachine0_level != 1'd0);
+assign main_litedramcore_bankmachine0_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine0_pipe_valid_source_valid) | main_litedramcore_bankmachine0_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine0_pipe_valid_sink_valid = main_litedramcore_bankmachine0_sink_sink_valid;
+assign main_litedramcore_bankmachine0_sink_sink_ready = main_litedramcore_bankmachine0_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine0_pipe_valid_sink_first = main_litedramcore_bankmachine0_sink_sink_first;
+assign main_litedramcore_bankmachine0_pipe_valid_sink_last = main_litedramcore_bankmachine0_sink_sink_last;
+assign main_litedramcore_bankmachine0_pipe_valid_sink_payload_we = main_litedramcore_bankmachine0_sink_sink_payload_we;
+assign main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine0_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine0_source_source_valid = main_litedramcore_bankmachine0_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine0_pipe_valid_source_ready = main_litedramcore_bankmachine0_source_source_ready;
+assign main_litedramcore_bankmachine0_source_source_first = main_litedramcore_bankmachine0_pipe_valid_source_first;
+assign main_litedramcore_bankmachine0_source_source_last = main_litedramcore_bankmachine0_pipe_valid_source_last;
+assign main_litedramcore_bankmachine0_source_source_payload_we = main_litedramcore_bankmachine0_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine0_source_source_payload_addr = main_litedramcore_bankmachine0_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine0_next_state <= 4'd0;
+    builder_bankmachine0_next_state <= builder_bankmachine0_state;
+    case (builder_bankmachine0_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                if (main_litedramcore_bankmachine0_cmd_ready) begin
+                    builder_bankmachine0_next_state <= 3'd5;
                 end
             end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_next_state <= 3'd5;
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                builder_bankmachine0_next_state <= 3'd5;
             end
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                if (litedramcore_bankmachine0_cmd_ready) begin
-                    litedramcore_bankmachine0_next_state <= 3'd7;
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                if (main_litedramcore_bankmachine0_cmd_ready) begin
+                    builder_bankmachine0_next_state <= 3'd7;
                 end
             end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine0_refresh_req)) begin
-                litedramcore_bankmachine0_next_state <= 1'd0;
+            if ((~main_litedramcore_bankmachine0_refresh_req)) begin
+                builder_bankmachine0_next_state <= 1'd0;
             end
         end
         3'd5: begin
-            litedramcore_bankmachine0_next_state <= 3'd6;
+            builder_bankmachine0_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine0_next_state <= 2'd3;
+            builder_bankmachine0_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine0_next_state <= 4'd8;
+            builder_bankmachine0_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine0_next_state <= 1'd0;
+            builder_bankmachine0_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
-                litedramcore_bankmachine0_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine0_refresh_req) begin
+                builder_bankmachine0_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
-                                litedramcore_bankmachine0_next_state <= 2'd2;
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if ((main_litedramcore_bankmachine0_cmd_ready & main_litedramcore_bankmachine0_auto_precharge)) begin
+                                builder_bankmachine0_next_state <= 2'd2;
                             end
                         end else begin
-                            litedramcore_bankmachine0_next_state <= 1'd1;
+                            builder_bankmachine0_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine0_next_state <= 2'd3;
+                        builder_bankmachine0_next_state <= 2'd3;
                     end
                 end
             end
@@ -6375,15 +6966,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         3'd4: begin
+            main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -6394,27 +6992,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
-                                litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6432,14 +7015,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
-                                litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
                             end else begin
+                                main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -6451,8 +7034,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6470,14 +7053,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
+                                main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
                             end else begin
-                                litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
                             end
                         end else begin
                         end
@@ -6489,8 +7072,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6498,9 +7081,6 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine0_twtpcon_ready) begin
-                litedramcore_bankmachine0_refresh_gnt <= 1'd1;
-            end
         end
         3'd5: begin
         end
@@ -6511,20 +7091,32 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
+                                main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_row_open <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_row_open <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -6537,25 +7129,37 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
+                            end else begin
+                                main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_cmd_valid <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_cmd_valid <= 1'd1;
-            end
         end
         3'd4: begin
+            if (main_litedramcore_bankmachine0_twtpcon_ready) begin
+                main_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -6566,34 +7170,22 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            litedramcore_bankmachine0_cmd_valid <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_row_close <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_row_open <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
-            litedramcore_bankmachine0_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine0_row_close <= 1'd1;
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_row_open <= 1'd1;
+            end
         end
         3'd4: begin
-            litedramcore_bankmachine0_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -6608,15 +7200,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_valid <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -6630,19 +7225,34 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_row_close <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
+            main_litedramcore_bankmachine0_row_close <= 1'd1;
         end
         2'd2: begin
+            main_litedramcore_bankmachine0_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
+            main_litedramcore_bankmachine0_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -6653,34 +7263,19 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -6698,12 +7293,9 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
-            end
         end
         2'd2: begin
         end
@@ -6720,15 +7312,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
-                                litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
-                            end else begin
-                            end
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -6739,22 +7328,21 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -6769,9 +7357,12 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+            end
         end
         2'd2: begin
         end
@@ -6788,14 +7379,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
+                                main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
                             end else begin
-                                litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -6806,139 +7397,139 @@ always @(*) begin
         end
     endcase
 end
-assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid;
-assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready;
-assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we;
-assign litedramcore_bankmachine1_sink_payload_addr = litedramcore_bankmachine1_req_addr;
-assign litedramcore_bankmachine1_sink_sink_valid = litedramcore_bankmachine1_source_valid;
-assign litedramcore_bankmachine1_source_ready = litedramcore_bankmachine1_sink_sink_ready;
-assign litedramcore_bankmachine1_sink_sink_first = litedramcore_bankmachine1_source_first;
-assign litedramcore_bankmachine1_sink_sink_last = litedramcore_bankmachine1_source_last;
-assign litedramcore_bankmachine1_sink_sink_payload_we = litedramcore_bankmachine1_source_payload_we;
-assign litedramcore_bankmachine1_sink_sink_payload_addr = litedramcore_bankmachine1_source_payload_addr;
-assign litedramcore_bankmachine1_source_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
-assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_source_valid | litedramcore_bankmachine1_source_source_valid);
-assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_source_source_payload_addr[21:7]);
-assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
+assign main_litedramcore_bankmachine1_sink_valid = main_litedramcore_bankmachine1_req_valid;
+assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_sink_ready;
+assign main_litedramcore_bankmachine1_sink_payload_we = main_litedramcore_bankmachine1_req_we;
+assign main_litedramcore_bankmachine1_sink_payload_addr = main_litedramcore_bankmachine1_req_addr;
+assign main_litedramcore_bankmachine1_sink_sink_valid = main_litedramcore_bankmachine1_source_valid;
+assign main_litedramcore_bankmachine1_source_ready = main_litedramcore_bankmachine1_sink_sink_ready;
+assign main_litedramcore_bankmachine1_sink_sink_first = main_litedramcore_bankmachine1_source_first;
+assign main_litedramcore_bankmachine1_sink_sink_last = main_litedramcore_bankmachine1_source_last;
+assign main_litedramcore_bankmachine1_sink_sink_payload_we = main_litedramcore_bankmachine1_source_payload_we;
+assign main_litedramcore_bankmachine1_sink_sink_payload_addr = main_litedramcore_bankmachine1_source_payload_addr;
+assign main_litedramcore_bankmachine1_source_source_ready = (main_litedramcore_bankmachine1_req_wdata_ready | main_litedramcore_bankmachine1_req_rdata_valid);
+assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_source_valid | main_litedramcore_bankmachine1_source_source_valid);
+assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_source_source_payload_addr[21:7]);
+assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_a <= 15'd0;
-    if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
-        litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_source_source_payload_addr[21:7];
+    main_litedramcore_bankmachine1_cmd_payload_a <= 15'd0;
+    if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine1_cmd_payload_a <= main_litedramcore_bankmachine1_source_source_payload_addr[21:7];
     end else begin
-        litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
-assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
-assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
-always @(*) begin
-    litedramcore_bankmachine1_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine1_source_valid & litedramcore_bankmachine1_source_source_valid)) begin
-        if ((litedramcore_bankmachine1_source_payload_addr[21:7] != litedramcore_bankmachine1_source_source_payload_addr[21:7])) begin
-            litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine1_syncfifo1_din = {litedramcore_bankmachine1_fifo_in_last, litedramcore_bankmachine1_fifo_in_first, litedramcore_bankmachine1_fifo_in_payload_addr, litedramcore_bankmachine1_fifo_in_payload_we};
-assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
-assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
-assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
-assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
-assign litedramcore_bankmachine1_sink_ready = litedramcore_bankmachine1_syncfifo1_writable;
-assign litedramcore_bankmachine1_syncfifo1_we = litedramcore_bankmachine1_sink_valid;
-assign litedramcore_bankmachine1_fifo_in_first = litedramcore_bankmachine1_sink_first;
-assign litedramcore_bankmachine1_fifo_in_last = litedramcore_bankmachine1_sink_last;
-assign litedramcore_bankmachine1_fifo_in_payload_we = litedramcore_bankmachine1_sink_payload_we;
-assign litedramcore_bankmachine1_fifo_in_payload_addr = litedramcore_bankmachine1_sink_payload_addr;
-assign litedramcore_bankmachine1_source_valid = litedramcore_bankmachine1_syncfifo1_readable;
-assign litedramcore_bankmachine1_source_first = litedramcore_bankmachine1_fifo_out_first;
-assign litedramcore_bankmachine1_source_last = litedramcore_bankmachine1_fifo_out_last;
-assign litedramcore_bankmachine1_source_payload_we = litedramcore_bankmachine1_fifo_out_payload_we;
-assign litedramcore_bankmachine1_source_payload_addr = litedramcore_bankmachine1_fifo_out_payload_addr;
-assign litedramcore_bankmachine1_syncfifo1_re = litedramcore_bankmachine1_source_ready;
-always @(*) begin
-    litedramcore_bankmachine1_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine1_replace) begin
-        litedramcore_bankmachine1_wrport_adr <= (litedramcore_bankmachine1_produce - 1'd1);
+        main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write);
+assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
+assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine1_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine1_source_valid & main_litedramcore_bankmachine1_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine1_source_payload_addr[21:7] != main_litedramcore_bankmachine1_source_source_payload_addr[21:7])) begin
+            main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine1_syncfifo1_din = {main_litedramcore_bankmachine1_fifo_in_last, main_litedramcore_bankmachine1_fifo_in_first, main_litedramcore_bankmachine1_fifo_in_payload_addr, main_litedramcore_bankmachine1_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout;
+assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout;
+assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout;
+assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout;
+assign main_litedramcore_bankmachine1_sink_ready = main_litedramcore_bankmachine1_syncfifo1_writable;
+assign main_litedramcore_bankmachine1_syncfifo1_we = main_litedramcore_bankmachine1_sink_valid;
+assign main_litedramcore_bankmachine1_fifo_in_first = main_litedramcore_bankmachine1_sink_first;
+assign main_litedramcore_bankmachine1_fifo_in_last = main_litedramcore_bankmachine1_sink_last;
+assign main_litedramcore_bankmachine1_fifo_in_payload_we = main_litedramcore_bankmachine1_sink_payload_we;
+assign main_litedramcore_bankmachine1_fifo_in_payload_addr = main_litedramcore_bankmachine1_sink_payload_addr;
+assign main_litedramcore_bankmachine1_source_valid = main_litedramcore_bankmachine1_syncfifo1_readable;
+assign main_litedramcore_bankmachine1_source_first = main_litedramcore_bankmachine1_fifo_out_first;
+assign main_litedramcore_bankmachine1_source_last = main_litedramcore_bankmachine1_fifo_out_last;
+assign main_litedramcore_bankmachine1_source_payload_we = main_litedramcore_bankmachine1_fifo_out_payload_we;
+assign main_litedramcore_bankmachine1_source_payload_addr = main_litedramcore_bankmachine1_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine1_syncfifo1_re = main_litedramcore_bankmachine1_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine1_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine1_replace) begin
+        main_litedramcore_bankmachine1_wrport_adr <= (main_litedramcore_bankmachine1_produce - 1'd1);
     end else begin
-        litedramcore_bankmachine1_wrport_adr <= litedramcore_bankmachine1_produce;
-    end
-end
-assign litedramcore_bankmachine1_wrport_dat_w = litedramcore_bankmachine1_syncfifo1_din;
-assign litedramcore_bankmachine1_wrport_we = (litedramcore_bankmachine1_syncfifo1_we & (litedramcore_bankmachine1_syncfifo1_writable | litedramcore_bankmachine1_replace));
-assign litedramcore_bankmachine1_do_read = (litedramcore_bankmachine1_syncfifo1_readable & litedramcore_bankmachine1_syncfifo1_re);
-assign litedramcore_bankmachine1_rdport_adr = litedramcore_bankmachine1_consume;
-assign litedramcore_bankmachine1_syncfifo1_dout = litedramcore_bankmachine1_rdport_dat_r;
-assign litedramcore_bankmachine1_syncfifo1_writable = (litedramcore_bankmachine1_level != 5'd16);
-assign litedramcore_bankmachine1_syncfifo1_readable = (litedramcore_bankmachine1_level != 1'd0);
-assign litedramcore_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready);
-assign litedramcore_bankmachine1_pipe_valid_sink_valid = litedramcore_bankmachine1_sink_sink_valid;
-assign litedramcore_bankmachine1_sink_sink_ready = litedramcore_bankmachine1_pipe_valid_sink_ready;
-assign litedramcore_bankmachine1_pipe_valid_sink_first = litedramcore_bankmachine1_sink_sink_first;
-assign litedramcore_bankmachine1_pipe_valid_sink_last = litedramcore_bankmachine1_sink_sink_last;
-assign litedramcore_bankmachine1_pipe_valid_sink_payload_we = litedramcore_bankmachine1_sink_sink_payload_we;
-assign litedramcore_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_bankmachine1_sink_sink_payload_addr;
-assign litedramcore_bankmachine1_source_source_valid = litedramcore_bankmachine1_pipe_valid_source_valid;
-assign litedramcore_bankmachine1_pipe_valid_source_ready = litedramcore_bankmachine1_source_source_ready;
-assign litedramcore_bankmachine1_source_source_first = litedramcore_bankmachine1_pipe_valid_source_first;
-assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_pipe_valid_source_last;
-assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine1_next_state <= 4'd0;
-    litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
-    case (litedramcore_bankmachine1_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                if (litedramcore_bankmachine1_cmd_ready) begin
-                    litedramcore_bankmachine1_next_state <= 3'd5;
+        main_litedramcore_bankmachine1_wrport_adr <= main_litedramcore_bankmachine1_produce;
+    end
+end
+assign main_litedramcore_bankmachine1_wrport_dat_w = main_litedramcore_bankmachine1_syncfifo1_din;
+assign main_litedramcore_bankmachine1_wrport_we = (main_litedramcore_bankmachine1_syncfifo1_we & (main_litedramcore_bankmachine1_syncfifo1_writable | main_litedramcore_bankmachine1_replace));
+assign main_litedramcore_bankmachine1_do_read = (main_litedramcore_bankmachine1_syncfifo1_readable & main_litedramcore_bankmachine1_syncfifo1_re);
+assign main_litedramcore_bankmachine1_rdport_adr = main_litedramcore_bankmachine1_consume;
+assign main_litedramcore_bankmachine1_syncfifo1_dout = main_litedramcore_bankmachine1_rdport_dat_r;
+assign main_litedramcore_bankmachine1_syncfifo1_writable = (main_litedramcore_bankmachine1_level != 5'd16);
+assign main_litedramcore_bankmachine1_syncfifo1_readable = (main_litedramcore_bankmachine1_level != 1'd0);
+assign main_litedramcore_bankmachine1_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine1_pipe_valid_source_valid) | main_litedramcore_bankmachine1_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine1_pipe_valid_sink_valid = main_litedramcore_bankmachine1_sink_sink_valid;
+assign main_litedramcore_bankmachine1_sink_sink_ready = main_litedramcore_bankmachine1_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine1_pipe_valid_sink_first = main_litedramcore_bankmachine1_sink_sink_first;
+assign main_litedramcore_bankmachine1_pipe_valid_sink_last = main_litedramcore_bankmachine1_sink_sink_last;
+assign main_litedramcore_bankmachine1_pipe_valid_sink_payload_we = main_litedramcore_bankmachine1_sink_sink_payload_we;
+assign main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine1_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine1_source_source_valid = main_litedramcore_bankmachine1_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine1_pipe_valid_source_ready = main_litedramcore_bankmachine1_source_source_ready;
+assign main_litedramcore_bankmachine1_source_source_first = main_litedramcore_bankmachine1_pipe_valid_source_first;
+assign main_litedramcore_bankmachine1_source_source_last = main_litedramcore_bankmachine1_pipe_valid_source_last;
+assign main_litedramcore_bankmachine1_source_source_payload_we = main_litedramcore_bankmachine1_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine1_source_source_payload_addr = main_litedramcore_bankmachine1_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine1_next_state <= 4'd0;
+    builder_bankmachine1_next_state <= builder_bankmachine1_state;
+    case (builder_bankmachine1_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                if (main_litedramcore_bankmachine1_cmd_ready) begin
+                    builder_bankmachine1_next_state <= 3'd5;
                 end
             end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_next_state <= 3'd5;
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                builder_bankmachine1_next_state <= 3'd5;
             end
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                if (litedramcore_bankmachine1_cmd_ready) begin
-                    litedramcore_bankmachine1_next_state <= 3'd7;
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                if (main_litedramcore_bankmachine1_cmd_ready) begin
+                    builder_bankmachine1_next_state <= 3'd7;
                 end
             end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine1_refresh_req)) begin
-                litedramcore_bankmachine1_next_state <= 1'd0;
+            if ((~main_litedramcore_bankmachine1_refresh_req)) begin
+                builder_bankmachine1_next_state <= 1'd0;
             end
         end
         3'd5: begin
-            litedramcore_bankmachine1_next_state <= 3'd6;
+            builder_bankmachine1_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine1_next_state <= 2'd3;
+            builder_bankmachine1_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine1_next_state <= 4'd8;
+            builder_bankmachine1_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine1_next_state <= 1'd0;
+            builder_bankmachine1_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
-                litedramcore_bankmachine1_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine1_refresh_req) begin
+                builder_bankmachine1_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
-                                litedramcore_bankmachine1_next_state <= 2'd2;
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if ((main_litedramcore_bankmachine1_cmd_ready & main_litedramcore_bankmachine1_auto_precharge)) begin
+                                builder_bankmachine1_next_state <= 2'd2;
                             end
                         end else begin
-                            litedramcore_bankmachine1_next_state <= 1'd1;
+                            builder_bankmachine1_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine1_next_state <= 2'd3;
+                        builder_bankmachine1_next_state <= 2'd3;
                     end
                 end
             end
@@ -6946,18 +7537,56 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_row_open <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_row_open <= 1'd1;
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
+                            end else begin
+                                main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
             end
         end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+    case (builder_bankmachine1_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
         3'd4: begin
+            if (main_litedramcore_bankmachine1_twtpcon_ready) begin
+                main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -6972,18 +7601,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -6997,12 +7626,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            litedramcore_bankmachine1_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -7013,18 +7642,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_row_close <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_row_close <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            litedramcore_bankmachine1_row_close <= 1'd1;
+            main_litedramcore_bankmachine1_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine1_row_close <= 1'd1;
+            main_litedramcore_bankmachine1_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine1_row_close <= 1'd1;
+            main_litedramcore_bankmachine1_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -7039,18 +7668,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_row_open <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_row_open <= 1'd1;
+            end
         end
         3'd4: begin
-            if (litedramcore_bankmachine1_twtpcon_ready) begin
-                litedramcore_bankmachine1_refresh_gnt <= 1'd1;
-            end
         end
         3'd5: begin
         end
@@ -7065,15 +7694,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -7091,8 +7720,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7110,12 +7739,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -7126,18 +7755,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -7155,11 +7784,11 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
@@ -7177,13 +7806,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                                litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
+                                main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -7196,22 +7825,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -7226,8 +7855,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7245,14 +7874,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -7264,8 +7893,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7283,13 +7912,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                                litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
+                                main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -7302,8 +7931,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7321,13 +7950,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                                litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
+                                main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -7339,193 +7968,181 @@ always @(*) begin
         end
     endcase
 end
+assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid;
+assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready;
+assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we;
+assign main_litedramcore_bankmachine2_sink_payload_addr = main_litedramcore_bankmachine2_req_addr;
+assign main_litedramcore_bankmachine2_sink_sink_valid = main_litedramcore_bankmachine2_source_valid;
+assign main_litedramcore_bankmachine2_source_ready = main_litedramcore_bankmachine2_sink_sink_ready;
+assign main_litedramcore_bankmachine2_sink_sink_first = main_litedramcore_bankmachine2_source_first;
+assign main_litedramcore_bankmachine2_sink_sink_last = main_litedramcore_bankmachine2_source_last;
+assign main_litedramcore_bankmachine2_sink_sink_payload_we = main_litedramcore_bankmachine2_source_payload_we;
+assign main_litedramcore_bankmachine2_sink_sink_payload_addr = main_litedramcore_bankmachine2_source_payload_addr;
+assign main_litedramcore_bankmachine2_source_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid);
+assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_source_valid | main_litedramcore_bankmachine2_source_source_valid);
+assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_source_source_payload_addr[21:7]);
+assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
 always @(*) begin
-    litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine1_state)
-        1'd1: begin
+    main_litedramcore_bankmachine2_cmd_payload_a <= 15'd0;
+    if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine2_cmd_payload_a <= main_litedramcore_bankmachine2_source_source_payload_addr[21:7];
+    end else begin
+        main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write);
+assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
+assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine2_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine2_source_valid & main_litedramcore_bankmachine2_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine2_source_payload_addr[21:7] != main_litedramcore_bankmachine2_source_source_payload_addr[21:7])) begin
+            main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine2_syncfifo2_din = {main_litedramcore_bankmachine2_fifo_in_last, main_litedramcore_bankmachine2_fifo_in_first, main_litedramcore_bankmachine2_fifo_in_payload_addr, main_litedramcore_bankmachine2_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
+assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
+assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
+assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
+assign main_litedramcore_bankmachine2_sink_ready = main_litedramcore_bankmachine2_syncfifo2_writable;
+assign main_litedramcore_bankmachine2_syncfifo2_we = main_litedramcore_bankmachine2_sink_valid;
+assign main_litedramcore_bankmachine2_fifo_in_first = main_litedramcore_bankmachine2_sink_first;
+assign main_litedramcore_bankmachine2_fifo_in_last = main_litedramcore_bankmachine2_sink_last;
+assign main_litedramcore_bankmachine2_fifo_in_payload_we = main_litedramcore_bankmachine2_sink_payload_we;
+assign main_litedramcore_bankmachine2_fifo_in_payload_addr = main_litedramcore_bankmachine2_sink_payload_addr;
+assign main_litedramcore_bankmachine2_source_valid = main_litedramcore_bankmachine2_syncfifo2_readable;
+assign main_litedramcore_bankmachine2_source_first = main_litedramcore_bankmachine2_fifo_out_first;
+assign main_litedramcore_bankmachine2_source_last = main_litedramcore_bankmachine2_fifo_out_last;
+assign main_litedramcore_bankmachine2_source_payload_we = main_litedramcore_bankmachine2_fifo_out_payload_we;
+assign main_litedramcore_bankmachine2_source_payload_addr = main_litedramcore_bankmachine2_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine2_syncfifo2_re = main_litedramcore_bankmachine2_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine2_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine2_replace) begin
+        main_litedramcore_bankmachine2_wrport_adr <= (main_litedramcore_bankmachine2_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine2_wrport_adr <= main_litedramcore_bankmachine2_produce;
+    end
+end
+assign main_litedramcore_bankmachine2_wrport_dat_w = main_litedramcore_bankmachine2_syncfifo2_din;
+assign main_litedramcore_bankmachine2_wrport_we = (main_litedramcore_bankmachine2_syncfifo2_we & (main_litedramcore_bankmachine2_syncfifo2_writable | main_litedramcore_bankmachine2_replace));
+assign main_litedramcore_bankmachine2_do_read = (main_litedramcore_bankmachine2_syncfifo2_readable & main_litedramcore_bankmachine2_syncfifo2_re);
+assign main_litedramcore_bankmachine2_rdport_adr = main_litedramcore_bankmachine2_consume;
+assign main_litedramcore_bankmachine2_syncfifo2_dout = main_litedramcore_bankmachine2_rdport_dat_r;
+assign main_litedramcore_bankmachine2_syncfifo2_writable = (main_litedramcore_bankmachine2_level != 5'd16);
+assign main_litedramcore_bankmachine2_syncfifo2_readable = (main_litedramcore_bankmachine2_level != 1'd0);
+assign main_litedramcore_bankmachine2_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine2_pipe_valid_source_valid) | main_litedramcore_bankmachine2_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine2_pipe_valid_sink_valid = main_litedramcore_bankmachine2_sink_sink_valid;
+assign main_litedramcore_bankmachine2_sink_sink_ready = main_litedramcore_bankmachine2_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine2_pipe_valid_sink_first = main_litedramcore_bankmachine2_sink_sink_first;
+assign main_litedramcore_bankmachine2_pipe_valid_sink_last = main_litedramcore_bankmachine2_sink_sink_last;
+assign main_litedramcore_bankmachine2_pipe_valid_sink_payload_we = main_litedramcore_bankmachine2_sink_sink_payload_we;
+assign main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine2_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine2_source_source_valid = main_litedramcore_bankmachine2_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine2_pipe_valid_source_ready = main_litedramcore_bankmachine2_source_source_ready;
+assign main_litedramcore_bankmachine2_source_source_first = main_litedramcore_bankmachine2_pipe_valid_source_first;
+assign main_litedramcore_bankmachine2_source_source_last = main_litedramcore_bankmachine2_pipe_valid_source_last;
+assign main_litedramcore_bankmachine2_source_source_payload_we = main_litedramcore_bankmachine2_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine2_source_source_payload_addr = main_litedramcore_bankmachine2_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine2_next_state <= 4'd0;
+    builder_bankmachine2_next_state <= builder_bankmachine2_state;
+    case (builder_bankmachine2_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                if (main_litedramcore_bankmachine2_cmd_ready) begin
+                    builder_bankmachine2_next_state <= 3'd5;
+                end
+            end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                builder_bankmachine2_next_state <= 3'd5;
+            end
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                if (main_litedramcore_bankmachine2_cmd_ready) begin
+                    builder_bankmachine2_next_state <= 3'd7;
+                end
+            end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine2_refresh_req)) begin
+                builder_bankmachine2_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine2_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine2_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine2_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine2_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
+                builder_bankmachine2_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if ((main_litedramcore_bankmachine2_cmd_ready & main_litedramcore_bankmachine2_auto_precharge)) begin
+                                builder_bankmachine2_next_state <= 2'd2;
                             end
                         end else begin
+                            builder_bankmachine2_next_state <= 1'd1;
                         end
                     end else begin
+                        builder_bankmachine2_next_state <= 2'd3;
                     end
                 end
             end
         end
     endcase
 end
-assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid;
-assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready;
-assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we;
-assign litedramcore_bankmachine2_sink_payload_addr = litedramcore_bankmachine2_req_addr;
-assign litedramcore_bankmachine2_sink_sink_valid = litedramcore_bankmachine2_source_valid;
-assign litedramcore_bankmachine2_source_ready = litedramcore_bankmachine2_sink_sink_ready;
-assign litedramcore_bankmachine2_sink_sink_first = litedramcore_bankmachine2_source_first;
-assign litedramcore_bankmachine2_sink_sink_last = litedramcore_bankmachine2_source_last;
-assign litedramcore_bankmachine2_sink_sink_payload_we = litedramcore_bankmachine2_source_payload_we;
-assign litedramcore_bankmachine2_sink_sink_payload_addr = litedramcore_bankmachine2_source_payload_addr;
-assign litedramcore_bankmachine2_source_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
-assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_source_valid | litedramcore_bankmachine2_source_source_valid);
-assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_source_source_payload_addr[21:7]);
-assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_a <= 15'd0;
-    if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
-        litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_source_source_payload_addr[21:7];
-    end else begin
-        litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
-assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
-assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
-always @(*) begin
-    litedramcore_bankmachine2_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine2_source_valid & litedramcore_bankmachine2_source_source_valid)) begin
-        if ((litedramcore_bankmachine2_source_payload_addr[21:7] != litedramcore_bankmachine2_source_source_payload_addr[21:7])) begin
-            litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine2_syncfifo2_din = {litedramcore_bankmachine2_fifo_in_last, litedramcore_bankmachine2_fifo_in_first, litedramcore_bankmachine2_fifo_in_payload_addr, litedramcore_bankmachine2_fifo_in_payload_we};
-assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
-assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
-assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
-assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
-assign litedramcore_bankmachine2_sink_ready = litedramcore_bankmachine2_syncfifo2_writable;
-assign litedramcore_bankmachine2_syncfifo2_we = litedramcore_bankmachine2_sink_valid;
-assign litedramcore_bankmachine2_fifo_in_first = litedramcore_bankmachine2_sink_first;
-assign litedramcore_bankmachine2_fifo_in_last = litedramcore_bankmachine2_sink_last;
-assign litedramcore_bankmachine2_fifo_in_payload_we = litedramcore_bankmachine2_sink_payload_we;
-assign litedramcore_bankmachine2_fifo_in_payload_addr = litedramcore_bankmachine2_sink_payload_addr;
-assign litedramcore_bankmachine2_source_valid = litedramcore_bankmachine2_syncfifo2_readable;
-assign litedramcore_bankmachine2_source_first = litedramcore_bankmachine2_fifo_out_first;
-assign litedramcore_bankmachine2_source_last = litedramcore_bankmachine2_fifo_out_last;
-assign litedramcore_bankmachine2_source_payload_we = litedramcore_bankmachine2_fifo_out_payload_we;
-assign litedramcore_bankmachine2_source_payload_addr = litedramcore_bankmachine2_fifo_out_payload_addr;
-assign litedramcore_bankmachine2_syncfifo2_re = litedramcore_bankmachine2_source_ready;
-always @(*) begin
-    litedramcore_bankmachine2_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine2_replace) begin
-        litedramcore_bankmachine2_wrport_adr <= (litedramcore_bankmachine2_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine2_wrport_adr <= litedramcore_bankmachine2_produce;
-    end
-end
-assign litedramcore_bankmachine2_wrport_dat_w = litedramcore_bankmachine2_syncfifo2_din;
-assign litedramcore_bankmachine2_wrport_we = (litedramcore_bankmachine2_syncfifo2_we & (litedramcore_bankmachine2_syncfifo2_writable | litedramcore_bankmachine2_replace));
-assign litedramcore_bankmachine2_do_read = (litedramcore_bankmachine2_syncfifo2_readable & litedramcore_bankmachine2_syncfifo2_re);
-assign litedramcore_bankmachine2_rdport_adr = litedramcore_bankmachine2_consume;
-assign litedramcore_bankmachine2_syncfifo2_dout = litedramcore_bankmachine2_rdport_dat_r;
-assign litedramcore_bankmachine2_syncfifo2_writable = (litedramcore_bankmachine2_level != 5'd16);
-assign litedramcore_bankmachine2_syncfifo2_readable = (litedramcore_bankmachine2_level != 1'd0);
-assign litedramcore_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready);
-assign litedramcore_bankmachine2_pipe_valid_sink_valid = litedramcore_bankmachine2_sink_sink_valid;
-assign litedramcore_bankmachine2_sink_sink_ready = litedramcore_bankmachine2_pipe_valid_sink_ready;
-assign litedramcore_bankmachine2_pipe_valid_sink_first = litedramcore_bankmachine2_sink_sink_first;
-assign litedramcore_bankmachine2_pipe_valid_sink_last = litedramcore_bankmachine2_sink_sink_last;
-assign litedramcore_bankmachine2_pipe_valid_sink_payload_we = litedramcore_bankmachine2_sink_sink_payload_we;
-assign litedramcore_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_bankmachine2_sink_sink_payload_addr;
-assign litedramcore_bankmachine2_source_source_valid = litedramcore_bankmachine2_pipe_valid_source_valid;
-assign litedramcore_bankmachine2_pipe_valid_source_ready = litedramcore_bankmachine2_source_source_ready;
-assign litedramcore_bankmachine2_source_source_first = litedramcore_bankmachine2_pipe_valid_source_first;
-assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_pipe_valid_source_last;
-assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine2_next_state <= 4'd0;
-    litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
-    case (litedramcore_bankmachine2_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                if (litedramcore_bankmachine2_cmd_ready) begin
-                    litedramcore_bankmachine2_next_state <= 3'd5;
-                end
-            end
+    main_litedramcore_bankmachine2_row_close <= 1'd0;
+    case (builder_bankmachine2_state)
+        1'd1: begin
+            main_litedramcore_bankmachine2_row_close <= 1'd1;
         end
         2'd2: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_next_state <= 3'd5;
-            end
+            main_litedramcore_bankmachine2_row_close <= 1'd1;
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                if (litedramcore_bankmachine2_cmd_ready) begin
-                    litedramcore_bankmachine2_next_state <= 3'd7;
-                end
-            end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine2_refresh_req)) begin
-                litedramcore_bankmachine2_next_state <= 1'd0;
-            end
+            main_litedramcore_bankmachine2_row_close <= 1'd1;
         end
         3'd5: begin
-            litedramcore_bankmachine2_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine2_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine2_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine2_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
-                litedramcore_bankmachine2_next_state <= 3'd4;
-            end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
-                                litedramcore_bankmachine2_next_state <= 2'd2;
-                            end
-                        end else begin
-                            litedramcore_bankmachine2_next_state <= 1'd1;
-                        end
-                    end else begin
-                        litedramcore_bankmachine2_next_state <= 2'd3;
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -7543,8 +8160,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7562,12 +8179,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -7578,18 +8195,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -7607,11 +8224,11 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
@@ -7629,13 +8246,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
-                                litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
+                                main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -7648,22 +8265,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -7678,8 +8295,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7697,14 +8314,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -7716,8 +8333,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7735,13 +8352,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
-                                litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
+                                main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -7754,8 +8371,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7773,13 +8390,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
-                                litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
+                                main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -7792,8 +8409,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7811,14 +8428,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
+                                main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
                             end
                         end else begin
                         end
@@ -7830,8 +8447,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7839,8 +8456,8 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine2_twtpcon_ready) begin
-                litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+            if (main_litedramcore_bankmachine2_twtpcon_ready) begin
+                main_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
             end
         end
         3'd5: begin
@@ -7856,15 +8473,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_row_open <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_row_open <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -7882,18 +8499,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -7907,12 +8524,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            litedramcore_bankmachine2_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -7922,165 +8539,174 @@ always @(*) begin
         end
     endcase
 end
+assign main_litedramcore_bankmachine3_sink_valid = main_litedramcore_bankmachine3_req_valid;
+assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_sink_ready;
+assign main_litedramcore_bankmachine3_sink_payload_we = main_litedramcore_bankmachine3_req_we;
+assign main_litedramcore_bankmachine3_sink_payload_addr = main_litedramcore_bankmachine3_req_addr;
+assign main_litedramcore_bankmachine3_sink_sink_valid = main_litedramcore_bankmachine3_source_valid;
+assign main_litedramcore_bankmachine3_source_ready = main_litedramcore_bankmachine3_sink_sink_ready;
+assign main_litedramcore_bankmachine3_sink_sink_first = main_litedramcore_bankmachine3_source_first;
+assign main_litedramcore_bankmachine3_sink_sink_last = main_litedramcore_bankmachine3_source_last;
+assign main_litedramcore_bankmachine3_sink_sink_payload_we = main_litedramcore_bankmachine3_source_payload_we;
+assign main_litedramcore_bankmachine3_sink_sink_payload_addr = main_litedramcore_bankmachine3_source_payload_addr;
+assign main_litedramcore_bankmachine3_source_source_ready = (main_litedramcore_bankmachine3_req_wdata_ready | main_litedramcore_bankmachine3_req_rdata_valid);
+assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_source_valid | main_litedramcore_bankmachine3_source_source_valid);
+assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_source_source_payload_addr[21:7]);
+assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
 always @(*) begin
-    litedramcore_bankmachine2_row_close <= 1'd0;
-    case (litedramcore_bankmachine2_state)
-        1'd1: begin
-            litedramcore_bankmachine2_row_close <= 1'd1;
+    main_litedramcore_bankmachine3_cmd_payload_a <= 15'd0;
+    if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine3_cmd_payload_a <= main_litedramcore_bankmachine3_source_source_payload_addr[21:7];
+    end else begin
+        main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write);
+assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
+assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine3_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine3_source_valid & main_litedramcore_bankmachine3_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine3_source_payload_addr[21:7] != main_litedramcore_bankmachine3_source_source_payload_addr[21:7])) begin
+            main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine3_syncfifo3_din = {main_litedramcore_bankmachine3_fifo_in_last, main_litedramcore_bankmachine3_fifo_in_first, main_litedramcore_bankmachine3_fifo_in_payload_addr, main_litedramcore_bankmachine3_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout;
+assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout;
+assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout;
+assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout;
+assign main_litedramcore_bankmachine3_sink_ready = main_litedramcore_bankmachine3_syncfifo3_writable;
+assign main_litedramcore_bankmachine3_syncfifo3_we = main_litedramcore_bankmachine3_sink_valid;
+assign main_litedramcore_bankmachine3_fifo_in_first = main_litedramcore_bankmachine3_sink_first;
+assign main_litedramcore_bankmachine3_fifo_in_last = main_litedramcore_bankmachine3_sink_last;
+assign main_litedramcore_bankmachine3_fifo_in_payload_we = main_litedramcore_bankmachine3_sink_payload_we;
+assign main_litedramcore_bankmachine3_fifo_in_payload_addr = main_litedramcore_bankmachine3_sink_payload_addr;
+assign main_litedramcore_bankmachine3_source_valid = main_litedramcore_bankmachine3_syncfifo3_readable;
+assign main_litedramcore_bankmachine3_source_first = main_litedramcore_bankmachine3_fifo_out_first;
+assign main_litedramcore_bankmachine3_source_last = main_litedramcore_bankmachine3_fifo_out_last;
+assign main_litedramcore_bankmachine3_source_payload_we = main_litedramcore_bankmachine3_fifo_out_payload_we;
+assign main_litedramcore_bankmachine3_source_payload_addr = main_litedramcore_bankmachine3_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine3_syncfifo3_re = main_litedramcore_bankmachine3_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine3_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine3_replace) begin
+        main_litedramcore_bankmachine3_wrport_adr <= (main_litedramcore_bankmachine3_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine3_wrport_adr <= main_litedramcore_bankmachine3_produce;
+    end
+end
+assign main_litedramcore_bankmachine3_wrport_dat_w = main_litedramcore_bankmachine3_syncfifo3_din;
+assign main_litedramcore_bankmachine3_wrport_we = (main_litedramcore_bankmachine3_syncfifo3_we & (main_litedramcore_bankmachine3_syncfifo3_writable | main_litedramcore_bankmachine3_replace));
+assign main_litedramcore_bankmachine3_do_read = (main_litedramcore_bankmachine3_syncfifo3_readable & main_litedramcore_bankmachine3_syncfifo3_re);
+assign main_litedramcore_bankmachine3_rdport_adr = main_litedramcore_bankmachine3_consume;
+assign main_litedramcore_bankmachine3_syncfifo3_dout = main_litedramcore_bankmachine3_rdport_dat_r;
+assign main_litedramcore_bankmachine3_syncfifo3_writable = (main_litedramcore_bankmachine3_level != 5'd16);
+assign main_litedramcore_bankmachine3_syncfifo3_readable = (main_litedramcore_bankmachine3_level != 1'd0);
+assign main_litedramcore_bankmachine3_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine3_pipe_valid_source_valid) | main_litedramcore_bankmachine3_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine3_pipe_valid_sink_valid = main_litedramcore_bankmachine3_sink_sink_valid;
+assign main_litedramcore_bankmachine3_sink_sink_ready = main_litedramcore_bankmachine3_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine3_pipe_valid_sink_first = main_litedramcore_bankmachine3_sink_sink_first;
+assign main_litedramcore_bankmachine3_pipe_valid_sink_last = main_litedramcore_bankmachine3_sink_sink_last;
+assign main_litedramcore_bankmachine3_pipe_valid_sink_payload_we = main_litedramcore_bankmachine3_sink_sink_payload_we;
+assign main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine3_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine3_source_source_valid = main_litedramcore_bankmachine3_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine3_pipe_valid_source_ready = main_litedramcore_bankmachine3_source_source_ready;
+assign main_litedramcore_bankmachine3_source_source_first = main_litedramcore_bankmachine3_pipe_valid_source_first;
+assign main_litedramcore_bankmachine3_source_source_last = main_litedramcore_bankmachine3_pipe_valid_source_last;
+assign main_litedramcore_bankmachine3_source_source_payload_we = main_litedramcore_bankmachine3_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine3_source_source_payload_addr = main_litedramcore_bankmachine3_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine3_next_state <= 4'd0;
+    builder_bankmachine3_next_state <= builder_bankmachine3_state;
+    case (builder_bankmachine3_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                if (main_litedramcore_bankmachine3_cmd_ready) begin
+                    builder_bankmachine3_next_state <= 3'd5;
+                end
+            end
         end
         2'd2: begin
-            litedramcore_bankmachine2_row_close <= 1'd1;
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                builder_bankmachine3_next_state <= 3'd5;
+            end
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                if (main_litedramcore_bankmachine3_cmd_ready) begin
+                    builder_bankmachine3_next_state <= 3'd7;
+                end
+            end
         end
         3'd4: begin
-            litedramcore_bankmachine2_row_close <= 1'd1;
+            if ((~main_litedramcore_bankmachine3_refresh_req)) begin
+                builder_bankmachine3_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine3_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine3_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine3_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine3_next_state <= 1'd0;
         end
         default: begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
+                builder_bankmachine3_next_state <= 3'd4;
+            end else begin
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin
+                                builder_bankmachine3_next_state <= 2'd2;
+                            end
+                        end else begin
+                            builder_bankmachine3_next_state <= 1'd1;
+                        end
+                    end else begin
+                        builder_bankmachine3_next_state <= 2'd3;
+                    end
+                end
+            end
         end
     endcase
 end
-assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid;
-assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready;
-assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we;
-assign litedramcore_bankmachine3_sink_payload_addr = litedramcore_bankmachine3_req_addr;
-assign litedramcore_bankmachine3_sink_sink_valid = litedramcore_bankmachine3_source_valid;
-assign litedramcore_bankmachine3_source_ready = litedramcore_bankmachine3_sink_sink_ready;
-assign litedramcore_bankmachine3_sink_sink_first = litedramcore_bankmachine3_source_first;
-assign litedramcore_bankmachine3_sink_sink_last = litedramcore_bankmachine3_source_last;
-assign litedramcore_bankmachine3_sink_sink_payload_we = litedramcore_bankmachine3_source_payload_we;
-assign litedramcore_bankmachine3_sink_sink_payload_addr = litedramcore_bankmachine3_source_payload_addr;
-assign litedramcore_bankmachine3_source_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
-assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_source_valid | litedramcore_bankmachine3_source_source_valid);
-assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_source_source_payload_addr[21:7]);
-assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
-always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_a <= 15'd0;
-    if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
-        litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_source_source_payload_addr[21:7];
-    end else begin
-        litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
-assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
-assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
-always @(*) begin
-    litedramcore_bankmachine3_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine3_source_valid & litedramcore_bankmachine3_source_source_valid)) begin
-        if ((litedramcore_bankmachine3_source_payload_addr[21:7] != litedramcore_bankmachine3_source_source_payload_addr[21:7])) begin
-            litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine3_syncfifo3_din = {litedramcore_bankmachine3_fifo_in_last, litedramcore_bankmachine3_fifo_in_first, litedramcore_bankmachine3_fifo_in_payload_addr, litedramcore_bankmachine3_fifo_in_payload_we};
-assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
-assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
-assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
-assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
-assign litedramcore_bankmachine3_sink_ready = litedramcore_bankmachine3_syncfifo3_writable;
-assign litedramcore_bankmachine3_syncfifo3_we = litedramcore_bankmachine3_sink_valid;
-assign litedramcore_bankmachine3_fifo_in_first = litedramcore_bankmachine3_sink_first;
-assign litedramcore_bankmachine3_fifo_in_last = litedramcore_bankmachine3_sink_last;
-assign litedramcore_bankmachine3_fifo_in_payload_we = litedramcore_bankmachine3_sink_payload_we;
-assign litedramcore_bankmachine3_fifo_in_payload_addr = litedramcore_bankmachine3_sink_payload_addr;
-assign litedramcore_bankmachine3_source_valid = litedramcore_bankmachine3_syncfifo3_readable;
-assign litedramcore_bankmachine3_source_first = litedramcore_bankmachine3_fifo_out_first;
-assign litedramcore_bankmachine3_source_last = litedramcore_bankmachine3_fifo_out_last;
-assign litedramcore_bankmachine3_source_payload_we = litedramcore_bankmachine3_fifo_out_payload_we;
-assign litedramcore_bankmachine3_source_payload_addr = litedramcore_bankmachine3_fifo_out_payload_addr;
-assign litedramcore_bankmachine3_syncfifo3_re = litedramcore_bankmachine3_source_ready;
-always @(*) begin
-    litedramcore_bankmachine3_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine3_replace) begin
-        litedramcore_bankmachine3_wrport_adr <= (litedramcore_bankmachine3_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine3_wrport_adr <= litedramcore_bankmachine3_produce;
-    end
-end
-assign litedramcore_bankmachine3_wrport_dat_w = litedramcore_bankmachine3_syncfifo3_din;
-assign litedramcore_bankmachine3_wrport_we = (litedramcore_bankmachine3_syncfifo3_we & (litedramcore_bankmachine3_syncfifo3_writable | litedramcore_bankmachine3_replace));
-assign litedramcore_bankmachine3_do_read = (litedramcore_bankmachine3_syncfifo3_readable & litedramcore_bankmachine3_syncfifo3_re);
-assign litedramcore_bankmachine3_rdport_adr = litedramcore_bankmachine3_consume;
-assign litedramcore_bankmachine3_syncfifo3_dout = litedramcore_bankmachine3_rdport_dat_r;
-assign litedramcore_bankmachine3_syncfifo3_writable = (litedramcore_bankmachine3_level != 5'd16);
-assign litedramcore_bankmachine3_syncfifo3_readable = (litedramcore_bankmachine3_level != 1'd0);
-assign litedramcore_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready);
-assign litedramcore_bankmachine3_pipe_valid_sink_valid = litedramcore_bankmachine3_sink_sink_valid;
-assign litedramcore_bankmachine3_sink_sink_ready = litedramcore_bankmachine3_pipe_valid_sink_ready;
-assign litedramcore_bankmachine3_pipe_valid_sink_first = litedramcore_bankmachine3_sink_sink_first;
-assign litedramcore_bankmachine3_pipe_valid_sink_last = litedramcore_bankmachine3_sink_sink_last;
-assign litedramcore_bankmachine3_pipe_valid_sink_payload_we = litedramcore_bankmachine3_sink_sink_payload_we;
-assign litedramcore_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_bankmachine3_sink_sink_payload_addr;
-assign litedramcore_bankmachine3_source_source_valid = litedramcore_bankmachine3_pipe_valid_source_valid;
-assign litedramcore_bankmachine3_pipe_valid_source_ready = litedramcore_bankmachine3_source_source_ready;
-assign litedramcore_bankmachine3_source_source_first = litedramcore_bankmachine3_pipe_valid_source_first;
-assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_pipe_valid_source_last;
-assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine3_next_state <= 4'd0;
-    litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
-    case (litedramcore_bankmachine3_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                if (litedramcore_bankmachine3_cmd_ready) begin
-                    litedramcore_bankmachine3_next_state <= 3'd5;
-                end
-            end
+always @(*) begin
+    main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine3_state)
+        1'd1: begin
         end
         2'd2: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                if (litedramcore_bankmachine3_cmd_ready) begin
-                    litedramcore_bankmachine3_next_state <= 3'd7;
-                end
-            end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine3_refresh_req)) begin
-                litedramcore_bankmachine3_next_state <= 1'd0;
-            end
         end
         3'd5: begin
-            litedramcore_bankmachine3_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine3_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine3_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine3_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
-                litedramcore_bankmachine3_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
-                                litedramcore_bankmachine3_next_state <= 2'd2;
-                            end
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
                         end else begin
-                            litedramcore_bankmachine3_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine3_next_state <= 2'd3;
                     end
                 end
             end
@@ -8088,18 +8714,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -8117,11 +8743,11 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
@@ -8139,13 +8765,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
-                                litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
+                                main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -8158,22 +8784,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -8188,8 +8814,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8207,14 +8833,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -8226,8 +8852,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8245,13 +8871,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
-                                litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
+                                main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -8264,8 +8890,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8283,13 +8909,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
-                                litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
+                                main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -8302,8 +8928,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8321,14 +8947,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
+                                main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
                             end
                         end else begin
                         end
@@ -8340,8 +8966,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8349,8 +8975,8 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine3_twtpcon_ready) begin
-                litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+            if (main_litedramcore_bankmachine3_twtpcon_ready) begin
+                main_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
             end
         end
         3'd5: begin
@@ -8366,15 +8992,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_row_open <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_row_open <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -8392,18 +9018,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -8417,12 +9043,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            litedramcore_bankmachine3_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -8433,18 +9059,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_row_close <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_row_close <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
-            litedramcore_bankmachine3_row_close <= 1'd1;
+            main_litedramcore_bankmachine3_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine3_row_close <= 1'd1;
+            main_litedramcore_bankmachine3_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine3_row_close <= 1'd1;
+            main_litedramcore_bankmachine3_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -8459,15 +9085,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -8484,174 +9110,207 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine3_state)
-        1'd1: begin
+assign main_litedramcore_bankmachine4_sink_valid = main_litedramcore_bankmachine4_req_valid;
+assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_sink_ready;
+assign main_litedramcore_bankmachine4_sink_payload_we = main_litedramcore_bankmachine4_req_we;
+assign main_litedramcore_bankmachine4_sink_payload_addr = main_litedramcore_bankmachine4_req_addr;
+assign main_litedramcore_bankmachine4_sink_sink_valid = main_litedramcore_bankmachine4_source_valid;
+assign main_litedramcore_bankmachine4_source_ready = main_litedramcore_bankmachine4_sink_sink_ready;
+assign main_litedramcore_bankmachine4_sink_sink_first = main_litedramcore_bankmachine4_source_first;
+assign main_litedramcore_bankmachine4_sink_sink_last = main_litedramcore_bankmachine4_source_last;
+assign main_litedramcore_bankmachine4_sink_sink_payload_we = main_litedramcore_bankmachine4_source_payload_we;
+assign main_litedramcore_bankmachine4_sink_sink_payload_addr = main_litedramcore_bankmachine4_source_payload_addr;
+assign main_litedramcore_bankmachine4_source_source_ready = (main_litedramcore_bankmachine4_req_wdata_ready | main_litedramcore_bankmachine4_req_rdata_valid);
+assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_source_valid | main_litedramcore_bankmachine4_source_source_valid);
+assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_source_source_payload_addr[21:7]);
+assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
+always @(*) begin
+    main_litedramcore_bankmachine4_cmd_payload_a <= 15'd0;
+    if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine4_cmd_payload_a <= main_litedramcore_bankmachine4_source_source_payload_addr[21:7];
+    end else begin
+        main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write);
+assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
+assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine4_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine4_source_valid & main_litedramcore_bankmachine4_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine4_source_payload_addr[21:7] != main_litedramcore_bankmachine4_source_source_payload_addr[21:7])) begin
+            main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine4_syncfifo4_din = {main_litedramcore_bankmachine4_fifo_in_last, main_litedramcore_bankmachine4_fifo_in_first, main_litedramcore_bankmachine4_fifo_in_payload_addr, main_litedramcore_bankmachine4_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout;
+assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout;
+assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout;
+assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout;
+assign main_litedramcore_bankmachine4_sink_ready = main_litedramcore_bankmachine4_syncfifo4_writable;
+assign main_litedramcore_bankmachine4_syncfifo4_we = main_litedramcore_bankmachine4_sink_valid;
+assign main_litedramcore_bankmachine4_fifo_in_first = main_litedramcore_bankmachine4_sink_first;
+assign main_litedramcore_bankmachine4_fifo_in_last = main_litedramcore_bankmachine4_sink_last;
+assign main_litedramcore_bankmachine4_fifo_in_payload_we = main_litedramcore_bankmachine4_sink_payload_we;
+assign main_litedramcore_bankmachine4_fifo_in_payload_addr = main_litedramcore_bankmachine4_sink_payload_addr;
+assign main_litedramcore_bankmachine4_source_valid = main_litedramcore_bankmachine4_syncfifo4_readable;
+assign main_litedramcore_bankmachine4_source_first = main_litedramcore_bankmachine4_fifo_out_first;
+assign main_litedramcore_bankmachine4_source_last = main_litedramcore_bankmachine4_fifo_out_last;
+assign main_litedramcore_bankmachine4_source_payload_we = main_litedramcore_bankmachine4_fifo_out_payload_we;
+assign main_litedramcore_bankmachine4_source_payload_addr = main_litedramcore_bankmachine4_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine4_syncfifo4_re = main_litedramcore_bankmachine4_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine4_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine4_replace) begin
+        main_litedramcore_bankmachine4_wrport_adr <= (main_litedramcore_bankmachine4_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine4_wrport_adr <= main_litedramcore_bankmachine4_produce;
+    end
+end
+assign main_litedramcore_bankmachine4_wrport_dat_w = main_litedramcore_bankmachine4_syncfifo4_din;
+assign main_litedramcore_bankmachine4_wrport_we = (main_litedramcore_bankmachine4_syncfifo4_we & (main_litedramcore_bankmachine4_syncfifo4_writable | main_litedramcore_bankmachine4_replace));
+assign main_litedramcore_bankmachine4_do_read = (main_litedramcore_bankmachine4_syncfifo4_readable & main_litedramcore_bankmachine4_syncfifo4_re);
+assign main_litedramcore_bankmachine4_rdport_adr = main_litedramcore_bankmachine4_consume;
+assign main_litedramcore_bankmachine4_syncfifo4_dout = main_litedramcore_bankmachine4_rdport_dat_r;
+assign main_litedramcore_bankmachine4_syncfifo4_writable = (main_litedramcore_bankmachine4_level != 5'd16);
+assign main_litedramcore_bankmachine4_syncfifo4_readable = (main_litedramcore_bankmachine4_level != 1'd0);
+assign main_litedramcore_bankmachine4_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine4_pipe_valid_source_valid) | main_litedramcore_bankmachine4_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine4_pipe_valid_sink_valid = main_litedramcore_bankmachine4_sink_sink_valid;
+assign main_litedramcore_bankmachine4_sink_sink_ready = main_litedramcore_bankmachine4_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine4_pipe_valid_sink_first = main_litedramcore_bankmachine4_sink_sink_first;
+assign main_litedramcore_bankmachine4_pipe_valid_sink_last = main_litedramcore_bankmachine4_sink_sink_last;
+assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_we = main_litedramcore_bankmachine4_sink_sink_payload_we;
+assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine4_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine4_source_source_valid = main_litedramcore_bankmachine4_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine4_pipe_valid_source_ready = main_litedramcore_bankmachine4_source_source_ready;
+assign main_litedramcore_bankmachine4_source_source_first = main_litedramcore_bankmachine4_pipe_valid_source_first;
+assign main_litedramcore_bankmachine4_source_source_last = main_litedramcore_bankmachine4_pipe_valid_source_last;
+assign main_litedramcore_bankmachine4_source_source_payload_we = main_litedramcore_bankmachine4_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine4_source_source_payload_addr = main_litedramcore_bankmachine4_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine4_next_state <= 4'd0;
+    builder_bankmachine4_next_state <= builder_bankmachine4_state;
+    case (builder_bankmachine4_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                if (main_litedramcore_bankmachine4_cmd_ready) begin
+                    builder_bankmachine4_next_state <= 3'd5;
+                end
+            end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                builder_bankmachine4_next_state <= 3'd5;
+            end
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                if (main_litedramcore_bankmachine4_cmd_ready) begin
+                    builder_bankmachine4_next_state <= 3'd7;
+                end
+            end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine4_refresh_req)) begin
+                builder_bankmachine4_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine4_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine4_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine4_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine4_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
+                builder_bankmachine4_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if ((main_litedramcore_bankmachine4_cmd_ready & main_litedramcore_bankmachine4_auto_precharge)) begin
+                                builder_bankmachine4_next_state <= 2'd2;
+                            end
                         end else begin
+                            builder_bankmachine4_next_state <= 1'd1;
                         end
                     end else begin
+                        builder_bankmachine4_next_state <= 2'd3;
                     end
                 end
             end
         end
     endcase
 end
-assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid;
-assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready;
-assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we;
-assign litedramcore_bankmachine4_sink_payload_addr = litedramcore_bankmachine4_req_addr;
-assign litedramcore_bankmachine4_sink_sink_valid = litedramcore_bankmachine4_source_valid;
-assign litedramcore_bankmachine4_source_ready = litedramcore_bankmachine4_sink_sink_ready;
-assign litedramcore_bankmachine4_sink_sink_first = litedramcore_bankmachine4_source_first;
-assign litedramcore_bankmachine4_sink_sink_last = litedramcore_bankmachine4_source_last;
-assign litedramcore_bankmachine4_sink_sink_payload_we = litedramcore_bankmachine4_source_payload_we;
-assign litedramcore_bankmachine4_sink_sink_payload_addr = litedramcore_bankmachine4_source_payload_addr;
-assign litedramcore_bankmachine4_source_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
-assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_source_valid | litedramcore_bankmachine4_source_source_valid);
-assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_source_source_payload_addr[21:7]);
-assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_a <= 15'd0;
-    if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
-        litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_source_source_payload_addr[21:7];
-    end else begin
-        litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
-assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
-assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
-always @(*) begin
-    litedramcore_bankmachine4_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine4_source_valid & litedramcore_bankmachine4_source_source_valid)) begin
-        if ((litedramcore_bankmachine4_source_payload_addr[21:7] != litedramcore_bankmachine4_source_source_payload_addr[21:7])) begin
-            litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine4_syncfifo4_din = {litedramcore_bankmachine4_fifo_in_last, litedramcore_bankmachine4_fifo_in_first, litedramcore_bankmachine4_fifo_in_payload_addr, litedramcore_bankmachine4_fifo_in_payload_we};
-assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
-assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
-assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
-assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
-assign litedramcore_bankmachine4_sink_ready = litedramcore_bankmachine4_syncfifo4_writable;
-assign litedramcore_bankmachine4_syncfifo4_we = litedramcore_bankmachine4_sink_valid;
-assign litedramcore_bankmachine4_fifo_in_first = litedramcore_bankmachine4_sink_first;
-assign litedramcore_bankmachine4_fifo_in_last = litedramcore_bankmachine4_sink_last;
-assign litedramcore_bankmachine4_fifo_in_payload_we = litedramcore_bankmachine4_sink_payload_we;
-assign litedramcore_bankmachine4_fifo_in_payload_addr = litedramcore_bankmachine4_sink_payload_addr;
-assign litedramcore_bankmachine4_source_valid = litedramcore_bankmachine4_syncfifo4_readable;
-assign litedramcore_bankmachine4_source_first = litedramcore_bankmachine4_fifo_out_first;
-assign litedramcore_bankmachine4_source_last = litedramcore_bankmachine4_fifo_out_last;
-assign litedramcore_bankmachine4_source_payload_we = litedramcore_bankmachine4_fifo_out_payload_we;
-assign litedramcore_bankmachine4_source_payload_addr = litedramcore_bankmachine4_fifo_out_payload_addr;
-assign litedramcore_bankmachine4_syncfifo4_re = litedramcore_bankmachine4_source_ready;
-always @(*) begin
-    litedramcore_bankmachine4_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine4_replace) begin
-        litedramcore_bankmachine4_wrport_adr <= (litedramcore_bankmachine4_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine4_wrport_adr <= litedramcore_bankmachine4_produce;
-    end
-end
-assign litedramcore_bankmachine4_wrport_dat_w = litedramcore_bankmachine4_syncfifo4_din;
-assign litedramcore_bankmachine4_wrport_we = (litedramcore_bankmachine4_syncfifo4_we & (litedramcore_bankmachine4_syncfifo4_writable | litedramcore_bankmachine4_replace));
-assign litedramcore_bankmachine4_do_read = (litedramcore_bankmachine4_syncfifo4_readable & litedramcore_bankmachine4_syncfifo4_re);
-assign litedramcore_bankmachine4_rdport_adr = litedramcore_bankmachine4_consume;
-assign litedramcore_bankmachine4_syncfifo4_dout = litedramcore_bankmachine4_rdport_dat_r;
-assign litedramcore_bankmachine4_syncfifo4_writable = (litedramcore_bankmachine4_level != 5'd16);
-assign litedramcore_bankmachine4_syncfifo4_readable = (litedramcore_bankmachine4_level != 1'd0);
-assign litedramcore_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready);
-assign litedramcore_bankmachine4_pipe_valid_sink_valid = litedramcore_bankmachine4_sink_sink_valid;
-assign litedramcore_bankmachine4_sink_sink_ready = litedramcore_bankmachine4_pipe_valid_sink_ready;
-assign litedramcore_bankmachine4_pipe_valid_sink_first = litedramcore_bankmachine4_sink_sink_first;
-assign litedramcore_bankmachine4_pipe_valid_sink_last = litedramcore_bankmachine4_sink_sink_last;
-assign litedramcore_bankmachine4_pipe_valid_sink_payload_we = litedramcore_bankmachine4_sink_sink_payload_we;
-assign litedramcore_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_bankmachine4_sink_sink_payload_addr;
-assign litedramcore_bankmachine4_source_source_valid = litedramcore_bankmachine4_pipe_valid_source_valid;
-assign litedramcore_bankmachine4_pipe_valid_source_ready = litedramcore_bankmachine4_source_source_ready;
-assign litedramcore_bankmachine4_source_source_first = litedramcore_bankmachine4_pipe_valid_source_first;
-assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_pipe_valid_source_last;
-assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine4_next_state <= 4'd0;
-    litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
-    case (litedramcore_bankmachine4_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                if (litedramcore_bankmachine4_cmd_ready) begin
-                    litedramcore_bankmachine4_next_state <= 3'd5;
-                end
+    main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine4_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                if (litedramcore_bankmachine4_cmd_ready) begin
-                    litedramcore_bankmachine4_next_state <= 3'd7;
-                end
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine4_refresh_req)) begin
-                litedramcore_bankmachine4_next_state <= 1'd0;
-            end
+            main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine4_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
         end
         3'd5: begin
-            litedramcore_bankmachine4_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine4_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine4_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine4_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
-                litedramcore_bankmachine4_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
-                                litedramcore_bankmachine4_next_state <= 2'd2;
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
+                            end else begin
+                                main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
-                            litedramcore_bankmachine4_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine4_next_state <= 2'd3;
                     end
                 end
             end
@@ -8659,8 +9318,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8678,13 +9337,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
-                                litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
+                                main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -8697,8 +9356,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8716,13 +9375,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
-                                litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
+                                main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -8735,8 +9394,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8754,14 +9413,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
+                                main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready;
                             end
                         end else begin
                         end
@@ -8773,8 +9432,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8782,8 +9441,8 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine4_twtpcon_ready) begin
-                litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+            if (main_litedramcore_bankmachine4_twtpcon_ready) begin
+                main_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
             end
         end
         3'd5: begin
@@ -8799,15 +9458,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_row_open <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_row_open <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -8825,18 +9484,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_valid <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -8850,12 +9509,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            litedramcore_bankmachine4_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -8866,18 +9525,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_row_close <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_row_close <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            litedramcore_bankmachine4_row_close <= 1'd1;
+            main_litedramcore_bankmachine4_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine4_row_close <= 1'd1;
+            main_litedramcore_bankmachine4_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine4_row_close <= 1'd1;
+            main_litedramcore_bankmachine4_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -8892,15 +9551,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -8918,8 +9577,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8937,12 +9596,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -8953,18 +9612,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -8982,11 +9641,11 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
@@ -9004,13 +9663,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
-                                litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
+                                main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -9022,207 +9681,177 @@ always @(*) begin
         end
     endcase
 end
+assign main_litedramcore_bankmachine5_sink_valid = main_litedramcore_bankmachine5_req_valid;
+assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_sink_ready;
+assign main_litedramcore_bankmachine5_sink_payload_we = main_litedramcore_bankmachine5_req_we;
+assign main_litedramcore_bankmachine5_sink_payload_addr = main_litedramcore_bankmachine5_req_addr;
+assign main_litedramcore_bankmachine5_sink_sink_valid = main_litedramcore_bankmachine5_source_valid;
+assign main_litedramcore_bankmachine5_source_ready = main_litedramcore_bankmachine5_sink_sink_ready;
+assign main_litedramcore_bankmachine5_sink_sink_first = main_litedramcore_bankmachine5_source_first;
+assign main_litedramcore_bankmachine5_sink_sink_last = main_litedramcore_bankmachine5_source_last;
+assign main_litedramcore_bankmachine5_sink_sink_payload_we = main_litedramcore_bankmachine5_source_payload_we;
+assign main_litedramcore_bankmachine5_sink_sink_payload_addr = main_litedramcore_bankmachine5_source_payload_addr;
+assign main_litedramcore_bankmachine5_source_source_ready = (main_litedramcore_bankmachine5_req_wdata_ready | main_litedramcore_bankmachine5_req_rdata_valid);
+assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_source_valid | main_litedramcore_bankmachine5_source_source_valid);
+assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_source_source_payload_addr[21:7]);
+assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine4_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+    main_litedramcore_bankmachine5_cmd_payload_a <= 15'd0;
+    if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine5_cmd_payload_a <= main_litedramcore_bankmachine5_source_source_payload_addr[21:7];
+    end else begin
+        main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write);
+assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
+assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine5_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine5_source_valid & main_litedramcore_bankmachine5_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine5_source_payload_addr[21:7] != main_litedramcore_bankmachine5_source_source_payload_addr[21:7])) begin
+            main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine5_syncfifo5_din = {main_litedramcore_bankmachine5_fifo_in_last, main_litedramcore_bankmachine5_fifo_in_first, main_litedramcore_bankmachine5_fifo_in_payload_addr, main_litedramcore_bankmachine5_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout;
+assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout;
+assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout;
+assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout;
+assign main_litedramcore_bankmachine5_sink_ready = main_litedramcore_bankmachine5_syncfifo5_writable;
+assign main_litedramcore_bankmachine5_syncfifo5_we = main_litedramcore_bankmachine5_sink_valid;
+assign main_litedramcore_bankmachine5_fifo_in_first = main_litedramcore_bankmachine5_sink_first;
+assign main_litedramcore_bankmachine5_fifo_in_last = main_litedramcore_bankmachine5_sink_last;
+assign main_litedramcore_bankmachine5_fifo_in_payload_we = main_litedramcore_bankmachine5_sink_payload_we;
+assign main_litedramcore_bankmachine5_fifo_in_payload_addr = main_litedramcore_bankmachine5_sink_payload_addr;
+assign main_litedramcore_bankmachine5_source_valid = main_litedramcore_bankmachine5_syncfifo5_readable;
+assign main_litedramcore_bankmachine5_source_first = main_litedramcore_bankmachine5_fifo_out_first;
+assign main_litedramcore_bankmachine5_source_last = main_litedramcore_bankmachine5_fifo_out_last;
+assign main_litedramcore_bankmachine5_source_payload_we = main_litedramcore_bankmachine5_fifo_out_payload_we;
+assign main_litedramcore_bankmachine5_source_payload_addr = main_litedramcore_bankmachine5_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine5_syncfifo5_re = main_litedramcore_bankmachine5_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine5_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine5_replace) begin
+        main_litedramcore_bankmachine5_wrport_adr <= (main_litedramcore_bankmachine5_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine5_wrport_adr <= main_litedramcore_bankmachine5_produce;
+    end
+end
+assign main_litedramcore_bankmachine5_wrport_dat_w = main_litedramcore_bankmachine5_syncfifo5_din;
+assign main_litedramcore_bankmachine5_wrport_we = (main_litedramcore_bankmachine5_syncfifo5_we & (main_litedramcore_bankmachine5_syncfifo5_writable | main_litedramcore_bankmachine5_replace));
+assign main_litedramcore_bankmachine5_do_read = (main_litedramcore_bankmachine5_syncfifo5_readable & main_litedramcore_bankmachine5_syncfifo5_re);
+assign main_litedramcore_bankmachine5_rdport_adr = main_litedramcore_bankmachine5_consume;
+assign main_litedramcore_bankmachine5_syncfifo5_dout = main_litedramcore_bankmachine5_rdport_dat_r;
+assign main_litedramcore_bankmachine5_syncfifo5_writable = (main_litedramcore_bankmachine5_level != 5'd16);
+assign main_litedramcore_bankmachine5_syncfifo5_readable = (main_litedramcore_bankmachine5_level != 1'd0);
+assign main_litedramcore_bankmachine5_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine5_pipe_valid_source_valid) | main_litedramcore_bankmachine5_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine5_pipe_valid_sink_valid = main_litedramcore_bankmachine5_sink_sink_valid;
+assign main_litedramcore_bankmachine5_sink_sink_ready = main_litedramcore_bankmachine5_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine5_pipe_valid_sink_first = main_litedramcore_bankmachine5_sink_sink_first;
+assign main_litedramcore_bankmachine5_pipe_valid_sink_last = main_litedramcore_bankmachine5_sink_sink_last;
+assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_we = main_litedramcore_bankmachine5_sink_sink_payload_we;
+assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine5_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine5_source_source_valid = main_litedramcore_bankmachine5_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine5_pipe_valid_source_ready = main_litedramcore_bankmachine5_source_source_ready;
+assign main_litedramcore_bankmachine5_source_source_first = main_litedramcore_bankmachine5_pipe_valid_source_first;
+assign main_litedramcore_bankmachine5_source_source_last = main_litedramcore_bankmachine5_pipe_valid_source_last;
+assign main_litedramcore_bankmachine5_source_source_payload_we = main_litedramcore_bankmachine5_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine5_source_source_payload_addr = main_litedramcore_bankmachine5_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine5_next_state <= 4'd0;
+    builder_bankmachine5_next_state <= builder_bankmachine5_state;
+    case (builder_bankmachine5_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                if (main_litedramcore_bankmachine5_cmd_ready) begin
+                    builder_bankmachine5_next_state <= 3'd5;
+                end
             end
         end
         2'd2: begin
-        end
-        2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                builder_bankmachine5_next_state <= 3'd5;
             end
         end
-        3'd4: begin
-            litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine4_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
         2'd3: begin
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                if (main_litedramcore_bankmachine5_cmd_ready) begin
+                    builder_bankmachine5_next_state <= 3'd7;
+                end
+            end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine5_refresh_req)) begin
+                builder_bankmachine5_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine5_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine5_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine5_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine5_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
+                builder_bankmachine5_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin
+                                builder_bankmachine5_next_state <= 2'd2;
                             end
                         end else begin
+                            builder_bankmachine5_next_state <= 1'd1;
                         end
                     end else begin
+                        builder_bankmachine5_next_state <= 2'd3;
                     end
                 end
             end
         end
     endcase
 end
-assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid;
-assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready;
-assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we;
-assign litedramcore_bankmachine5_sink_payload_addr = litedramcore_bankmachine5_req_addr;
-assign litedramcore_bankmachine5_sink_sink_valid = litedramcore_bankmachine5_source_valid;
-assign litedramcore_bankmachine5_source_ready = litedramcore_bankmachine5_sink_sink_ready;
-assign litedramcore_bankmachine5_sink_sink_first = litedramcore_bankmachine5_source_first;
-assign litedramcore_bankmachine5_sink_sink_last = litedramcore_bankmachine5_source_last;
-assign litedramcore_bankmachine5_sink_sink_payload_we = litedramcore_bankmachine5_source_payload_we;
-assign litedramcore_bankmachine5_sink_sink_payload_addr = litedramcore_bankmachine5_source_payload_addr;
-assign litedramcore_bankmachine5_source_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
-assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_source_valid | litedramcore_bankmachine5_source_source_valid);
-assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_source_source_payload_addr[21:7]);
-assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_a <= 15'd0;
-    if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
-        litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_source_source_payload_addr[21:7];
-    end else begin
-        litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
-assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
-assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
-always @(*) begin
-    litedramcore_bankmachine5_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine5_source_valid & litedramcore_bankmachine5_source_source_valid)) begin
-        if ((litedramcore_bankmachine5_source_payload_addr[21:7] != litedramcore_bankmachine5_source_source_payload_addr[21:7])) begin
-            litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine5_syncfifo5_din = {litedramcore_bankmachine5_fifo_in_last, litedramcore_bankmachine5_fifo_in_first, litedramcore_bankmachine5_fifo_in_payload_addr, litedramcore_bankmachine5_fifo_in_payload_we};
-assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
-assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
-assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
-assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
-assign litedramcore_bankmachine5_sink_ready = litedramcore_bankmachine5_syncfifo5_writable;
-assign litedramcore_bankmachine5_syncfifo5_we = litedramcore_bankmachine5_sink_valid;
-assign litedramcore_bankmachine5_fifo_in_first = litedramcore_bankmachine5_sink_first;
-assign litedramcore_bankmachine5_fifo_in_last = litedramcore_bankmachine5_sink_last;
-assign litedramcore_bankmachine5_fifo_in_payload_we = litedramcore_bankmachine5_sink_payload_we;
-assign litedramcore_bankmachine5_fifo_in_payload_addr = litedramcore_bankmachine5_sink_payload_addr;
-assign litedramcore_bankmachine5_source_valid = litedramcore_bankmachine5_syncfifo5_readable;
-assign litedramcore_bankmachine5_source_first = litedramcore_bankmachine5_fifo_out_first;
-assign litedramcore_bankmachine5_source_last = litedramcore_bankmachine5_fifo_out_last;
-assign litedramcore_bankmachine5_source_payload_we = litedramcore_bankmachine5_fifo_out_payload_we;
-assign litedramcore_bankmachine5_source_payload_addr = litedramcore_bankmachine5_fifo_out_payload_addr;
-assign litedramcore_bankmachine5_syncfifo5_re = litedramcore_bankmachine5_source_ready;
-always @(*) begin
-    litedramcore_bankmachine5_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine5_replace) begin
-        litedramcore_bankmachine5_wrport_adr <= (litedramcore_bankmachine5_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine5_wrport_adr <= litedramcore_bankmachine5_produce;
-    end
-end
-assign litedramcore_bankmachine5_wrport_dat_w = litedramcore_bankmachine5_syncfifo5_din;
-assign litedramcore_bankmachine5_wrport_we = (litedramcore_bankmachine5_syncfifo5_we & (litedramcore_bankmachine5_syncfifo5_writable | litedramcore_bankmachine5_replace));
-assign litedramcore_bankmachine5_do_read = (litedramcore_bankmachine5_syncfifo5_readable & litedramcore_bankmachine5_syncfifo5_re);
-assign litedramcore_bankmachine5_rdport_adr = litedramcore_bankmachine5_consume;
-assign litedramcore_bankmachine5_syncfifo5_dout = litedramcore_bankmachine5_rdport_dat_r;
-assign litedramcore_bankmachine5_syncfifo5_writable = (litedramcore_bankmachine5_level != 5'd16);
-assign litedramcore_bankmachine5_syncfifo5_readable = (litedramcore_bankmachine5_level != 1'd0);
-assign litedramcore_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready);
-assign litedramcore_bankmachine5_pipe_valid_sink_valid = litedramcore_bankmachine5_sink_sink_valid;
-assign litedramcore_bankmachine5_sink_sink_ready = litedramcore_bankmachine5_pipe_valid_sink_ready;
-assign litedramcore_bankmachine5_pipe_valid_sink_first = litedramcore_bankmachine5_sink_sink_first;
-assign litedramcore_bankmachine5_pipe_valid_sink_last = litedramcore_bankmachine5_sink_sink_last;
-assign litedramcore_bankmachine5_pipe_valid_sink_payload_we = litedramcore_bankmachine5_sink_sink_payload_we;
-assign litedramcore_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_bankmachine5_sink_sink_payload_addr;
-assign litedramcore_bankmachine5_source_source_valid = litedramcore_bankmachine5_pipe_valid_source_valid;
-assign litedramcore_bankmachine5_pipe_valid_source_ready = litedramcore_bankmachine5_source_source_ready;
-assign litedramcore_bankmachine5_source_source_first = litedramcore_bankmachine5_pipe_valid_source_first;
-assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_pipe_valid_source_last;
-assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine5_next_state <= 4'd0;
-    litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
-    case (litedramcore_bankmachine5_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                if (litedramcore_bankmachine5_cmd_ready) begin
-                    litedramcore_bankmachine5_next_state <= 3'd5;
-                end
-            end
+    main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine5_state)
+        1'd1: begin
         end
         2'd2: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                if (litedramcore_bankmachine5_cmd_ready) begin
-                    litedramcore_bankmachine5_next_state <= 3'd7;
-                end
-            end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine5_refresh_req)) begin
-                litedramcore_bankmachine5_next_state <= 1'd0;
-            end
         end
         3'd5: begin
-            litedramcore_bankmachine5_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine5_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine5_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine5_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
-                litedramcore_bankmachine5_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
-                                litedramcore_bankmachine5_next_state <= 2'd2;
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
+                            end else begin
+                                main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
                             end
                         end else begin
-                            litedramcore_bankmachine5_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine5_next_state <= 2'd3;
                     end
                 end
             end
@@ -9230,18 +9859,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_row_open <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_row_open <= 1'd1;
-            end
         end
         3'd4: begin
+            if (main_litedramcore_bankmachine5_twtpcon_ready) begin
+                main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -9256,18 +9885,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_valid <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -9281,12 +9910,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            litedramcore_bankmachine5_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -9297,18 +9926,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_row_close <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_row_close <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
-            litedramcore_bankmachine5_row_close <= 1'd1;
+            main_litedramcore_bankmachine5_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine5_row_close <= 1'd1;
+            main_litedramcore_bankmachine5_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine5_row_close <= 1'd1;
+            main_litedramcore_bankmachine5_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -9323,18 +9952,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_row_open <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_row_open <= 1'd1;
+            end
         end
         3'd4: begin
-            if (litedramcore_bankmachine5_twtpcon_ready) begin
-                litedramcore_bankmachine5_refresh_gnt <= 1'd1;
-            end
         end
         3'd5: begin
         end
@@ -9349,15 +9978,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -9375,8 +10004,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9394,12 +10023,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -9410,18 +10039,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -9439,11 +10068,11 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
@@ -9461,13 +10090,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
-                                litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
+                                main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -9480,22 +10109,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -9510,8 +10139,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9529,14 +10158,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -9548,8 +10177,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9567,13 +10196,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
-                                litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
+                                main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -9586,8 +10215,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9605,13 +10234,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
-                                litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
+                                main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -9623,193 +10252,181 @@ always @(*) begin
         end
     endcase
 end
+assign main_litedramcore_bankmachine6_sink_valid = main_litedramcore_bankmachine6_req_valid;
+assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_sink_ready;
+assign main_litedramcore_bankmachine6_sink_payload_we = main_litedramcore_bankmachine6_req_we;
+assign main_litedramcore_bankmachine6_sink_payload_addr = main_litedramcore_bankmachine6_req_addr;
+assign main_litedramcore_bankmachine6_sink_sink_valid = main_litedramcore_bankmachine6_source_valid;
+assign main_litedramcore_bankmachine6_source_ready = main_litedramcore_bankmachine6_sink_sink_ready;
+assign main_litedramcore_bankmachine6_sink_sink_first = main_litedramcore_bankmachine6_source_first;
+assign main_litedramcore_bankmachine6_sink_sink_last = main_litedramcore_bankmachine6_source_last;
+assign main_litedramcore_bankmachine6_sink_sink_payload_we = main_litedramcore_bankmachine6_source_payload_we;
+assign main_litedramcore_bankmachine6_sink_sink_payload_addr = main_litedramcore_bankmachine6_source_payload_addr;
+assign main_litedramcore_bankmachine6_source_source_ready = (main_litedramcore_bankmachine6_req_wdata_ready | main_litedramcore_bankmachine6_req_rdata_valid);
+assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_source_valid | main_litedramcore_bankmachine6_source_source_valid);
+assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_source_source_payload_addr[21:7]);
+assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
 always @(*) begin
-    litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine5_state)
-        1'd1: begin
+    main_litedramcore_bankmachine6_cmd_payload_a <= 15'd0;
+    if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine6_cmd_payload_a <= main_litedramcore_bankmachine6_source_source_payload_addr[21:7];
+    end else begin
+        main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write);
+assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
+assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine6_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine6_source_valid & main_litedramcore_bankmachine6_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine6_source_payload_addr[21:7] != main_litedramcore_bankmachine6_source_source_payload_addr[21:7])) begin
+            main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine6_syncfifo6_din = {main_litedramcore_bankmachine6_fifo_in_last, main_litedramcore_bankmachine6_fifo_in_first, main_litedramcore_bankmachine6_fifo_in_payload_addr, main_litedramcore_bankmachine6_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout;
+assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout;
+assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout;
+assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout;
+assign main_litedramcore_bankmachine6_sink_ready = main_litedramcore_bankmachine6_syncfifo6_writable;
+assign main_litedramcore_bankmachine6_syncfifo6_we = main_litedramcore_bankmachine6_sink_valid;
+assign main_litedramcore_bankmachine6_fifo_in_first = main_litedramcore_bankmachine6_sink_first;
+assign main_litedramcore_bankmachine6_fifo_in_last = main_litedramcore_bankmachine6_sink_last;
+assign main_litedramcore_bankmachine6_fifo_in_payload_we = main_litedramcore_bankmachine6_sink_payload_we;
+assign main_litedramcore_bankmachine6_fifo_in_payload_addr = main_litedramcore_bankmachine6_sink_payload_addr;
+assign main_litedramcore_bankmachine6_source_valid = main_litedramcore_bankmachine6_syncfifo6_readable;
+assign main_litedramcore_bankmachine6_source_first = main_litedramcore_bankmachine6_fifo_out_first;
+assign main_litedramcore_bankmachine6_source_last = main_litedramcore_bankmachine6_fifo_out_last;
+assign main_litedramcore_bankmachine6_source_payload_we = main_litedramcore_bankmachine6_fifo_out_payload_we;
+assign main_litedramcore_bankmachine6_source_payload_addr = main_litedramcore_bankmachine6_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine6_syncfifo6_re = main_litedramcore_bankmachine6_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine6_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine6_replace) begin
+        main_litedramcore_bankmachine6_wrport_adr <= (main_litedramcore_bankmachine6_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine6_wrport_adr <= main_litedramcore_bankmachine6_produce;
+    end
+end
+assign main_litedramcore_bankmachine6_wrport_dat_w = main_litedramcore_bankmachine6_syncfifo6_din;
+assign main_litedramcore_bankmachine6_wrport_we = (main_litedramcore_bankmachine6_syncfifo6_we & (main_litedramcore_bankmachine6_syncfifo6_writable | main_litedramcore_bankmachine6_replace));
+assign main_litedramcore_bankmachine6_do_read = (main_litedramcore_bankmachine6_syncfifo6_readable & main_litedramcore_bankmachine6_syncfifo6_re);
+assign main_litedramcore_bankmachine6_rdport_adr = main_litedramcore_bankmachine6_consume;
+assign main_litedramcore_bankmachine6_syncfifo6_dout = main_litedramcore_bankmachine6_rdport_dat_r;
+assign main_litedramcore_bankmachine6_syncfifo6_writable = (main_litedramcore_bankmachine6_level != 5'd16);
+assign main_litedramcore_bankmachine6_syncfifo6_readable = (main_litedramcore_bankmachine6_level != 1'd0);
+assign main_litedramcore_bankmachine6_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine6_pipe_valid_source_valid) | main_litedramcore_bankmachine6_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine6_pipe_valid_sink_valid = main_litedramcore_bankmachine6_sink_sink_valid;
+assign main_litedramcore_bankmachine6_sink_sink_ready = main_litedramcore_bankmachine6_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine6_pipe_valid_sink_first = main_litedramcore_bankmachine6_sink_sink_first;
+assign main_litedramcore_bankmachine6_pipe_valid_sink_last = main_litedramcore_bankmachine6_sink_sink_last;
+assign main_litedramcore_bankmachine6_pipe_valid_sink_payload_we = main_litedramcore_bankmachine6_sink_sink_payload_we;
+assign main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine6_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine6_source_source_valid = main_litedramcore_bankmachine6_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine6_pipe_valid_source_ready = main_litedramcore_bankmachine6_source_source_ready;
+assign main_litedramcore_bankmachine6_source_source_first = main_litedramcore_bankmachine6_pipe_valid_source_first;
+assign main_litedramcore_bankmachine6_source_source_last = main_litedramcore_bankmachine6_pipe_valid_source_last;
+assign main_litedramcore_bankmachine6_source_source_payload_we = main_litedramcore_bankmachine6_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine6_source_source_payload_addr = main_litedramcore_bankmachine6_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine6_next_state <= 4'd0;
+    builder_bankmachine6_next_state <= builder_bankmachine6_state;
+    case (builder_bankmachine6_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                if (main_litedramcore_bankmachine6_cmd_ready) begin
+                    builder_bankmachine6_next_state <= 3'd5;
+                end
+            end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                builder_bankmachine6_next_state <= 3'd5;
+            end
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                if (main_litedramcore_bankmachine6_cmd_ready) begin
+                    builder_bankmachine6_next_state <= 3'd7;
+                end
+            end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine6_refresh_req)) begin
+                builder_bankmachine6_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine6_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine6_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine6_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine6_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
+                builder_bankmachine6_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if ((main_litedramcore_bankmachine6_cmd_ready & main_litedramcore_bankmachine6_auto_precharge)) begin
+                                builder_bankmachine6_next_state <= 2'd2;
                             end
                         end else begin
+                            builder_bankmachine6_next_state <= 1'd1;
                         end
                     end else begin
+                        builder_bankmachine6_next_state <= 2'd3;
                     end
                 end
             end
         end
     endcase
 end
-assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid;
-assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready;
-assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we;
-assign litedramcore_bankmachine6_sink_payload_addr = litedramcore_bankmachine6_req_addr;
-assign litedramcore_bankmachine6_sink_sink_valid = litedramcore_bankmachine6_source_valid;
-assign litedramcore_bankmachine6_source_ready = litedramcore_bankmachine6_sink_sink_ready;
-assign litedramcore_bankmachine6_sink_sink_first = litedramcore_bankmachine6_source_first;
-assign litedramcore_bankmachine6_sink_sink_last = litedramcore_bankmachine6_source_last;
-assign litedramcore_bankmachine6_sink_sink_payload_we = litedramcore_bankmachine6_source_payload_we;
-assign litedramcore_bankmachine6_sink_sink_payload_addr = litedramcore_bankmachine6_source_payload_addr;
-assign litedramcore_bankmachine6_source_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
-assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_source_valid | litedramcore_bankmachine6_source_source_valid);
-assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_source_source_payload_addr[21:7]);
-assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_a <= 15'd0;
-    if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
-        litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_source_source_payload_addr[21:7];
-    end else begin
-        litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
-assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
-assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
-always @(*) begin
-    litedramcore_bankmachine6_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine6_source_valid & litedramcore_bankmachine6_source_source_valid)) begin
-        if ((litedramcore_bankmachine6_source_payload_addr[21:7] != litedramcore_bankmachine6_source_source_payload_addr[21:7])) begin
-            litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine6_syncfifo6_din = {litedramcore_bankmachine6_fifo_in_last, litedramcore_bankmachine6_fifo_in_first, litedramcore_bankmachine6_fifo_in_payload_addr, litedramcore_bankmachine6_fifo_in_payload_we};
-assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
-assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
-assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
-assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
-assign litedramcore_bankmachine6_sink_ready = litedramcore_bankmachine6_syncfifo6_writable;
-assign litedramcore_bankmachine6_syncfifo6_we = litedramcore_bankmachine6_sink_valid;
-assign litedramcore_bankmachine6_fifo_in_first = litedramcore_bankmachine6_sink_first;
-assign litedramcore_bankmachine6_fifo_in_last = litedramcore_bankmachine6_sink_last;
-assign litedramcore_bankmachine6_fifo_in_payload_we = litedramcore_bankmachine6_sink_payload_we;
-assign litedramcore_bankmachine6_fifo_in_payload_addr = litedramcore_bankmachine6_sink_payload_addr;
-assign litedramcore_bankmachine6_source_valid = litedramcore_bankmachine6_syncfifo6_readable;
-assign litedramcore_bankmachine6_source_first = litedramcore_bankmachine6_fifo_out_first;
-assign litedramcore_bankmachine6_source_last = litedramcore_bankmachine6_fifo_out_last;
-assign litedramcore_bankmachine6_source_payload_we = litedramcore_bankmachine6_fifo_out_payload_we;
-assign litedramcore_bankmachine6_source_payload_addr = litedramcore_bankmachine6_fifo_out_payload_addr;
-assign litedramcore_bankmachine6_syncfifo6_re = litedramcore_bankmachine6_source_ready;
-always @(*) begin
-    litedramcore_bankmachine6_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine6_replace) begin
-        litedramcore_bankmachine6_wrport_adr <= (litedramcore_bankmachine6_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine6_wrport_adr <= litedramcore_bankmachine6_produce;
-    end
-end
-assign litedramcore_bankmachine6_wrport_dat_w = litedramcore_bankmachine6_syncfifo6_din;
-assign litedramcore_bankmachine6_wrport_we = (litedramcore_bankmachine6_syncfifo6_we & (litedramcore_bankmachine6_syncfifo6_writable | litedramcore_bankmachine6_replace));
-assign litedramcore_bankmachine6_do_read = (litedramcore_bankmachine6_syncfifo6_readable & litedramcore_bankmachine6_syncfifo6_re);
-assign litedramcore_bankmachine6_rdport_adr = litedramcore_bankmachine6_consume;
-assign litedramcore_bankmachine6_syncfifo6_dout = litedramcore_bankmachine6_rdport_dat_r;
-assign litedramcore_bankmachine6_syncfifo6_writable = (litedramcore_bankmachine6_level != 5'd16);
-assign litedramcore_bankmachine6_syncfifo6_readable = (litedramcore_bankmachine6_level != 1'd0);
-assign litedramcore_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready);
-assign litedramcore_bankmachine6_pipe_valid_sink_valid = litedramcore_bankmachine6_sink_sink_valid;
-assign litedramcore_bankmachine6_sink_sink_ready = litedramcore_bankmachine6_pipe_valid_sink_ready;
-assign litedramcore_bankmachine6_pipe_valid_sink_first = litedramcore_bankmachine6_sink_sink_first;
-assign litedramcore_bankmachine6_pipe_valid_sink_last = litedramcore_bankmachine6_sink_sink_last;
-assign litedramcore_bankmachine6_pipe_valid_sink_payload_we = litedramcore_bankmachine6_sink_sink_payload_we;
-assign litedramcore_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_bankmachine6_sink_sink_payload_addr;
-assign litedramcore_bankmachine6_source_source_valid = litedramcore_bankmachine6_pipe_valid_source_valid;
-assign litedramcore_bankmachine6_pipe_valid_source_ready = litedramcore_bankmachine6_source_source_ready;
-assign litedramcore_bankmachine6_source_source_first = litedramcore_bankmachine6_pipe_valid_source_first;
-assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_pipe_valid_source_last;
-assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine6_next_state <= 4'd0;
-    litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
-    case (litedramcore_bankmachine6_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                if (litedramcore_bankmachine6_cmd_ready) begin
-                    litedramcore_bankmachine6_next_state <= 3'd5;
-                end
-            end
+    main_litedramcore_bankmachine6_row_close <= 1'd0;
+    case (builder_bankmachine6_state)
+        1'd1: begin
+            main_litedramcore_bankmachine6_row_close <= 1'd1;
         end
         2'd2: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_next_state <= 3'd5;
-            end
+            main_litedramcore_bankmachine6_row_close <= 1'd1;
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                if (litedramcore_bankmachine6_cmd_ready) begin
-                    litedramcore_bankmachine6_next_state <= 3'd7;
-                end
-            end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine6_refresh_req)) begin
-                litedramcore_bankmachine6_next_state <= 1'd0;
-            end
+            main_litedramcore_bankmachine6_row_close <= 1'd1;
         end
         3'd5: begin
-            litedramcore_bankmachine6_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine6_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine6_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine6_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
-                litedramcore_bankmachine6_next_state <= 3'd4;
-            end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
-                                litedramcore_bankmachine6_next_state <= 2'd2;
-                            end
-                        end else begin
-                            litedramcore_bankmachine6_next_state <= 1'd1;
-                        end
-                    end else begin
-                        litedramcore_bankmachine6_next_state <= 2'd3;
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -9827,8 +10444,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9846,12 +10463,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -9862,18 +10479,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -9891,11 +10508,11 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
@@ -9913,13 +10530,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
-                                litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
+                                main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -9932,22 +10549,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -9962,8 +10579,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9981,14 +10598,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -10000,8 +10617,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -10019,13 +10636,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
-                                litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
+                                main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -10038,8 +10655,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -10057,13 +10674,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
-                                litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
+                                main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -10076,8 +10693,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -10095,14 +10712,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
+                                main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
                             end
                         end else begin
                         end
@@ -10114,8 +10731,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -10123,8 +10740,8 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine6_twtpcon_ready) begin
-                litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+            if (main_litedramcore_bankmachine6_twtpcon_ready) begin
+                main_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
             end
         end
         3'd5: begin
@@ -10140,15 +10757,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_row_open <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_row_open <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -10166,18 +10783,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -10191,12 +10808,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            litedramcore_bankmachine6_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -10206,165 +10823,174 @@ always @(*) begin
         end
     endcase
 end
+assign main_litedramcore_bankmachine7_sink_valid = main_litedramcore_bankmachine7_req_valid;
+assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_sink_ready;
+assign main_litedramcore_bankmachine7_sink_payload_we = main_litedramcore_bankmachine7_req_we;
+assign main_litedramcore_bankmachine7_sink_payload_addr = main_litedramcore_bankmachine7_req_addr;
+assign main_litedramcore_bankmachine7_sink_sink_valid = main_litedramcore_bankmachine7_source_valid;
+assign main_litedramcore_bankmachine7_source_ready = main_litedramcore_bankmachine7_sink_sink_ready;
+assign main_litedramcore_bankmachine7_sink_sink_first = main_litedramcore_bankmachine7_source_first;
+assign main_litedramcore_bankmachine7_sink_sink_last = main_litedramcore_bankmachine7_source_last;
+assign main_litedramcore_bankmachine7_sink_sink_payload_we = main_litedramcore_bankmachine7_source_payload_we;
+assign main_litedramcore_bankmachine7_sink_sink_payload_addr = main_litedramcore_bankmachine7_source_payload_addr;
+assign main_litedramcore_bankmachine7_source_source_ready = (main_litedramcore_bankmachine7_req_wdata_ready | main_litedramcore_bankmachine7_req_rdata_valid);
+assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_source_valid | main_litedramcore_bankmachine7_source_source_valid);
+assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_source_source_payload_addr[21:7]);
+assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
 always @(*) begin
-    litedramcore_bankmachine6_row_close <= 1'd0;
-    case (litedramcore_bankmachine6_state)
-        1'd1: begin
-            litedramcore_bankmachine6_row_close <= 1'd1;
+    main_litedramcore_bankmachine7_cmd_payload_a <= 15'd0;
+    if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine7_cmd_payload_a <= main_litedramcore_bankmachine7_source_source_payload_addr[21:7];
+    end else begin
+        main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write);
+assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
+assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine7_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine7_source_valid & main_litedramcore_bankmachine7_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine7_source_payload_addr[21:7] != main_litedramcore_bankmachine7_source_source_payload_addr[21:7])) begin
+            main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine7_syncfifo7_din = {main_litedramcore_bankmachine7_fifo_in_last, main_litedramcore_bankmachine7_fifo_in_first, main_litedramcore_bankmachine7_fifo_in_payload_addr, main_litedramcore_bankmachine7_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout;
+assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout;
+assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout;
+assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout;
+assign main_litedramcore_bankmachine7_sink_ready = main_litedramcore_bankmachine7_syncfifo7_writable;
+assign main_litedramcore_bankmachine7_syncfifo7_we = main_litedramcore_bankmachine7_sink_valid;
+assign main_litedramcore_bankmachine7_fifo_in_first = main_litedramcore_bankmachine7_sink_first;
+assign main_litedramcore_bankmachine7_fifo_in_last = main_litedramcore_bankmachine7_sink_last;
+assign main_litedramcore_bankmachine7_fifo_in_payload_we = main_litedramcore_bankmachine7_sink_payload_we;
+assign main_litedramcore_bankmachine7_fifo_in_payload_addr = main_litedramcore_bankmachine7_sink_payload_addr;
+assign main_litedramcore_bankmachine7_source_valid = main_litedramcore_bankmachine7_syncfifo7_readable;
+assign main_litedramcore_bankmachine7_source_first = main_litedramcore_bankmachine7_fifo_out_first;
+assign main_litedramcore_bankmachine7_source_last = main_litedramcore_bankmachine7_fifo_out_last;
+assign main_litedramcore_bankmachine7_source_payload_we = main_litedramcore_bankmachine7_fifo_out_payload_we;
+assign main_litedramcore_bankmachine7_source_payload_addr = main_litedramcore_bankmachine7_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine7_syncfifo7_re = main_litedramcore_bankmachine7_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine7_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine7_replace) begin
+        main_litedramcore_bankmachine7_wrport_adr <= (main_litedramcore_bankmachine7_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine7_wrport_adr <= main_litedramcore_bankmachine7_produce;
+    end
+end
+assign main_litedramcore_bankmachine7_wrport_dat_w = main_litedramcore_bankmachine7_syncfifo7_din;
+assign main_litedramcore_bankmachine7_wrport_we = (main_litedramcore_bankmachine7_syncfifo7_we & (main_litedramcore_bankmachine7_syncfifo7_writable | main_litedramcore_bankmachine7_replace));
+assign main_litedramcore_bankmachine7_do_read = (main_litedramcore_bankmachine7_syncfifo7_readable & main_litedramcore_bankmachine7_syncfifo7_re);
+assign main_litedramcore_bankmachine7_rdport_adr = main_litedramcore_bankmachine7_consume;
+assign main_litedramcore_bankmachine7_syncfifo7_dout = main_litedramcore_bankmachine7_rdport_dat_r;
+assign main_litedramcore_bankmachine7_syncfifo7_writable = (main_litedramcore_bankmachine7_level != 5'd16);
+assign main_litedramcore_bankmachine7_syncfifo7_readable = (main_litedramcore_bankmachine7_level != 1'd0);
+assign main_litedramcore_bankmachine7_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine7_pipe_valid_source_valid) | main_litedramcore_bankmachine7_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine7_pipe_valid_sink_valid = main_litedramcore_bankmachine7_sink_sink_valid;
+assign main_litedramcore_bankmachine7_sink_sink_ready = main_litedramcore_bankmachine7_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine7_pipe_valid_sink_first = main_litedramcore_bankmachine7_sink_sink_first;
+assign main_litedramcore_bankmachine7_pipe_valid_sink_last = main_litedramcore_bankmachine7_sink_sink_last;
+assign main_litedramcore_bankmachine7_pipe_valid_sink_payload_we = main_litedramcore_bankmachine7_sink_sink_payload_we;
+assign main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine7_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine7_source_source_valid = main_litedramcore_bankmachine7_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine7_pipe_valid_source_ready = main_litedramcore_bankmachine7_source_source_ready;
+assign main_litedramcore_bankmachine7_source_source_first = main_litedramcore_bankmachine7_pipe_valid_source_first;
+assign main_litedramcore_bankmachine7_source_source_last = main_litedramcore_bankmachine7_pipe_valid_source_last;
+assign main_litedramcore_bankmachine7_source_source_payload_we = main_litedramcore_bankmachine7_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine7_source_source_payload_addr = main_litedramcore_bankmachine7_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine7_next_state <= 4'd0;
+    builder_bankmachine7_next_state <= builder_bankmachine7_state;
+    case (builder_bankmachine7_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                if (main_litedramcore_bankmachine7_cmd_ready) begin
+                    builder_bankmachine7_next_state <= 3'd5;
+                end
+            end
         end
         2'd2: begin
-            litedramcore_bankmachine6_row_close <= 1'd1;
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                builder_bankmachine7_next_state <= 3'd5;
+            end
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                if (main_litedramcore_bankmachine7_cmd_ready) begin
+                    builder_bankmachine7_next_state <= 3'd7;
+                end
+            end
         end
         3'd4: begin
-            litedramcore_bankmachine6_row_close <= 1'd1;
+            if ((~main_litedramcore_bankmachine7_refresh_req)) begin
+                builder_bankmachine7_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine7_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine7_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine7_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine7_next_state <= 1'd0;
         end
         default: begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
+                builder_bankmachine7_next_state <= 3'd4;
+            end else begin
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if ((main_litedramcore_bankmachine7_cmd_ready & main_litedramcore_bankmachine7_auto_precharge)) begin
+                                builder_bankmachine7_next_state <= 2'd2;
+                            end
+                        end else begin
+                            builder_bankmachine7_next_state <= 1'd1;
+                        end
+                    end else begin
+                        builder_bankmachine7_next_state <= 2'd3;
+                    end
+                end
+            end
         end
     endcase
 end
-assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid;
-assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready;
-assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we;
-assign litedramcore_bankmachine7_sink_payload_addr = litedramcore_bankmachine7_req_addr;
-assign litedramcore_bankmachine7_sink_sink_valid = litedramcore_bankmachine7_source_valid;
-assign litedramcore_bankmachine7_source_ready = litedramcore_bankmachine7_sink_sink_ready;
-assign litedramcore_bankmachine7_sink_sink_first = litedramcore_bankmachine7_source_first;
-assign litedramcore_bankmachine7_sink_sink_last = litedramcore_bankmachine7_source_last;
-assign litedramcore_bankmachine7_sink_sink_payload_we = litedramcore_bankmachine7_source_payload_we;
-assign litedramcore_bankmachine7_sink_sink_payload_addr = litedramcore_bankmachine7_source_payload_addr;
-assign litedramcore_bankmachine7_source_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
-assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_source_valid | litedramcore_bankmachine7_source_source_valid);
-assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_source_source_payload_addr[21:7]);
-assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
-always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_a <= 15'd0;
-    if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
-        litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_source_source_payload_addr[21:7];
-    end else begin
-        litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
-assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
-assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
-always @(*) begin
-    litedramcore_bankmachine7_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine7_source_valid & litedramcore_bankmachine7_source_source_valid)) begin
-        if ((litedramcore_bankmachine7_source_payload_addr[21:7] != litedramcore_bankmachine7_source_source_payload_addr[21:7])) begin
-            litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine7_syncfifo7_din = {litedramcore_bankmachine7_fifo_in_last, litedramcore_bankmachine7_fifo_in_first, litedramcore_bankmachine7_fifo_in_payload_addr, litedramcore_bankmachine7_fifo_in_payload_we};
-assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
-assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
-assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
-assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
-assign litedramcore_bankmachine7_sink_ready = litedramcore_bankmachine7_syncfifo7_writable;
-assign litedramcore_bankmachine7_syncfifo7_we = litedramcore_bankmachine7_sink_valid;
-assign litedramcore_bankmachine7_fifo_in_first = litedramcore_bankmachine7_sink_first;
-assign litedramcore_bankmachine7_fifo_in_last = litedramcore_bankmachine7_sink_last;
-assign litedramcore_bankmachine7_fifo_in_payload_we = litedramcore_bankmachine7_sink_payload_we;
-assign litedramcore_bankmachine7_fifo_in_payload_addr = litedramcore_bankmachine7_sink_payload_addr;
-assign litedramcore_bankmachine7_source_valid = litedramcore_bankmachine7_syncfifo7_readable;
-assign litedramcore_bankmachine7_source_first = litedramcore_bankmachine7_fifo_out_first;
-assign litedramcore_bankmachine7_source_last = litedramcore_bankmachine7_fifo_out_last;
-assign litedramcore_bankmachine7_source_payload_we = litedramcore_bankmachine7_fifo_out_payload_we;
-assign litedramcore_bankmachine7_source_payload_addr = litedramcore_bankmachine7_fifo_out_payload_addr;
-assign litedramcore_bankmachine7_syncfifo7_re = litedramcore_bankmachine7_source_ready;
-always @(*) begin
-    litedramcore_bankmachine7_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine7_replace) begin
-        litedramcore_bankmachine7_wrport_adr <= (litedramcore_bankmachine7_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine7_wrport_adr <= litedramcore_bankmachine7_produce;
-    end
-end
-assign litedramcore_bankmachine7_wrport_dat_w = litedramcore_bankmachine7_syncfifo7_din;
-assign litedramcore_bankmachine7_wrport_we = (litedramcore_bankmachine7_syncfifo7_we & (litedramcore_bankmachine7_syncfifo7_writable | litedramcore_bankmachine7_replace));
-assign litedramcore_bankmachine7_do_read = (litedramcore_bankmachine7_syncfifo7_readable & litedramcore_bankmachine7_syncfifo7_re);
-assign litedramcore_bankmachine7_rdport_adr = litedramcore_bankmachine7_consume;
-assign litedramcore_bankmachine7_syncfifo7_dout = litedramcore_bankmachine7_rdport_dat_r;
-assign litedramcore_bankmachine7_syncfifo7_writable = (litedramcore_bankmachine7_level != 5'd16);
-assign litedramcore_bankmachine7_syncfifo7_readable = (litedramcore_bankmachine7_level != 1'd0);
-assign litedramcore_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready);
-assign litedramcore_bankmachine7_pipe_valid_sink_valid = litedramcore_bankmachine7_sink_sink_valid;
-assign litedramcore_bankmachine7_sink_sink_ready = litedramcore_bankmachine7_pipe_valid_sink_ready;
-assign litedramcore_bankmachine7_pipe_valid_sink_first = litedramcore_bankmachine7_sink_sink_first;
-assign litedramcore_bankmachine7_pipe_valid_sink_last = litedramcore_bankmachine7_sink_sink_last;
-assign litedramcore_bankmachine7_pipe_valid_sink_payload_we = litedramcore_bankmachine7_sink_sink_payload_we;
-assign litedramcore_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_bankmachine7_sink_sink_payload_addr;
-assign litedramcore_bankmachine7_source_source_valid = litedramcore_bankmachine7_pipe_valid_source_valid;
-assign litedramcore_bankmachine7_pipe_valid_source_ready = litedramcore_bankmachine7_source_source_ready;
-assign litedramcore_bankmachine7_source_source_first = litedramcore_bankmachine7_pipe_valid_source_first;
-assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_pipe_valid_source_last;
-assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine7_next_state <= 4'd0;
-    litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
-    case (litedramcore_bankmachine7_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                if (litedramcore_bankmachine7_cmd_ready) begin
-                    litedramcore_bankmachine7_next_state <= 3'd5;
-                end
-            end
+always @(*) begin
+    main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine7_state)
+        1'd1: begin
         end
         2'd2: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                if (litedramcore_bankmachine7_cmd_ready) begin
-                    litedramcore_bankmachine7_next_state <= 3'd7;
-                end
-            end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine7_refresh_req)) begin
-                litedramcore_bankmachine7_next_state <= 1'd0;
-            end
         end
         3'd5: begin
-            litedramcore_bankmachine7_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine7_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine7_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine7_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
-                litedramcore_bankmachine7_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
-                                litedramcore_bankmachine7_next_state <= 2'd2;
-                            end
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
                         end else begin
-                            litedramcore_bankmachine7_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine7_next_state <= 2'd3;
                     end
                 end
             end
@@ -10372,18 +10998,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -10401,11 +11027,11 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
@@ -10423,13 +11049,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
-                                litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
+                                main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -10442,22 +11068,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -10472,8 +11098,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -10491,14 +11117,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -10510,8 +11136,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -10529,13 +11155,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
-                                litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
+                                main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -10548,8 +11174,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -10567,13 +11193,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
-                                litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
+                                main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -10586,8 +11212,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -10605,14 +11231,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
+                                main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
                             end
                         end else begin
                         end
@@ -10624,8 +11250,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -10633,8 +11259,8 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine7_twtpcon_ready) begin
-                litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+            if (main_litedramcore_bankmachine7_twtpcon_ready) begin
+                main_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
             end
         end
         3'd5: begin
@@ -10650,15 +11276,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_row_open <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_row_open <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -10676,18 +11302,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -10701,12 +11327,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            litedramcore_bankmachine7_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -10717,18 +11343,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_row_close <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_row_close <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            litedramcore_bankmachine7_row_close <= 1'd1;
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine7_row_close <= 1'd1;
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine7_row_close <= 1'd1;
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -10743,15 +11369,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -10768,301 +11394,259 @@ always @(*) begin
         end
     endcase
 end
+assign main_litedramcore_nphases = (main_k7ddrphy_rdphase_storage - 1'd1);
+assign main_litedramcore_rdphase = (main_k7ddrphy_wrphase_storage - 1'd1);
+assign main_litedramcore_trrdcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we)));
+assign main_litedramcore_tfawcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we)));
+assign main_litedramcore_ras_allowed = (main_litedramcore_trrdcon_ready & main_litedramcore_tfawcon_ready);
+assign main_litedramcore_tccdcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_cmd_payload_is_write | main_litedramcore_choose_req_cmd_payload_is_read));
+assign main_litedramcore_cas_allowed = main_litedramcore_tccdcon_ready;
+assign main_litedramcore_twtrcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+assign main_litedramcore_read_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_read) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_read)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_read)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_read)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_read)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_read)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_read)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_read));
+assign main_litedramcore_write_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_write) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_write)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_write)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_write)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_write)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_write)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_write)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_write));
+assign main_litedramcore_max_time0 = (main_litedramcore_time0 == 1'd0);
+assign main_litedramcore_max_time1 = (main_litedramcore_time1 == 1'd0);
+assign main_litedramcore_bankmachine0_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine1_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine2_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine3_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine4_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine5_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine6_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine7_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_go_to_refresh = (((((((main_litedramcore_bankmachine0_refresh_gnt & main_litedramcore_bankmachine1_refresh_gnt) & main_litedramcore_bankmachine2_refresh_gnt) & main_litedramcore_bankmachine3_refresh_gnt) & main_litedramcore_bankmachine4_refresh_gnt) & main_litedramcore_bankmachine5_refresh_gnt) & main_litedramcore_bankmachine6_refresh_gnt) & main_litedramcore_bankmachine7_refresh_gnt);
+assign main_litedramcore_interface_rdata = {main_litedramcore_dfi_p3_rddata, main_litedramcore_dfi_p2_rddata, main_litedramcore_dfi_p1_rddata, main_litedramcore_dfi_p0_rddata};
+assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
+assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
+assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
+assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
+assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
+assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
+assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
+assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine7_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
-assign litedramcore_rdcmdphase = (k7ddrphy_rdphase_storage - 1'd1);
-assign litedramcore_wrcmdphase = (k7ddrphy_wrphase_storage - 1'd1);
-assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
-assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
-assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready);
-assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read));
-assign litedramcore_cas_allowed = litedramcore_tccdcon_ready;
-assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
-assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read));
-assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write));
-assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0);
-assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0);
-assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt);
-assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata};
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
-always @(*) begin
-    litedramcore_choose_cmd_valids <= 8'd0;
-    litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids <= 8'd0;
+    main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
 end
-assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
-assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
-assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1;
-assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
-assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
-assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
-assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
+assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids;
+assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_self0;
+assign main_litedramcore_choose_cmd_cmd_payload_a = builder_rhs_self1;
+assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_self2;
+assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_self3;
+assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_self4;
+assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_self5;
 always @(*) begin
-    litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
-    if (litedramcore_choose_cmd_cmd_valid) begin
-        litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
+    main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
+    if (main_litedramcore_choose_cmd_cmd_valid) begin
+        main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_self0;
     end
 end
 always @(*) begin
-    litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
-    if (litedramcore_choose_cmd_cmd_valid) begin
-        litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
+    main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
+    if (main_litedramcore_choose_cmd_cmd_valid) begin
+        main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_self1;
     end
 end
 always @(*) begin
-    litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
-    if (litedramcore_choose_cmd_cmd_valid) begin
-        litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
+    main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
+    if (main_litedramcore_choose_cmd_cmd_valid) begin
+        main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_self2;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
-        litedramcore_bankmachine0_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine0_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin
+        main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
-        litedramcore_bankmachine0_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin
+        main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
-        litedramcore_bankmachine1_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine1_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin
+        main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
-        litedramcore_bankmachine1_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin
+        main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
-        litedramcore_bankmachine2_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine2_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin
+        main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
-        litedramcore_bankmachine2_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin
+        main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
-        litedramcore_bankmachine3_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine3_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin
+        main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
-        litedramcore_bankmachine3_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin
+        main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
-        litedramcore_bankmachine4_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine4_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin
+        main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
-        litedramcore_bankmachine4_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin
+        main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
-        litedramcore_bankmachine5_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine5_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin
+        main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
-        litedramcore_bankmachine5_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin
+        main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
-        litedramcore_bankmachine6_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine6_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin
+        main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
-        litedramcore_bankmachine6_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin
+        main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
-        litedramcore_bankmachine7_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine7_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin
+        main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
-        litedramcore_bankmachine7_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin
+        main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
     end
 end
-assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
+assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid));
 always @(*) begin
-    litedramcore_choose_req_valids <= 8'd0;
-    litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids <= 8'd0;
+    main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
 end
-assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
-assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
-assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7;
-assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8;
-assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9;
-assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
-assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
+assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids;
+assign main_litedramcore_choose_req_cmd_valid = builder_rhs_self6;
+assign main_litedramcore_choose_req_cmd_payload_a = builder_rhs_self7;
+assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_self8;
+assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_self9;
+assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_self10;
+assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_self11;
 always @(*) begin
-    litedramcore_choose_req_cmd_payload_cas <= 1'd0;
-    if (litedramcore_choose_req_cmd_valid) begin
-        litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
+    main_litedramcore_choose_req_cmd_payload_cas <= 1'd0;
+    if (main_litedramcore_choose_req_cmd_valid) begin
+        main_litedramcore_choose_req_cmd_payload_cas <= builder_t_self3;
     end
 end
 always @(*) begin
-    litedramcore_choose_req_cmd_payload_ras <= 1'd0;
-    if (litedramcore_choose_req_cmd_valid) begin
-        litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
+    main_litedramcore_choose_req_cmd_payload_ras <= 1'd0;
+    if (main_litedramcore_choose_req_cmd_valid) begin
+        main_litedramcore_choose_req_cmd_payload_ras <= builder_t_self4;
     end
 end
 always @(*) begin
-    litedramcore_choose_req_cmd_payload_we <= 1'd0;
-    if (litedramcore_choose_req_cmd_valid) begin
-        litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
+    main_litedramcore_choose_req_cmd_payload_we <= 1'd0;
+    if (main_litedramcore_choose_req_cmd_valid) begin
+        main_litedramcore_choose_req_cmd_payload_we <= builder_t_self5;
     end
 end
-assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
-assign litedramcore_dfi_p0_reset_n = 1'd1;
-assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}};
-assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}};
-assign litedramcore_dfi_p1_reset_n = 1'd1;
-assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}};
-assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}};
-assign litedramcore_dfi_p2_reset_n = 1'd1;
-assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}};
-assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}};
-assign litedramcore_dfi_p3_reset_n = 1'd1;
-assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}};
-assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}};
-assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]);
+assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid));
+assign main_litedramcore_dfi_p0_reset_n = 1'd1;
+assign main_litedramcore_dfi_p0_cke = {1{main_litedramcore_steerer4}};
+assign main_litedramcore_dfi_p0_odt = {1{main_litedramcore_steerer5}};
+assign main_litedramcore_dfi_p1_reset_n = 1'd1;
+assign main_litedramcore_dfi_p1_cke = {1{main_litedramcore_steerer6}};
+assign main_litedramcore_dfi_p1_odt = {1{main_litedramcore_steerer7}};
+assign main_litedramcore_dfi_p2_reset_n = 1'd1;
+assign main_litedramcore_dfi_p2_cke = {1{main_litedramcore_steerer8}};
+assign main_litedramcore_dfi_p2_odt = {1{main_litedramcore_steerer9}};
+assign main_litedramcore_dfi_p3_reset_n = 1'd1;
+assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer10}};
+assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer11}};
+assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]);
 always @(*) begin
-    litedramcore_multiplexer_next_state <= 4'd0;
-    litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
-    case (litedramcore_multiplexer_state)
+    builder_multiplexer_next_state <= 4'd0;
+    builder_multiplexer_next_state <= builder_multiplexer_state;
+    case (builder_multiplexer_state)
         1'd1: begin
-            if (litedramcore_read_available) begin
-                if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
-                    litedramcore_multiplexer_next_state <= 2'd3;
+            if (main_litedramcore_read_available) begin
+                if (((~main_litedramcore_write_available) | main_litedramcore_max_time1)) begin
+                    builder_multiplexer_next_state <= 2'd3;
                 end
             end
-            if (litedramcore_go_to_refresh) begin
-                litedramcore_multiplexer_next_state <= 2'd2;
+            if (main_litedramcore_go_to_refresh) begin
+                builder_multiplexer_next_state <= 2'd2;
             end
         end
         2'd2: begin
-            if (litedramcore_cmd_last) begin
-                litedramcore_multiplexer_next_state <= 1'd0;
+            if (main_litedramcore_cmd_last) begin
+                builder_multiplexer_next_state <= 1'd0;
             end
         end
         2'd3: begin
-            if (litedramcore_twtrcon_ready) begin
-                litedramcore_multiplexer_next_state <= 1'd0;
+            if (main_litedramcore_twtrcon_ready) begin
+                builder_multiplexer_next_state <= 1'd0;
             end
         end
         3'd4: begin
-            litedramcore_multiplexer_next_state <= 3'd5;
+            builder_multiplexer_next_state <= 3'd5;
         end
         3'd5: begin
-            litedramcore_multiplexer_next_state <= 3'd6;
+            builder_multiplexer_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_multiplexer_next_state <= 3'd7;
+            builder_multiplexer_next_state <= 3'd7;
         end
         3'd7: begin
-            litedramcore_multiplexer_next_state <= 4'd8;
+            builder_multiplexer_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_multiplexer_next_state <= 4'd9;
+            builder_multiplexer_next_state <= 4'd9;
         end
         4'd9: begin
-            litedramcore_multiplexer_next_state <= 4'd10;
+            builder_multiplexer_next_state <= 4'd10;
         end
         4'd10: begin
-            litedramcore_multiplexer_next_state <= 1'd1;
+            builder_multiplexer_next_state <= 1'd1;
         end
         default: begin
-            if (litedramcore_write_available) begin
-                if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
-                    litedramcore_multiplexer_next_state <= 3'd4;
+            if (main_litedramcore_write_available) begin
+                if (((~main_litedramcore_read_available) | main_litedramcore_max_time0)) begin
+                    builder_multiplexer_next_state <= 3'd4;
                 end
             end
-            if (litedramcore_go_to_refresh) begin
-                litedramcore_multiplexer_next_state <= 2'd2;
+            if (main_litedramcore_go_to_refresh) begin
+                builder_multiplexer_next_state <= 2'd2;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_steerer_sel0 <= 2'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_en1 <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer_sel0 <= 1'd0;
-            if ((k7ddrphy_wrphase_storage == 1'd0)) begin
-                litedramcore_steerer_sel0 <= 2'd2;
-            end
-            if ((litedramcore_wrcmdphase == 1'd0)) begin
-                litedramcore_steerer_sel0 <= 1'd1;
-            end
+            main_litedramcore_en1 <= 1'd1;
         end
         2'd2: begin
-            litedramcore_steerer_sel0 <= 2'd3;
         end
         2'd3: begin
         end
@@ -11081,23 +11665,23 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_steerer_sel0 <= 1'd0;
-            if ((k7ddrphy_rdphase_storage == 1'd0)) begin
-                litedramcore_steerer_sel0 <= 2'd2;
-            end
-            if ((litedramcore_rdcmdphase == 1'd0)) begin
-                litedramcore_steerer_sel0 <= 1'd1;
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_cmd_ready <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_steerer0 <= 2'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
+            main_litedramcore_steerer0 <= 1'd0;
+            if ((main_k7ddrphy_wrphase_storage == 1'd0)) begin
+                main_litedramcore_steerer0 <= 2'd2;
+            end
+            if ((main_litedramcore_rdphase == 1'd0)) begin
+                main_litedramcore_steerer0 <= 1'd1;
+            end
         end
         2'd2: begin
-            litedramcore_cmd_ready <= 1'd1;
+            main_litedramcore_steerer0 <= 2'd3;
         end
         2'd3: begin
         end
@@ -11116,22 +11700,23 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
+            main_litedramcore_steerer0 <= 1'd0;
+            if ((main_k7ddrphy_rdphase_storage == 1'd0)) begin
+                main_litedramcore_steerer0 <= 2'd2;
+            end
+            if ((main_litedramcore_nphases == 1'd0)) begin
+                main_litedramcore_steerer0 <= 1'd1;
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_steerer_sel1 <= 2'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_cmd_ready <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer_sel1 <= 1'd0;
-            if ((k7ddrphy_wrphase_storage == 1'd1)) begin
-                litedramcore_steerer_sel1 <= 2'd2;
-            end
-            if ((litedramcore_wrcmdphase == 1'd1)) begin
-                litedramcore_steerer_sel1 <= 1'd1;
-            end
         end
         2'd2: begin
+            main_litedramcore_cmd_ready <= 1'd1;
         end
         2'd3: begin
         end
@@ -11150,26 +11735,19 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_steerer_sel1 <= 1'd0;
-            if ((k7ddrphy_rdphase_storage == 1'd1)) begin
-                litedramcore_steerer_sel1 <= 2'd2;
-            end
-            if ((litedramcore_rdcmdphase == 1'd1)) begin
-                litedramcore_steerer_sel1 <= 1'd1;
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_steerer_sel2 <= 2'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_steerer1 <= 2'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer_sel2 <= 1'd0;
-            if ((k7ddrphy_wrphase_storage == 2'd2)) begin
-                litedramcore_steerer_sel2 <= 2'd2;
+            main_litedramcore_steerer1 <= 1'd0;
+            if ((main_k7ddrphy_wrphase_storage == 1'd1)) begin
+                main_litedramcore_steerer1 <= 2'd2;
             end
-            if ((litedramcore_wrcmdphase == 2'd2)) begin
-                litedramcore_steerer_sel2 <= 1'd1;
+            if ((main_litedramcore_rdphase == 1'd1)) begin
+                main_litedramcore_steerer1 <= 1'd1;
             end
         end
         2'd2: begin
@@ -11191,23 +11769,26 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_steerer_sel2 <= 1'd0;
-            if ((k7ddrphy_rdphase_storage == 2'd2)) begin
-                litedramcore_steerer_sel2 <= 2'd2;
+            main_litedramcore_steerer1 <= 1'd0;
+            if ((main_k7ddrphy_rdphase_storage == 1'd1)) begin
+                main_litedramcore_steerer1 <= 2'd2;
             end
-            if ((litedramcore_rdcmdphase == 2'd2)) begin
-                litedramcore_steerer_sel2 <= 1'd1;
+            if ((main_litedramcore_nphases == 1'd1)) begin
+                main_litedramcore_steerer1 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_cmd_want_activates <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_steerer2 <= 2'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            if (1'd0) begin
-            end else begin
-                litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+            main_litedramcore_steerer2 <= 1'd0;
+            if ((main_k7ddrphy_wrphase_storage == 2'd2)) begin
+                main_litedramcore_steerer2 <= 2'd2;
+            end
+            if ((main_litedramcore_rdphase == 2'd2)) begin
+                main_litedramcore_steerer2 <= 1'd1;
             end
         end
         2'd2: begin
@@ -11229,23 +11810,23 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            if (1'd0) begin
-            end else begin
-                litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+            main_litedramcore_steerer2 <= 1'd0;
+            if ((main_k7ddrphy_rdphase_storage == 2'd2)) begin
+                main_litedramcore_steerer2 <= 2'd2;
+            end
+            if ((main_litedramcore_nphases == 2'd2)) begin
+                main_litedramcore_steerer2 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_steerer_sel3 <= 2'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_choose_cmd_want_activates <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer_sel3 <= 1'd0;
-            if ((k7ddrphy_wrphase_storage == 2'd3)) begin
-                litedramcore_steerer_sel3 <= 2'd2;
-            end
-            if ((litedramcore_wrcmdphase == 2'd3)) begin
-                litedramcore_steerer_sel3 <= 1'd1;
+            if (1'd0) begin
+            end else begin
+                main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
             end
         end
         2'd2: begin
@@ -11267,20 +11848,24 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_steerer_sel3 <= 1'd0;
-            if ((k7ddrphy_rdphase_storage == 2'd3)) begin
-                litedramcore_steerer_sel3 <= 2'd2;
-            end
-            if ((litedramcore_rdcmdphase == 2'd3)) begin
-                litedramcore_steerer_sel3 <= 1'd1;
+            if (1'd0) begin
+            end else begin
+                main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_en0 <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_steerer3 <= 2'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
+            main_litedramcore_steerer3 <= 1'd0;
+            if ((main_k7ddrphy_wrphase_storage == 2'd3)) begin
+                main_litedramcore_steerer3 <= 2'd2;
+            end
+            if ((main_litedramcore_rdphase == 2'd3)) begin
+                main_litedramcore_steerer3 <= 1'd1;
+            end
         end
         2'd2: begin
         end
@@ -11301,15 +11886,20 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_en0 <= 1'd1;
+            main_litedramcore_steerer3 <= 1'd0;
+            if ((main_k7ddrphy_rdphase_storage == 2'd3)) begin
+                main_litedramcore_steerer3 <= 2'd2;
+            end
+            if ((main_litedramcore_nphases == 2'd3)) begin
+                main_litedramcore_steerer3 <= 1'd1;
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_en1 <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_en0 <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_en1 <= 1'd1;
         end
         2'd2: begin
         end
@@ -11330,16 +11920,17 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
+            main_litedramcore_en0 <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_cmd_cmd_ready <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
             if (1'd0) begin
             end else begin
-                litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+                main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
             end
         end
         2'd2: begin
@@ -11363,14 +11954,14 @@ always @(*) begin
         default: begin
             if (1'd0) begin
             end else begin
-                litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+                main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_req_want_reads <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_choose_req_want_reads <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
         end
         2'd2: begin
@@ -11392,15 +11983,15 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_choose_req_want_reads <= 1'd1;
+            main_litedramcore_choose_req_want_reads <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_req_want_writes <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_choose_req_want_writes <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_choose_req_want_writes <= 1'd1;
+            main_litedramcore_choose_req_want_writes <= 1'd1;
         end
         2'd2: begin
         end
@@ -11425,13 +12016,13 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_choose_req_cmd_ready <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_choose_req_cmd_ready <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
             if (1'd0) begin
-                litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
             end else begin
-                litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
             end
         end
         2'd2: begin
@@ -11454,2205 +12045,2202 @@ always @(*) begin
         end
         default: begin
             if (1'd0) begin
-                litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
             end else begin
-                litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
-            end
-        end
-    endcase
-end
-assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
-assign litedramcore_interface_bank0_addr = rhs_array_muxed12;
-assign litedramcore_interface_bank0_we = rhs_array_muxed13;
-assign litedramcore_interface_bank0_valid = rhs_array_muxed14;
-assign litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock));
-assign litedramcore_interface_bank1_addr = rhs_array_muxed15;
-assign litedramcore_interface_bank1_we = rhs_array_muxed16;
-assign litedramcore_interface_bank1_valid = rhs_array_muxed17;
-assign litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock));
-assign litedramcore_interface_bank2_addr = rhs_array_muxed18;
-assign litedramcore_interface_bank2_we = rhs_array_muxed19;
-assign litedramcore_interface_bank2_valid = rhs_array_muxed20;
-assign litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock));
-assign litedramcore_interface_bank3_addr = rhs_array_muxed21;
-assign litedramcore_interface_bank3_we = rhs_array_muxed22;
-assign litedramcore_interface_bank3_valid = rhs_array_muxed23;
-assign litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock));
-assign litedramcore_interface_bank4_addr = rhs_array_muxed24;
-assign litedramcore_interface_bank4_we = rhs_array_muxed25;
-assign litedramcore_interface_bank4_valid = rhs_array_muxed26;
-assign litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock));
-assign litedramcore_interface_bank5_addr = rhs_array_muxed27;
-assign litedramcore_interface_bank5_we = rhs_array_muxed28;
-assign litedramcore_interface_bank5_valid = rhs_array_muxed29;
-assign litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock));
-assign litedramcore_interface_bank6_addr = rhs_array_muxed30;
-assign litedramcore_interface_bank6_we = rhs_array_muxed31;
-assign litedramcore_interface_bank6_valid = rhs_array_muxed32;
-assign litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock));
-assign litedramcore_interface_bank7_addr = rhs_array_muxed33;
-assign litedramcore_interface_bank7_we = rhs_array_muxed34;
-assign litedramcore_interface_bank7_valid = rhs_array_muxed35;
-assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready));
-assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1;
-assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8;
-always @(*) begin
-    litedramcore_interface_wdata <= 256'd0;
-    case ({litedramcore_new_master_wdata_ready1})
-        1'd1: begin
-            litedramcore_interface_wdata <= user_port_wdata_payload_data;
+                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
+            end
+        end
+    endcase
+end
+assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock));
+assign main_litedramcore_interface_bank0_addr = builder_rhs_self12;
+assign main_litedramcore_interface_bank0_we = builder_rhs_self13;
+assign main_litedramcore_interface_bank0_valid = builder_rhs_self14;
+assign builder_roundrobin1_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin1_ce = ((~main_litedramcore_interface_bank1_valid) & (~main_litedramcore_interface_bank1_lock));
+assign main_litedramcore_interface_bank1_addr = builder_rhs_self15;
+assign main_litedramcore_interface_bank1_we = builder_rhs_self16;
+assign main_litedramcore_interface_bank1_valid = builder_rhs_self17;
+assign builder_roundrobin2_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin2_ce = ((~main_litedramcore_interface_bank2_valid) & (~main_litedramcore_interface_bank2_lock));
+assign main_litedramcore_interface_bank2_addr = builder_rhs_self18;
+assign main_litedramcore_interface_bank2_we = builder_rhs_self19;
+assign main_litedramcore_interface_bank2_valid = builder_rhs_self20;
+assign builder_roundrobin3_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin3_ce = ((~main_litedramcore_interface_bank3_valid) & (~main_litedramcore_interface_bank3_lock));
+assign main_litedramcore_interface_bank3_addr = builder_rhs_self21;
+assign main_litedramcore_interface_bank3_we = builder_rhs_self22;
+assign main_litedramcore_interface_bank3_valid = builder_rhs_self23;
+assign builder_roundrobin4_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin4_ce = ((~main_litedramcore_interface_bank4_valid) & (~main_litedramcore_interface_bank4_lock));
+assign main_litedramcore_interface_bank4_addr = builder_rhs_self24;
+assign main_litedramcore_interface_bank4_we = builder_rhs_self25;
+assign main_litedramcore_interface_bank4_valid = builder_rhs_self26;
+assign builder_roundrobin5_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin5_ce = ((~main_litedramcore_interface_bank5_valid) & (~main_litedramcore_interface_bank5_lock));
+assign main_litedramcore_interface_bank5_addr = builder_rhs_self27;
+assign main_litedramcore_interface_bank5_we = builder_rhs_self28;
+assign main_litedramcore_interface_bank5_valid = builder_rhs_self29;
+assign builder_roundrobin6_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin6_ce = ((~main_litedramcore_interface_bank6_valid) & (~main_litedramcore_interface_bank6_lock));
+assign main_litedramcore_interface_bank6_addr = builder_rhs_self30;
+assign main_litedramcore_interface_bank6_we = builder_rhs_self31;
+assign main_litedramcore_interface_bank6_valid = builder_rhs_self32;
+assign builder_roundrobin7_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin7_ce = ((~main_litedramcore_interface_bank7_valid) & (~main_litedramcore_interface_bank7_lock));
+assign main_litedramcore_interface_bank7_addr = builder_rhs_self33;
+assign main_litedramcore_interface_bank7_we = builder_rhs_self34;
+assign main_litedramcore_interface_bank7_valid = builder_rhs_self35;
+assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready));
+assign main_user_port_wdata_ready = builder_new_master_wdata_ready1;
+assign main_user_port_rdata_valid = builder_new_master_rdata_valid8;
+always @(*) begin
+    main_litedramcore_interface_wdata_we <= 32'd0;
+    case ({builder_new_master_wdata_ready1})
+        1'd1: begin
+            main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we;
         end
         default: begin
-            litedramcore_interface_wdata <= 1'd0;
+            main_litedramcore_interface_wdata_we <= 1'd0;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_interface_wdata_we <= 32'd0;
-    case ({litedramcore_new_master_wdata_ready1})
+    main_litedramcore_interface_wdata <= 256'd0;
+    case ({builder_new_master_wdata_ready1})
         1'd1: begin
-            litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
+            main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data;
         end
         default: begin
-            litedramcore_interface_wdata_we <= 1'd0;
+            main_litedramcore_interface_wdata <= 1'd0;
         end
     endcase
 end
-assign user_port_rdata_payload_data = litedramcore_interface_rdata;
-assign litedramcore_roundrobin0_grant = 1'd0;
-assign litedramcore_roundrobin1_grant = 1'd0;
-assign litedramcore_roundrobin2_grant = 1'd0;
-assign litedramcore_roundrobin3_grant = 1'd0;
-assign litedramcore_roundrobin4_grant = 1'd0;
-assign litedramcore_roundrobin5_grant = 1'd0;
-assign litedramcore_roundrobin6_grant = 1'd0;
-assign litedramcore_roundrobin7_grant = 1'd0;
+assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata;
+assign builder_roundrobin0_grant = 1'd0;
+assign builder_roundrobin1_grant = 1'd0;
+assign builder_roundrobin2_grant = 1'd0;
+assign builder_roundrobin3_grant = 1'd0;
+assign builder_roundrobin4_grant = 1'd0;
+assign builder_roundrobin5_grant = 1'd0;
+assign builder_roundrobin6_grant = 1'd0;
+assign builder_roundrobin7_grant = 1'd0;
 always @(*) begin
-    litedramcore_next_state <= 2'd0;
-    litedramcore_next_state <= litedramcore_state;
-    case (litedramcore_state)
+    builder_next_state <= 2'd0;
+    builder_next_state <= builder_state;
+    case (builder_state)
         1'd1: begin
-            litedramcore_next_state <= 2'd2;
+            builder_next_state <= 2'd2;
         end
         2'd2: begin
-            litedramcore_next_state <= 1'd0;
+            builder_next_state <= 1'd0;
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_next_state <= 1'd1;
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_next_state <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_wishbone_dat_r <= 32'd0;
-    case (litedramcore_state)
+    builder_interface1_we_next_value2 <= 1'd0;
+    case (builder_state)
         1'd1: begin
+            builder_interface1_we_next_value2 <= 1'd0;
         end
         2'd2: begin
-            litedramcore_wishbone_dat_r <= litedramcore_dat_r;
         end
         default: begin
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_we_next_value2 <= (builder_interface0_we & (builder_interface0_sel != 1'd0));
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_wishbone_ack <= 1'd0;
-    case (litedramcore_state)
+    builder_interface1_we_next_value_ce2 <= 1'd0;
+    case (builder_state)
         1'd1: begin
+            builder_interface1_we_next_value_ce2 <= 1'd1;
         end
         2'd2: begin
-            litedramcore_wishbone_ack <= 1'd1;
         end
         default: begin
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_we_next_value_ce2 <= 1'd1;
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_dat_w_next_value0 <= 32'd0;
-    case (litedramcore_state)
+    builder_interface0_ack <= 1'd0;
+    case (builder_state)
         1'd1: begin
         end
         2'd2: begin
+            builder_interface0_ack <= 1'd1;
         end
         default: begin
-            litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_dat_w_next_value_ce0 <= 1'd0;
-    case (litedramcore_state)
+    builder_interface1_dat_w_next_value0 <= 32'd0;
+    case (builder_state)
         1'd1: begin
         end
         2'd2: begin
         end
         default: begin
-            litedramcore_dat_w_next_value_ce0 <= 1'd1;
+            builder_interface1_dat_w_next_value0 <= builder_interface0_dat_w;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_adr_next_value1 <= 14'd0;
-    case (litedramcore_state)
+    builder_interface1_dat_w_next_value_ce0 <= 1'd0;
+    case (builder_state)
         1'd1: begin
-            litedramcore_adr_next_value1 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
-            end
+            builder_interface1_dat_w_next_value_ce0 <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_adr_next_value_ce1 <= 1'd0;
-    case (litedramcore_state)
+    builder_interface1_adr_next_value1 <= 14'd0;
+    case (builder_state)
         1'd1: begin
-            litedramcore_adr_next_value_ce1 <= 1'd1;
+            builder_interface1_adr_next_value1 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_adr_next_value_ce1 <= 1'd1;
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_adr_next_value1 <= builder_interface0_adr[29:0];
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_we_next_value2 <= 1'd0;
-    case (litedramcore_state)
+    builder_interface1_adr_next_value_ce1 <= 1'd0;
+    case (builder_state)
         1'd1: begin
-            litedramcore_we_next_value2 <= 1'd0;
+            builder_interface1_adr_next_value_ce1 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_adr_next_value_ce1 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_we_next_value_ce2 <= 1'd0;
-    case (litedramcore_state)
+    builder_interface0_dat_r <= 32'd0;
+    case (builder_state)
         1'd1: begin
-            litedramcore_we_next_value_ce2 <= 1'd1;
         end
         2'd2: begin
+            builder_interface0_dat_r <= builder_interface1_dat_r;
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_we_next_value_ce2 <= 1'd1;
-            end
         end
     endcase
 end
-assign litedramcore_wishbone_adr = wb_bus_adr;
-assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
-assign wb_bus_dat_r = litedramcore_wishbone_dat_r;
-assign litedramcore_wishbone_sel = wb_bus_sel;
-assign litedramcore_wishbone_cyc = wb_bus_cyc;
-assign litedramcore_wishbone_stb = wb_bus_stb;
-assign wb_bus_ack = litedramcore_wishbone_ack;
-assign litedramcore_wishbone_we = wb_bus_we;
-assign litedramcore_wishbone_cti = wb_bus_cti;
-assign litedramcore_wishbone_bte = wb_bus_bte;
-assign wb_bus_err = litedramcore_wishbone_err;
-assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
-assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
+assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0);
+assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank0_init_done0_re <= 1'd0;
-    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank0_init_done0_re <= interface0_bank_bus_we;
+    builder_csrbank0_init_done0_re <= 1'd0;
+    if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank0_init_done0_we <= 1'd0;
-    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank0_init_done0_we <= (~interface0_bank_bus_we);
+    builder_csrbank0_init_done0_we <= 1'd0;
+    if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
     end
 end
-assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
+assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank0_init_error0_we <= 1'd0;
-    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank0_init_error0_we <= (~interface0_bank_bus_we);
+    builder_csrbank0_init_error0_re <= 1'd0;
+    if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank0_init_error0_re <= 1'd0;
-    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank0_init_error0_re <= interface0_bank_bus_we;
+    builder_csrbank0_init_error0_we <= 1'd0;
+    if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
     end
 end
-assign csrbank0_init_done0_w = init_done_storage;
-assign csrbank0_init_error0_w = init_error_storage;
-assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
-assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0];
+assign builder_csrbank0_init_done0_w = main_init_done_storage;
+assign builder_csrbank0_init_error0_w = main_init_error_storage;
+assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
+assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank1_rst0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank1_rst0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_rst0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_rst0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank1_rst0_re <= interface1_bank_bus_we;
+    builder_csrbank1_rst0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[3:0];
+assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[3:0];
 always @(*) begin
-    csrbank1_dly_sel0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank1_dly_sel0_re <= interface1_bank_bus_we;
+    builder_csrbank1_dly_sel0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank1_dly_sel0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_dly_sel0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
     end
 end
-assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
+assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0];
 always @(*) begin
-    csrbank1_half_sys8x_taps0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we;
+    builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
+        builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_half_sys8x_taps0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
+        builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0];
+assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank1_wlevel_en0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_wlevel_en0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
+        builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank1_wlevel_en0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank1_wlevel_en0_re <= interface1_bank_bus_we;
+    builder_csrbank1_wlevel_en0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
+        builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
     end
 end
-assign k7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0];
+assign main_k7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    k7ddrphy_wlevel_strobe_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
-        k7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we;
+    main_k7ddrphy_wlevel_strobe_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
+        main_k7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    k7ddrphy_wlevel_strobe_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
-        k7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we);
+    main_k7ddrphy_wlevel_strobe_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
+        main_k7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign k7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0];
+assign main_k7ddrphy_cdly_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    k7ddrphy_cdly_rst_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        k7ddrphy_cdly_rst_we <= (~interface1_bank_bus_we);
+    main_k7ddrphy_cdly_rst_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
+        main_k7ddrphy_cdly_rst_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    k7ddrphy_cdly_rst_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        k7ddrphy_cdly_rst_re <= interface1_bank_bus_we;
+    main_k7ddrphy_cdly_rst_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
+        main_k7ddrphy_cdly_rst_re <= builder_interface1_bank_bus_we;
     end
 end
-assign k7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0];
+assign main_k7ddrphy_cdly_inc_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    k7ddrphy_cdly_inc_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        k7ddrphy_cdly_inc_we <= (~interface1_bank_bus_we);
+    main_k7ddrphy_cdly_inc_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
+        main_k7ddrphy_cdly_inc_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    k7ddrphy_cdly_inc_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        k7ddrphy_cdly_inc_re <= interface1_bank_bus_we;
+    main_k7ddrphy_cdly_inc_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
+        main_k7ddrphy_cdly_inc_re <= builder_interface1_bank_bus_we;
     end
 end
-assign k7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
+assign main_k7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    k7ddrphy_rdly_dq_rst_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
-        k7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
+    main_k7ddrphy_rdly_dq_rst_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
+        main_k7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    k7ddrphy_rdly_dq_rst_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
-        k7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
+    main_k7ddrphy_rdly_dq_rst_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
+        main_k7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
     end
 end
-assign k7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
+assign main_k7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    k7ddrphy_rdly_dq_inc_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
-        k7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
+    main_k7ddrphy_rdly_dq_inc_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
+        main_k7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    k7ddrphy_rdly_dq_inc_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
-        k7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
+    main_k7ddrphy_rdly_dq_inc_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
+        main_k7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
     end
 end
-assign k7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
+assign main_k7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    k7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
-        k7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
+    main_k7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
+        main_k7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    k7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
-        k7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
+    main_k7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
+        main_k7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign k7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
+assign main_k7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    k7ddrphy_rdly_dq_bitslip_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
-        k7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we;
+    main_k7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
+        main_k7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    k7ddrphy_rdly_dq_bitslip_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
-        k7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
+    main_k7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
+        main_k7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign k7ddrphy_wdly_dq_rst_r = interface1_bank_bus_dat_w[0];
+assign main_k7ddrphy_wdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    k7ddrphy_wdly_dq_rst_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
-        k7ddrphy_wdly_dq_rst_re <= interface1_bank_bus_we;
+    main_k7ddrphy_wdly_dq_rst_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
+        main_k7ddrphy_wdly_dq_rst_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    k7ddrphy_wdly_dq_rst_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
-        k7ddrphy_wdly_dq_rst_we <= (~interface1_bank_bus_we);
+    main_k7ddrphy_wdly_dq_rst_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
+        main_k7ddrphy_wdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign k7ddrphy_wdly_dq_inc_r = interface1_bank_bus_dat_w[0];
+assign main_k7ddrphy_wdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    k7ddrphy_wdly_dq_inc_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
-        k7ddrphy_wdly_dq_inc_re <= interface1_bank_bus_we;
+    main_k7ddrphy_wdly_dq_inc_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
+        main_k7ddrphy_wdly_dq_inc_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    k7ddrphy_wdly_dq_inc_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
-        k7ddrphy_wdly_dq_inc_we <= (~interface1_bank_bus_we);
+    main_k7ddrphy_wdly_dq_inc_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
+        main_k7ddrphy_wdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign k7ddrphy_wdly_dqs_rst_r = interface1_bank_bus_dat_w[0];
+assign main_k7ddrphy_wdly_dqs_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    k7ddrphy_wdly_dqs_rst_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin
-        k7ddrphy_wdly_dqs_rst_we <= (~interface1_bank_bus_we);
+    main_k7ddrphy_wdly_dqs_rst_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin
+        main_k7ddrphy_wdly_dqs_rst_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    k7ddrphy_wdly_dqs_rst_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin
-        k7ddrphy_wdly_dqs_rst_re <= interface1_bank_bus_we;
+    main_k7ddrphy_wdly_dqs_rst_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin
+        main_k7ddrphy_wdly_dqs_rst_re <= builder_interface1_bank_bus_we;
     end
 end
-assign k7ddrphy_wdly_dqs_inc_r = interface1_bank_bus_dat_w[0];
+assign main_k7ddrphy_wdly_dqs_inc_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    k7ddrphy_wdly_dqs_inc_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
-        k7ddrphy_wdly_dqs_inc_we <= (~interface1_bank_bus_we);
+    main_k7ddrphy_wdly_dqs_inc_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin
+        main_k7ddrphy_wdly_dqs_inc_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    k7ddrphy_wdly_dqs_inc_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
-        k7ddrphy_wdly_dqs_inc_re <= interface1_bank_bus_we;
+    main_k7ddrphy_wdly_dqs_inc_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin
+        main_k7ddrphy_wdly_dqs_inc_re <= builder_interface1_bank_bus_we;
     end
 end
-assign k7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
+assign main_k7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    k7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin
-        k7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
+    main_k7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin
+        main_k7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    k7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin
-        k7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
+    main_k7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin
+        main_k7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
     end
 end
-assign k7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
+assign main_k7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    k7ddrphy_wdly_dq_bitslip_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin
-        k7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we);
+    main_k7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin
+        main_k7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    k7ddrphy_wdly_dq_bitslip_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin
-        k7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we;
+    main_k7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin
+        main_k7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
     end
 end
-assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0];
+assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    csrbank1_rdphase0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin
-        csrbank1_rdphase0_re <= interface1_bank_bus_we;
+    builder_csrbank1_rdphase0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd17))) begin
+        builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank1_rdphase0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin
-        csrbank1_rdphase0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_rdphase0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd17))) begin
+        builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
     end
 end
-assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0];
+assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    csrbank1_wrphase0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin
-        csrbank1_wrphase0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_wrphase0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd18))) begin
+        builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_wrphase0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin
-        csrbank1_wrphase0_re <= interface1_bank_bus_we;
+    builder_csrbank1_wrphase0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd18))) begin
+        builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign csrbank1_rst0_w = k7ddrphy_rst_storage;
-assign csrbank1_dly_sel0_w = k7ddrphy_dly_sel_storage[3:0];
-assign csrbank1_half_sys8x_taps0_w = k7ddrphy_half_sys8x_taps_storage[4:0];
-assign csrbank1_wlevel_en0_w = k7ddrphy_wlevel_en_storage;
-assign csrbank1_rdphase0_w = k7ddrphy_rdphase_storage[1:0];
-assign csrbank1_wrphase0_w = k7ddrphy_wrphase_storage[1:0];
-assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2);
-assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
+assign builder_csrbank1_rst0_w = main_k7ddrphy_rst_storage;
+assign builder_csrbank1_dly_sel0_w = main_k7ddrphy_dly_sel_storage[3:0];
+assign builder_csrbank1_half_sys8x_taps0_w = main_k7ddrphy_half_sys8x_taps_storage[4:0];
+assign builder_csrbank1_wlevel_en0_w = main_k7ddrphy_wlevel_en_storage;
+assign builder_csrbank1_rdphase0_w = main_k7ddrphy_rdphase_storage[1:0];
+assign builder_csrbank1_wrphase0_w = main_k7ddrphy_wrphase_storage[1:0];
+assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
+assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
 always @(*) begin
-    csrbank2_dfii_control0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank2_dfii_control0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_control0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_control0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_control0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
+assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi0_command0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_command0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_command0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
+assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    litedramcore_phaseinjector0_command_issue_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
-        litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
+    main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
+        main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    litedramcore_phaseinjector0_command_issue_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
-        litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
+    main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
+        main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0];
+assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-    csrbank2_dfii_pi0_address0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
+        builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_address0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_address0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
+        builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank2_dfii_pi0_baddress0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
-        csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
+        builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_baddress0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
-        csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
+        builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
-        csrbank2_dfii_pi0_wrdata1_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
+        builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_wrdata1_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
-        csrbank2_dfii_pi0_wrdata1_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_wrdata1_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
+        builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
-        csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
+        builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
-        csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
+        builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi0_rddata1_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi0_rddata1_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
-        csrbank2_dfii_pi0_rddata1_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
+        builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_rddata1_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
-        csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
+        builder_csrbank2_dfii_pi0_rddata1_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi0_rddata0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
-        csrbank2_dfii_pi0_rddata0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
+        builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_rddata0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
-        csrbank2_dfii_pi0_rddata0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_rddata0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
+        builder_csrbank2_dfii_pi0_rddata0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
+assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi1_command0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
-        csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
+        builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_command0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
-        csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_command0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
+        builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
+assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    litedramcore_phaseinjector1_command_issue_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
-        litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we;
+    main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
+        main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    litedramcore_phaseinjector1_command_issue_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
-        litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
+    main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
+        main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0];
+assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-    csrbank2_dfii_pi1_address0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
-        csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_address0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
+        builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_address0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
-        csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
+        builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank2_dfii_pi1_baddress0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
-        csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
+        builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_baddress0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
-        csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
+        builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
-        csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
+        builder_csrbank2_dfii_pi1_wrdata1_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
-        csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
+        builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
-        csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
+        builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
-        csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
+        builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi1_rddata1_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi1_rddata1_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
-        csrbank2_dfii_pi1_rddata1_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
+        builder_csrbank2_dfii_pi1_rddata1_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_rddata1_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
-        csrbank2_dfii_pi1_rddata1_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
+        builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi1_rddata0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
-        csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
+        builder_csrbank2_dfii_pi1_rddata0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_rddata0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
-        csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
+        builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0];
+assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi2_command0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
-        csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_command0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+        builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_command0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
-        csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_command0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+        builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0];
+assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    litedramcore_phaseinjector2_command_issue_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
-        litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we;
+    main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+        main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    litedramcore_phaseinjector2_command_issue_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
-        litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we);
+    main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+        main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[14:0];
+assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-    csrbank2_dfii_pi2_address0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
-        csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
+        builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_address0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
-        csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_address0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
+        builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank2_dfii_pi2_baddress0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
-        csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
+        builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_baddress0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
-        csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
+        builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi2_wrdata1_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi2_wrdata1_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
-        csrbank2_dfii_pi2_wrdata1_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
+        builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_wrdata1_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
-        csrbank2_dfii_pi2_wrdata1_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
+        builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
-        csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+        builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
-        csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+        builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi2_rddata1_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi2_rddata1_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi2_rddata1_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
-        csrbank2_dfii_pi2_rddata1_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_rddata1_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
+        builder_csrbank2_dfii_pi2_rddata1_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_rddata1_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
-        csrbank2_dfii_pi2_rddata1_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_rddata1_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
+        builder_csrbank2_dfii_pi2_rddata1_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi2_rddata0_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi2_rddata0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
-        csrbank2_dfii_pi2_rddata0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
+        builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_rddata0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
-        csrbank2_dfii_pi2_rddata0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
+        builder_csrbank2_dfii_pi2_rddata0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0];
+assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi3_command0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd25))) begin
-        csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin
+        builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_command0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd25))) begin
-        csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_command0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin
+        builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0];
+assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    litedramcore_phaseinjector3_command_issue_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd26))) begin
-        litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we);
+    main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin
+        main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    litedramcore_phaseinjector3_command_issue_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd26))) begin
-        litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we;
+    main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin
+        main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[14:0];
+assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-    csrbank2_dfii_pi3_address0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd27))) begin
-        csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_address0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin
+        builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_address0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd27))) begin
-        csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin
+        builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank2_dfii_pi3_baddress0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd28))) begin
-        csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
+        builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_baddress0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd28))) begin
-        csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
+        builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi3_wrdata1_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi3_wrdata1_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd29))) begin
-        csrbank2_dfii_pi3_wrdata1_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
+        builder_csrbank2_dfii_pi3_wrdata1_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_wrdata1_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd29))) begin
-        csrbank2_dfii_pi3_wrdata1_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
+        builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd30))) begin
-        csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin
+        builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd30))) begin
-        csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin
+        builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi3_rddata1_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi3_rddata1_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi3_rddata1_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd31))) begin
-        csrbank2_dfii_pi3_rddata1_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_rddata1_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin
+        builder_csrbank2_dfii_pi3_rddata1_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_rddata1_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd31))) begin
-        csrbank2_dfii_pi3_rddata1_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_rddata1_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin
+        builder_csrbank2_dfii_pi3_rddata1_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi3_rddata0_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi3_rddata0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 6'd32))) begin
-        csrbank2_dfii_pi3_rddata0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin
+        builder_csrbank2_dfii_pi3_rddata0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_rddata0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 6'd32))) begin
-        csrbank2_dfii_pi3_rddata0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin
+        builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign litedramcore_sel = litedramcore_storage[0];
-assign litedramcore_cke = litedramcore_storage[1];
-assign litedramcore_odt = litedramcore_storage[2];
-assign litedramcore_reset_n = litedramcore_storage[3];
-assign csrbank2_dfii_control0_w = litedramcore_storage[3:0];
-assign litedramcore_phaseinjector0_csrfield_cs = litedramcore_phaseinjector0_command_storage[0];
-assign litedramcore_phaseinjector0_csrfield_we = litedramcore_phaseinjector0_command_storage[1];
-assign litedramcore_phaseinjector0_csrfield_cas = litedramcore_phaseinjector0_command_storage[2];
-assign litedramcore_phaseinjector0_csrfield_ras = litedramcore_phaseinjector0_command_storage[3];
-assign litedramcore_phaseinjector0_csrfield_wren = litedramcore_phaseinjector0_command_storage[4];
-assign litedramcore_phaseinjector0_csrfield_rden = litedramcore_phaseinjector0_command_storage[5];
-assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
-assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0];
-assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
-assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[63:32];
-assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
-assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_rddata_status[63:32];
-assign csrbank2_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_rddata_status[31:0];
-assign litedramcore_phaseinjector0_rddata_we = csrbank2_dfii_pi0_rddata0_we;
-assign litedramcore_phaseinjector1_csrfield_cs = litedramcore_phaseinjector1_command_storage[0];
-assign litedramcore_phaseinjector1_csrfield_we = litedramcore_phaseinjector1_command_storage[1];
-assign litedramcore_phaseinjector1_csrfield_cas = litedramcore_phaseinjector1_command_storage[2];
-assign litedramcore_phaseinjector1_csrfield_ras = litedramcore_phaseinjector1_command_storage[3];
-assign litedramcore_phaseinjector1_csrfield_wren = litedramcore_phaseinjector1_command_storage[4];
-assign litedramcore_phaseinjector1_csrfield_rden = litedramcore_phaseinjector1_command_storage[5];
-assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
-assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[14:0];
-assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
-assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[63:32];
-assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
-assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_rddata_status[63:32];
-assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_rddata_status[31:0];
-assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata0_we;
-assign litedramcore_phaseinjector2_csrfield_cs = litedramcore_phaseinjector2_command_storage[0];
-assign litedramcore_phaseinjector2_csrfield_we = litedramcore_phaseinjector2_command_storage[1];
-assign litedramcore_phaseinjector2_csrfield_cas = litedramcore_phaseinjector2_command_storage[2];
-assign litedramcore_phaseinjector2_csrfield_ras = litedramcore_phaseinjector2_command_storage[3];
-assign litedramcore_phaseinjector2_csrfield_wren = litedramcore_phaseinjector2_command_storage[4];
-assign litedramcore_phaseinjector2_csrfield_rden = litedramcore_phaseinjector2_command_storage[5];
-assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
-assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[14:0];
-assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
-assign csrbank2_dfii_pi2_wrdata1_w = litedramcore_phaseinjector2_wrdata_storage[63:32];
-assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0];
-assign csrbank2_dfii_pi2_rddata1_w = litedramcore_phaseinjector2_rddata_status[63:32];
-assign csrbank2_dfii_pi2_rddata0_w = litedramcore_phaseinjector2_rddata_status[31:0];
-assign litedramcore_phaseinjector2_rddata_we = csrbank2_dfii_pi2_rddata0_we;
-assign litedramcore_phaseinjector3_csrfield_cs = litedramcore_phaseinjector3_command_storage[0];
-assign litedramcore_phaseinjector3_csrfield_we = litedramcore_phaseinjector3_command_storage[1];
-assign litedramcore_phaseinjector3_csrfield_cas = litedramcore_phaseinjector3_command_storage[2];
-assign litedramcore_phaseinjector3_csrfield_ras = litedramcore_phaseinjector3_command_storage[3];
-assign litedramcore_phaseinjector3_csrfield_wren = litedramcore_phaseinjector3_command_storage[4];
-assign litedramcore_phaseinjector3_csrfield_rden = litedramcore_phaseinjector3_command_storage[5];
-assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
-assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[14:0];
-assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
-assign csrbank2_dfii_pi3_wrdata1_w = litedramcore_phaseinjector3_wrdata_storage[63:32];
-assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0];
-assign csrbank2_dfii_pi3_rddata1_w = litedramcore_phaseinjector3_rddata_status[63:32];
-assign csrbank2_dfii_pi3_rddata0_w = litedramcore_phaseinjector3_rddata_status[31:0];
-assign litedramcore_phaseinjector3_rddata_we = csrbank2_dfii_pi3_rddata0_we;
-assign csr_interconnect_adr = litedramcore_adr;
-assign csr_interconnect_we = litedramcore_we;
-assign csr_interconnect_dat_w = litedramcore_dat_w;
-assign litedramcore_dat_r = csr_interconnect_dat_r;
-assign interface0_bank_bus_adr = csr_interconnect_adr;
-assign interface1_bank_bus_adr = csr_interconnect_adr;
-assign interface2_bank_bus_adr = csr_interconnect_adr;
-assign interface0_bank_bus_we = csr_interconnect_we;
-assign interface1_bank_bus_we = csr_interconnect_we;
-assign interface2_bank_bus_we = csr_interconnect_we;
-assign interface0_bank_bus_dat_w = csr_interconnect_dat_w;
-assign interface1_bank_bus_dat_w = csr_interconnect_dat_w;
-assign interface2_bank_bus_dat_w = csr_interconnect_dat_w;
-assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
-always @(*) begin
-    rhs_array_muxed0 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+assign main_litedramcore_sel = main_litedramcore_storage[0];
+assign main_litedramcore_cke = main_litedramcore_storage[1];
+assign main_litedramcore_odt = main_litedramcore_storage[2];
+assign main_litedramcore_reset_n = main_litedramcore_storage[3];
+assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0];
+assign main_litedramcore_phaseinjector0_csrfield_cs = main_litedramcore_phaseinjector0_command_storage[0];
+assign main_litedramcore_phaseinjector0_csrfield_we = main_litedramcore_phaseinjector0_command_storage[1];
+assign main_litedramcore_phaseinjector0_csrfield_cas = main_litedramcore_phaseinjector0_command_storage[2];
+assign main_litedramcore_phaseinjector0_csrfield_ras = main_litedramcore_phaseinjector0_command_storage[3];
+assign main_litedramcore_phaseinjector0_csrfield_wren = main_litedramcore_phaseinjector0_command_storage[4];
+assign main_litedramcore_phaseinjector0_csrfield_rden = main_litedramcore_phaseinjector0_command_storage[5];
+assign main_litedramcore_phaseinjector0_csrfield_cs_top = main_litedramcore_phaseinjector0_command_storage[6];
+assign main_litedramcore_phaseinjector0_csrfield_cs_bottom = main_litedramcore_phaseinjector0_command_storage[7];
+assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[7:0];
+assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[14:0];
+assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi0_wrdata1_w = main_litedramcore_phaseinjector0_wrdata_storage[63:32];
+assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi0_rddata1_w = main_litedramcore_phaseinjector0_rddata_status[63:32];
+assign builder_csrbank2_dfii_pi0_rddata0_w = main_litedramcore_phaseinjector0_rddata_status[31:0];
+assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata0_we;
+assign main_litedramcore_phaseinjector1_csrfield_cs = main_litedramcore_phaseinjector1_command_storage[0];
+assign main_litedramcore_phaseinjector1_csrfield_we = main_litedramcore_phaseinjector1_command_storage[1];
+assign main_litedramcore_phaseinjector1_csrfield_cas = main_litedramcore_phaseinjector1_command_storage[2];
+assign main_litedramcore_phaseinjector1_csrfield_ras = main_litedramcore_phaseinjector1_command_storage[3];
+assign main_litedramcore_phaseinjector1_csrfield_wren = main_litedramcore_phaseinjector1_command_storage[4];
+assign main_litedramcore_phaseinjector1_csrfield_rden = main_litedramcore_phaseinjector1_command_storage[5];
+assign main_litedramcore_phaseinjector1_csrfield_cs_top = main_litedramcore_phaseinjector1_command_storage[6];
+assign main_litedramcore_phaseinjector1_csrfield_cs_bottom = main_litedramcore_phaseinjector1_command_storage[7];
+assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[7:0];
+assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[14:0];
+assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi1_wrdata1_w = main_litedramcore_phaseinjector1_wrdata_storage[63:32];
+assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi1_rddata1_w = main_litedramcore_phaseinjector1_rddata_status[63:32];
+assign builder_csrbank2_dfii_pi1_rddata0_w = main_litedramcore_phaseinjector1_rddata_status[31:0];
+assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata0_we;
+assign main_litedramcore_phaseinjector2_csrfield_cs = main_litedramcore_phaseinjector2_command_storage[0];
+assign main_litedramcore_phaseinjector2_csrfield_we = main_litedramcore_phaseinjector2_command_storage[1];
+assign main_litedramcore_phaseinjector2_csrfield_cas = main_litedramcore_phaseinjector2_command_storage[2];
+assign main_litedramcore_phaseinjector2_csrfield_ras = main_litedramcore_phaseinjector2_command_storage[3];
+assign main_litedramcore_phaseinjector2_csrfield_wren = main_litedramcore_phaseinjector2_command_storage[4];
+assign main_litedramcore_phaseinjector2_csrfield_rden = main_litedramcore_phaseinjector2_command_storage[5];
+assign main_litedramcore_phaseinjector2_csrfield_cs_top = main_litedramcore_phaseinjector2_command_storage[6];
+assign main_litedramcore_phaseinjector2_csrfield_cs_bottom = main_litedramcore_phaseinjector2_command_storage[7];
+assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[7:0];
+assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[14:0];
+assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi2_wrdata1_w = main_litedramcore_phaseinjector2_wrdata_storage[63:32];
+assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi2_rddata1_w = main_litedramcore_phaseinjector2_rddata_status[63:32];
+assign builder_csrbank2_dfii_pi2_rddata0_w = main_litedramcore_phaseinjector2_rddata_status[31:0];
+assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata0_we;
+assign main_litedramcore_phaseinjector3_csrfield_cs = main_litedramcore_phaseinjector3_command_storage[0];
+assign main_litedramcore_phaseinjector3_csrfield_we = main_litedramcore_phaseinjector3_command_storage[1];
+assign main_litedramcore_phaseinjector3_csrfield_cas = main_litedramcore_phaseinjector3_command_storage[2];
+assign main_litedramcore_phaseinjector3_csrfield_ras = main_litedramcore_phaseinjector3_command_storage[3];
+assign main_litedramcore_phaseinjector3_csrfield_wren = main_litedramcore_phaseinjector3_command_storage[4];
+assign main_litedramcore_phaseinjector3_csrfield_rden = main_litedramcore_phaseinjector3_command_storage[5];
+assign main_litedramcore_phaseinjector3_csrfield_cs_top = main_litedramcore_phaseinjector3_command_storage[6];
+assign main_litedramcore_phaseinjector3_csrfield_cs_bottom = main_litedramcore_phaseinjector3_command_storage[7];
+assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[7:0];
+assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[14:0];
+assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi3_wrdata1_w = main_litedramcore_phaseinjector3_wrdata_storage[63:32];
+assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi3_rddata1_w = main_litedramcore_phaseinjector3_rddata_status[63:32];
+assign builder_csrbank2_dfii_pi3_rddata0_w = main_litedramcore_phaseinjector3_rddata_status[31:0];
+assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata0_we;
+assign builder_adr = builder_interface1_adr;
+assign builder_we = builder_interface1_we;
+assign builder_dat_w = builder_interface1_dat_w;
+assign builder_interface1_dat_r = builder_dat_r;
+assign builder_interface0_bank_bus_adr = builder_adr;
+assign builder_interface1_bank_bus_adr = builder_adr;
+assign builder_interface2_bank_bus_adr = builder_adr;
+assign builder_interface0_bank_bus_we = builder_we;
+assign builder_interface1_bank_bus_we = builder_we;
+assign builder_interface2_bank_bus_we = builder_we;
+assign builder_interface0_bank_bus_dat_w = builder_dat_w;
+assign builder_interface1_bank_bus_dat_w = builder_dat_w;
+assign builder_interface2_bank_bus_dat_w = builder_dat_w;
+assign builder_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r);
+always @(*) begin
+    builder_rhs_self0 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[0];
         end
         1'd1: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[1];
         end
         2'd2: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[2];
         end
         2'd3: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[3];
         end
         3'd4: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[4];
         end
         3'd5: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[5];
         end
         3'd6: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[6];
         end
         default: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[7];
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed1 <= 15'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_rhs_self1 <= 15'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine0_cmd_payload_a;
         end
         1'd1: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine1_cmd_payload_a;
         end
         2'd2: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine2_cmd_payload_a;
         end
         2'd3: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine3_cmd_payload_a;
         end
         3'd4: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine4_cmd_payload_a;
         end
         3'd5: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine5_cmd_payload_a;
         end
         3'd6: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine6_cmd_payload_a;
         end
         default: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine7_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed2 <= 3'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_rhs_self2 <= 3'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine0_cmd_payload_ba;
         end
         1'd1: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine1_cmd_payload_ba;
         end
         2'd2: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine2_cmd_payload_ba;
         end
         2'd3: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine3_cmd_payload_ba;
         end
         3'd4: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine4_cmd_payload_ba;
         end
         3'd5: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine5_cmd_payload_ba;
         end
         3'd6: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine6_cmd_payload_ba;
         end
         default: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine7_cmd_payload_ba;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed3 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_rhs_self3 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine0_cmd_payload_is_read;
         end
         1'd1: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine1_cmd_payload_is_read;
         end
         2'd2: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine2_cmd_payload_is_read;
         end
         2'd3: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine3_cmd_payload_is_read;
         end
         3'd4: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine4_cmd_payload_is_read;
         end
         3'd5: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine5_cmd_payload_is_read;
         end
         3'd6: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine6_cmd_payload_is_read;
         end
         default: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed4 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_rhs_self4 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine0_cmd_payload_is_write;
         end
         1'd1: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine1_cmd_payload_is_write;
         end
         2'd2: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine2_cmd_payload_is_write;
         end
         2'd3: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine3_cmd_payload_is_write;
         end
         3'd4: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine4_cmd_payload_is_write;
         end
         3'd5: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine5_cmd_payload_is_write;
         end
         3'd6: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine6_cmd_payload_is_write;
         end
         default: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed5 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_rhs_self5 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd;
         end
         1'd1: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd;
         end
         2'd2: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd;
         end
         2'd3: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd;
         end
         3'd4: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd;
         end
         3'd5: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd;
         end
         3'd6: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd;
         end
         default: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed0 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_t_self0 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine0_cmd_payload_cas;
         end
         1'd1: begin
-            t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine1_cmd_payload_cas;
         end
         2'd2: begin
-            t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine2_cmd_payload_cas;
         end
         2'd3: begin
-            t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine3_cmd_payload_cas;
         end
         3'd4: begin
-            t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine4_cmd_payload_cas;
         end
         3'd5: begin
-            t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine5_cmd_payload_cas;
         end
         3'd6: begin
-            t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine6_cmd_payload_cas;
         end
         default: begin
-            t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine7_cmd_payload_cas;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed1 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_t_self1 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine0_cmd_payload_ras;
         end
         1'd1: begin
-            t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine1_cmd_payload_ras;
         end
         2'd2: begin
-            t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine2_cmd_payload_ras;
         end
         2'd3: begin
-            t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine3_cmd_payload_ras;
         end
         3'd4: begin
-            t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine4_cmd_payload_ras;
         end
         3'd5: begin
-            t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine5_cmd_payload_ras;
         end
         3'd6: begin
-            t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine6_cmd_payload_ras;
         end
         default: begin
-            t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine7_cmd_payload_ras;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed2 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_t_self2 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine0_cmd_payload_we;
         end
         1'd1: begin
-            t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine1_cmd_payload_we;
         end
         2'd2: begin
-            t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine2_cmd_payload_we;
         end
         2'd3: begin
-            t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine3_cmd_payload_we;
         end
         3'd4: begin
-            t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine4_cmd_payload_we;
         end
         3'd5: begin
-            t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine5_cmd_payload_we;
         end
         3'd6: begin
-            t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine6_cmd_payload_we;
         end
         default: begin
-            t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine7_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed6 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self6 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[0];
         end
         1'd1: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[1];
         end
         2'd2: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[2];
         end
         2'd3: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[3];
         end
         3'd4: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[4];
         end
         3'd5: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[5];
         end
         3'd6: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[6];
         end
         default: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[7];
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed7 <= 15'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self7 <= 15'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine0_cmd_payload_a;
         end
         1'd1: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine1_cmd_payload_a;
         end
         2'd2: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine2_cmd_payload_a;
         end
         2'd3: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine3_cmd_payload_a;
         end
         3'd4: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine4_cmd_payload_a;
         end
         3'd5: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine5_cmd_payload_a;
         end
         3'd6: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine6_cmd_payload_a;
         end
         default: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine7_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed8 <= 3'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self8 <= 3'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine0_cmd_payload_ba;
         end
         1'd1: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine1_cmd_payload_ba;
         end
         2'd2: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine2_cmd_payload_ba;
         end
         2'd3: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine3_cmd_payload_ba;
         end
         3'd4: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine4_cmd_payload_ba;
         end
         3'd5: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine5_cmd_payload_ba;
         end
         3'd6: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine6_cmd_payload_ba;
         end
         default: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine7_cmd_payload_ba;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed9 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self9 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine0_cmd_payload_is_read;
         end
         1'd1: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine1_cmd_payload_is_read;
         end
         2'd2: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine2_cmd_payload_is_read;
         end
         2'd3: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine3_cmd_payload_is_read;
         end
         3'd4: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine4_cmd_payload_is_read;
         end
         3'd5: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine5_cmd_payload_is_read;
         end
         3'd6: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine6_cmd_payload_is_read;
         end
         default: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed10 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self10 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine0_cmd_payload_is_write;
         end
         1'd1: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine1_cmd_payload_is_write;
         end
         2'd2: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine2_cmd_payload_is_write;
         end
         2'd3: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine3_cmd_payload_is_write;
         end
         3'd4: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine4_cmd_payload_is_write;
         end
         3'd5: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine5_cmd_payload_is_write;
         end
         3'd6: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine6_cmd_payload_is_write;
         end
         default: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed11 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self11 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd;
         end
         1'd1: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd;
         end
         2'd2: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd;
         end
         2'd3: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd;
         end
         3'd4: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd;
         end
         3'd5: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd;
         end
         3'd6: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd;
         end
         default: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed3 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_t_self3 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine0_cmd_payload_cas;
         end
         1'd1: begin
-            t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine1_cmd_payload_cas;
         end
         2'd2: begin
-            t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine2_cmd_payload_cas;
         end
         2'd3: begin
-            t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine3_cmd_payload_cas;
         end
         3'd4: begin
-            t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine4_cmd_payload_cas;
         end
         3'd5: begin
-            t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine5_cmd_payload_cas;
         end
         3'd6: begin
-            t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine6_cmd_payload_cas;
         end
         default: begin
-            t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine7_cmd_payload_cas;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed4 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_t_self4 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine0_cmd_payload_ras;
         end
         1'd1: begin
-            t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine1_cmd_payload_ras;
         end
         2'd2: begin
-            t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine2_cmd_payload_ras;
         end
         2'd3: begin
-            t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine3_cmd_payload_ras;
         end
         3'd4: begin
-            t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine4_cmd_payload_ras;
         end
         3'd5: begin
-            t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine5_cmd_payload_ras;
         end
         3'd6: begin
-            t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine6_cmd_payload_ras;
         end
         default: begin
-            t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine7_cmd_payload_ras;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed5 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_t_self5 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine0_cmd_payload_we;
         end
         1'd1: begin
-            t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine1_cmd_payload_we;
         end
         2'd2: begin
-            t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine2_cmd_payload_we;
         end
         2'd3: begin
-            t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine3_cmd_payload_we;
         end
         3'd4: begin
-            t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine4_cmd_payload_we;
         end
         3'd5: begin
-            t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine5_cmd_payload_we;
         end
         3'd6: begin
-            t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine6_cmd_payload_we;
         end
         default: begin
-            t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine7_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed12 <= 22'd0;
-    case (litedramcore_roundrobin0_grant)
+    builder_rhs_self12 <= 22'd0;
+    case (builder_roundrobin0_grant)
         default: begin
-            rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self12 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed13 <= 1'd0;
-    case (litedramcore_roundrobin0_grant)
+    builder_rhs_self13 <= 1'd0;
+    case (builder_roundrobin0_grant)
         default: begin
-            rhs_array_muxed13 <= user_port_cmd_payload_we;
+            builder_rhs_self13 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed14 <= 1'd0;
-    case (litedramcore_roundrobin0_grant)
+    builder_rhs_self14 <= 1'd0;
+    case (builder_roundrobin0_grant)
         default: begin
-            rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed15 <= 22'd0;
-    case (litedramcore_roundrobin1_grant)
+    builder_rhs_self15 <= 22'd0;
+    case (builder_roundrobin1_grant)
         default: begin
-            rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self15 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed16 <= 1'd0;
-    case (litedramcore_roundrobin1_grant)
+    builder_rhs_self16 <= 1'd0;
+    case (builder_roundrobin1_grant)
         default: begin
-            rhs_array_muxed16 <= user_port_cmd_payload_we;
+            builder_rhs_self16 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed17 <= 1'd0;
-    case (litedramcore_roundrobin1_grant)
+    builder_rhs_self17 <= 1'd0;
+    case (builder_roundrobin1_grant)
         default: begin
-            rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed18 <= 22'd0;
-    case (litedramcore_roundrobin2_grant)
+    builder_rhs_self18 <= 22'd0;
+    case (builder_roundrobin2_grant)
         default: begin
-            rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self18 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed19 <= 1'd0;
-    case (litedramcore_roundrobin2_grant)
+    builder_rhs_self19 <= 1'd0;
+    case (builder_roundrobin2_grant)
         default: begin
-            rhs_array_muxed19 <= user_port_cmd_payload_we;
+            builder_rhs_self19 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed20 <= 1'd0;
-    case (litedramcore_roundrobin2_grant)
+    builder_rhs_self20 <= 1'd0;
+    case (builder_roundrobin2_grant)
         default: begin
-            rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed21 <= 22'd0;
-    case (litedramcore_roundrobin3_grant)
+    builder_rhs_self21 <= 22'd0;
+    case (builder_roundrobin3_grant)
         default: begin
-            rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self21 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed22 <= 1'd0;
-    case (litedramcore_roundrobin3_grant)
+    builder_rhs_self22 <= 1'd0;
+    case (builder_roundrobin3_grant)
         default: begin
-            rhs_array_muxed22 <= user_port_cmd_payload_we;
+            builder_rhs_self22 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed23 <= 1'd0;
-    case (litedramcore_roundrobin3_grant)
+    builder_rhs_self23 <= 1'd0;
+    case (builder_roundrobin3_grant)
         default: begin
-            rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed24 <= 22'd0;
-    case (litedramcore_roundrobin4_grant)
+    builder_rhs_self24 <= 22'd0;
+    case (builder_roundrobin4_grant)
         default: begin
-            rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self24 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed25 <= 1'd0;
-    case (litedramcore_roundrobin4_grant)
+    builder_rhs_self25 <= 1'd0;
+    case (builder_roundrobin4_grant)
         default: begin
-            rhs_array_muxed25 <= user_port_cmd_payload_we;
+            builder_rhs_self25 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed26 <= 1'd0;
-    case (litedramcore_roundrobin4_grant)
+    builder_rhs_self26 <= 1'd0;
+    case (builder_roundrobin4_grant)
         default: begin
-            rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed27 <= 22'd0;
-    case (litedramcore_roundrobin5_grant)
+    builder_rhs_self27 <= 22'd0;
+    case (builder_roundrobin5_grant)
         default: begin
-            rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self27 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed28 <= 1'd0;
-    case (litedramcore_roundrobin5_grant)
+    builder_rhs_self28 <= 1'd0;
+    case (builder_roundrobin5_grant)
         default: begin
-            rhs_array_muxed28 <= user_port_cmd_payload_we;
+            builder_rhs_self28 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed29 <= 1'd0;
-    case (litedramcore_roundrobin5_grant)
+    builder_rhs_self29 <= 1'd0;
+    case (builder_roundrobin5_grant)
         default: begin
-            rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed30 <= 22'd0;
-    case (litedramcore_roundrobin6_grant)
+    builder_rhs_self30 <= 22'd0;
+    case (builder_roundrobin6_grant)
         default: begin
-            rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self30 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed31 <= 1'd0;
-    case (litedramcore_roundrobin6_grant)
+    builder_rhs_self31 <= 1'd0;
+    case (builder_roundrobin6_grant)
         default: begin
-            rhs_array_muxed31 <= user_port_cmd_payload_we;
+            builder_rhs_self31 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed32 <= 1'd0;
-    case (litedramcore_roundrobin6_grant)
+    builder_rhs_self32 <= 1'd0;
+    case (builder_roundrobin6_grant)
         default: begin
-            rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed33 <= 22'd0;
-    case (litedramcore_roundrobin7_grant)
+    builder_rhs_self33 <= 22'd0;
+    case (builder_roundrobin7_grant)
         default: begin
-            rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self33 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed34 <= 1'd0;
-    case (litedramcore_roundrobin7_grant)
+    builder_rhs_self34 <= 1'd0;
+    case (builder_roundrobin7_grant)
         default: begin
-            rhs_array_muxed34 <= user_port_cmd_payload_we;
+            builder_rhs_self34 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed35 <= 1'd0;
-    case (litedramcore_roundrobin7_grant)
+    builder_rhs_self35 <= 1'd0;
+    case (builder_roundrobin7_grant)
         default: begin
-            rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    array_muxed0 <= 3'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self0 <= 3'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed0 <= litedramcore_nop_ba[2:0];
+            builder_self0 <= main_litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed1 <= 15'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self1 <= 15'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed1 <= litedramcore_nop_a;
+            builder_self1 <= main_litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
+            builder_self1 <= main_litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
+            builder_self1 <= main_litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed1 <= litedramcore_cmd_payload_a;
+            builder_self1 <= main_litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed2 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self2 <= 1'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed2 <= 1'd0;
+            builder_self2 <= 1'd0;
         end
         1'd1: begin
-            array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+            builder_self2 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+            builder_self2 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+            builder_self2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed3 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self3 <= 1'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed3 <= 1'd0;
+            builder_self3 <= 1'd0;
         end
         1'd1: begin
-            array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+            builder_self3 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+            builder_self3 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+            builder_self3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed4 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self4 <= 1'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed4 <= 1'd0;
+            builder_self4 <= 1'd0;
         end
         1'd1: begin
-            array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+            builder_self4 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+            builder_self4 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+            builder_self4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed5 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self5 <= 1'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed5 <= 1'd0;
+            builder_self5 <= 1'd0;
         end
         1'd1: begin
-            array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+            builder_self5 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+            builder_self5 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+            builder_self5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed6 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self6 <= 1'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed6 <= 1'd0;
+            builder_self6 <= 1'd0;
         end
         1'd1: begin
-            array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+            builder_self6 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+            builder_self6 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+            builder_self6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
         end
     endcase
 end
 always @(*) begin
-    array_muxed7 <= 3'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self7 <= 3'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed7 <= litedramcore_nop_ba[2:0];
+            builder_self7 <= main_litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed8 <= 15'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self8 <= 15'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed8 <= litedramcore_nop_a;
+            builder_self8 <= main_litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
+            builder_self8 <= main_litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
+            builder_self8 <= main_litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed8 <= litedramcore_cmd_payload_a;
+            builder_self8 <= main_litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed9 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self9 <= 1'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed9 <= 1'd0;
+            builder_self9 <= 1'd0;
         end
         1'd1: begin
-            array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+            builder_self9 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+            builder_self9 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+            builder_self9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed10 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self10 <= 1'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed10 <= 1'd0;
+            builder_self10 <= 1'd0;
         end
         1'd1: begin
-            array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+            builder_self10 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+            builder_self10 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+            builder_self10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed11 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self11 <= 1'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed11 <= 1'd0;
+            builder_self11 <= 1'd0;
         end
         1'd1: begin
-            array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+            builder_self11 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+            builder_self11 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+            builder_self11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed12 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self12 <= 1'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed12 <= 1'd0;
+            builder_self12 <= 1'd0;
         end
         1'd1: begin
-            array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+            builder_self12 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+            builder_self12 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+            builder_self12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed13 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self13 <= 1'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed13 <= 1'd0;
+            builder_self13 <= 1'd0;
         end
         1'd1: begin
-            array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+            builder_self13 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+            builder_self13 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+            builder_self13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
         end
     endcase
 end
 always @(*) begin
-    array_muxed14 <= 3'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self14 <= 3'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed14 <= litedramcore_nop_ba[2:0];
+            builder_self14 <= main_litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed14 <= litedramcore_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed15 <= 15'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self15 <= 15'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed15 <= litedramcore_nop_a;
+            builder_self15 <= main_litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a;
+            builder_self15 <= main_litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed15 <= litedramcore_choose_req_cmd_payload_a;
+            builder_self15 <= main_litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed15 <= litedramcore_cmd_payload_a;
+            builder_self15 <= main_litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed16 <= 1'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self16 <= 1'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed16 <= 1'd0;
+            builder_self16 <= 1'd0;
         end
         1'd1: begin
-            array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+            builder_self16 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+            builder_self16 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+            builder_self16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed17 <= 1'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self17 <= 1'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed17 <= 1'd0;
+            builder_self17 <= 1'd0;
         end
         1'd1: begin
-            array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+            builder_self17 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+            builder_self17 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+            builder_self17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed18 <= 1'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self18 <= 1'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed18 <= 1'd0;
+            builder_self18 <= 1'd0;
         end
         1'd1: begin
-            array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+            builder_self18 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+            builder_self18 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+            builder_self18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed19 <= 1'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self19 <= 1'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed19 <= 1'd0;
+            builder_self19 <= 1'd0;
         end
         1'd1: begin
-            array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+            builder_self19 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+            builder_self19 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+            builder_self19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed20 <= 1'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self20 <= 1'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed20 <= 1'd0;
+            builder_self20 <= 1'd0;
         end
         1'd1: begin
-            array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+            builder_self20 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+            builder_self20 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+            builder_self20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
         end
     endcase
 end
 always @(*) begin
-    array_muxed21 <= 3'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self21 <= 3'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed21 <= litedramcore_nop_ba[2:0];
+            builder_self21 <= main_litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed21 <= litedramcore_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed22 <= 15'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self22 <= 15'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed22 <= litedramcore_nop_a;
+            builder_self22 <= main_litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a;
+            builder_self22 <= main_litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed22 <= litedramcore_choose_req_cmd_payload_a;
+            builder_self22 <= main_litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed22 <= litedramcore_cmd_payload_a;
+            builder_self22 <= main_litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed23 <= 1'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self23 <= 1'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed23 <= 1'd0;
+            builder_self23 <= 1'd0;
         end
         1'd1: begin
-            array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+            builder_self23 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+            builder_self23 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+            builder_self23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed24 <= 1'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self24 <= 1'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed24 <= 1'd0;
+            builder_self24 <= 1'd0;
         end
         1'd1: begin
-            array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+            builder_self24 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+            builder_self24 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+            builder_self24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed25 <= 1'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self25 <= 1'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed25 <= 1'd0;
+            builder_self25 <= 1'd0;
         end
         1'd1: begin
-            array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+            builder_self25 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+            builder_self25 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+            builder_self25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed26 <= 1'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self26 <= 1'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed26 <= 1'd0;
+            builder_self26 <= 1'd0;
         end
         1'd1: begin
-            array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+            builder_self26 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+            builder_self26 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+            builder_self26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed27 <= 1'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self27 <= 1'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed27 <= 1'd0;
+            builder_self27 <= 1'd0;
         end
         1'd1: begin
-            array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+            builder_self27 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+            builder_self27 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+            builder_self27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
         end
     endcase
 end
-assign xilinxasyncresetsynchronizerimpl0 = (~locked);
-assign xilinxasyncresetsynchronizerimpl1 = (~locked);
-assign xilinxasyncresetsynchronizerimpl2 = (~locked);
-assign xilinxasyncresetsynchronizerimpl3 = (~locked);
+assign builder_xilinxasyncresetsynchronizerimpl0_async_reset = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl1_async_reset = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl2_async_reset = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl3_async_reset = (~main_locked);
 
 
 //------------------------------------------------------------------------------
@@ -13660,1295 +14248,1295 @@ assign xilinxasyncresetsynchronizerimpl3 = (~locked);
 //------------------------------------------------------------------------------
 
 always @(posedge iodelay_clk) begin
-    if ((reset_counter != 1'd0)) begin
-        reset_counter <= (reset_counter - 1'd1);
+    if ((main_reset_counter != 1'd0)) begin
+        main_reset_counter <= (main_reset_counter - 1'd1);
     end else begin
-        ic_reset <= 1'd0;
+        main_ic_reset <= 1'd0;
     end
     if (iodelay_rst) begin
-        reset_counter <= 4'd15;
-        ic_reset <= 1'd1;
+        main_reset_counter <= 4'd15;
+        main_ic_reset <= 1'd1;
     end
 end
 
 always @(posedge sys_clk) begin
-    k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= k7ddrphy_dqs_oe_delay_tappeddelayline;
-    k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
-    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip0_value0 <= (k7ddrphy_bitslip0_value0 + 1'd1);
+    main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= main_k7ddrphy_dqs_oe_delay_tappeddelayline;
+    main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
+    if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip0_value0 <= (main_k7ddrphy_bitslip0_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip0_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip0_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip0_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip0_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip1_value0 <= (k7ddrphy_bitslip1_value0 + 1'd1);
+    main_k7ddrphy_bitslip0_r0 <= {main_k7ddrphy_dqspattern_o, main_k7ddrphy_bitslip0_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip1_value0 <= (main_k7ddrphy_bitslip1_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip1_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip1_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip1_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip1_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip2_value0 <= (k7ddrphy_bitslip2_value0 + 1'd1);
+    main_k7ddrphy_bitslip1_r0 <= {main_k7ddrphy_dqspattern_o, main_k7ddrphy_bitslip1_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip2_value0 <= (main_k7ddrphy_bitslip2_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip2_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip2_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip2_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip2_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip3_value0 <= (k7ddrphy_bitslip3_value0 + 1'd1);
+    main_k7ddrphy_bitslip2_r0 <= {main_k7ddrphy_dqspattern_o, main_k7ddrphy_bitslip2_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip3_value0 <= (main_k7ddrphy_bitslip3_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip3_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip3_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip3_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip3_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip0_value1 <= (k7ddrphy_bitslip0_value1 + 1'd1);
+    main_k7ddrphy_bitslip3_r0 <= {main_k7ddrphy_dqspattern_o, main_k7ddrphy_bitslip3_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip0_value1 <= (main_k7ddrphy_bitslip0_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip0_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip0_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip0_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[4], k7ddrphy_dfi_p3_wrdata_mask[0], k7ddrphy_dfi_p2_wrdata_mask[4], k7ddrphy_dfi_p2_wrdata_mask[0], k7ddrphy_dfi_p1_wrdata_mask[4], k7ddrphy_dfi_p1_wrdata_mask[0], k7ddrphy_dfi_p0_wrdata_mask[4], k7ddrphy_dfi_p0_wrdata_mask[0]}, k7ddrphy_bitslip0_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip1_value1 <= (k7ddrphy_bitslip1_value1 + 1'd1);
+    main_k7ddrphy_bitslip0_r1 <= {{main_k7ddrphy_dfi_p3_wrdata_mask[4], main_k7ddrphy_dfi_p3_wrdata_mask[0], main_k7ddrphy_dfi_p2_wrdata_mask[4], main_k7ddrphy_dfi_p2_wrdata_mask[0], main_k7ddrphy_dfi_p1_wrdata_mask[4], main_k7ddrphy_dfi_p1_wrdata_mask[0], main_k7ddrphy_dfi_p0_wrdata_mask[4], main_k7ddrphy_dfi_p0_wrdata_mask[0]}, main_k7ddrphy_bitslip0_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip1_value1 <= (main_k7ddrphy_bitslip1_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip1_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip1_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip1_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[5], k7ddrphy_dfi_p3_wrdata_mask[1], k7ddrphy_dfi_p2_wrdata_mask[5], k7ddrphy_dfi_p2_wrdata_mask[1], k7ddrphy_dfi_p1_wrdata_mask[5], k7ddrphy_dfi_p1_wrdata_mask[1], k7ddrphy_dfi_p0_wrdata_mask[5], k7ddrphy_dfi_p0_wrdata_mask[1]}, k7ddrphy_bitslip1_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip2_value1 <= (k7ddrphy_bitslip2_value1 + 1'd1);
+    main_k7ddrphy_bitslip1_r1 <= {{main_k7ddrphy_dfi_p3_wrdata_mask[5], main_k7ddrphy_dfi_p3_wrdata_mask[1], main_k7ddrphy_dfi_p2_wrdata_mask[5], main_k7ddrphy_dfi_p2_wrdata_mask[1], main_k7ddrphy_dfi_p1_wrdata_mask[5], main_k7ddrphy_dfi_p1_wrdata_mask[1], main_k7ddrphy_dfi_p0_wrdata_mask[5], main_k7ddrphy_dfi_p0_wrdata_mask[1]}, main_k7ddrphy_bitslip1_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip2_value1 <= (main_k7ddrphy_bitslip2_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip2_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip2_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip2_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[6], k7ddrphy_dfi_p3_wrdata_mask[2], k7ddrphy_dfi_p2_wrdata_mask[6], k7ddrphy_dfi_p2_wrdata_mask[2], k7ddrphy_dfi_p1_wrdata_mask[6], k7ddrphy_dfi_p1_wrdata_mask[2], k7ddrphy_dfi_p0_wrdata_mask[6], k7ddrphy_dfi_p0_wrdata_mask[2]}, k7ddrphy_bitslip2_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip3_value1 <= (k7ddrphy_bitslip3_value1 + 1'd1);
+    main_k7ddrphy_bitslip2_r1 <= {{main_k7ddrphy_dfi_p3_wrdata_mask[6], main_k7ddrphy_dfi_p3_wrdata_mask[2], main_k7ddrphy_dfi_p2_wrdata_mask[6], main_k7ddrphy_dfi_p2_wrdata_mask[2], main_k7ddrphy_dfi_p1_wrdata_mask[6], main_k7ddrphy_dfi_p1_wrdata_mask[2], main_k7ddrphy_dfi_p0_wrdata_mask[6], main_k7ddrphy_dfi_p0_wrdata_mask[2]}, main_k7ddrphy_bitslip2_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip3_value1 <= (main_k7ddrphy_bitslip3_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip3_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip3_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip3_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[7], k7ddrphy_dfi_p3_wrdata_mask[3], k7ddrphy_dfi_p2_wrdata_mask[7], k7ddrphy_dfi_p2_wrdata_mask[3], k7ddrphy_dfi_p1_wrdata_mask[7], k7ddrphy_dfi_p1_wrdata_mask[3], k7ddrphy_dfi_p0_wrdata_mask[7], k7ddrphy_dfi_p0_wrdata_mask[3]}, k7ddrphy_bitslip3_r1[15:8]};
-    k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= k7ddrphy_dq_oe_delay_tappeddelayline;
-    k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
-    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip0_value2 <= (k7ddrphy_bitslip0_value2 + 1'd1);
+    main_k7ddrphy_bitslip3_r1 <= {{main_k7ddrphy_dfi_p3_wrdata_mask[7], main_k7ddrphy_dfi_p3_wrdata_mask[3], main_k7ddrphy_dfi_p2_wrdata_mask[7], main_k7ddrphy_dfi_p2_wrdata_mask[3], main_k7ddrphy_dfi_p1_wrdata_mask[7], main_k7ddrphy_dfi_p1_wrdata_mask[3], main_k7ddrphy_dfi_p0_wrdata_mask[7], main_k7ddrphy_dfi_p0_wrdata_mask[3]}, main_k7ddrphy_bitslip3_r1[15:8]};
+    main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= main_k7ddrphy_dq_oe_delay_tappeddelayline;
+    main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
+    if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip0_value2 <= (main_k7ddrphy_bitslip0_value2 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip0_value2 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip0_value2 <= 3'd7;
     end
-    k7ddrphy_bitslip0_r2 <= {{k7ddrphy_dfi_p3_wrdata[32], k7ddrphy_dfi_p3_wrdata[0], k7ddrphy_dfi_p2_wrdata[32], k7ddrphy_dfi_p2_wrdata[0], k7ddrphy_dfi_p1_wrdata[32], k7ddrphy_dfi_p1_wrdata[0], k7ddrphy_dfi_p0_wrdata[32], k7ddrphy_dfi_p0_wrdata[0]}, k7ddrphy_bitslip0_r2[15:8]};
-    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip0_value3 <= (k7ddrphy_bitslip0_value3 + 1'd1);
+    main_k7ddrphy_bitslip0_r2 <= {{main_k7ddrphy_dfi_p3_wrdata[32], main_k7ddrphy_dfi_p3_wrdata[0], main_k7ddrphy_dfi_p2_wrdata[32], main_k7ddrphy_dfi_p2_wrdata[0], main_k7ddrphy_dfi_p1_wrdata[32], main_k7ddrphy_dfi_p1_wrdata[0], main_k7ddrphy_dfi_p0_wrdata[32], main_k7ddrphy_dfi_p0_wrdata[0]}, main_k7ddrphy_bitslip0_r2[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip0_value3 <= (main_k7ddrphy_bitslip0_value3 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip0_value3 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip0_value3 <= 3'd7;
     end
-    k7ddrphy_bitslip0_r3 <= {k7ddrphy_bitslip03, k7ddrphy_bitslip0_r3[15:8]};
-    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip1_value2 <= (k7ddrphy_bitslip1_value2 + 1'd1);
+    main_k7ddrphy_bitslip0_r3 <= {main_k7ddrphy_bitslip03, main_k7ddrphy_bitslip0_r3[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip1_value2 <= (main_k7ddrphy_bitslip1_value2 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip1_value2 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip1_value2 <= 3'd7;
     end
-    k7ddrphy_bitslip1_r2 <= {{k7ddrphy_dfi_p3_wrdata[33], k7ddrphy_dfi_p3_wrdata[1], k7ddrphy_dfi_p2_wrdata[33], k7ddrphy_dfi_p2_wrdata[1], k7ddrphy_dfi_p1_wrdata[33], k7ddrphy_dfi_p1_wrdata[1], k7ddrphy_dfi_p0_wrdata[33], k7ddrphy_dfi_p0_wrdata[1]}, k7ddrphy_bitslip1_r2[15:8]};
-    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip1_value3 <= (k7ddrphy_bitslip1_value3 + 1'd1);
+    main_k7ddrphy_bitslip1_r2 <= {{main_k7ddrphy_dfi_p3_wrdata[33], main_k7ddrphy_dfi_p3_wrdata[1], main_k7ddrphy_dfi_p2_wrdata[33], main_k7ddrphy_dfi_p2_wrdata[1], main_k7ddrphy_dfi_p1_wrdata[33], main_k7ddrphy_dfi_p1_wrdata[1], main_k7ddrphy_dfi_p0_wrdata[33], main_k7ddrphy_dfi_p0_wrdata[1]}, main_k7ddrphy_bitslip1_r2[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip1_value3 <= (main_k7ddrphy_bitslip1_value3 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip1_value3 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip1_value3 <= 3'd7;
     end
-    k7ddrphy_bitslip1_r3 <= {k7ddrphy_bitslip13, k7ddrphy_bitslip1_r3[15:8]};
-    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip2_value2 <= (k7ddrphy_bitslip2_value2 + 1'd1);
+    main_k7ddrphy_bitslip1_r3 <= {main_k7ddrphy_bitslip13, main_k7ddrphy_bitslip1_r3[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip2_value2 <= (main_k7ddrphy_bitslip2_value2 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip2_value2 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip2_value2 <= 3'd7;
     end
-    k7ddrphy_bitslip2_r2 <= {{k7ddrphy_dfi_p3_wrdata[34], k7ddrphy_dfi_p3_wrdata[2], k7ddrphy_dfi_p2_wrdata[34], k7ddrphy_dfi_p2_wrdata[2], k7ddrphy_dfi_p1_wrdata[34], k7ddrphy_dfi_p1_wrdata[2], k7ddrphy_dfi_p0_wrdata[34], k7ddrphy_dfi_p0_wrdata[2]}, k7ddrphy_bitslip2_r2[15:8]};
-    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip2_value3 <= (k7ddrphy_bitslip2_value3 + 1'd1);
+    main_k7ddrphy_bitslip2_r2 <= {{main_k7ddrphy_dfi_p3_wrdata[34], main_k7ddrphy_dfi_p3_wrdata[2], main_k7ddrphy_dfi_p2_wrdata[34], main_k7ddrphy_dfi_p2_wrdata[2], main_k7ddrphy_dfi_p1_wrdata[34], main_k7ddrphy_dfi_p1_wrdata[2], main_k7ddrphy_dfi_p0_wrdata[34], main_k7ddrphy_dfi_p0_wrdata[2]}, main_k7ddrphy_bitslip2_r2[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip2_value3 <= (main_k7ddrphy_bitslip2_value3 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip2_value3 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip2_value3 <= 3'd7;
     end
-    k7ddrphy_bitslip2_r3 <= {k7ddrphy_bitslip23, k7ddrphy_bitslip2_r3[15:8]};
-    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip3_value2 <= (k7ddrphy_bitslip3_value2 + 1'd1);
+    main_k7ddrphy_bitslip2_r3 <= {main_k7ddrphy_bitslip23, main_k7ddrphy_bitslip2_r3[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip3_value2 <= (main_k7ddrphy_bitslip3_value2 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip3_value2 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip3_value2 <= 3'd7;
     end
-    k7ddrphy_bitslip3_r2 <= {{k7ddrphy_dfi_p3_wrdata[35], k7ddrphy_dfi_p3_wrdata[3], k7ddrphy_dfi_p2_wrdata[35], k7ddrphy_dfi_p2_wrdata[3], k7ddrphy_dfi_p1_wrdata[35], k7ddrphy_dfi_p1_wrdata[3], k7ddrphy_dfi_p0_wrdata[35], k7ddrphy_dfi_p0_wrdata[3]}, k7ddrphy_bitslip3_r2[15:8]};
-    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip3_value3 <= (k7ddrphy_bitslip3_value3 + 1'd1);
+    main_k7ddrphy_bitslip3_r2 <= {{main_k7ddrphy_dfi_p3_wrdata[35], main_k7ddrphy_dfi_p3_wrdata[3], main_k7ddrphy_dfi_p2_wrdata[35], main_k7ddrphy_dfi_p2_wrdata[3], main_k7ddrphy_dfi_p1_wrdata[35], main_k7ddrphy_dfi_p1_wrdata[3], main_k7ddrphy_dfi_p0_wrdata[35], main_k7ddrphy_dfi_p0_wrdata[3]}, main_k7ddrphy_bitslip3_r2[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip3_value3 <= (main_k7ddrphy_bitslip3_value3 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip3_value3 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip3_value3 <= 3'd7;
     end
-    k7ddrphy_bitslip3_r3 <= {k7ddrphy_bitslip33, k7ddrphy_bitslip3_r3[15:8]};
-    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip4_value0 <= (k7ddrphy_bitslip4_value0 + 1'd1);
+    main_k7ddrphy_bitslip3_r3 <= {main_k7ddrphy_bitslip33, main_k7ddrphy_bitslip3_r3[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip4_value0 <= (main_k7ddrphy_bitslip4_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip4_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip4_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip4_r0 <= {{k7ddrphy_dfi_p3_wrdata[36], k7ddrphy_dfi_p3_wrdata[4], k7ddrphy_dfi_p2_wrdata[36], k7ddrphy_dfi_p2_wrdata[4], k7ddrphy_dfi_p1_wrdata[36], k7ddrphy_dfi_p1_wrdata[4], k7ddrphy_dfi_p0_wrdata[36], k7ddrphy_dfi_p0_wrdata[4]}, k7ddrphy_bitslip4_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip4_value1 <= (k7ddrphy_bitslip4_value1 + 1'd1);
+    main_k7ddrphy_bitslip4_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[36], main_k7ddrphy_dfi_p3_wrdata[4], main_k7ddrphy_dfi_p2_wrdata[36], main_k7ddrphy_dfi_p2_wrdata[4], main_k7ddrphy_dfi_p1_wrdata[36], main_k7ddrphy_dfi_p1_wrdata[4], main_k7ddrphy_dfi_p0_wrdata[36], main_k7ddrphy_dfi_p0_wrdata[4]}, main_k7ddrphy_bitslip4_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip4_value1 <= (main_k7ddrphy_bitslip4_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip4_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip4_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip4_r1 <= {k7ddrphy_bitslip41, k7ddrphy_bitslip4_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip5_value0 <= (k7ddrphy_bitslip5_value0 + 1'd1);
+    main_k7ddrphy_bitslip4_r1 <= {main_k7ddrphy_bitslip41, main_k7ddrphy_bitslip4_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip5_value0 <= (main_k7ddrphy_bitslip5_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip5_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip5_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip5_r0 <= {{k7ddrphy_dfi_p3_wrdata[37], k7ddrphy_dfi_p3_wrdata[5], k7ddrphy_dfi_p2_wrdata[37], k7ddrphy_dfi_p2_wrdata[5], k7ddrphy_dfi_p1_wrdata[37], k7ddrphy_dfi_p1_wrdata[5], k7ddrphy_dfi_p0_wrdata[37], k7ddrphy_dfi_p0_wrdata[5]}, k7ddrphy_bitslip5_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip5_value1 <= (k7ddrphy_bitslip5_value1 + 1'd1);
+    main_k7ddrphy_bitslip5_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[37], main_k7ddrphy_dfi_p3_wrdata[5], main_k7ddrphy_dfi_p2_wrdata[37], main_k7ddrphy_dfi_p2_wrdata[5], main_k7ddrphy_dfi_p1_wrdata[37], main_k7ddrphy_dfi_p1_wrdata[5], main_k7ddrphy_dfi_p0_wrdata[37], main_k7ddrphy_dfi_p0_wrdata[5]}, main_k7ddrphy_bitslip5_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip5_value1 <= (main_k7ddrphy_bitslip5_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip5_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip5_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip5_r1 <= {k7ddrphy_bitslip51, k7ddrphy_bitslip5_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip6_value0 <= (k7ddrphy_bitslip6_value0 + 1'd1);
+    main_k7ddrphy_bitslip5_r1 <= {main_k7ddrphy_bitslip51, main_k7ddrphy_bitslip5_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip6_value0 <= (main_k7ddrphy_bitslip6_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip6_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip6_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip6_r0 <= {{k7ddrphy_dfi_p3_wrdata[38], k7ddrphy_dfi_p3_wrdata[6], k7ddrphy_dfi_p2_wrdata[38], k7ddrphy_dfi_p2_wrdata[6], k7ddrphy_dfi_p1_wrdata[38], k7ddrphy_dfi_p1_wrdata[6], k7ddrphy_dfi_p0_wrdata[38], k7ddrphy_dfi_p0_wrdata[6]}, k7ddrphy_bitslip6_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip6_value1 <= (k7ddrphy_bitslip6_value1 + 1'd1);
+    main_k7ddrphy_bitslip6_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[38], main_k7ddrphy_dfi_p3_wrdata[6], main_k7ddrphy_dfi_p2_wrdata[38], main_k7ddrphy_dfi_p2_wrdata[6], main_k7ddrphy_dfi_p1_wrdata[38], main_k7ddrphy_dfi_p1_wrdata[6], main_k7ddrphy_dfi_p0_wrdata[38], main_k7ddrphy_dfi_p0_wrdata[6]}, main_k7ddrphy_bitslip6_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip6_value1 <= (main_k7ddrphy_bitslip6_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip6_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip6_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip6_r1 <= {k7ddrphy_bitslip61, k7ddrphy_bitslip6_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip7_value0 <= (k7ddrphy_bitslip7_value0 + 1'd1);
+    main_k7ddrphy_bitslip6_r1 <= {main_k7ddrphy_bitslip61, main_k7ddrphy_bitslip6_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip7_value0 <= (main_k7ddrphy_bitslip7_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip7_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip7_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip7_r0 <= {{k7ddrphy_dfi_p3_wrdata[39], k7ddrphy_dfi_p3_wrdata[7], k7ddrphy_dfi_p2_wrdata[39], k7ddrphy_dfi_p2_wrdata[7], k7ddrphy_dfi_p1_wrdata[39], k7ddrphy_dfi_p1_wrdata[7], k7ddrphy_dfi_p0_wrdata[39], k7ddrphy_dfi_p0_wrdata[7]}, k7ddrphy_bitslip7_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip7_value1 <= (k7ddrphy_bitslip7_value1 + 1'd1);
+    main_k7ddrphy_bitslip7_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[39], main_k7ddrphy_dfi_p3_wrdata[7], main_k7ddrphy_dfi_p2_wrdata[39], main_k7ddrphy_dfi_p2_wrdata[7], main_k7ddrphy_dfi_p1_wrdata[39], main_k7ddrphy_dfi_p1_wrdata[7], main_k7ddrphy_dfi_p0_wrdata[39], main_k7ddrphy_dfi_p0_wrdata[7]}, main_k7ddrphy_bitslip7_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip7_value1 <= (main_k7ddrphy_bitslip7_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip7_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip7_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip7_r1 <= {k7ddrphy_bitslip71, k7ddrphy_bitslip7_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip8_value0 <= (k7ddrphy_bitslip8_value0 + 1'd1);
+    main_k7ddrphy_bitslip7_r1 <= {main_k7ddrphy_bitslip71, main_k7ddrphy_bitslip7_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip8_value0 <= (main_k7ddrphy_bitslip8_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip8_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip8_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip8_r0 <= {{k7ddrphy_dfi_p3_wrdata[40], k7ddrphy_dfi_p3_wrdata[8], k7ddrphy_dfi_p2_wrdata[40], k7ddrphy_dfi_p2_wrdata[8], k7ddrphy_dfi_p1_wrdata[40], k7ddrphy_dfi_p1_wrdata[8], k7ddrphy_dfi_p0_wrdata[40], k7ddrphy_dfi_p0_wrdata[8]}, k7ddrphy_bitslip8_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip8_value1 <= (k7ddrphy_bitslip8_value1 + 1'd1);
+    main_k7ddrphy_bitslip8_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[40], main_k7ddrphy_dfi_p3_wrdata[8], main_k7ddrphy_dfi_p2_wrdata[40], main_k7ddrphy_dfi_p2_wrdata[8], main_k7ddrphy_dfi_p1_wrdata[40], main_k7ddrphy_dfi_p1_wrdata[8], main_k7ddrphy_dfi_p0_wrdata[40], main_k7ddrphy_dfi_p0_wrdata[8]}, main_k7ddrphy_bitslip8_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip8_value1 <= (main_k7ddrphy_bitslip8_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip8_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip8_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip8_r1 <= {k7ddrphy_bitslip81, k7ddrphy_bitslip8_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip9_value0 <= (k7ddrphy_bitslip9_value0 + 1'd1);
+    main_k7ddrphy_bitslip8_r1 <= {main_k7ddrphy_bitslip81, main_k7ddrphy_bitslip8_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip9_value0 <= (main_k7ddrphy_bitslip9_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip9_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip9_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip9_r0 <= {{k7ddrphy_dfi_p3_wrdata[41], k7ddrphy_dfi_p3_wrdata[9], k7ddrphy_dfi_p2_wrdata[41], k7ddrphy_dfi_p2_wrdata[9], k7ddrphy_dfi_p1_wrdata[41], k7ddrphy_dfi_p1_wrdata[9], k7ddrphy_dfi_p0_wrdata[41], k7ddrphy_dfi_p0_wrdata[9]}, k7ddrphy_bitslip9_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip9_value1 <= (k7ddrphy_bitslip9_value1 + 1'd1);
+    main_k7ddrphy_bitslip9_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[41], main_k7ddrphy_dfi_p3_wrdata[9], main_k7ddrphy_dfi_p2_wrdata[41], main_k7ddrphy_dfi_p2_wrdata[9], main_k7ddrphy_dfi_p1_wrdata[41], main_k7ddrphy_dfi_p1_wrdata[9], main_k7ddrphy_dfi_p0_wrdata[41], main_k7ddrphy_dfi_p0_wrdata[9]}, main_k7ddrphy_bitslip9_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip9_value1 <= (main_k7ddrphy_bitslip9_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip9_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip9_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip9_r1 <= {k7ddrphy_bitslip91, k7ddrphy_bitslip9_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip10_value0 <= (k7ddrphy_bitslip10_value0 + 1'd1);
+    main_k7ddrphy_bitslip9_r1 <= {main_k7ddrphy_bitslip91, main_k7ddrphy_bitslip9_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip10_value0 <= (main_k7ddrphy_bitslip10_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip10_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip10_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip10_r0 <= {{k7ddrphy_dfi_p3_wrdata[42], k7ddrphy_dfi_p3_wrdata[10], k7ddrphy_dfi_p2_wrdata[42], k7ddrphy_dfi_p2_wrdata[10], k7ddrphy_dfi_p1_wrdata[42], k7ddrphy_dfi_p1_wrdata[10], k7ddrphy_dfi_p0_wrdata[42], k7ddrphy_dfi_p0_wrdata[10]}, k7ddrphy_bitslip10_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip10_value1 <= (k7ddrphy_bitslip10_value1 + 1'd1);
+    main_k7ddrphy_bitslip10_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[42], main_k7ddrphy_dfi_p3_wrdata[10], main_k7ddrphy_dfi_p2_wrdata[42], main_k7ddrphy_dfi_p2_wrdata[10], main_k7ddrphy_dfi_p1_wrdata[42], main_k7ddrphy_dfi_p1_wrdata[10], main_k7ddrphy_dfi_p0_wrdata[42], main_k7ddrphy_dfi_p0_wrdata[10]}, main_k7ddrphy_bitslip10_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip10_value1 <= (main_k7ddrphy_bitslip10_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip10_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip10_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip10_r1 <= {k7ddrphy_bitslip101, k7ddrphy_bitslip10_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip11_value0 <= (k7ddrphy_bitslip11_value0 + 1'd1);
+    main_k7ddrphy_bitslip10_r1 <= {main_k7ddrphy_bitslip101, main_k7ddrphy_bitslip10_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip11_value0 <= (main_k7ddrphy_bitslip11_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip11_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip11_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip11_r0 <= {{k7ddrphy_dfi_p3_wrdata[43], k7ddrphy_dfi_p3_wrdata[11], k7ddrphy_dfi_p2_wrdata[43], k7ddrphy_dfi_p2_wrdata[11], k7ddrphy_dfi_p1_wrdata[43], k7ddrphy_dfi_p1_wrdata[11], k7ddrphy_dfi_p0_wrdata[43], k7ddrphy_dfi_p0_wrdata[11]}, k7ddrphy_bitslip11_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip11_value1 <= (k7ddrphy_bitslip11_value1 + 1'd1);
+    main_k7ddrphy_bitslip11_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[43], main_k7ddrphy_dfi_p3_wrdata[11], main_k7ddrphy_dfi_p2_wrdata[43], main_k7ddrphy_dfi_p2_wrdata[11], main_k7ddrphy_dfi_p1_wrdata[43], main_k7ddrphy_dfi_p1_wrdata[11], main_k7ddrphy_dfi_p0_wrdata[43], main_k7ddrphy_dfi_p0_wrdata[11]}, main_k7ddrphy_bitslip11_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip11_value1 <= (main_k7ddrphy_bitslip11_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip11_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip11_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip11_r1 <= {k7ddrphy_bitslip111, k7ddrphy_bitslip11_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip12_value0 <= (k7ddrphy_bitslip12_value0 + 1'd1);
+    main_k7ddrphy_bitslip11_r1 <= {main_k7ddrphy_bitslip111, main_k7ddrphy_bitslip11_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip12_value0 <= (main_k7ddrphy_bitslip12_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip12_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip12_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip12_r0 <= {{k7ddrphy_dfi_p3_wrdata[44], k7ddrphy_dfi_p3_wrdata[12], k7ddrphy_dfi_p2_wrdata[44], k7ddrphy_dfi_p2_wrdata[12], k7ddrphy_dfi_p1_wrdata[44], k7ddrphy_dfi_p1_wrdata[12], k7ddrphy_dfi_p0_wrdata[44], k7ddrphy_dfi_p0_wrdata[12]}, k7ddrphy_bitslip12_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip12_value1 <= (k7ddrphy_bitslip12_value1 + 1'd1);
+    main_k7ddrphy_bitslip12_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[44], main_k7ddrphy_dfi_p3_wrdata[12], main_k7ddrphy_dfi_p2_wrdata[44], main_k7ddrphy_dfi_p2_wrdata[12], main_k7ddrphy_dfi_p1_wrdata[44], main_k7ddrphy_dfi_p1_wrdata[12], main_k7ddrphy_dfi_p0_wrdata[44], main_k7ddrphy_dfi_p0_wrdata[12]}, main_k7ddrphy_bitslip12_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip12_value1 <= (main_k7ddrphy_bitslip12_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip12_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip12_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip12_r1 <= {k7ddrphy_bitslip121, k7ddrphy_bitslip12_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip13_value0 <= (k7ddrphy_bitslip13_value0 + 1'd1);
+    main_k7ddrphy_bitslip12_r1 <= {main_k7ddrphy_bitslip121, main_k7ddrphy_bitslip12_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip13_value0 <= (main_k7ddrphy_bitslip13_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip13_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip13_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip13_r0 <= {{k7ddrphy_dfi_p3_wrdata[45], k7ddrphy_dfi_p3_wrdata[13], k7ddrphy_dfi_p2_wrdata[45], k7ddrphy_dfi_p2_wrdata[13], k7ddrphy_dfi_p1_wrdata[45], k7ddrphy_dfi_p1_wrdata[13], k7ddrphy_dfi_p0_wrdata[45], k7ddrphy_dfi_p0_wrdata[13]}, k7ddrphy_bitslip13_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip13_value1 <= (k7ddrphy_bitslip13_value1 + 1'd1);
+    main_k7ddrphy_bitslip13_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[45], main_k7ddrphy_dfi_p3_wrdata[13], main_k7ddrphy_dfi_p2_wrdata[45], main_k7ddrphy_dfi_p2_wrdata[13], main_k7ddrphy_dfi_p1_wrdata[45], main_k7ddrphy_dfi_p1_wrdata[13], main_k7ddrphy_dfi_p0_wrdata[45], main_k7ddrphy_dfi_p0_wrdata[13]}, main_k7ddrphy_bitslip13_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip13_value1 <= (main_k7ddrphy_bitslip13_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip13_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip13_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip13_r1 <= {k7ddrphy_bitslip131, k7ddrphy_bitslip13_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip14_value0 <= (k7ddrphy_bitslip14_value0 + 1'd1);
+    main_k7ddrphy_bitslip13_r1 <= {main_k7ddrphy_bitslip131, main_k7ddrphy_bitslip13_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip14_value0 <= (main_k7ddrphy_bitslip14_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip14_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip14_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip14_r0 <= {{k7ddrphy_dfi_p3_wrdata[46], k7ddrphy_dfi_p3_wrdata[14], k7ddrphy_dfi_p2_wrdata[46], k7ddrphy_dfi_p2_wrdata[14], k7ddrphy_dfi_p1_wrdata[46], k7ddrphy_dfi_p1_wrdata[14], k7ddrphy_dfi_p0_wrdata[46], k7ddrphy_dfi_p0_wrdata[14]}, k7ddrphy_bitslip14_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip14_value1 <= (k7ddrphy_bitslip14_value1 + 1'd1);
+    main_k7ddrphy_bitslip14_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[46], main_k7ddrphy_dfi_p3_wrdata[14], main_k7ddrphy_dfi_p2_wrdata[46], main_k7ddrphy_dfi_p2_wrdata[14], main_k7ddrphy_dfi_p1_wrdata[46], main_k7ddrphy_dfi_p1_wrdata[14], main_k7ddrphy_dfi_p0_wrdata[46], main_k7ddrphy_dfi_p0_wrdata[14]}, main_k7ddrphy_bitslip14_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip14_value1 <= (main_k7ddrphy_bitslip14_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip14_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip14_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip14_r1 <= {k7ddrphy_bitslip141, k7ddrphy_bitslip14_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip15_value0 <= (k7ddrphy_bitslip15_value0 + 1'd1);
+    main_k7ddrphy_bitslip14_r1 <= {main_k7ddrphy_bitslip141, main_k7ddrphy_bitslip14_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip15_value0 <= (main_k7ddrphy_bitslip15_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip15_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip15_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip15_r0 <= {{k7ddrphy_dfi_p3_wrdata[47], k7ddrphy_dfi_p3_wrdata[15], k7ddrphy_dfi_p2_wrdata[47], k7ddrphy_dfi_p2_wrdata[15], k7ddrphy_dfi_p1_wrdata[47], k7ddrphy_dfi_p1_wrdata[15], k7ddrphy_dfi_p0_wrdata[47], k7ddrphy_dfi_p0_wrdata[15]}, k7ddrphy_bitslip15_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip15_value1 <= (k7ddrphy_bitslip15_value1 + 1'd1);
+    main_k7ddrphy_bitslip15_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[47], main_k7ddrphy_dfi_p3_wrdata[15], main_k7ddrphy_dfi_p2_wrdata[47], main_k7ddrphy_dfi_p2_wrdata[15], main_k7ddrphy_dfi_p1_wrdata[47], main_k7ddrphy_dfi_p1_wrdata[15], main_k7ddrphy_dfi_p0_wrdata[47], main_k7ddrphy_dfi_p0_wrdata[15]}, main_k7ddrphy_bitslip15_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip15_value1 <= (main_k7ddrphy_bitslip15_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip15_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip15_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip15_r1 <= {k7ddrphy_bitslip151, k7ddrphy_bitslip15_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip16_value0 <= (k7ddrphy_bitslip16_value0 + 1'd1);
+    main_k7ddrphy_bitslip15_r1 <= {main_k7ddrphy_bitslip151, main_k7ddrphy_bitslip15_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip16_value0 <= (main_k7ddrphy_bitslip16_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip16_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip16_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip16_r0 <= {{k7ddrphy_dfi_p3_wrdata[48], k7ddrphy_dfi_p3_wrdata[16], k7ddrphy_dfi_p2_wrdata[48], k7ddrphy_dfi_p2_wrdata[16], k7ddrphy_dfi_p1_wrdata[48], k7ddrphy_dfi_p1_wrdata[16], k7ddrphy_dfi_p0_wrdata[48], k7ddrphy_dfi_p0_wrdata[16]}, k7ddrphy_bitslip16_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip16_value1 <= (k7ddrphy_bitslip16_value1 + 1'd1);
+    main_k7ddrphy_bitslip16_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[48], main_k7ddrphy_dfi_p3_wrdata[16], main_k7ddrphy_dfi_p2_wrdata[48], main_k7ddrphy_dfi_p2_wrdata[16], main_k7ddrphy_dfi_p1_wrdata[48], main_k7ddrphy_dfi_p1_wrdata[16], main_k7ddrphy_dfi_p0_wrdata[48], main_k7ddrphy_dfi_p0_wrdata[16]}, main_k7ddrphy_bitslip16_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip16_value1 <= (main_k7ddrphy_bitslip16_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip16_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip16_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip16_r1 <= {k7ddrphy_bitslip161, k7ddrphy_bitslip16_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip17_value0 <= (k7ddrphy_bitslip17_value0 + 1'd1);
+    main_k7ddrphy_bitslip16_r1 <= {main_k7ddrphy_bitslip161, main_k7ddrphy_bitslip16_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip17_value0 <= (main_k7ddrphy_bitslip17_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip17_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip17_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip17_r0 <= {{k7ddrphy_dfi_p3_wrdata[49], k7ddrphy_dfi_p3_wrdata[17], k7ddrphy_dfi_p2_wrdata[49], k7ddrphy_dfi_p2_wrdata[17], k7ddrphy_dfi_p1_wrdata[49], k7ddrphy_dfi_p1_wrdata[17], k7ddrphy_dfi_p0_wrdata[49], k7ddrphy_dfi_p0_wrdata[17]}, k7ddrphy_bitslip17_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip17_value1 <= (k7ddrphy_bitslip17_value1 + 1'd1);
+    main_k7ddrphy_bitslip17_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[49], main_k7ddrphy_dfi_p3_wrdata[17], main_k7ddrphy_dfi_p2_wrdata[49], main_k7ddrphy_dfi_p2_wrdata[17], main_k7ddrphy_dfi_p1_wrdata[49], main_k7ddrphy_dfi_p1_wrdata[17], main_k7ddrphy_dfi_p0_wrdata[49], main_k7ddrphy_dfi_p0_wrdata[17]}, main_k7ddrphy_bitslip17_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip17_value1 <= (main_k7ddrphy_bitslip17_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip17_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip17_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip17_r1 <= {k7ddrphy_bitslip171, k7ddrphy_bitslip17_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip18_value0 <= (k7ddrphy_bitslip18_value0 + 1'd1);
+    main_k7ddrphy_bitslip17_r1 <= {main_k7ddrphy_bitslip171, main_k7ddrphy_bitslip17_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip18_value0 <= (main_k7ddrphy_bitslip18_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip18_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip18_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip18_r0 <= {{k7ddrphy_dfi_p3_wrdata[50], k7ddrphy_dfi_p3_wrdata[18], k7ddrphy_dfi_p2_wrdata[50], k7ddrphy_dfi_p2_wrdata[18], k7ddrphy_dfi_p1_wrdata[50], k7ddrphy_dfi_p1_wrdata[18], k7ddrphy_dfi_p0_wrdata[50], k7ddrphy_dfi_p0_wrdata[18]}, k7ddrphy_bitslip18_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip18_value1 <= (k7ddrphy_bitslip18_value1 + 1'd1);
+    main_k7ddrphy_bitslip18_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[50], main_k7ddrphy_dfi_p3_wrdata[18], main_k7ddrphy_dfi_p2_wrdata[50], main_k7ddrphy_dfi_p2_wrdata[18], main_k7ddrphy_dfi_p1_wrdata[50], main_k7ddrphy_dfi_p1_wrdata[18], main_k7ddrphy_dfi_p0_wrdata[50], main_k7ddrphy_dfi_p0_wrdata[18]}, main_k7ddrphy_bitslip18_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip18_value1 <= (main_k7ddrphy_bitslip18_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip18_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip18_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip18_r1 <= {k7ddrphy_bitslip181, k7ddrphy_bitslip18_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip19_value0 <= (k7ddrphy_bitslip19_value0 + 1'd1);
+    main_k7ddrphy_bitslip18_r1 <= {main_k7ddrphy_bitslip181, main_k7ddrphy_bitslip18_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip19_value0 <= (main_k7ddrphy_bitslip19_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip19_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip19_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip19_r0 <= {{k7ddrphy_dfi_p3_wrdata[51], k7ddrphy_dfi_p3_wrdata[19], k7ddrphy_dfi_p2_wrdata[51], k7ddrphy_dfi_p2_wrdata[19], k7ddrphy_dfi_p1_wrdata[51], k7ddrphy_dfi_p1_wrdata[19], k7ddrphy_dfi_p0_wrdata[51], k7ddrphy_dfi_p0_wrdata[19]}, k7ddrphy_bitslip19_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip19_value1 <= (k7ddrphy_bitslip19_value1 + 1'd1);
+    main_k7ddrphy_bitslip19_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[51], main_k7ddrphy_dfi_p3_wrdata[19], main_k7ddrphy_dfi_p2_wrdata[51], main_k7ddrphy_dfi_p2_wrdata[19], main_k7ddrphy_dfi_p1_wrdata[51], main_k7ddrphy_dfi_p1_wrdata[19], main_k7ddrphy_dfi_p0_wrdata[51], main_k7ddrphy_dfi_p0_wrdata[19]}, main_k7ddrphy_bitslip19_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip19_value1 <= (main_k7ddrphy_bitslip19_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip19_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip19_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip19_r1 <= {k7ddrphy_bitslip191, k7ddrphy_bitslip19_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip20_value0 <= (k7ddrphy_bitslip20_value0 + 1'd1);
+    main_k7ddrphy_bitslip19_r1 <= {main_k7ddrphy_bitslip191, main_k7ddrphy_bitslip19_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip20_value0 <= (main_k7ddrphy_bitslip20_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip20_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip20_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip20_r0 <= {{k7ddrphy_dfi_p3_wrdata[52], k7ddrphy_dfi_p3_wrdata[20], k7ddrphy_dfi_p2_wrdata[52], k7ddrphy_dfi_p2_wrdata[20], k7ddrphy_dfi_p1_wrdata[52], k7ddrphy_dfi_p1_wrdata[20], k7ddrphy_dfi_p0_wrdata[52], k7ddrphy_dfi_p0_wrdata[20]}, k7ddrphy_bitslip20_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip20_value1 <= (k7ddrphy_bitslip20_value1 + 1'd1);
+    main_k7ddrphy_bitslip20_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[52], main_k7ddrphy_dfi_p3_wrdata[20], main_k7ddrphy_dfi_p2_wrdata[52], main_k7ddrphy_dfi_p2_wrdata[20], main_k7ddrphy_dfi_p1_wrdata[52], main_k7ddrphy_dfi_p1_wrdata[20], main_k7ddrphy_dfi_p0_wrdata[52], main_k7ddrphy_dfi_p0_wrdata[20]}, main_k7ddrphy_bitslip20_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip20_value1 <= (main_k7ddrphy_bitslip20_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip20_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip20_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip20_r1 <= {k7ddrphy_bitslip201, k7ddrphy_bitslip20_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip21_value0 <= (k7ddrphy_bitslip21_value0 + 1'd1);
+    main_k7ddrphy_bitslip20_r1 <= {main_k7ddrphy_bitslip201, main_k7ddrphy_bitslip20_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip21_value0 <= (main_k7ddrphy_bitslip21_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip21_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip21_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip21_r0 <= {{k7ddrphy_dfi_p3_wrdata[53], k7ddrphy_dfi_p3_wrdata[21], k7ddrphy_dfi_p2_wrdata[53], k7ddrphy_dfi_p2_wrdata[21], k7ddrphy_dfi_p1_wrdata[53], k7ddrphy_dfi_p1_wrdata[21], k7ddrphy_dfi_p0_wrdata[53], k7ddrphy_dfi_p0_wrdata[21]}, k7ddrphy_bitslip21_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip21_value1 <= (k7ddrphy_bitslip21_value1 + 1'd1);
+    main_k7ddrphy_bitslip21_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[53], main_k7ddrphy_dfi_p3_wrdata[21], main_k7ddrphy_dfi_p2_wrdata[53], main_k7ddrphy_dfi_p2_wrdata[21], main_k7ddrphy_dfi_p1_wrdata[53], main_k7ddrphy_dfi_p1_wrdata[21], main_k7ddrphy_dfi_p0_wrdata[53], main_k7ddrphy_dfi_p0_wrdata[21]}, main_k7ddrphy_bitslip21_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip21_value1 <= (main_k7ddrphy_bitslip21_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip21_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip21_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip21_r1 <= {k7ddrphy_bitslip211, k7ddrphy_bitslip21_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip22_value0 <= (k7ddrphy_bitslip22_value0 + 1'd1);
+    main_k7ddrphy_bitslip21_r1 <= {main_k7ddrphy_bitslip211, main_k7ddrphy_bitslip21_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip22_value0 <= (main_k7ddrphy_bitslip22_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip22_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip22_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip22_r0 <= {{k7ddrphy_dfi_p3_wrdata[54], k7ddrphy_dfi_p3_wrdata[22], k7ddrphy_dfi_p2_wrdata[54], k7ddrphy_dfi_p2_wrdata[22], k7ddrphy_dfi_p1_wrdata[54], k7ddrphy_dfi_p1_wrdata[22], k7ddrphy_dfi_p0_wrdata[54], k7ddrphy_dfi_p0_wrdata[22]}, k7ddrphy_bitslip22_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip22_value1 <= (k7ddrphy_bitslip22_value1 + 1'd1);
+    main_k7ddrphy_bitslip22_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[54], main_k7ddrphy_dfi_p3_wrdata[22], main_k7ddrphy_dfi_p2_wrdata[54], main_k7ddrphy_dfi_p2_wrdata[22], main_k7ddrphy_dfi_p1_wrdata[54], main_k7ddrphy_dfi_p1_wrdata[22], main_k7ddrphy_dfi_p0_wrdata[54], main_k7ddrphy_dfi_p0_wrdata[22]}, main_k7ddrphy_bitslip22_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip22_value1 <= (main_k7ddrphy_bitslip22_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip22_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip22_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip22_r1 <= {k7ddrphy_bitslip221, k7ddrphy_bitslip22_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip23_value0 <= (k7ddrphy_bitslip23_value0 + 1'd1);
+    main_k7ddrphy_bitslip22_r1 <= {main_k7ddrphy_bitslip221, main_k7ddrphy_bitslip22_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip23_value0 <= (main_k7ddrphy_bitslip23_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip23_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip23_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip23_r0 <= {{k7ddrphy_dfi_p3_wrdata[55], k7ddrphy_dfi_p3_wrdata[23], k7ddrphy_dfi_p2_wrdata[55], k7ddrphy_dfi_p2_wrdata[23], k7ddrphy_dfi_p1_wrdata[55], k7ddrphy_dfi_p1_wrdata[23], k7ddrphy_dfi_p0_wrdata[55], k7ddrphy_dfi_p0_wrdata[23]}, k7ddrphy_bitslip23_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip23_value1 <= (k7ddrphy_bitslip23_value1 + 1'd1);
+    main_k7ddrphy_bitslip23_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[55], main_k7ddrphy_dfi_p3_wrdata[23], main_k7ddrphy_dfi_p2_wrdata[55], main_k7ddrphy_dfi_p2_wrdata[23], main_k7ddrphy_dfi_p1_wrdata[55], main_k7ddrphy_dfi_p1_wrdata[23], main_k7ddrphy_dfi_p0_wrdata[55], main_k7ddrphy_dfi_p0_wrdata[23]}, main_k7ddrphy_bitslip23_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip23_value1 <= (main_k7ddrphy_bitslip23_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip23_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip23_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip23_r1 <= {k7ddrphy_bitslip231, k7ddrphy_bitslip23_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip24_value0 <= (k7ddrphy_bitslip24_value0 + 1'd1);
+    main_k7ddrphy_bitslip23_r1 <= {main_k7ddrphy_bitslip231, main_k7ddrphy_bitslip23_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip24_value0 <= (main_k7ddrphy_bitslip24_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip24_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip24_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip24_r0 <= {{k7ddrphy_dfi_p3_wrdata[56], k7ddrphy_dfi_p3_wrdata[24], k7ddrphy_dfi_p2_wrdata[56], k7ddrphy_dfi_p2_wrdata[24], k7ddrphy_dfi_p1_wrdata[56], k7ddrphy_dfi_p1_wrdata[24], k7ddrphy_dfi_p0_wrdata[56], k7ddrphy_dfi_p0_wrdata[24]}, k7ddrphy_bitslip24_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip24_value1 <= (k7ddrphy_bitslip24_value1 + 1'd1);
+    main_k7ddrphy_bitslip24_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[56], main_k7ddrphy_dfi_p3_wrdata[24], main_k7ddrphy_dfi_p2_wrdata[56], main_k7ddrphy_dfi_p2_wrdata[24], main_k7ddrphy_dfi_p1_wrdata[56], main_k7ddrphy_dfi_p1_wrdata[24], main_k7ddrphy_dfi_p0_wrdata[56], main_k7ddrphy_dfi_p0_wrdata[24]}, main_k7ddrphy_bitslip24_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip24_value1 <= (main_k7ddrphy_bitslip24_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip24_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip24_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip24_r1 <= {k7ddrphy_bitslip241, k7ddrphy_bitslip24_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip25_value0 <= (k7ddrphy_bitslip25_value0 + 1'd1);
+    main_k7ddrphy_bitslip24_r1 <= {main_k7ddrphy_bitslip241, main_k7ddrphy_bitslip24_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip25_value0 <= (main_k7ddrphy_bitslip25_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip25_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip25_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip25_r0 <= {{k7ddrphy_dfi_p3_wrdata[57], k7ddrphy_dfi_p3_wrdata[25], k7ddrphy_dfi_p2_wrdata[57], k7ddrphy_dfi_p2_wrdata[25], k7ddrphy_dfi_p1_wrdata[57], k7ddrphy_dfi_p1_wrdata[25], k7ddrphy_dfi_p0_wrdata[57], k7ddrphy_dfi_p0_wrdata[25]}, k7ddrphy_bitslip25_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip25_value1 <= (k7ddrphy_bitslip25_value1 + 1'd1);
+    main_k7ddrphy_bitslip25_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[57], main_k7ddrphy_dfi_p3_wrdata[25], main_k7ddrphy_dfi_p2_wrdata[57], main_k7ddrphy_dfi_p2_wrdata[25], main_k7ddrphy_dfi_p1_wrdata[57], main_k7ddrphy_dfi_p1_wrdata[25], main_k7ddrphy_dfi_p0_wrdata[57], main_k7ddrphy_dfi_p0_wrdata[25]}, main_k7ddrphy_bitslip25_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip25_value1 <= (main_k7ddrphy_bitslip25_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip25_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip25_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip25_r1 <= {k7ddrphy_bitslip251, k7ddrphy_bitslip25_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip26_value0 <= (k7ddrphy_bitslip26_value0 + 1'd1);
+    main_k7ddrphy_bitslip25_r1 <= {main_k7ddrphy_bitslip251, main_k7ddrphy_bitslip25_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip26_value0 <= (main_k7ddrphy_bitslip26_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip26_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip26_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip26_r0 <= {{k7ddrphy_dfi_p3_wrdata[58], k7ddrphy_dfi_p3_wrdata[26], k7ddrphy_dfi_p2_wrdata[58], k7ddrphy_dfi_p2_wrdata[26], k7ddrphy_dfi_p1_wrdata[58], k7ddrphy_dfi_p1_wrdata[26], k7ddrphy_dfi_p0_wrdata[58], k7ddrphy_dfi_p0_wrdata[26]}, k7ddrphy_bitslip26_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip26_value1 <= (k7ddrphy_bitslip26_value1 + 1'd1);
+    main_k7ddrphy_bitslip26_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[58], main_k7ddrphy_dfi_p3_wrdata[26], main_k7ddrphy_dfi_p2_wrdata[58], main_k7ddrphy_dfi_p2_wrdata[26], main_k7ddrphy_dfi_p1_wrdata[58], main_k7ddrphy_dfi_p1_wrdata[26], main_k7ddrphy_dfi_p0_wrdata[58], main_k7ddrphy_dfi_p0_wrdata[26]}, main_k7ddrphy_bitslip26_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip26_value1 <= (main_k7ddrphy_bitslip26_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip26_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip26_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip26_r1 <= {k7ddrphy_bitslip261, k7ddrphy_bitslip26_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip27_value0 <= (k7ddrphy_bitslip27_value0 + 1'd1);
+    main_k7ddrphy_bitslip26_r1 <= {main_k7ddrphy_bitslip261, main_k7ddrphy_bitslip26_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip27_value0 <= (main_k7ddrphy_bitslip27_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip27_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip27_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip27_r0 <= {{k7ddrphy_dfi_p3_wrdata[59], k7ddrphy_dfi_p3_wrdata[27], k7ddrphy_dfi_p2_wrdata[59], k7ddrphy_dfi_p2_wrdata[27], k7ddrphy_dfi_p1_wrdata[59], k7ddrphy_dfi_p1_wrdata[27], k7ddrphy_dfi_p0_wrdata[59], k7ddrphy_dfi_p0_wrdata[27]}, k7ddrphy_bitslip27_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip27_value1 <= (k7ddrphy_bitslip27_value1 + 1'd1);
+    main_k7ddrphy_bitslip27_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[59], main_k7ddrphy_dfi_p3_wrdata[27], main_k7ddrphy_dfi_p2_wrdata[59], main_k7ddrphy_dfi_p2_wrdata[27], main_k7ddrphy_dfi_p1_wrdata[59], main_k7ddrphy_dfi_p1_wrdata[27], main_k7ddrphy_dfi_p0_wrdata[59], main_k7ddrphy_dfi_p0_wrdata[27]}, main_k7ddrphy_bitslip27_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip27_value1 <= (main_k7ddrphy_bitslip27_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip27_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip27_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip27_r1 <= {k7ddrphy_bitslip271, k7ddrphy_bitslip27_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip28_value0 <= (k7ddrphy_bitslip28_value0 + 1'd1);
+    main_k7ddrphy_bitslip27_r1 <= {main_k7ddrphy_bitslip271, main_k7ddrphy_bitslip27_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip28_value0 <= (main_k7ddrphy_bitslip28_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip28_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip28_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip28_r0 <= {{k7ddrphy_dfi_p3_wrdata[60], k7ddrphy_dfi_p3_wrdata[28], k7ddrphy_dfi_p2_wrdata[60], k7ddrphy_dfi_p2_wrdata[28], k7ddrphy_dfi_p1_wrdata[60], k7ddrphy_dfi_p1_wrdata[28], k7ddrphy_dfi_p0_wrdata[60], k7ddrphy_dfi_p0_wrdata[28]}, k7ddrphy_bitslip28_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip28_value1 <= (k7ddrphy_bitslip28_value1 + 1'd1);
+    main_k7ddrphy_bitslip28_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[60], main_k7ddrphy_dfi_p3_wrdata[28], main_k7ddrphy_dfi_p2_wrdata[60], main_k7ddrphy_dfi_p2_wrdata[28], main_k7ddrphy_dfi_p1_wrdata[60], main_k7ddrphy_dfi_p1_wrdata[28], main_k7ddrphy_dfi_p0_wrdata[60], main_k7ddrphy_dfi_p0_wrdata[28]}, main_k7ddrphy_bitslip28_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip28_value1 <= (main_k7ddrphy_bitslip28_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip28_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip28_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip28_r1 <= {k7ddrphy_bitslip281, k7ddrphy_bitslip28_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip29_value0 <= (k7ddrphy_bitslip29_value0 + 1'd1);
+    main_k7ddrphy_bitslip28_r1 <= {main_k7ddrphy_bitslip281, main_k7ddrphy_bitslip28_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip29_value0 <= (main_k7ddrphy_bitslip29_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip29_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip29_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip29_r0 <= {{k7ddrphy_dfi_p3_wrdata[61], k7ddrphy_dfi_p3_wrdata[29], k7ddrphy_dfi_p2_wrdata[61], k7ddrphy_dfi_p2_wrdata[29], k7ddrphy_dfi_p1_wrdata[61], k7ddrphy_dfi_p1_wrdata[29], k7ddrphy_dfi_p0_wrdata[61], k7ddrphy_dfi_p0_wrdata[29]}, k7ddrphy_bitslip29_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip29_value1 <= (k7ddrphy_bitslip29_value1 + 1'd1);
+    main_k7ddrphy_bitslip29_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[61], main_k7ddrphy_dfi_p3_wrdata[29], main_k7ddrphy_dfi_p2_wrdata[61], main_k7ddrphy_dfi_p2_wrdata[29], main_k7ddrphy_dfi_p1_wrdata[61], main_k7ddrphy_dfi_p1_wrdata[29], main_k7ddrphy_dfi_p0_wrdata[61], main_k7ddrphy_dfi_p0_wrdata[29]}, main_k7ddrphy_bitslip29_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip29_value1 <= (main_k7ddrphy_bitslip29_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip29_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip29_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip29_r1 <= {k7ddrphy_bitslip291, k7ddrphy_bitslip29_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip30_value0 <= (k7ddrphy_bitslip30_value0 + 1'd1);
+    main_k7ddrphy_bitslip29_r1 <= {main_k7ddrphy_bitslip291, main_k7ddrphy_bitslip29_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip30_value0 <= (main_k7ddrphy_bitslip30_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip30_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip30_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip30_r0 <= {{k7ddrphy_dfi_p3_wrdata[62], k7ddrphy_dfi_p3_wrdata[30], k7ddrphy_dfi_p2_wrdata[62], k7ddrphy_dfi_p2_wrdata[30], k7ddrphy_dfi_p1_wrdata[62], k7ddrphy_dfi_p1_wrdata[30], k7ddrphy_dfi_p0_wrdata[62], k7ddrphy_dfi_p0_wrdata[30]}, k7ddrphy_bitslip30_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip30_value1 <= (k7ddrphy_bitslip30_value1 + 1'd1);
+    main_k7ddrphy_bitslip30_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[62], main_k7ddrphy_dfi_p3_wrdata[30], main_k7ddrphy_dfi_p2_wrdata[62], main_k7ddrphy_dfi_p2_wrdata[30], main_k7ddrphy_dfi_p1_wrdata[62], main_k7ddrphy_dfi_p1_wrdata[30], main_k7ddrphy_dfi_p0_wrdata[62], main_k7ddrphy_dfi_p0_wrdata[30]}, main_k7ddrphy_bitslip30_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip30_value1 <= (main_k7ddrphy_bitslip30_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip30_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip30_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip30_r1 <= {k7ddrphy_bitslip301, k7ddrphy_bitslip30_r1[15:8]};
-    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip31_value0 <= (k7ddrphy_bitslip31_value0 + 1'd1);
+    main_k7ddrphy_bitslip30_r1 <= {main_k7ddrphy_bitslip301, main_k7ddrphy_bitslip30_r1[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip31_value0 <= (main_k7ddrphy_bitslip31_value0 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip31_value0 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip31_value0 <= 3'd7;
     end
-    k7ddrphy_bitslip31_r0 <= {{k7ddrphy_dfi_p3_wrdata[63], k7ddrphy_dfi_p3_wrdata[31], k7ddrphy_dfi_p2_wrdata[63], k7ddrphy_dfi_p2_wrdata[31], k7ddrphy_dfi_p1_wrdata[63], k7ddrphy_dfi_p1_wrdata[31], k7ddrphy_dfi_p0_wrdata[63], k7ddrphy_dfi_p0_wrdata[31]}, k7ddrphy_bitslip31_r0[15:8]};
-    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
-        k7ddrphy_bitslip31_value1 <= (k7ddrphy_bitslip31_value1 + 1'd1);
+    main_k7ddrphy_bitslip31_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[63], main_k7ddrphy_dfi_p3_wrdata[31], main_k7ddrphy_dfi_p2_wrdata[63], main_k7ddrphy_dfi_p2_wrdata[31], main_k7ddrphy_dfi_p1_wrdata[63], main_k7ddrphy_dfi_p1_wrdata[31], main_k7ddrphy_dfi_p0_wrdata[63], main_k7ddrphy_dfi_p0_wrdata[31]}, main_k7ddrphy_bitslip31_r0[15:8]};
+    if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin
+        main_k7ddrphy_bitslip31_value1 <= (main_k7ddrphy_bitslip31_value1 + 1'd1);
     end
-    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
-        k7ddrphy_bitslip31_value1 <= 3'd7;
+    if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin
+        main_k7ddrphy_bitslip31_value1 <= 3'd7;
     end
-    k7ddrphy_bitslip31_r1 <= {k7ddrphy_bitslip311, k7ddrphy_bitslip31_r1[15:8]};
-    k7ddrphy_rddata_en_tappeddelayline0 <= (((k7ddrphy_dfi_p0_rddata_en | k7ddrphy_dfi_p1_rddata_en) | k7ddrphy_dfi_p2_rddata_en) | k7ddrphy_dfi_p3_rddata_en);
-    k7ddrphy_rddata_en_tappeddelayline1 <= k7ddrphy_rddata_en_tappeddelayline0;
-    k7ddrphy_rddata_en_tappeddelayline2 <= k7ddrphy_rddata_en_tappeddelayline1;
-    k7ddrphy_rddata_en_tappeddelayline3 <= k7ddrphy_rddata_en_tappeddelayline2;
-    k7ddrphy_rddata_en_tappeddelayline4 <= k7ddrphy_rddata_en_tappeddelayline3;
-    k7ddrphy_rddata_en_tappeddelayline5 <= k7ddrphy_rddata_en_tappeddelayline4;
-    k7ddrphy_rddata_en_tappeddelayline6 <= k7ddrphy_rddata_en_tappeddelayline5;
-    k7ddrphy_rddata_en_tappeddelayline7 <= k7ddrphy_rddata_en_tappeddelayline6;
-    k7ddrphy_wrdata_en_tappeddelayline0 <= (((k7ddrphy_dfi_p0_wrdata_en | k7ddrphy_dfi_p1_wrdata_en) | k7ddrphy_dfi_p2_wrdata_en) | k7ddrphy_dfi_p3_wrdata_en);
-    k7ddrphy_wrdata_en_tappeddelayline1 <= k7ddrphy_wrdata_en_tappeddelayline0;
-    k7ddrphy_wrdata_en_tappeddelayline2 <= k7ddrphy_wrdata_en_tappeddelayline1;
-    if (litedramcore_csr_dfi_p0_rddata_valid) begin
-        litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata;
+    main_k7ddrphy_bitslip31_r1 <= {main_k7ddrphy_bitslip311, main_k7ddrphy_bitslip31_r1[15:8]};
+    main_k7ddrphy_rddata_en_tappeddelayline0 <= (((main_k7ddrphy_dfi_p0_rddata_en | main_k7ddrphy_dfi_p1_rddata_en) | main_k7ddrphy_dfi_p2_rddata_en) | main_k7ddrphy_dfi_p3_rddata_en);
+    main_k7ddrphy_rddata_en_tappeddelayline1 <= main_k7ddrphy_rddata_en_tappeddelayline0;
+    main_k7ddrphy_rddata_en_tappeddelayline2 <= main_k7ddrphy_rddata_en_tappeddelayline1;
+    main_k7ddrphy_rddata_en_tappeddelayline3 <= main_k7ddrphy_rddata_en_tappeddelayline2;
+    main_k7ddrphy_rddata_en_tappeddelayline4 <= main_k7ddrphy_rddata_en_tappeddelayline3;
+    main_k7ddrphy_rddata_en_tappeddelayline5 <= main_k7ddrphy_rddata_en_tappeddelayline4;
+    main_k7ddrphy_rddata_en_tappeddelayline6 <= main_k7ddrphy_rddata_en_tappeddelayline5;
+    main_k7ddrphy_rddata_en_tappeddelayline7 <= main_k7ddrphy_rddata_en_tappeddelayline6;
+    main_k7ddrphy_wrdata_en_tappeddelayline0 <= (((main_k7ddrphy_dfi_p0_wrdata_en | main_k7ddrphy_dfi_p1_wrdata_en) | main_k7ddrphy_dfi_p2_wrdata_en) | main_k7ddrphy_dfi_p3_wrdata_en);
+    main_k7ddrphy_wrdata_en_tappeddelayline1 <= main_k7ddrphy_wrdata_en_tappeddelayline0;
+    main_k7ddrphy_wrdata_en_tappeddelayline2 <= main_k7ddrphy_wrdata_en_tappeddelayline1;
+    if (main_litedramcore_csr_dfi_p0_rddata_valid) begin
+        main_litedramcore_phaseinjector0_rddata_status <= main_litedramcore_csr_dfi_p0_rddata;
     end
-    if (litedramcore_csr_dfi_p1_rddata_valid) begin
-        litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata;
+    if (main_litedramcore_csr_dfi_p1_rddata_valid) begin
+        main_litedramcore_phaseinjector1_rddata_status <= main_litedramcore_csr_dfi_p1_rddata;
     end
-    if (litedramcore_csr_dfi_p2_rddata_valid) begin
-        litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata;
+    if (main_litedramcore_csr_dfi_p2_rddata_valid) begin
+        main_litedramcore_phaseinjector2_rddata_status <= main_litedramcore_csr_dfi_p2_rddata;
     end
-    if (litedramcore_csr_dfi_p3_rddata_valid) begin
-        litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata;
+    if (main_litedramcore_csr_dfi_p3_rddata_valid) begin
+        main_litedramcore_phaseinjector3_rddata_status <= main_litedramcore_csr_dfi_p3_rddata;
     end
-    if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
-        litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
+    if ((main_litedramcore_timer_wait & (~main_litedramcore_timer_done0))) begin
+        main_litedramcore_timer_count1 <= (main_litedramcore_timer_count1 - 1'd1);
     end else begin
-        litedramcore_timer_count1 <= 10'd781;
+        main_litedramcore_timer_count1 <= 10'd781;
     end
-    litedramcore_postponer_req_o <= 1'd0;
-    if (litedramcore_postponer_req_i) begin
-        litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
-        if ((litedramcore_postponer_count == 1'd0)) begin
-            litedramcore_postponer_count <= 1'd0;
-            litedramcore_postponer_req_o <= 1'd1;
+    main_litedramcore_postponer_req_o <= 1'd0;
+    if (main_litedramcore_postponer_req_i) begin
+        main_litedramcore_postponer_count <= (main_litedramcore_postponer_count - 1'd1);
+        if ((main_litedramcore_postponer_count == 1'd0)) begin
+            main_litedramcore_postponer_count <= 1'd0;
+            main_litedramcore_postponer_req_o <= 1'd1;
         end
     end
-    if (litedramcore_sequencer_start0) begin
-        litedramcore_sequencer_count <= 1'd0;
+    if (main_litedramcore_sequencer_start0) begin
+        main_litedramcore_sequencer_count <= 1'd0;
     end else begin
-        if (litedramcore_sequencer_done1) begin
-            if ((litedramcore_sequencer_count != 1'd0)) begin
-                litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
-            end
-        end
-    end
-    litedramcore_cmd_payload_a <= 1'd0;
-    litedramcore_cmd_payload_ba <= 1'd0;
-    litedramcore_cmd_payload_cas <= 1'd0;
-    litedramcore_cmd_payload_ras <= 1'd0;
-    litedramcore_cmd_payload_we <= 1'd0;
-    litedramcore_sequencer_done1 <= 1'd0;
-    if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
-        litedramcore_cmd_payload_a <= 11'd1024;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd1;
-        litedramcore_cmd_payload_we <= 1'd1;
-    end
-    if ((litedramcore_sequencer_counter == 2'd3)) begin
-        litedramcore_cmd_payload_a <= 11'd1024;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd1;
-        litedramcore_cmd_payload_ras <= 1'd1;
-        litedramcore_cmd_payload_we <= 1'd0;
-    end
-    if ((litedramcore_sequencer_counter == 6'd55)) begin
-        litedramcore_cmd_payload_a <= 1'd0;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd0;
-        litedramcore_cmd_payload_we <= 1'd0;
-        litedramcore_sequencer_done1 <= 1'd1;
-    end
-    if ((litedramcore_sequencer_counter == 6'd55)) begin
-        litedramcore_sequencer_counter <= 1'd0;
+        if (main_litedramcore_sequencer_done1) begin
+            if ((main_litedramcore_sequencer_count != 1'd0)) begin
+                main_litedramcore_sequencer_count <= (main_litedramcore_sequencer_count - 1'd1);
+            end
+        end
+    end
+    main_litedramcore_cmd_payload_a <= 1'd0;
+    main_litedramcore_cmd_payload_ba <= 1'd0;
+    main_litedramcore_cmd_payload_cas <= 1'd0;
+    main_litedramcore_cmd_payload_ras <= 1'd0;
+    main_litedramcore_cmd_payload_we <= 1'd0;
+    main_litedramcore_sequencer_done1 <= 1'd0;
+    if ((main_litedramcore_sequencer_start1 & (main_litedramcore_sequencer_trigger == 1'd0))) begin
+        main_litedramcore_cmd_payload_a <= 11'd1024;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd1;
+        main_litedramcore_cmd_payload_we <= 1'd1;
+    end
+    if ((main_litedramcore_sequencer_trigger == 2'd3)) begin
+        main_litedramcore_cmd_payload_a <= 11'd1024;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd1;
+        main_litedramcore_cmd_payload_ras <= 1'd1;
+        main_litedramcore_cmd_payload_we <= 1'd0;
+    end
+    if ((main_litedramcore_sequencer_trigger == 6'd55)) begin
+        main_litedramcore_cmd_payload_a <= 1'd0;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd0;
+        main_litedramcore_cmd_payload_we <= 1'd0;
+        main_litedramcore_sequencer_done1 <= 1'd1;
+    end
+    if ((main_litedramcore_sequencer_trigger == 6'd55)) begin
+        main_litedramcore_sequencer_trigger <= 1'd0;
     end else begin
-        if ((litedramcore_sequencer_counter != 1'd0)) begin
-            litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
+        if ((main_litedramcore_sequencer_trigger != 1'd0)) begin
+            main_litedramcore_sequencer_trigger <= (main_litedramcore_sequencer_trigger + 1'd1);
         end else begin
-            if (litedramcore_sequencer_start1) begin
-                litedramcore_sequencer_counter <= 1'd1;
+            if (main_litedramcore_sequencer_start1) begin
+                main_litedramcore_sequencer_trigger <= 1'd1;
             end
         end
     end
-    if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
-        litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
+    if ((main_litedramcore_zqcs_timer_wait & (~main_litedramcore_zqcs_timer_done0))) begin
+        main_litedramcore_zqcs_timer_count1 <= (main_litedramcore_zqcs_timer_count1 - 1'd1);
     end else begin
-        litedramcore_zqcs_timer_count1 <= 27'd99999999;
-    end
-    litedramcore_zqcs_executer_done <= 1'd0;
-    if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
-        litedramcore_cmd_payload_a <= 11'd1024;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd1;
-        litedramcore_cmd_payload_we <= 1'd1;
-    end
-    if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
-        litedramcore_cmd_payload_a <= 1'd0;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd0;
-        litedramcore_cmd_payload_we <= 1'd1;
-    end
-    if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
-        litedramcore_cmd_payload_a <= 1'd0;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd0;
-        litedramcore_cmd_payload_we <= 1'd0;
-        litedramcore_zqcs_executer_done <= 1'd1;
-    end
-    if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
-        litedramcore_zqcs_executer_counter <= 1'd0;
+        main_litedramcore_zqcs_timer_count1 <= 27'd99999999;
+    end
+    main_litedramcore_zqcs_executer_done <= 1'd0;
+    if ((main_litedramcore_zqcs_executer_start & (main_litedramcore_zqcs_executer_trigger == 1'd0))) begin
+        main_litedramcore_cmd_payload_a <= 11'd1024;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd1;
+        main_litedramcore_cmd_payload_we <= 1'd1;
+    end
+    if ((main_litedramcore_zqcs_executer_trigger == 2'd3)) begin
+        main_litedramcore_cmd_payload_a <= 1'd0;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd0;
+        main_litedramcore_cmd_payload_we <= 1'd1;
+    end
+    if ((main_litedramcore_zqcs_executer_trigger == 5'd19)) begin
+        main_litedramcore_cmd_payload_a <= 1'd0;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd0;
+        main_litedramcore_cmd_payload_we <= 1'd0;
+        main_litedramcore_zqcs_executer_done <= 1'd1;
+    end
+    if ((main_litedramcore_zqcs_executer_trigger == 5'd19)) begin
+        main_litedramcore_zqcs_executer_trigger <= 1'd0;
     end else begin
-        if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
-            litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
+        if ((main_litedramcore_zqcs_executer_trigger != 1'd0)) begin
+            main_litedramcore_zqcs_executer_trigger <= (main_litedramcore_zqcs_executer_trigger + 1'd1);
         end else begin
-            if (litedramcore_zqcs_executer_start) begin
-                litedramcore_zqcs_executer_counter <= 1'd1;
+            if (main_litedramcore_zqcs_executer_start) begin
+                main_litedramcore_zqcs_executer_trigger <= 1'd1;
             end
         end
     end
-    litedramcore_refresher_state <= litedramcore_refresher_next_state;
-    if (litedramcore_bankmachine0_row_close) begin
-        litedramcore_bankmachine0_row_opened <= 1'd0;
+    builder_refresher_state <= builder_refresher_next_state;
+    if (main_litedramcore_bankmachine0_row_close) begin
+        main_litedramcore_bankmachine0_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine0_row_open) begin
-            litedramcore_bankmachine0_row_opened <= 1'd1;
-            litedramcore_bankmachine0_row <= litedramcore_bankmachine0_source_source_payload_addr[21:7];
+        if (main_litedramcore_bankmachine0_row_open) begin
+            main_litedramcore_bankmachine0_row_opened <= 1'd1;
+            main_litedramcore_bankmachine0_row <= main_litedramcore_bankmachine0_source_source_payload_addr[21:7];
         end
     end
-    if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin
-        litedramcore_bankmachine0_produce <= (litedramcore_bankmachine0_produce + 1'd1);
+    if (((main_litedramcore_bankmachine0_syncfifo0_we & main_litedramcore_bankmachine0_syncfifo0_writable) & (~main_litedramcore_bankmachine0_replace))) begin
+        main_litedramcore_bankmachine0_produce <= (main_litedramcore_bankmachine0_produce + 1'd1);
     end
-    if (litedramcore_bankmachine0_do_read) begin
-        litedramcore_bankmachine0_consume <= (litedramcore_bankmachine0_consume + 1'd1);
+    if (main_litedramcore_bankmachine0_do_read) begin
+        main_litedramcore_bankmachine0_consume <= (main_litedramcore_bankmachine0_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin
-        if ((~litedramcore_bankmachine0_do_read)) begin
-            litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level + 1'd1);
+    if (((main_litedramcore_bankmachine0_syncfifo0_we & main_litedramcore_bankmachine0_syncfifo0_writable) & (~main_litedramcore_bankmachine0_replace))) begin
+        if ((~main_litedramcore_bankmachine0_do_read)) begin
+            main_litedramcore_bankmachine0_level <= (main_litedramcore_bankmachine0_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine0_do_read) begin
-            litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level - 1'd1);
+        if (main_litedramcore_bankmachine0_do_read) begin
+            main_litedramcore_bankmachine0_level <= (main_litedramcore_bankmachine0_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine0_pipe_valid_source_valid <= litedramcore_bankmachine0_pipe_valid_sink_valid;
-        litedramcore_bankmachine0_pipe_valid_source_first <= litedramcore_bankmachine0_pipe_valid_sink_first;
-        litedramcore_bankmachine0_pipe_valid_source_last <= litedramcore_bankmachine0_pipe_valid_sink_last;
-        litedramcore_bankmachine0_pipe_valid_source_payload_we <= litedramcore_bankmachine0_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine0_pipe_valid_source_valid) | main_litedramcore_bankmachine0_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine0_pipe_valid_source_valid <= main_litedramcore_bankmachine0_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine0_pipe_valid_source_first <= main_litedramcore_bankmachine0_pipe_valid_sink_first;
+        main_litedramcore_bankmachine0_pipe_valid_source_last <= main_litedramcore_bankmachine0_pipe_valid_sink_last;
+        main_litedramcore_bankmachine0_pipe_valid_source_payload_we <= main_litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine0_twtpcon_valid) begin
-        litedramcore_bankmachine0_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine0_twtpcon_valid) begin
+        main_litedramcore_bankmachine0_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
-            litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine0_twtpcon_ready)) begin
+            main_litedramcore_bankmachine0_twtpcon_count <= (main_litedramcore_bankmachine0_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine0_trccon_valid) begin
-        litedramcore_bankmachine0_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine0_trccon_valid) begin
+        main_litedramcore_bankmachine0_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine0_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine0_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine0_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine0_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine0_trccon_ready)) begin
-            litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine0_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine0_trccon_ready)) begin
+            main_litedramcore_bankmachine0_trccon_count <= (main_litedramcore_bankmachine0_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine0_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine0_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine0_trascon_valid) begin
-        litedramcore_bankmachine0_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine0_trascon_valid) begin
+        main_litedramcore_bankmachine0_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine0_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine0_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine0_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine0_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine0_trascon_ready)) begin
-            litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine0_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine0_trascon_ready)) begin
+            main_litedramcore_bankmachine0_trascon_count <= (main_litedramcore_bankmachine0_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine0_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine0_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
-    if (litedramcore_bankmachine1_row_close) begin
-        litedramcore_bankmachine1_row_opened <= 1'd0;
+    builder_bankmachine0_state <= builder_bankmachine0_next_state;
+    if (main_litedramcore_bankmachine1_row_close) begin
+        main_litedramcore_bankmachine1_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine1_row_open) begin
-            litedramcore_bankmachine1_row_opened <= 1'd1;
-            litedramcore_bankmachine1_row <= litedramcore_bankmachine1_source_source_payload_addr[21:7];
+        if (main_litedramcore_bankmachine1_row_open) begin
+            main_litedramcore_bankmachine1_row_opened <= 1'd1;
+            main_litedramcore_bankmachine1_row <= main_litedramcore_bankmachine1_source_source_payload_addr[21:7];
         end
     end
-    if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin
-        litedramcore_bankmachine1_produce <= (litedramcore_bankmachine1_produce + 1'd1);
+    if (((main_litedramcore_bankmachine1_syncfifo1_we & main_litedramcore_bankmachine1_syncfifo1_writable) & (~main_litedramcore_bankmachine1_replace))) begin
+        main_litedramcore_bankmachine1_produce <= (main_litedramcore_bankmachine1_produce + 1'd1);
     end
-    if (litedramcore_bankmachine1_do_read) begin
-        litedramcore_bankmachine1_consume <= (litedramcore_bankmachine1_consume + 1'd1);
+    if (main_litedramcore_bankmachine1_do_read) begin
+        main_litedramcore_bankmachine1_consume <= (main_litedramcore_bankmachine1_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin
-        if ((~litedramcore_bankmachine1_do_read)) begin
-            litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level + 1'd1);
+    if (((main_litedramcore_bankmachine1_syncfifo1_we & main_litedramcore_bankmachine1_syncfifo1_writable) & (~main_litedramcore_bankmachine1_replace))) begin
+        if ((~main_litedramcore_bankmachine1_do_read)) begin
+            main_litedramcore_bankmachine1_level <= (main_litedramcore_bankmachine1_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine1_do_read) begin
-            litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level - 1'd1);
+        if (main_litedramcore_bankmachine1_do_read) begin
+            main_litedramcore_bankmachine1_level <= (main_litedramcore_bankmachine1_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine1_pipe_valid_source_valid <= litedramcore_bankmachine1_pipe_valid_sink_valid;
-        litedramcore_bankmachine1_pipe_valid_source_first <= litedramcore_bankmachine1_pipe_valid_sink_first;
-        litedramcore_bankmachine1_pipe_valid_source_last <= litedramcore_bankmachine1_pipe_valid_sink_last;
-        litedramcore_bankmachine1_pipe_valid_source_payload_we <= litedramcore_bankmachine1_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine1_pipe_valid_source_valid) | main_litedramcore_bankmachine1_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine1_pipe_valid_source_valid <= main_litedramcore_bankmachine1_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine1_pipe_valid_source_first <= main_litedramcore_bankmachine1_pipe_valid_sink_first;
+        main_litedramcore_bankmachine1_pipe_valid_source_last <= main_litedramcore_bankmachine1_pipe_valid_sink_last;
+        main_litedramcore_bankmachine1_pipe_valid_source_payload_we <= main_litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine1_twtpcon_valid) begin
-        litedramcore_bankmachine1_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine1_twtpcon_valid) begin
+        main_litedramcore_bankmachine1_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
-            litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine1_twtpcon_ready)) begin
+            main_litedramcore_bankmachine1_twtpcon_count <= (main_litedramcore_bankmachine1_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine1_trccon_valid) begin
-        litedramcore_bankmachine1_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine1_trccon_valid) begin
+        main_litedramcore_bankmachine1_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine1_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine1_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine1_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine1_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine1_trccon_ready)) begin
-            litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine1_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine1_trccon_ready)) begin
+            main_litedramcore_bankmachine1_trccon_count <= (main_litedramcore_bankmachine1_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine1_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine1_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine1_trascon_valid) begin
-        litedramcore_bankmachine1_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine1_trascon_valid) begin
+        main_litedramcore_bankmachine1_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine1_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine1_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine1_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine1_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine1_trascon_ready)) begin
-            litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine1_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine1_trascon_ready)) begin
+            main_litedramcore_bankmachine1_trascon_count <= (main_litedramcore_bankmachine1_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine1_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine1_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
-    if (litedramcore_bankmachine2_row_close) begin
-        litedramcore_bankmachine2_row_opened <= 1'd0;
+    builder_bankmachine1_state <= builder_bankmachine1_next_state;
+    if (main_litedramcore_bankmachine2_row_close) begin
+        main_litedramcore_bankmachine2_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine2_row_open) begin
-            litedramcore_bankmachine2_row_opened <= 1'd1;
-            litedramcore_bankmachine2_row <= litedramcore_bankmachine2_source_source_payload_addr[21:7];
+        if (main_litedramcore_bankmachine2_row_open) begin
+            main_litedramcore_bankmachine2_row_opened <= 1'd1;
+            main_litedramcore_bankmachine2_row <= main_litedramcore_bankmachine2_source_source_payload_addr[21:7];
         end
     end
-    if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin
-        litedramcore_bankmachine2_produce <= (litedramcore_bankmachine2_produce + 1'd1);
+    if (((main_litedramcore_bankmachine2_syncfifo2_we & main_litedramcore_bankmachine2_syncfifo2_writable) & (~main_litedramcore_bankmachine2_replace))) begin
+        main_litedramcore_bankmachine2_produce <= (main_litedramcore_bankmachine2_produce + 1'd1);
     end
-    if (litedramcore_bankmachine2_do_read) begin
-        litedramcore_bankmachine2_consume <= (litedramcore_bankmachine2_consume + 1'd1);
+    if (main_litedramcore_bankmachine2_do_read) begin
+        main_litedramcore_bankmachine2_consume <= (main_litedramcore_bankmachine2_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin
-        if ((~litedramcore_bankmachine2_do_read)) begin
-            litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level + 1'd1);
+    if (((main_litedramcore_bankmachine2_syncfifo2_we & main_litedramcore_bankmachine2_syncfifo2_writable) & (~main_litedramcore_bankmachine2_replace))) begin
+        if ((~main_litedramcore_bankmachine2_do_read)) begin
+            main_litedramcore_bankmachine2_level <= (main_litedramcore_bankmachine2_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine2_do_read) begin
-            litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level - 1'd1);
+        if (main_litedramcore_bankmachine2_do_read) begin
+            main_litedramcore_bankmachine2_level <= (main_litedramcore_bankmachine2_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine2_pipe_valid_source_valid <= litedramcore_bankmachine2_pipe_valid_sink_valid;
-        litedramcore_bankmachine2_pipe_valid_source_first <= litedramcore_bankmachine2_pipe_valid_sink_first;
-        litedramcore_bankmachine2_pipe_valid_source_last <= litedramcore_bankmachine2_pipe_valid_sink_last;
-        litedramcore_bankmachine2_pipe_valid_source_payload_we <= litedramcore_bankmachine2_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine2_pipe_valid_source_valid) | main_litedramcore_bankmachine2_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine2_pipe_valid_source_valid <= main_litedramcore_bankmachine2_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine2_pipe_valid_source_first <= main_litedramcore_bankmachine2_pipe_valid_sink_first;
+        main_litedramcore_bankmachine2_pipe_valid_source_last <= main_litedramcore_bankmachine2_pipe_valid_sink_last;
+        main_litedramcore_bankmachine2_pipe_valid_source_payload_we <= main_litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine2_twtpcon_valid) begin
-        litedramcore_bankmachine2_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine2_twtpcon_valid) begin
+        main_litedramcore_bankmachine2_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
-            litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine2_twtpcon_ready)) begin
+            main_litedramcore_bankmachine2_twtpcon_count <= (main_litedramcore_bankmachine2_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine2_trccon_valid) begin
-        litedramcore_bankmachine2_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine2_trccon_valid) begin
+        main_litedramcore_bankmachine2_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine2_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine2_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine2_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine2_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine2_trccon_ready)) begin
-            litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine2_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine2_trccon_ready)) begin
+            main_litedramcore_bankmachine2_trccon_count <= (main_litedramcore_bankmachine2_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine2_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine2_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine2_trascon_valid) begin
-        litedramcore_bankmachine2_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine2_trascon_valid) begin
+        main_litedramcore_bankmachine2_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine2_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine2_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine2_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine2_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine2_trascon_ready)) begin
-            litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine2_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine2_trascon_ready)) begin
+            main_litedramcore_bankmachine2_trascon_count <= (main_litedramcore_bankmachine2_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine2_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine2_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
-    if (litedramcore_bankmachine3_row_close) begin
-        litedramcore_bankmachine3_row_opened <= 1'd0;
+    builder_bankmachine2_state <= builder_bankmachine2_next_state;
+    if (main_litedramcore_bankmachine3_row_close) begin
+        main_litedramcore_bankmachine3_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine3_row_open) begin
-            litedramcore_bankmachine3_row_opened <= 1'd1;
-            litedramcore_bankmachine3_row <= litedramcore_bankmachine3_source_source_payload_addr[21:7];
+        if (main_litedramcore_bankmachine3_row_open) begin
+            main_litedramcore_bankmachine3_row_opened <= 1'd1;
+            main_litedramcore_bankmachine3_row <= main_litedramcore_bankmachine3_source_source_payload_addr[21:7];
         end
     end
-    if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin
-        litedramcore_bankmachine3_produce <= (litedramcore_bankmachine3_produce + 1'd1);
+    if (((main_litedramcore_bankmachine3_syncfifo3_we & main_litedramcore_bankmachine3_syncfifo3_writable) & (~main_litedramcore_bankmachine3_replace))) begin
+        main_litedramcore_bankmachine3_produce <= (main_litedramcore_bankmachine3_produce + 1'd1);
     end
-    if (litedramcore_bankmachine3_do_read) begin
-        litedramcore_bankmachine3_consume <= (litedramcore_bankmachine3_consume + 1'd1);
+    if (main_litedramcore_bankmachine3_do_read) begin
+        main_litedramcore_bankmachine3_consume <= (main_litedramcore_bankmachine3_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin
-        if ((~litedramcore_bankmachine3_do_read)) begin
-            litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level + 1'd1);
+    if (((main_litedramcore_bankmachine3_syncfifo3_we & main_litedramcore_bankmachine3_syncfifo3_writable) & (~main_litedramcore_bankmachine3_replace))) begin
+        if ((~main_litedramcore_bankmachine3_do_read)) begin
+            main_litedramcore_bankmachine3_level <= (main_litedramcore_bankmachine3_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine3_do_read) begin
-            litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level - 1'd1);
+        if (main_litedramcore_bankmachine3_do_read) begin
+            main_litedramcore_bankmachine3_level <= (main_litedramcore_bankmachine3_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine3_pipe_valid_source_valid <= litedramcore_bankmachine3_pipe_valid_sink_valid;
-        litedramcore_bankmachine3_pipe_valid_source_first <= litedramcore_bankmachine3_pipe_valid_sink_first;
-        litedramcore_bankmachine3_pipe_valid_source_last <= litedramcore_bankmachine3_pipe_valid_sink_last;
-        litedramcore_bankmachine3_pipe_valid_source_payload_we <= litedramcore_bankmachine3_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine3_pipe_valid_source_valid) | main_litedramcore_bankmachine3_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine3_pipe_valid_source_valid <= main_litedramcore_bankmachine3_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine3_pipe_valid_source_first <= main_litedramcore_bankmachine3_pipe_valid_sink_first;
+        main_litedramcore_bankmachine3_pipe_valid_source_last <= main_litedramcore_bankmachine3_pipe_valid_sink_last;
+        main_litedramcore_bankmachine3_pipe_valid_source_payload_we <= main_litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine3_twtpcon_valid) begin
-        litedramcore_bankmachine3_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine3_twtpcon_valid) begin
+        main_litedramcore_bankmachine3_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
-            litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine3_twtpcon_ready)) begin
+            main_litedramcore_bankmachine3_twtpcon_count <= (main_litedramcore_bankmachine3_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine3_trccon_valid) begin
-        litedramcore_bankmachine3_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine3_trccon_valid) begin
+        main_litedramcore_bankmachine3_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine3_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine3_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine3_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine3_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine3_trccon_ready)) begin
-            litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine3_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine3_trccon_ready)) begin
+            main_litedramcore_bankmachine3_trccon_count <= (main_litedramcore_bankmachine3_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine3_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine3_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine3_trascon_valid) begin
-        litedramcore_bankmachine3_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine3_trascon_valid) begin
+        main_litedramcore_bankmachine3_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine3_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine3_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine3_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine3_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine3_trascon_ready)) begin
-            litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine3_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine3_trascon_ready)) begin
+            main_litedramcore_bankmachine3_trascon_count <= (main_litedramcore_bankmachine3_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine3_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine3_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
-    if (litedramcore_bankmachine4_row_close) begin
-        litedramcore_bankmachine4_row_opened <= 1'd0;
+    builder_bankmachine3_state <= builder_bankmachine3_next_state;
+    if (main_litedramcore_bankmachine4_row_close) begin
+        main_litedramcore_bankmachine4_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine4_row_open) begin
-            litedramcore_bankmachine4_row_opened <= 1'd1;
-            litedramcore_bankmachine4_row <= litedramcore_bankmachine4_source_source_payload_addr[21:7];
+        if (main_litedramcore_bankmachine4_row_open) begin
+            main_litedramcore_bankmachine4_row_opened <= 1'd1;
+            main_litedramcore_bankmachine4_row <= main_litedramcore_bankmachine4_source_source_payload_addr[21:7];
         end
     end
-    if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin
-        litedramcore_bankmachine4_produce <= (litedramcore_bankmachine4_produce + 1'd1);
+    if (((main_litedramcore_bankmachine4_syncfifo4_we & main_litedramcore_bankmachine4_syncfifo4_writable) & (~main_litedramcore_bankmachine4_replace))) begin
+        main_litedramcore_bankmachine4_produce <= (main_litedramcore_bankmachine4_produce + 1'd1);
     end
-    if (litedramcore_bankmachine4_do_read) begin
-        litedramcore_bankmachine4_consume <= (litedramcore_bankmachine4_consume + 1'd1);
+    if (main_litedramcore_bankmachine4_do_read) begin
+        main_litedramcore_bankmachine4_consume <= (main_litedramcore_bankmachine4_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin
-        if ((~litedramcore_bankmachine4_do_read)) begin
-            litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level + 1'd1);
+    if (((main_litedramcore_bankmachine4_syncfifo4_we & main_litedramcore_bankmachine4_syncfifo4_writable) & (~main_litedramcore_bankmachine4_replace))) begin
+        if ((~main_litedramcore_bankmachine4_do_read)) begin
+            main_litedramcore_bankmachine4_level <= (main_litedramcore_bankmachine4_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine4_do_read) begin
-            litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level - 1'd1);
+        if (main_litedramcore_bankmachine4_do_read) begin
+            main_litedramcore_bankmachine4_level <= (main_litedramcore_bankmachine4_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine4_pipe_valid_source_valid <= litedramcore_bankmachine4_pipe_valid_sink_valid;
-        litedramcore_bankmachine4_pipe_valid_source_first <= litedramcore_bankmachine4_pipe_valid_sink_first;
-        litedramcore_bankmachine4_pipe_valid_source_last <= litedramcore_bankmachine4_pipe_valid_sink_last;
-        litedramcore_bankmachine4_pipe_valid_source_payload_we <= litedramcore_bankmachine4_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine4_pipe_valid_source_valid) | main_litedramcore_bankmachine4_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine4_pipe_valid_source_valid <= main_litedramcore_bankmachine4_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine4_pipe_valid_source_first <= main_litedramcore_bankmachine4_pipe_valid_sink_first;
+        main_litedramcore_bankmachine4_pipe_valid_source_last <= main_litedramcore_bankmachine4_pipe_valid_sink_last;
+        main_litedramcore_bankmachine4_pipe_valid_source_payload_we <= main_litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine4_twtpcon_valid) begin
-        litedramcore_bankmachine4_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine4_twtpcon_valid) begin
+        main_litedramcore_bankmachine4_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
-            litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine4_twtpcon_ready)) begin
+            main_litedramcore_bankmachine4_twtpcon_count <= (main_litedramcore_bankmachine4_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine4_trccon_valid) begin
-        litedramcore_bankmachine4_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine4_trccon_valid) begin
+        main_litedramcore_bankmachine4_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine4_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine4_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine4_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine4_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine4_trccon_ready)) begin
-            litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine4_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine4_trccon_ready)) begin
+            main_litedramcore_bankmachine4_trccon_count <= (main_litedramcore_bankmachine4_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine4_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine4_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine4_trascon_valid) begin
-        litedramcore_bankmachine4_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine4_trascon_valid) begin
+        main_litedramcore_bankmachine4_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine4_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine4_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine4_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine4_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine4_trascon_ready)) begin
-            litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine4_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine4_trascon_ready)) begin
+            main_litedramcore_bankmachine4_trascon_count <= (main_litedramcore_bankmachine4_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine4_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine4_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
-    if (litedramcore_bankmachine5_row_close) begin
-        litedramcore_bankmachine5_row_opened <= 1'd0;
+    builder_bankmachine4_state <= builder_bankmachine4_next_state;
+    if (main_litedramcore_bankmachine5_row_close) begin
+        main_litedramcore_bankmachine5_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine5_row_open) begin
-            litedramcore_bankmachine5_row_opened <= 1'd1;
-            litedramcore_bankmachine5_row <= litedramcore_bankmachine5_source_source_payload_addr[21:7];
+        if (main_litedramcore_bankmachine5_row_open) begin
+            main_litedramcore_bankmachine5_row_opened <= 1'd1;
+            main_litedramcore_bankmachine5_row <= main_litedramcore_bankmachine5_source_source_payload_addr[21:7];
         end
     end
-    if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin
-        litedramcore_bankmachine5_produce <= (litedramcore_bankmachine5_produce + 1'd1);
+    if (((main_litedramcore_bankmachine5_syncfifo5_we & main_litedramcore_bankmachine5_syncfifo5_writable) & (~main_litedramcore_bankmachine5_replace))) begin
+        main_litedramcore_bankmachine5_produce <= (main_litedramcore_bankmachine5_produce + 1'd1);
     end
-    if (litedramcore_bankmachine5_do_read) begin
-        litedramcore_bankmachine5_consume <= (litedramcore_bankmachine5_consume + 1'd1);
+    if (main_litedramcore_bankmachine5_do_read) begin
+        main_litedramcore_bankmachine5_consume <= (main_litedramcore_bankmachine5_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin
-        if ((~litedramcore_bankmachine5_do_read)) begin
-            litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level + 1'd1);
+    if (((main_litedramcore_bankmachine5_syncfifo5_we & main_litedramcore_bankmachine5_syncfifo5_writable) & (~main_litedramcore_bankmachine5_replace))) begin
+        if ((~main_litedramcore_bankmachine5_do_read)) begin
+            main_litedramcore_bankmachine5_level <= (main_litedramcore_bankmachine5_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine5_do_read) begin
-            litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level - 1'd1);
+        if (main_litedramcore_bankmachine5_do_read) begin
+            main_litedramcore_bankmachine5_level <= (main_litedramcore_bankmachine5_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine5_pipe_valid_source_valid <= litedramcore_bankmachine5_pipe_valid_sink_valid;
-        litedramcore_bankmachine5_pipe_valid_source_first <= litedramcore_bankmachine5_pipe_valid_sink_first;
-        litedramcore_bankmachine5_pipe_valid_source_last <= litedramcore_bankmachine5_pipe_valid_sink_last;
-        litedramcore_bankmachine5_pipe_valid_source_payload_we <= litedramcore_bankmachine5_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine5_pipe_valid_source_valid) | main_litedramcore_bankmachine5_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine5_pipe_valid_source_valid <= main_litedramcore_bankmachine5_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine5_pipe_valid_source_first <= main_litedramcore_bankmachine5_pipe_valid_sink_first;
+        main_litedramcore_bankmachine5_pipe_valid_source_last <= main_litedramcore_bankmachine5_pipe_valid_sink_last;
+        main_litedramcore_bankmachine5_pipe_valid_source_payload_we <= main_litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine5_twtpcon_valid) begin
-        litedramcore_bankmachine5_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine5_twtpcon_valid) begin
+        main_litedramcore_bankmachine5_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
-            litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine5_twtpcon_ready)) begin
+            main_litedramcore_bankmachine5_twtpcon_count <= (main_litedramcore_bankmachine5_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine5_trccon_valid) begin
-        litedramcore_bankmachine5_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine5_trccon_valid) begin
+        main_litedramcore_bankmachine5_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine5_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine5_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine5_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine5_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine5_trccon_ready)) begin
-            litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine5_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine5_trccon_ready)) begin
+            main_litedramcore_bankmachine5_trccon_count <= (main_litedramcore_bankmachine5_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine5_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine5_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine5_trascon_valid) begin
-        litedramcore_bankmachine5_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine5_trascon_valid) begin
+        main_litedramcore_bankmachine5_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine5_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine5_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine5_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine5_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine5_trascon_ready)) begin
-            litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine5_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine5_trascon_ready)) begin
+            main_litedramcore_bankmachine5_trascon_count <= (main_litedramcore_bankmachine5_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine5_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine5_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
-    if (litedramcore_bankmachine6_row_close) begin
-        litedramcore_bankmachine6_row_opened <= 1'd0;
+    builder_bankmachine5_state <= builder_bankmachine5_next_state;
+    if (main_litedramcore_bankmachine6_row_close) begin
+        main_litedramcore_bankmachine6_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine6_row_open) begin
-            litedramcore_bankmachine6_row_opened <= 1'd1;
-            litedramcore_bankmachine6_row <= litedramcore_bankmachine6_source_source_payload_addr[21:7];
+        if (main_litedramcore_bankmachine6_row_open) begin
+            main_litedramcore_bankmachine6_row_opened <= 1'd1;
+            main_litedramcore_bankmachine6_row <= main_litedramcore_bankmachine6_source_source_payload_addr[21:7];
         end
     end
-    if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin
-        litedramcore_bankmachine6_produce <= (litedramcore_bankmachine6_produce + 1'd1);
+    if (((main_litedramcore_bankmachine6_syncfifo6_we & main_litedramcore_bankmachine6_syncfifo6_writable) & (~main_litedramcore_bankmachine6_replace))) begin
+        main_litedramcore_bankmachine6_produce <= (main_litedramcore_bankmachine6_produce + 1'd1);
     end
-    if (litedramcore_bankmachine6_do_read) begin
-        litedramcore_bankmachine6_consume <= (litedramcore_bankmachine6_consume + 1'd1);
+    if (main_litedramcore_bankmachine6_do_read) begin
+        main_litedramcore_bankmachine6_consume <= (main_litedramcore_bankmachine6_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin
-        if ((~litedramcore_bankmachine6_do_read)) begin
-            litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level + 1'd1);
+    if (((main_litedramcore_bankmachine6_syncfifo6_we & main_litedramcore_bankmachine6_syncfifo6_writable) & (~main_litedramcore_bankmachine6_replace))) begin
+        if ((~main_litedramcore_bankmachine6_do_read)) begin
+            main_litedramcore_bankmachine6_level <= (main_litedramcore_bankmachine6_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine6_do_read) begin
-            litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level - 1'd1);
+        if (main_litedramcore_bankmachine6_do_read) begin
+            main_litedramcore_bankmachine6_level <= (main_litedramcore_bankmachine6_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine6_pipe_valid_source_valid <= litedramcore_bankmachine6_pipe_valid_sink_valid;
-        litedramcore_bankmachine6_pipe_valid_source_first <= litedramcore_bankmachine6_pipe_valid_sink_first;
-        litedramcore_bankmachine6_pipe_valid_source_last <= litedramcore_bankmachine6_pipe_valid_sink_last;
-        litedramcore_bankmachine6_pipe_valid_source_payload_we <= litedramcore_bankmachine6_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine6_pipe_valid_source_valid) | main_litedramcore_bankmachine6_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine6_pipe_valid_source_valid <= main_litedramcore_bankmachine6_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine6_pipe_valid_source_first <= main_litedramcore_bankmachine6_pipe_valid_sink_first;
+        main_litedramcore_bankmachine6_pipe_valid_source_last <= main_litedramcore_bankmachine6_pipe_valid_sink_last;
+        main_litedramcore_bankmachine6_pipe_valid_source_payload_we <= main_litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine6_twtpcon_valid) begin
-        litedramcore_bankmachine6_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine6_twtpcon_valid) begin
+        main_litedramcore_bankmachine6_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
-            litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine6_twtpcon_ready)) begin
+            main_litedramcore_bankmachine6_twtpcon_count <= (main_litedramcore_bankmachine6_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine6_trccon_valid) begin
-        litedramcore_bankmachine6_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine6_trccon_valid) begin
+        main_litedramcore_bankmachine6_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine6_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine6_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine6_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine6_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine6_trccon_ready)) begin
-            litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine6_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine6_trccon_ready)) begin
+            main_litedramcore_bankmachine6_trccon_count <= (main_litedramcore_bankmachine6_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine6_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine6_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine6_trascon_valid) begin
-        litedramcore_bankmachine6_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine6_trascon_valid) begin
+        main_litedramcore_bankmachine6_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine6_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine6_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine6_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine6_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine6_trascon_ready)) begin
-            litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine6_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine6_trascon_ready)) begin
+            main_litedramcore_bankmachine6_trascon_count <= (main_litedramcore_bankmachine6_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine6_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine6_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
-    if (litedramcore_bankmachine7_row_close) begin
-        litedramcore_bankmachine7_row_opened <= 1'd0;
+    builder_bankmachine6_state <= builder_bankmachine6_next_state;
+    if (main_litedramcore_bankmachine7_row_close) begin
+        main_litedramcore_bankmachine7_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine7_row_open) begin
-            litedramcore_bankmachine7_row_opened <= 1'd1;
-            litedramcore_bankmachine7_row <= litedramcore_bankmachine7_source_source_payload_addr[21:7];
+        if (main_litedramcore_bankmachine7_row_open) begin
+            main_litedramcore_bankmachine7_row_opened <= 1'd1;
+            main_litedramcore_bankmachine7_row <= main_litedramcore_bankmachine7_source_source_payload_addr[21:7];
         end
     end
-    if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin
-        litedramcore_bankmachine7_produce <= (litedramcore_bankmachine7_produce + 1'd1);
+    if (((main_litedramcore_bankmachine7_syncfifo7_we & main_litedramcore_bankmachine7_syncfifo7_writable) & (~main_litedramcore_bankmachine7_replace))) begin
+        main_litedramcore_bankmachine7_produce <= (main_litedramcore_bankmachine7_produce + 1'd1);
     end
-    if (litedramcore_bankmachine7_do_read) begin
-        litedramcore_bankmachine7_consume <= (litedramcore_bankmachine7_consume + 1'd1);
+    if (main_litedramcore_bankmachine7_do_read) begin
+        main_litedramcore_bankmachine7_consume <= (main_litedramcore_bankmachine7_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin
-        if ((~litedramcore_bankmachine7_do_read)) begin
-            litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level + 1'd1);
+    if (((main_litedramcore_bankmachine7_syncfifo7_we & main_litedramcore_bankmachine7_syncfifo7_writable) & (~main_litedramcore_bankmachine7_replace))) begin
+        if ((~main_litedramcore_bankmachine7_do_read)) begin
+            main_litedramcore_bankmachine7_level <= (main_litedramcore_bankmachine7_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine7_do_read) begin
-            litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level - 1'd1);
+        if (main_litedramcore_bankmachine7_do_read) begin
+            main_litedramcore_bankmachine7_level <= (main_litedramcore_bankmachine7_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine7_pipe_valid_source_valid <= litedramcore_bankmachine7_pipe_valid_sink_valid;
-        litedramcore_bankmachine7_pipe_valid_source_first <= litedramcore_bankmachine7_pipe_valid_sink_first;
-        litedramcore_bankmachine7_pipe_valid_source_last <= litedramcore_bankmachine7_pipe_valid_sink_last;
-        litedramcore_bankmachine7_pipe_valid_source_payload_we <= litedramcore_bankmachine7_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine7_pipe_valid_source_valid) | main_litedramcore_bankmachine7_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine7_pipe_valid_source_valid <= main_litedramcore_bankmachine7_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine7_pipe_valid_source_first <= main_litedramcore_bankmachine7_pipe_valid_sink_first;
+        main_litedramcore_bankmachine7_pipe_valid_source_last <= main_litedramcore_bankmachine7_pipe_valid_sink_last;
+        main_litedramcore_bankmachine7_pipe_valid_source_payload_we <= main_litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine7_twtpcon_valid) begin
-        litedramcore_bankmachine7_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine7_twtpcon_valid) begin
+        main_litedramcore_bankmachine7_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
-            litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine7_twtpcon_ready)) begin
+            main_litedramcore_bankmachine7_twtpcon_count <= (main_litedramcore_bankmachine7_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine7_trccon_valid) begin
-        litedramcore_bankmachine7_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine7_trccon_valid) begin
+        main_litedramcore_bankmachine7_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine7_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine7_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine7_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine7_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine7_trccon_ready)) begin
-            litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine7_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine7_trccon_ready)) begin
+            main_litedramcore_bankmachine7_trccon_count <= (main_litedramcore_bankmachine7_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine7_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine7_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine7_trascon_valid) begin
-        litedramcore_bankmachine7_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine7_trascon_valid) begin
+        main_litedramcore_bankmachine7_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine7_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine7_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine7_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine7_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine7_trascon_ready)) begin
-            litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine7_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine7_trascon_ready)) begin
+            main_litedramcore_bankmachine7_trascon_count <= (main_litedramcore_bankmachine7_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine7_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine7_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
-    if ((~litedramcore_en0)) begin
-        litedramcore_time0 <= 5'd31;
+    builder_bankmachine7_state <= builder_bankmachine7_next_state;
+    if ((~main_litedramcore_en0)) begin
+        main_litedramcore_time0 <= 5'd31;
     end else begin
-        if ((~litedramcore_max_time0)) begin
-            litedramcore_time0 <= (litedramcore_time0 - 1'd1);
+        if ((~main_litedramcore_max_time0)) begin
+            main_litedramcore_time0 <= (main_litedramcore_time0 - 1'd1);
         end
     end
-    if ((~litedramcore_en1)) begin
-        litedramcore_time1 <= 4'd15;
+    if ((~main_litedramcore_en1)) begin
+        main_litedramcore_time1 <= 4'd15;
     end else begin
-        if ((~litedramcore_max_time1)) begin
-            litedramcore_time1 <= (litedramcore_time1 - 1'd1);
+        if ((~main_litedramcore_max_time1)) begin
+            main_litedramcore_time1 <= (main_litedramcore_time1 - 1'd1);
         end
     end
-    if (litedramcore_choose_cmd_ce) begin
-        case (litedramcore_choose_cmd_grant)
+    if (main_litedramcore_choose_cmd_ce) begin
+        case (main_litedramcore_choose_cmd_grant)
             1'd0: begin
-                if (litedramcore_choose_cmd_request[1]) begin
-                    litedramcore_choose_cmd_grant <= 1'd1;
+                if (main_litedramcore_choose_cmd_request[1]) begin
+                    main_litedramcore_choose_cmd_grant <= 1'd1;
                 end else begin
-                    if (litedramcore_choose_cmd_request[2]) begin
-                        litedramcore_choose_cmd_grant <= 2'd2;
+                    if (main_litedramcore_choose_cmd_request[2]) begin
+                        main_litedramcore_choose_cmd_grant <= 2'd2;
                     end else begin
-                        if (litedramcore_choose_cmd_request[3]) begin
-                            litedramcore_choose_cmd_grant <= 2'd3;
+                        if (main_litedramcore_choose_cmd_request[3]) begin
+                            main_litedramcore_choose_cmd_grant <= 2'd3;
                         end else begin
-                            if (litedramcore_choose_cmd_request[4]) begin
-                                litedramcore_choose_cmd_grant <= 3'd4;
+                            if (main_litedramcore_choose_cmd_request[4]) begin
+                                main_litedramcore_choose_cmd_grant <= 3'd4;
                             end else begin
-                                if (litedramcore_choose_cmd_request[5]) begin
-                                    litedramcore_choose_cmd_grant <= 3'd5;
+                                if (main_litedramcore_choose_cmd_request[5]) begin
+                                    main_litedramcore_choose_cmd_grant <= 3'd5;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[6]) begin
-                                        litedramcore_choose_cmd_grant <= 3'd6;
+                                    if (main_litedramcore_choose_cmd_request[6]) begin
+                                        main_litedramcore_choose_cmd_grant <= 3'd6;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[7]) begin
-                                            litedramcore_choose_cmd_grant <= 3'd7;
+                                        if (main_litedramcore_choose_cmd_request[7]) begin
+                                            main_litedramcore_choose_cmd_grant <= 3'd7;
                                         end
                                     end
                                 end
@@ -14958,26 +15546,26 @@ always @(posedge sys_clk) begin
                 end
             end
             1'd1: begin
-                if (litedramcore_choose_cmd_request[2]) begin
-                    litedramcore_choose_cmd_grant <= 2'd2;
+                if (main_litedramcore_choose_cmd_request[2]) begin
+                    main_litedramcore_choose_cmd_grant <= 2'd2;
                 end else begin
-                    if (litedramcore_choose_cmd_request[3]) begin
-                        litedramcore_choose_cmd_grant <= 2'd3;
+                    if (main_litedramcore_choose_cmd_request[3]) begin
+                        main_litedramcore_choose_cmd_grant <= 2'd3;
                     end else begin
-                        if (litedramcore_choose_cmd_request[4]) begin
-                            litedramcore_choose_cmd_grant <= 3'd4;
+                        if (main_litedramcore_choose_cmd_request[4]) begin
+                            main_litedramcore_choose_cmd_grant <= 3'd4;
                         end else begin
-                            if (litedramcore_choose_cmd_request[5]) begin
-                                litedramcore_choose_cmd_grant <= 3'd5;
+                            if (main_litedramcore_choose_cmd_request[5]) begin
+                                main_litedramcore_choose_cmd_grant <= 3'd5;
                             end else begin
-                                if (litedramcore_choose_cmd_request[6]) begin
-                                    litedramcore_choose_cmd_grant <= 3'd6;
+                                if (main_litedramcore_choose_cmd_request[6]) begin
+                                    main_litedramcore_choose_cmd_grant <= 3'd6;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[7]) begin
-                                        litedramcore_choose_cmd_grant <= 3'd7;
+                                    if (main_litedramcore_choose_cmd_request[7]) begin
+                                        main_litedramcore_choose_cmd_grant <= 3'd7;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[0]) begin
-                                            litedramcore_choose_cmd_grant <= 1'd0;
+                                        if (main_litedramcore_choose_cmd_request[0]) begin
+                                            main_litedramcore_choose_cmd_grant <= 1'd0;
                                         end
                                     end
                                 end
@@ -14987,26 +15575,26 @@ always @(posedge sys_clk) begin
                 end
             end
             2'd2: begin
-                if (litedramcore_choose_cmd_request[3]) begin
-                    litedramcore_choose_cmd_grant <= 2'd3;
+                if (main_litedramcore_choose_cmd_request[3]) begin
+                    main_litedramcore_choose_cmd_grant <= 2'd3;
                 end else begin
-                    if (litedramcore_choose_cmd_request[4]) begin
-                        litedramcore_choose_cmd_grant <= 3'd4;
+                    if (main_litedramcore_choose_cmd_request[4]) begin
+                        main_litedramcore_choose_cmd_grant <= 3'd4;
                     end else begin
-                        if (litedramcore_choose_cmd_request[5]) begin
-                            litedramcore_choose_cmd_grant <= 3'd5;
+                        if (main_litedramcore_choose_cmd_request[5]) begin
+                            main_litedramcore_choose_cmd_grant <= 3'd5;
                         end else begin
-                            if (litedramcore_choose_cmd_request[6]) begin
-                                litedramcore_choose_cmd_grant <= 3'd6;
+                            if (main_litedramcore_choose_cmd_request[6]) begin
+                                main_litedramcore_choose_cmd_grant <= 3'd6;
                             end else begin
-                                if (litedramcore_choose_cmd_request[7]) begin
-                                    litedramcore_choose_cmd_grant <= 3'd7;
+                                if (main_litedramcore_choose_cmd_request[7]) begin
+                                    main_litedramcore_choose_cmd_grant <= 3'd7;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[0]) begin
-                                        litedramcore_choose_cmd_grant <= 1'd0;
+                                    if (main_litedramcore_choose_cmd_request[0]) begin
+                                        main_litedramcore_choose_cmd_grant <= 1'd0;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[1]) begin
-                                            litedramcore_choose_cmd_grant <= 1'd1;
+                                        if (main_litedramcore_choose_cmd_request[1]) begin
+                                            main_litedramcore_choose_cmd_grant <= 1'd1;
                                         end
                                     end
                                 end
@@ -15016,26 +15604,26 @@ always @(posedge sys_clk) begin
                 end
             end
             2'd3: begin
-                if (litedramcore_choose_cmd_request[4]) begin
-                    litedramcore_choose_cmd_grant <= 3'd4;
+                if (main_litedramcore_choose_cmd_request[4]) begin
+                    main_litedramcore_choose_cmd_grant <= 3'd4;
                 end else begin
-                    if (litedramcore_choose_cmd_request[5]) begin
-                        litedramcore_choose_cmd_grant <= 3'd5;
+                    if (main_litedramcore_choose_cmd_request[5]) begin
+                        main_litedramcore_choose_cmd_grant <= 3'd5;
                     end else begin
-                        if (litedramcore_choose_cmd_request[6]) begin
-                            litedramcore_choose_cmd_grant <= 3'd6;
+                        if (main_litedramcore_choose_cmd_request[6]) begin
+                            main_litedramcore_choose_cmd_grant <= 3'd6;
                         end else begin
-                            if (litedramcore_choose_cmd_request[7]) begin
-                                litedramcore_choose_cmd_grant <= 3'd7;
+                            if (main_litedramcore_choose_cmd_request[7]) begin
+                                main_litedramcore_choose_cmd_grant <= 3'd7;
                             end else begin
-                                if (litedramcore_choose_cmd_request[0]) begin
-                                    litedramcore_choose_cmd_grant <= 1'd0;
+                                if (main_litedramcore_choose_cmd_request[0]) begin
+                                    main_litedramcore_choose_cmd_grant <= 1'd0;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[1]) begin
-                                        litedramcore_choose_cmd_grant <= 1'd1;
+                                    if (main_litedramcore_choose_cmd_request[1]) begin
+                                        main_litedramcore_choose_cmd_grant <= 1'd1;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[2]) begin
-                                            litedramcore_choose_cmd_grant <= 2'd2;
+                                        if (main_litedramcore_choose_cmd_request[2]) begin
+                                            main_litedramcore_choose_cmd_grant <= 2'd2;
                                         end
                                     end
                                 end
@@ -15045,26 +15633,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd4: begin
-                if (litedramcore_choose_cmd_request[5]) begin
-                    litedramcore_choose_cmd_grant <= 3'd5;
+                if (main_litedramcore_choose_cmd_request[5]) begin
+                    main_litedramcore_choose_cmd_grant <= 3'd5;
                 end else begin
-                    if (litedramcore_choose_cmd_request[6]) begin
-                        litedramcore_choose_cmd_grant <= 3'd6;
+                    if (main_litedramcore_choose_cmd_request[6]) begin
+                        main_litedramcore_choose_cmd_grant <= 3'd6;
                     end else begin
-                        if (litedramcore_choose_cmd_request[7]) begin
-                            litedramcore_choose_cmd_grant <= 3'd7;
+                        if (main_litedramcore_choose_cmd_request[7]) begin
+                            main_litedramcore_choose_cmd_grant <= 3'd7;
                         end else begin
-                            if (litedramcore_choose_cmd_request[0]) begin
-                                litedramcore_choose_cmd_grant <= 1'd0;
+                            if (main_litedramcore_choose_cmd_request[0]) begin
+                                main_litedramcore_choose_cmd_grant <= 1'd0;
                             end else begin
-                                if (litedramcore_choose_cmd_request[1]) begin
-                                    litedramcore_choose_cmd_grant <= 1'd1;
+                                if (main_litedramcore_choose_cmd_request[1]) begin
+                                    main_litedramcore_choose_cmd_grant <= 1'd1;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[2]) begin
-                                        litedramcore_choose_cmd_grant <= 2'd2;
+                                    if (main_litedramcore_choose_cmd_request[2]) begin
+                                        main_litedramcore_choose_cmd_grant <= 2'd2;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[3]) begin
-                                            litedramcore_choose_cmd_grant <= 2'd3;
+                                        if (main_litedramcore_choose_cmd_request[3]) begin
+                                            main_litedramcore_choose_cmd_grant <= 2'd3;
                                         end
                                     end
                                 end
@@ -15074,26 +15662,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd5: begin
-                if (litedramcore_choose_cmd_request[6]) begin
-                    litedramcore_choose_cmd_grant <= 3'd6;
+                if (main_litedramcore_choose_cmd_request[6]) begin
+                    main_litedramcore_choose_cmd_grant <= 3'd6;
                 end else begin
-                    if (litedramcore_choose_cmd_request[7]) begin
-                        litedramcore_choose_cmd_grant <= 3'd7;
+                    if (main_litedramcore_choose_cmd_request[7]) begin
+                        main_litedramcore_choose_cmd_grant <= 3'd7;
                     end else begin
-                        if (litedramcore_choose_cmd_request[0]) begin
-                            litedramcore_choose_cmd_grant <= 1'd0;
+                        if (main_litedramcore_choose_cmd_request[0]) begin
+                            main_litedramcore_choose_cmd_grant <= 1'd0;
                         end else begin
-                            if (litedramcore_choose_cmd_request[1]) begin
-                                litedramcore_choose_cmd_grant <= 1'd1;
+                            if (main_litedramcore_choose_cmd_request[1]) begin
+                                main_litedramcore_choose_cmd_grant <= 1'd1;
                             end else begin
-                                if (litedramcore_choose_cmd_request[2]) begin
-                                    litedramcore_choose_cmd_grant <= 2'd2;
+                                if (main_litedramcore_choose_cmd_request[2]) begin
+                                    main_litedramcore_choose_cmd_grant <= 2'd2;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[3]) begin
-                                        litedramcore_choose_cmd_grant <= 2'd3;
+                                    if (main_litedramcore_choose_cmd_request[3]) begin
+                                        main_litedramcore_choose_cmd_grant <= 2'd3;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[4]) begin
-                                            litedramcore_choose_cmd_grant <= 3'd4;
+                                        if (main_litedramcore_choose_cmd_request[4]) begin
+                                            main_litedramcore_choose_cmd_grant <= 3'd4;
                                         end
                                     end
                                 end
@@ -15103,26 +15691,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd6: begin
-                if (litedramcore_choose_cmd_request[7]) begin
-                    litedramcore_choose_cmd_grant <= 3'd7;
+                if (main_litedramcore_choose_cmd_request[7]) begin
+                    main_litedramcore_choose_cmd_grant <= 3'd7;
                 end else begin
-                    if (litedramcore_choose_cmd_request[0]) begin
-                        litedramcore_choose_cmd_grant <= 1'd0;
+                    if (main_litedramcore_choose_cmd_request[0]) begin
+                        main_litedramcore_choose_cmd_grant <= 1'd0;
                     end else begin
-                        if (litedramcore_choose_cmd_request[1]) begin
-                            litedramcore_choose_cmd_grant <= 1'd1;
+                        if (main_litedramcore_choose_cmd_request[1]) begin
+                            main_litedramcore_choose_cmd_grant <= 1'd1;
                         end else begin
-                            if (litedramcore_choose_cmd_request[2]) begin
-                                litedramcore_choose_cmd_grant <= 2'd2;
+                            if (main_litedramcore_choose_cmd_request[2]) begin
+                                main_litedramcore_choose_cmd_grant <= 2'd2;
                             end else begin
-                                if (litedramcore_choose_cmd_request[3]) begin
-                                    litedramcore_choose_cmd_grant <= 2'd3;
+                                if (main_litedramcore_choose_cmd_request[3]) begin
+                                    main_litedramcore_choose_cmd_grant <= 2'd3;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[4]) begin
-                                        litedramcore_choose_cmd_grant <= 3'd4;
+                                    if (main_litedramcore_choose_cmd_request[4]) begin
+                                        main_litedramcore_choose_cmd_grant <= 3'd4;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[5]) begin
-                                            litedramcore_choose_cmd_grant <= 3'd5;
+                                        if (main_litedramcore_choose_cmd_request[5]) begin
+                                            main_litedramcore_choose_cmd_grant <= 3'd5;
                                         end
                                     end
                                 end
@@ -15132,26 +15720,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd7: begin
-                if (litedramcore_choose_cmd_request[0]) begin
-                    litedramcore_choose_cmd_grant <= 1'd0;
+                if (main_litedramcore_choose_cmd_request[0]) begin
+                    main_litedramcore_choose_cmd_grant <= 1'd0;
                 end else begin
-                    if (litedramcore_choose_cmd_request[1]) begin
-                        litedramcore_choose_cmd_grant <= 1'd1;
+                    if (main_litedramcore_choose_cmd_request[1]) begin
+                        main_litedramcore_choose_cmd_grant <= 1'd1;
                     end else begin
-                        if (litedramcore_choose_cmd_request[2]) begin
-                            litedramcore_choose_cmd_grant <= 2'd2;
+                        if (main_litedramcore_choose_cmd_request[2]) begin
+                            main_litedramcore_choose_cmd_grant <= 2'd2;
                         end else begin
-                            if (litedramcore_choose_cmd_request[3]) begin
-                                litedramcore_choose_cmd_grant <= 2'd3;
+                            if (main_litedramcore_choose_cmd_request[3]) begin
+                                main_litedramcore_choose_cmd_grant <= 2'd3;
                             end else begin
-                                if (litedramcore_choose_cmd_request[4]) begin
-                                    litedramcore_choose_cmd_grant <= 3'd4;
+                                if (main_litedramcore_choose_cmd_request[4]) begin
+                                    main_litedramcore_choose_cmd_grant <= 3'd4;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[5]) begin
-                                        litedramcore_choose_cmd_grant <= 3'd5;
+                                    if (main_litedramcore_choose_cmd_request[5]) begin
+                                        main_litedramcore_choose_cmd_grant <= 3'd5;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[6]) begin
-                                            litedramcore_choose_cmd_grant <= 3'd6;
+                                        if (main_litedramcore_choose_cmd_request[6]) begin
+                                            main_litedramcore_choose_cmd_grant <= 3'd6;
                                         end
                                     end
                                 end
@@ -15162,29 +15750,29 @@ always @(posedge sys_clk) begin
             end
         endcase
     end
-    if (litedramcore_choose_req_ce) begin
-        case (litedramcore_choose_req_grant)
+    if (main_litedramcore_choose_req_ce) begin
+        case (main_litedramcore_choose_req_grant)
             1'd0: begin
-                if (litedramcore_choose_req_request[1]) begin
-                    litedramcore_choose_req_grant <= 1'd1;
+                if (main_litedramcore_choose_req_request[1]) begin
+                    main_litedramcore_choose_req_grant <= 1'd1;
                 end else begin
-                    if (litedramcore_choose_req_request[2]) begin
-                        litedramcore_choose_req_grant <= 2'd2;
+                    if (main_litedramcore_choose_req_request[2]) begin
+                        main_litedramcore_choose_req_grant <= 2'd2;
                     end else begin
-                        if (litedramcore_choose_req_request[3]) begin
-                            litedramcore_choose_req_grant <= 2'd3;
+                        if (main_litedramcore_choose_req_request[3]) begin
+                            main_litedramcore_choose_req_grant <= 2'd3;
                         end else begin
-                            if (litedramcore_choose_req_request[4]) begin
-                                litedramcore_choose_req_grant <= 3'd4;
+                            if (main_litedramcore_choose_req_request[4]) begin
+                                main_litedramcore_choose_req_grant <= 3'd4;
                             end else begin
-                                if (litedramcore_choose_req_request[5]) begin
-                                    litedramcore_choose_req_grant <= 3'd5;
+                                if (main_litedramcore_choose_req_request[5]) begin
+                                    main_litedramcore_choose_req_grant <= 3'd5;
                                 end else begin
-                                    if (litedramcore_choose_req_request[6]) begin
-                                        litedramcore_choose_req_grant <= 3'd6;
+                                    if (main_litedramcore_choose_req_request[6]) begin
+                                        main_litedramcore_choose_req_grant <= 3'd6;
                                     end else begin
-                                        if (litedramcore_choose_req_request[7]) begin
-                                            litedramcore_choose_req_grant <= 3'd7;
+                                        if (main_litedramcore_choose_req_request[7]) begin
+                                            main_litedramcore_choose_req_grant <= 3'd7;
                                         end
                                     end
                                 end
@@ -15194,26 +15782,26 @@ always @(posedge sys_clk) begin
                 end
             end
             1'd1: begin
-                if (litedramcore_choose_req_request[2]) begin
-                    litedramcore_choose_req_grant <= 2'd2;
+                if (main_litedramcore_choose_req_request[2]) begin
+                    main_litedramcore_choose_req_grant <= 2'd2;
                 end else begin
-                    if (litedramcore_choose_req_request[3]) begin
-                        litedramcore_choose_req_grant <= 2'd3;
+                    if (main_litedramcore_choose_req_request[3]) begin
+                        main_litedramcore_choose_req_grant <= 2'd3;
                     end else begin
-                        if (litedramcore_choose_req_request[4]) begin
-                            litedramcore_choose_req_grant <= 3'd4;
+                        if (main_litedramcore_choose_req_request[4]) begin
+                            main_litedramcore_choose_req_grant <= 3'd4;
                         end else begin
-                            if (litedramcore_choose_req_request[5]) begin
-                                litedramcore_choose_req_grant <= 3'd5;
+                            if (main_litedramcore_choose_req_request[5]) begin
+                                main_litedramcore_choose_req_grant <= 3'd5;
                             end else begin
-                                if (litedramcore_choose_req_request[6]) begin
-                                    litedramcore_choose_req_grant <= 3'd6;
+                                if (main_litedramcore_choose_req_request[6]) begin
+                                    main_litedramcore_choose_req_grant <= 3'd6;
                                 end else begin
-                                    if (litedramcore_choose_req_request[7]) begin
-                                        litedramcore_choose_req_grant <= 3'd7;
+                                    if (main_litedramcore_choose_req_request[7]) begin
+                                        main_litedramcore_choose_req_grant <= 3'd7;
                                     end else begin
-                                        if (litedramcore_choose_req_request[0]) begin
-                                            litedramcore_choose_req_grant <= 1'd0;
+                                        if (main_litedramcore_choose_req_request[0]) begin
+                                            main_litedramcore_choose_req_grant <= 1'd0;
                                         end
                                     end
                                 end
@@ -15223,26 +15811,26 @@ always @(posedge sys_clk) begin
                 end
             end
             2'd2: begin
-                if (litedramcore_choose_req_request[3]) begin
-                    litedramcore_choose_req_grant <= 2'd3;
+                if (main_litedramcore_choose_req_request[3]) begin
+                    main_litedramcore_choose_req_grant <= 2'd3;
                 end else begin
-                    if (litedramcore_choose_req_request[4]) begin
-                        litedramcore_choose_req_grant <= 3'd4;
+                    if (main_litedramcore_choose_req_request[4]) begin
+                        main_litedramcore_choose_req_grant <= 3'd4;
                     end else begin
-                        if (litedramcore_choose_req_request[5]) begin
-                            litedramcore_choose_req_grant <= 3'd5;
+                        if (main_litedramcore_choose_req_request[5]) begin
+                            main_litedramcore_choose_req_grant <= 3'd5;
                         end else begin
-                            if (litedramcore_choose_req_request[6]) begin
-                                litedramcore_choose_req_grant <= 3'd6;
+                            if (main_litedramcore_choose_req_request[6]) begin
+                                main_litedramcore_choose_req_grant <= 3'd6;
                             end else begin
-                                if (litedramcore_choose_req_request[7]) begin
-                                    litedramcore_choose_req_grant <= 3'd7;
+                                if (main_litedramcore_choose_req_request[7]) begin
+                                    main_litedramcore_choose_req_grant <= 3'd7;
                                 end else begin
-                                    if (litedramcore_choose_req_request[0]) begin
-                                        litedramcore_choose_req_grant <= 1'd0;
+                                    if (main_litedramcore_choose_req_request[0]) begin
+                                        main_litedramcore_choose_req_grant <= 1'd0;
                                     end else begin
-                                        if (litedramcore_choose_req_request[1]) begin
-                                            litedramcore_choose_req_grant <= 1'd1;
+                                        if (main_litedramcore_choose_req_request[1]) begin
+                                            main_litedramcore_choose_req_grant <= 1'd1;
                                         end
                                     end
                                 end
@@ -15252,26 +15840,26 @@ always @(posedge sys_clk) begin
                 end
             end
             2'd3: begin
-                if (litedramcore_choose_req_request[4]) begin
-                    litedramcore_choose_req_grant <= 3'd4;
+                if (main_litedramcore_choose_req_request[4]) begin
+                    main_litedramcore_choose_req_grant <= 3'd4;
                 end else begin
-                    if (litedramcore_choose_req_request[5]) begin
-                        litedramcore_choose_req_grant <= 3'd5;
+                    if (main_litedramcore_choose_req_request[5]) begin
+                        main_litedramcore_choose_req_grant <= 3'd5;
                     end else begin
-                        if (litedramcore_choose_req_request[6]) begin
-                            litedramcore_choose_req_grant <= 3'd6;
+                        if (main_litedramcore_choose_req_request[6]) begin
+                            main_litedramcore_choose_req_grant <= 3'd6;
                         end else begin
-                            if (litedramcore_choose_req_request[7]) begin
-                                litedramcore_choose_req_grant <= 3'd7;
+                            if (main_litedramcore_choose_req_request[7]) begin
+                                main_litedramcore_choose_req_grant <= 3'd7;
                             end else begin
-                                if (litedramcore_choose_req_request[0]) begin
-                                    litedramcore_choose_req_grant <= 1'd0;
+                                if (main_litedramcore_choose_req_request[0]) begin
+                                    main_litedramcore_choose_req_grant <= 1'd0;
                                 end else begin
-                                    if (litedramcore_choose_req_request[1]) begin
-                                        litedramcore_choose_req_grant <= 1'd1;
+                                    if (main_litedramcore_choose_req_request[1]) begin
+                                        main_litedramcore_choose_req_grant <= 1'd1;
                                     end else begin
-                                        if (litedramcore_choose_req_request[2]) begin
-                                            litedramcore_choose_req_grant <= 2'd2;
+                                        if (main_litedramcore_choose_req_request[2]) begin
+                                            main_litedramcore_choose_req_grant <= 2'd2;
                                         end
                                     end
                                 end
@@ -15281,26 +15869,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd4: begin
-                if (litedramcore_choose_req_request[5]) begin
-                    litedramcore_choose_req_grant <= 3'd5;
+                if (main_litedramcore_choose_req_request[5]) begin
+                    main_litedramcore_choose_req_grant <= 3'd5;
                 end else begin
-                    if (litedramcore_choose_req_request[6]) begin
-                        litedramcore_choose_req_grant <= 3'd6;
+                    if (main_litedramcore_choose_req_request[6]) begin
+                        main_litedramcore_choose_req_grant <= 3'd6;
                     end else begin
-                        if (litedramcore_choose_req_request[7]) begin
-                            litedramcore_choose_req_grant <= 3'd7;
+                        if (main_litedramcore_choose_req_request[7]) begin
+                            main_litedramcore_choose_req_grant <= 3'd7;
                         end else begin
-                            if (litedramcore_choose_req_request[0]) begin
-                                litedramcore_choose_req_grant <= 1'd0;
+                            if (main_litedramcore_choose_req_request[0]) begin
+                                main_litedramcore_choose_req_grant <= 1'd0;
                             end else begin
-                                if (litedramcore_choose_req_request[1]) begin
-                                    litedramcore_choose_req_grant <= 1'd1;
+                                if (main_litedramcore_choose_req_request[1]) begin
+                                    main_litedramcore_choose_req_grant <= 1'd1;
                                 end else begin
-                                    if (litedramcore_choose_req_request[2]) begin
-                                        litedramcore_choose_req_grant <= 2'd2;
+                                    if (main_litedramcore_choose_req_request[2]) begin
+                                        main_litedramcore_choose_req_grant <= 2'd2;
                                     end else begin
-                                        if (litedramcore_choose_req_request[3]) begin
-                                            litedramcore_choose_req_grant <= 2'd3;
+                                        if (main_litedramcore_choose_req_request[3]) begin
+                                            main_litedramcore_choose_req_grant <= 2'd3;
                                         end
                                     end
                                 end
@@ -15310,26 +15898,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd5: begin
-                if (litedramcore_choose_req_request[6]) begin
-                    litedramcore_choose_req_grant <= 3'd6;
+                if (main_litedramcore_choose_req_request[6]) begin
+                    main_litedramcore_choose_req_grant <= 3'd6;
                 end else begin
-                    if (litedramcore_choose_req_request[7]) begin
-                        litedramcore_choose_req_grant <= 3'd7;
+                    if (main_litedramcore_choose_req_request[7]) begin
+                        main_litedramcore_choose_req_grant <= 3'd7;
                     end else begin
-                        if (litedramcore_choose_req_request[0]) begin
-                            litedramcore_choose_req_grant <= 1'd0;
+                        if (main_litedramcore_choose_req_request[0]) begin
+                            main_litedramcore_choose_req_grant <= 1'd0;
                         end else begin
-                            if (litedramcore_choose_req_request[1]) begin
-                                litedramcore_choose_req_grant <= 1'd1;
+                            if (main_litedramcore_choose_req_request[1]) begin
+                                main_litedramcore_choose_req_grant <= 1'd1;
                             end else begin
-                                if (litedramcore_choose_req_request[2]) begin
-                                    litedramcore_choose_req_grant <= 2'd2;
+                                if (main_litedramcore_choose_req_request[2]) begin
+                                    main_litedramcore_choose_req_grant <= 2'd2;
                                 end else begin
-                                    if (litedramcore_choose_req_request[3]) begin
-                                        litedramcore_choose_req_grant <= 2'd3;
+                                    if (main_litedramcore_choose_req_request[3]) begin
+                                        main_litedramcore_choose_req_grant <= 2'd3;
                                     end else begin
-                                        if (litedramcore_choose_req_request[4]) begin
-                                            litedramcore_choose_req_grant <= 3'd4;
+                                        if (main_litedramcore_choose_req_request[4]) begin
+                                            main_litedramcore_choose_req_grant <= 3'd4;
                                         end
                                     end
                                 end
@@ -15339,26 +15927,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd6: begin
-                if (litedramcore_choose_req_request[7]) begin
-                    litedramcore_choose_req_grant <= 3'd7;
+                if (main_litedramcore_choose_req_request[7]) begin
+                    main_litedramcore_choose_req_grant <= 3'd7;
                 end else begin
-                    if (litedramcore_choose_req_request[0]) begin
-                        litedramcore_choose_req_grant <= 1'd0;
+                    if (main_litedramcore_choose_req_request[0]) begin
+                        main_litedramcore_choose_req_grant <= 1'd0;
                     end else begin
-                        if (litedramcore_choose_req_request[1]) begin
-                            litedramcore_choose_req_grant <= 1'd1;
+                        if (main_litedramcore_choose_req_request[1]) begin
+                            main_litedramcore_choose_req_grant <= 1'd1;
                         end else begin
-                            if (litedramcore_choose_req_request[2]) begin
-                                litedramcore_choose_req_grant <= 2'd2;
+                            if (main_litedramcore_choose_req_request[2]) begin
+                                main_litedramcore_choose_req_grant <= 2'd2;
                             end else begin
-                                if (litedramcore_choose_req_request[3]) begin
-                                    litedramcore_choose_req_grant <= 2'd3;
+                                if (main_litedramcore_choose_req_request[3]) begin
+                                    main_litedramcore_choose_req_grant <= 2'd3;
                                 end else begin
-                                    if (litedramcore_choose_req_request[4]) begin
-                                        litedramcore_choose_req_grant <= 3'd4;
+                                    if (main_litedramcore_choose_req_request[4]) begin
+                                        main_litedramcore_choose_req_grant <= 3'd4;
                                     end else begin
-                                        if (litedramcore_choose_req_request[5]) begin
-                                            litedramcore_choose_req_grant <= 3'd5;
+                                        if (main_litedramcore_choose_req_request[5]) begin
+                                            main_litedramcore_choose_req_grant <= 3'd5;
                                         end
                                     end
                                 end
@@ -15368,26 +15956,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd7: begin
-                if (litedramcore_choose_req_request[0]) begin
-                    litedramcore_choose_req_grant <= 1'd0;
+                if (main_litedramcore_choose_req_request[0]) begin
+                    main_litedramcore_choose_req_grant <= 1'd0;
                 end else begin
-                    if (litedramcore_choose_req_request[1]) begin
-                        litedramcore_choose_req_grant <= 1'd1;
+                    if (main_litedramcore_choose_req_request[1]) begin
+                        main_litedramcore_choose_req_grant <= 1'd1;
                     end else begin
-                        if (litedramcore_choose_req_request[2]) begin
-                            litedramcore_choose_req_grant <= 2'd2;
+                        if (main_litedramcore_choose_req_request[2]) begin
+                            main_litedramcore_choose_req_grant <= 2'd2;
                         end else begin
-                            if (litedramcore_choose_req_request[3]) begin
-                                litedramcore_choose_req_grant <= 2'd3;
+                            if (main_litedramcore_choose_req_request[3]) begin
+                                main_litedramcore_choose_req_grant <= 2'd3;
                             end else begin
-                                if (litedramcore_choose_req_request[4]) begin
-                                    litedramcore_choose_req_grant <= 3'd4;
+                                if (main_litedramcore_choose_req_request[4]) begin
+                                    main_litedramcore_choose_req_grant <= 3'd4;
                                 end else begin
-                                    if (litedramcore_choose_req_request[5]) begin
-                                        litedramcore_choose_req_grant <= 3'd5;
+                                    if (main_litedramcore_choose_req_request[5]) begin
+                                        main_litedramcore_choose_req_grant <= 3'd5;
                                     end else begin
-                                        if (litedramcore_choose_req_request[6]) begin
-                                            litedramcore_choose_req_grant <= 3'd6;
+                                        if (main_litedramcore_choose_req_request[6]) begin
+                                            main_litedramcore_choose_req_grant <= 3'd6;
                                         end
                                     end
                                 end
@@ -15398,733 +15986,733 @@ always @(posedge sys_clk) begin
             end
         endcase
     end
-    litedramcore_dfi_p0_cs_n <= 1'd0;
-    litedramcore_dfi_p0_bank <= array_muxed0;
-    litedramcore_dfi_p0_address <= array_muxed1;
-    litedramcore_dfi_p0_cas_n <= (~array_muxed2);
-    litedramcore_dfi_p0_ras_n <= (~array_muxed3);
-    litedramcore_dfi_p0_we_n <= (~array_muxed4);
-    litedramcore_dfi_p0_rddata_en <= array_muxed5;
-    litedramcore_dfi_p0_wrdata_en <= array_muxed6;
-    litedramcore_dfi_p1_cs_n <= 1'd0;
-    litedramcore_dfi_p1_bank <= array_muxed7;
-    litedramcore_dfi_p1_address <= array_muxed8;
-    litedramcore_dfi_p1_cas_n <= (~array_muxed9);
-    litedramcore_dfi_p1_ras_n <= (~array_muxed10);
-    litedramcore_dfi_p1_we_n <= (~array_muxed11);
-    litedramcore_dfi_p1_rddata_en <= array_muxed12;
-    litedramcore_dfi_p1_wrdata_en <= array_muxed13;
-    litedramcore_dfi_p2_cs_n <= 1'd0;
-    litedramcore_dfi_p2_bank <= array_muxed14;
-    litedramcore_dfi_p2_address <= array_muxed15;
-    litedramcore_dfi_p2_cas_n <= (~array_muxed16);
-    litedramcore_dfi_p2_ras_n <= (~array_muxed17);
-    litedramcore_dfi_p2_we_n <= (~array_muxed18);
-    litedramcore_dfi_p2_rddata_en <= array_muxed19;
-    litedramcore_dfi_p2_wrdata_en <= array_muxed20;
-    litedramcore_dfi_p3_cs_n <= 1'd0;
-    litedramcore_dfi_p3_bank <= array_muxed21;
-    litedramcore_dfi_p3_address <= array_muxed22;
-    litedramcore_dfi_p3_cas_n <= (~array_muxed23);
-    litedramcore_dfi_p3_ras_n <= (~array_muxed24);
-    litedramcore_dfi_p3_we_n <= (~array_muxed25);
-    litedramcore_dfi_p3_rddata_en <= array_muxed26;
-    litedramcore_dfi_p3_wrdata_en <= array_muxed27;
-    if (litedramcore_trrdcon_valid) begin
-        litedramcore_trrdcon_count <= 1'd1;
+    main_litedramcore_dfi_p0_cs_n <= 1'd0;
+    main_litedramcore_dfi_p0_bank <= builder_self0;
+    main_litedramcore_dfi_p0_address <= builder_self1;
+    main_litedramcore_dfi_p0_cas_n <= (~builder_self2);
+    main_litedramcore_dfi_p0_ras_n <= (~builder_self3);
+    main_litedramcore_dfi_p0_we_n <= (~builder_self4);
+    main_litedramcore_dfi_p0_rddata_en <= builder_self5;
+    main_litedramcore_dfi_p0_wrdata_en <= builder_self6;
+    main_litedramcore_dfi_p1_cs_n <= 1'd0;
+    main_litedramcore_dfi_p1_bank <= builder_self7;
+    main_litedramcore_dfi_p1_address <= builder_self8;
+    main_litedramcore_dfi_p1_cas_n <= (~builder_self9);
+    main_litedramcore_dfi_p1_ras_n <= (~builder_self10);
+    main_litedramcore_dfi_p1_we_n <= (~builder_self11);
+    main_litedramcore_dfi_p1_rddata_en <= builder_self12;
+    main_litedramcore_dfi_p1_wrdata_en <= builder_self13;
+    main_litedramcore_dfi_p2_cs_n <= 1'd0;
+    main_litedramcore_dfi_p2_bank <= builder_self14;
+    main_litedramcore_dfi_p2_address <= builder_self15;
+    main_litedramcore_dfi_p2_cas_n <= (~builder_self16);
+    main_litedramcore_dfi_p2_ras_n <= (~builder_self17);
+    main_litedramcore_dfi_p2_we_n <= (~builder_self18);
+    main_litedramcore_dfi_p2_rddata_en <= builder_self19;
+    main_litedramcore_dfi_p2_wrdata_en <= builder_self20;
+    main_litedramcore_dfi_p3_cs_n <= 1'd0;
+    main_litedramcore_dfi_p3_bank <= builder_self21;
+    main_litedramcore_dfi_p3_address <= builder_self22;
+    main_litedramcore_dfi_p3_cas_n <= (~builder_self23);
+    main_litedramcore_dfi_p3_ras_n <= (~builder_self24);
+    main_litedramcore_dfi_p3_we_n <= (~builder_self25);
+    main_litedramcore_dfi_p3_rddata_en <= builder_self26;
+    main_litedramcore_dfi_p3_wrdata_en <= builder_self27;
+    if (main_litedramcore_trrdcon_valid) begin
+        main_litedramcore_trrdcon_count <= 1'd1;
         if (1'd0) begin
-            litedramcore_trrdcon_ready <= 1'd1;
+            main_litedramcore_trrdcon_ready <= 1'd1;
         end else begin
-            litedramcore_trrdcon_ready <= 1'd0;
+            main_litedramcore_trrdcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_trrdcon_ready)) begin
-            litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
-            if ((litedramcore_trrdcon_count == 1'd1)) begin
-                litedramcore_trrdcon_ready <= 1'd1;
+        if ((~main_litedramcore_trrdcon_ready)) begin
+            main_litedramcore_trrdcon_count <= (main_litedramcore_trrdcon_count - 1'd1);
+            if ((main_litedramcore_trrdcon_count == 1'd1)) begin
+                main_litedramcore_trrdcon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
-    if ((litedramcore_tfawcon_count < 3'd4)) begin
-        if ((litedramcore_tfawcon_count == 2'd3)) begin
-            litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
+    main_litedramcore_tfawcon_window <= {main_litedramcore_tfawcon_window, main_litedramcore_tfawcon_valid};
+    if ((main_litedramcore_tfawcon_count < 3'd4)) begin
+        if ((main_litedramcore_tfawcon_count == 2'd3)) begin
+            main_litedramcore_tfawcon_ready <= (~main_litedramcore_tfawcon_valid);
         end else begin
-            litedramcore_tfawcon_ready <= 1'd1;
+            main_litedramcore_tfawcon_ready <= 1'd1;
         end
     end
-    if (litedramcore_tccdcon_valid) begin
-        litedramcore_tccdcon_count <= 1'd0;
+    if (main_litedramcore_tccdcon_valid) begin
+        main_litedramcore_tccdcon_count <= 1'd0;
         if (1'd1) begin
-            litedramcore_tccdcon_ready <= 1'd1;
+            main_litedramcore_tccdcon_ready <= 1'd1;
         end else begin
-            litedramcore_tccdcon_ready <= 1'd0;
+            main_litedramcore_tccdcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_tccdcon_ready)) begin
-            litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
-            if ((litedramcore_tccdcon_count == 1'd1)) begin
-                litedramcore_tccdcon_ready <= 1'd1;
+        if ((~main_litedramcore_tccdcon_ready)) begin
+            main_litedramcore_tccdcon_count <= (main_litedramcore_tccdcon_count - 1'd1);
+            if ((main_litedramcore_tccdcon_count == 1'd1)) begin
+                main_litedramcore_tccdcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_twtrcon_valid) begin
-        litedramcore_twtrcon_count <= 3'd4;
+    if (main_litedramcore_twtrcon_valid) begin
+        main_litedramcore_twtrcon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_twtrcon_ready <= 1'd1;
+            main_litedramcore_twtrcon_ready <= 1'd1;
         end else begin
-            litedramcore_twtrcon_ready <= 1'd0;
+            main_litedramcore_twtrcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_twtrcon_ready)) begin
-            litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
-            if ((litedramcore_twtrcon_count == 1'd1)) begin
-                litedramcore_twtrcon_ready <= 1'd1;
-            end
-        end
-    end
-    litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
-    litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
-    litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
-    litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
-    litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
-    litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
-    litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
-    litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
-    litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
-    litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
-    litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
-    litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
-    litedramcore_state <= litedramcore_next_state;
-    if (litedramcore_dat_w_next_value_ce0) begin
-        litedramcore_dat_w <= litedramcore_dat_w_next_value0;
-    end
-    if (litedramcore_adr_next_value_ce1) begin
-        litedramcore_adr <= litedramcore_adr_next_value1;
-    end
-    if (litedramcore_we_next_value_ce2) begin
-        litedramcore_we <= litedramcore_we_next_value2;
-    end
-    interface0_bank_bus_dat_r <= 1'd0;
-    if (csrbank0_sel) begin
-        case (interface0_bank_bus_adr[8:0])
+        if ((~main_litedramcore_twtrcon_ready)) begin
+            main_litedramcore_twtrcon_count <= (main_litedramcore_twtrcon_count - 1'd1);
+            if ((main_litedramcore_twtrcon_count == 1'd1)) begin
+                main_litedramcore_twtrcon_ready <= 1'd1;
+            end
+        end
+    end
+    builder_multiplexer_state <= builder_multiplexer_next_state;
+    builder_new_master_wdata_ready0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_wdata_ready)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_wdata_ready)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_wdata_ready)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_wdata_ready)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_wdata_ready)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_wdata_ready)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_wdata_ready)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_wdata_ready));
+    builder_new_master_wdata_ready1 <= builder_new_master_wdata_ready0;
+    builder_new_master_rdata_valid0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_rdata_valid)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_rdata_valid)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_rdata_valid)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_rdata_valid)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_rdata_valid)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_rdata_valid)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_rdata_valid)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_rdata_valid));
+    builder_new_master_rdata_valid1 <= builder_new_master_rdata_valid0;
+    builder_new_master_rdata_valid2 <= builder_new_master_rdata_valid1;
+    builder_new_master_rdata_valid3 <= builder_new_master_rdata_valid2;
+    builder_new_master_rdata_valid4 <= builder_new_master_rdata_valid3;
+    builder_new_master_rdata_valid5 <= builder_new_master_rdata_valid4;
+    builder_new_master_rdata_valid6 <= builder_new_master_rdata_valid5;
+    builder_new_master_rdata_valid7 <= builder_new_master_rdata_valid6;
+    builder_new_master_rdata_valid8 <= builder_new_master_rdata_valid7;
+    builder_state <= builder_next_state;
+    if (builder_interface1_dat_w_next_value_ce0) begin
+        builder_interface1_dat_w <= builder_interface1_dat_w_next_value0;
+    end
+    if (builder_interface1_adr_next_value_ce1) begin
+        builder_interface1_adr <= builder_interface1_adr_next_value1;
+    end
+    if (builder_interface1_we_next_value_ce2) begin
+        builder_interface1_we <= builder_interface1_we_next_value2;
+    end
+    builder_interface0_bank_bus_dat_r <= 1'd0;
+    if (builder_csrbank0_sel) begin
+        case (builder_interface0_bank_bus_adr[8:0])
             1'd0: begin
-                interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
+                builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_done0_w;
             end
             1'd1: begin
-                interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
+                builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_error0_w;
             end
         endcase
     end
-    if (csrbank0_init_done0_re) begin
-        init_done_storage <= csrbank0_init_done0_r;
+    if (builder_csrbank0_init_done0_re) begin
+        main_init_done_storage <= builder_csrbank0_init_done0_r;
     end
-    init_done_re <= csrbank0_init_done0_re;
-    if (csrbank0_init_error0_re) begin
-        init_error_storage <= csrbank0_init_error0_r;
+    main_init_done_re <= builder_csrbank0_init_done0_re;
+    if (builder_csrbank0_init_error0_re) begin
+        main_init_error_storage <= builder_csrbank0_init_error0_r;
     end
-    init_error_re <= csrbank0_init_error0_re;
-    interface1_bank_bus_dat_r <= 1'd0;
-    if (csrbank1_sel) begin
-        case (interface1_bank_bus_adr[8:0])
+    main_init_error_re <= builder_csrbank0_init_error0_re;
+    builder_interface1_bank_bus_dat_r <= 1'd0;
+    if (builder_csrbank1_sel) begin
+        case (builder_interface1_bank_bus_adr[8:0])
             1'd0: begin
-                interface1_bank_bus_dat_r <= csrbank1_rst0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_rst0_w;
             end
             1'd1: begin
-                interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_dly_sel0_w;
             end
             2'd2: begin
-                interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_half_sys8x_taps0_w;
             end
             2'd3: begin
-                interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_wlevel_en0_w;
             end
             3'd4: begin
-                interface1_bank_bus_dat_r <= k7ddrphy_wlevel_strobe_w;
+                builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wlevel_strobe_w;
             end
             3'd5: begin
-                interface1_bank_bus_dat_r <= k7ddrphy_cdly_rst_w;
+                builder_interface1_bank_bus_dat_r <= main_k7ddrphy_cdly_rst_w;
             end
             3'd6: begin
-                interface1_bank_bus_dat_r <= k7ddrphy_cdly_inc_w;
+                builder_interface1_bank_bus_dat_r <= main_k7ddrphy_cdly_inc_w;
             end
             3'd7: begin
-                interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_rst_w;
+                builder_interface1_bank_bus_dat_r <= main_k7ddrphy_rdly_dq_rst_w;
             end
             4'd8: begin
-                interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_inc_w;
+                builder_interface1_bank_bus_dat_r <= main_k7ddrphy_rdly_dq_inc_w;
             end
             4'd9: begin
-                interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_bitslip_rst_w;
+                builder_interface1_bank_bus_dat_r <= main_k7ddrphy_rdly_dq_bitslip_rst_w;
             end
             4'd10: begin
-                interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_bitslip_w;
+                builder_interface1_bank_bus_dat_r <= main_k7ddrphy_rdly_dq_bitslip_w;
             end
             4'd11: begin
-                interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_rst_w;
+                builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wdly_dq_rst_w;
             end
             4'd12: begin
-                interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_inc_w;
+                builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wdly_dq_inc_w;
             end
             4'd13: begin
-                interface1_bank_bus_dat_r <= k7ddrphy_wdly_dqs_rst_w;
+                builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wdly_dqs_rst_w;
             end
             4'd14: begin
-                interface1_bank_bus_dat_r <= k7ddrphy_wdly_dqs_inc_w;
+                builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wdly_dqs_inc_w;
             end
             4'd15: begin
-                interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_bitslip_rst_w;
+                builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wdly_dq_bitslip_rst_w;
             end
             5'd16: begin
-                interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_bitslip_w;
+                builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wdly_dq_bitslip_w;
             end
             5'd17: begin
-                interface1_bank_bus_dat_r <= csrbank1_rdphase0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_rdphase0_w;
             end
             5'd18: begin
-                interface1_bank_bus_dat_r <= csrbank1_wrphase0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_wrphase0_w;
             end
         endcase
     end
-    if (csrbank1_rst0_re) begin
-        k7ddrphy_rst_storage <= csrbank1_rst0_r;
+    if (builder_csrbank1_rst0_re) begin
+        main_k7ddrphy_rst_storage <= builder_csrbank1_rst0_r;
     end
-    k7ddrphy_rst_re <= csrbank1_rst0_re;
-    if (csrbank1_dly_sel0_re) begin
-        k7ddrphy_dly_sel_storage[3:0] <= csrbank1_dly_sel0_r;
+    main_k7ddrphy_rst_re <= builder_csrbank1_rst0_re;
+    if (builder_csrbank1_dly_sel0_re) begin
+        main_k7ddrphy_dly_sel_storage[3:0] <= builder_csrbank1_dly_sel0_r;
     end
-    k7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
-    if (csrbank1_half_sys8x_taps0_re) begin
-        k7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r;
+    main_k7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re;
+    if (builder_csrbank1_half_sys8x_taps0_re) begin
+        main_k7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r;
     end
-    k7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re;
-    if (csrbank1_wlevel_en0_re) begin
-        k7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r;
+    main_k7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re;
+    if (builder_csrbank1_wlevel_en0_re) begin
+        main_k7ddrphy_wlevel_en_storage <= builder_csrbank1_wlevel_en0_r;
     end
-    k7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re;
-    if (csrbank1_rdphase0_re) begin
-        k7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r;
+    main_k7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re;
+    if (builder_csrbank1_rdphase0_re) begin
+        main_k7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r;
     end
-    k7ddrphy_rdphase_re <= csrbank1_rdphase0_re;
-    if (csrbank1_wrphase0_re) begin
-        k7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r;
+    main_k7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re;
+    if (builder_csrbank1_wrphase0_re) begin
+        main_k7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r;
     end
-    k7ddrphy_wrphase_re <= csrbank1_wrphase0_re;
-    interface2_bank_bus_dat_r <= 1'd0;
-    if (csrbank2_sel) begin
-        case (interface2_bank_bus_adr[8:0])
+    main_k7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re;
+    builder_interface2_bank_bus_dat_r <= 1'd0;
+    if (builder_csrbank2_sel) begin
+        case (builder_interface2_bank_bus_adr[8:0])
             1'd0: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_control0_w;
             end
             1'd1: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_command0_w;
             end
             2'd2: begin
-                interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
+                builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w;
             end
             2'd3: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w;
             end
             3'd4: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w;
             end
             3'd5: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata1_w;
             end
             3'd6: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w;
             end
             3'd7: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata1_w;
             end
             4'd8: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata0_w;
             end
             4'd9: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w;
             end
             4'd10: begin
-                interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
+                builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w;
             end
             4'd11: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w;
             end
             4'd12: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w;
             end
             4'd13: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata1_w;
             end
             4'd14: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w;
             end
             4'd15: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata1_w;
             end
             5'd16: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata0_w;
             end
             5'd17: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w;
             end
             5'd18: begin
-                interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
+                builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w;
             end
             5'd19: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w;
             end
             5'd20: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w;
             end
             5'd21: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata1_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata1_w;
             end
             5'd22: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w;
             end
             5'd23: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata1_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata1_w;
             end
             5'd24: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata0_w;
             end
             5'd25: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w;
             end
             5'd26: begin
-                interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
+                builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w;
             end
             5'd27: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w;
             end
             5'd28: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w;
             end
             5'd29: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata1_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata1_w;
             end
             5'd30: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w;
             end
             5'd31: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata1_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata1_w;
             end
             6'd32: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata0_w;
             end
         endcase
     end
-    if (csrbank2_dfii_control0_re) begin
-        litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
+    if (builder_csrbank2_dfii_control0_re) begin
+        main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r;
     end
-    litedramcore_re <= csrbank2_dfii_control0_re;
-    if (csrbank2_dfii_pi0_command0_re) begin
-        litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
+    main_litedramcore_re <= builder_csrbank2_dfii_control0_re;
+    if (builder_csrbank2_dfii_pi0_command0_re) begin
+        main_litedramcore_phaseinjector0_command_storage[7:0] <= builder_csrbank2_dfii_pi0_command0_r;
     end
-    litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
-    if (csrbank2_dfii_pi0_address0_re) begin
-        litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r;
+    main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re;
+    if (builder_csrbank2_dfii_pi0_address0_re) begin
+        main_litedramcore_phaseinjector0_address_storage[14:0] <= builder_csrbank2_dfii_pi0_address0_r;
     end
-    litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
-    if (csrbank2_dfii_pi0_baddress0_re) begin
-        litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
+    main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re;
+    if (builder_csrbank2_dfii_pi0_baddress0_re) begin
+        main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r;
     end
-    litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
-    if (csrbank2_dfii_pi0_wrdata1_re) begin
-        litedramcore_phaseinjector0_wrdata_storage[63:32] <= csrbank2_dfii_pi0_wrdata1_r;
+    main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re;
+    if (builder_csrbank2_dfii_pi0_wrdata1_re) begin
+        main_litedramcore_phaseinjector0_wrdata_storage[63:32] <= builder_csrbank2_dfii_pi0_wrdata1_r;
     end
-    if (csrbank2_dfii_pi0_wrdata0_re) begin
-        litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
+    if (builder_csrbank2_dfii_pi0_wrdata0_re) begin
+        main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r;
     end
-    litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
-    litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata0_re;
-    if (csrbank2_dfii_pi1_command0_re) begin
-        litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
+    main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re;
+    main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata0_re;
+    if (builder_csrbank2_dfii_pi1_command0_re) begin
+        main_litedramcore_phaseinjector1_command_storage[7:0] <= builder_csrbank2_dfii_pi1_command0_r;
     end
-    litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
-    if (csrbank2_dfii_pi1_address0_re) begin
-        litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r;
+    main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re;
+    if (builder_csrbank2_dfii_pi1_address0_re) begin
+        main_litedramcore_phaseinjector1_address_storage[14:0] <= builder_csrbank2_dfii_pi1_address0_r;
     end
-    litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
-    if (csrbank2_dfii_pi1_baddress0_re) begin
-        litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
+    main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re;
+    if (builder_csrbank2_dfii_pi1_baddress0_re) begin
+        main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r;
     end
-    litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
-    if (csrbank2_dfii_pi1_wrdata1_re) begin
-        litedramcore_phaseinjector1_wrdata_storage[63:32] <= csrbank2_dfii_pi1_wrdata1_r;
+    main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re;
+    if (builder_csrbank2_dfii_pi1_wrdata1_re) begin
+        main_litedramcore_phaseinjector1_wrdata_storage[63:32] <= builder_csrbank2_dfii_pi1_wrdata1_r;
     end
-    if (csrbank2_dfii_pi1_wrdata0_re) begin
-        litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
+    if (builder_csrbank2_dfii_pi1_wrdata0_re) begin
+        main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r;
     end
-    litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
-    litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata0_re;
-    if (csrbank2_dfii_pi2_command0_re) begin
-        litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
+    main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re;
+    main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata0_re;
+    if (builder_csrbank2_dfii_pi2_command0_re) begin
+        main_litedramcore_phaseinjector2_command_storage[7:0] <= builder_csrbank2_dfii_pi2_command0_r;
     end
-    litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
-    if (csrbank2_dfii_pi2_address0_re) begin
-        litedramcore_phaseinjector2_address_storage[14:0] <= csrbank2_dfii_pi2_address0_r;
+    main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re;
+    if (builder_csrbank2_dfii_pi2_address0_re) begin
+        main_litedramcore_phaseinjector2_address_storage[14:0] <= builder_csrbank2_dfii_pi2_address0_r;
     end
-    litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
-    if (csrbank2_dfii_pi2_baddress0_re) begin
-        litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
+    main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re;
+    if (builder_csrbank2_dfii_pi2_baddress0_re) begin
+        main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r;
     end
-    litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
-    if (csrbank2_dfii_pi2_wrdata1_re) begin
-        litedramcore_phaseinjector2_wrdata_storage[63:32] <= csrbank2_dfii_pi2_wrdata1_r;
+    main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re;
+    if (builder_csrbank2_dfii_pi2_wrdata1_re) begin
+        main_litedramcore_phaseinjector2_wrdata_storage[63:32] <= builder_csrbank2_dfii_pi2_wrdata1_r;
     end
-    if (csrbank2_dfii_pi2_wrdata0_re) begin
-        litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
+    if (builder_csrbank2_dfii_pi2_wrdata0_re) begin
+        main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r;
     end
-    litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
-    litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata0_re;
-    if (csrbank2_dfii_pi3_command0_re) begin
-        litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
+    main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re;
+    main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata0_re;
+    if (builder_csrbank2_dfii_pi3_command0_re) begin
+        main_litedramcore_phaseinjector3_command_storage[7:0] <= builder_csrbank2_dfii_pi3_command0_r;
     end
-    litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
-    if (csrbank2_dfii_pi3_address0_re) begin
-        litedramcore_phaseinjector3_address_storage[14:0] <= csrbank2_dfii_pi3_address0_r;
+    main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re;
+    if (builder_csrbank2_dfii_pi3_address0_re) begin
+        main_litedramcore_phaseinjector3_address_storage[14:0] <= builder_csrbank2_dfii_pi3_address0_r;
     end
-    litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
-    if (csrbank2_dfii_pi3_baddress0_re) begin
-        litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
+    main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re;
+    if (builder_csrbank2_dfii_pi3_baddress0_re) begin
+        main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r;
     end
-    litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
-    if (csrbank2_dfii_pi3_wrdata1_re) begin
-        litedramcore_phaseinjector3_wrdata_storage[63:32] <= csrbank2_dfii_pi3_wrdata1_r;
+    main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re;
+    if (builder_csrbank2_dfii_pi3_wrdata1_re) begin
+        main_litedramcore_phaseinjector3_wrdata_storage[63:32] <= builder_csrbank2_dfii_pi3_wrdata1_r;
     end
-    if (csrbank2_dfii_pi3_wrdata0_re) begin
-        litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
+    if (builder_csrbank2_dfii_pi3_wrdata0_re) begin
+        main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r;
     end
-    litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
-    litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata0_re;
+    main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re;
+    main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata0_re;
     if (sys_rst) begin
-        k7ddrphy_rst_storage <= 1'd0;
-        k7ddrphy_rst_re <= 1'd0;
-        k7ddrphy_dly_sel_storage <= 4'd0;
-        k7ddrphy_dly_sel_re <= 1'd0;
-        k7ddrphy_half_sys8x_taps_storage <= 5'd8;
-        k7ddrphy_half_sys8x_taps_re <= 1'd0;
-        k7ddrphy_wlevel_en_storage <= 1'd0;
-        k7ddrphy_wlevel_en_re <= 1'd0;
-        k7ddrphy_rdphase_storage <= 2'd1;
-        k7ddrphy_rdphase_re <= 1'd0;
-        k7ddrphy_wrphase_storage <= 2'd2;
-        k7ddrphy_wrphase_re <= 1'd0;
-        k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
-        k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
-        k7ddrphy_bitslip0_value0 <= 3'd7;
-        k7ddrphy_bitslip1_value0 <= 3'd7;
-        k7ddrphy_bitslip2_value0 <= 3'd7;
-        k7ddrphy_bitslip3_value0 <= 3'd7;
-        k7ddrphy_bitslip0_value1 <= 3'd7;
-        k7ddrphy_bitslip1_value1 <= 3'd7;
-        k7ddrphy_bitslip2_value1 <= 3'd7;
-        k7ddrphy_bitslip3_value1 <= 3'd7;
-        k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
-        k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
-        k7ddrphy_bitslip0_value2 <= 3'd7;
-        k7ddrphy_bitslip0_value3 <= 3'd7;
-        k7ddrphy_bitslip1_value2 <= 3'd7;
-        k7ddrphy_bitslip1_value3 <= 3'd7;
-        k7ddrphy_bitslip2_value2 <= 3'd7;
-        k7ddrphy_bitslip2_value3 <= 3'd7;
-        k7ddrphy_bitslip3_value2 <= 3'd7;
-        k7ddrphy_bitslip3_value3 <= 3'd7;
-        k7ddrphy_bitslip4_value0 <= 3'd7;
-        k7ddrphy_bitslip4_value1 <= 3'd7;
-        k7ddrphy_bitslip5_value0 <= 3'd7;
-        k7ddrphy_bitslip5_value1 <= 3'd7;
-        k7ddrphy_bitslip6_value0 <= 3'd7;
-        k7ddrphy_bitslip6_value1 <= 3'd7;
-        k7ddrphy_bitslip7_value0 <= 3'd7;
-        k7ddrphy_bitslip7_value1 <= 3'd7;
-        k7ddrphy_bitslip8_value0 <= 3'd7;
-        k7ddrphy_bitslip8_value1 <= 3'd7;
-        k7ddrphy_bitslip9_value0 <= 3'd7;
-        k7ddrphy_bitslip9_value1 <= 3'd7;
-        k7ddrphy_bitslip10_value0 <= 3'd7;
-        k7ddrphy_bitslip10_value1 <= 3'd7;
-        k7ddrphy_bitslip11_value0 <= 3'd7;
-        k7ddrphy_bitslip11_value1 <= 3'd7;
-        k7ddrphy_bitslip12_value0 <= 3'd7;
-        k7ddrphy_bitslip12_value1 <= 3'd7;
-        k7ddrphy_bitslip13_value0 <= 3'd7;
-        k7ddrphy_bitslip13_value1 <= 3'd7;
-        k7ddrphy_bitslip14_value0 <= 3'd7;
-        k7ddrphy_bitslip14_value1 <= 3'd7;
-        k7ddrphy_bitslip15_value0 <= 3'd7;
-        k7ddrphy_bitslip15_value1 <= 3'd7;
-        k7ddrphy_bitslip16_value0 <= 3'd7;
-        k7ddrphy_bitslip16_value1 <= 3'd7;
-        k7ddrphy_bitslip17_value0 <= 3'd7;
-        k7ddrphy_bitslip17_value1 <= 3'd7;
-        k7ddrphy_bitslip18_value0 <= 3'd7;
-        k7ddrphy_bitslip18_value1 <= 3'd7;
-        k7ddrphy_bitslip19_value0 <= 3'd7;
-        k7ddrphy_bitslip19_value1 <= 3'd7;
-        k7ddrphy_bitslip20_value0 <= 3'd7;
-        k7ddrphy_bitslip20_value1 <= 3'd7;
-        k7ddrphy_bitslip21_value0 <= 3'd7;
-        k7ddrphy_bitslip21_value1 <= 3'd7;
-        k7ddrphy_bitslip22_value0 <= 3'd7;
-        k7ddrphy_bitslip22_value1 <= 3'd7;
-        k7ddrphy_bitslip23_value0 <= 3'd7;
-        k7ddrphy_bitslip23_value1 <= 3'd7;
-        k7ddrphy_bitslip24_value0 <= 3'd7;
-        k7ddrphy_bitslip24_value1 <= 3'd7;
-        k7ddrphy_bitslip25_value0 <= 3'd7;
-        k7ddrphy_bitslip25_value1 <= 3'd7;
-        k7ddrphy_bitslip26_value0 <= 3'd7;
-        k7ddrphy_bitslip26_value1 <= 3'd7;
-        k7ddrphy_bitslip27_value0 <= 3'd7;
-        k7ddrphy_bitslip27_value1 <= 3'd7;
-        k7ddrphy_bitslip28_value0 <= 3'd7;
-        k7ddrphy_bitslip28_value1 <= 3'd7;
-        k7ddrphy_bitslip29_value0 <= 3'd7;
-        k7ddrphy_bitslip29_value1 <= 3'd7;
-        k7ddrphy_bitslip30_value0 <= 3'd7;
-        k7ddrphy_bitslip30_value1 <= 3'd7;
-        k7ddrphy_bitslip31_value0 <= 3'd7;
-        k7ddrphy_bitslip31_value1 <= 3'd7;
-        k7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
-        k7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
-        k7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
-        k7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
-        k7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
-        k7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
-        k7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
-        k7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
-        k7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
-        k7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
-        k7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
-        litedramcore_storage <= 4'd1;
-        litedramcore_re <= 1'd0;
-        litedramcore_phaseinjector0_command_storage <= 6'd0;
-        litedramcore_phaseinjector0_command_re <= 1'd0;
-        litedramcore_phaseinjector0_address_re <= 1'd0;
-        litedramcore_phaseinjector0_baddress_re <= 1'd0;
-        litedramcore_phaseinjector0_wrdata_re <= 1'd0;
-        litedramcore_phaseinjector0_rddata_status <= 64'd0;
-        litedramcore_phaseinjector0_rddata_re <= 1'd0;
-        litedramcore_phaseinjector1_command_storage <= 6'd0;
-        litedramcore_phaseinjector1_command_re <= 1'd0;
-        litedramcore_phaseinjector1_address_re <= 1'd0;
-        litedramcore_phaseinjector1_baddress_re <= 1'd0;
-        litedramcore_phaseinjector1_wrdata_re <= 1'd0;
-        litedramcore_phaseinjector1_rddata_status <= 64'd0;
-        litedramcore_phaseinjector1_rddata_re <= 1'd0;
-        litedramcore_phaseinjector2_command_storage <= 6'd0;
-        litedramcore_phaseinjector2_command_re <= 1'd0;
-        litedramcore_phaseinjector2_address_re <= 1'd0;
-        litedramcore_phaseinjector2_baddress_re <= 1'd0;
-        litedramcore_phaseinjector2_wrdata_re <= 1'd0;
-        litedramcore_phaseinjector2_rddata_status <= 64'd0;
-        litedramcore_phaseinjector2_rddata_re <= 1'd0;
-        litedramcore_phaseinjector3_command_storage <= 6'd0;
-        litedramcore_phaseinjector3_command_re <= 1'd0;
-        litedramcore_phaseinjector3_address_re <= 1'd0;
-        litedramcore_phaseinjector3_baddress_re <= 1'd0;
-        litedramcore_phaseinjector3_wrdata_re <= 1'd0;
-        litedramcore_phaseinjector3_rddata_status <= 64'd0;
-        litedramcore_phaseinjector3_rddata_re <= 1'd0;
-        litedramcore_dfi_p0_address <= 15'd0;
-        litedramcore_dfi_p0_bank <= 3'd0;
-        litedramcore_dfi_p0_cas_n <= 1'd1;
-        litedramcore_dfi_p0_cs_n <= 1'd1;
-        litedramcore_dfi_p0_ras_n <= 1'd1;
-        litedramcore_dfi_p0_we_n <= 1'd1;
-        litedramcore_dfi_p0_wrdata_en <= 1'd0;
-        litedramcore_dfi_p0_rddata_en <= 1'd0;
-        litedramcore_dfi_p1_address <= 15'd0;
-        litedramcore_dfi_p1_bank <= 3'd0;
-        litedramcore_dfi_p1_cas_n <= 1'd1;
-        litedramcore_dfi_p1_cs_n <= 1'd1;
-        litedramcore_dfi_p1_ras_n <= 1'd1;
-        litedramcore_dfi_p1_we_n <= 1'd1;
-        litedramcore_dfi_p1_wrdata_en <= 1'd0;
-        litedramcore_dfi_p1_rddata_en <= 1'd0;
-        litedramcore_dfi_p2_address <= 15'd0;
-        litedramcore_dfi_p2_bank <= 3'd0;
-        litedramcore_dfi_p2_cas_n <= 1'd1;
-        litedramcore_dfi_p2_cs_n <= 1'd1;
-        litedramcore_dfi_p2_ras_n <= 1'd1;
-        litedramcore_dfi_p2_we_n <= 1'd1;
-        litedramcore_dfi_p2_wrdata_en <= 1'd0;
-        litedramcore_dfi_p2_rddata_en <= 1'd0;
-        litedramcore_dfi_p3_address <= 15'd0;
-        litedramcore_dfi_p3_bank <= 3'd0;
-        litedramcore_dfi_p3_cas_n <= 1'd1;
-        litedramcore_dfi_p3_cs_n <= 1'd1;
-        litedramcore_dfi_p3_ras_n <= 1'd1;
-        litedramcore_dfi_p3_we_n <= 1'd1;
-        litedramcore_dfi_p3_wrdata_en <= 1'd0;
-        litedramcore_dfi_p3_rddata_en <= 1'd0;
-        litedramcore_cmd_payload_a <= 15'd0;
-        litedramcore_cmd_payload_ba <= 3'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd0;
-        litedramcore_cmd_payload_we <= 1'd0;
-        litedramcore_timer_count1 <= 10'd781;
-        litedramcore_postponer_req_o <= 1'd0;
-        litedramcore_postponer_count <= 1'd0;
-        litedramcore_sequencer_done1 <= 1'd0;
-        litedramcore_sequencer_counter <= 6'd0;
-        litedramcore_sequencer_count <= 1'd0;
-        litedramcore_zqcs_timer_count1 <= 27'd99999999;
-        litedramcore_zqcs_executer_done <= 1'd0;
-        litedramcore_zqcs_executer_counter <= 5'd0;
-        litedramcore_bankmachine0_level <= 5'd0;
-        litedramcore_bankmachine0_produce <= 4'd0;
-        litedramcore_bankmachine0_consume <= 4'd0;
-        litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 22'd0;
-        litedramcore_bankmachine0_row <= 15'd0;
-        litedramcore_bankmachine0_row_opened <= 1'd0;
-        litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine0_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine0_trccon_ready <= 1'd0;
-        litedramcore_bankmachine0_trccon_count <= 3'd0;
-        litedramcore_bankmachine0_trascon_ready <= 1'd0;
-        litedramcore_bankmachine0_trascon_count <= 3'd0;
-        litedramcore_bankmachine1_level <= 5'd0;
-        litedramcore_bankmachine1_produce <= 4'd0;
-        litedramcore_bankmachine1_consume <= 4'd0;
-        litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 22'd0;
-        litedramcore_bankmachine1_row <= 15'd0;
-        litedramcore_bankmachine1_row_opened <= 1'd0;
-        litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine1_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine1_trccon_ready <= 1'd0;
-        litedramcore_bankmachine1_trccon_count <= 3'd0;
-        litedramcore_bankmachine1_trascon_ready <= 1'd0;
-        litedramcore_bankmachine1_trascon_count <= 3'd0;
-        litedramcore_bankmachine2_level <= 5'd0;
-        litedramcore_bankmachine2_produce <= 4'd0;
-        litedramcore_bankmachine2_consume <= 4'd0;
-        litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 22'd0;
-        litedramcore_bankmachine2_row <= 15'd0;
-        litedramcore_bankmachine2_row_opened <= 1'd0;
-        litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine2_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine2_trccon_ready <= 1'd0;
-        litedramcore_bankmachine2_trccon_count <= 3'd0;
-        litedramcore_bankmachine2_trascon_ready <= 1'd0;
-        litedramcore_bankmachine2_trascon_count <= 3'd0;
-        litedramcore_bankmachine3_level <= 5'd0;
-        litedramcore_bankmachine3_produce <= 4'd0;
-        litedramcore_bankmachine3_consume <= 4'd0;
-        litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 22'd0;
-        litedramcore_bankmachine3_row <= 15'd0;
-        litedramcore_bankmachine3_row_opened <= 1'd0;
-        litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine3_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine3_trccon_ready <= 1'd0;
-        litedramcore_bankmachine3_trccon_count <= 3'd0;
-        litedramcore_bankmachine3_trascon_ready <= 1'd0;
-        litedramcore_bankmachine3_trascon_count <= 3'd0;
-        litedramcore_bankmachine4_level <= 5'd0;
-        litedramcore_bankmachine4_produce <= 4'd0;
-        litedramcore_bankmachine4_consume <= 4'd0;
-        litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 22'd0;
-        litedramcore_bankmachine4_row <= 15'd0;
-        litedramcore_bankmachine4_row_opened <= 1'd0;
-        litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine4_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine4_trccon_ready <= 1'd0;
-        litedramcore_bankmachine4_trccon_count <= 3'd0;
-        litedramcore_bankmachine4_trascon_ready <= 1'd0;
-        litedramcore_bankmachine4_trascon_count <= 3'd0;
-        litedramcore_bankmachine5_level <= 5'd0;
-        litedramcore_bankmachine5_produce <= 4'd0;
-        litedramcore_bankmachine5_consume <= 4'd0;
-        litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 22'd0;
-        litedramcore_bankmachine5_row <= 15'd0;
-        litedramcore_bankmachine5_row_opened <= 1'd0;
-        litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine5_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine5_trccon_ready <= 1'd0;
-        litedramcore_bankmachine5_trccon_count <= 3'd0;
-        litedramcore_bankmachine5_trascon_ready <= 1'd0;
-        litedramcore_bankmachine5_trascon_count <= 3'd0;
-        litedramcore_bankmachine6_level <= 5'd0;
-        litedramcore_bankmachine6_produce <= 4'd0;
-        litedramcore_bankmachine6_consume <= 4'd0;
-        litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 22'd0;
-        litedramcore_bankmachine6_row <= 15'd0;
-        litedramcore_bankmachine6_row_opened <= 1'd0;
-        litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine6_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine6_trccon_ready <= 1'd0;
-        litedramcore_bankmachine6_trccon_count <= 3'd0;
-        litedramcore_bankmachine6_trascon_ready <= 1'd0;
-        litedramcore_bankmachine6_trascon_count <= 3'd0;
-        litedramcore_bankmachine7_level <= 5'd0;
-        litedramcore_bankmachine7_produce <= 4'd0;
-        litedramcore_bankmachine7_consume <= 4'd0;
-        litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 22'd0;
-        litedramcore_bankmachine7_row <= 15'd0;
-        litedramcore_bankmachine7_row_opened <= 1'd0;
-        litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine7_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine7_trccon_ready <= 1'd0;
-        litedramcore_bankmachine7_trccon_count <= 3'd0;
-        litedramcore_bankmachine7_trascon_ready <= 1'd0;
-        litedramcore_bankmachine7_trascon_count <= 3'd0;
-        litedramcore_choose_cmd_grant <= 3'd0;
-        litedramcore_choose_req_grant <= 3'd0;
-        litedramcore_trrdcon_ready <= 1'd0;
-        litedramcore_trrdcon_count <= 1'd0;
-        litedramcore_tfawcon_ready <= 1'd1;
-        litedramcore_tfawcon_window <= 5'd0;
-        litedramcore_tccdcon_ready <= 1'd0;
-        litedramcore_tccdcon_count <= 1'd0;
-        litedramcore_twtrcon_ready <= 1'd0;
-        litedramcore_twtrcon_count <= 3'd0;
-        litedramcore_time0 <= 5'd0;
-        litedramcore_time1 <= 4'd0;
-        init_done_storage <= 1'd0;
-        init_done_re <= 1'd0;
-        init_error_storage <= 1'd0;
-        init_error_re <= 1'd0;
-        litedramcore_we <= 1'd0;
-        litedramcore_refresher_state <= 2'd0;
-        litedramcore_bankmachine0_state <= 4'd0;
-        litedramcore_bankmachine1_state <= 4'd0;
-        litedramcore_bankmachine2_state <= 4'd0;
-        litedramcore_bankmachine3_state <= 4'd0;
-        litedramcore_bankmachine4_state <= 4'd0;
-        litedramcore_bankmachine5_state <= 4'd0;
-        litedramcore_bankmachine6_state <= 4'd0;
-        litedramcore_bankmachine7_state <= 4'd0;
-        litedramcore_multiplexer_state <= 4'd0;
-        litedramcore_new_master_wdata_ready0 <= 1'd0;
-        litedramcore_new_master_wdata_ready1 <= 1'd0;
-        litedramcore_new_master_rdata_valid0 <= 1'd0;
-        litedramcore_new_master_rdata_valid1 <= 1'd0;
-        litedramcore_new_master_rdata_valid2 <= 1'd0;
-        litedramcore_new_master_rdata_valid3 <= 1'd0;
-        litedramcore_new_master_rdata_valid4 <= 1'd0;
-        litedramcore_new_master_rdata_valid5 <= 1'd0;
-        litedramcore_new_master_rdata_valid6 <= 1'd0;
-        litedramcore_new_master_rdata_valid7 <= 1'd0;
-        litedramcore_new_master_rdata_valid8 <= 1'd0;
-        litedramcore_state <= 2'd0;
+        main_k7ddrphy_rst_storage <= 1'd0;
+        main_k7ddrphy_rst_re <= 1'd0;
+        main_k7ddrphy_dly_sel_storage <= 4'd0;
+        main_k7ddrphy_dly_sel_re <= 1'd0;
+        main_k7ddrphy_half_sys8x_taps_storage <= 5'd8;
+        main_k7ddrphy_half_sys8x_taps_re <= 1'd0;
+        main_k7ddrphy_wlevel_en_storage <= 1'd0;
+        main_k7ddrphy_wlevel_en_re <= 1'd0;
+        main_k7ddrphy_rdphase_storage <= 2'd1;
+        main_k7ddrphy_rdphase_re <= 1'd0;
+        main_k7ddrphy_wrphase_storage <= 2'd2;
+        main_k7ddrphy_wrphase_re <= 1'd0;
+        main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+        main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+        main_k7ddrphy_bitslip0_value0 <= 3'd7;
+        main_k7ddrphy_bitslip1_value0 <= 3'd7;
+        main_k7ddrphy_bitslip2_value0 <= 3'd7;
+        main_k7ddrphy_bitslip3_value0 <= 3'd7;
+        main_k7ddrphy_bitslip0_value1 <= 3'd7;
+        main_k7ddrphy_bitslip1_value1 <= 3'd7;
+        main_k7ddrphy_bitslip2_value1 <= 3'd7;
+        main_k7ddrphy_bitslip3_value1 <= 3'd7;
+        main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+        main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+        main_k7ddrphy_bitslip0_value2 <= 3'd7;
+        main_k7ddrphy_bitslip0_value3 <= 3'd7;
+        main_k7ddrphy_bitslip1_value2 <= 3'd7;
+        main_k7ddrphy_bitslip1_value3 <= 3'd7;
+        main_k7ddrphy_bitslip2_value2 <= 3'd7;
+        main_k7ddrphy_bitslip2_value3 <= 3'd7;
+        main_k7ddrphy_bitslip3_value2 <= 3'd7;
+        main_k7ddrphy_bitslip3_value3 <= 3'd7;
+        main_k7ddrphy_bitslip4_value0 <= 3'd7;
+        main_k7ddrphy_bitslip4_value1 <= 3'd7;
+        main_k7ddrphy_bitslip5_value0 <= 3'd7;
+        main_k7ddrphy_bitslip5_value1 <= 3'd7;
+        main_k7ddrphy_bitslip6_value0 <= 3'd7;
+        main_k7ddrphy_bitslip6_value1 <= 3'd7;
+        main_k7ddrphy_bitslip7_value0 <= 3'd7;
+        main_k7ddrphy_bitslip7_value1 <= 3'd7;
+        main_k7ddrphy_bitslip8_value0 <= 3'd7;
+        main_k7ddrphy_bitslip8_value1 <= 3'd7;
+        main_k7ddrphy_bitslip9_value0 <= 3'd7;
+        main_k7ddrphy_bitslip9_value1 <= 3'd7;
+        main_k7ddrphy_bitslip10_value0 <= 3'd7;
+        main_k7ddrphy_bitslip10_value1 <= 3'd7;
+        main_k7ddrphy_bitslip11_value0 <= 3'd7;
+        main_k7ddrphy_bitslip11_value1 <= 3'd7;
+        main_k7ddrphy_bitslip12_value0 <= 3'd7;
+        main_k7ddrphy_bitslip12_value1 <= 3'd7;
+        main_k7ddrphy_bitslip13_value0 <= 3'd7;
+        main_k7ddrphy_bitslip13_value1 <= 3'd7;
+        main_k7ddrphy_bitslip14_value0 <= 3'd7;
+        main_k7ddrphy_bitslip14_value1 <= 3'd7;
+        main_k7ddrphy_bitslip15_value0 <= 3'd7;
+        main_k7ddrphy_bitslip15_value1 <= 3'd7;
+        main_k7ddrphy_bitslip16_value0 <= 3'd7;
+        main_k7ddrphy_bitslip16_value1 <= 3'd7;
+        main_k7ddrphy_bitslip17_value0 <= 3'd7;
+        main_k7ddrphy_bitslip17_value1 <= 3'd7;
+        main_k7ddrphy_bitslip18_value0 <= 3'd7;
+        main_k7ddrphy_bitslip18_value1 <= 3'd7;
+        main_k7ddrphy_bitslip19_value0 <= 3'd7;
+        main_k7ddrphy_bitslip19_value1 <= 3'd7;
+        main_k7ddrphy_bitslip20_value0 <= 3'd7;
+        main_k7ddrphy_bitslip20_value1 <= 3'd7;
+        main_k7ddrphy_bitslip21_value0 <= 3'd7;
+        main_k7ddrphy_bitslip21_value1 <= 3'd7;
+        main_k7ddrphy_bitslip22_value0 <= 3'd7;
+        main_k7ddrphy_bitslip22_value1 <= 3'd7;
+        main_k7ddrphy_bitslip23_value0 <= 3'd7;
+        main_k7ddrphy_bitslip23_value1 <= 3'd7;
+        main_k7ddrphy_bitslip24_value0 <= 3'd7;
+        main_k7ddrphy_bitslip24_value1 <= 3'd7;
+        main_k7ddrphy_bitslip25_value0 <= 3'd7;
+        main_k7ddrphy_bitslip25_value1 <= 3'd7;
+        main_k7ddrphy_bitslip26_value0 <= 3'd7;
+        main_k7ddrphy_bitslip26_value1 <= 3'd7;
+        main_k7ddrphy_bitslip27_value0 <= 3'd7;
+        main_k7ddrphy_bitslip27_value1 <= 3'd7;
+        main_k7ddrphy_bitslip28_value0 <= 3'd7;
+        main_k7ddrphy_bitslip28_value1 <= 3'd7;
+        main_k7ddrphy_bitslip29_value0 <= 3'd7;
+        main_k7ddrphy_bitslip29_value1 <= 3'd7;
+        main_k7ddrphy_bitslip30_value0 <= 3'd7;
+        main_k7ddrphy_bitslip30_value1 <= 3'd7;
+        main_k7ddrphy_bitslip31_value0 <= 3'd7;
+        main_k7ddrphy_bitslip31_value1 <= 3'd7;
+        main_k7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
+        main_k7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
+        main_k7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
+        main_k7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
+        main_k7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
+        main_k7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
+        main_k7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
+        main_k7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
+        main_k7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
+        main_k7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
+        main_k7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
+        main_litedramcore_storage <= 4'd1;
+        main_litedramcore_re <= 1'd0;
+        main_litedramcore_phaseinjector0_command_storage <= 8'd0;
+        main_litedramcore_phaseinjector0_command_re <= 1'd0;
+        main_litedramcore_phaseinjector0_address_re <= 1'd0;
+        main_litedramcore_phaseinjector0_baddress_re <= 1'd0;
+        main_litedramcore_phaseinjector0_wrdata_re <= 1'd0;
+        main_litedramcore_phaseinjector0_rddata_status <= 64'd0;
+        main_litedramcore_phaseinjector0_rddata_re <= 1'd0;
+        main_litedramcore_phaseinjector1_command_storage <= 8'd0;
+        main_litedramcore_phaseinjector1_command_re <= 1'd0;
+        main_litedramcore_phaseinjector1_address_re <= 1'd0;
+        main_litedramcore_phaseinjector1_baddress_re <= 1'd0;
+        main_litedramcore_phaseinjector1_wrdata_re <= 1'd0;
+        main_litedramcore_phaseinjector1_rddata_status <= 64'd0;
+        main_litedramcore_phaseinjector1_rddata_re <= 1'd0;
+        main_litedramcore_phaseinjector2_command_storage <= 8'd0;
+        main_litedramcore_phaseinjector2_command_re <= 1'd0;
+        main_litedramcore_phaseinjector2_address_re <= 1'd0;
+        main_litedramcore_phaseinjector2_baddress_re <= 1'd0;
+        main_litedramcore_phaseinjector2_wrdata_re <= 1'd0;
+        main_litedramcore_phaseinjector2_rddata_status <= 64'd0;
+        main_litedramcore_phaseinjector2_rddata_re <= 1'd0;
+        main_litedramcore_phaseinjector3_command_storage <= 8'd0;
+        main_litedramcore_phaseinjector3_command_re <= 1'd0;
+        main_litedramcore_phaseinjector3_address_re <= 1'd0;
+        main_litedramcore_phaseinjector3_baddress_re <= 1'd0;
+        main_litedramcore_phaseinjector3_wrdata_re <= 1'd0;
+        main_litedramcore_phaseinjector3_rddata_status <= 64'd0;
+        main_litedramcore_phaseinjector3_rddata_re <= 1'd0;
+        main_litedramcore_dfi_p0_address <= 15'd0;
+        main_litedramcore_dfi_p0_bank <= 3'd0;
+        main_litedramcore_dfi_p0_cas_n <= 1'd1;
+        main_litedramcore_dfi_p0_cs_n <= 1'd1;
+        main_litedramcore_dfi_p0_ras_n <= 1'd1;
+        main_litedramcore_dfi_p0_we_n <= 1'd1;
+        main_litedramcore_dfi_p0_wrdata_en <= 1'd0;
+        main_litedramcore_dfi_p0_rddata_en <= 1'd0;
+        main_litedramcore_dfi_p1_address <= 15'd0;
+        main_litedramcore_dfi_p1_bank <= 3'd0;
+        main_litedramcore_dfi_p1_cas_n <= 1'd1;
+        main_litedramcore_dfi_p1_cs_n <= 1'd1;
+        main_litedramcore_dfi_p1_ras_n <= 1'd1;
+        main_litedramcore_dfi_p1_we_n <= 1'd1;
+        main_litedramcore_dfi_p1_wrdata_en <= 1'd0;
+        main_litedramcore_dfi_p1_rddata_en <= 1'd0;
+        main_litedramcore_dfi_p2_address <= 15'd0;
+        main_litedramcore_dfi_p2_bank <= 3'd0;
+        main_litedramcore_dfi_p2_cas_n <= 1'd1;
+        main_litedramcore_dfi_p2_cs_n <= 1'd1;
+        main_litedramcore_dfi_p2_ras_n <= 1'd1;
+        main_litedramcore_dfi_p2_we_n <= 1'd1;
+        main_litedramcore_dfi_p2_wrdata_en <= 1'd0;
+        main_litedramcore_dfi_p2_rddata_en <= 1'd0;
+        main_litedramcore_dfi_p3_address <= 15'd0;
+        main_litedramcore_dfi_p3_bank <= 3'd0;
+        main_litedramcore_dfi_p3_cas_n <= 1'd1;
+        main_litedramcore_dfi_p3_cs_n <= 1'd1;
+        main_litedramcore_dfi_p3_ras_n <= 1'd1;
+        main_litedramcore_dfi_p3_we_n <= 1'd1;
+        main_litedramcore_dfi_p3_wrdata_en <= 1'd0;
+        main_litedramcore_dfi_p3_rddata_en <= 1'd0;
+        main_litedramcore_cmd_payload_a <= 15'd0;
+        main_litedramcore_cmd_payload_ba <= 3'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd0;
+        main_litedramcore_cmd_payload_we <= 1'd0;
+        main_litedramcore_timer_count1 <= 10'd781;
+        main_litedramcore_postponer_req_o <= 1'd0;
+        main_litedramcore_postponer_count <= 1'd0;
+        main_litedramcore_sequencer_done1 <= 1'd0;
+        main_litedramcore_sequencer_trigger <= 6'd0;
+        main_litedramcore_sequencer_count <= 1'd0;
+        main_litedramcore_zqcs_timer_count1 <= 27'd99999999;
+        main_litedramcore_zqcs_executer_done <= 1'd0;
+        main_litedramcore_zqcs_executer_trigger <= 5'd0;
+        main_litedramcore_bankmachine0_level <= 5'd0;
+        main_litedramcore_bankmachine0_produce <= 4'd0;
+        main_litedramcore_bankmachine0_consume <= 4'd0;
+        main_litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 22'd0;
+        main_litedramcore_bankmachine0_row <= 15'd0;
+        main_litedramcore_bankmachine0_row_opened <= 1'd0;
+        main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine0_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine0_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine0_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine0_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine0_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine1_level <= 5'd0;
+        main_litedramcore_bankmachine1_produce <= 4'd0;
+        main_litedramcore_bankmachine1_consume <= 4'd0;
+        main_litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 22'd0;
+        main_litedramcore_bankmachine1_row <= 15'd0;
+        main_litedramcore_bankmachine1_row_opened <= 1'd0;
+        main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine1_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine1_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine1_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine1_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine1_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine2_level <= 5'd0;
+        main_litedramcore_bankmachine2_produce <= 4'd0;
+        main_litedramcore_bankmachine2_consume <= 4'd0;
+        main_litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 22'd0;
+        main_litedramcore_bankmachine2_row <= 15'd0;
+        main_litedramcore_bankmachine2_row_opened <= 1'd0;
+        main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine2_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine2_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine2_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine2_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine2_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine3_level <= 5'd0;
+        main_litedramcore_bankmachine3_produce <= 4'd0;
+        main_litedramcore_bankmachine3_consume <= 4'd0;
+        main_litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 22'd0;
+        main_litedramcore_bankmachine3_row <= 15'd0;
+        main_litedramcore_bankmachine3_row_opened <= 1'd0;
+        main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine3_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine3_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine3_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine3_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine3_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine4_level <= 5'd0;
+        main_litedramcore_bankmachine4_produce <= 4'd0;
+        main_litedramcore_bankmachine4_consume <= 4'd0;
+        main_litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 22'd0;
+        main_litedramcore_bankmachine4_row <= 15'd0;
+        main_litedramcore_bankmachine4_row_opened <= 1'd0;
+        main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine4_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine4_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine4_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine4_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine4_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine5_level <= 5'd0;
+        main_litedramcore_bankmachine5_produce <= 4'd0;
+        main_litedramcore_bankmachine5_consume <= 4'd0;
+        main_litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 22'd0;
+        main_litedramcore_bankmachine5_row <= 15'd0;
+        main_litedramcore_bankmachine5_row_opened <= 1'd0;
+        main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine5_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine5_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine5_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine5_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine5_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine6_level <= 5'd0;
+        main_litedramcore_bankmachine6_produce <= 4'd0;
+        main_litedramcore_bankmachine6_consume <= 4'd0;
+        main_litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 22'd0;
+        main_litedramcore_bankmachine6_row <= 15'd0;
+        main_litedramcore_bankmachine6_row_opened <= 1'd0;
+        main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine6_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine6_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine6_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine6_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine6_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine7_level <= 5'd0;
+        main_litedramcore_bankmachine7_produce <= 4'd0;
+        main_litedramcore_bankmachine7_consume <= 4'd0;
+        main_litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 22'd0;
+        main_litedramcore_bankmachine7_row <= 15'd0;
+        main_litedramcore_bankmachine7_row_opened <= 1'd0;
+        main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine7_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine7_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine7_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine7_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine7_trascon_count <= 3'd0;
+        main_litedramcore_choose_cmd_grant <= 3'd0;
+        main_litedramcore_choose_req_grant <= 3'd0;
+        main_litedramcore_trrdcon_ready <= 1'd0;
+        main_litedramcore_trrdcon_count <= 1'd0;
+        main_litedramcore_tfawcon_ready <= 1'd1;
+        main_litedramcore_tfawcon_window <= 5'd0;
+        main_litedramcore_tccdcon_ready <= 1'd0;
+        main_litedramcore_tccdcon_count <= 1'd0;
+        main_litedramcore_twtrcon_ready <= 1'd0;
+        main_litedramcore_twtrcon_count <= 3'd0;
+        main_litedramcore_time0 <= 5'd0;
+        main_litedramcore_time1 <= 4'd0;
+        main_init_done_storage <= 1'd0;
+        main_init_done_re <= 1'd0;
+        main_init_error_storage <= 1'd0;
+        main_init_error_re <= 1'd0;
+        builder_interface1_we <= 1'd0;
+        builder_refresher_state <= 2'd0;
+        builder_bankmachine0_state <= 4'd0;
+        builder_bankmachine1_state <= 4'd0;
+        builder_bankmachine2_state <= 4'd0;
+        builder_bankmachine3_state <= 4'd0;
+        builder_bankmachine4_state <= 4'd0;
+        builder_bankmachine5_state <= 4'd0;
+        builder_bankmachine6_state <= 4'd0;
+        builder_bankmachine7_state <= 4'd0;
+        builder_multiplexer_state <= 4'd0;
+        builder_new_master_wdata_ready0 <= 1'd0;
+        builder_new_master_wdata_ready1 <= 1'd0;
+        builder_new_master_rdata_valid0 <= 1'd0;
+        builder_new_master_rdata_valid1 <= 1'd0;
+        builder_new_master_rdata_valid2 <= 1'd0;
+        builder_new_master_rdata_valid3 <= 1'd0;
+        builder_new_master_rdata_valid4 <= 1'd0;
+        builder_new_master_rdata_valid5 <= 1'd0;
+        builder_new_master_rdata_valid6 <= 1'd0;
+        builder_new_master_rdata_valid7 <= 1'd0;
+        builder_new_master_rdata_valid8 <= 1'd0;
+        builder_state <= 2'd0;
     end
 end
 
@@ -16133,4513 +16721,6199 @@ end
 // Specialized Logic
 //------------------------------------------------------------------------------
 
+//------------------------------------------------------------------------------
+// Instance BUFG of BUFG Module.
+//------------------------------------------------------------------------------
 BUFG BUFG(
-	.I(clkout0),
-	.O(clkout_buf0)
+	// Inputs.
+	.I (main_clkout0),
+
+	// Outputs.
+	.O (main_clkout_buf0)
 );
 
+//------------------------------------------------------------------------------
+// Instance BUFG_1 of BUFG Module.
+//------------------------------------------------------------------------------
 BUFG BUFG_1(
-	.I(clkout1),
-	.O(clkout_buf1)
+	// Inputs.
+	.I (main_clkout1),
+
+	// Outputs.
+	.O (main_clkout_buf1)
 );
 
+//------------------------------------------------------------------------------
+// Instance BUFG_2 of BUFG Module.
+//------------------------------------------------------------------------------
 BUFG BUFG_2(
-	.I(clkout2),
-	.O(clkout_buf2)
+	// Inputs.
+	.I (main_clkout2),
+
+	// Outputs.
+	.O (main_clkout_buf2)
 );
 
+//------------------------------------------------------------------------------
+// Instance BUFG_3 of BUFG Module.
+//------------------------------------------------------------------------------
 BUFG BUFG_3(
-	.I(clkout3),
-	.O(clkout_buf3)
+	// Inputs.
+	.I (main_clkout3),
+
+	// Outputs.
+	.O (main_clkout_buf3)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYCTRL of IDELAYCTRL Module.
+//------------------------------------------------------------------------------
 IDELAYCTRL IDELAYCTRL(
-	.REFCLK(iodelay_clk),
-	.RST(ic_reset)
+	// Inputs.
+	.REFCLK (iodelay_clk),
+	.RST    (main_ic_reset)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(1'd0),
-	.D2(1'd1),
-	.D3(1'd0),
-	.D4(1'd1),
-	.D5(1'd0),
-	.D6(1'd1),
-	.D7(1'd0),
-	.D8(1'd1),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_sd_clk_se_nodelay)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (1'd0),
+	.D2     (1'd1),
+	.D3     (1'd0),
+	.D4     (1'd1),
+	.D5     (1'd0),
+	.D6     (1'd1),
+	.D7     (1'd0),
+	.D8     (1'd1),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_sd_clk_se_nodelay)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_sd_clk_se_delayed),
-	.ODATAIN(k7ddrphy_sd_clk_se_nodelay)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_sd_clk_se_delayed),
+	.ODATAIN  (main_k7ddrphy_sd_clk_se_nodelay)
 );
 
+//------------------------------------------------------------------------------
+// Instance OBUFDS of OBUFDS Module.
+//------------------------------------------------------------------------------
 OBUFDS OBUFDS(
-	.I(k7ddrphy_sd_clk_se_delayed),
-	.O(ddram_clk_p),
-	.OB(ddram_clk_n)
+	// Inputs.
+	.I  (main_k7ddrphy_sd_clk_se_delayed),
+
+	// Outputs.
+	.O  (ddram_clk_p),
+	.OB (ddram_clk_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_1 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_1 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_dfi_p0_reset_n),
-	.D2(k7ddrphy_dfi_p0_reset_n),
-	.D3(k7ddrphy_dfi_p1_reset_n),
-	.D4(k7ddrphy_dfi_p1_reset_n),
-	.D5(k7ddrphy_dfi_p2_reset_n),
-	.D6(k7ddrphy_dfi_p2_reset_n),
-	.D7(k7ddrphy_dfi_p3_reset_n),
-	.D8(k7ddrphy_dfi_p3_reset_n),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_oq0)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_dfi_p0_reset_n),
+	.D2     (main_k7ddrphy_dfi_p0_reset_n),
+	.D3     (main_k7ddrphy_dfi_p1_reset_n),
+	.D4     (main_k7ddrphy_dfi_p1_reset_n),
+	.D5     (main_k7ddrphy_dfi_p2_reset_n),
+	.D6     (main_k7ddrphy_dfi_p2_reset_n),
+	.D7     (main_k7ddrphy_dfi_p3_reset_n),
+	.D8     (main_k7ddrphy_dfi_p3_reset_n),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_oq0)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_1 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_1 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_reset_n),
-	.ODATAIN(k7ddrphy_oq0)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_reset_n),
+	.ODATAIN  (main_k7ddrphy_oq0)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_2 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_2 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_dfi_p0_cs_n),
-	.D2(k7ddrphy_dfi_p0_cs_n),
-	.D3(k7ddrphy_dfi_p1_cs_n),
-	.D4(k7ddrphy_dfi_p1_cs_n),
-	.D5(k7ddrphy_dfi_p2_cs_n),
-	.D6(k7ddrphy_dfi_p2_cs_n),
-	.D7(k7ddrphy_dfi_p3_cs_n),
-	.D8(k7ddrphy_dfi_p3_cs_n),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_oq1)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_dfi_p0_cs_n),
+	.D2     (main_k7ddrphy_dfi_p0_cs_n),
+	.D3     (main_k7ddrphy_dfi_p1_cs_n),
+	.D4     (main_k7ddrphy_dfi_p1_cs_n),
+	.D5     (main_k7ddrphy_dfi_p2_cs_n),
+	.D6     (main_k7ddrphy_dfi_p2_cs_n),
+	.D7     (main_k7ddrphy_dfi_p3_cs_n),
+	.D8     (main_k7ddrphy_dfi_p3_cs_n),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_oq1)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_2 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_2 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_cs_n),
-	.ODATAIN(k7ddrphy_oq1)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_cs_n),
+	.ODATAIN  (main_k7ddrphy_oq1)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_3 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_3 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_dfi_p0_address[0]),
-	.D2(k7ddrphy_dfi_p0_address[0]),
-	.D3(k7ddrphy_dfi_p1_address[0]),
-	.D4(k7ddrphy_dfi_p1_address[0]),
-	.D5(k7ddrphy_dfi_p2_address[0]),
-	.D6(k7ddrphy_dfi_p2_address[0]),
-	.D7(k7ddrphy_dfi_p3_address[0]),
-	.D8(k7ddrphy_dfi_p3_address[0]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_oq2)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_dfi_p0_address[0]),
+	.D2     (main_k7ddrphy_dfi_p0_address[0]),
+	.D3     (main_k7ddrphy_dfi_p1_address[0]),
+	.D4     (main_k7ddrphy_dfi_p1_address[0]),
+	.D5     (main_k7ddrphy_dfi_p2_address[0]),
+	.D6     (main_k7ddrphy_dfi_p2_address[0]),
+	.D7     (main_k7ddrphy_dfi_p3_address[0]),
+	.D8     (main_k7ddrphy_dfi_p3_address[0]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_oq2)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_3 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_3 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_a[0]),
-	.ODATAIN(k7ddrphy_oq2)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_a[0]),
+	.ODATAIN  (main_k7ddrphy_oq2)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_4 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_4 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_dfi_p0_address[1]),
-	.D2(k7ddrphy_dfi_p0_address[1]),
-	.D3(k7ddrphy_dfi_p1_address[1]),
-	.D4(k7ddrphy_dfi_p1_address[1]),
-	.D5(k7ddrphy_dfi_p2_address[1]),
-	.D6(k7ddrphy_dfi_p2_address[1]),
-	.D7(k7ddrphy_dfi_p3_address[1]),
-	.D8(k7ddrphy_dfi_p3_address[1]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_oq3)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_dfi_p0_address[1]),
+	.D2     (main_k7ddrphy_dfi_p0_address[1]),
+	.D3     (main_k7ddrphy_dfi_p1_address[1]),
+	.D4     (main_k7ddrphy_dfi_p1_address[1]),
+	.D5     (main_k7ddrphy_dfi_p2_address[1]),
+	.D6     (main_k7ddrphy_dfi_p2_address[1]),
+	.D7     (main_k7ddrphy_dfi_p3_address[1]),
+	.D8     (main_k7ddrphy_dfi_p3_address[1]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_oq3)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_4 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_4 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_a[1]),
-	.ODATAIN(k7ddrphy_oq3)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_a[1]),
+	.ODATAIN  (main_k7ddrphy_oq3)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_5 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_5 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_dfi_p0_address[2]),
-	.D2(k7ddrphy_dfi_p0_address[2]),
-	.D3(k7ddrphy_dfi_p1_address[2]),
-	.D4(k7ddrphy_dfi_p1_address[2]),
-	.D5(k7ddrphy_dfi_p2_address[2]),
-	.D6(k7ddrphy_dfi_p2_address[2]),
-	.D7(k7ddrphy_dfi_p3_address[2]),
-	.D8(k7ddrphy_dfi_p3_address[2]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_oq4)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_dfi_p0_address[2]),
+	.D2     (main_k7ddrphy_dfi_p0_address[2]),
+	.D3     (main_k7ddrphy_dfi_p1_address[2]),
+	.D4     (main_k7ddrphy_dfi_p1_address[2]),
+	.D5     (main_k7ddrphy_dfi_p2_address[2]),
+	.D6     (main_k7ddrphy_dfi_p2_address[2]),
+	.D7     (main_k7ddrphy_dfi_p3_address[2]),
+	.D8     (main_k7ddrphy_dfi_p3_address[2]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_oq4)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_5 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_5 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_a[2]),
-	.ODATAIN(k7ddrphy_oq4)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_a[2]),
+	.ODATAIN  (main_k7ddrphy_oq4)
 );
 
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_6 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
+OSERDESE2 #(
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_6 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_dfi_p0_address[3]),
-	.D2(k7ddrphy_dfi_p0_address[3]),
-	.D3(k7ddrphy_dfi_p1_address[3]),
-	.D4(k7ddrphy_dfi_p1_address[3]),
-	.D5(k7ddrphy_dfi_p2_address[3]),
-	.D6(k7ddrphy_dfi_p2_address[3]),
-	.D7(k7ddrphy_dfi_p3_address[3]),
-	.D8(k7ddrphy_dfi_p3_address[3]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_oq5)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_dfi_p0_address[3]),
+	.D2     (main_k7ddrphy_dfi_p0_address[3]),
+	.D3     (main_k7ddrphy_dfi_p1_address[3]),
+	.D4     (main_k7ddrphy_dfi_p1_address[3]),
+	.D5     (main_k7ddrphy_dfi_p2_address[3]),
+	.D6     (main_k7ddrphy_dfi_p2_address[3]),
+	.D7     (main_k7ddrphy_dfi_p3_address[3]),
+	.D8     (main_k7ddrphy_dfi_p3_address[3]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_oq5)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_6 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_6 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_a[3]),
-	.ODATAIN(k7ddrphy_oq5)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_a[3]),
+	.ODATAIN  (main_k7ddrphy_oq5)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_7 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_7 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_dfi_p0_address[4]),
-	.D2(k7ddrphy_dfi_p0_address[4]),
-	.D3(k7ddrphy_dfi_p1_address[4]),
-	.D4(k7ddrphy_dfi_p1_address[4]),
-	.D5(k7ddrphy_dfi_p2_address[4]),
-	.D6(k7ddrphy_dfi_p2_address[4]),
-	.D7(k7ddrphy_dfi_p3_address[4]),
-	.D8(k7ddrphy_dfi_p3_address[4]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_oq6)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_dfi_p0_address[4]),
+	.D2     (main_k7ddrphy_dfi_p0_address[4]),
+	.D3     (main_k7ddrphy_dfi_p1_address[4]),
+	.D4     (main_k7ddrphy_dfi_p1_address[4]),
+	.D5     (main_k7ddrphy_dfi_p2_address[4]),
+	.D6     (main_k7ddrphy_dfi_p2_address[4]),
+	.D7     (main_k7ddrphy_dfi_p3_address[4]),
+	.D8     (main_k7ddrphy_dfi_p3_address[4]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_oq6)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_7 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_7 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_a[4]),
-	.ODATAIN(k7ddrphy_oq6)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_a[4]),
+	.ODATAIN  (main_k7ddrphy_oq6)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_8 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_8 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_dfi_p0_address[5]),
-	.D2(k7ddrphy_dfi_p0_address[5]),
-	.D3(k7ddrphy_dfi_p1_address[5]),
-	.D4(k7ddrphy_dfi_p1_address[5]),
-	.D5(k7ddrphy_dfi_p2_address[5]),
-	.D6(k7ddrphy_dfi_p2_address[5]),
-	.D7(k7ddrphy_dfi_p3_address[5]),
-	.D8(k7ddrphy_dfi_p3_address[5]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_oq7)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_dfi_p0_address[5]),
+	.D2     (main_k7ddrphy_dfi_p0_address[5]),
+	.D3     (main_k7ddrphy_dfi_p1_address[5]),
+	.D4     (main_k7ddrphy_dfi_p1_address[5]),
+	.D5     (main_k7ddrphy_dfi_p2_address[5]),
+	.D6     (main_k7ddrphy_dfi_p2_address[5]),
+	.D7     (main_k7ddrphy_dfi_p3_address[5]),
+	.D8     (main_k7ddrphy_dfi_p3_address[5]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_oq7)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_8 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_8 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_a[5]),
-	.ODATAIN(k7ddrphy_oq7)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_a[5]),
+	.ODATAIN  (main_k7ddrphy_oq7)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_9 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_9 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_dfi_p0_address[6]),
-	.D2(k7ddrphy_dfi_p0_address[6]),
-	.D3(k7ddrphy_dfi_p1_address[6]),
-	.D4(k7ddrphy_dfi_p1_address[6]),
-	.D5(k7ddrphy_dfi_p2_address[6]),
-	.D6(k7ddrphy_dfi_p2_address[6]),
-	.D7(k7ddrphy_dfi_p3_address[6]),
-	.D8(k7ddrphy_dfi_p3_address[6]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_oq8)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_dfi_p0_address[6]),
+	.D2     (main_k7ddrphy_dfi_p0_address[6]),
+	.D3     (main_k7ddrphy_dfi_p1_address[6]),
+	.D4     (main_k7ddrphy_dfi_p1_address[6]),
+	.D5     (main_k7ddrphy_dfi_p2_address[6]),
+	.D6     (main_k7ddrphy_dfi_p2_address[6]),
+	.D7     (main_k7ddrphy_dfi_p3_address[6]),
+	.D8     (main_k7ddrphy_dfi_p3_address[6]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_oq8)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_9 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_9 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_a[6]),
-	.ODATAIN(k7ddrphy_oq8)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_a[6]),
+	.ODATAIN  (main_k7ddrphy_oq8)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_10 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_10 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_dfi_p0_address[7]),
-	.D2(k7ddrphy_dfi_p0_address[7]),
-	.D3(k7ddrphy_dfi_p1_address[7]),
-	.D4(k7ddrphy_dfi_p1_address[7]),
-	.D5(k7ddrphy_dfi_p2_address[7]),
-	.D6(k7ddrphy_dfi_p2_address[7]),
-	.D7(k7ddrphy_dfi_p3_address[7]),
-	.D8(k7ddrphy_dfi_p3_address[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_oq9)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_dfi_p0_address[7]),
+	.D2     (main_k7ddrphy_dfi_p0_address[7]),
+	.D3     (main_k7ddrphy_dfi_p1_address[7]),
+	.D4     (main_k7ddrphy_dfi_p1_address[7]),
+	.D5     (main_k7ddrphy_dfi_p2_address[7]),
+	.D6     (main_k7ddrphy_dfi_p2_address[7]),
+	.D7     (main_k7ddrphy_dfi_p3_address[7]),
+	.D8     (main_k7ddrphy_dfi_p3_address[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_oq9)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_10 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_10 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_a[7]),
-	.ODATAIN(k7ddrphy_oq9)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_a[7]),
+	.ODATAIN  (main_k7ddrphy_oq9)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_11 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_11 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_dfi_p0_address[8]),
-	.D2(k7ddrphy_dfi_p0_address[8]),
-	.D3(k7ddrphy_dfi_p1_address[8]),
-	.D4(k7ddrphy_dfi_p1_address[8]),
-	.D5(k7ddrphy_dfi_p2_address[8]),
-	.D6(k7ddrphy_dfi_p2_address[8]),
-	.D7(k7ddrphy_dfi_p3_address[8]),
-	.D8(k7ddrphy_dfi_p3_address[8]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_oq10)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_dfi_p0_address[8]),
+	.D2     (main_k7ddrphy_dfi_p0_address[8]),
+	.D3     (main_k7ddrphy_dfi_p1_address[8]),
+	.D4     (main_k7ddrphy_dfi_p1_address[8]),
+	.D5     (main_k7ddrphy_dfi_p2_address[8]),
+	.D6     (main_k7ddrphy_dfi_p2_address[8]),
+	.D7     (main_k7ddrphy_dfi_p3_address[8]),
+	.D8     (main_k7ddrphy_dfi_p3_address[8]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_oq10)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_11 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_11 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_a[8]),
-	.ODATAIN(k7ddrphy_oq10)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_a[8]),
+	.ODATAIN  (main_k7ddrphy_oq10)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_12 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_12 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_dfi_p0_address[9]),
-	.D2(k7ddrphy_dfi_p0_address[9]),
-	.D3(k7ddrphy_dfi_p1_address[9]),
-	.D4(k7ddrphy_dfi_p1_address[9]),
-	.D5(k7ddrphy_dfi_p2_address[9]),
-	.D6(k7ddrphy_dfi_p2_address[9]),
-	.D7(k7ddrphy_dfi_p3_address[9]),
-	.D8(k7ddrphy_dfi_p3_address[9]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_oq11)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_dfi_p0_address[9]),
+	.D2     (main_k7ddrphy_dfi_p0_address[9]),
+	.D3     (main_k7ddrphy_dfi_p1_address[9]),
+	.D4     (main_k7ddrphy_dfi_p1_address[9]),
+	.D5     (main_k7ddrphy_dfi_p2_address[9]),
+	.D6     (main_k7ddrphy_dfi_p2_address[9]),
+	.D7     (main_k7ddrphy_dfi_p3_address[9]),
+	.D8     (main_k7ddrphy_dfi_p3_address[9]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_oq11)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_12 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_12 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_a[9]),
-	.ODATAIN(k7ddrphy_oq11)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_a[9]),
+	.ODATAIN  (main_k7ddrphy_oq11)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_13 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_13 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_dfi_p0_address[10]),
-	.D2(k7ddrphy_dfi_p0_address[10]),
-	.D3(k7ddrphy_dfi_p1_address[10]),
-	.D4(k7ddrphy_dfi_p1_address[10]),
-	.D5(k7ddrphy_dfi_p2_address[10]),
-	.D6(k7ddrphy_dfi_p2_address[10]),
-	.D7(k7ddrphy_dfi_p3_address[10]),
-	.D8(k7ddrphy_dfi_p3_address[10]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_oq12)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_dfi_p0_address[10]),
+	.D2     (main_k7ddrphy_dfi_p0_address[10]),
+	.D3     (main_k7ddrphy_dfi_p1_address[10]),
+	.D4     (main_k7ddrphy_dfi_p1_address[10]),
+	.D5     (main_k7ddrphy_dfi_p2_address[10]),
+	.D6     (main_k7ddrphy_dfi_p2_address[10]),
+	.D7     (main_k7ddrphy_dfi_p3_address[10]),
+	.D8     (main_k7ddrphy_dfi_p3_address[10]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_oq12)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_13 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_13 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_a[10]),
-	.ODATAIN(k7ddrphy_oq12)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_a[10]),
+	.ODATAIN  (main_k7ddrphy_oq12)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_14 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_14 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_dfi_p0_address[11]),
-	.D2(k7ddrphy_dfi_p0_address[11]),
-	.D3(k7ddrphy_dfi_p1_address[11]),
-	.D4(k7ddrphy_dfi_p1_address[11]),
-	.D5(k7ddrphy_dfi_p2_address[11]),
-	.D6(k7ddrphy_dfi_p2_address[11]),
-	.D7(k7ddrphy_dfi_p3_address[11]),
-	.D8(k7ddrphy_dfi_p3_address[11]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_oq13)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_dfi_p0_address[11]),
+	.D2     (main_k7ddrphy_dfi_p0_address[11]),
+	.D3     (main_k7ddrphy_dfi_p1_address[11]),
+	.D4     (main_k7ddrphy_dfi_p1_address[11]),
+	.D5     (main_k7ddrphy_dfi_p2_address[11]),
+	.D6     (main_k7ddrphy_dfi_p2_address[11]),
+	.D7     (main_k7ddrphy_dfi_p3_address[11]),
+	.D8     (main_k7ddrphy_dfi_p3_address[11]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_oq13)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_14 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_14 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_a[11]),
-	.ODATAIN(k7ddrphy_oq13)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_a[11]),
+	.ODATAIN  (main_k7ddrphy_oq13)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_15 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_15 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_dfi_p0_address[12]),
-	.D2(k7ddrphy_dfi_p0_address[12]),
-	.D3(k7ddrphy_dfi_p1_address[12]),
-	.D4(k7ddrphy_dfi_p1_address[12]),
-	.D5(k7ddrphy_dfi_p2_address[12]),
-	.D6(k7ddrphy_dfi_p2_address[12]),
-	.D7(k7ddrphy_dfi_p3_address[12]),
-	.D8(k7ddrphy_dfi_p3_address[12]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_oq14)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_dfi_p0_address[12]),
+	.D2     (main_k7ddrphy_dfi_p0_address[12]),
+	.D3     (main_k7ddrphy_dfi_p1_address[12]),
+	.D4     (main_k7ddrphy_dfi_p1_address[12]),
+	.D5     (main_k7ddrphy_dfi_p2_address[12]),
+	.D6     (main_k7ddrphy_dfi_p2_address[12]),
+	.D7     (main_k7ddrphy_dfi_p3_address[12]),
+	.D8     (main_k7ddrphy_dfi_p3_address[12]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_oq14)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_15 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_15 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_a[12]),
-	.ODATAIN(k7ddrphy_oq14)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_a[12]),
+	.ODATAIN  (main_k7ddrphy_oq14)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_16 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_16 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_dfi_p0_address[13]),
-	.D2(k7ddrphy_dfi_p0_address[13]),
-	.D3(k7ddrphy_dfi_p1_address[13]),
-	.D4(k7ddrphy_dfi_p1_address[13]),
-	.D5(k7ddrphy_dfi_p2_address[13]),
-	.D6(k7ddrphy_dfi_p2_address[13]),
-	.D7(k7ddrphy_dfi_p3_address[13]),
-	.D8(k7ddrphy_dfi_p3_address[13]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_oq15)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_dfi_p0_address[13]),
+	.D2     (main_k7ddrphy_dfi_p0_address[13]),
+	.D3     (main_k7ddrphy_dfi_p1_address[13]),
+	.D4     (main_k7ddrphy_dfi_p1_address[13]),
+	.D5     (main_k7ddrphy_dfi_p2_address[13]),
+	.D6     (main_k7ddrphy_dfi_p2_address[13]),
+	.D7     (main_k7ddrphy_dfi_p3_address[13]),
+	.D8     (main_k7ddrphy_dfi_p3_address[13]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_oq15)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_16 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_16 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_a[13]),
-	.ODATAIN(k7ddrphy_oq15)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_a[13]),
+	.ODATAIN  (main_k7ddrphy_oq15)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_17 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_17 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_dfi_p0_address[14]),
-	.D2(k7ddrphy_dfi_p0_address[14]),
-	.D3(k7ddrphy_dfi_p1_address[14]),
-	.D4(k7ddrphy_dfi_p1_address[14]),
-	.D5(k7ddrphy_dfi_p2_address[14]),
-	.D6(k7ddrphy_dfi_p2_address[14]),
-	.D7(k7ddrphy_dfi_p3_address[14]),
-	.D8(k7ddrphy_dfi_p3_address[14]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_oq16)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_dfi_p0_address[14]),
+	.D2     (main_k7ddrphy_dfi_p0_address[14]),
+	.D3     (main_k7ddrphy_dfi_p1_address[14]),
+	.D4     (main_k7ddrphy_dfi_p1_address[14]),
+	.D5     (main_k7ddrphy_dfi_p2_address[14]),
+	.D6     (main_k7ddrphy_dfi_p2_address[14]),
+	.D7     (main_k7ddrphy_dfi_p3_address[14]),
+	.D8     (main_k7ddrphy_dfi_p3_address[14]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_oq16)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_17 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_17 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_a[14]),
-	.ODATAIN(k7ddrphy_oq16)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_a[14]),
+	.ODATAIN  (main_k7ddrphy_oq16)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_18 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_18 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_dfi_p0_bank[0]),
-	.D2(k7ddrphy_dfi_p0_bank[0]),
-	.D3(k7ddrphy_dfi_p1_bank[0]),
-	.D4(k7ddrphy_dfi_p1_bank[0]),
-	.D5(k7ddrphy_dfi_p2_bank[0]),
-	.D6(k7ddrphy_dfi_p2_bank[0]),
-	.D7(k7ddrphy_dfi_p3_bank[0]),
-	.D8(k7ddrphy_dfi_p3_bank[0]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_oq17)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_dfi_p0_bank[0]),
+	.D2     (main_k7ddrphy_dfi_p0_bank[0]),
+	.D3     (main_k7ddrphy_dfi_p1_bank[0]),
+	.D4     (main_k7ddrphy_dfi_p1_bank[0]),
+	.D5     (main_k7ddrphy_dfi_p2_bank[0]),
+	.D6     (main_k7ddrphy_dfi_p2_bank[0]),
+	.D7     (main_k7ddrphy_dfi_p3_bank[0]),
+	.D8     (main_k7ddrphy_dfi_p3_bank[0]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_oq17)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_18 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_18 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_pads_ba[0]),
-	.ODATAIN(k7ddrphy_oq17)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_pads_ba[0]),
+	.ODATAIN  (main_k7ddrphy_oq17)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_19 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_19 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_dfi_p0_bank[1]),
-	.D2(k7ddrphy_dfi_p0_bank[1]),
-	.D3(k7ddrphy_dfi_p1_bank[1]),
-	.D4(k7ddrphy_dfi_p1_bank[1]),
-	.D5(k7ddrphy_dfi_p2_bank[1]),
-	.D6(k7ddrphy_dfi_p2_bank[1]),
-	.D7(k7ddrphy_dfi_p3_bank[1]),
-	.D8(k7ddrphy_dfi_p3_bank[1]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_oq18)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_dfi_p0_bank[1]),
+	.D2     (main_k7ddrphy_dfi_p0_bank[1]),
+	.D3     (main_k7ddrphy_dfi_p1_bank[1]),
+	.D4     (main_k7ddrphy_dfi_p1_bank[1]),
+	.D5     (main_k7ddrphy_dfi_p2_bank[1]),
+	.D6     (main_k7ddrphy_dfi_p2_bank[1]),
+	.D7     (main_k7ddrphy_dfi_p3_bank[1]),
+	.D8     (main_k7ddrphy_dfi_p3_bank[1]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_oq18)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_19 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_19 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_pads_ba[1]),
-	.ODATAIN(k7ddrphy_oq18)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_pads_ba[1]),
+	.ODATAIN  (main_k7ddrphy_oq18)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_20 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_20 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_dfi_p0_bank[2]),
-	.D2(k7ddrphy_dfi_p0_bank[2]),
-	.D3(k7ddrphy_dfi_p1_bank[2]),
-	.D4(k7ddrphy_dfi_p1_bank[2]),
-	.D5(k7ddrphy_dfi_p2_bank[2]),
-	.D6(k7ddrphy_dfi_p2_bank[2]),
-	.D7(k7ddrphy_dfi_p3_bank[2]),
-	.D8(k7ddrphy_dfi_p3_bank[2]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_oq19)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_dfi_p0_bank[2]),
+	.D2     (main_k7ddrphy_dfi_p0_bank[2]),
+	.D3     (main_k7ddrphy_dfi_p1_bank[2]),
+	.D4     (main_k7ddrphy_dfi_p1_bank[2]),
+	.D5     (main_k7ddrphy_dfi_p2_bank[2]),
+	.D6     (main_k7ddrphy_dfi_p2_bank[2]),
+	.D7     (main_k7ddrphy_dfi_p3_bank[2]),
+	.D8     (main_k7ddrphy_dfi_p3_bank[2]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_oq19)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_20 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_20 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_pads_ba[2]),
-	.ODATAIN(k7ddrphy_oq19)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_pads_ba[2]),
+	.ODATAIN  (main_k7ddrphy_oq19)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_21 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_21 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_dfi_p0_ras_n),
-	.D2(k7ddrphy_dfi_p0_ras_n),
-	.D3(k7ddrphy_dfi_p1_ras_n),
-	.D4(k7ddrphy_dfi_p1_ras_n),
-	.D5(k7ddrphy_dfi_p2_ras_n),
-	.D6(k7ddrphy_dfi_p2_ras_n),
-	.D7(k7ddrphy_dfi_p3_ras_n),
-	.D8(k7ddrphy_dfi_p3_ras_n),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_oq20)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_dfi_p0_ras_n),
+	.D2     (main_k7ddrphy_dfi_p0_ras_n),
+	.D3     (main_k7ddrphy_dfi_p1_ras_n),
+	.D4     (main_k7ddrphy_dfi_p1_ras_n),
+	.D5     (main_k7ddrphy_dfi_p2_ras_n),
+	.D6     (main_k7ddrphy_dfi_p2_ras_n),
+	.D7     (main_k7ddrphy_dfi_p3_ras_n),
+	.D8     (main_k7ddrphy_dfi_p3_ras_n),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_oq20)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_21 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_21 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_ras_n),
-	.ODATAIN(k7ddrphy_oq20)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_ras_n),
+	.ODATAIN  (main_k7ddrphy_oq20)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_22 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_22 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_dfi_p0_cas_n),
-	.D2(k7ddrphy_dfi_p0_cas_n),
-	.D3(k7ddrphy_dfi_p1_cas_n),
-	.D4(k7ddrphy_dfi_p1_cas_n),
-	.D5(k7ddrphy_dfi_p2_cas_n),
-	.D6(k7ddrphy_dfi_p2_cas_n),
-	.D7(k7ddrphy_dfi_p3_cas_n),
-	.D8(k7ddrphy_dfi_p3_cas_n),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_oq21)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_dfi_p0_cas_n),
+	.D2     (main_k7ddrphy_dfi_p0_cas_n),
+	.D3     (main_k7ddrphy_dfi_p1_cas_n),
+	.D4     (main_k7ddrphy_dfi_p1_cas_n),
+	.D5     (main_k7ddrphy_dfi_p2_cas_n),
+	.D6     (main_k7ddrphy_dfi_p2_cas_n),
+	.D7     (main_k7ddrphy_dfi_p3_cas_n),
+	.D8     (main_k7ddrphy_dfi_p3_cas_n),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_oq21)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_22 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_22 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_cas_n),
-	.ODATAIN(k7ddrphy_oq21)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_cas_n),
+	.ODATAIN  (main_k7ddrphy_oq21)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_23 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_23 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_dfi_p0_we_n),
-	.D2(k7ddrphy_dfi_p0_we_n),
-	.D3(k7ddrphy_dfi_p1_we_n),
-	.D4(k7ddrphy_dfi_p1_we_n),
-	.D5(k7ddrphy_dfi_p2_we_n),
-	.D6(k7ddrphy_dfi_p2_we_n),
-	.D7(k7ddrphy_dfi_p3_we_n),
-	.D8(k7ddrphy_dfi_p3_we_n),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_oq22)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_dfi_p0_we_n),
+	.D2     (main_k7ddrphy_dfi_p0_we_n),
+	.D3     (main_k7ddrphy_dfi_p1_we_n),
+	.D4     (main_k7ddrphy_dfi_p1_we_n),
+	.D5     (main_k7ddrphy_dfi_p2_we_n),
+	.D6     (main_k7ddrphy_dfi_p2_we_n),
+	.D7     (main_k7ddrphy_dfi_p3_we_n),
+	.D8     (main_k7ddrphy_dfi_p3_we_n),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_oq22)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_23 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_23 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_we_n),
-	.ODATAIN(k7ddrphy_oq22)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_we_n),
+	.ODATAIN  (main_k7ddrphy_oq22)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_24 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_24 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_dfi_p0_cke),
-	.D2(k7ddrphy_dfi_p0_cke),
-	.D3(k7ddrphy_dfi_p1_cke),
-	.D4(k7ddrphy_dfi_p1_cke),
-	.D5(k7ddrphy_dfi_p2_cke),
-	.D6(k7ddrphy_dfi_p2_cke),
-	.D7(k7ddrphy_dfi_p3_cke),
-	.D8(k7ddrphy_dfi_p3_cke),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_oq23)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_dfi_p0_cke),
+	.D2     (main_k7ddrphy_dfi_p0_cke),
+	.D3     (main_k7ddrphy_dfi_p1_cke),
+	.D4     (main_k7ddrphy_dfi_p1_cke),
+	.D5     (main_k7ddrphy_dfi_p2_cke),
+	.D6     (main_k7ddrphy_dfi_p2_cke),
+	.D7     (main_k7ddrphy_dfi_p3_cke),
+	.D8     (main_k7ddrphy_dfi_p3_cke),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_oq23)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_24 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_24 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_cke),
-	.ODATAIN(k7ddrphy_oq23)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_cke),
+	.ODATAIN  (main_k7ddrphy_oq23)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_25 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_25 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_dfi_p0_odt),
-	.D2(k7ddrphy_dfi_p0_odt),
-	.D3(k7ddrphy_dfi_p1_odt),
-	.D4(k7ddrphy_dfi_p1_odt),
-	.D5(k7ddrphy_dfi_p2_odt),
-	.D6(k7ddrphy_dfi_p2_odt),
-	.D7(k7ddrphy_dfi_p3_odt),
-	.D8(k7ddrphy_dfi_p3_odt),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_oq24)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_dfi_p0_odt),
+	.D2     (main_k7ddrphy_dfi_p0_odt),
+	.D3     (main_k7ddrphy_dfi_p1_odt),
+	.D4     (main_k7ddrphy_dfi_p1_odt),
+	.D5     (main_k7ddrphy_dfi_p2_odt),
+	.D6     (main_k7ddrphy_dfi_p2_odt),
+	.D7     (main_k7ddrphy_dfi_p3_odt),
+	.D8     (main_k7ddrphy_dfi_p3_odt),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_oq24)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_25 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_25 (
-	.C(sys_clk),
-	.CE(k7ddrphy_cdly_inc_re),
-	.INC(1'd1),
-	.LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_odt),
-	.ODATAIN(k7ddrphy_oq24)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       (main_k7ddrphy_cdly_inc_re),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_odt),
+	.ODATAIN  (main_k7ddrphy_oq24)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_26 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_26 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip00[0]),
-	.D2(k7ddrphy_bitslip00[1]),
-	.D3(k7ddrphy_bitslip00[2]),
-	.D4(k7ddrphy_bitslip00[3]),
-	.D5(k7ddrphy_bitslip00[4]),
-	.D6(k7ddrphy_bitslip00[5]),
-	.D7(k7ddrphy_bitslip00[6]),
-	.D8(k7ddrphy_bitslip00[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OFB(k7ddrphy_dqs_o_no_delay0),
-	.OQ(k7ddrphy0),
-	.TQ(k7ddrphy_dqs_t0)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip00[0]),
+	.D2     (main_k7ddrphy_bitslip00[1]),
+	.D3     (main_k7ddrphy_bitslip00[2]),
+	.D4     (main_k7ddrphy_bitslip00[3]),
+	.D5     (main_k7ddrphy_bitslip00[4]),
+	.D6     (main_k7ddrphy_bitslip00[5]),
+	.D7     (main_k7ddrphy_bitslip00[6]),
+	.D8     (main_k7ddrphy_bitslip00[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OFB    (main_k7ddrphy_dqs_o_no_delay0),
+	.OQ     (main_k7ddrphy0),
+	.TQ     (main_k7ddrphy_dqs_t0)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_26 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(4'd8),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (4'd8),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_26 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dqs_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dqs_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dqs_o_delayed0),
-	.ODATAIN(k7ddrphy_dqs_o_no_delay0)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dqs_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dqs_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dqs_o_delayed0),
+	.ODATAIN  (main_k7ddrphy_dqs_o_no_delay0)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUFDS of IOBUFDS Module.
+//------------------------------------------------------------------------------
 IOBUFDS IOBUFDS(
-	.I(k7ddrphy_dqs_o_delayed0),
-	.T(k7ddrphy_dqs_t0),
-	.IO(ddram_dqs_p[0]),
-	.IOB(ddram_dqs_n[0])
+	// Inputs.
+	.I   (main_k7ddrphy_dqs_o_delayed0),
+	.T   (main_k7ddrphy_dqs_t0),
+
+	// InOuts.
+	.IO  (ddram_dqs_p[0]),
+	.IOB (ddram_dqs_n[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_27 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_27 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip10[0]),
-	.D2(k7ddrphy_bitslip10[1]),
-	.D3(k7ddrphy_bitslip10[2]),
-	.D4(k7ddrphy_bitslip10[3]),
-	.D5(k7ddrphy_bitslip10[4]),
-	.D6(k7ddrphy_bitslip10[5]),
-	.D7(k7ddrphy_bitslip10[6]),
-	.D8(k7ddrphy_bitslip10[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OFB(k7ddrphy_dqs_o_no_delay1),
-	.OQ(k7ddrphy1),
-	.TQ(k7ddrphy_dqs_t1)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip10[0]),
+	.D2     (main_k7ddrphy_bitslip10[1]),
+	.D3     (main_k7ddrphy_bitslip10[2]),
+	.D4     (main_k7ddrphy_bitslip10[3]),
+	.D5     (main_k7ddrphy_bitslip10[4]),
+	.D6     (main_k7ddrphy_bitslip10[5]),
+	.D7     (main_k7ddrphy_bitslip10[6]),
+	.D8     (main_k7ddrphy_bitslip10[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OFB    (main_k7ddrphy_dqs_o_no_delay1),
+	.OQ     (main_k7ddrphy1),
+	.TQ     (main_k7ddrphy_dqs_t1)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_27 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(4'd8),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (4'd8),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_27 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dqs_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dqs_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dqs_o_delayed1),
-	.ODATAIN(k7ddrphy_dqs_o_no_delay1)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dqs_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dqs_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dqs_o_delayed1),
+	.ODATAIN  (main_k7ddrphy_dqs_o_no_delay1)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUFDS_1 of IOBUFDS Module.
+//------------------------------------------------------------------------------
 IOBUFDS IOBUFDS_1(
-	.I(k7ddrphy_dqs_o_delayed1),
-	.T(k7ddrphy_dqs_t1),
-	.IO(ddram_dqs_p[1]),
-	.IOB(ddram_dqs_n[1])
+	// Inputs.
+	.I   (main_k7ddrphy_dqs_o_delayed1),
+	.T   (main_k7ddrphy_dqs_t1),
+
+	// InOuts.
+	.IO  (ddram_dqs_p[1]),
+	.IOB (ddram_dqs_n[1])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_28 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_28 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip20[0]),
-	.D2(k7ddrphy_bitslip20[1]),
-	.D3(k7ddrphy_bitslip20[2]),
-	.D4(k7ddrphy_bitslip20[3]),
-	.D5(k7ddrphy_bitslip20[4]),
-	.D6(k7ddrphy_bitslip20[5]),
-	.D7(k7ddrphy_bitslip20[6]),
-	.D8(k7ddrphy_bitslip20[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OFB(k7ddrphy_dqs_o_no_delay2),
-	.OQ(k7ddrphy2),
-	.TQ(k7ddrphy_dqs_t2)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip20[0]),
+	.D2     (main_k7ddrphy_bitslip20[1]),
+	.D3     (main_k7ddrphy_bitslip20[2]),
+	.D4     (main_k7ddrphy_bitslip20[3]),
+	.D5     (main_k7ddrphy_bitslip20[4]),
+	.D6     (main_k7ddrphy_bitslip20[5]),
+	.D7     (main_k7ddrphy_bitslip20[6]),
+	.D8     (main_k7ddrphy_bitslip20[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OFB    (main_k7ddrphy_dqs_o_no_delay2),
+	.OQ     (main_k7ddrphy2),
+	.TQ     (main_k7ddrphy_dqs_t2)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_28 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(4'd8),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (4'd8),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_28 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dqs_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dqs_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dqs_o_delayed2),
-	.ODATAIN(k7ddrphy_dqs_o_no_delay2)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dqs_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dqs_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dqs_o_delayed2),
+	.ODATAIN  (main_k7ddrphy_dqs_o_no_delay2)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUFDS_2 of IOBUFDS Module.
+//------------------------------------------------------------------------------
 IOBUFDS IOBUFDS_2(
-	.I(k7ddrphy_dqs_o_delayed2),
-	.T(k7ddrphy_dqs_t2),
-	.IO(ddram_dqs_p[2]),
-	.IOB(ddram_dqs_n[2])
+	// Inputs.
+	.I   (main_k7ddrphy_dqs_o_delayed2),
+	.T   (main_k7ddrphy_dqs_t2),
+
+	// InOuts.
+	.IO  (ddram_dqs_p[2]),
+	.IOB (ddram_dqs_n[2])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_29 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_29 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip30[0]),
-	.D2(k7ddrphy_bitslip30[1]),
-	.D3(k7ddrphy_bitslip30[2]),
-	.D4(k7ddrphy_bitslip30[3]),
-	.D5(k7ddrphy_bitslip30[4]),
-	.D6(k7ddrphy_bitslip30[5]),
-	.D7(k7ddrphy_bitslip30[6]),
-	.D8(k7ddrphy_bitslip30[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OFB(k7ddrphy_dqs_o_no_delay3),
-	.OQ(k7ddrphy3),
-	.TQ(k7ddrphy_dqs_t3)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip30[0]),
+	.D2     (main_k7ddrphy_bitslip30[1]),
+	.D3     (main_k7ddrphy_bitslip30[2]),
+	.D4     (main_k7ddrphy_bitslip30[3]),
+	.D5     (main_k7ddrphy_bitslip30[4]),
+	.D6     (main_k7ddrphy_bitslip30[5]),
+	.D7     (main_k7ddrphy_bitslip30[6]),
+	.D8     (main_k7ddrphy_bitslip30[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OFB    (main_k7ddrphy_dqs_o_no_delay3),
+	.OQ     (main_k7ddrphy3),
+	.TQ     (main_k7ddrphy_dqs_t3)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_29 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(4'd8),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (4'd8),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_29 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dqs_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dqs_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dqs_o_delayed3),
-	.ODATAIN(k7ddrphy_dqs_o_no_delay3)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dqs_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dqs_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dqs_o_delayed3),
+	.ODATAIN  (main_k7ddrphy_dqs_o_no_delay3)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUFDS_3 of IOBUFDS Module.
+//------------------------------------------------------------------------------
 IOBUFDS IOBUFDS_3(
-	.I(k7ddrphy_dqs_o_delayed3),
-	.T(k7ddrphy_dqs_t3),
-	.IO(ddram_dqs_p[3]),
-	.IOB(ddram_dqs_n[3])
+	// Inputs.
+	.I   (main_k7ddrphy_dqs_o_delayed3),
+	.T   (main_k7ddrphy_dqs_t3),
+
+	// InOuts.
+	.IO  (ddram_dqs_p[3]),
+	.IOB (ddram_dqs_n[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_30 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_30 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip01[0]),
-	.D2(k7ddrphy_bitslip01[1]),
-	.D3(k7ddrphy_bitslip01[2]),
-	.D4(k7ddrphy_bitslip01[3]),
-	.D5(k7ddrphy_bitslip01[4]),
-	.D6(k7ddrphy_bitslip01[5]),
-	.D7(k7ddrphy_bitslip01[6]),
-	.D8(k7ddrphy_bitslip01[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_dm_o_nodelay0)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip01[0]),
+	.D2     (main_k7ddrphy_bitslip01[1]),
+	.D3     (main_k7ddrphy_bitslip01[2]),
+	.D4     (main_k7ddrphy_bitslip01[3]),
+	.D5     (main_k7ddrphy_bitslip01[4]),
+	.D6     (main_k7ddrphy_bitslip01[5]),
+	.D7     (main_k7ddrphy_bitslip01[6]),
+	.D8     (main_k7ddrphy_bitslip01[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dm_o_nodelay0)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_30 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_30 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_dm[0]),
-	.ODATAIN(k7ddrphy_dm_o_nodelay0)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_dm[0]),
+	.ODATAIN  (main_k7ddrphy_dm_o_nodelay0)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_31 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_31 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip11[0]),
-	.D2(k7ddrphy_bitslip11[1]),
-	.D3(k7ddrphy_bitslip11[2]),
-	.D4(k7ddrphy_bitslip11[3]),
-	.D5(k7ddrphy_bitslip11[4]),
-	.D6(k7ddrphy_bitslip11[5]),
-	.D7(k7ddrphy_bitslip11[6]),
-	.D8(k7ddrphy_bitslip11[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_dm_o_nodelay1)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip11[0]),
+	.D2     (main_k7ddrphy_bitslip11[1]),
+	.D3     (main_k7ddrphy_bitslip11[2]),
+	.D4     (main_k7ddrphy_bitslip11[3]),
+	.D5     (main_k7ddrphy_bitslip11[4]),
+	.D6     (main_k7ddrphy_bitslip11[5]),
+	.D7     (main_k7ddrphy_bitslip11[6]),
+	.D8     (main_k7ddrphy_bitslip11[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dm_o_nodelay1)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_31 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_31 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_dm[1]),
-	.ODATAIN(k7ddrphy_dm_o_nodelay1)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_dm[1]),
+	.ODATAIN  (main_k7ddrphy_dm_o_nodelay1)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_32 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_32 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip21[0]),
-	.D2(k7ddrphy_bitslip21[1]),
-	.D3(k7ddrphy_bitslip21[2]),
-	.D4(k7ddrphy_bitslip21[3]),
-	.D5(k7ddrphy_bitslip21[4]),
-	.D6(k7ddrphy_bitslip21[5]),
-	.D7(k7ddrphy_bitslip21[6]),
-	.D8(k7ddrphy_bitslip21[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_dm_o_nodelay2)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip21[0]),
+	.D2     (main_k7ddrphy_bitslip21[1]),
+	.D3     (main_k7ddrphy_bitslip21[2]),
+	.D4     (main_k7ddrphy_bitslip21[3]),
+	.D5     (main_k7ddrphy_bitslip21[4]),
+	.D6     (main_k7ddrphy_bitslip21[5]),
+	.D7     (main_k7ddrphy_bitslip21[6]),
+	.D8     (main_k7ddrphy_bitslip21[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dm_o_nodelay2)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_32 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_32 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_dm[2]),
-	.ODATAIN(k7ddrphy_dm_o_nodelay2)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_dm[2]),
+	.ODATAIN  (main_k7ddrphy_dm_o_nodelay2)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_33 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_33 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip31[0]),
-	.D2(k7ddrphy_bitslip31[1]),
-	.D3(k7ddrphy_bitslip31[2]),
-	.D4(k7ddrphy_bitslip31[3]),
-	.D5(k7ddrphy_bitslip31[4]),
-	.D6(k7ddrphy_bitslip31[5]),
-	.D7(k7ddrphy_bitslip31[6]),
-	.D8(k7ddrphy_bitslip31[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.OQ(k7ddrphy_dm_o_nodelay3)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip31[0]),
+	.D2     (main_k7ddrphy_bitslip31[1]),
+	.D3     (main_k7ddrphy_bitslip31[2]),
+	.D4     (main_k7ddrphy_bitslip31[3]),
+	.D5     (main_k7ddrphy_bitslip31[4]),
+	.D6     (main_k7ddrphy_bitslip31[5]),
+	.D7     (main_k7ddrphy_bitslip31[6]),
+	.D8     (main_k7ddrphy_bitslip31[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dm_o_nodelay3)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_33 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_33 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(ddram_dm[3]),
-	.ODATAIN(k7ddrphy_dm_o_nodelay3)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (ddram_dm[3]),
+	.ODATAIN  (main_k7ddrphy_dm_o_nodelay3)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_34 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_34 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip02[0]),
-	.D2(k7ddrphy_bitslip02[1]),
-	.D3(k7ddrphy_bitslip02[2]),
-	.D4(k7ddrphy_bitslip02[3]),
-	.D5(k7ddrphy_bitslip02[4]),
-	.D6(k7ddrphy_bitslip02[5]),
-	.D7(k7ddrphy_bitslip02[6]),
-	.D8(k7ddrphy_bitslip02[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay0),
-	.TQ(k7ddrphy_dq_t0)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip02[0]),
+	.D2     (main_k7ddrphy_bitslip02[1]),
+	.D3     (main_k7ddrphy_bitslip02[2]),
+	.D4     (main_k7ddrphy_bitslip02[3]),
+	.D5     (main_k7ddrphy_bitslip02[4]),
+	.D6     (main_k7ddrphy_bitslip02[5]),
+	.D7     (main_k7ddrphy_bitslip02[6]),
+	.D8     (main_k7ddrphy_bitslip02[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay0),
+	.TQ     (main_k7ddrphy_dq_t0)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed0),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip03[7]),
-	.Q2(k7ddrphy_bitslip03[6]),
-	.Q3(k7ddrphy_bitslip03[5]),
-	.Q4(k7ddrphy_bitslip03[4]),
-	.Q5(k7ddrphy_bitslip03[3]),
-	.Q6(k7ddrphy_bitslip03[2]),
-	.Q7(k7ddrphy_bitslip03[1]),
-	.Q8(k7ddrphy_bitslip03[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed0),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip03[7]),
+	.Q2      (main_k7ddrphy_bitslip03[6]),
+	.Q3      (main_k7ddrphy_bitslip03[5]),
+	.Q4      (main_k7ddrphy_bitslip03[4]),
+	.Q5      (main_k7ddrphy_bitslip03[3]),
+	.Q6      (main_k7ddrphy_bitslip03[2]),
+	.Q7      (main_k7ddrphy_bitslip03[1]),
+	.Q8      (main_k7ddrphy_bitslip03[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_34 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_34 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed0),
-	.ODATAIN(k7ddrphy_dq_o_nodelay0)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed0),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay0)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay0),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed0)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay0),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed0)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF(
-	.I(k7ddrphy_dq_o_delayed0),
-	.T(k7ddrphy_dq_t0),
-	.IO(ddram_dq[0]),
-	.O(k7ddrphy_dq_i_nodelay0)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed0),
+	.T  (main_k7ddrphy_dq_t0),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay0),
+
+	// InOuts.
+	.IO (ddram_dq[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_35 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_35 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip12[0]),
-	.D2(k7ddrphy_bitslip12[1]),
-	.D3(k7ddrphy_bitslip12[2]),
-	.D4(k7ddrphy_bitslip12[3]),
-	.D5(k7ddrphy_bitslip12[4]),
-	.D6(k7ddrphy_bitslip12[5]),
-	.D7(k7ddrphy_bitslip12[6]),
-	.D8(k7ddrphy_bitslip12[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay1),
-	.TQ(k7ddrphy_dq_t1)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip12[0]),
+	.D2     (main_k7ddrphy_bitslip12[1]),
+	.D3     (main_k7ddrphy_bitslip12[2]),
+	.D4     (main_k7ddrphy_bitslip12[3]),
+	.D5     (main_k7ddrphy_bitslip12[4]),
+	.D6     (main_k7ddrphy_bitslip12[5]),
+	.D7     (main_k7ddrphy_bitslip12[6]),
+	.D8     (main_k7ddrphy_bitslip12[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay1),
+	.TQ     (main_k7ddrphy_dq_t1)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_1 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_1 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip13[7]),
-	.Q2(k7ddrphy_bitslip13[6]),
-	.Q3(k7ddrphy_bitslip13[5]),
-	.Q4(k7ddrphy_bitslip13[4]),
-	.Q5(k7ddrphy_bitslip13[3]),
-	.Q6(k7ddrphy_bitslip13[2]),
-	.Q7(k7ddrphy_bitslip13[1]),
-	.Q8(k7ddrphy_bitslip13[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed1),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip13[7]),
+	.Q2      (main_k7ddrphy_bitslip13[6]),
+	.Q3      (main_k7ddrphy_bitslip13[5]),
+	.Q4      (main_k7ddrphy_bitslip13[4]),
+	.Q5      (main_k7ddrphy_bitslip13[3]),
+	.Q6      (main_k7ddrphy_bitslip13[2]),
+	.Q7      (main_k7ddrphy_bitslip13[1]),
+	.Q8      (main_k7ddrphy_bitslip13[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_35 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_35 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed1),
-	.ODATAIN(k7ddrphy_dq_o_nodelay1)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed1),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay1)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_1 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_1 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay1),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed1)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay1),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed1)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_1 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_1(
-	.I(k7ddrphy_dq_o_delayed1),
-	.T(k7ddrphy_dq_t1),
-	.IO(ddram_dq[1]),
-	.O(k7ddrphy_dq_i_nodelay1)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed1),
+	.T  (main_k7ddrphy_dq_t1),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay1),
+
+	// InOuts.
+	.IO (ddram_dq[1])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_36 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_36 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip22[0]),
-	.D2(k7ddrphy_bitslip22[1]),
-	.D3(k7ddrphy_bitslip22[2]),
-	.D4(k7ddrphy_bitslip22[3]),
-	.D5(k7ddrphy_bitslip22[4]),
-	.D6(k7ddrphy_bitslip22[5]),
-	.D7(k7ddrphy_bitslip22[6]),
-	.D8(k7ddrphy_bitslip22[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay2),
-	.TQ(k7ddrphy_dq_t2)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip22[0]),
+	.D2     (main_k7ddrphy_bitslip22[1]),
+	.D3     (main_k7ddrphy_bitslip22[2]),
+	.D4     (main_k7ddrphy_bitslip22[3]),
+	.D5     (main_k7ddrphy_bitslip22[4]),
+	.D6     (main_k7ddrphy_bitslip22[5]),
+	.D7     (main_k7ddrphy_bitslip22[6]),
+	.D8     (main_k7ddrphy_bitslip22[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay2),
+	.TQ     (main_k7ddrphy_dq_t2)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_2 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_2 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed2),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip23[7]),
-	.Q2(k7ddrphy_bitslip23[6]),
-	.Q3(k7ddrphy_bitslip23[5]),
-	.Q4(k7ddrphy_bitslip23[4]),
-	.Q5(k7ddrphy_bitslip23[3]),
-	.Q6(k7ddrphy_bitslip23[2]),
-	.Q7(k7ddrphy_bitslip23[1]),
-	.Q8(k7ddrphy_bitslip23[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed2),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip23[7]),
+	.Q2      (main_k7ddrphy_bitslip23[6]),
+	.Q3      (main_k7ddrphy_bitslip23[5]),
+	.Q4      (main_k7ddrphy_bitslip23[4]),
+	.Q5      (main_k7ddrphy_bitslip23[3]),
+	.Q6      (main_k7ddrphy_bitslip23[2]),
+	.Q7      (main_k7ddrphy_bitslip23[1]),
+	.Q8      (main_k7ddrphy_bitslip23[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_36 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_36 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed2),
-	.ODATAIN(k7ddrphy_dq_o_nodelay2)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed2),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay2)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_2 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_2 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay2),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed2)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay2),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed2)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_2 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_2(
-	.I(k7ddrphy_dq_o_delayed2),
-	.T(k7ddrphy_dq_t2),
-	.IO(ddram_dq[2]),
-	.O(k7ddrphy_dq_i_nodelay2)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed2),
+	.T  (main_k7ddrphy_dq_t2),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay2),
+
+	// InOuts.
+	.IO (ddram_dq[2])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_37 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_37 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip32[0]),
-	.D2(k7ddrphy_bitslip32[1]),
-	.D3(k7ddrphy_bitslip32[2]),
-	.D4(k7ddrphy_bitslip32[3]),
-	.D5(k7ddrphy_bitslip32[4]),
-	.D6(k7ddrphy_bitslip32[5]),
-	.D7(k7ddrphy_bitslip32[6]),
-	.D8(k7ddrphy_bitslip32[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay3),
-	.TQ(k7ddrphy_dq_t3)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip32[0]),
+	.D2     (main_k7ddrphy_bitslip32[1]),
+	.D3     (main_k7ddrphy_bitslip32[2]),
+	.D4     (main_k7ddrphy_bitslip32[3]),
+	.D5     (main_k7ddrphy_bitslip32[4]),
+	.D6     (main_k7ddrphy_bitslip32[5]),
+	.D7     (main_k7ddrphy_bitslip32[6]),
+	.D8     (main_k7ddrphy_bitslip32[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay3),
+	.TQ     (main_k7ddrphy_dq_t3)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_3 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_3 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed3),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip33[7]),
-	.Q2(k7ddrphy_bitslip33[6]),
-	.Q3(k7ddrphy_bitslip33[5]),
-	.Q4(k7ddrphy_bitslip33[4]),
-	.Q5(k7ddrphy_bitslip33[3]),
-	.Q6(k7ddrphy_bitslip33[2]),
-	.Q7(k7ddrphy_bitslip33[1]),
-	.Q8(k7ddrphy_bitslip33[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed3),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip33[7]),
+	.Q2      (main_k7ddrphy_bitslip33[6]),
+	.Q3      (main_k7ddrphy_bitslip33[5]),
+	.Q4      (main_k7ddrphy_bitslip33[4]),
+	.Q5      (main_k7ddrphy_bitslip33[3]),
+	.Q6      (main_k7ddrphy_bitslip33[2]),
+	.Q7      (main_k7ddrphy_bitslip33[1]),
+	.Q8      (main_k7ddrphy_bitslip33[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_37 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_37 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed3),
-	.ODATAIN(k7ddrphy_dq_o_nodelay3)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed3),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay3)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_3 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_3 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay3),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed3)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay3),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed3)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_3 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_3(
-	.I(k7ddrphy_dq_o_delayed3),
-	.T(k7ddrphy_dq_t3),
-	.IO(ddram_dq[3]),
-	.O(k7ddrphy_dq_i_nodelay3)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed3),
+	.T  (main_k7ddrphy_dq_t3),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay3),
+
+	// InOuts.
+	.IO (ddram_dq[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_38 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_38 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip40[0]),
-	.D2(k7ddrphy_bitslip40[1]),
-	.D3(k7ddrphy_bitslip40[2]),
-	.D4(k7ddrphy_bitslip40[3]),
-	.D5(k7ddrphy_bitslip40[4]),
-	.D6(k7ddrphy_bitslip40[5]),
-	.D7(k7ddrphy_bitslip40[6]),
-	.D8(k7ddrphy_bitslip40[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay4),
-	.TQ(k7ddrphy_dq_t4)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip40[0]),
+	.D2     (main_k7ddrphy_bitslip40[1]),
+	.D3     (main_k7ddrphy_bitslip40[2]),
+	.D4     (main_k7ddrphy_bitslip40[3]),
+	.D5     (main_k7ddrphy_bitslip40[4]),
+	.D6     (main_k7ddrphy_bitslip40[5]),
+	.D7     (main_k7ddrphy_bitslip40[6]),
+	.D8     (main_k7ddrphy_bitslip40[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay4),
+	.TQ     (main_k7ddrphy_dq_t4)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_4 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_4 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed4),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip41[7]),
-	.Q2(k7ddrphy_bitslip41[6]),
-	.Q3(k7ddrphy_bitslip41[5]),
-	.Q4(k7ddrphy_bitslip41[4]),
-	.Q5(k7ddrphy_bitslip41[3]),
-	.Q6(k7ddrphy_bitslip41[2]),
-	.Q7(k7ddrphy_bitslip41[1]),
-	.Q8(k7ddrphy_bitslip41[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed4),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip41[7]),
+	.Q2      (main_k7ddrphy_bitslip41[6]),
+	.Q3      (main_k7ddrphy_bitslip41[5]),
+	.Q4      (main_k7ddrphy_bitslip41[4]),
+	.Q5      (main_k7ddrphy_bitslip41[3]),
+	.Q6      (main_k7ddrphy_bitslip41[2]),
+	.Q7      (main_k7ddrphy_bitslip41[1]),
+	.Q8      (main_k7ddrphy_bitslip41[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_38 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_38 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed4),
-	.ODATAIN(k7ddrphy_dq_o_nodelay4)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed4),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay4)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_4 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_4 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay4),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed4)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay4),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed4)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_4 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_4(
-	.I(k7ddrphy_dq_o_delayed4),
-	.T(k7ddrphy_dq_t4),
-	.IO(ddram_dq[4]),
-	.O(k7ddrphy_dq_i_nodelay4)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed4),
+	.T  (main_k7ddrphy_dq_t4),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay4),
+
+	// InOuts.
+	.IO (ddram_dq[4])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_39 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_39 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip50[0]),
-	.D2(k7ddrphy_bitslip50[1]),
-	.D3(k7ddrphy_bitslip50[2]),
-	.D4(k7ddrphy_bitslip50[3]),
-	.D5(k7ddrphy_bitslip50[4]),
-	.D6(k7ddrphy_bitslip50[5]),
-	.D7(k7ddrphy_bitslip50[6]),
-	.D8(k7ddrphy_bitslip50[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay5),
-	.TQ(k7ddrphy_dq_t5)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip50[0]),
+	.D2     (main_k7ddrphy_bitslip50[1]),
+	.D3     (main_k7ddrphy_bitslip50[2]),
+	.D4     (main_k7ddrphy_bitslip50[3]),
+	.D5     (main_k7ddrphy_bitslip50[4]),
+	.D6     (main_k7ddrphy_bitslip50[5]),
+	.D7     (main_k7ddrphy_bitslip50[6]),
+	.D8     (main_k7ddrphy_bitslip50[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay5),
+	.TQ     (main_k7ddrphy_dq_t5)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_5 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_5 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed5),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip51[7]),
-	.Q2(k7ddrphy_bitslip51[6]),
-	.Q3(k7ddrphy_bitslip51[5]),
-	.Q4(k7ddrphy_bitslip51[4]),
-	.Q5(k7ddrphy_bitslip51[3]),
-	.Q6(k7ddrphy_bitslip51[2]),
-	.Q7(k7ddrphy_bitslip51[1]),
-	.Q8(k7ddrphy_bitslip51[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed5),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip51[7]),
+	.Q2      (main_k7ddrphy_bitslip51[6]),
+	.Q3      (main_k7ddrphy_bitslip51[5]),
+	.Q4      (main_k7ddrphy_bitslip51[4]),
+	.Q5      (main_k7ddrphy_bitslip51[3]),
+	.Q6      (main_k7ddrphy_bitslip51[2]),
+	.Q7      (main_k7ddrphy_bitslip51[1]),
+	.Q8      (main_k7ddrphy_bitslip51[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_39 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_39 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed5),
-	.ODATAIN(k7ddrphy_dq_o_nodelay5)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed5),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay5)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_5 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_5 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay5),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed5)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay5),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed5)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_5 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_5(
-	.I(k7ddrphy_dq_o_delayed5),
-	.T(k7ddrphy_dq_t5),
-	.IO(ddram_dq[5]),
-	.O(k7ddrphy_dq_i_nodelay5)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed5),
+	.T  (main_k7ddrphy_dq_t5),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay5),
+
+	// InOuts.
+	.IO (ddram_dq[5])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_40 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_40 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip60[0]),
-	.D2(k7ddrphy_bitslip60[1]),
-	.D3(k7ddrphy_bitslip60[2]),
-	.D4(k7ddrphy_bitslip60[3]),
-	.D5(k7ddrphy_bitslip60[4]),
-	.D6(k7ddrphy_bitslip60[5]),
-	.D7(k7ddrphy_bitslip60[6]),
-	.D8(k7ddrphy_bitslip60[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay6),
-	.TQ(k7ddrphy_dq_t6)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip60[0]),
+	.D2     (main_k7ddrphy_bitslip60[1]),
+	.D3     (main_k7ddrphy_bitslip60[2]),
+	.D4     (main_k7ddrphy_bitslip60[3]),
+	.D5     (main_k7ddrphy_bitslip60[4]),
+	.D6     (main_k7ddrphy_bitslip60[5]),
+	.D7     (main_k7ddrphy_bitslip60[6]),
+	.D8     (main_k7ddrphy_bitslip60[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay6),
+	.TQ     (main_k7ddrphy_dq_t6)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_6 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_6 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed6),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip61[7]),
-	.Q2(k7ddrphy_bitslip61[6]),
-	.Q3(k7ddrphy_bitslip61[5]),
-	.Q4(k7ddrphy_bitslip61[4]),
-	.Q5(k7ddrphy_bitslip61[3]),
-	.Q6(k7ddrphy_bitslip61[2]),
-	.Q7(k7ddrphy_bitslip61[1]),
-	.Q8(k7ddrphy_bitslip61[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed6),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip61[7]),
+	.Q2      (main_k7ddrphy_bitslip61[6]),
+	.Q3      (main_k7ddrphy_bitslip61[5]),
+	.Q4      (main_k7ddrphy_bitslip61[4]),
+	.Q5      (main_k7ddrphy_bitslip61[3]),
+	.Q6      (main_k7ddrphy_bitslip61[2]),
+	.Q7      (main_k7ddrphy_bitslip61[1]),
+	.Q8      (main_k7ddrphy_bitslip61[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_40 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_40 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed6),
-	.ODATAIN(k7ddrphy_dq_o_nodelay6)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed6),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay6)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_6 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_6 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay6),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed6)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay6),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed6)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_6 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_6(
-	.I(k7ddrphy_dq_o_delayed6),
-	.T(k7ddrphy_dq_t6),
-	.IO(ddram_dq[6]),
-	.O(k7ddrphy_dq_i_nodelay6)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed6),
+	.T  (main_k7ddrphy_dq_t6),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay6),
+
+	// InOuts.
+	.IO (ddram_dq[6])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_41 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_41 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip70[0]),
-	.D2(k7ddrphy_bitslip70[1]),
-	.D3(k7ddrphy_bitslip70[2]),
-	.D4(k7ddrphy_bitslip70[3]),
-	.D5(k7ddrphy_bitslip70[4]),
-	.D6(k7ddrphy_bitslip70[5]),
-	.D7(k7ddrphy_bitslip70[6]),
-	.D8(k7ddrphy_bitslip70[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay7),
-	.TQ(k7ddrphy_dq_t7)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip70[0]),
+	.D2     (main_k7ddrphy_bitslip70[1]),
+	.D3     (main_k7ddrphy_bitslip70[2]),
+	.D4     (main_k7ddrphy_bitslip70[3]),
+	.D5     (main_k7ddrphy_bitslip70[4]),
+	.D6     (main_k7ddrphy_bitslip70[5]),
+	.D7     (main_k7ddrphy_bitslip70[6]),
+	.D8     (main_k7ddrphy_bitslip70[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay7),
+	.TQ     (main_k7ddrphy_dq_t7)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_7 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_7 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed7),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip71[7]),
-	.Q2(k7ddrphy_bitslip71[6]),
-	.Q3(k7ddrphy_bitslip71[5]),
-	.Q4(k7ddrphy_bitslip71[4]),
-	.Q5(k7ddrphy_bitslip71[3]),
-	.Q6(k7ddrphy_bitslip71[2]),
-	.Q7(k7ddrphy_bitslip71[1]),
-	.Q8(k7ddrphy_bitslip71[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed7),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip71[7]),
+	.Q2      (main_k7ddrphy_bitslip71[6]),
+	.Q3      (main_k7ddrphy_bitslip71[5]),
+	.Q4      (main_k7ddrphy_bitslip71[4]),
+	.Q5      (main_k7ddrphy_bitslip71[3]),
+	.Q6      (main_k7ddrphy_bitslip71[2]),
+	.Q7      (main_k7ddrphy_bitslip71[1]),
+	.Q8      (main_k7ddrphy_bitslip71[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_41 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_41 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed7),
-	.ODATAIN(k7ddrphy_dq_o_nodelay7)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed7),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay7)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_7 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_7 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay7),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed7)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay7),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed7)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_7 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_7(
-	.I(k7ddrphy_dq_o_delayed7),
-	.T(k7ddrphy_dq_t7),
-	.IO(ddram_dq[7]),
-	.O(k7ddrphy_dq_i_nodelay7)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed7),
+	.T  (main_k7ddrphy_dq_t7),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay7),
+
+	// InOuts.
+	.IO (ddram_dq[7])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_42 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_42 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip80[0]),
-	.D2(k7ddrphy_bitslip80[1]),
-	.D3(k7ddrphy_bitslip80[2]),
-	.D4(k7ddrphy_bitslip80[3]),
-	.D5(k7ddrphy_bitslip80[4]),
-	.D6(k7ddrphy_bitslip80[5]),
-	.D7(k7ddrphy_bitslip80[6]),
-	.D8(k7ddrphy_bitslip80[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay8),
-	.TQ(k7ddrphy_dq_t8)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip80[0]),
+	.D2     (main_k7ddrphy_bitslip80[1]),
+	.D3     (main_k7ddrphy_bitslip80[2]),
+	.D4     (main_k7ddrphy_bitslip80[3]),
+	.D5     (main_k7ddrphy_bitslip80[4]),
+	.D6     (main_k7ddrphy_bitslip80[5]),
+	.D7     (main_k7ddrphy_bitslip80[6]),
+	.D8     (main_k7ddrphy_bitslip80[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay8),
+	.TQ     (main_k7ddrphy_dq_t8)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_8 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_8 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed8),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip81[7]),
-	.Q2(k7ddrphy_bitslip81[6]),
-	.Q3(k7ddrphy_bitslip81[5]),
-	.Q4(k7ddrphy_bitslip81[4]),
-	.Q5(k7ddrphy_bitslip81[3]),
-	.Q6(k7ddrphy_bitslip81[2]),
-	.Q7(k7ddrphy_bitslip81[1]),
-	.Q8(k7ddrphy_bitslip81[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed8),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip81[7]),
+	.Q2      (main_k7ddrphy_bitslip81[6]),
+	.Q3      (main_k7ddrphy_bitslip81[5]),
+	.Q4      (main_k7ddrphy_bitslip81[4]),
+	.Q5      (main_k7ddrphy_bitslip81[3]),
+	.Q6      (main_k7ddrphy_bitslip81[2]),
+	.Q7      (main_k7ddrphy_bitslip81[1]),
+	.Q8      (main_k7ddrphy_bitslip81[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_42 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_42 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed8),
-	.ODATAIN(k7ddrphy_dq_o_nodelay8)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed8),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay8)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_8 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_8 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay8),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed8)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay8),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed8)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_8 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_8(
-	.I(k7ddrphy_dq_o_delayed8),
-	.T(k7ddrphy_dq_t8),
-	.IO(ddram_dq[8]),
-	.O(k7ddrphy_dq_i_nodelay8)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed8),
+	.T  (main_k7ddrphy_dq_t8),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay8),
+
+	// InOuts.
+	.IO (ddram_dq[8])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_43 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_43 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip90[0]),
-	.D2(k7ddrphy_bitslip90[1]),
-	.D3(k7ddrphy_bitslip90[2]),
-	.D4(k7ddrphy_bitslip90[3]),
-	.D5(k7ddrphy_bitslip90[4]),
-	.D6(k7ddrphy_bitslip90[5]),
-	.D7(k7ddrphy_bitslip90[6]),
-	.D8(k7ddrphy_bitslip90[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay9),
-	.TQ(k7ddrphy_dq_t9)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip90[0]),
+	.D2     (main_k7ddrphy_bitslip90[1]),
+	.D3     (main_k7ddrphy_bitslip90[2]),
+	.D4     (main_k7ddrphy_bitslip90[3]),
+	.D5     (main_k7ddrphy_bitslip90[4]),
+	.D6     (main_k7ddrphy_bitslip90[5]),
+	.D7     (main_k7ddrphy_bitslip90[6]),
+	.D8     (main_k7ddrphy_bitslip90[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay9),
+	.TQ     (main_k7ddrphy_dq_t9)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_9 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_9 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed9),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip91[7]),
-	.Q2(k7ddrphy_bitslip91[6]),
-	.Q3(k7ddrphy_bitslip91[5]),
-	.Q4(k7ddrphy_bitslip91[4]),
-	.Q5(k7ddrphy_bitslip91[3]),
-	.Q6(k7ddrphy_bitslip91[2]),
-	.Q7(k7ddrphy_bitslip91[1]),
-	.Q8(k7ddrphy_bitslip91[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed9),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip91[7]),
+	.Q2      (main_k7ddrphy_bitslip91[6]),
+	.Q3      (main_k7ddrphy_bitslip91[5]),
+	.Q4      (main_k7ddrphy_bitslip91[4]),
+	.Q5      (main_k7ddrphy_bitslip91[3]),
+	.Q6      (main_k7ddrphy_bitslip91[2]),
+	.Q7      (main_k7ddrphy_bitslip91[1]),
+	.Q8      (main_k7ddrphy_bitslip91[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_43 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_43 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed9),
-	.ODATAIN(k7ddrphy_dq_o_nodelay9)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed9),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay9)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_9 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_9 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay9),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed9)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay9),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed9)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_9 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_9(
-	.I(k7ddrphy_dq_o_delayed9),
-	.T(k7ddrphy_dq_t9),
-	.IO(ddram_dq[9]),
-	.O(k7ddrphy_dq_i_nodelay9)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed9),
+	.T  (main_k7ddrphy_dq_t9),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay9),
+
+	// InOuts.
+	.IO (ddram_dq[9])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_44 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_44 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip100[0]),
-	.D2(k7ddrphy_bitslip100[1]),
-	.D3(k7ddrphy_bitslip100[2]),
-	.D4(k7ddrphy_bitslip100[3]),
-	.D5(k7ddrphy_bitslip100[4]),
-	.D6(k7ddrphy_bitslip100[5]),
-	.D7(k7ddrphy_bitslip100[6]),
-	.D8(k7ddrphy_bitslip100[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay10),
-	.TQ(k7ddrphy_dq_t10)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip100[0]),
+	.D2     (main_k7ddrphy_bitslip100[1]),
+	.D3     (main_k7ddrphy_bitslip100[2]),
+	.D4     (main_k7ddrphy_bitslip100[3]),
+	.D5     (main_k7ddrphy_bitslip100[4]),
+	.D6     (main_k7ddrphy_bitslip100[5]),
+	.D7     (main_k7ddrphy_bitslip100[6]),
+	.D8     (main_k7ddrphy_bitslip100[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay10),
+	.TQ     (main_k7ddrphy_dq_t10)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_10 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_10 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed10),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip101[7]),
-	.Q2(k7ddrphy_bitslip101[6]),
-	.Q3(k7ddrphy_bitslip101[5]),
-	.Q4(k7ddrphy_bitslip101[4]),
-	.Q5(k7ddrphy_bitslip101[3]),
-	.Q6(k7ddrphy_bitslip101[2]),
-	.Q7(k7ddrphy_bitslip101[1]),
-	.Q8(k7ddrphy_bitslip101[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed10),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip101[7]),
+	.Q2      (main_k7ddrphy_bitslip101[6]),
+	.Q3      (main_k7ddrphy_bitslip101[5]),
+	.Q4      (main_k7ddrphy_bitslip101[4]),
+	.Q5      (main_k7ddrphy_bitslip101[3]),
+	.Q6      (main_k7ddrphy_bitslip101[2]),
+	.Q7      (main_k7ddrphy_bitslip101[1]),
+	.Q8      (main_k7ddrphy_bitslip101[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_44 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_44 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed10),
-	.ODATAIN(k7ddrphy_dq_o_nodelay10)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed10),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay10)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_10 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_10 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay10),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed10)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay10),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed10)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_10 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_10(
-	.I(k7ddrphy_dq_o_delayed10),
-	.T(k7ddrphy_dq_t10),
-	.IO(ddram_dq[10]),
-	.O(k7ddrphy_dq_i_nodelay10)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed10),
+	.T  (main_k7ddrphy_dq_t10),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay10),
+
+	// InOuts.
+	.IO (ddram_dq[10])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_45 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_45 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip110[0]),
-	.D2(k7ddrphy_bitslip110[1]),
-	.D3(k7ddrphy_bitslip110[2]),
-	.D4(k7ddrphy_bitslip110[3]),
-	.D5(k7ddrphy_bitslip110[4]),
-	.D6(k7ddrphy_bitslip110[5]),
-	.D7(k7ddrphy_bitslip110[6]),
-	.D8(k7ddrphy_bitslip110[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay11),
-	.TQ(k7ddrphy_dq_t11)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip110[0]),
+	.D2     (main_k7ddrphy_bitslip110[1]),
+	.D3     (main_k7ddrphy_bitslip110[2]),
+	.D4     (main_k7ddrphy_bitslip110[3]),
+	.D5     (main_k7ddrphy_bitslip110[4]),
+	.D6     (main_k7ddrphy_bitslip110[5]),
+	.D7     (main_k7ddrphy_bitslip110[6]),
+	.D8     (main_k7ddrphy_bitslip110[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay11),
+	.TQ     (main_k7ddrphy_dq_t11)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_11 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_11 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed11),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip111[7]),
-	.Q2(k7ddrphy_bitslip111[6]),
-	.Q3(k7ddrphy_bitslip111[5]),
-	.Q4(k7ddrphy_bitslip111[4]),
-	.Q5(k7ddrphy_bitslip111[3]),
-	.Q6(k7ddrphy_bitslip111[2]),
-	.Q7(k7ddrphy_bitslip111[1]),
-	.Q8(k7ddrphy_bitslip111[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed11),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip111[7]),
+	.Q2      (main_k7ddrphy_bitslip111[6]),
+	.Q3      (main_k7ddrphy_bitslip111[5]),
+	.Q4      (main_k7ddrphy_bitslip111[4]),
+	.Q5      (main_k7ddrphy_bitslip111[3]),
+	.Q6      (main_k7ddrphy_bitslip111[2]),
+	.Q7      (main_k7ddrphy_bitslip111[1]),
+	.Q8      (main_k7ddrphy_bitslip111[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_45 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_45 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed11),
-	.ODATAIN(k7ddrphy_dq_o_nodelay11)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed11),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay11)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_11 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_11 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay11),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed11)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay11),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed11)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_11 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_11(
-	.I(k7ddrphy_dq_o_delayed11),
-	.T(k7ddrphy_dq_t11),
-	.IO(ddram_dq[11]),
-	.O(k7ddrphy_dq_i_nodelay11)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed11),
+	.T  (main_k7ddrphy_dq_t11),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay11),
+
+	// InOuts.
+	.IO (ddram_dq[11])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_46 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_46 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip120[0]),
-	.D2(k7ddrphy_bitslip120[1]),
-	.D3(k7ddrphy_bitslip120[2]),
-	.D4(k7ddrphy_bitslip120[3]),
-	.D5(k7ddrphy_bitslip120[4]),
-	.D6(k7ddrphy_bitslip120[5]),
-	.D7(k7ddrphy_bitslip120[6]),
-	.D8(k7ddrphy_bitslip120[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay12),
-	.TQ(k7ddrphy_dq_t12)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip120[0]),
+	.D2     (main_k7ddrphy_bitslip120[1]),
+	.D3     (main_k7ddrphy_bitslip120[2]),
+	.D4     (main_k7ddrphy_bitslip120[3]),
+	.D5     (main_k7ddrphy_bitslip120[4]),
+	.D6     (main_k7ddrphy_bitslip120[5]),
+	.D7     (main_k7ddrphy_bitslip120[6]),
+	.D8     (main_k7ddrphy_bitslip120[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay12),
+	.TQ     (main_k7ddrphy_dq_t12)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_12 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_12 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed12),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip121[7]),
-	.Q2(k7ddrphy_bitslip121[6]),
-	.Q3(k7ddrphy_bitslip121[5]),
-	.Q4(k7ddrphy_bitslip121[4]),
-	.Q5(k7ddrphy_bitslip121[3]),
-	.Q6(k7ddrphy_bitslip121[2]),
-	.Q7(k7ddrphy_bitslip121[1]),
-	.Q8(k7ddrphy_bitslip121[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed12),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip121[7]),
+	.Q2      (main_k7ddrphy_bitslip121[6]),
+	.Q3      (main_k7ddrphy_bitslip121[5]),
+	.Q4      (main_k7ddrphy_bitslip121[4]),
+	.Q5      (main_k7ddrphy_bitslip121[3]),
+	.Q6      (main_k7ddrphy_bitslip121[2]),
+	.Q7      (main_k7ddrphy_bitslip121[1]),
+	.Q8      (main_k7ddrphy_bitslip121[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_46 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_46 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed12),
-	.ODATAIN(k7ddrphy_dq_o_nodelay12)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed12),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay12)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_12 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_12 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay12),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed12)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay12),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed12)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_12 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_12(
-	.I(k7ddrphy_dq_o_delayed12),
-	.T(k7ddrphy_dq_t12),
-	.IO(ddram_dq[12]),
-	.O(k7ddrphy_dq_i_nodelay12)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed12),
+	.T  (main_k7ddrphy_dq_t12),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay12),
+
+	// InOuts.
+	.IO (ddram_dq[12])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_47 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_47 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip130[0]),
-	.D2(k7ddrphy_bitslip130[1]),
-	.D3(k7ddrphy_bitslip130[2]),
-	.D4(k7ddrphy_bitslip130[3]),
-	.D5(k7ddrphy_bitslip130[4]),
-	.D6(k7ddrphy_bitslip130[5]),
-	.D7(k7ddrphy_bitslip130[6]),
-	.D8(k7ddrphy_bitslip130[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay13),
-	.TQ(k7ddrphy_dq_t13)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip130[0]),
+	.D2     (main_k7ddrphy_bitslip130[1]),
+	.D3     (main_k7ddrphy_bitslip130[2]),
+	.D4     (main_k7ddrphy_bitslip130[3]),
+	.D5     (main_k7ddrphy_bitslip130[4]),
+	.D6     (main_k7ddrphy_bitslip130[5]),
+	.D7     (main_k7ddrphy_bitslip130[6]),
+	.D8     (main_k7ddrphy_bitslip130[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay13),
+	.TQ     (main_k7ddrphy_dq_t13)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_13 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_13 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed13),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip131[7]),
-	.Q2(k7ddrphy_bitslip131[6]),
-	.Q3(k7ddrphy_bitslip131[5]),
-	.Q4(k7ddrphy_bitslip131[4]),
-	.Q5(k7ddrphy_bitslip131[3]),
-	.Q6(k7ddrphy_bitslip131[2]),
-	.Q7(k7ddrphy_bitslip131[1]),
-	.Q8(k7ddrphy_bitslip131[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed13),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip131[7]),
+	.Q2      (main_k7ddrphy_bitslip131[6]),
+	.Q3      (main_k7ddrphy_bitslip131[5]),
+	.Q4      (main_k7ddrphy_bitslip131[4]),
+	.Q5      (main_k7ddrphy_bitslip131[3]),
+	.Q6      (main_k7ddrphy_bitslip131[2]),
+	.Q7      (main_k7ddrphy_bitslip131[1]),
+	.Q8      (main_k7ddrphy_bitslip131[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_47 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_47 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed13),
-	.ODATAIN(k7ddrphy_dq_o_nodelay13)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed13),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay13)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_13 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_13 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay13),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed13)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay13),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed13)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_13 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_13(
-	.I(k7ddrphy_dq_o_delayed13),
-	.T(k7ddrphy_dq_t13),
-	.IO(ddram_dq[13]),
-	.O(k7ddrphy_dq_i_nodelay13)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed13),
+	.T  (main_k7ddrphy_dq_t13),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay13),
+
+	// InOuts.
+	.IO (ddram_dq[13])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_48 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_48 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip140[0]),
-	.D2(k7ddrphy_bitslip140[1]),
-	.D3(k7ddrphy_bitslip140[2]),
-	.D4(k7ddrphy_bitslip140[3]),
-	.D5(k7ddrphy_bitslip140[4]),
-	.D6(k7ddrphy_bitslip140[5]),
-	.D7(k7ddrphy_bitslip140[6]),
-	.D8(k7ddrphy_bitslip140[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay14),
-	.TQ(k7ddrphy_dq_t14)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip140[0]),
+	.D2     (main_k7ddrphy_bitslip140[1]),
+	.D3     (main_k7ddrphy_bitslip140[2]),
+	.D4     (main_k7ddrphy_bitslip140[3]),
+	.D5     (main_k7ddrphy_bitslip140[4]),
+	.D6     (main_k7ddrphy_bitslip140[5]),
+	.D7     (main_k7ddrphy_bitslip140[6]),
+	.D8     (main_k7ddrphy_bitslip140[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay14),
+	.TQ     (main_k7ddrphy_dq_t14)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_14 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_14 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed14),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip141[7]),
-	.Q2(k7ddrphy_bitslip141[6]),
-	.Q3(k7ddrphy_bitslip141[5]),
-	.Q4(k7ddrphy_bitslip141[4]),
-	.Q5(k7ddrphy_bitslip141[3]),
-	.Q6(k7ddrphy_bitslip141[2]),
-	.Q7(k7ddrphy_bitslip141[1]),
-	.Q8(k7ddrphy_bitslip141[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed14),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip141[7]),
+	.Q2      (main_k7ddrphy_bitslip141[6]),
+	.Q3      (main_k7ddrphy_bitslip141[5]),
+	.Q4      (main_k7ddrphy_bitslip141[4]),
+	.Q5      (main_k7ddrphy_bitslip141[3]),
+	.Q6      (main_k7ddrphy_bitslip141[2]),
+	.Q7      (main_k7ddrphy_bitslip141[1]),
+	.Q8      (main_k7ddrphy_bitslip141[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_48 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_48 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed14),
-	.ODATAIN(k7ddrphy_dq_o_nodelay14)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed14),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay14)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_14 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_14 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay14),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed14)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay14),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed14)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_14 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_14(
-	.I(k7ddrphy_dq_o_delayed14),
-	.T(k7ddrphy_dq_t14),
-	.IO(ddram_dq[14]),
-	.O(k7ddrphy_dq_i_nodelay14)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed14),
+	.T  (main_k7ddrphy_dq_t14),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay14),
+
+	// InOuts.
+	.IO (ddram_dq[14])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_49 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_49 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip150[0]),
-	.D2(k7ddrphy_bitslip150[1]),
-	.D3(k7ddrphy_bitslip150[2]),
-	.D4(k7ddrphy_bitslip150[3]),
-	.D5(k7ddrphy_bitslip150[4]),
-	.D6(k7ddrphy_bitslip150[5]),
-	.D7(k7ddrphy_bitslip150[6]),
-	.D8(k7ddrphy_bitslip150[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay15),
-	.TQ(k7ddrphy_dq_t15)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip150[0]),
+	.D2     (main_k7ddrphy_bitslip150[1]),
+	.D3     (main_k7ddrphy_bitslip150[2]),
+	.D4     (main_k7ddrphy_bitslip150[3]),
+	.D5     (main_k7ddrphy_bitslip150[4]),
+	.D6     (main_k7ddrphy_bitslip150[5]),
+	.D7     (main_k7ddrphy_bitslip150[6]),
+	.D8     (main_k7ddrphy_bitslip150[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay15),
+	.TQ     (main_k7ddrphy_dq_t15)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_15 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_15 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed15),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip151[7]),
-	.Q2(k7ddrphy_bitslip151[6]),
-	.Q3(k7ddrphy_bitslip151[5]),
-	.Q4(k7ddrphy_bitslip151[4]),
-	.Q5(k7ddrphy_bitslip151[3]),
-	.Q6(k7ddrphy_bitslip151[2]),
-	.Q7(k7ddrphy_bitslip151[1]),
-	.Q8(k7ddrphy_bitslip151[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed15),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip151[7]),
+	.Q2      (main_k7ddrphy_bitslip151[6]),
+	.Q3      (main_k7ddrphy_bitslip151[5]),
+	.Q4      (main_k7ddrphy_bitslip151[4]),
+	.Q5      (main_k7ddrphy_bitslip151[3]),
+	.Q6      (main_k7ddrphy_bitslip151[2]),
+	.Q7      (main_k7ddrphy_bitslip151[1]),
+	.Q8      (main_k7ddrphy_bitslip151[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_49 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_49 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed15),
-	.ODATAIN(k7ddrphy_dq_o_nodelay15)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed15),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay15)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_15 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_15 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay15),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed15)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay15),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed15)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_15 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_15(
-	.I(k7ddrphy_dq_o_delayed15),
-	.T(k7ddrphy_dq_t15),
-	.IO(ddram_dq[15]),
-	.O(k7ddrphy_dq_i_nodelay15)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed15),
+	.T  (main_k7ddrphy_dq_t15),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay15),
+
+	// InOuts.
+	.IO (ddram_dq[15])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_50 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_50 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip160[0]),
-	.D2(k7ddrphy_bitslip160[1]),
-	.D3(k7ddrphy_bitslip160[2]),
-	.D4(k7ddrphy_bitslip160[3]),
-	.D5(k7ddrphy_bitslip160[4]),
-	.D6(k7ddrphy_bitslip160[5]),
-	.D7(k7ddrphy_bitslip160[6]),
-	.D8(k7ddrphy_bitslip160[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay16),
-	.TQ(k7ddrphy_dq_t16)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip160[0]),
+	.D2     (main_k7ddrphy_bitslip160[1]),
+	.D3     (main_k7ddrphy_bitslip160[2]),
+	.D4     (main_k7ddrphy_bitslip160[3]),
+	.D5     (main_k7ddrphy_bitslip160[4]),
+	.D6     (main_k7ddrphy_bitslip160[5]),
+	.D7     (main_k7ddrphy_bitslip160[6]),
+	.D8     (main_k7ddrphy_bitslip160[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay16),
+	.TQ     (main_k7ddrphy_dq_t16)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_16 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_16 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed16),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip161[7]),
-	.Q2(k7ddrphy_bitslip161[6]),
-	.Q3(k7ddrphy_bitslip161[5]),
-	.Q4(k7ddrphy_bitslip161[4]),
-	.Q5(k7ddrphy_bitslip161[3]),
-	.Q6(k7ddrphy_bitslip161[2]),
-	.Q7(k7ddrphy_bitslip161[1]),
-	.Q8(k7ddrphy_bitslip161[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed16),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip161[7]),
+	.Q2      (main_k7ddrphy_bitslip161[6]),
+	.Q3      (main_k7ddrphy_bitslip161[5]),
+	.Q4      (main_k7ddrphy_bitslip161[4]),
+	.Q5      (main_k7ddrphy_bitslip161[3]),
+	.Q6      (main_k7ddrphy_bitslip161[2]),
+	.Q7      (main_k7ddrphy_bitslip161[1]),
+	.Q8      (main_k7ddrphy_bitslip161[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_50 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_50 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed16),
-	.ODATAIN(k7ddrphy_dq_o_nodelay16)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed16),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay16)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_16 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_16 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay16),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed16)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay16),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed16)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_16 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_16(
-	.I(k7ddrphy_dq_o_delayed16),
-	.T(k7ddrphy_dq_t16),
-	.IO(ddram_dq[16]),
-	.O(k7ddrphy_dq_i_nodelay16)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed16),
+	.T  (main_k7ddrphy_dq_t16),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay16),
+
+	// InOuts.
+	.IO (ddram_dq[16])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_51 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_51 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip170[0]),
-	.D2(k7ddrphy_bitslip170[1]),
-	.D3(k7ddrphy_bitslip170[2]),
-	.D4(k7ddrphy_bitslip170[3]),
-	.D5(k7ddrphy_bitslip170[4]),
-	.D6(k7ddrphy_bitslip170[5]),
-	.D7(k7ddrphy_bitslip170[6]),
-	.D8(k7ddrphy_bitslip170[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay17),
-	.TQ(k7ddrphy_dq_t17)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip170[0]),
+	.D2     (main_k7ddrphy_bitslip170[1]),
+	.D3     (main_k7ddrphy_bitslip170[2]),
+	.D4     (main_k7ddrphy_bitslip170[3]),
+	.D5     (main_k7ddrphy_bitslip170[4]),
+	.D6     (main_k7ddrphy_bitslip170[5]),
+	.D7     (main_k7ddrphy_bitslip170[6]),
+	.D8     (main_k7ddrphy_bitslip170[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay17),
+	.TQ     (main_k7ddrphy_dq_t17)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_17 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_17 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed17),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip171[7]),
-	.Q2(k7ddrphy_bitslip171[6]),
-	.Q3(k7ddrphy_bitslip171[5]),
-	.Q4(k7ddrphy_bitslip171[4]),
-	.Q5(k7ddrphy_bitslip171[3]),
-	.Q6(k7ddrphy_bitslip171[2]),
-	.Q7(k7ddrphy_bitslip171[1]),
-	.Q8(k7ddrphy_bitslip171[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed17),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip171[7]),
+	.Q2      (main_k7ddrphy_bitslip171[6]),
+	.Q3      (main_k7ddrphy_bitslip171[5]),
+	.Q4      (main_k7ddrphy_bitslip171[4]),
+	.Q5      (main_k7ddrphy_bitslip171[3]),
+	.Q6      (main_k7ddrphy_bitslip171[2]),
+	.Q7      (main_k7ddrphy_bitslip171[1]),
+	.Q8      (main_k7ddrphy_bitslip171[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_51 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_51 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed17),
-	.ODATAIN(k7ddrphy_dq_o_nodelay17)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed17),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay17)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_17 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_17 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay17),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed17)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay17),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed17)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_17 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_17(
-	.I(k7ddrphy_dq_o_delayed17),
-	.T(k7ddrphy_dq_t17),
-	.IO(ddram_dq[17]),
-	.O(k7ddrphy_dq_i_nodelay17)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed17),
+	.T  (main_k7ddrphy_dq_t17),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay17),
+
+	// InOuts.
+	.IO (ddram_dq[17])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_52 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_52 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip180[0]),
-	.D2(k7ddrphy_bitslip180[1]),
-	.D3(k7ddrphy_bitslip180[2]),
-	.D4(k7ddrphy_bitslip180[3]),
-	.D5(k7ddrphy_bitslip180[4]),
-	.D6(k7ddrphy_bitslip180[5]),
-	.D7(k7ddrphy_bitslip180[6]),
-	.D8(k7ddrphy_bitslip180[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay18),
-	.TQ(k7ddrphy_dq_t18)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip180[0]),
+	.D2     (main_k7ddrphy_bitslip180[1]),
+	.D3     (main_k7ddrphy_bitslip180[2]),
+	.D4     (main_k7ddrphy_bitslip180[3]),
+	.D5     (main_k7ddrphy_bitslip180[4]),
+	.D6     (main_k7ddrphy_bitslip180[5]),
+	.D7     (main_k7ddrphy_bitslip180[6]),
+	.D8     (main_k7ddrphy_bitslip180[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay18),
+	.TQ     (main_k7ddrphy_dq_t18)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_18 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_18 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed18),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip181[7]),
-	.Q2(k7ddrphy_bitslip181[6]),
-	.Q3(k7ddrphy_bitslip181[5]),
-	.Q4(k7ddrphy_bitslip181[4]),
-	.Q5(k7ddrphy_bitslip181[3]),
-	.Q6(k7ddrphy_bitslip181[2]),
-	.Q7(k7ddrphy_bitslip181[1]),
-	.Q8(k7ddrphy_bitslip181[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed18),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip181[7]),
+	.Q2      (main_k7ddrphy_bitslip181[6]),
+	.Q3      (main_k7ddrphy_bitslip181[5]),
+	.Q4      (main_k7ddrphy_bitslip181[4]),
+	.Q5      (main_k7ddrphy_bitslip181[3]),
+	.Q6      (main_k7ddrphy_bitslip181[2]),
+	.Q7      (main_k7ddrphy_bitslip181[1]),
+	.Q8      (main_k7ddrphy_bitslip181[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_52 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_52 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed18),
-	.ODATAIN(k7ddrphy_dq_o_nodelay18)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed18),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay18)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_18 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_18 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay18),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed18)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay18),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed18)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_18 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_18(
-	.I(k7ddrphy_dq_o_delayed18),
-	.T(k7ddrphy_dq_t18),
-	.IO(ddram_dq[18]),
-	.O(k7ddrphy_dq_i_nodelay18)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed18),
+	.T  (main_k7ddrphy_dq_t18),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay18),
+
+	// InOuts.
+	.IO (ddram_dq[18])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_53 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_53 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip190[0]),
-	.D2(k7ddrphy_bitslip190[1]),
-	.D3(k7ddrphy_bitslip190[2]),
-	.D4(k7ddrphy_bitslip190[3]),
-	.D5(k7ddrphy_bitslip190[4]),
-	.D6(k7ddrphy_bitslip190[5]),
-	.D7(k7ddrphy_bitslip190[6]),
-	.D8(k7ddrphy_bitslip190[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay19),
-	.TQ(k7ddrphy_dq_t19)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip190[0]),
+	.D2     (main_k7ddrphy_bitslip190[1]),
+	.D3     (main_k7ddrphy_bitslip190[2]),
+	.D4     (main_k7ddrphy_bitslip190[3]),
+	.D5     (main_k7ddrphy_bitslip190[4]),
+	.D6     (main_k7ddrphy_bitslip190[5]),
+	.D7     (main_k7ddrphy_bitslip190[6]),
+	.D8     (main_k7ddrphy_bitslip190[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay19),
+	.TQ     (main_k7ddrphy_dq_t19)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_19 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_19 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed19),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip191[7]),
-	.Q2(k7ddrphy_bitslip191[6]),
-	.Q3(k7ddrphy_bitslip191[5]),
-	.Q4(k7ddrphy_bitslip191[4]),
-	.Q5(k7ddrphy_bitslip191[3]),
-	.Q6(k7ddrphy_bitslip191[2]),
-	.Q7(k7ddrphy_bitslip191[1]),
-	.Q8(k7ddrphy_bitslip191[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed19),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip191[7]),
+	.Q2      (main_k7ddrphy_bitslip191[6]),
+	.Q3      (main_k7ddrphy_bitslip191[5]),
+	.Q4      (main_k7ddrphy_bitslip191[4]),
+	.Q5      (main_k7ddrphy_bitslip191[3]),
+	.Q6      (main_k7ddrphy_bitslip191[2]),
+	.Q7      (main_k7ddrphy_bitslip191[1]),
+	.Q8      (main_k7ddrphy_bitslip191[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_53 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_53 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed19),
-	.ODATAIN(k7ddrphy_dq_o_nodelay19)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed19),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay19)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_19 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_19 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay19),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed19)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay19),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed19)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_19 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_19(
-	.I(k7ddrphy_dq_o_delayed19),
-	.T(k7ddrphy_dq_t19),
-	.IO(ddram_dq[19]),
-	.O(k7ddrphy_dq_i_nodelay19)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed19),
+	.T  (main_k7ddrphy_dq_t19),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay19),
+
+	// InOuts.
+	.IO (ddram_dq[19])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_54 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_54 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip200[0]),
-	.D2(k7ddrphy_bitslip200[1]),
-	.D3(k7ddrphy_bitslip200[2]),
-	.D4(k7ddrphy_bitslip200[3]),
-	.D5(k7ddrphy_bitslip200[4]),
-	.D6(k7ddrphy_bitslip200[5]),
-	.D7(k7ddrphy_bitslip200[6]),
-	.D8(k7ddrphy_bitslip200[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay20),
-	.TQ(k7ddrphy_dq_t20)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip200[0]),
+	.D2     (main_k7ddrphy_bitslip200[1]),
+	.D3     (main_k7ddrphy_bitslip200[2]),
+	.D4     (main_k7ddrphy_bitslip200[3]),
+	.D5     (main_k7ddrphy_bitslip200[4]),
+	.D6     (main_k7ddrphy_bitslip200[5]),
+	.D7     (main_k7ddrphy_bitslip200[6]),
+	.D8     (main_k7ddrphy_bitslip200[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay20),
+	.TQ     (main_k7ddrphy_dq_t20)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_20 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_20 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed20),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip201[7]),
-	.Q2(k7ddrphy_bitslip201[6]),
-	.Q3(k7ddrphy_bitslip201[5]),
-	.Q4(k7ddrphy_bitslip201[4]),
-	.Q5(k7ddrphy_bitslip201[3]),
-	.Q6(k7ddrphy_bitslip201[2]),
-	.Q7(k7ddrphy_bitslip201[1]),
-	.Q8(k7ddrphy_bitslip201[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed20),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip201[7]),
+	.Q2      (main_k7ddrphy_bitslip201[6]),
+	.Q3      (main_k7ddrphy_bitslip201[5]),
+	.Q4      (main_k7ddrphy_bitslip201[4]),
+	.Q5      (main_k7ddrphy_bitslip201[3]),
+	.Q6      (main_k7ddrphy_bitslip201[2]),
+	.Q7      (main_k7ddrphy_bitslip201[1]),
+	.Q8      (main_k7ddrphy_bitslip201[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_54 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_54 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed20),
-	.ODATAIN(k7ddrphy_dq_o_nodelay20)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed20),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay20)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_20 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_20 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay20),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed20)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay20),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed20)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_20 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_20(
-	.I(k7ddrphy_dq_o_delayed20),
-	.T(k7ddrphy_dq_t20),
-	.IO(ddram_dq[20]),
-	.O(k7ddrphy_dq_i_nodelay20)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed20),
+	.T  (main_k7ddrphy_dq_t20),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay20),
+
+	// InOuts.
+	.IO (ddram_dq[20])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_55 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_55 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip210[0]),
-	.D2(k7ddrphy_bitslip210[1]),
-	.D3(k7ddrphy_bitslip210[2]),
-	.D4(k7ddrphy_bitslip210[3]),
-	.D5(k7ddrphy_bitslip210[4]),
-	.D6(k7ddrphy_bitslip210[5]),
-	.D7(k7ddrphy_bitslip210[6]),
-	.D8(k7ddrphy_bitslip210[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay21),
-	.TQ(k7ddrphy_dq_t21)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip210[0]),
+	.D2     (main_k7ddrphy_bitslip210[1]),
+	.D3     (main_k7ddrphy_bitslip210[2]),
+	.D4     (main_k7ddrphy_bitslip210[3]),
+	.D5     (main_k7ddrphy_bitslip210[4]),
+	.D6     (main_k7ddrphy_bitslip210[5]),
+	.D7     (main_k7ddrphy_bitslip210[6]),
+	.D8     (main_k7ddrphy_bitslip210[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay21),
+	.TQ     (main_k7ddrphy_dq_t21)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_21 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_21 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed21),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip211[7]),
-	.Q2(k7ddrphy_bitslip211[6]),
-	.Q3(k7ddrphy_bitslip211[5]),
-	.Q4(k7ddrphy_bitslip211[4]),
-	.Q5(k7ddrphy_bitslip211[3]),
-	.Q6(k7ddrphy_bitslip211[2]),
-	.Q7(k7ddrphy_bitslip211[1]),
-	.Q8(k7ddrphy_bitslip211[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed21),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip211[7]),
+	.Q2      (main_k7ddrphy_bitslip211[6]),
+	.Q3      (main_k7ddrphy_bitslip211[5]),
+	.Q4      (main_k7ddrphy_bitslip211[4]),
+	.Q5      (main_k7ddrphy_bitslip211[3]),
+	.Q6      (main_k7ddrphy_bitslip211[2]),
+	.Q7      (main_k7ddrphy_bitslip211[1]),
+	.Q8      (main_k7ddrphy_bitslip211[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_55 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_55 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed21),
-	.ODATAIN(k7ddrphy_dq_o_nodelay21)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed21),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay21)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_21 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_21 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay21),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed21)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay21),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed21)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_21 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_21(
-	.I(k7ddrphy_dq_o_delayed21),
-	.T(k7ddrphy_dq_t21),
-	.IO(ddram_dq[21]),
-	.O(k7ddrphy_dq_i_nodelay21)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed21),
+	.T  (main_k7ddrphy_dq_t21),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay21),
+
+	// InOuts.
+	.IO (ddram_dq[21])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_56 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_56 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip220[0]),
-	.D2(k7ddrphy_bitslip220[1]),
-	.D3(k7ddrphy_bitslip220[2]),
-	.D4(k7ddrphy_bitslip220[3]),
-	.D5(k7ddrphy_bitslip220[4]),
-	.D6(k7ddrphy_bitslip220[5]),
-	.D7(k7ddrphy_bitslip220[6]),
-	.D8(k7ddrphy_bitslip220[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay22),
-	.TQ(k7ddrphy_dq_t22)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip220[0]),
+	.D2     (main_k7ddrphy_bitslip220[1]),
+	.D3     (main_k7ddrphy_bitslip220[2]),
+	.D4     (main_k7ddrphy_bitslip220[3]),
+	.D5     (main_k7ddrphy_bitslip220[4]),
+	.D6     (main_k7ddrphy_bitslip220[5]),
+	.D7     (main_k7ddrphy_bitslip220[6]),
+	.D8     (main_k7ddrphy_bitslip220[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay22),
+	.TQ     (main_k7ddrphy_dq_t22)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_22 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_22 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed22),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip221[7]),
-	.Q2(k7ddrphy_bitslip221[6]),
-	.Q3(k7ddrphy_bitslip221[5]),
-	.Q4(k7ddrphy_bitslip221[4]),
-	.Q5(k7ddrphy_bitslip221[3]),
-	.Q6(k7ddrphy_bitslip221[2]),
-	.Q7(k7ddrphy_bitslip221[1]),
-	.Q8(k7ddrphy_bitslip221[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed22),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip221[7]),
+	.Q2      (main_k7ddrphy_bitslip221[6]),
+	.Q3      (main_k7ddrphy_bitslip221[5]),
+	.Q4      (main_k7ddrphy_bitslip221[4]),
+	.Q5      (main_k7ddrphy_bitslip221[3]),
+	.Q6      (main_k7ddrphy_bitslip221[2]),
+	.Q7      (main_k7ddrphy_bitslip221[1]),
+	.Q8      (main_k7ddrphy_bitslip221[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_56 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_56 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed22),
-	.ODATAIN(k7ddrphy_dq_o_nodelay22)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed22),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay22)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_22 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_22 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay22),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed22)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay22),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed22)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_22 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_22(
-	.I(k7ddrphy_dq_o_delayed22),
-	.T(k7ddrphy_dq_t22),
-	.IO(ddram_dq[22]),
-	.O(k7ddrphy_dq_i_nodelay22)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed22),
+	.T  (main_k7ddrphy_dq_t22),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay22),
+
+	// InOuts.
+	.IO (ddram_dq[22])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_57 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_57 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip230[0]),
-	.D2(k7ddrphy_bitslip230[1]),
-	.D3(k7ddrphy_bitslip230[2]),
-	.D4(k7ddrphy_bitslip230[3]),
-	.D5(k7ddrphy_bitslip230[4]),
-	.D6(k7ddrphy_bitslip230[5]),
-	.D7(k7ddrphy_bitslip230[6]),
-	.D8(k7ddrphy_bitslip230[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay23),
-	.TQ(k7ddrphy_dq_t23)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip230[0]),
+	.D2     (main_k7ddrphy_bitslip230[1]),
+	.D3     (main_k7ddrphy_bitslip230[2]),
+	.D4     (main_k7ddrphy_bitslip230[3]),
+	.D5     (main_k7ddrphy_bitslip230[4]),
+	.D6     (main_k7ddrphy_bitslip230[5]),
+	.D7     (main_k7ddrphy_bitslip230[6]),
+	.D8     (main_k7ddrphy_bitslip230[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay23),
+	.TQ     (main_k7ddrphy_dq_t23)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_23 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_23 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed23),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip231[7]),
-	.Q2(k7ddrphy_bitslip231[6]),
-	.Q3(k7ddrphy_bitslip231[5]),
-	.Q4(k7ddrphy_bitslip231[4]),
-	.Q5(k7ddrphy_bitslip231[3]),
-	.Q6(k7ddrphy_bitslip231[2]),
-	.Q7(k7ddrphy_bitslip231[1]),
-	.Q8(k7ddrphy_bitslip231[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed23),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip231[7]),
+	.Q2      (main_k7ddrphy_bitslip231[6]),
+	.Q3      (main_k7ddrphy_bitslip231[5]),
+	.Q4      (main_k7ddrphy_bitslip231[4]),
+	.Q5      (main_k7ddrphy_bitslip231[3]),
+	.Q6      (main_k7ddrphy_bitslip231[2]),
+	.Q7      (main_k7ddrphy_bitslip231[1]),
+	.Q8      (main_k7ddrphy_bitslip231[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_57 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_57 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed23),
-	.ODATAIN(k7ddrphy_dq_o_nodelay23)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed23),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay23)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_23 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_23 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay23),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed23)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay23),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed23)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_23 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_23(
-	.I(k7ddrphy_dq_o_delayed23),
-	.T(k7ddrphy_dq_t23),
-	.IO(ddram_dq[23]),
-	.O(k7ddrphy_dq_i_nodelay23)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed23),
+	.T  (main_k7ddrphy_dq_t23),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay23),
+
+	// InOuts.
+	.IO (ddram_dq[23])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_58 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_58 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip240[0]),
-	.D2(k7ddrphy_bitslip240[1]),
-	.D3(k7ddrphy_bitslip240[2]),
-	.D4(k7ddrphy_bitslip240[3]),
-	.D5(k7ddrphy_bitslip240[4]),
-	.D6(k7ddrphy_bitslip240[5]),
-	.D7(k7ddrphy_bitslip240[6]),
-	.D8(k7ddrphy_bitslip240[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay24),
-	.TQ(k7ddrphy_dq_t24)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip240[0]),
+	.D2     (main_k7ddrphy_bitslip240[1]),
+	.D3     (main_k7ddrphy_bitslip240[2]),
+	.D4     (main_k7ddrphy_bitslip240[3]),
+	.D5     (main_k7ddrphy_bitslip240[4]),
+	.D6     (main_k7ddrphy_bitslip240[5]),
+	.D7     (main_k7ddrphy_bitslip240[6]),
+	.D8     (main_k7ddrphy_bitslip240[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay24),
+	.TQ     (main_k7ddrphy_dq_t24)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_24 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_24 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed24),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip241[7]),
-	.Q2(k7ddrphy_bitslip241[6]),
-	.Q3(k7ddrphy_bitslip241[5]),
-	.Q4(k7ddrphy_bitslip241[4]),
-	.Q5(k7ddrphy_bitslip241[3]),
-	.Q6(k7ddrphy_bitslip241[2]),
-	.Q7(k7ddrphy_bitslip241[1]),
-	.Q8(k7ddrphy_bitslip241[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed24),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip241[7]),
+	.Q2      (main_k7ddrphy_bitslip241[6]),
+	.Q3      (main_k7ddrphy_bitslip241[5]),
+	.Q4      (main_k7ddrphy_bitslip241[4]),
+	.Q5      (main_k7ddrphy_bitslip241[3]),
+	.Q6      (main_k7ddrphy_bitslip241[2]),
+	.Q7      (main_k7ddrphy_bitslip241[1]),
+	.Q8      (main_k7ddrphy_bitslip241[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_58 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_58 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed24),
-	.ODATAIN(k7ddrphy_dq_o_nodelay24)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed24),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay24)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_24 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_24 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay24),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed24)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay24),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed24)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_24 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_24(
-	.I(k7ddrphy_dq_o_delayed24),
-	.T(k7ddrphy_dq_t24),
-	.IO(ddram_dq[24]),
-	.O(k7ddrphy_dq_i_nodelay24)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed24),
+	.T  (main_k7ddrphy_dq_t24),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay24),
+
+	// InOuts.
+	.IO (ddram_dq[24])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_59 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_59 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip250[0]),
-	.D2(k7ddrphy_bitslip250[1]),
-	.D3(k7ddrphy_bitslip250[2]),
-	.D4(k7ddrphy_bitslip250[3]),
-	.D5(k7ddrphy_bitslip250[4]),
-	.D6(k7ddrphy_bitslip250[5]),
-	.D7(k7ddrphy_bitslip250[6]),
-	.D8(k7ddrphy_bitslip250[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay25),
-	.TQ(k7ddrphy_dq_t25)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip250[0]),
+	.D2     (main_k7ddrphy_bitslip250[1]),
+	.D3     (main_k7ddrphy_bitslip250[2]),
+	.D4     (main_k7ddrphy_bitslip250[3]),
+	.D5     (main_k7ddrphy_bitslip250[4]),
+	.D6     (main_k7ddrphy_bitslip250[5]),
+	.D7     (main_k7ddrphy_bitslip250[6]),
+	.D8     (main_k7ddrphy_bitslip250[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay25),
+	.TQ     (main_k7ddrphy_dq_t25)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_25 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_25 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed25),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip251[7]),
-	.Q2(k7ddrphy_bitslip251[6]),
-	.Q3(k7ddrphy_bitslip251[5]),
-	.Q4(k7ddrphy_bitslip251[4]),
-	.Q5(k7ddrphy_bitslip251[3]),
-	.Q6(k7ddrphy_bitslip251[2]),
-	.Q7(k7ddrphy_bitslip251[1]),
-	.Q8(k7ddrphy_bitslip251[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed25),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip251[7]),
+	.Q2      (main_k7ddrphy_bitslip251[6]),
+	.Q3      (main_k7ddrphy_bitslip251[5]),
+	.Q4      (main_k7ddrphy_bitslip251[4]),
+	.Q5      (main_k7ddrphy_bitslip251[3]),
+	.Q6      (main_k7ddrphy_bitslip251[2]),
+	.Q7      (main_k7ddrphy_bitslip251[1]),
+	.Q8      (main_k7ddrphy_bitslip251[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_59 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_59 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed25),
-	.ODATAIN(k7ddrphy_dq_o_nodelay25)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed25),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay25)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_25 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_25 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay25),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed25)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay25),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed25)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_25 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_25(
-	.I(k7ddrphy_dq_o_delayed25),
-	.T(k7ddrphy_dq_t25),
-	.IO(ddram_dq[25]),
-	.O(k7ddrphy_dq_i_nodelay25)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed25),
+	.T  (main_k7ddrphy_dq_t25),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay25),
+
+	// InOuts.
+	.IO (ddram_dq[25])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_60 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_60 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip260[0]),
-	.D2(k7ddrphy_bitslip260[1]),
-	.D3(k7ddrphy_bitslip260[2]),
-	.D4(k7ddrphy_bitslip260[3]),
-	.D5(k7ddrphy_bitslip260[4]),
-	.D6(k7ddrphy_bitslip260[5]),
-	.D7(k7ddrphy_bitslip260[6]),
-	.D8(k7ddrphy_bitslip260[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay26),
-	.TQ(k7ddrphy_dq_t26)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip260[0]),
+	.D2     (main_k7ddrphy_bitslip260[1]),
+	.D3     (main_k7ddrphy_bitslip260[2]),
+	.D4     (main_k7ddrphy_bitslip260[3]),
+	.D5     (main_k7ddrphy_bitslip260[4]),
+	.D6     (main_k7ddrphy_bitslip260[5]),
+	.D7     (main_k7ddrphy_bitslip260[6]),
+	.D8     (main_k7ddrphy_bitslip260[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay26),
+	.TQ     (main_k7ddrphy_dq_t26)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_26 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_26 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed26),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip261[7]),
-	.Q2(k7ddrphy_bitslip261[6]),
-	.Q3(k7ddrphy_bitslip261[5]),
-	.Q4(k7ddrphy_bitslip261[4]),
-	.Q5(k7ddrphy_bitslip261[3]),
-	.Q6(k7ddrphy_bitslip261[2]),
-	.Q7(k7ddrphy_bitslip261[1]),
-	.Q8(k7ddrphy_bitslip261[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed26),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip261[7]),
+	.Q2      (main_k7ddrphy_bitslip261[6]),
+	.Q3      (main_k7ddrphy_bitslip261[5]),
+	.Q4      (main_k7ddrphy_bitslip261[4]),
+	.Q5      (main_k7ddrphy_bitslip261[3]),
+	.Q6      (main_k7ddrphy_bitslip261[2]),
+	.Q7      (main_k7ddrphy_bitslip261[1]),
+	.Q8      (main_k7ddrphy_bitslip261[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_60 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_60 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed26),
-	.ODATAIN(k7ddrphy_dq_o_nodelay26)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed26),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay26)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_26 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_26 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay26),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed26)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay26),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed26)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_26 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_26(
-	.I(k7ddrphy_dq_o_delayed26),
-	.T(k7ddrphy_dq_t26),
-	.IO(ddram_dq[26]),
-	.O(k7ddrphy_dq_i_nodelay26)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed26),
+	.T  (main_k7ddrphy_dq_t26),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay26),
+
+	// InOuts.
+	.IO (ddram_dq[26])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_61 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_61 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip270[0]),
-	.D2(k7ddrphy_bitslip270[1]),
-	.D3(k7ddrphy_bitslip270[2]),
-	.D4(k7ddrphy_bitslip270[3]),
-	.D5(k7ddrphy_bitslip270[4]),
-	.D6(k7ddrphy_bitslip270[5]),
-	.D7(k7ddrphy_bitslip270[6]),
-	.D8(k7ddrphy_bitslip270[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay27),
-	.TQ(k7ddrphy_dq_t27)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip270[0]),
+	.D2     (main_k7ddrphy_bitslip270[1]),
+	.D3     (main_k7ddrphy_bitslip270[2]),
+	.D4     (main_k7ddrphy_bitslip270[3]),
+	.D5     (main_k7ddrphy_bitslip270[4]),
+	.D6     (main_k7ddrphy_bitslip270[5]),
+	.D7     (main_k7ddrphy_bitslip270[6]),
+	.D8     (main_k7ddrphy_bitslip270[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay27),
+	.TQ     (main_k7ddrphy_dq_t27)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_27 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_27 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed27),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip271[7]),
-	.Q2(k7ddrphy_bitslip271[6]),
-	.Q3(k7ddrphy_bitslip271[5]),
-	.Q4(k7ddrphy_bitslip271[4]),
-	.Q5(k7ddrphy_bitslip271[3]),
-	.Q6(k7ddrphy_bitslip271[2]),
-	.Q7(k7ddrphy_bitslip271[1]),
-	.Q8(k7ddrphy_bitslip271[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed27),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip271[7]),
+	.Q2      (main_k7ddrphy_bitslip271[6]),
+	.Q3      (main_k7ddrphy_bitslip271[5]),
+	.Q4      (main_k7ddrphy_bitslip271[4]),
+	.Q5      (main_k7ddrphy_bitslip271[3]),
+	.Q6      (main_k7ddrphy_bitslip271[2]),
+	.Q7      (main_k7ddrphy_bitslip271[1]),
+	.Q8      (main_k7ddrphy_bitslip271[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_61 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_61 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed27),
-	.ODATAIN(k7ddrphy_dq_o_nodelay27)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed27),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay27)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_27 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_27 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay27),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed27)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay27),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed27)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_27 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_27(
-	.I(k7ddrphy_dq_o_delayed27),
-	.T(k7ddrphy_dq_t27),
-	.IO(ddram_dq[27]),
-	.O(k7ddrphy_dq_i_nodelay27)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed27),
+	.T  (main_k7ddrphy_dq_t27),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay27),
+
+	// InOuts.
+	.IO (ddram_dq[27])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_62 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_62 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip280[0]),
-	.D2(k7ddrphy_bitslip280[1]),
-	.D3(k7ddrphy_bitslip280[2]),
-	.D4(k7ddrphy_bitslip280[3]),
-	.D5(k7ddrphy_bitslip280[4]),
-	.D6(k7ddrphy_bitslip280[5]),
-	.D7(k7ddrphy_bitslip280[6]),
-	.D8(k7ddrphy_bitslip280[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay28),
-	.TQ(k7ddrphy_dq_t28)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip280[0]),
+	.D2     (main_k7ddrphy_bitslip280[1]),
+	.D3     (main_k7ddrphy_bitslip280[2]),
+	.D4     (main_k7ddrphy_bitslip280[3]),
+	.D5     (main_k7ddrphy_bitslip280[4]),
+	.D6     (main_k7ddrphy_bitslip280[5]),
+	.D7     (main_k7ddrphy_bitslip280[6]),
+	.D8     (main_k7ddrphy_bitslip280[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay28),
+	.TQ     (main_k7ddrphy_dq_t28)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_28 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_28 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed28),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip281[7]),
-	.Q2(k7ddrphy_bitslip281[6]),
-	.Q3(k7ddrphy_bitslip281[5]),
-	.Q4(k7ddrphy_bitslip281[4]),
-	.Q5(k7ddrphy_bitslip281[3]),
-	.Q6(k7ddrphy_bitslip281[2]),
-	.Q7(k7ddrphy_bitslip281[1]),
-	.Q8(k7ddrphy_bitslip281[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed28),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip281[7]),
+	.Q2      (main_k7ddrphy_bitslip281[6]),
+	.Q3      (main_k7ddrphy_bitslip281[5]),
+	.Q4      (main_k7ddrphy_bitslip281[4]),
+	.Q5      (main_k7ddrphy_bitslip281[3]),
+	.Q6      (main_k7ddrphy_bitslip281[2]),
+	.Q7      (main_k7ddrphy_bitslip281[1]),
+	.Q8      (main_k7ddrphy_bitslip281[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_62 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_62 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed28),
-	.ODATAIN(k7ddrphy_dq_o_nodelay28)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed28),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay28)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_28 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_28 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay28),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed28)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay28),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed28)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_28 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_28(
-	.I(k7ddrphy_dq_o_delayed28),
-	.T(k7ddrphy_dq_t28),
-	.IO(ddram_dq[28]),
-	.O(k7ddrphy_dq_i_nodelay28)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed28),
+	.T  (main_k7ddrphy_dq_t28),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay28),
+
+	// InOuts.
+	.IO (ddram_dq[28])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_63 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_63 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip290[0]),
-	.D2(k7ddrphy_bitslip290[1]),
-	.D3(k7ddrphy_bitslip290[2]),
-	.D4(k7ddrphy_bitslip290[3]),
-	.D5(k7ddrphy_bitslip290[4]),
-	.D6(k7ddrphy_bitslip290[5]),
-	.D7(k7ddrphy_bitslip290[6]),
-	.D8(k7ddrphy_bitslip290[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay29),
-	.TQ(k7ddrphy_dq_t29)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip290[0]),
+	.D2     (main_k7ddrphy_bitslip290[1]),
+	.D3     (main_k7ddrphy_bitslip290[2]),
+	.D4     (main_k7ddrphy_bitslip290[3]),
+	.D5     (main_k7ddrphy_bitslip290[4]),
+	.D6     (main_k7ddrphy_bitslip290[5]),
+	.D7     (main_k7ddrphy_bitslip290[6]),
+	.D8     (main_k7ddrphy_bitslip290[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay29),
+	.TQ     (main_k7ddrphy_dq_t29)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_29 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_29 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed29),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip291[7]),
-	.Q2(k7ddrphy_bitslip291[6]),
-	.Q3(k7ddrphy_bitslip291[5]),
-	.Q4(k7ddrphy_bitslip291[4]),
-	.Q5(k7ddrphy_bitslip291[3]),
-	.Q6(k7ddrphy_bitslip291[2]),
-	.Q7(k7ddrphy_bitslip291[1]),
-	.Q8(k7ddrphy_bitslip291[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed29),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip291[7]),
+	.Q2      (main_k7ddrphy_bitslip291[6]),
+	.Q3      (main_k7ddrphy_bitslip291[5]),
+	.Q4      (main_k7ddrphy_bitslip291[4]),
+	.Q5      (main_k7ddrphy_bitslip291[3]),
+	.Q6      (main_k7ddrphy_bitslip291[2]),
+	.Q7      (main_k7ddrphy_bitslip291[1]),
+	.Q8      (main_k7ddrphy_bitslip291[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_63 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_63 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed29),
-	.ODATAIN(k7ddrphy_dq_o_nodelay29)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed29),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay29)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_29 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_29 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay29),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed29)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay29),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed29)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_29 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_29(
-	.I(k7ddrphy_dq_o_delayed29),
-	.T(k7ddrphy_dq_t29),
-	.IO(ddram_dq[29]),
-	.O(k7ddrphy_dq_i_nodelay29)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed29),
+	.T  (main_k7ddrphy_dq_t29),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay29),
+
+	// InOuts.
+	.IO (ddram_dq[29])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_64 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_64 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip300[0]),
-	.D2(k7ddrphy_bitslip300[1]),
-	.D3(k7ddrphy_bitslip300[2]),
-	.D4(k7ddrphy_bitslip300[3]),
-	.D5(k7ddrphy_bitslip300[4]),
-	.D6(k7ddrphy_bitslip300[5]),
-	.D7(k7ddrphy_bitslip300[6]),
-	.D8(k7ddrphy_bitslip300[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay30),
-	.TQ(k7ddrphy_dq_t30)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip300[0]),
+	.D2     (main_k7ddrphy_bitslip300[1]),
+	.D3     (main_k7ddrphy_bitslip300[2]),
+	.D4     (main_k7ddrphy_bitslip300[3]),
+	.D5     (main_k7ddrphy_bitslip300[4]),
+	.D6     (main_k7ddrphy_bitslip300[5]),
+	.D7     (main_k7ddrphy_bitslip300[6]),
+	.D8     (main_k7ddrphy_bitslip300[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay30),
+	.TQ     (main_k7ddrphy_dq_t30)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_30 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_30 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed30),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip301[7]),
-	.Q2(k7ddrphy_bitslip301[6]),
-	.Q3(k7ddrphy_bitslip301[5]),
-	.Q4(k7ddrphy_bitslip301[4]),
-	.Q5(k7ddrphy_bitslip301[3]),
-	.Q6(k7ddrphy_bitslip301[2]),
-	.Q7(k7ddrphy_bitslip301[1]),
-	.Q8(k7ddrphy_bitslip301[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed30),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip301[7]),
+	.Q2      (main_k7ddrphy_bitslip301[6]),
+	.Q3      (main_k7ddrphy_bitslip301[5]),
+	.Q4      (main_k7ddrphy_bitslip301[4]),
+	.Q5      (main_k7ddrphy_bitslip301[3]),
+	.Q6      (main_k7ddrphy_bitslip301[2]),
+	.Q7      (main_k7ddrphy_bitslip301[1]),
+	.Q8      (main_k7ddrphy_bitslip301[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_64 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_64 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed30),
-	.ODATAIN(k7ddrphy_dq_o_nodelay30)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed30),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay30)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_30 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_30 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay30),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed30)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay30),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed30)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_30 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_30(
-	.I(k7ddrphy_dq_o_delayed30),
-	.T(k7ddrphy_dq_t30),
-	.IO(ddram_dq[30]),
-	.O(k7ddrphy_dq_i_nodelay30)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed30),
+	.T  (main_k7ddrphy_dq_t30),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay30),
+
+	// InOuts.
+	.IO (ddram_dq[30])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_65 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_65 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(k7ddrphy_bitslip310[0]),
-	.D2(k7ddrphy_bitslip310[1]),
-	.D3(k7ddrphy_bitslip310[2]),
-	.D4(k7ddrphy_bitslip310[3]),
-	.D5(k7ddrphy_bitslip310[4]),
-	.D6(k7ddrphy_bitslip310[5]),
-	.D7(k7ddrphy_bitslip310[6]),
-	.D8(k7ddrphy_bitslip310[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(k7ddrphy_dq_o_nodelay31),
-	.TQ(k7ddrphy_dq_t31)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_k7ddrphy_bitslip310[0]),
+	.D2     (main_k7ddrphy_bitslip310[1]),
+	.D3     (main_k7ddrphy_bitslip310[2]),
+	.D4     (main_k7ddrphy_bitslip310[3]),
+	.D5     (main_k7ddrphy_bitslip310[4]),
+	.D6     (main_k7ddrphy_bitslip310[5]),
+	.D7     (main_k7ddrphy_bitslip310[6]),
+	.D8     (main_k7ddrphy_bitslip310[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_k7ddrphy_rst_storage)),
+	.T1     ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_k7ddrphy_dq_o_nodelay31),
+	.TQ     (main_k7ddrphy_dq_t31)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_31 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_31 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(k7ddrphy_dq_i_delayed31),
-	.RST((sys_rst | k7ddrphy_rst_storage)),
-	.Q1(k7ddrphy_bitslip311[7]),
-	.Q2(k7ddrphy_bitslip311[6]),
-	.Q3(k7ddrphy_bitslip311[5]),
-	.Q4(k7ddrphy_bitslip311[4]),
-	.Q5(k7ddrphy_bitslip311[3]),
-	.Q6(k7ddrphy_bitslip311[2]),
-	.Q7(k7ddrphy_bitslip311[1]),
-	.Q8(k7ddrphy_bitslip311[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_k7ddrphy_dq_i_delayed31),
+	.RST     ((sys_rst | main_k7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_k7ddrphy_bitslip311[7]),
+	.Q2      (main_k7ddrphy_bitslip311[6]),
+	.Q3      (main_k7ddrphy_bitslip311[5]),
+	.Q4      (main_k7ddrphy_bitslip311[4]),
+	.Q5      (main_k7ddrphy_bitslip311[3]),
+	.Q6      (main_k7ddrphy_bitslip311[2]),
+	.Q7      (main_k7ddrphy_bitslip311[1]),
+	.Q8      (main_k7ddrphy_bitslip311[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODELAYE2_65 of ODELAYE2 Module.
+//------------------------------------------------------------------------------
 ODELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("ODATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.ODELAY_TYPE("VARIABLE"),
-	.ODELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("ODATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.ODELAY_TYPE           ("VARIABLE"),
+	.ODELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) ODELAYE2_65 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_o_delayed31),
-	.ODATAIN(k7ddrphy_dq_o_nodelay31)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_o_delayed31),
+	.ODATAIN  (main_k7ddrphy_dq_o_nodelay31)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_31 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_31 (
-	.C(sys_clk),
-	.CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(k7ddrphy_dq_i_nodelay31),
-	.INC(1'd1),
-	.LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(k7ddrphy_dq_i_delayed31)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_k7ddrphy_dq_i_nodelay31),
+	.INC      (1'd1),
+	.LD       (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_k7ddrphy_dq_i_delayed31)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_31 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_31(
-	.I(k7ddrphy_dq_o_delayed31),
-	.T(k7ddrphy_dq_t31),
-	.IO(ddram_dq[31]),
-	.O(k7ddrphy_dq_i_nodelay31)
+	// Inputs.
+	.I  (main_k7ddrphy_dq_o_delayed31),
+	.T  (main_k7ddrphy_dq_t31),
+
+	// Outputs.
+	.O  (main_k7ddrphy_dq_i_nodelay31),
+
+	// InOuts.
+	.IO (ddram_dq[31])
 );
 
 //------------------------------------------------------------------------------
@@ -20650,14 +22924,14 @@ IOBUF IOBUF_31(
 reg [24:0] storage[0:15];
 reg [24:0] storage_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine0_wrport_we)
-		storage[litedramcore_bankmachine0_wrport_adr] <= litedramcore_bankmachine0_wrport_dat_w;
-	storage_dat0 <= storage[litedramcore_bankmachine0_wrport_adr];
+	if (main_litedramcore_bankmachine0_wrport_we)
+		storage[main_litedramcore_bankmachine0_wrport_adr] <= main_litedramcore_bankmachine0_wrport_dat_w;
+	storage_dat0 <= storage[main_litedramcore_bankmachine0_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine0_wrport_dat_r = storage_dat0;
-assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine0_rdport_adr];
+assign main_litedramcore_bankmachine0_wrport_dat_r = storage_dat0;
+assign main_litedramcore_bankmachine0_rdport_dat_r = storage[main_litedramcore_bankmachine0_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -20668,14 +22942,14 @@ assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine
 reg [24:0] storage_1[0:15];
 reg [24:0] storage_1_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine1_wrport_we)
-		storage_1[litedramcore_bankmachine1_wrport_adr] <= litedramcore_bankmachine1_wrport_dat_w;
-	storage_1_dat0 <= storage_1[litedramcore_bankmachine1_wrport_adr];
+	if (main_litedramcore_bankmachine1_wrport_we)
+		storage_1[main_litedramcore_bankmachine1_wrport_adr] <= main_litedramcore_bankmachine1_wrport_dat_w;
+	storage_1_dat0 <= storage_1[main_litedramcore_bankmachine1_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0;
-assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachine1_rdport_adr];
+assign main_litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0;
+assign main_litedramcore_bankmachine1_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -20686,14 +22960,14 @@ assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachi
 reg [24:0] storage_2[0:15];
 reg [24:0] storage_2_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine2_wrport_we)
-		storage_2[litedramcore_bankmachine2_wrport_adr] <= litedramcore_bankmachine2_wrport_dat_w;
-	storage_2_dat0 <= storage_2[litedramcore_bankmachine2_wrport_adr];
+	if (main_litedramcore_bankmachine2_wrport_we)
+		storage_2[main_litedramcore_bankmachine2_wrport_adr] <= main_litedramcore_bankmachine2_wrport_dat_w;
+	storage_2_dat0 <= storage_2[main_litedramcore_bankmachine2_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0;
-assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachine2_rdport_adr];
+assign main_litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0;
+assign main_litedramcore_bankmachine2_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -20704,14 +22978,14 @@ assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachi
 reg [24:0] storage_3[0:15];
 reg [24:0] storage_3_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine3_wrport_we)
-		storage_3[litedramcore_bankmachine3_wrport_adr] <= litedramcore_bankmachine3_wrport_dat_w;
-	storage_3_dat0 <= storage_3[litedramcore_bankmachine3_wrport_adr];
+	if (main_litedramcore_bankmachine3_wrport_we)
+		storage_3[main_litedramcore_bankmachine3_wrport_adr] <= main_litedramcore_bankmachine3_wrport_dat_w;
+	storage_3_dat0 <= storage_3[main_litedramcore_bankmachine3_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0;
-assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachine3_rdport_adr];
+assign main_litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0;
+assign main_litedramcore_bankmachine3_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -20722,14 +22996,14 @@ assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachi
 reg [24:0] storage_4[0:15];
 reg [24:0] storage_4_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine4_wrport_we)
-		storage_4[litedramcore_bankmachine4_wrport_adr] <= litedramcore_bankmachine4_wrport_dat_w;
-	storage_4_dat0 <= storage_4[litedramcore_bankmachine4_wrport_adr];
+	if (main_litedramcore_bankmachine4_wrport_we)
+		storage_4[main_litedramcore_bankmachine4_wrport_adr] <= main_litedramcore_bankmachine4_wrport_dat_w;
+	storage_4_dat0 <= storage_4[main_litedramcore_bankmachine4_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0;
-assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachine4_rdport_adr];
+assign main_litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0;
+assign main_litedramcore_bankmachine4_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -20740,14 +23014,14 @@ assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachi
 reg [24:0] storage_5[0:15];
 reg [24:0] storage_5_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine5_wrport_we)
-		storage_5[litedramcore_bankmachine5_wrport_adr] <= litedramcore_bankmachine5_wrport_dat_w;
-	storage_5_dat0 <= storage_5[litedramcore_bankmachine5_wrport_adr];
+	if (main_litedramcore_bankmachine5_wrport_we)
+		storage_5[main_litedramcore_bankmachine5_wrport_adr] <= main_litedramcore_bankmachine5_wrport_dat_w;
+	storage_5_dat0 <= storage_5[main_litedramcore_bankmachine5_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0;
-assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachine5_rdport_adr];
+assign main_litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0;
+assign main_litedramcore_bankmachine5_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -20758,14 +23032,14 @@ assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachi
 reg [24:0] storage_6[0:15];
 reg [24:0] storage_6_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine6_wrport_we)
-		storage_6[litedramcore_bankmachine6_wrport_adr] <= litedramcore_bankmachine6_wrport_dat_w;
-	storage_6_dat0 <= storage_6[litedramcore_bankmachine6_wrport_adr];
+	if (main_litedramcore_bankmachine6_wrport_we)
+		storage_6[main_litedramcore_bankmachine6_wrport_adr] <= main_litedramcore_bankmachine6_wrport_dat_w;
+	storage_6_dat0 <= storage_6[main_litedramcore_bankmachine6_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0;
-assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachine6_rdport_adr];
+assign main_litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0;
+assign main_litedramcore_bankmachine6_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -20776,197 +23050,308 @@ assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachi
 reg [24:0] storage_7[0:15];
 reg [24:0] storage_7_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine7_wrport_we)
-		storage_7[litedramcore_bankmachine7_wrport_adr] <= litedramcore_bankmachine7_wrport_dat_w;
-	storage_7_dat0 <= storage_7[litedramcore_bankmachine7_wrport_adr];
+	if (main_litedramcore_bankmachine7_wrport_we)
+		storage_7[main_litedramcore_bankmachine7_wrport_adr] <= main_litedramcore_bankmachine7_wrport_dat_w;
+	storage_7_dat0 <= storage_7[main_litedramcore_bankmachine7_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0;
-assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachine7_rdport_adr];
+assign main_litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0;
+assign main_litedramcore_bankmachine7_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_rdport_adr];
 
 
+//------------------------------------------------------------------------------
+// Instance FDCE of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(reset),
-	.Q(litedramcore_reset0)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (main_reset),
+
+	// Outputs.
+	.Q   (builder_reset0)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_1 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_1(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset0),
-	.Q(litedramcore_reset1)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset0),
+
+	// Outputs.
+	.Q   (builder_reset1)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_2 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_2(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset1),
-	.Q(litedramcore_reset2)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset1),
+
+	// Outputs.
+	.Q   (builder_reset2)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_3 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_3(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset2),
-	.Q(litedramcore_reset3)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset2),
+
+	// Outputs.
+	.Q   (builder_reset3)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_4 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_4(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset3),
-	.Q(litedramcore_reset4)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset3),
+
+	// Outputs.
+	.Q   (builder_reset4)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_5 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_5(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset4),
-	.Q(litedramcore_reset5)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset4),
+
+	// Outputs.
+	.Q   (builder_reset5)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_6 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_6(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset5),
-	.Q(litedramcore_reset6)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset5),
+
+	// Outputs.
+	.Q   (builder_reset6)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_7 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_7(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset6),
-	.Q(litedramcore_reset7)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset6),
+
+	// Outputs.
+	.Q   (builder_reset7)
 );
 
+//------------------------------------------------------------------------------
+// Instance PLLE2_ADV of PLLE2_ADV Module.
+//------------------------------------------------------------------------------
 PLLE2_ADV #(
-	.CLKFBOUT_MULT(4'd8),
-	.CLKIN1_PERIOD(5.0),
-	.CLKOUT0_DIVIDE(4'd8),
-	.CLKOUT0_PHASE(1'd0),
-	.CLKOUT1_DIVIDE(5'd16),
-	.CLKOUT1_PHASE(1'd0),
-	.CLKOUT2_DIVIDE(3'd4),
-	.CLKOUT2_PHASE(1'd0),
-	.CLKOUT3_DIVIDE(3'd4),
-	.CLKOUT3_PHASE(7'd90),
-	.DIVCLK_DIVIDE(1'd1),
-	.REF_JITTER1(0.01),
-	.STARTUP_WAIT("FALSE")
+	// Parameters.
+	.CLKFBOUT_MULT  (4'd8),
+	.CLKIN1_PERIOD  (5.0),
+	.CLKOUT0_DIVIDE (4'd8),
+	.CLKOUT0_PHASE  (1'd0),
+	.CLKOUT1_DIVIDE (5'd16),
+	.CLKOUT1_PHASE  (1'd0),
+	.CLKOUT2_DIVIDE (3'd4),
+	.CLKOUT2_PHASE  (1'd0),
+	.CLKOUT3_DIVIDE (3'd4),
+	.CLKOUT3_PHASE  (7'd90),
+	.DIVCLK_DIVIDE  (1'd1),
+	.REF_JITTER1    (0.01),
+	.STARTUP_WAIT   ("FALSE")
 ) PLLE2_ADV (
-	.CLKFBIN(litedramcore_pll_fb),
-	.CLKIN1(clkin),
-	.PWRDWN(power_down),
-	.RST(litedramcore_reset7),
-	.CLKFBOUT(litedramcore_pll_fb),
-	.CLKOUT0(clkout0),
-	.CLKOUT1(clkout1),
-	.CLKOUT2(clkout2),
-	.CLKOUT3(clkout3),
-	.LOCKED(locked)
+	// Inputs.
+	.CLKFBIN  (builder_pll_fb),
+	.CLKIN1   (main_clkin),
+	.PWRDWN   (main_power_down),
+	.RST      (builder_reset7),
+
+	// Outputs.
+	.CLKFBOUT (builder_pll_fb),
+	.CLKOUT0  (main_clkout0),
+	.CLKOUT1  (main_clkout1),
+	.CLKOUT2  (main_clkout2),
+	.CLKOUT3  (main_clkout3),
+	.LOCKED   (main_locked)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE (
-	.C(iodelay_clk),
-	.CE(1'd1),
-	.D(1'd0),
-	.PRE(xilinxasyncresetsynchronizerimpl0),
-	.Q(xilinxasyncresetsynchronizerimpl0_rst_meta)
+	// Inputs.
+	.C   (iodelay_clk),
+	.CE  (1'd1),
+	.D   (1'd0),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl0_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_1 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_1 (
-	.C(iodelay_clk),
-	.CE(1'd1),
-	.D(xilinxasyncresetsynchronizerimpl0_rst_meta),
-	.PRE(xilinxasyncresetsynchronizerimpl0),
-	.Q(iodelay_rst)
+	// Inputs.
+	.C   (iodelay_clk),
+	.CE  (1'd1),
+	.D   (builder_xilinxasyncresetsynchronizerimpl0_rst_meta),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset),
+
+	// Outputs.
+	.Q   (iodelay_rst)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_2 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_2 (
-	.C(sys_clk),
-	.CE(1'd1),
-	.D(1'd0),
-	.PRE(xilinxasyncresetsynchronizerimpl1),
-	.Q(xilinxasyncresetsynchronizerimpl1_rst_meta)
+	// Inputs.
+	.C   (sys_clk),
+	.CE  (1'd1),
+	.D   (1'd0),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl1_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_3 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_3 (
-	.C(sys_clk),
-	.CE(1'd1),
-	.D(xilinxasyncresetsynchronizerimpl1_rst_meta),
-	.PRE(xilinxasyncresetsynchronizerimpl1),
-	.Q(sys_rst)
+	// Inputs.
+	.C   (sys_clk),
+	.CE  (1'd1),
+	.D   (builder_xilinxasyncresetsynchronizerimpl1_rst_meta),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset),
+
+	// Outputs.
+	.Q   (sys_rst)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_4 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_4 (
-	.C(sys4x_clk),
-	.CE(1'd1),
-	.D(1'd0),
-	.PRE(xilinxasyncresetsynchronizerimpl2),
-	.Q(xilinxasyncresetsynchronizerimpl2_rst_meta)
+	// Inputs.
+	.C   (sys4x_clk),
+	.CE  (1'd1),
+	.D   (1'd0),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl2_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_5 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_5 (
-	.C(sys4x_clk),
-	.CE(1'd1),
-	.D(xilinxasyncresetsynchronizerimpl2_rst_meta),
-	.PRE(xilinxasyncresetsynchronizerimpl2),
-	.Q(xilinxasyncresetsynchronizerimpl2_expr)
+	// Inputs.
+	.C   (sys4x_clk),
+	.CE  (1'd1),
+	.D   (builder_xilinxasyncresetsynchronizerimpl2_rst_meta),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl2_expr)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_6 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_6 (
-	.C(sys4x_dqs_clk),
-	.CE(1'd1),
-	.D(1'd0),
-	.PRE(xilinxasyncresetsynchronizerimpl3),
-	.Q(xilinxasyncresetsynchronizerimpl3_rst_meta)
+	// Inputs.
+	.C   (sys4x_dqs_clk),
+	.CE  (1'd1),
+	.D   (1'd0),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl3_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_7 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_7 (
-	.C(sys4x_dqs_clk),
-	.CE(1'd1),
-	.D(xilinxasyncresetsynchronizerimpl3_rst_meta),
-	.PRE(xilinxasyncresetsynchronizerimpl3),
-	.Q(xilinxasyncresetsynchronizerimpl3_expr)
+	// Inputs.
+	.C   (sys4x_dqs_clk),
+	.CE  (1'd1),
+	.D   (builder_xilinxasyncresetsynchronizerimpl3_rst_meta),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl3_expr)
 );
 
 endmodule
 
 // -----------------------------------------------------------------------------
-//  Auto-Generated by LiteX on 2022-10-28 19:01:22.
+//  Auto-Generated by LiteX on 2024-04-01 10:12:08.
 //------------------------------------------------------------------------------
diff --git a/litedram/generated/nexys-video/litedram_core.init b/litedram/generated/nexys-video/litedram_core.init
index 61e54f3..0573632 100644
--- a/litedram/generated/nexys-video/litedram_core.init
+++ b/litedram/generated/nexys-video/litedram_core.init
@@ -7,7 +7,7 @@ a64b5a7d14004a39
 6421ff00782107c6
 3d80000060215f00
 798c07c6618c0000
-618c10e0658cff00
+618c10d4658cff00
 4e8004217d8903a6
 4e8004207c6903a6
 0000000000000000
@@ -510,677 +510,687 @@ a64b5a7d14004a39
 0000000000000000
 0000000000000000
 0000000000000000
-392000003d40c000
-794a0020614a6004
-7d2057aa7c0004ac
+3920000039406004
+7c0004ac654ac000
+600000007d2057aa
 6000000060000000
 6000000060000000
-4e80002060000000
+000000004e800020
 0000000000000000
-3c4c000100000000
-7c0802a63842adc4
-fbe1fff8fbc1fff0
+3842adc83c4c0001
+fbe1fff87c0802a6
 f821ff51f8010010
-f88100d83bc10020
-f8c100e8f8a100e0
-38c100d87c651b78
-f8e100f038800080
-7fc3f378f90100f8
-f9410108f9210100
-6000000048002139
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 6d6f636c65570a0a
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@@ -1875,7 +1859,7 @@ ebe1fff8e8010010
 203a46464f204853
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 00000000000a7365
-2d2d2d2d2d2d2d2d
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 0000000000000000
 4d4152446574694c
 6620746c69756220
@@ -1944,6 +1928,8 @@ ebe1fff8e8010010
 52445320676e697a
 3025783040204d41
 000a2e2e2e786c38
+000000540000002a
+6000000000000024
 0000000042756c25
 4b756c252e756c25
 0000000000004269
diff --git a/litedram/generated/nexys-video/litedram_core.v b/litedram/generated/nexys-video/litedram_core.v
index 0bf0d54..bab09c2 100644
--- a/litedram/generated/nexys-video/litedram_core.v
+++ b/litedram/generated/nexys-video/litedram_core.v
@@ -8,10 +8,11 @@
 //
 // Filename   : litedram_core.v
 // Device     : 
-// LiteX sha1 : --------
-// Date       : 2022-10-28 19:01:20
+// LiteX sha1 : 87137c30
+// Date       : 2024-04-01 10:12:06
 //------------------------------------------------------------------------------
 
+`timescale 1ns / 1ps
 
 //------------------------------------------------------------------------------
 // Module
@@ -19,4659 +20,5077 @@
 
 module litedram_core (
     input  wire          clk,
-    input  wire          rst,
-    output wire          pll_locked,
     output wire   [14:0] ddram_a,
     output wire    [2:0] ddram_ba,
-    output wire          ddram_ras_n,
     output wire          ddram_cas_n,
-    output wire          ddram_we_n,
+    output wire          ddram_cke,
+    output wire          ddram_clk_n,
+    output wire          ddram_clk_p,
     output wire          ddram_cs_n,
     output wire    [1:0] ddram_dm,
     inout  wire   [15:0] ddram_dq,
-    inout  wire    [1:0] ddram_dqs_p,
     inout  wire    [1:0] ddram_dqs_n,
-    output wire          ddram_clk_p,
-    output wire          ddram_clk_n,
-    output wire          ddram_cke,
+    inout  wire    [1:0] ddram_dqs_p,
     output wire          ddram_odt,
+    output wire          ddram_ras_n,
     output wire          ddram_reset_n,
+    output wire          ddram_we_n,
     output wire          init_done,
     output wire          init_error,
-    input  wire   [29:0] wb_ctrl_adr,
-    input  wire   [31:0] wb_ctrl_dat_w,
-    output wire   [31:0] wb_ctrl_dat_r,
-    input  wire    [3:0] wb_ctrl_sel,
-    input  wire          wb_ctrl_cyc,
-    input  wire          wb_ctrl_stb,
-    output wire          wb_ctrl_ack,
-    input  wire          wb_ctrl_we,
-    input  wire    [2:0] wb_ctrl_cti,
-    input  wire    [1:0] wb_ctrl_bte,
-    output wire          wb_ctrl_err,
+    output wire          pll_locked,
+    input  wire          rst,
     output wire          user_clk,
-    output wire          user_rst,
-    input  wire          user_port_native_0_cmd_valid,
+    input  wire   [24:0] user_port_native_0_cmd_addr,
     output wire          user_port_native_0_cmd_ready,
+    input  wire          user_port_native_0_cmd_valid,
     input  wire          user_port_native_0_cmd_we,
-    input  wire   [24:0] user_port_native_0_cmd_addr,
-    input  wire          user_port_native_0_wdata_valid,
+    output wire  [127:0] user_port_native_0_rdata_data,
+    input  wire          user_port_native_0_rdata_ready,
+    output wire          user_port_native_0_rdata_valid,
+    input  wire  [127:0] user_port_native_0_wdata_data,
     output wire          user_port_native_0_wdata_ready,
+    input  wire          user_port_native_0_wdata_valid,
     input  wire   [15:0] user_port_native_0_wdata_we,
-    input  wire  [127:0] user_port_native_0_wdata_data,
-    output wire          user_port_native_0_rdata_valid,
-    input  wire          user_port_native_0_rdata_ready,
-    output wire  [127:0] user_port_native_0_rdata_data
+    output wire          user_rst,
+    output wire          wb_ctrl_ack,
+    input  wire   [29:0] wb_ctrl_adr,
+    input  wire    [1:0] wb_ctrl_bte,
+    input  wire    [2:0] wb_ctrl_cti,
+    input  wire          wb_ctrl_cyc,
+    output wire   [31:0] wb_ctrl_dat_r,
+    input  wire   [31:0] wb_ctrl_dat_w,
+    output wire          wb_ctrl_err,
+    input  wire    [3:0] wb_ctrl_sel,
+    input  wire          wb_ctrl_stb,
+    input  wire          wb_ctrl_we
 );
 
 
+//------------------------------------------------------------------------------
+// Hierarchy
+//------------------------------------------------------------------------------
+
+/*
+LiteDRAMCore
+└─── bus (SoCBusHandler)
+│    └─── _interconnect (InterconnectPointToPoint)
+└─── csr (SoCCSRHandler)
+└─── irq (SoCIRQHandler)
+└─── cpu (CPUNone)
+└─── crg (LiteDRAMS7DDRPHYCRG)
+│    └─── pll (S7PLL)
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [BUFG]
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [BUFG]
+│    │    └─── [BUFG]
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [PLLE2_ADV]
+│    │    └─── [BUFG]
+│    └─── idelayctrl (S7IDELAYCTRL)
+│    │    └─── [IDELAYCTRL]
+└─── ddrphy (A7DDRPHY)
+│    └─── tappeddelayline_0* (TappedDelayLine)
+│    └─── dqspattern_0* (DQSPattern)
+│    └─── bitslip_0* (BitSlip)
+│    └─── bitslip_1* (BitSlip)
+│    └─── bitslip_2* (BitSlip)
+│    └─── bitslip_3* (BitSlip)
+│    └─── tappeddelayline_1* (TappedDelayLine)
+│    └─── bitslip_4* (BitSlip)
+│    └─── bitslip_5* (BitSlip)
+│    └─── bitslip_6* (BitSlip)
+│    └─── bitslip_7* (BitSlip)
+│    └─── bitslip_8* (BitSlip)
+│    └─── bitslip_9* (BitSlip)
+│    └─── bitslip_10* (BitSlip)
+│    └─── bitslip_11* (BitSlip)
+│    └─── bitslip_12* (BitSlip)
+│    └─── bitslip_13* (BitSlip)
+│    └─── bitslip_14* (BitSlip)
+│    └─── bitslip_15* (BitSlip)
+│    └─── bitslip_16* (BitSlip)
+│    └─── bitslip_17* (BitSlip)
+│    └─── bitslip_18* (BitSlip)
+│    └─── bitslip_19* (BitSlip)
+│    └─── bitslip_20* (BitSlip)
+│    └─── bitslip_21* (BitSlip)
+│    └─── bitslip_22* (BitSlip)
+│    └─── bitslip_23* (BitSlip)
+│    └─── bitslip_24* (BitSlip)
+│    └─── bitslip_25* (BitSlip)
+│    └─── bitslip_26* (BitSlip)
+│    └─── bitslip_27* (BitSlip)
+│    └─── bitslip_28* (BitSlip)
+│    └─── bitslip_29* (BitSlip)
+│    └─── bitslip_30* (BitSlip)
+│    └─── bitslip_31* (BitSlip)
+│    └─── bitslip_32* (BitSlip)
+│    └─── bitslip_33* (BitSlip)
+│    └─── bitslip_34* (BitSlip)
+│    └─── bitslip_35* (BitSlip)
+│    └─── tappeddelayline_2* (TappedDelayLine)
+│    └─── tappeddelayline_3* (TappedDelayLine)
+│    └─── [IOBUF]
+│    └─── [ISERDESE2]
+│    └─── [IOBUFDS]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [IDELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OBUFDS]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUFDS]
+│    └─── [IOBUF]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [IOBUF]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+└─── sdram (LiteDRAMCore)
+│    └─── dfii (DFIInjector)
+│    │    └─── pi0 (PhaseInjector)
+│    │    └─── pi1 (PhaseInjector)
+│    │    └─── pi2 (PhaseInjector)
+│    │    └─── pi3 (PhaseInjector)
+│    └─── controller (LiteDRAMController)
+│    │    └─── refresher (Refresher)
+│    │    │    └─── timer (RefreshTimer)
+│    │    │    └─── postponer (RefreshPostponer)
+│    │    │    └─── sequencer (RefreshSequencer)
+│    │    │    │    └─── refreshexecuter_0* (RefreshExecuter)
+│    │    │    └─── zqcs_timer (RefreshTimer)
+│    │    │    └─── zqs_executer (ZQCSExecuter)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_0* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_1* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_2* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_3* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_4* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_5* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_6* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_7* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── multiplexer (Multiplexer)
+│    │    │    └─── choose_cmd (_CommandChooser)
+│    │    │    │    └─── roundrobin_0* (RoundRobin)
+│    │    │    └─── choose_req (_CommandChooser)
+│    │    │    │    └─── roundrobin_0* (RoundRobin)
+│    │    │    └─── _steerer_0* (_Steerer)
+│    │    │    └─── trrdcon (tXXDController)
+│    │    │    └─── tfawcon (tFAWController)
+│    │    │    └─── tccdcon (tXXDController)
+│    │    │    └─── twtrcon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    └─── crossbar (LiteDRAMCrossbar)
+│    │    └─── roundrobin_0* (RoundRobin)
+│    │    └─── roundrobin_1* (RoundRobin)
+│    │    └─── roundrobin_2* (RoundRobin)
+│    │    └─── roundrobin_3* (RoundRobin)
+│    │    └─── roundrobin_4* (RoundRobin)
+│    │    └─── roundrobin_5* (RoundRobin)
+│    │    └─── roundrobin_6* (RoundRobin)
+│    │    └─── roundrobin_7* (RoundRobin)
+└─── ddrctrl (LiteDRAMCoreControl)
+└─── csr_bridge (Wishbone2CSR)
+│    └─── fsm (FSM)
+└─── csr_bankarray (CSRBankArray)
+│    └─── csrbank_0* (CSRBank)
+│    │    └─── csrstorage_0* (CSRStorage)
+│    │    └─── csrstorage_1* (CSRStorage)
+│    └─── csrbank_1* (CSRBank)
+│    │    └─── csrstorage_0* (CSRStorage)
+│    │    └─── csrstorage_1* (CSRStorage)
+│    │    └─── csrstorage_2* (CSRStorage)
+│    │    └─── csrstorage_3* (CSRStorage)
+│    │    └─── csrstorage_4* (CSRStorage)
+│    │    └─── csrstorage_5* (CSRStorage)
+│    └─── csrbank_2* (CSRBank)
+│    │    └─── csrstorage_0* (CSRStorage)
+│    │    └─── csrstorage_1* (CSRStorage)
+│    │    └─── csrstorage_2* (CSRStorage)
+│    │    └─── csrstorage_3* (CSRStorage)
+│    │    └─── csrstorage_4* (CSRStorage)
+│    │    └─── csrstatus_0* (CSRStatus)
+│    │    └─── csrstorage_5* (CSRStorage)
+│    │    └─── csrstorage_6* (CSRStorage)
+│    │    └─── csrstorage_7* (CSRStorage)
+│    │    └─── csrstorage_8* (CSRStorage)
+│    │    └─── csrstatus_1* (CSRStatus)
+│    │    └─── csrstorage_9* (CSRStorage)
+│    │    └─── csrstorage_10* (CSRStorage)
+│    │    └─── csrstorage_11* (CSRStorage)
+│    │    └─── csrstorage_12* (CSRStorage)
+│    │    └─── csrstatus_2* (CSRStatus)
+│    │    └─── csrstorage_13* (CSRStorage)
+│    │    └─── csrstorage_14* (CSRStorage)
+│    │    └─── csrstorage_15* (CSRStorage)
+│    │    └─── csrstorage_16* (CSRStorage)
+│    │    └─── csrstatus_3* (CSRStatus)
+└─── csr_interconnect (InterconnectShared)
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+* : Generated name.
+[]: BlackBox.
+*/
+
 //------------------------------------------------------------------------------
 // Signals
 //------------------------------------------------------------------------------
 
-reg           rst_1 = 1'd0;
-wire          sys_clk;
-wire          sys_rst;
-wire          sys4x_clk;
-wire          sys4x_dqs_clk;
+wire   [13:0] builder_adr;
+reg     [3:0] builder_bankmachine0_next_state = 4'd0;
+reg     [3:0] builder_bankmachine0_state = 4'd0;
+reg     [3:0] builder_bankmachine1_next_state = 4'd0;
+reg     [3:0] builder_bankmachine1_state = 4'd0;
+reg     [3:0] builder_bankmachine2_next_state = 4'd0;
+reg     [3:0] builder_bankmachine2_state = 4'd0;
+reg     [3:0] builder_bankmachine3_next_state = 4'd0;
+reg     [3:0] builder_bankmachine3_state = 4'd0;
+reg     [3:0] builder_bankmachine4_next_state = 4'd0;
+reg     [3:0] builder_bankmachine4_state = 4'd0;
+reg     [3:0] builder_bankmachine5_next_state = 4'd0;
+reg     [3:0] builder_bankmachine5_state = 4'd0;
+reg     [3:0] builder_bankmachine6_next_state = 4'd0;
+reg     [3:0] builder_bankmachine6_state = 4'd0;
+reg     [3:0] builder_bankmachine7_next_state = 4'd0;
+reg     [3:0] builder_bankmachine7_state = 4'd0;
+wire          builder_csrbank0_init_done0_r;
+reg           builder_csrbank0_init_done0_re = 1'd0;
+wire          builder_csrbank0_init_done0_w;
+reg           builder_csrbank0_init_done0_we = 1'd0;
+wire          builder_csrbank0_init_error0_r;
+reg           builder_csrbank0_init_error0_re = 1'd0;
+wire          builder_csrbank0_init_error0_w;
+reg           builder_csrbank0_init_error0_we = 1'd0;
+wire          builder_csrbank0_sel;
+wire    [1:0] builder_csrbank1_dly_sel0_r;
+reg           builder_csrbank1_dly_sel0_re = 1'd0;
+wire    [1:0] builder_csrbank1_dly_sel0_w;
+reg           builder_csrbank1_dly_sel0_we = 1'd0;
+wire    [4:0] builder_csrbank1_half_sys8x_taps0_r;
+reg           builder_csrbank1_half_sys8x_taps0_re = 1'd0;
+wire    [4:0] builder_csrbank1_half_sys8x_taps0_w;
+reg           builder_csrbank1_half_sys8x_taps0_we = 1'd0;
+wire    [1:0] builder_csrbank1_rdphase0_r;
+reg           builder_csrbank1_rdphase0_re = 1'd0;
+wire    [1:0] builder_csrbank1_rdphase0_w;
+reg           builder_csrbank1_rdphase0_we = 1'd0;
+wire          builder_csrbank1_rst0_r;
+reg           builder_csrbank1_rst0_re = 1'd0;
+wire          builder_csrbank1_rst0_w;
+reg           builder_csrbank1_rst0_we = 1'd0;
+wire          builder_csrbank1_sel;
+wire          builder_csrbank1_wlevel_en0_r;
+reg           builder_csrbank1_wlevel_en0_re = 1'd0;
+wire          builder_csrbank1_wlevel_en0_w;
+reg           builder_csrbank1_wlevel_en0_we = 1'd0;
+wire    [1:0] builder_csrbank1_wrphase0_r;
+reg           builder_csrbank1_wrphase0_re = 1'd0;
+wire    [1:0] builder_csrbank1_wrphase0_w;
+reg           builder_csrbank1_wrphase0_we = 1'd0;
+wire    [3:0] builder_csrbank2_dfii_control0_r;
+reg           builder_csrbank2_dfii_control0_re = 1'd0;
+wire    [3:0] builder_csrbank2_dfii_control0_w;
+reg           builder_csrbank2_dfii_control0_we = 1'd0;
+wire   [14:0] builder_csrbank2_dfii_pi0_address0_r;
+reg           builder_csrbank2_dfii_pi0_address0_re = 1'd0;
+wire   [14:0] builder_csrbank2_dfii_pi0_address0_w;
+reg           builder_csrbank2_dfii_pi0_address0_we = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi0_baddress0_r;
+reg           builder_csrbank2_dfii_pi0_baddress0_re = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi0_baddress0_w;
+reg           builder_csrbank2_dfii_pi0_baddress0_we = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi0_command0_r;
+reg           builder_csrbank2_dfii_pi0_command0_re = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi0_command0_w;
+reg           builder_csrbank2_dfii_pi0_command0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi0_rddata_r;
+reg           builder_csrbank2_dfii_pi0_rddata_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi0_rddata_w;
+reg           builder_csrbank2_dfii_pi0_rddata_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi0_wrdata0_r;
+reg           builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi0_wrdata0_w;
+reg           builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0;
+wire   [14:0] builder_csrbank2_dfii_pi1_address0_r;
+reg           builder_csrbank2_dfii_pi1_address0_re = 1'd0;
+wire   [14:0] builder_csrbank2_dfii_pi1_address0_w;
+reg           builder_csrbank2_dfii_pi1_address0_we = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi1_baddress0_r;
+reg           builder_csrbank2_dfii_pi1_baddress0_re = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi1_baddress0_w;
+reg           builder_csrbank2_dfii_pi1_baddress0_we = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi1_command0_r;
+reg           builder_csrbank2_dfii_pi1_command0_re = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi1_command0_w;
+reg           builder_csrbank2_dfii_pi1_command0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi1_rddata_r;
+reg           builder_csrbank2_dfii_pi1_rddata_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi1_rddata_w;
+reg           builder_csrbank2_dfii_pi1_rddata_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi1_wrdata0_r;
+reg           builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi1_wrdata0_w;
+reg           builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0;
+wire   [14:0] builder_csrbank2_dfii_pi2_address0_r;
+reg           builder_csrbank2_dfii_pi2_address0_re = 1'd0;
+wire   [14:0] builder_csrbank2_dfii_pi2_address0_w;
+reg           builder_csrbank2_dfii_pi2_address0_we = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi2_baddress0_r;
+reg           builder_csrbank2_dfii_pi2_baddress0_re = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi2_baddress0_w;
+reg           builder_csrbank2_dfii_pi2_baddress0_we = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi2_command0_r;
+reg           builder_csrbank2_dfii_pi2_command0_re = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi2_command0_w;
+reg           builder_csrbank2_dfii_pi2_command0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi2_rddata_r;
+reg           builder_csrbank2_dfii_pi2_rddata_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi2_rddata_w;
+reg           builder_csrbank2_dfii_pi2_rddata_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi2_wrdata0_r;
+reg           builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi2_wrdata0_w;
+reg           builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0;
+wire   [14:0] builder_csrbank2_dfii_pi3_address0_r;
+reg           builder_csrbank2_dfii_pi3_address0_re = 1'd0;
+wire   [14:0] builder_csrbank2_dfii_pi3_address0_w;
+reg           builder_csrbank2_dfii_pi3_address0_we = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi3_baddress0_r;
+reg           builder_csrbank2_dfii_pi3_baddress0_re = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi3_baddress0_w;
+reg           builder_csrbank2_dfii_pi3_baddress0_we = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi3_command0_r;
+reg           builder_csrbank2_dfii_pi3_command0_re = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi3_command0_w;
+reg           builder_csrbank2_dfii_pi3_command0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi3_rddata_r;
+reg           builder_csrbank2_dfii_pi3_rddata_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi3_rddata_w;
+reg           builder_csrbank2_dfii_pi3_rddata_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi3_wrdata0_r;
+reg           builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi3_wrdata0_w;
+reg           builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0;
+wire          builder_csrbank2_sel;
+wire   [31:0] builder_dat_r;
+wire   [31:0] builder_dat_w;
+reg           builder_interface0_ack = 1'd0;
+wire   [29:0] builder_interface0_adr;
+wire   [13:0] builder_interface0_bank_bus_adr;
+reg    [31:0] builder_interface0_bank_bus_dat_r = 32'd0;
+wire   [31:0] builder_interface0_bank_bus_dat_w;
+wire          builder_interface0_bank_bus_we;
+wire    [1:0] builder_interface0_bte;
+wire    [2:0] builder_interface0_cti;
+wire          builder_interface0_cyc;
+reg    [31:0] builder_interface0_dat_r = 32'd0;
+wire   [31:0] builder_interface0_dat_w;
+reg           builder_interface0_err = 1'd0;
+wire    [3:0] builder_interface0_sel;
+wire          builder_interface0_stb;
+wire          builder_interface0_we;
+reg    [13:0] builder_interface1_adr = 14'd0;
+reg    [13:0] builder_interface1_adr_next_value1 = 14'd0;
+reg           builder_interface1_adr_next_value_ce1 = 1'd0;
+wire   [13:0] builder_interface1_bank_bus_adr;
+reg    [31:0] builder_interface1_bank_bus_dat_r = 32'd0;
+wire   [31:0] builder_interface1_bank_bus_dat_w;
+wire          builder_interface1_bank_bus_we;
+wire   [31:0] builder_interface1_dat_r;
+reg    [31:0] builder_interface1_dat_w = 32'd0;
+reg    [31:0] builder_interface1_dat_w_next_value0 = 32'd0;
+reg           builder_interface1_dat_w_next_value_ce0 = 1'd0;
+reg           builder_interface1_we = 1'd0;
+reg           builder_interface1_we_next_value2 = 1'd0;
+reg           builder_interface1_we_next_value_ce2 = 1'd0;
+wire   [13:0] builder_interface2_bank_bus_adr;
+reg    [31:0] builder_interface2_bank_bus_dat_r = 32'd0;
+wire   [31:0] builder_interface2_bank_bus_dat_w;
+wire          builder_interface2_bank_bus_we;
+reg           builder_locked0 = 1'd0;
+reg           builder_locked1 = 1'd0;
+reg           builder_locked2 = 1'd0;
+reg           builder_locked3 = 1'd0;
+reg           builder_locked4 = 1'd0;
+reg           builder_locked5 = 1'd0;
+reg           builder_locked6 = 1'd0;
+reg           builder_locked7 = 1'd0;
+reg     [3:0] builder_multiplexer_next_state = 4'd0;
+reg     [3:0] builder_multiplexer_state = 4'd0;
+reg           builder_new_master_rdata_valid0 = 1'd0;
+reg           builder_new_master_rdata_valid1 = 1'd0;
+reg           builder_new_master_rdata_valid2 = 1'd0;
+reg           builder_new_master_rdata_valid3 = 1'd0;
+reg           builder_new_master_rdata_valid4 = 1'd0;
+reg           builder_new_master_rdata_valid5 = 1'd0;
+reg           builder_new_master_rdata_valid6 = 1'd0;
+reg           builder_new_master_rdata_valid7 = 1'd0;
+reg           builder_new_master_rdata_valid8 = 1'd0;
+reg           builder_new_master_wdata_ready0 = 1'd0;
+reg           builder_new_master_wdata_ready1 = 1'd0;
+reg     [1:0] builder_next_state = 2'd0;
+wire          builder_pll_fb;
+reg     [1:0] builder_refresher_next_state = 2'd0;
+reg     [1:0] builder_refresher_state = 2'd0;
+wire          builder_reset0;
+wire          builder_reset1;
+wire          builder_reset2;
+wire          builder_reset3;
+wire          builder_reset4;
+wire          builder_reset5;
+wire          builder_reset6;
+wire          builder_reset7;
+reg           builder_rhs_self0 = 1'd0;
+reg    [14:0] builder_rhs_self1 = 15'd0;
+reg           builder_rhs_self10 = 1'd0;
+reg           builder_rhs_self11 = 1'd0;
+reg    [21:0] builder_rhs_self12 = 22'd0;
+reg           builder_rhs_self13 = 1'd0;
+reg           builder_rhs_self14 = 1'd0;
+reg    [21:0] builder_rhs_self15 = 22'd0;
+reg           builder_rhs_self16 = 1'd0;
+reg           builder_rhs_self17 = 1'd0;
+reg    [21:0] builder_rhs_self18 = 22'd0;
+reg           builder_rhs_self19 = 1'd0;
+reg     [2:0] builder_rhs_self2 = 3'd0;
+reg           builder_rhs_self20 = 1'd0;
+reg    [21:0] builder_rhs_self21 = 22'd0;
+reg           builder_rhs_self22 = 1'd0;
+reg           builder_rhs_self23 = 1'd0;
+reg    [21:0] builder_rhs_self24 = 22'd0;
+reg           builder_rhs_self25 = 1'd0;
+reg           builder_rhs_self26 = 1'd0;
+reg    [21:0] builder_rhs_self27 = 22'd0;
+reg           builder_rhs_self28 = 1'd0;
+reg           builder_rhs_self29 = 1'd0;
+reg           builder_rhs_self3 = 1'd0;
+reg    [21:0] builder_rhs_self30 = 22'd0;
+reg           builder_rhs_self31 = 1'd0;
+reg           builder_rhs_self32 = 1'd0;
+reg    [21:0] builder_rhs_self33 = 22'd0;
+reg           builder_rhs_self34 = 1'd0;
+reg           builder_rhs_self35 = 1'd0;
+reg           builder_rhs_self4 = 1'd0;
+reg           builder_rhs_self5 = 1'd0;
+reg           builder_rhs_self6 = 1'd0;
+reg    [14:0] builder_rhs_self7 = 15'd0;
+reg     [2:0] builder_rhs_self8 = 3'd0;
+reg           builder_rhs_self9 = 1'd0;
+wire          builder_roundrobin0_ce;
+wire          builder_roundrobin0_grant;
+wire          builder_roundrobin0_request;
+wire          builder_roundrobin1_ce;
+wire          builder_roundrobin1_grant;
+wire          builder_roundrobin1_request;
+wire          builder_roundrobin2_ce;
+wire          builder_roundrobin2_grant;
+wire          builder_roundrobin2_request;
+wire          builder_roundrobin3_ce;
+wire          builder_roundrobin3_grant;
+wire          builder_roundrobin3_request;
+wire          builder_roundrobin4_ce;
+wire          builder_roundrobin4_grant;
+wire          builder_roundrobin4_request;
+wire          builder_roundrobin5_ce;
+wire          builder_roundrobin5_grant;
+wire          builder_roundrobin5_request;
+wire          builder_roundrobin6_ce;
+wire          builder_roundrobin6_grant;
+wire          builder_roundrobin6_request;
+wire          builder_roundrobin7_ce;
+wire          builder_roundrobin7_grant;
+wire          builder_roundrobin7_request;
+reg     [2:0] builder_self0 = 3'd0;
+reg    [14:0] builder_self1 = 15'd0;
+reg           builder_self10 = 1'd0;
+reg           builder_self11 = 1'd0;
+reg           builder_self12 = 1'd0;
+reg           builder_self13 = 1'd0;
+reg     [2:0] builder_self14 = 3'd0;
+reg    [14:0] builder_self15 = 15'd0;
+reg           builder_self16 = 1'd0;
+reg           builder_self17 = 1'd0;
+reg           builder_self18 = 1'd0;
+reg           builder_self19 = 1'd0;
+reg           builder_self2 = 1'd0;
+reg           builder_self20 = 1'd0;
+reg     [2:0] builder_self21 = 3'd0;
+reg    [14:0] builder_self22 = 15'd0;
+reg           builder_self23 = 1'd0;
+reg           builder_self24 = 1'd0;
+reg           builder_self25 = 1'd0;
+reg           builder_self26 = 1'd0;
+reg           builder_self27 = 1'd0;
+reg           builder_self3 = 1'd0;
+reg           builder_self4 = 1'd0;
+reg           builder_self5 = 1'd0;
+reg           builder_self6 = 1'd0;
+reg     [2:0] builder_self7 = 3'd0;
+reg    [14:0] builder_self8 = 15'd0;
+reg           builder_self9 = 1'd0;
+reg     [1:0] builder_state = 2'd0;
+reg           builder_t_self0 = 1'd0;
+reg           builder_t_self1 = 1'd0;
+reg           builder_t_self2 = 1'd0;
+reg           builder_t_self3 = 1'd0;
+reg           builder_t_self4 = 1'd0;
+reg           builder_t_self5 = 1'd0;
+wire          builder_we;
+wire          builder_xilinxasyncresetsynchronizerimpl0_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl0_rst_meta;
+wire          builder_xilinxasyncresetsynchronizerimpl1_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl1_rst_meta;
+wire          builder_xilinxasyncresetsynchronizerimpl2_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl2_expr;
+wire          builder_xilinxasyncresetsynchronizerimpl2_rst_meta;
+wire          builder_xilinxasyncresetsynchronizerimpl3_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl3_expr;
+wire          builder_xilinxasyncresetsynchronizerimpl3_rst_meta;
 wire          iodelay_clk;
 wire          iodelay_rst;
-wire          reset;
-reg           power_down = 1'd0;
-wire          locked;
-wire          clkin;
-wire          clkout0;
-wire          clkout_buf0;
-wire          clkout1;
-wire          clkout_buf1;
-wire          clkout2;
-wire          clkout_buf2;
-wire          clkout3;
-wire          clkout_buf3;
-reg     [3:0] reset_counter = 4'd15;
-reg           ic_reset = 1'd1;
-reg           a7ddrphy_rst_storage = 1'd0;
-reg           a7ddrphy_rst_re = 1'd0;
-reg     [1:0] a7ddrphy_dly_sel_storage = 2'd0;
-reg           a7ddrphy_dly_sel_re = 1'd0;
-reg     [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8;
-reg           a7ddrphy_half_sys8x_taps_re = 1'd0;
-reg           a7ddrphy_wlevel_en_storage = 1'd0;
-reg           a7ddrphy_wlevel_en_re = 1'd0;
-reg           a7ddrphy_wlevel_strobe_re = 1'd0;
-wire          a7ddrphy_wlevel_strobe_r;
-reg           a7ddrphy_wlevel_strobe_we = 1'd0;
-reg           a7ddrphy_wlevel_strobe_w = 1'd0;
-reg           a7ddrphy_rdly_dq_rst_re = 1'd0;
-wire          a7ddrphy_rdly_dq_rst_r;
-reg           a7ddrphy_rdly_dq_rst_we = 1'd0;
-reg           a7ddrphy_rdly_dq_rst_w = 1'd0;
-reg           a7ddrphy_rdly_dq_inc_re = 1'd0;
-wire          a7ddrphy_rdly_dq_inc_r;
-reg           a7ddrphy_rdly_dq_inc_we = 1'd0;
-reg           a7ddrphy_rdly_dq_inc_w = 1'd0;
-reg           a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
-wire          a7ddrphy_rdly_dq_bitslip_rst_r;
-reg           a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
-reg           a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-reg           a7ddrphy_rdly_dq_bitslip_re = 1'd0;
-wire          a7ddrphy_rdly_dq_bitslip_r;
-reg           a7ddrphy_rdly_dq_bitslip_we = 1'd0;
-reg           a7ddrphy_rdly_dq_bitslip_w = 1'd0;
-reg           a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
-wire          a7ddrphy_wdly_dq_bitslip_rst_r;
-reg           a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
-reg           a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
-reg           a7ddrphy_wdly_dq_bitslip_re = 1'd0;
-wire          a7ddrphy_wdly_dq_bitslip_r;
-reg           a7ddrphy_wdly_dq_bitslip_we = 1'd0;
-reg           a7ddrphy_wdly_dq_bitslip_w = 1'd0;
-reg     [1:0] a7ddrphy_rdphase_storage = 2'd2;
-reg           a7ddrphy_rdphase_re = 1'd0;
-reg     [1:0] a7ddrphy_wrphase_storage = 2'd3;
-reg           a7ddrphy_wrphase_re = 1'd0;
-wire   [14:0] a7ddrphy_dfi_p0_address;
-wire    [2:0] a7ddrphy_dfi_p0_bank;
-wire          a7ddrphy_dfi_p0_cas_n;
-wire          a7ddrphy_dfi_p0_cs_n;
-wire          a7ddrphy_dfi_p0_ras_n;
-wire          a7ddrphy_dfi_p0_we_n;
-wire          a7ddrphy_dfi_p0_cke;
-wire          a7ddrphy_dfi_p0_odt;
-wire          a7ddrphy_dfi_p0_reset_n;
-wire          a7ddrphy_dfi_p0_act_n;
-wire   [31:0] a7ddrphy_dfi_p0_wrdata;
-wire          a7ddrphy_dfi_p0_wrdata_en;
-wire    [3:0] a7ddrphy_dfi_p0_wrdata_mask;
-wire          a7ddrphy_dfi_p0_rddata_en;
-reg    [31:0] a7ddrphy_dfi_p0_rddata = 32'd0;
-wire          a7ddrphy_dfi_p0_rddata_valid;
-wire   [14:0] a7ddrphy_dfi_p1_address;
-wire    [2:0] a7ddrphy_dfi_p1_bank;
-wire          a7ddrphy_dfi_p1_cas_n;
-wire          a7ddrphy_dfi_p1_cs_n;
-wire          a7ddrphy_dfi_p1_ras_n;
-wire          a7ddrphy_dfi_p1_we_n;
-wire          a7ddrphy_dfi_p1_cke;
-wire          a7ddrphy_dfi_p1_odt;
-wire          a7ddrphy_dfi_p1_reset_n;
-wire          a7ddrphy_dfi_p1_act_n;
-wire   [31:0] a7ddrphy_dfi_p1_wrdata;
-wire          a7ddrphy_dfi_p1_wrdata_en;
-wire    [3:0] a7ddrphy_dfi_p1_wrdata_mask;
-wire          a7ddrphy_dfi_p1_rddata_en;
-reg    [31:0] a7ddrphy_dfi_p1_rddata = 32'd0;
-wire          a7ddrphy_dfi_p1_rddata_valid;
-wire   [14:0] a7ddrphy_dfi_p2_address;
-wire    [2:0] a7ddrphy_dfi_p2_bank;
-wire          a7ddrphy_dfi_p2_cas_n;
-wire          a7ddrphy_dfi_p2_cs_n;
-wire          a7ddrphy_dfi_p2_ras_n;
-wire          a7ddrphy_dfi_p2_we_n;
-wire          a7ddrphy_dfi_p2_cke;
-wire          a7ddrphy_dfi_p2_odt;
-wire          a7ddrphy_dfi_p2_reset_n;
-wire          a7ddrphy_dfi_p2_act_n;
-wire   [31:0] a7ddrphy_dfi_p2_wrdata;
-wire          a7ddrphy_dfi_p2_wrdata_en;
-wire    [3:0] a7ddrphy_dfi_p2_wrdata_mask;
-wire          a7ddrphy_dfi_p2_rddata_en;
-reg    [31:0] a7ddrphy_dfi_p2_rddata = 32'd0;
-wire          a7ddrphy_dfi_p2_rddata_valid;
-wire   [14:0] a7ddrphy_dfi_p3_address;
-wire    [2:0] a7ddrphy_dfi_p3_bank;
-wire          a7ddrphy_dfi_p3_cas_n;
-wire          a7ddrphy_dfi_p3_cs_n;
-wire          a7ddrphy_dfi_p3_ras_n;
-wire          a7ddrphy_dfi_p3_we_n;
-wire          a7ddrphy_dfi_p3_cke;
-wire          a7ddrphy_dfi_p3_odt;
-wire          a7ddrphy_dfi_p3_reset_n;
-wire          a7ddrphy_dfi_p3_act_n;
-wire   [31:0] a7ddrphy_dfi_p3_wrdata;
-wire          a7ddrphy_dfi_p3_wrdata_en;
-wire    [3:0] a7ddrphy_dfi_p3_wrdata_mask;
-wire          a7ddrphy_dfi_p3_rddata_en;
-reg    [31:0] a7ddrphy_dfi_p3_rddata = 32'd0;
-wire          a7ddrphy_dfi_p3_rddata_valid;
-wire          a7ddrphy_sd_clk_se_nodelay;
-wire    [2:0] a7ddrphy_pads_ba;
-reg           a7ddrphy_dqs_oe = 1'd0;
-wire          a7ddrphy_dqs_preamble;
-wire          a7ddrphy_dqs_postamble;
-wire          a7ddrphy_dqs_oe_delay_tappeddelayline;
-reg           a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg           a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-reg           a7ddrphy_dqspattern0 = 1'd0;
-reg           a7ddrphy_dqspattern1 = 1'd0;
-reg     [7:0] a7ddrphy_dqspattern_o0 = 8'd0;
-reg     [7:0] a7ddrphy_dqspattern_o1 = 8'd0;
-wire          a7ddrphy_dqs_o_no_delay0;
-wire          a7ddrphy_dqs_t0;
-reg     [7:0] a7ddrphy_bitslip00 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip0_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip0_r0 = 16'd0;
-wire          a7ddrphy0;
-wire          a7ddrphy_dqs_o_no_delay1;
-wire          a7ddrphy_dqs_t1;
-reg     [7:0] a7ddrphy_bitslip10 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip1_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip1_r0 = 16'd0;
-wire          a7ddrphy1;
-reg     [7:0] a7ddrphy_bitslip01 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip0_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip0_r1 = 16'd0;
-reg     [7:0] a7ddrphy_bitslip11 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip1_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip1_r1 = 16'd0;
-wire          a7ddrphy_dq_oe;
-wire          a7ddrphy_dq_oe_delay_tappeddelayline;
-reg           a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg           a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-wire          a7ddrphy_dq_o_nodelay0;
-wire          a7ddrphy_dq_i_nodelay0;
-wire          a7ddrphy_dq_i_delayed0;
-wire          a7ddrphy_dq_t0;
-reg     [7:0] a7ddrphy_bitslip02 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip0_value2 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip0_r2 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip03;
-reg     [7:0] a7ddrphy_bitslip04 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip0_value3 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip0_r3 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay1;
-wire          a7ddrphy_dq_i_nodelay1;
-wire          a7ddrphy_dq_i_delayed1;
-wire          a7ddrphy_dq_t1;
-reg     [7:0] a7ddrphy_bitslip12 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip1_value2 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip1_r2 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip13;
-reg     [7:0] a7ddrphy_bitslip14 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip1_value3 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip1_r3 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay2;
-wire          a7ddrphy_dq_i_nodelay2;
-wire          a7ddrphy_dq_i_delayed2;
-wire          a7ddrphy_dq_t2;
-reg     [7:0] a7ddrphy_bitslip20 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip2_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip2_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip21;
-reg     [7:0] a7ddrphy_bitslip22 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip2_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip2_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay3;
-wire          a7ddrphy_dq_i_nodelay3;
-wire          a7ddrphy_dq_i_delayed3;
-wire          a7ddrphy_dq_t3;
-reg     [7:0] a7ddrphy_bitslip30 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip3_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip3_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip31;
-reg     [7:0] a7ddrphy_bitslip32 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip3_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip3_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay4;
-wire          a7ddrphy_dq_i_nodelay4;
-wire          a7ddrphy_dq_i_delayed4;
-wire          a7ddrphy_dq_t4;
-reg     [7:0] a7ddrphy_bitslip40 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip4_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip4_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip41;
-reg     [7:0] a7ddrphy_bitslip42 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip4_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip4_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay5;
-wire          a7ddrphy_dq_i_nodelay5;
-wire          a7ddrphy_dq_i_delayed5;
-wire          a7ddrphy_dq_t5;
-reg     [7:0] a7ddrphy_bitslip50 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip5_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip5_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip51;
-reg     [7:0] a7ddrphy_bitslip52 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip5_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip5_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay6;
-wire          a7ddrphy_dq_i_nodelay6;
-wire          a7ddrphy_dq_i_delayed6;
-wire          a7ddrphy_dq_t6;
-reg     [7:0] a7ddrphy_bitslip60 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip6_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip6_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip61;
-reg     [7:0] a7ddrphy_bitslip62 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip6_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip6_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay7;
-wire          a7ddrphy_dq_i_nodelay7;
-wire          a7ddrphy_dq_i_delayed7;
-wire          a7ddrphy_dq_t7;
-reg     [7:0] a7ddrphy_bitslip70 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip7_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip7_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip71;
-reg     [7:0] a7ddrphy_bitslip72 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip7_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip7_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay8;
-wire          a7ddrphy_dq_i_nodelay8;
-wire          a7ddrphy_dq_i_delayed8;
-wire          a7ddrphy_dq_t8;
-reg     [7:0] a7ddrphy_bitslip80 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip8_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip8_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip81;
-reg     [7:0] a7ddrphy_bitslip82 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip8_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip8_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay9;
-wire          a7ddrphy_dq_i_nodelay9;
-wire          a7ddrphy_dq_i_delayed9;
-wire          a7ddrphy_dq_t9;
-reg     [7:0] a7ddrphy_bitslip90 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip9_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip9_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip91;
-reg     [7:0] a7ddrphy_bitslip92 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip9_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip9_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay10;
-wire          a7ddrphy_dq_i_nodelay10;
-wire          a7ddrphy_dq_i_delayed10;
-wire          a7ddrphy_dq_t10;
-reg     [7:0] a7ddrphy_bitslip100 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip10_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip10_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip101;
-reg     [7:0] a7ddrphy_bitslip102 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip10_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip10_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay11;
-wire          a7ddrphy_dq_i_nodelay11;
-wire          a7ddrphy_dq_i_delayed11;
-wire          a7ddrphy_dq_t11;
-reg     [7:0] a7ddrphy_bitslip110 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip11_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip11_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip111;
-reg     [7:0] a7ddrphy_bitslip112 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip11_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip11_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay12;
-wire          a7ddrphy_dq_i_nodelay12;
-wire          a7ddrphy_dq_i_delayed12;
-wire          a7ddrphy_dq_t12;
-reg     [7:0] a7ddrphy_bitslip120 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip12_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip12_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip121;
-reg     [7:0] a7ddrphy_bitslip122 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip12_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip12_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay13;
-wire          a7ddrphy_dq_i_nodelay13;
-wire          a7ddrphy_dq_i_delayed13;
-wire          a7ddrphy_dq_t13;
-reg     [7:0] a7ddrphy_bitslip130 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip13_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip13_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip131;
-reg     [7:0] a7ddrphy_bitslip132 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip13_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip13_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay14;
-wire          a7ddrphy_dq_i_nodelay14;
-wire          a7ddrphy_dq_i_delayed14;
-wire          a7ddrphy_dq_t14;
-reg     [7:0] a7ddrphy_bitslip140 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip14_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip14_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip141;
-reg     [7:0] a7ddrphy_bitslip142 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip14_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip14_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay15;
-wire          a7ddrphy_dq_i_nodelay15;
-wire          a7ddrphy_dq_i_delayed15;
-wire          a7ddrphy_dq_t15;
-reg     [7:0] a7ddrphy_bitslip150 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip15_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip15_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip151;
-reg     [7:0] a7ddrphy_bitslip152 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip15_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip15_r1 = 16'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
-reg           a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
-reg           a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
-reg           a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
-wire   [14:0] litedramcore_slave_p0_address;
-wire    [2:0] litedramcore_slave_p0_bank;
-wire          litedramcore_slave_p0_cas_n;
-wire          litedramcore_slave_p0_cs_n;
-wire          litedramcore_slave_p0_ras_n;
-wire          litedramcore_slave_p0_we_n;
-wire          litedramcore_slave_p0_cke;
-wire          litedramcore_slave_p0_odt;
-wire          litedramcore_slave_p0_reset_n;
-wire          litedramcore_slave_p0_act_n;
-wire   [31:0] litedramcore_slave_p0_wrdata;
-wire          litedramcore_slave_p0_wrdata_en;
-wire    [3:0] litedramcore_slave_p0_wrdata_mask;
-wire          litedramcore_slave_p0_rddata_en;
-reg    [31:0] litedramcore_slave_p0_rddata = 32'd0;
-reg           litedramcore_slave_p0_rddata_valid = 1'd0;
-wire   [14:0] litedramcore_slave_p1_address;
-wire    [2:0] litedramcore_slave_p1_bank;
-wire          litedramcore_slave_p1_cas_n;
-wire          litedramcore_slave_p1_cs_n;
-wire          litedramcore_slave_p1_ras_n;
-wire          litedramcore_slave_p1_we_n;
-wire          litedramcore_slave_p1_cke;
-wire          litedramcore_slave_p1_odt;
-wire          litedramcore_slave_p1_reset_n;
-wire          litedramcore_slave_p1_act_n;
-wire   [31:0] litedramcore_slave_p1_wrdata;
-wire          litedramcore_slave_p1_wrdata_en;
-wire    [3:0] litedramcore_slave_p1_wrdata_mask;
-wire          litedramcore_slave_p1_rddata_en;
-reg    [31:0] litedramcore_slave_p1_rddata = 32'd0;
-reg           litedramcore_slave_p1_rddata_valid = 1'd0;
-wire   [14:0] litedramcore_slave_p2_address;
-wire    [2:0] litedramcore_slave_p2_bank;
-wire          litedramcore_slave_p2_cas_n;
-wire          litedramcore_slave_p2_cs_n;
-wire          litedramcore_slave_p2_ras_n;
-wire          litedramcore_slave_p2_we_n;
-wire          litedramcore_slave_p2_cke;
-wire          litedramcore_slave_p2_odt;
-wire          litedramcore_slave_p2_reset_n;
-wire          litedramcore_slave_p2_act_n;
-wire   [31:0] litedramcore_slave_p2_wrdata;
-wire          litedramcore_slave_p2_wrdata_en;
-wire    [3:0] litedramcore_slave_p2_wrdata_mask;
-wire          litedramcore_slave_p2_rddata_en;
-reg    [31:0] litedramcore_slave_p2_rddata = 32'd0;
-reg           litedramcore_slave_p2_rddata_valid = 1'd0;
-wire   [14:0] litedramcore_slave_p3_address;
-wire    [2:0] litedramcore_slave_p3_bank;
-wire          litedramcore_slave_p3_cas_n;
-wire          litedramcore_slave_p3_cs_n;
-wire          litedramcore_slave_p3_ras_n;
-wire          litedramcore_slave_p3_we_n;
-wire          litedramcore_slave_p3_cke;
-wire          litedramcore_slave_p3_odt;
-wire          litedramcore_slave_p3_reset_n;
-wire          litedramcore_slave_p3_act_n;
-wire   [31:0] litedramcore_slave_p3_wrdata;
-wire          litedramcore_slave_p3_wrdata_en;
-wire    [3:0] litedramcore_slave_p3_wrdata_mask;
-wire          litedramcore_slave_p3_rddata_en;
-reg    [31:0] litedramcore_slave_p3_rddata = 32'd0;
-reg           litedramcore_slave_p3_rddata_valid = 1'd0;
-reg    [14:0] litedramcore_master_p0_address = 15'd0;
-reg     [2:0] litedramcore_master_p0_bank = 3'd0;
-reg           litedramcore_master_p0_cas_n = 1'd1;
-reg           litedramcore_master_p0_cs_n = 1'd1;
-reg           litedramcore_master_p0_ras_n = 1'd1;
-reg           litedramcore_master_p0_we_n = 1'd1;
-reg           litedramcore_master_p0_cke = 1'd0;
-reg           litedramcore_master_p0_odt = 1'd0;
-reg           litedramcore_master_p0_reset_n = 1'd0;
-reg           litedramcore_master_p0_act_n = 1'd1;
-reg    [31:0] litedramcore_master_p0_wrdata = 32'd0;
-reg           litedramcore_master_p0_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_master_p0_wrdata_mask = 4'd0;
-reg           litedramcore_master_p0_rddata_en = 1'd0;
-wire   [31:0] litedramcore_master_p0_rddata;
-wire          litedramcore_master_p0_rddata_valid;
-reg    [14:0] litedramcore_master_p1_address = 15'd0;
-reg     [2:0] litedramcore_master_p1_bank = 3'd0;
-reg           litedramcore_master_p1_cas_n = 1'd1;
-reg           litedramcore_master_p1_cs_n = 1'd1;
-reg           litedramcore_master_p1_ras_n = 1'd1;
-reg           litedramcore_master_p1_we_n = 1'd1;
-reg           litedramcore_master_p1_cke = 1'd0;
-reg           litedramcore_master_p1_odt = 1'd0;
-reg           litedramcore_master_p1_reset_n = 1'd0;
-reg           litedramcore_master_p1_act_n = 1'd1;
-reg    [31:0] litedramcore_master_p1_wrdata = 32'd0;
-reg           litedramcore_master_p1_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_master_p1_wrdata_mask = 4'd0;
-reg           litedramcore_master_p1_rddata_en = 1'd0;
-wire   [31:0] litedramcore_master_p1_rddata;
-wire          litedramcore_master_p1_rddata_valid;
-reg    [14:0] litedramcore_master_p2_address = 15'd0;
-reg     [2:0] litedramcore_master_p2_bank = 3'd0;
-reg           litedramcore_master_p2_cas_n = 1'd1;
-reg           litedramcore_master_p2_cs_n = 1'd1;
-reg           litedramcore_master_p2_ras_n = 1'd1;
-reg           litedramcore_master_p2_we_n = 1'd1;
-reg           litedramcore_master_p2_cke = 1'd0;
-reg           litedramcore_master_p2_odt = 1'd0;
-reg           litedramcore_master_p2_reset_n = 1'd0;
-reg           litedramcore_master_p2_act_n = 1'd1;
-reg    [31:0] litedramcore_master_p2_wrdata = 32'd0;
-reg           litedramcore_master_p2_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_master_p2_wrdata_mask = 4'd0;
-reg           litedramcore_master_p2_rddata_en = 1'd0;
-wire   [31:0] litedramcore_master_p2_rddata;
-wire          litedramcore_master_p2_rddata_valid;
-reg    [14:0] litedramcore_master_p3_address = 15'd0;
-reg     [2:0] litedramcore_master_p3_bank = 3'd0;
-reg           litedramcore_master_p3_cas_n = 1'd1;
-reg           litedramcore_master_p3_cs_n = 1'd1;
-reg           litedramcore_master_p3_ras_n = 1'd1;
-reg           litedramcore_master_p3_we_n = 1'd1;
-reg           litedramcore_master_p3_cke = 1'd0;
-reg           litedramcore_master_p3_odt = 1'd0;
-reg           litedramcore_master_p3_reset_n = 1'd0;
-reg           litedramcore_master_p3_act_n = 1'd1;
-reg    [31:0] litedramcore_master_p3_wrdata = 32'd0;
-reg           litedramcore_master_p3_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_master_p3_wrdata_mask = 4'd0;
-reg           litedramcore_master_p3_rddata_en = 1'd0;
-wire   [31:0] litedramcore_master_p3_rddata;
-wire          litedramcore_master_p3_rddata_valid;
-wire   [14:0] litedramcore_csr_dfi_p0_address;
-wire    [2:0] litedramcore_csr_dfi_p0_bank;
-reg           litedramcore_csr_dfi_p0_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p0_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p0_ras_n = 1'd1;
-reg           litedramcore_csr_dfi_p0_we_n = 1'd1;
-wire          litedramcore_csr_dfi_p0_cke;
-wire          litedramcore_csr_dfi_p0_odt;
-wire          litedramcore_csr_dfi_p0_reset_n;
-reg           litedramcore_csr_dfi_p0_act_n = 1'd1;
-wire   [31:0] litedramcore_csr_dfi_p0_wrdata;
-wire          litedramcore_csr_dfi_p0_wrdata_en;
-wire    [3:0] litedramcore_csr_dfi_p0_wrdata_mask;
-wire          litedramcore_csr_dfi_p0_rddata_en;
-reg    [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0;
-reg           litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
-wire   [14:0] litedramcore_csr_dfi_p1_address;
-wire    [2:0] litedramcore_csr_dfi_p1_bank;
-reg           litedramcore_csr_dfi_p1_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p1_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p1_ras_n = 1'd1;
-reg           litedramcore_csr_dfi_p1_we_n = 1'd1;
-wire          litedramcore_csr_dfi_p1_cke;
-wire          litedramcore_csr_dfi_p1_odt;
-wire          litedramcore_csr_dfi_p1_reset_n;
-reg           litedramcore_csr_dfi_p1_act_n = 1'd1;
-wire   [31:0] litedramcore_csr_dfi_p1_wrdata;
-wire          litedramcore_csr_dfi_p1_wrdata_en;
-wire    [3:0] litedramcore_csr_dfi_p1_wrdata_mask;
-wire          litedramcore_csr_dfi_p1_rddata_en;
-reg    [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0;
-reg           litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
-wire   [14:0] litedramcore_csr_dfi_p2_address;
-wire    [2:0] litedramcore_csr_dfi_p2_bank;
-reg           litedramcore_csr_dfi_p2_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p2_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p2_ras_n = 1'd1;
-reg           litedramcore_csr_dfi_p2_we_n = 1'd1;
-wire          litedramcore_csr_dfi_p2_cke;
-wire          litedramcore_csr_dfi_p2_odt;
-wire          litedramcore_csr_dfi_p2_reset_n;
-reg           litedramcore_csr_dfi_p2_act_n = 1'd1;
-wire   [31:0] litedramcore_csr_dfi_p2_wrdata;
-wire          litedramcore_csr_dfi_p2_wrdata_en;
-wire    [3:0] litedramcore_csr_dfi_p2_wrdata_mask;
-wire          litedramcore_csr_dfi_p2_rddata_en;
-reg    [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0;
-reg           litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
-wire   [14:0] litedramcore_csr_dfi_p3_address;
-wire    [2:0] litedramcore_csr_dfi_p3_bank;
-reg           litedramcore_csr_dfi_p3_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p3_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p3_ras_n = 1'd1;
-reg           litedramcore_csr_dfi_p3_we_n = 1'd1;
-wire          litedramcore_csr_dfi_p3_cke;
-wire          litedramcore_csr_dfi_p3_odt;
-wire          litedramcore_csr_dfi_p3_reset_n;
-reg           litedramcore_csr_dfi_p3_act_n = 1'd1;
-wire   [31:0] litedramcore_csr_dfi_p3_wrdata;
-wire          litedramcore_csr_dfi_p3_wrdata_en;
-wire    [3:0] litedramcore_csr_dfi_p3_wrdata_mask;
-wire          litedramcore_csr_dfi_p3_rddata_en;
-reg    [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0;
-reg           litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
-reg    [14:0] litedramcore_ext_dfi_p0_address = 15'd0;
-reg     [2:0] litedramcore_ext_dfi_p0_bank = 3'd0;
-reg           litedramcore_ext_dfi_p0_cas_n = 1'd1;
-reg           litedramcore_ext_dfi_p0_cs_n = 1'd1;
-reg           litedramcore_ext_dfi_p0_ras_n = 1'd1;
-reg           litedramcore_ext_dfi_p0_we_n = 1'd1;
-reg           litedramcore_ext_dfi_p0_cke = 1'd0;
-reg           litedramcore_ext_dfi_p0_odt = 1'd0;
-reg           litedramcore_ext_dfi_p0_reset_n = 1'd0;
-reg           litedramcore_ext_dfi_p0_act_n = 1'd1;
-reg    [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0;
-reg           litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
-reg           litedramcore_ext_dfi_p0_rddata_en = 1'd0;
-reg    [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0;
-reg           litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
-reg    [14:0] litedramcore_ext_dfi_p1_address = 15'd0;
-reg     [2:0] litedramcore_ext_dfi_p1_bank = 3'd0;
-reg           litedramcore_ext_dfi_p1_cas_n = 1'd1;
-reg           litedramcore_ext_dfi_p1_cs_n = 1'd1;
-reg           litedramcore_ext_dfi_p1_ras_n = 1'd1;
-reg           litedramcore_ext_dfi_p1_we_n = 1'd1;
-reg           litedramcore_ext_dfi_p1_cke = 1'd0;
-reg           litedramcore_ext_dfi_p1_odt = 1'd0;
-reg           litedramcore_ext_dfi_p1_reset_n = 1'd0;
-reg           litedramcore_ext_dfi_p1_act_n = 1'd1;
-reg    [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0;
-reg           litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
-reg           litedramcore_ext_dfi_p1_rddata_en = 1'd0;
-reg    [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0;
-reg           litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
-reg    [14:0] litedramcore_ext_dfi_p2_address = 15'd0;
-reg     [2:0] litedramcore_ext_dfi_p2_bank = 3'd0;
-reg           litedramcore_ext_dfi_p2_cas_n = 1'd1;
-reg           litedramcore_ext_dfi_p2_cs_n = 1'd1;
-reg           litedramcore_ext_dfi_p2_ras_n = 1'd1;
-reg           litedramcore_ext_dfi_p2_we_n = 1'd1;
-reg           litedramcore_ext_dfi_p2_cke = 1'd0;
-reg           litedramcore_ext_dfi_p2_odt = 1'd0;
-reg           litedramcore_ext_dfi_p2_reset_n = 1'd0;
-reg           litedramcore_ext_dfi_p2_act_n = 1'd1;
-reg    [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0;
-reg           litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
-reg           litedramcore_ext_dfi_p2_rddata_en = 1'd0;
-reg    [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0;
-reg           litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
-reg    [14:0] litedramcore_ext_dfi_p3_address = 15'd0;
-reg     [2:0] litedramcore_ext_dfi_p3_bank = 3'd0;
-reg           litedramcore_ext_dfi_p3_cas_n = 1'd1;
-reg           litedramcore_ext_dfi_p3_cs_n = 1'd1;
-reg           litedramcore_ext_dfi_p3_ras_n = 1'd1;
-reg           litedramcore_ext_dfi_p3_we_n = 1'd1;
-reg           litedramcore_ext_dfi_p3_cke = 1'd0;
-reg           litedramcore_ext_dfi_p3_odt = 1'd0;
-reg           litedramcore_ext_dfi_p3_reset_n = 1'd0;
-reg           litedramcore_ext_dfi_p3_act_n = 1'd1;
-reg    [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0;
-reg           litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
-reg           litedramcore_ext_dfi_p3_rddata_en = 1'd0;
-reg    [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0;
-reg           litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
-reg           litedramcore_ext_dfi_sel = 1'd0;
-wire          litedramcore_sel;
-wire          litedramcore_cke;
-wire          litedramcore_odt;
-wire          litedramcore_reset_n;
-reg     [3:0] litedramcore_storage = 4'd1;
-reg           litedramcore_re = 1'd0;
-wire          litedramcore_phaseinjector0_csrfield_cs;
-wire          litedramcore_phaseinjector0_csrfield_we;
-wire          litedramcore_phaseinjector0_csrfield_cas;
-wire          litedramcore_phaseinjector0_csrfield_ras;
-wire          litedramcore_phaseinjector0_csrfield_wren;
-wire          litedramcore_phaseinjector0_csrfield_rden;
-reg     [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
-reg           litedramcore_phaseinjector0_command_re = 1'd0;
-reg           litedramcore_phaseinjector0_command_issue_re = 1'd0;
-wire          litedramcore_phaseinjector0_command_issue_r;
-reg           litedramcore_phaseinjector0_command_issue_we = 1'd0;
-reg           litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg    [14:0] litedramcore_phaseinjector0_address_storage = 15'd0;
-reg           litedramcore_phaseinjector0_address_re = 1'd0;
-reg     [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg           litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0;
-reg           litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0;
-wire          litedramcore_phaseinjector0_rddata_we;
-reg           litedramcore_phaseinjector0_rddata_re = 1'd0;
-wire          litedramcore_phaseinjector1_csrfield_cs;
-wire          litedramcore_phaseinjector1_csrfield_we;
-wire          litedramcore_phaseinjector1_csrfield_cas;
-wire          litedramcore_phaseinjector1_csrfield_ras;
-wire          litedramcore_phaseinjector1_csrfield_wren;
-wire          litedramcore_phaseinjector1_csrfield_rden;
-reg     [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
-reg           litedramcore_phaseinjector1_command_re = 1'd0;
-reg           litedramcore_phaseinjector1_command_issue_re = 1'd0;
-wire          litedramcore_phaseinjector1_command_issue_r;
-reg           litedramcore_phaseinjector1_command_issue_we = 1'd0;
-reg           litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg    [14:0] litedramcore_phaseinjector1_address_storage = 15'd0;
-reg           litedramcore_phaseinjector1_address_re = 1'd0;
-reg     [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg           litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0;
-reg           litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0;
-wire          litedramcore_phaseinjector1_rddata_we;
-reg           litedramcore_phaseinjector1_rddata_re = 1'd0;
-wire          litedramcore_phaseinjector2_csrfield_cs;
-wire          litedramcore_phaseinjector2_csrfield_we;
-wire          litedramcore_phaseinjector2_csrfield_cas;
-wire          litedramcore_phaseinjector2_csrfield_ras;
-wire          litedramcore_phaseinjector2_csrfield_wren;
-wire          litedramcore_phaseinjector2_csrfield_rden;
-reg     [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
-reg           litedramcore_phaseinjector2_command_re = 1'd0;
-reg           litedramcore_phaseinjector2_command_issue_re = 1'd0;
-wire          litedramcore_phaseinjector2_command_issue_r;
-reg           litedramcore_phaseinjector2_command_issue_we = 1'd0;
-reg           litedramcore_phaseinjector2_command_issue_w = 1'd0;
-reg    [14:0] litedramcore_phaseinjector2_address_storage = 15'd0;
-reg           litedramcore_phaseinjector2_address_re = 1'd0;
-reg     [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
-reg           litedramcore_phaseinjector2_baddress_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0;
-reg           litedramcore_phaseinjector2_wrdata_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0;
-wire          litedramcore_phaseinjector2_rddata_we;
-reg           litedramcore_phaseinjector2_rddata_re = 1'd0;
-wire          litedramcore_phaseinjector3_csrfield_cs;
-wire          litedramcore_phaseinjector3_csrfield_we;
-wire          litedramcore_phaseinjector3_csrfield_cas;
-wire          litedramcore_phaseinjector3_csrfield_ras;
-wire          litedramcore_phaseinjector3_csrfield_wren;
-wire          litedramcore_phaseinjector3_csrfield_rden;
-reg     [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
-reg           litedramcore_phaseinjector3_command_re = 1'd0;
-reg           litedramcore_phaseinjector3_command_issue_re = 1'd0;
-wire          litedramcore_phaseinjector3_command_issue_r;
-reg           litedramcore_phaseinjector3_command_issue_we = 1'd0;
-reg           litedramcore_phaseinjector3_command_issue_w = 1'd0;
-reg    [14:0] litedramcore_phaseinjector3_address_storage = 15'd0;
-reg           litedramcore_phaseinjector3_address_re = 1'd0;
-reg     [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
-reg           litedramcore_phaseinjector3_baddress_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0;
-reg           litedramcore_phaseinjector3_wrdata_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0;
-wire          litedramcore_phaseinjector3_rddata_we;
-reg           litedramcore_phaseinjector3_rddata_re = 1'd0;
-wire          litedramcore_interface_bank0_valid;
-wire          litedramcore_interface_bank0_ready;
-wire          litedramcore_interface_bank0_we;
-wire   [21:0] litedramcore_interface_bank0_addr;
-wire          litedramcore_interface_bank0_lock;
-wire          litedramcore_interface_bank0_wdata_ready;
-wire          litedramcore_interface_bank0_rdata_valid;
-wire          litedramcore_interface_bank1_valid;
-wire          litedramcore_interface_bank1_ready;
-wire          litedramcore_interface_bank1_we;
-wire   [21:0] litedramcore_interface_bank1_addr;
-wire          litedramcore_interface_bank1_lock;
-wire          litedramcore_interface_bank1_wdata_ready;
-wire          litedramcore_interface_bank1_rdata_valid;
-wire          litedramcore_interface_bank2_valid;
-wire          litedramcore_interface_bank2_ready;
-wire          litedramcore_interface_bank2_we;
-wire   [21:0] litedramcore_interface_bank2_addr;
-wire          litedramcore_interface_bank2_lock;
-wire          litedramcore_interface_bank2_wdata_ready;
-wire          litedramcore_interface_bank2_rdata_valid;
-wire          litedramcore_interface_bank3_valid;
-wire          litedramcore_interface_bank3_ready;
-wire          litedramcore_interface_bank3_we;
-wire   [21:0] litedramcore_interface_bank3_addr;
-wire          litedramcore_interface_bank3_lock;
-wire          litedramcore_interface_bank3_wdata_ready;
-wire          litedramcore_interface_bank3_rdata_valid;
-wire          litedramcore_interface_bank4_valid;
-wire          litedramcore_interface_bank4_ready;
-wire          litedramcore_interface_bank4_we;
-wire   [21:0] litedramcore_interface_bank4_addr;
-wire          litedramcore_interface_bank4_lock;
-wire          litedramcore_interface_bank4_wdata_ready;
-wire          litedramcore_interface_bank4_rdata_valid;
-wire          litedramcore_interface_bank5_valid;
-wire          litedramcore_interface_bank5_ready;
-wire          litedramcore_interface_bank5_we;
-wire   [21:0] litedramcore_interface_bank5_addr;
-wire          litedramcore_interface_bank5_lock;
-wire          litedramcore_interface_bank5_wdata_ready;
-wire          litedramcore_interface_bank5_rdata_valid;
-wire          litedramcore_interface_bank6_valid;
-wire          litedramcore_interface_bank6_ready;
-wire          litedramcore_interface_bank6_we;
-wire   [21:0] litedramcore_interface_bank6_addr;
-wire          litedramcore_interface_bank6_lock;
-wire          litedramcore_interface_bank6_wdata_ready;
-wire          litedramcore_interface_bank6_rdata_valid;
-wire          litedramcore_interface_bank7_valid;
-wire          litedramcore_interface_bank7_ready;
-wire          litedramcore_interface_bank7_we;
-wire   [21:0] litedramcore_interface_bank7_addr;
-wire          litedramcore_interface_bank7_lock;
-wire          litedramcore_interface_bank7_wdata_ready;
-wire          litedramcore_interface_bank7_rdata_valid;
-reg   [127:0] litedramcore_interface_wdata = 128'd0;
-reg    [15:0] litedramcore_interface_wdata_we = 16'd0;
-wire  [127:0] litedramcore_interface_rdata;
-reg    [14:0] litedramcore_dfi_p0_address = 15'd0;
-reg     [2:0] litedramcore_dfi_p0_bank = 3'd0;
-reg           litedramcore_dfi_p0_cas_n = 1'd1;
-reg           litedramcore_dfi_p0_cs_n = 1'd1;
-reg           litedramcore_dfi_p0_ras_n = 1'd1;
-reg           litedramcore_dfi_p0_we_n = 1'd1;
-wire          litedramcore_dfi_p0_cke;
-wire          litedramcore_dfi_p0_odt;
-wire          litedramcore_dfi_p0_reset_n;
-reg           litedramcore_dfi_p0_act_n = 1'd1;
-wire   [31:0] litedramcore_dfi_p0_wrdata;
-reg           litedramcore_dfi_p0_wrdata_en = 1'd0;
-wire    [3:0] litedramcore_dfi_p0_wrdata_mask;
-reg           litedramcore_dfi_p0_rddata_en = 1'd0;
-wire   [31:0] litedramcore_dfi_p0_rddata;
-wire          litedramcore_dfi_p0_rddata_valid;
-reg    [14:0] litedramcore_dfi_p1_address = 15'd0;
-reg     [2:0] litedramcore_dfi_p1_bank = 3'd0;
-reg           litedramcore_dfi_p1_cas_n = 1'd1;
-reg           litedramcore_dfi_p1_cs_n = 1'd1;
-reg           litedramcore_dfi_p1_ras_n = 1'd1;
-reg           litedramcore_dfi_p1_we_n = 1'd1;
-wire          litedramcore_dfi_p1_cke;
-wire          litedramcore_dfi_p1_odt;
-wire          litedramcore_dfi_p1_reset_n;
-reg           litedramcore_dfi_p1_act_n = 1'd1;
-wire   [31:0] litedramcore_dfi_p1_wrdata;
-reg           litedramcore_dfi_p1_wrdata_en = 1'd0;
-wire    [3:0] litedramcore_dfi_p1_wrdata_mask;
-reg           litedramcore_dfi_p1_rddata_en = 1'd0;
-wire   [31:0] litedramcore_dfi_p1_rddata;
-wire          litedramcore_dfi_p1_rddata_valid;
-reg    [14:0] litedramcore_dfi_p2_address = 15'd0;
-reg     [2:0] litedramcore_dfi_p2_bank = 3'd0;
-reg           litedramcore_dfi_p2_cas_n = 1'd1;
-reg           litedramcore_dfi_p2_cs_n = 1'd1;
-reg           litedramcore_dfi_p2_ras_n = 1'd1;
-reg           litedramcore_dfi_p2_we_n = 1'd1;
-wire          litedramcore_dfi_p2_cke;
-wire          litedramcore_dfi_p2_odt;
-wire          litedramcore_dfi_p2_reset_n;
-reg           litedramcore_dfi_p2_act_n = 1'd1;
-wire   [31:0] litedramcore_dfi_p2_wrdata;
-reg           litedramcore_dfi_p2_wrdata_en = 1'd0;
-wire    [3:0] litedramcore_dfi_p2_wrdata_mask;
-reg           litedramcore_dfi_p2_rddata_en = 1'd0;
-wire   [31:0] litedramcore_dfi_p2_rddata;
-wire          litedramcore_dfi_p2_rddata_valid;
-reg    [14:0] litedramcore_dfi_p3_address = 15'd0;
-reg     [2:0] litedramcore_dfi_p3_bank = 3'd0;
-reg           litedramcore_dfi_p3_cas_n = 1'd1;
-reg           litedramcore_dfi_p3_cs_n = 1'd1;
-reg           litedramcore_dfi_p3_ras_n = 1'd1;
-reg           litedramcore_dfi_p3_we_n = 1'd1;
-wire          litedramcore_dfi_p3_cke;
-wire          litedramcore_dfi_p3_odt;
-wire          litedramcore_dfi_p3_reset_n;
-reg           litedramcore_dfi_p3_act_n = 1'd1;
-wire   [31:0] litedramcore_dfi_p3_wrdata;
-reg           litedramcore_dfi_p3_wrdata_en = 1'd0;
-wire    [3:0] litedramcore_dfi_p3_wrdata_mask;
-reg           litedramcore_dfi_p3_rddata_en = 1'd0;
-wire   [31:0] litedramcore_dfi_p3_rddata;
-wire          litedramcore_dfi_p3_rddata_valid;
-reg           litedramcore_cmd_valid = 1'd0;
-reg           litedramcore_cmd_ready = 1'd0;
-reg           litedramcore_cmd_last = 1'd0;
-reg    [14:0] litedramcore_cmd_payload_a = 15'd0;
-reg     [2:0] litedramcore_cmd_payload_ba = 3'd0;
-reg           litedramcore_cmd_payload_cas = 1'd0;
-reg           litedramcore_cmd_payload_ras = 1'd0;
-reg           litedramcore_cmd_payload_we = 1'd0;
-reg           litedramcore_cmd_payload_is_read = 1'd0;
-reg           litedramcore_cmd_payload_is_write = 1'd0;
-wire          litedramcore_wants_refresh;
-wire          litedramcore_wants_zqcs;
-wire          litedramcore_timer_wait;
-wire          litedramcore_timer_done0;
-wire    [9:0] litedramcore_timer_count0;
-wire          litedramcore_timer_done1;
-reg     [9:0] litedramcore_timer_count1 = 10'd781;
-wire          litedramcore_postponer_req_i;
-reg           litedramcore_postponer_req_o = 1'd0;
-reg           litedramcore_postponer_count = 1'd0;
-reg           litedramcore_sequencer_start0 = 1'd0;
-wire          litedramcore_sequencer_done0;
-wire          litedramcore_sequencer_start1;
-reg           litedramcore_sequencer_done1 = 1'd0;
-reg     [5:0] litedramcore_sequencer_counter = 6'd0;
-reg           litedramcore_sequencer_count = 1'd0;
-wire          litedramcore_zqcs_timer_wait;
-wire          litedramcore_zqcs_timer_done0;
-wire   [26:0] litedramcore_zqcs_timer_count0;
-wire          litedramcore_zqcs_timer_done1;
-reg    [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
-reg           litedramcore_zqcs_executer_start = 1'd0;
-reg           litedramcore_zqcs_executer_done = 1'd0;
-reg     [4:0] litedramcore_zqcs_executer_counter = 5'd0;
-wire          litedramcore_bankmachine0_req_valid;
-wire          litedramcore_bankmachine0_req_ready;
-wire          litedramcore_bankmachine0_req_we;
-wire   [21:0] litedramcore_bankmachine0_req_addr;
-wire          litedramcore_bankmachine0_req_lock;
-reg           litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine0_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine0_refresh_req;
-reg           litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg    [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0;
-wire    [2:0] litedramcore_bankmachine0_cmd_payload_ba;
-reg           litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine0_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine0_sink_valid;
-wire          litedramcore_bankmachine0_sink_ready;
-reg           litedramcore_bankmachine0_sink_first = 1'd0;
-reg           litedramcore_bankmachine0_sink_last = 1'd0;
-wire          litedramcore_bankmachine0_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine0_sink_payload_addr;
-wire          litedramcore_bankmachine0_source_valid;
-wire          litedramcore_bankmachine0_source_ready;
-wire          litedramcore_bankmachine0_source_first;
-wire          litedramcore_bankmachine0_source_last;
-wire          litedramcore_bankmachine0_source_payload_we;
-wire   [21:0] litedramcore_bankmachine0_source_payload_addr;
-wire          litedramcore_bankmachine0_syncfifo0_we;
-wire          litedramcore_bankmachine0_syncfifo0_writable;
-wire          litedramcore_bankmachine0_syncfifo0_re;
-wire          litedramcore_bankmachine0_syncfifo0_readable;
-wire   [24:0] litedramcore_bankmachine0_syncfifo0_din;
-wire   [24:0] litedramcore_bankmachine0_syncfifo0_dout;
-reg     [4:0] litedramcore_bankmachine0_level = 5'd0;
-reg           litedramcore_bankmachine0_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine0_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine0_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0;
-wire   [24:0] litedramcore_bankmachine0_wrport_dat_r;
-wire          litedramcore_bankmachine0_wrport_we;
-wire   [24:0] litedramcore_bankmachine0_wrport_dat_w;
-wire          litedramcore_bankmachine0_do_read;
-wire    [3:0] litedramcore_bankmachine0_rdport_adr;
-wire   [24:0] litedramcore_bankmachine0_rdport_dat_r;
-wire          litedramcore_bankmachine0_fifo_in_payload_we;
-wire   [21:0] litedramcore_bankmachine0_fifo_in_payload_addr;
-wire          litedramcore_bankmachine0_fifo_in_first;
-wire          litedramcore_bankmachine0_fifo_in_last;
-wire          litedramcore_bankmachine0_fifo_out_payload_we;
-wire   [21:0] litedramcore_bankmachine0_fifo_out_payload_addr;
-wire          litedramcore_bankmachine0_fifo_out_first;
-wire          litedramcore_bankmachine0_fifo_out_last;
-wire          litedramcore_bankmachine0_sink_sink_valid;
-wire          litedramcore_bankmachine0_sink_sink_ready;
-wire          litedramcore_bankmachine0_sink_sink_first;
-wire          litedramcore_bankmachine0_sink_sink_last;
-wire          litedramcore_bankmachine0_sink_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine0_sink_sink_payload_addr;
-wire          litedramcore_bankmachine0_source_source_valid;
-wire          litedramcore_bankmachine0_source_source_ready;
-wire          litedramcore_bankmachine0_source_source_first;
-wire          litedramcore_bankmachine0_source_source_last;
-wire          litedramcore_bankmachine0_source_source_payload_we;
-wire   [21:0] litedramcore_bankmachine0_source_source_payload_addr;
-wire          litedramcore_bankmachine0_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine0_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine0_pipe_valid_sink_first;
-wire          litedramcore_bankmachine0_pipe_valid_sink_last;
-wire          litedramcore_bankmachine0_pipe_valid_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine0_pipe_valid_source_ready;
-reg           litedramcore_bankmachine0_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine0_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0;
-reg    [21:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 22'd0;
-reg    [14:0] litedramcore_bankmachine0_row = 15'd0;
-reg           litedramcore_bankmachine0_row_opened = 1'd0;
-wire          litedramcore_bankmachine0_row_hit;
-reg           litedramcore_bankmachine0_row_open = 1'd0;
-reg           litedramcore_bankmachine0_row_close = 1'd0;
-reg           litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine0_twtpcon_valid;
+wire          main_a7ddrphy0;
+wire          main_a7ddrphy1;
+reg     [7:0] main_a7ddrphy_bitslip00 = 8'd0;
+reg     [7:0] main_a7ddrphy_bitslip01 = 8'd0;
+reg     [7:0] main_a7ddrphy_bitslip02 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip03;
+reg     [7:0] main_a7ddrphy_bitslip04 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip10 = 8'd0;
+reg     [7:0] main_a7ddrphy_bitslip100 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip101;
+reg     [7:0] main_a7ddrphy_bitslip102 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip11 = 8'd0;
+reg     [7:0] main_a7ddrphy_bitslip110 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip111;
+reg     [7:0] main_a7ddrphy_bitslip112 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip12 = 8'd0;
+reg     [7:0] main_a7ddrphy_bitslip120 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip121;
+reg     [7:0] main_a7ddrphy_bitslip122 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7;
+wire    [7:0] main_a7ddrphy_bitslip13;
+reg     [7:0] main_a7ddrphy_bitslip130 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip131;
+reg     [7:0] main_a7ddrphy_bitslip132 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip14 = 8'd0;
+reg     [7:0] main_a7ddrphy_bitslip140 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip141;
+reg     [7:0] main_a7ddrphy_bitslip142 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip150 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip151;
+reg     [7:0] main_a7ddrphy_bitslip152 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7;
+reg    [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip20 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip21;
+reg     [7:0] main_a7ddrphy_bitslip22 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip30 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip31;
+reg     [7:0] main_a7ddrphy_bitslip32 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip40 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip41;
+reg     [7:0] main_a7ddrphy_bitslip42 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip50 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip51;
+reg     [7:0] main_a7ddrphy_bitslip52 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip60 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip61;
+reg     [7:0] main_a7ddrphy_bitslip62 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip70 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip71;
+reg     [7:0] main_a7ddrphy_bitslip72 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip80 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip81;
+reg     [7:0] main_a7ddrphy_bitslip82 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip90 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip91;
+reg     [7:0] main_a7ddrphy_bitslip92 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7;
+wire          main_a7ddrphy_dfi_p0_act_n;
+wire   [14:0] main_a7ddrphy_dfi_p0_address;
+wire    [2:0] main_a7ddrphy_dfi_p0_bank;
+wire          main_a7ddrphy_dfi_p0_cas_n;
+wire          main_a7ddrphy_dfi_p0_cke;
+wire          main_a7ddrphy_dfi_p0_cs_n;
+wire          main_a7ddrphy_dfi_p0_odt;
+wire          main_a7ddrphy_dfi_p0_ras_n;
+reg    [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0;
+wire          main_a7ddrphy_dfi_p0_rddata_en;
+wire          main_a7ddrphy_dfi_p0_rddata_valid;
+wire          main_a7ddrphy_dfi_p0_reset_n;
+wire          main_a7ddrphy_dfi_p0_we_n;
+wire   [31:0] main_a7ddrphy_dfi_p0_wrdata;
+wire          main_a7ddrphy_dfi_p0_wrdata_en;
+wire    [3:0] main_a7ddrphy_dfi_p0_wrdata_mask;
+wire          main_a7ddrphy_dfi_p1_act_n;
+wire   [14:0] main_a7ddrphy_dfi_p1_address;
+wire    [2:0] main_a7ddrphy_dfi_p1_bank;
+wire          main_a7ddrphy_dfi_p1_cas_n;
+wire          main_a7ddrphy_dfi_p1_cke;
+wire          main_a7ddrphy_dfi_p1_cs_n;
+wire          main_a7ddrphy_dfi_p1_odt;
+wire          main_a7ddrphy_dfi_p1_ras_n;
+reg    [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0;
+wire          main_a7ddrphy_dfi_p1_rddata_en;
+wire          main_a7ddrphy_dfi_p1_rddata_valid;
+wire          main_a7ddrphy_dfi_p1_reset_n;
+wire          main_a7ddrphy_dfi_p1_we_n;
+wire   [31:0] main_a7ddrphy_dfi_p1_wrdata;
+wire          main_a7ddrphy_dfi_p1_wrdata_en;
+wire    [3:0] main_a7ddrphy_dfi_p1_wrdata_mask;
+wire          main_a7ddrphy_dfi_p2_act_n;
+wire   [14:0] main_a7ddrphy_dfi_p2_address;
+wire    [2:0] main_a7ddrphy_dfi_p2_bank;
+wire          main_a7ddrphy_dfi_p2_cas_n;
+wire          main_a7ddrphy_dfi_p2_cke;
+wire          main_a7ddrphy_dfi_p2_cs_n;
+wire          main_a7ddrphy_dfi_p2_odt;
+wire          main_a7ddrphy_dfi_p2_ras_n;
+reg    [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0;
+wire          main_a7ddrphy_dfi_p2_rddata_en;
+wire          main_a7ddrphy_dfi_p2_rddata_valid;
+wire          main_a7ddrphy_dfi_p2_reset_n;
+wire          main_a7ddrphy_dfi_p2_we_n;
+wire   [31:0] main_a7ddrphy_dfi_p2_wrdata;
+wire          main_a7ddrphy_dfi_p2_wrdata_en;
+wire    [3:0] main_a7ddrphy_dfi_p2_wrdata_mask;
+wire          main_a7ddrphy_dfi_p3_act_n;
+wire   [14:0] main_a7ddrphy_dfi_p3_address;
+wire    [2:0] main_a7ddrphy_dfi_p3_bank;
+wire          main_a7ddrphy_dfi_p3_cas_n;
+wire          main_a7ddrphy_dfi_p3_cke;
+wire          main_a7ddrphy_dfi_p3_cs_n;
+wire          main_a7ddrphy_dfi_p3_odt;
+wire          main_a7ddrphy_dfi_p3_ras_n;
+reg    [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0;
+wire          main_a7ddrphy_dfi_p3_rddata_en;
+wire          main_a7ddrphy_dfi_p3_rddata_valid;
+wire          main_a7ddrphy_dfi_p3_reset_n;
+wire          main_a7ddrphy_dfi_p3_we_n;
+wire   [31:0] main_a7ddrphy_dfi_p3_wrdata;
+wire          main_a7ddrphy_dfi_p3_wrdata_en;
+wire    [3:0] main_a7ddrphy_dfi_p3_wrdata_mask;
+reg           main_a7ddrphy_dly_sel_re = 1'd0;
+reg     [1:0] main_a7ddrphy_dly_sel_storage = 2'd0;
+wire          main_a7ddrphy_dq_i_delayed0;
+wire          main_a7ddrphy_dq_i_delayed1;
+wire          main_a7ddrphy_dq_i_delayed10;
+wire          main_a7ddrphy_dq_i_delayed11;
+wire          main_a7ddrphy_dq_i_delayed12;
+wire          main_a7ddrphy_dq_i_delayed13;
+wire          main_a7ddrphy_dq_i_delayed14;
+wire          main_a7ddrphy_dq_i_delayed15;
+wire          main_a7ddrphy_dq_i_delayed2;
+wire          main_a7ddrphy_dq_i_delayed3;
+wire          main_a7ddrphy_dq_i_delayed4;
+wire          main_a7ddrphy_dq_i_delayed5;
+wire          main_a7ddrphy_dq_i_delayed6;
+wire          main_a7ddrphy_dq_i_delayed7;
+wire          main_a7ddrphy_dq_i_delayed8;
+wire          main_a7ddrphy_dq_i_delayed9;
+wire          main_a7ddrphy_dq_i_nodelay0;
+wire          main_a7ddrphy_dq_i_nodelay1;
+wire          main_a7ddrphy_dq_i_nodelay10;
+wire          main_a7ddrphy_dq_i_nodelay11;
+wire          main_a7ddrphy_dq_i_nodelay12;
+wire          main_a7ddrphy_dq_i_nodelay13;
+wire          main_a7ddrphy_dq_i_nodelay14;
+wire          main_a7ddrphy_dq_i_nodelay15;
+wire          main_a7ddrphy_dq_i_nodelay2;
+wire          main_a7ddrphy_dq_i_nodelay3;
+wire          main_a7ddrphy_dq_i_nodelay4;
+wire          main_a7ddrphy_dq_i_nodelay5;
+wire          main_a7ddrphy_dq_i_nodelay6;
+wire          main_a7ddrphy_dq_i_nodelay7;
+wire          main_a7ddrphy_dq_i_nodelay8;
+wire          main_a7ddrphy_dq_i_nodelay9;
+wire          main_a7ddrphy_dq_o_nodelay0;
+wire          main_a7ddrphy_dq_o_nodelay1;
+wire          main_a7ddrphy_dq_o_nodelay10;
+wire          main_a7ddrphy_dq_o_nodelay11;
+wire          main_a7ddrphy_dq_o_nodelay12;
+wire          main_a7ddrphy_dq_o_nodelay13;
+wire          main_a7ddrphy_dq_o_nodelay14;
+wire          main_a7ddrphy_dq_o_nodelay15;
+wire          main_a7ddrphy_dq_o_nodelay2;
+wire          main_a7ddrphy_dq_o_nodelay3;
+wire          main_a7ddrphy_dq_o_nodelay4;
+wire          main_a7ddrphy_dq_o_nodelay5;
+wire          main_a7ddrphy_dq_o_nodelay6;
+wire          main_a7ddrphy_dq_o_nodelay7;
+wire          main_a7ddrphy_dq_o_nodelay8;
+wire          main_a7ddrphy_dq_o_nodelay9;
+wire          main_a7ddrphy_dq_oe;
+wire          main_a7ddrphy_dq_oe_delay_tappeddelayline;
+reg           main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg           main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+wire          main_a7ddrphy_dq_t0;
+wire          main_a7ddrphy_dq_t1;
+wire          main_a7ddrphy_dq_t10;
+wire          main_a7ddrphy_dq_t11;
+wire          main_a7ddrphy_dq_t12;
+wire          main_a7ddrphy_dq_t13;
+wire          main_a7ddrphy_dq_t14;
+wire          main_a7ddrphy_dq_t15;
+wire          main_a7ddrphy_dq_t2;
+wire          main_a7ddrphy_dq_t3;
+wire          main_a7ddrphy_dq_t4;
+wire          main_a7ddrphy_dq_t5;
+wire          main_a7ddrphy_dq_t6;
+wire          main_a7ddrphy_dq_t7;
+wire          main_a7ddrphy_dq_t8;
+wire          main_a7ddrphy_dq_t9;
+wire          main_a7ddrphy_dqs_o_no_delay0;
+wire          main_a7ddrphy_dqs_o_no_delay1;
+reg           main_a7ddrphy_dqs_oe = 1'd0;
+wire          main_a7ddrphy_dqs_oe_delay_tappeddelayline;
+reg           main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg           main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+wire          main_a7ddrphy_dqs_postamble;
+wire          main_a7ddrphy_dqs_preamble;
+wire          main_a7ddrphy_dqs_t0;
+wire          main_a7ddrphy_dqs_t1;
+reg           main_a7ddrphy_dqspattern0 = 1'd0;
+reg           main_a7ddrphy_dqspattern1 = 1'd0;
+reg     [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0;
+reg     [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0;
+reg           main_a7ddrphy_half_sys8x_taps_re = 1'd0;
+reg     [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8;
+wire    [2:0] main_a7ddrphy_pads_ba;
+reg           main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
+wire          main_a7ddrphy_rdly_dq_bitslip_r;
+reg           main_a7ddrphy_rdly_dq_bitslip_re = 1'd0;
+wire          main_a7ddrphy_rdly_dq_bitslip_rst_r;
+reg           main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
+reg           main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+reg           main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
+reg           main_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
+reg           main_a7ddrphy_rdly_dq_bitslip_we = 1'd0;
+wire          main_a7ddrphy_rdly_dq_inc_r;
+reg           main_a7ddrphy_rdly_dq_inc_re = 1'd0;
+reg           main_a7ddrphy_rdly_dq_inc_w = 1'd0;
+reg           main_a7ddrphy_rdly_dq_inc_we = 1'd0;
+wire          main_a7ddrphy_rdly_dq_rst_r;
+reg           main_a7ddrphy_rdly_dq_rst_re = 1'd0;
+reg           main_a7ddrphy_rdly_dq_rst_w = 1'd0;
+reg           main_a7ddrphy_rdly_dq_rst_we = 1'd0;
+reg           main_a7ddrphy_rdphase_re = 1'd0;
+reg     [1:0] main_a7ddrphy_rdphase_storage = 2'd2;
+reg           main_a7ddrphy_rst_re = 1'd0;
+reg           main_a7ddrphy_rst_storage = 1'd0;
+wire          main_a7ddrphy_sd_clk_se_nodelay;
+wire          main_a7ddrphy_wdly_dq_bitslip_r;
+reg           main_a7ddrphy_wdly_dq_bitslip_re = 1'd0;
+wire          main_a7ddrphy_wdly_dq_bitslip_rst_r;
+reg           main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
+reg           main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
+reg           main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
+reg           main_a7ddrphy_wdly_dq_bitslip_w = 1'd0;
+reg           main_a7ddrphy_wdly_dq_bitslip_we = 1'd0;
+reg           main_a7ddrphy_wlevel_en_re = 1'd0;
+reg           main_a7ddrphy_wlevel_en_storage = 1'd0;
+wire          main_a7ddrphy_wlevel_strobe_r;
+reg           main_a7ddrphy_wlevel_strobe_re = 1'd0;
+reg           main_a7ddrphy_wlevel_strobe_w = 1'd0;
+reg           main_a7ddrphy_wlevel_strobe_we = 1'd0;
+reg           main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
+reg           main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
+reg           main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
+reg           main_a7ddrphy_wrphase_re = 1'd0;
+reg     [1:0] main_a7ddrphy_wrphase_storage = 2'd3;
+wire          main_clkin;
+wire          main_clkout0;
+wire          main_clkout1;
+wire          main_clkout2;
+wire          main_clkout3;
+wire          main_clkout_buf0;
+wire          main_clkout_buf1;
+wire          main_clkout_buf2;
+wire          main_clkout_buf3;
+reg           main_ic_reset = 1'd1;
+reg           main_init_done_re = 1'd0;
+reg           main_init_done_storage = 1'd0;
+reg           main_init_error_re = 1'd0;
+reg           main_init_error_storage = 1'd0;
+reg           main_litedramcore_bankmachine0_auto_precharge = 1'd0;
+reg    [14:0] main_litedramcore_bankmachine0_cmd_payload_a = 15'd0;
+wire    [2:0] main_litedramcore_bankmachine0_cmd_payload_ba;
+reg           main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine0_consume = 4'd0;
+wire          main_litedramcore_bankmachine0_do_read;
+wire          main_litedramcore_bankmachine0_fifo_in_first;
+wire          main_litedramcore_bankmachine0_fifo_in_last;
+wire   [21:0] main_litedramcore_bankmachine0_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine0_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine0_fifo_out_first;
+wire          main_litedramcore_bankmachine0_fifo_out_last;
+wire   [21:0] main_litedramcore_bankmachine0_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine0_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine0_level = 5'd0;
+wire          main_litedramcore_bankmachine0_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine0_pipe_valid_sink_last;
+wire   [21:0] main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine0_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine0_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine0_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine0_pipe_valid_source_last = 1'd0;
+reg    [21:0] main_litedramcore_bankmachine0_pipe_valid_source_payload_addr = 22'd0;
+reg           main_litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine0_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine0_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine0_rdport_adr;
+wire   [24:0] main_litedramcore_bankmachine0_rdport_dat_r;
+reg           main_litedramcore_bankmachine0_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine0_refresh_req;
+reg           main_litedramcore_bankmachine0_replace = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine0_req_addr;
+wire          main_litedramcore_bankmachine0_req_lock;
+reg           main_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine0_req_ready;
+wire          main_litedramcore_bankmachine0_req_valid;
+reg           main_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine0_req_we;
+reg    [14:0] main_litedramcore_bankmachine0_row = 15'd0;
+reg           main_litedramcore_bankmachine0_row_close = 1'd0;
+reg           main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine0_row_hit;
+reg           main_litedramcore_bankmachine0_row_open = 1'd0;
+reg           main_litedramcore_bankmachine0_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine0_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine0_sink_last = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine0_sink_payload_addr;
+wire          main_litedramcore_bankmachine0_sink_payload_we;
+wire          main_litedramcore_bankmachine0_sink_ready;
+wire          main_litedramcore_bankmachine0_sink_sink_first;
+wire          main_litedramcore_bankmachine0_sink_sink_last;
+wire   [21:0] main_litedramcore_bankmachine0_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine0_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine0_sink_sink_ready;
+wire          main_litedramcore_bankmachine0_sink_sink_valid;
+wire          main_litedramcore_bankmachine0_sink_valid;
+wire          main_litedramcore_bankmachine0_source_first;
+wire          main_litedramcore_bankmachine0_source_last;
+wire   [21:0] main_litedramcore_bankmachine0_source_payload_addr;
+wire          main_litedramcore_bankmachine0_source_payload_we;
+wire          main_litedramcore_bankmachine0_source_ready;
+wire          main_litedramcore_bankmachine0_source_source_first;
+wire          main_litedramcore_bankmachine0_source_source_last;
+wire   [21:0] main_litedramcore_bankmachine0_source_source_payload_addr;
+wire          main_litedramcore_bankmachine0_source_source_payload_we;
+wire          main_litedramcore_bankmachine0_source_source_ready;
+wire          main_litedramcore_bankmachine0_source_source_valid;
+wire          main_litedramcore_bankmachine0_source_valid;
+wire   [24:0] main_litedramcore_bankmachine0_syncfifo0_din;
+wire   [24:0] main_litedramcore_bankmachine0_syncfifo0_dout;
+wire          main_litedramcore_bankmachine0_syncfifo0_re;
+wire          main_litedramcore_bankmachine0_syncfifo0_readable;
+wire          main_litedramcore_bankmachine0_syncfifo0_we;
+wire          main_litedramcore_bankmachine0_syncfifo0_writable;
+reg     [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine0_trccon_valid;
+reg           main_litedramcore_bankmachine0_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine0_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
-wire          litedramcore_bankmachine0_trascon_valid;
+reg           main_litedramcore_bankmachine0_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine0_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine0_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
-wire          litedramcore_bankmachine1_req_valid;
-wire          litedramcore_bankmachine1_req_ready;
-wire          litedramcore_bankmachine1_req_we;
-wire   [21:0] litedramcore_bankmachine1_req_addr;
-wire          litedramcore_bankmachine1_req_lock;
-reg           litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine1_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine1_refresh_req;
-reg           litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine1_cmd_ready = 1'd0;
-reg    [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0;
-wire    [2:0] litedramcore_bankmachine1_cmd_payload_ba;
-reg           litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine1_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine1_sink_valid;
-wire          litedramcore_bankmachine1_sink_ready;
-reg           litedramcore_bankmachine1_sink_first = 1'd0;
-reg           litedramcore_bankmachine1_sink_last = 1'd0;
-wire          litedramcore_bankmachine1_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine1_sink_payload_addr;
-wire          litedramcore_bankmachine1_source_valid;
-wire          litedramcore_bankmachine1_source_ready;
-wire          litedramcore_bankmachine1_source_first;
-wire          litedramcore_bankmachine1_source_last;
-wire          litedramcore_bankmachine1_source_payload_we;
-wire   [21:0] litedramcore_bankmachine1_source_payload_addr;
-wire          litedramcore_bankmachine1_syncfifo1_we;
-wire          litedramcore_bankmachine1_syncfifo1_writable;
-wire          litedramcore_bankmachine1_syncfifo1_re;
-wire          litedramcore_bankmachine1_syncfifo1_readable;
-wire   [24:0] litedramcore_bankmachine1_syncfifo1_din;
-wire   [24:0] litedramcore_bankmachine1_syncfifo1_dout;
-reg     [4:0] litedramcore_bankmachine1_level = 5'd0;
-reg           litedramcore_bankmachine1_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine1_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine1_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0;
-wire   [24:0] litedramcore_bankmachine1_wrport_dat_r;
-wire          litedramcore_bankmachine1_wrport_we;
-wire   [24:0] litedramcore_bankmachine1_wrport_dat_w;
-wire          litedramcore_bankmachine1_do_read;
-wire    [3:0] litedramcore_bankmachine1_rdport_adr;
-wire   [24:0] litedramcore_bankmachine1_rdport_dat_r;
-wire          litedramcore_bankmachine1_fifo_in_payload_we;
-wire   [21:0] litedramcore_bankmachine1_fifo_in_payload_addr;
-wire          litedramcore_bankmachine1_fifo_in_first;
-wire          litedramcore_bankmachine1_fifo_in_last;
-wire          litedramcore_bankmachine1_fifo_out_payload_we;
-wire   [21:0] litedramcore_bankmachine1_fifo_out_payload_addr;
-wire          litedramcore_bankmachine1_fifo_out_first;
-wire          litedramcore_bankmachine1_fifo_out_last;
-wire          litedramcore_bankmachine1_sink_sink_valid;
-wire          litedramcore_bankmachine1_sink_sink_ready;
-wire          litedramcore_bankmachine1_sink_sink_first;
-wire          litedramcore_bankmachine1_sink_sink_last;
-wire          litedramcore_bankmachine1_sink_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine1_sink_sink_payload_addr;
-wire          litedramcore_bankmachine1_source_source_valid;
-wire          litedramcore_bankmachine1_source_source_ready;
-wire          litedramcore_bankmachine1_source_source_first;
-wire          litedramcore_bankmachine1_source_source_last;
-wire          litedramcore_bankmachine1_source_source_payload_we;
-wire   [21:0] litedramcore_bankmachine1_source_source_payload_addr;
-wire          litedramcore_bankmachine1_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine1_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine1_pipe_valid_sink_first;
-wire          litedramcore_bankmachine1_pipe_valid_sink_last;
-wire          litedramcore_bankmachine1_pipe_valid_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine1_pipe_valid_source_ready;
-reg           litedramcore_bankmachine1_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine1_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0;
-reg    [21:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 22'd0;
-reg    [14:0] litedramcore_bankmachine1_row = 15'd0;
-reg           litedramcore_bankmachine1_row_opened = 1'd0;
-wire          litedramcore_bankmachine1_row_hit;
-reg           litedramcore_bankmachine1_row_open = 1'd0;
-reg           litedramcore_bankmachine1_row_close = 1'd0;
-reg           litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine1_twtpcon_valid;
+reg           main_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine0_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine0_wrport_adr = 4'd0;
+wire   [24:0] main_litedramcore_bankmachine0_wrport_dat_r;
+wire   [24:0] main_litedramcore_bankmachine0_wrport_dat_w;
+wire          main_litedramcore_bankmachine0_wrport_we;
+reg           main_litedramcore_bankmachine1_auto_precharge = 1'd0;
+reg    [14:0] main_litedramcore_bankmachine1_cmd_payload_a = 15'd0;
+wire    [2:0] main_litedramcore_bankmachine1_cmd_payload_ba;
+reg           main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine1_consume = 4'd0;
+wire          main_litedramcore_bankmachine1_do_read;
+wire          main_litedramcore_bankmachine1_fifo_in_first;
+wire          main_litedramcore_bankmachine1_fifo_in_last;
+wire   [21:0] main_litedramcore_bankmachine1_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine1_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine1_fifo_out_first;
+wire          main_litedramcore_bankmachine1_fifo_out_last;
+wire   [21:0] main_litedramcore_bankmachine1_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine1_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine1_level = 5'd0;
+wire          main_litedramcore_bankmachine1_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine1_pipe_valid_sink_last;
+wire   [21:0] main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine1_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine1_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine1_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine1_pipe_valid_source_last = 1'd0;
+reg    [21:0] main_litedramcore_bankmachine1_pipe_valid_source_payload_addr = 22'd0;
+reg           main_litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine1_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine1_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine1_rdport_adr;
+wire   [24:0] main_litedramcore_bankmachine1_rdport_dat_r;
+reg           main_litedramcore_bankmachine1_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine1_refresh_req;
+reg           main_litedramcore_bankmachine1_replace = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine1_req_addr;
+wire          main_litedramcore_bankmachine1_req_lock;
+reg           main_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine1_req_ready;
+wire          main_litedramcore_bankmachine1_req_valid;
+reg           main_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine1_req_we;
+reg    [14:0] main_litedramcore_bankmachine1_row = 15'd0;
+reg           main_litedramcore_bankmachine1_row_close = 1'd0;
+reg           main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine1_row_hit;
+reg           main_litedramcore_bankmachine1_row_open = 1'd0;
+reg           main_litedramcore_bankmachine1_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine1_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine1_sink_last = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine1_sink_payload_addr;
+wire          main_litedramcore_bankmachine1_sink_payload_we;
+wire          main_litedramcore_bankmachine1_sink_ready;
+wire          main_litedramcore_bankmachine1_sink_sink_first;
+wire          main_litedramcore_bankmachine1_sink_sink_last;
+wire   [21:0] main_litedramcore_bankmachine1_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine1_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine1_sink_sink_ready;
+wire          main_litedramcore_bankmachine1_sink_sink_valid;
+wire          main_litedramcore_bankmachine1_sink_valid;
+wire          main_litedramcore_bankmachine1_source_first;
+wire          main_litedramcore_bankmachine1_source_last;
+wire   [21:0] main_litedramcore_bankmachine1_source_payload_addr;
+wire          main_litedramcore_bankmachine1_source_payload_we;
+wire          main_litedramcore_bankmachine1_source_ready;
+wire          main_litedramcore_bankmachine1_source_source_first;
+wire          main_litedramcore_bankmachine1_source_source_last;
+wire   [21:0] main_litedramcore_bankmachine1_source_source_payload_addr;
+wire          main_litedramcore_bankmachine1_source_source_payload_we;
+wire          main_litedramcore_bankmachine1_source_source_ready;
+wire          main_litedramcore_bankmachine1_source_source_valid;
+wire          main_litedramcore_bankmachine1_source_valid;
+wire   [24:0] main_litedramcore_bankmachine1_syncfifo1_din;
+wire   [24:0] main_litedramcore_bankmachine1_syncfifo1_dout;
+wire          main_litedramcore_bankmachine1_syncfifo1_re;
+wire          main_litedramcore_bankmachine1_syncfifo1_readable;
+wire          main_litedramcore_bankmachine1_syncfifo1_we;
+wire          main_litedramcore_bankmachine1_syncfifo1_writable;
+reg     [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine1_trccon_valid;
+reg           main_litedramcore_bankmachine1_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine1_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
-wire          litedramcore_bankmachine1_trascon_valid;
+reg           main_litedramcore_bankmachine1_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine1_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine1_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
-wire          litedramcore_bankmachine2_req_valid;
-wire          litedramcore_bankmachine2_req_ready;
-wire          litedramcore_bankmachine2_req_we;
-wire   [21:0] litedramcore_bankmachine2_req_addr;
-wire          litedramcore_bankmachine2_req_lock;
-reg           litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine2_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine2_refresh_req;
-reg           litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine2_cmd_ready = 1'd0;
-reg    [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0;
-wire    [2:0] litedramcore_bankmachine2_cmd_payload_ba;
-reg           litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine2_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine2_sink_valid;
-wire          litedramcore_bankmachine2_sink_ready;
-reg           litedramcore_bankmachine2_sink_first = 1'd0;
-reg           litedramcore_bankmachine2_sink_last = 1'd0;
-wire          litedramcore_bankmachine2_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine2_sink_payload_addr;
-wire          litedramcore_bankmachine2_source_valid;
-wire          litedramcore_bankmachine2_source_ready;
-wire          litedramcore_bankmachine2_source_first;
-wire          litedramcore_bankmachine2_source_last;
-wire          litedramcore_bankmachine2_source_payload_we;
-wire   [21:0] litedramcore_bankmachine2_source_payload_addr;
-wire          litedramcore_bankmachine2_syncfifo2_we;
-wire          litedramcore_bankmachine2_syncfifo2_writable;
-wire          litedramcore_bankmachine2_syncfifo2_re;
-wire          litedramcore_bankmachine2_syncfifo2_readable;
-wire   [24:0] litedramcore_bankmachine2_syncfifo2_din;
-wire   [24:0] litedramcore_bankmachine2_syncfifo2_dout;
-reg     [4:0] litedramcore_bankmachine2_level = 5'd0;
-reg           litedramcore_bankmachine2_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine2_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine2_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0;
-wire   [24:0] litedramcore_bankmachine2_wrport_dat_r;
-wire          litedramcore_bankmachine2_wrport_we;
-wire   [24:0] litedramcore_bankmachine2_wrport_dat_w;
-wire          litedramcore_bankmachine2_do_read;
-wire    [3:0] litedramcore_bankmachine2_rdport_adr;
-wire   [24:0] litedramcore_bankmachine2_rdport_dat_r;
-wire          litedramcore_bankmachine2_fifo_in_payload_we;
-wire   [21:0] litedramcore_bankmachine2_fifo_in_payload_addr;
-wire          litedramcore_bankmachine2_fifo_in_first;
-wire          litedramcore_bankmachine2_fifo_in_last;
-wire          litedramcore_bankmachine2_fifo_out_payload_we;
-wire   [21:0] litedramcore_bankmachine2_fifo_out_payload_addr;
-wire          litedramcore_bankmachine2_fifo_out_first;
-wire          litedramcore_bankmachine2_fifo_out_last;
-wire          litedramcore_bankmachine2_sink_sink_valid;
-wire          litedramcore_bankmachine2_sink_sink_ready;
-wire          litedramcore_bankmachine2_sink_sink_first;
-wire          litedramcore_bankmachine2_sink_sink_last;
-wire          litedramcore_bankmachine2_sink_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine2_sink_sink_payload_addr;
-wire          litedramcore_bankmachine2_source_source_valid;
-wire          litedramcore_bankmachine2_source_source_ready;
-wire          litedramcore_bankmachine2_source_source_first;
-wire          litedramcore_bankmachine2_source_source_last;
-wire          litedramcore_bankmachine2_source_source_payload_we;
-wire   [21:0] litedramcore_bankmachine2_source_source_payload_addr;
-wire          litedramcore_bankmachine2_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine2_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine2_pipe_valid_sink_first;
-wire          litedramcore_bankmachine2_pipe_valid_sink_last;
-wire          litedramcore_bankmachine2_pipe_valid_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine2_pipe_valid_source_ready;
-reg           litedramcore_bankmachine2_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine2_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0;
-reg    [21:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 22'd0;
-reg    [14:0] litedramcore_bankmachine2_row = 15'd0;
-reg           litedramcore_bankmachine2_row_opened = 1'd0;
-wire          litedramcore_bankmachine2_row_hit;
-reg           litedramcore_bankmachine2_row_open = 1'd0;
-reg           litedramcore_bankmachine2_row_close = 1'd0;
-reg           litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine2_twtpcon_valid;
+reg           main_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine1_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine1_wrport_adr = 4'd0;
+wire   [24:0] main_litedramcore_bankmachine1_wrport_dat_r;
+wire   [24:0] main_litedramcore_bankmachine1_wrport_dat_w;
+wire          main_litedramcore_bankmachine1_wrport_we;
+reg           main_litedramcore_bankmachine2_auto_precharge = 1'd0;
+reg    [14:0] main_litedramcore_bankmachine2_cmd_payload_a = 15'd0;
+wire    [2:0] main_litedramcore_bankmachine2_cmd_payload_ba;
+reg           main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine2_consume = 4'd0;
+wire          main_litedramcore_bankmachine2_do_read;
+wire          main_litedramcore_bankmachine2_fifo_in_first;
+wire          main_litedramcore_bankmachine2_fifo_in_last;
+wire   [21:0] main_litedramcore_bankmachine2_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine2_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine2_fifo_out_first;
+wire          main_litedramcore_bankmachine2_fifo_out_last;
+wire   [21:0] main_litedramcore_bankmachine2_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine2_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine2_level = 5'd0;
+wire          main_litedramcore_bankmachine2_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine2_pipe_valid_sink_last;
+wire   [21:0] main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine2_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine2_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine2_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine2_pipe_valid_source_last = 1'd0;
+reg    [21:0] main_litedramcore_bankmachine2_pipe_valid_source_payload_addr = 22'd0;
+reg           main_litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine2_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine2_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine2_rdport_adr;
+wire   [24:0] main_litedramcore_bankmachine2_rdport_dat_r;
+reg           main_litedramcore_bankmachine2_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine2_refresh_req;
+reg           main_litedramcore_bankmachine2_replace = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine2_req_addr;
+wire          main_litedramcore_bankmachine2_req_lock;
+reg           main_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine2_req_ready;
+wire          main_litedramcore_bankmachine2_req_valid;
+reg           main_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine2_req_we;
+reg    [14:0] main_litedramcore_bankmachine2_row = 15'd0;
+reg           main_litedramcore_bankmachine2_row_close = 1'd0;
+reg           main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine2_row_hit;
+reg           main_litedramcore_bankmachine2_row_open = 1'd0;
+reg           main_litedramcore_bankmachine2_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine2_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine2_sink_last = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine2_sink_payload_addr;
+wire          main_litedramcore_bankmachine2_sink_payload_we;
+wire          main_litedramcore_bankmachine2_sink_ready;
+wire          main_litedramcore_bankmachine2_sink_sink_first;
+wire          main_litedramcore_bankmachine2_sink_sink_last;
+wire   [21:0] main_litedramcore_bankmachine2_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine2_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine2_sink_sink_ready;
+wire          main_litedramcore_bankmachine2_sink_sink_valid;
+wire          main_litedramcore_bankmachine2_sink_valid;
+wire          main_litedramcore_bankmachine2_source_first;
+wire          main_litedramcore_bankmachine2_source_last;
+wire   [21:0] main_litedramcore_bankmachine2_source_payload_addr;
+wire          main_litedramcore_bankmachine2_source_payload_we;
+wire          main_litedramcore_bankmachine2_source_ready;
+wire          main_litedramcore_bankmachine2_source_source_first;
+wire          main_litedramcore_bankmachine2_source_source_last;
+wire   [21:0] main_litedramcore_bankmachine2_source_source_payload_addr;
+wire          main_litedramcore_bankmachine2_source_source_payload_we;
+wire          main_litedramcore_bankmachine2_source_source_ready;
+wire          main_litedramcore_bankmachine2_source_source_valid;
+wire          main_litedramcore_bankmachine2_source_valid;
+wire   [24:0] main_litedramcore_bankmachine2_syncfifo2_din;
+wire   [24:0] main_litedramcore_bankmachine2_syncfifo2_dout;
+wire          main_litedramcore_bankmachine2_syncfifo2_re;
+wire          main_litedramcore_bankmachine2_syncfifo2_readable;
+wire          main_litedramcore_bankmachine2_syncfifo2_we;
+wire          main_litedramcore_bankmachine2_syncfifo2_writable;
+reg     [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine2_trccon_valid;
+reg           main_litedramcore_bankmachine2_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine2_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
-wire          litedramcore_bankmachine2_trascon_valid;
+reg           main_litedramcore_bankmachine2_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine2_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine2_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
-wire          litedramcore_bankmachine3_req_valid;
-wire          litedramcore_bankmachine3_req_ready;
-wire          litedramcore_bankmachine3_req_we;
-wire   [21:0] litedramcore_bankmachine3_req_addr;
-wire          litedramcore_bankmachine3_req_lock;
-reg           litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine3_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine3_refresh_req;
-reg           litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine3_cmd_ready = 1'd0;
-reg    [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0;
-wire    [2:0] litedramcore_bankmachine3_cmd_payload_ba;
-reg           litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine3_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine3_sink_valid;
-wire          litedramcore_bankmachine3_sink_ready;
-reg           litedramcore_bankmachine3_sink_first = 1'd0;
-reg           litedramcore_bankmachine3_sink_last = 1'd0;
-wire          litedramcore_bankmachine3_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine3_sink_payload_addr;
-wire          litedramcore_bankmachine3_source_valid;
-wire          litedramcore_bankmachine3_source_ready;
-wire          litedramcore_bankmachine3_source_first;
-wire          litedramcore_bankmachine3_source_last;
-wire          litedramcore_bankmachine3_source_payload_we;
-wire   [21:0] litedramcore_bankmachine3_source_payload_addr;
-wire          litedramcore_bankmachine3_syncfifo3_we;
-wire          litedramcore_bankmachine3_syncfifo3_writable;
-wire          litedramcore_bankmachine3_syncfifo3_re;
-wire          litedramcore_bankmachine3_syncfifo3_readable;
-wire   [24:0] litedramcore_bankmachine3_syncfifo3_din;
-wire   [24:0] litedramcore_bankmachine3_syncfifo3_dout;
-reg     [4:0] litedramcore_bankmachine3_level = 5'd0;
-reg           litedramcore_bankmachine3_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine3_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine3_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0;
-wire   [24:0] litedramcore_bankmachine3_wrport_dat_r;
-wire          litedramcore_bankmachine3_wrport_we;
-wire   [24:0] litedramcore_bankmachine3_wrport_dat_w;
-wire          litedramcore_bankmachine3_do_read;
-wire    [3:0] litedramcore_bankmachine3_rdport_adr;
-wire   [24:0] litedramcore_bankmachine3_rdport_dat_r;
-wire          litedramcore_bankmachine3_fifo_in_payload_we;
-wire   [21:0] litedramcore_bankmachine3_fifo_in_payload_addr;
-wire          litedramcore_bankmachine3_fifo_in_first;
-wire          litedramcore_bankmachine3_fifo_in_last;
-wire          litedramcore_bankmachine3_fifo_out_payload_we;
-wire   [21:0] litedramcore_bankmachine3_fifo_out_payload_addr;
-wire          litedramcore_bankmachine3_fifo_out_first;
-wire          litedramcore_bankmachine3_fifo_out_last;
-wire          litedramcore_bankmachine3_sink_sink_valid;
-wire          litedramcore_bankmachine3_sink_sink_ready;
-wire          litedramcore_bankmachine3_sink_sink_first;
-wire          litedramcore_bankmachine3_sink_sink_last;
-wire          litedramcore_bankmachine3_sink_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine3_sink_sink_payload_addr;
-wire          litedramcore_bankmachine3_source_source_valid;
-wire          litedramcore_bankmachine3_source_source_ready;
-wire          litedramcore_bankmachine3_source_source_first;
-wire          litedramcore_bankmachine3_source_source_last;
-wire          litedramcore_bankmachine3_source_source_payload_we;
-wire   [21:0] litedramcore_bankmachine3_source_source_payload_addr;
-wire          litedramcore_bankmachine3_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine3_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine3_pipe_valid_sink_first;
-wire          litedramcore_bankmachine3_pipe_valid_sink_last;
-wire          litedramcore_bankmachine3_pipe_valid_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine3_pipe_valid_source_ready;
-reg           litedramcore_bankmachine3_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine3_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0;
-reg    [21:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 22'd0;
-reg    [14:0] litedramcore_bankmachine3_row = 15'd0;
-reg           litedramcore_bankmachine3_row_opened = 1'd0;
-wire          litedramcore_bankmachine3_row_hit;
-reg           litedramcore_bankmachine3_row_open = 1'd0;
-reg           litedramcore_bankmachine3_row_close = 1'd0;
-reg           litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine3_twtpcon_valid;
+reg           main_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine2_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine2_wrport_adr = 4'd0;
+wire   [24:0] main_litedramcore_bankmachine2_wrport_dat_r;
+wire   [24:0] main_litedramcore_bankmachine2_wrport_dat_w;
+wire          main_litedramcore_bankmachine2_wrport_we;
+reg           main_litedramcore_bankmachine3_auto_precharge = 1'd0;
+reg    [14:0] main_litedramcore_bankmachine3_cmd_payload_a = 15'd0;
+wire    [2:0] main_litedramcore_bankmachine3_cmd_payload_ba;
+reg           main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine3_consume = 4'd0;
+wire          main_litedramcore_bankmachine3_do_read;
+wire          main_litedramcore_bankmachine3_fifo_in_first;
+wire          main_litedramcore_bankmachine3_fifo_in_last;
+wire   [21:0] main_litedramcore_bankmachine3_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine3_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine3_fifo_out_first;
+wire          main_litedramcore_bankmachine3_fifo_out_last;
+wire   [21:0] main_litedramcore_bankmachine3_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine3_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine3_level = 5'd0;
+wire          main_litedramcore_bankmachine3_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine3_pipe_valid_sink_last;
+wire   [21:0] main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine3_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine3_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine3_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine3_pipe_valid_source_last = 1'd0;
+reg    [21:0] main_litedramcore_bankmachine3_pipe_valid_source_payload_addr = 22'd0;
+reg           main_litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine3_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine3_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine3_rdport_adr;
+wire   [24:0] main_litedramcore_bankmachine3_rdport_dat_r;
+reg           main_litedramcore_bankmachine3_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine3_refresh_req;
+reg           main_litedramcore_bankmachine3_replace = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine3_req_addr;
+wire          main_litedramcore_bankmachine3_req_lock;
+reg           main_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine3_req_ready;
+wire          main_litedramcore_bankmachine3_req_valid;
+reg           main_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine3_req_we;
+reg    [14:0] main_litedramcore_bankmachine3_row = 15'd0;
+reg           main_litedramcore_bankmachine3_row_close = 1'd0;
+reg           main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine3_row_hit;
+reg           main_litedramcore_bankmachine3_row_open = 1'd0;
+reg           main_litedramcore_bankmachine3_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine3_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine3_sink_last = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine3_sink_payload_addr;
+wire          main_litedramcore_bankmachine3_sink_payload_we;
+wire          main_litedramcore_bankmachine3_sink_ready;
+wire          main_litedramcore_bankmachine3_sink_sink_first;
+wire          main_litedramcore_bankmachine3_sink_sink_last;
+wire   [21:0] main_litedramcore_bankmachine3_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine3_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine3_sink_sink_ready;
+wire          main_litedramcore_bankmachine3_sink_sink_valid;
+wire          main_litedramcore_bankmachine3_sink_valid;
+wire          main_litedramcore_bankmachine3_source_first;
+wire          main_litedramcore_bankmachine3_source_last;
+wire   [21:0] main_litedramcore_bankmachine3_source_payload_addr;
+wire          main_litedramcore_bankmachine3_source_payload_we;
+wire          main_litedramcore_bankmachine3_source_ready;
+wire          main_litedramcore_bankmachine3_source_source_first;
+wire          main_litedramcore_bankmachine3_source_source_last;
+wire   [21:0] main_litedramcore_bankmachine3_source_source_payload_addr;
+wire          main_litedramcore_bankmachine3_source_source_payload_we;
+wire          main_litedramcore_bankmachine3_source_source_ready;
+wire          main_litedramcore_bankmachine3_source_source_valid;
+wire          main_litedramcore_bankmachine3_source_valid;
+wire   [24:0] main_litedramcore_bankmachine3_syncfifo3_din;
+wire   [24:0] main_litedramcore_bankmachine3_syncfifo3_dout;
+wire          main_litedramcore_bankmachine3_syncfifo3_re;
+wire          main_litedramcore_bankmachine3_syncfifo3_readable;
+wire          main_litedramcore_bankmachine3_syncfifo3_we;
+wire          main_litedramcore_bankmachine3_syncfifo3_writable;
+reg     [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine3_trccon_valid;
+reg           main_litedramcore_bankmachine3_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine3_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
-wire          litedramcore_bankmachine3_trascon_valid;
+reg           main_litedramcore_bankmachine3_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine3_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine3_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
-wire          litedramcore_bankmachine4_req_valid;
-wire          litedramcore_bankmachine4_req_ready;
-wire          litedramcore_bankmachine4_req_we;
-wire   [21:0] litedramcore_bankmachine4_req_addr;
-wire          litedramcore_bankmachine4_req_lock;
-reg           litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine4_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine4_refresh_req;
-reg           litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine4_cmd_ready = 1'd0;
-reg    [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0;
-wire    [2:0] litedramcore_bankmachine4_cmd_payload_ba;
-reg           litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine4_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine4_sink_valid;
-wire          litedramcore_bankmachine4_sink_ready;
-reg           litedramcore_bankmachine4_sink_first = 1'd0;
-reg           litedramcore_bankmachine4_sink_last = 1'd0;
-wire          litedramcore_bankmachine4_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine4_sink_payload_addr;
-wire          litedramcore_bankmachine4_source_valid;
-wire          litedramcore_bankmachine4_source_ready;
-wire          litedramcore_bankmachine4_source_first;
-wire          litedramcore_bankmachine4_source_last;
-wire          litedramcore_bankmachine4_source_payload_we;
-wire   [21:0] litedramcore_bankmachine4_source_payload_addr;
-wire          litedramcore_bankmachine4_syncfifo4_we;
-wire          litedramcore_bankmachine4_syncfifo4_writable;
-wire          litedramcore_bankmachine4_syncfifo4_re;
-wire          litedramcore_bankmachine4_syncfifo4_readable;
-wire   [24:0] litedramcore_bankmachine4_syncfifo4_din;
-wire   [24:0] litedramcore_bankmachine4_syncfifo4_dout;
-reg     [4:0] litedramcore_bankmachine4_level = 5'd0;
-reg           litedramcore_bankmachine4_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine4_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine4_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0;
-wire   [24:0] litedramcore_bankmachine4_wrport_dat_r;
-wire          litedramcore_bankmachine4_wrport_we;
-wire   [24:0] litedramcore_bankmachine4_wrport_dat_w;
-wire          litedramcore_bankmachine4_do_read;
-wire    [3:0] litedramcore_bankmachine4_rdport_adr;
-wire   [24:0] litedramcore_bankmachine4_rdport_dat_r;
-wire          litedramcore_bankmachine4_fifo_in_payload_we;
-wire   [21:0] litedramcore_bankmachine4_fifo_in_payload_addr;
-wire          litedramcore_bankmachine4_fifo_in_first;
-wire          litedramcore_bankmachine4_fifo_in_last;
-wire          litedramcore_bankmachine4_fifo_out_payload_we;
-wire   [21:0] litedramcore_bankmachine4_fifo_out_payload_addr;
-wire          litedramcore_bankmachine4_fifo_out_first;
-wire          litedramcore_bankmachine4_fifo_out_last;
-wire          litedramcore_bankmachine4_sink_sink_valid;
-wire          litedramcore_bankmachine4_sink_sink_ready;
-wire          litedramcore_bankmachine4_sink_sink_first;
-wire          litedramcore_bankmachine4_sink_sink_last;
-wire          litedramcore_bankmachine4_sink_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine4_sink_sink_payload_addr;
-wire          litedramcore_bankmachine4_source_source_valid;
-wire          litedramcore_bankmachine4_source_source_ready;
-wire          litedramcore_bankmachine4_source_source_first;
-wire          litedramcore_bankmachine4_source_source_last;
-wire          litedramcore_bankmachine4_source_source_payload_we;
-wire   [21:0] litedramcore_bankmachine4_source_source_payload_addr;
-wire          litedramcore_bankmachine4_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine4_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine4_pipe_valid_sink_first;
-wire          litedramcore_bankmachine4_pipe_valid_sink_last;
-wire          litedramcore_bankmachine4_pipe_valid_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine4_pipe_valid_source_ready;
-reg           litedramcore_bankmachine4_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine4_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0;
-reg    [21:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 22'd0;
-reg    [14:0] litedramcore_bankmachine4_row = 15'd0;
-reg           litedramcore_bankmachine4_row_opened = 1'd0;
-wire          litedramcore_bankmachine4_row_hit;
-reg           litedramcore_bankmachine4_row_open = 1'd0;
-reg           litedramcore_bankmachine4_row_close = 1'd0;
-reg           litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine4_twtpcon_valid;
+reg           main_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine3_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine3_wrport_adr = 4'd0;
+wire   [24:0] main_litedramcore_bankmachine3_wrport_dat_r;
+wire   [24:0] main_litedramcore_bankmachine3_wrport_dat_w;
+wire          main_litedramcore_bankmachine3_wrport_we;
+reg           main_litedramcore_bankmachine4_auto_precharge = 1'd0;
+reg    [14:0] main_litedramcore_bankmachine4_cmd_payload_a = 15'd0;
+wire    [2:0] main_litedramcore_bankmachine4_cmd_payload_ba;
+reg           main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine4_consume = 4'd0;
+wire          main_litedramcore_bankmachine4_do_read;
+wire          main_litedramcore_bankmachine4_fifo_in_first;
+wire          main_litedramcore_bankmachine4_fifo_in_last;
+wire   [21:0] main_litedramcore_bankmachine4_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine4_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine4_fifo_out_first;
+wire          main_litedramcore_bankmachine4_fifo_out_last;
+wire   [21:0] main_litedramcore_bankmachine4_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine4_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine4_level = 5'd0;
+wire          main_litedramcore_bankmachine4_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine4_pipe_valid_sink_last;
+wire   [21:0] main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine4_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine4_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine4_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine4_pipe_valid_source_last = 1'd0;
+reg    [21:0] main_litedramcore_bankmachine4_pipe_valid_source_payload_addr = 22'd0;
+reg           main_litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine4_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine4_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine4_rdport_adr;
+wire   [24:0] main_litedramcore_bankmachine4_rdport_dat_r;
+reg           main_litedramcore_bankmachine4_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine4_refresh_req;
+reg           main_litedramcore_bankmachine4_replace = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine4_req_addr;
+wire          main_litedramcore_bankmachine4_req_lock;
+reg           main_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine4_req_ready;
+wire          main_litedramcore_bankmachine4_req_valid;
+reg           main_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine4_req_we;
+reg    [14:0] main_litedramcore_bankmachine4_row = 15'd0;
+reg           main_litedramcore_bankmachine4_row_close = 1'd0;
+reg           main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine4_row_hit;
+reg           main_litedramcore_bankmachine4_row_open = 1'd0;
+reg           main_litedramcore_bankmachine4_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine4_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine4_sink_last = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine4_sink_payload_addr;
+wire          main_litedramcore_bankmachine4_sink_payload_we;
+wire          main_litedramcore_bankmachine4_sink_ready;
+wire          main_litedramcore_bankmachine4_sink_sink_first;
+wire          main_litedramcore_bankmachine4_sink_sink_last;
+wire   [21:0] main_litedramcore_bankmachine4_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine4_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine4_sink_sink_ready;
+wire          main_litedramcore_bankmachine4_sink_sink_valid;
+wire          main_litedramcore_bankmachine4_sink_valid;
+wire          main_litedramcore_bankmachine4_source_first;
+wire          main_litedramcore_bankmachine4_source_last;
+wire   [21:0] main_litedramcore_bankmachine4_source_payload_addr;
+wire          main_litedramcore_bankmachine4_source_payload_we;
+wire          main_litedramcore_bankmachine4_source_ready;
+wire          main_litedramcore_bankmachine4_source_source_first;
+wire          main_litedramcore_bankmachine4_source_source_last;
+wire   [21:0] main_litedramcore_bankmachine4_source_source_payload_addr;
+wire          main_litedramcore_bankmachine4_source_source_payload_we;
+wire          main_litedramcore_bankmachine4_source_source_ready;
+wire          main_litedramcore_bankmachine4_source_source_valid;
+wire          main_litedramcore_bankmachine4_source_valid;
+wire   [24:0] main_litedramcore_bankmachine4_syncfifo4_din;
+wire   [24:0] main_litedramcore_bankmachine4_syncfifo4_dout;
+wire          main_litedramcore_bankmachine4_syncfifo4_re;
+wire          main_litedramcore_bankmachine4_syncfifo4_readable;
+wire          main_litedramcore_bankmachine4_syncfifo4_we;
+wire          main_litedramcore_bankmachine4_syncfifo4_writable;
+reg     [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine4_trccon_valid;
+reg           main_litedramcore_bankmachine4_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine4_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
-wire          litedramcore_bankmachine4_trascon_valid;
+reg           main_litedramcore_bankmachine4_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine4_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine4_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
-wire          litedramcore_bankmachine5_req_valid;
-wire          litedramcore_bankmachine5_req_ready;
-wire          litedramcore_bankmachine5_req_we;
-wire   [21:0] litedramcore_bankmachine5_req_addr;
-wire          litedramcore_bankmachine5_req_lock;
-reg           litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine5_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine5_refresh_req;
-reg           litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine5_cmd_ready = 1'd0;
-reg    [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0;
-wire    [2:0] litedramcore_bankmachine5_cmd_payload_ba;
-reg           litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine5_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine5_sink_valid;
-wire          litedramcore_bankmachine5_sink_ready;
-reg           litedramcore_bankmachine5_sink_first = 1'd0;
-reg           litedramcore_bankmachine5_sink_last = 1'd0;
-wire          litedramcore_bankmachine5_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine5_sink_payload_addr;
-wire          litedramcore_bankmachine5_source_valid;
-wire          litedramcore_bankmachine5_source_ready;
-wire          litedramcore_bankmachine5_source_first;
-wire          litedramcore_bankmachine5_source_last;
-wire          litedramcore_bankmachine5_source_payload_we;
-wire   [21:0] litedramcore_bankmachine5_source_payload_addr;
-wire          litedramcore_bankmachine5_syncfifo5_we;
-wire          litedramcore_bankmachine5_syncfifo5_writable;
-wire          litedramcore_bankmachine5_syncfifo5_re;
-wire          litedramcore_bankmachine5_syncfifo5_readable;
-wire   [24:0] litedramcore_bankmachine5_syncfifo5_din;
-wire   [24:0] litedramcore_bankmachine5_syncfifo5_dout;
-reg     [4:0] litedramcore_bankmachine5_level = 5'd0;
-reg           litedramcore_bankmachine5_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine5_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine5_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0;
-wire   [24:0] litedramcore_bankmachine5_wrport_dat_r;
-wire          litedramcore_bankmachine5_wrport_we;
-wire   [24:0] litedramcore_bankmachine5_wrport_dat_w;
-wire          litedramcore_bankmachine5_do_read;
-wire    [3:0] litedramcore_bankmachine5_rdport_adr;
-wire   [24:0] litedramcore_bankmachine5_rdport_dat_r;
-wire          litedramcore_bankmachine5_fifo_in_payload_we;
-wire   [21:0] litedramcore_bankmachine5_fifo_in_payload_addr;
-wire          litedramcore_bankmachine5_fifo_in_first;
-wire          litedramcore_bankmachine5_fifo_in_last;
-wire          litedramcore_bankmachine5_fifo_out_payload_we;
-wire   [21:0] litedramcore_bankmachine5_fifo_out_payload_addr;
-wire          litedramcore_bankmachine5_fifo_out_first;
-wire          litedramcore_bankmachine5_fifo_out_last;
-wire          litedramcore_bankmachine5_sink_sink_valid;
-wire          litedramcore_bankmachine5_sink_sink_ready;
-wire          litedramcore_bankmachine5_sink_sink_first;
-wire          litedramcore_bankmachine5_sink_sink_last;
-wire          litedramcore_bankmachine5_sink_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine5_sink_sink_payload_addr;
-wire          litedramcore_bankmachine5_source_source_valid;
-wire          litedramcore_bankmachine5_source_source_ready;
-wire          litedramcore_bankmachine5_source_source_first;
-wire          litedramcore_bankmachine5_source_source_last;
-wire          litedramcore_bankmachine5_source_source_payload_we;
-wire   [21:0] litedramcore_bankmachine5_source_source_payload_addr;
-wire          litedramcore_bankmachine5_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine5_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine5_pipe_valid_sink_first;
-wire          litedramcore_bankmachine5_pipe_valid_sink_last;
-wire          litedramcore_bankmachine5_pipe_valid_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine5_pipe_valid_source_ready;
-reg           litedramcore_bankmachine5_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine5_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0;
-reg    [21:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 22'd0;
-reg    [14:0] litedramcore_bankmachine5_row = 15'd0;
-reg           litedramcore_bankmachine5_row_opened = 1'd0;
-wire          litedramcore_bankmachine5_row_hit;
-reg           litedramcore_bankmachine5_row_open = 1'd0;
-reg           litedramcore_bankmachine5_row_close = 1'd0;
-reg           litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine5_twtpcon_valid;
+reg           main_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine4_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine4_wrport_adr = 4'd0;
+wire   [24:0] main_litedramcore_bankmachine4_wrport_dat_r;
+wire   [24:0] main_litedramcore_bankmachine4_wrport_dat_w;
+wire          main_litedramcore_bankmachine4_wrport_we;
+reg           main_litedramcore_bankmachine5_auto_precharge = 1'd0;
+reg    [14:0] main_litedramcore_bankmachine5_cmd_payload_a = 15'd0;
+wire    [2:0] main_litedramcore_bankmachine5_cmd_payload_ba;
+reg           main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine5_consume = 4'd0;
+wire          main_litedramcore_bankmachine5_do_read;
+wire          main_litedramcore_bankmachine5_fifo_in_first;
+wire          main_litedramcore_bankmachine5_fifo_in_last;
+wire   [21:0] main_litedramcore_bankmachine5_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine5_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine5_fifo_out_first;
+wire          main_litedramcore_bankmachine5_fifo_out_last;
+wire   [21:0] main_litedramcore_bankmachine5_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine5_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine5_level = 5'd0;
+wire          main_litedramcore_bankmachine5_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine5_pipe_valid_sink_last;
+wire   [21:0] main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine5_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine5_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine5_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine5_pipe_valid_source_last = 1'd0;
+reg    [21:0] main_litedramcore_bankmachine5_pipe_valid_source_payload_addr = 22'd0;
+reg           main_litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine5_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine5_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine5_rdport_adr;
+wire   [24:0] main_litedramcore_bankmachine5_rdport_dat_r;
+reg           main_litedramcore_bankmachine5_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine5_refresh_req;
+reg           main_litedramcore_bankmachine5_replace = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine5_req_addr;
+wire          main_litedramcore_bankmachine5_req_lock;
+reg           main_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine5_req_ready;
+wire          main_litedramcore_bankmachine5_req_valid;
+reg           main_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine5_req_we;
+reg    [14:0] main_litedramcore_bankmachine5_row = 15'd0;
+reg           main_litedramcore_bankmachine5_row_close = 1'd0;
+reg           main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine5_row_hit;
+reg           main_litedramcore_bankmachine5_row_open = 1'd0;
+reg           main_litedramcore_bankmachine5_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine5_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine5_sink_last = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine5_sink_payload_addr;
+wire          main_litedramcore_bankmachine5_sink_payload_we;
+wire          main_litedramcore_bankmachine5_sink_ready;
+wire          main_litedramcore_bankmachine5_sink_sink_first;
+wire          main_litedramcore_bankmachine5_sink_sink_last;
+wire   [21:0] main_litedramcore_bankmachine5_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine5_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine5_sink_sink_ready;
+wire          main_litedramcore_bankmachine5_sink_sink_valid;
+wire          main_litedramcore_bankmachine5_sink_valid;
+wire          main_litedramcore_bankmachine5_source_first;
+wire          main_litedramcore_bankmachine5_source_last;
+wire   [21:0] main_litedramcore_bankmachine5_source_payload_addr;
+wire          main_litedramcore_bankmachine5_source_payload_we;
+wire          main_litedramcore_bankmachine5_source_ready;
+wire          main_litedramcore_bankmachine5_source_source_first;
+wire          main_litedramcore_bankmachine5_source_source_last;
+wire   [21:0] main_litedramcore_bankmachine5_source_source_payload_addr;
+wire          main_litedramcore_bankmachine5_source_source_payload_we;
+wire          main_litedramcore_bankmachine5_source_source_ready;
+wire          main_litedramcore_bankmachine5_source_source_valid;
+wire          main_litedramcore_bankmachine5_source_valid;
+wire   [24:0] main_litedramcore_bankmachine5_syncfifo5_din;
+wire   [24:0] main_litedramcore_bankmachine5_syncfifo5_dout;
+wire          main_litedramcore_bankmachine5_syncfifo5_re;
+wire          main_litedramcore_bankmachine5_syncfifo5_readable;
+wire          main_litedramcore_bankmachine5_syncfifo5_we;
+wire          main_litedramcore_bankmachine5_syncfifo5_writable;
+reg     [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine5_trccon_valid;
+reg           main_litedramcore_bankmachine5_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine5_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
-wire          litedramcore_bankmachine5_trascon_valid;
+reg           main_litedramcore_bankmachine5_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine5_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine5_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
-wire          litedramcore_bankmachine6_req_valid;
-wire          litedramcore_bankmachine6_req_ready;
-wire          litedramcore_bankmachine6_req_we;
-wire   [21:0] litedramcore_bankmachine6_req_addr;
-wire          litedramcore_bankmachine6_req_lock;
-reg           litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine6_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine6_refresh_req;
-reg           litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine6_cmd_ready = 1'd0;
-reg    [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0;
-wire    [2:0] litedramcore_bankmachine6_cmd_payload_ba;
-reg           litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine6_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine6_sink_valid;
-wire          litedramcore_bankmachine6_sink_ready;
-reg           litedramcore_bankmachine6_sink_first = 1'd0;
-reg           litedramcore_bankmachine6_sink_last = 1'd0;
-wire          litedramcore_bankmachine6_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine6_sink_payload_addr;
-wire          litedramcore_bankmachine6_source_valid;
-wire          litedramcore_bankmachine6_source_ready;
-wire          litedramcore_bankmachine6_source_first;
-wire          litedramcore_bankmachine6_source_last;
-wire          litedramcore_bankmachine6_source_payload_we;
-wire   [21:0] litedramcore_bankmachine6_source_payload_addr;
-wire          litedramcore_bankmachine6_syncfifo6_we;
-wire          litedramcore_bankmachine6_syncfifo6_writable;
-wire          litedramcore_bankmachine6_syncfifo6_re;
-wire          litedramcore_bankmachine6_syncfifo6_readable;
-wire   [24:0] litedramcore_bankmachine6_syncfifo6_din;
-wire   [24:0] litedramcore_bankmachine6_syncfifo6_dout;
-reg     [4:0] litedramcore_bankmachine6_level = 5'd0;
-reg           litedramcore_bankmachine6_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine6_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine6_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0;
-wire   [24:0] litedramcore_bankmachine6_wrport_dat_r;
-wire          litedramcore_bankmachine6_wrport_we;
-wire   [24:0] litedramcore_bankmachine6_wrport_dat_w;
-wire          litedramcore_bankmachine6_do_read;
-wire    [3:0] litedramcore_bankmachine6_rdport_adr;
-wire   [24:0] litedramcore_bankmachine6_rdport_dat_r;
-wire          litedramcore_bankmachine6_fifo_in_payload_we;
-wire   [21:0] litedramcore_bankmachine6_fifo_in_payload_addr;
-wire          litedramcore_bankmachine6_fifo_in_first;
-wire          litedramcore_bankmachine6_fifo_in_last;
-wire          litedramcore_bankmachine6_fifo_out_payload_we;
-wire   [21:0] litedramcore_bankmachine6_fifo_out_payload_addr;
-wire          litedramcore_bankmachine6_fifo_out_first;
-wire          litedramcore_bankmachine6_fifo_out_last;
-wire          litedramcore_bankmachine6_sink_sink_valid;
-wire          litedramcore_bankmachine6_sink_sink_ready;
-wire          litedramcore_bankmachine6_sink_sink_first;
-wire          litedramcore_bankmachine6_sink_sink_last;
-wire          litedramcore_bankmachine6_sink_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine6_sink_sink_payload_addr;
-wire          litedramcore_bankmachine6_source_source_valid;
-wire          litedramcore_bankmachine6_source_source_ready;
-wire          litedramcore_bankmachine6_source_source_first;
-wire          litedramcore_bankmachine6_source_source_last;
-wire          litedramcore_bankmachine6_source_source_payload_we;
-wire   [21:0] litedramcore_bankmachine6_source_source_payload_addr;
-wire          litedramcore_bankmachine6_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine6_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine6_pipe_valid_sink_first;
-wire          litedramcore_bankmachine6_pipe_valid_sink_last;
-wire          litedramcore_bankmachine6_pipe_valid_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine6_pipe_valid_source_ready;
-reg           litedramcore_bankmachine6_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine6_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0;
-reg    [21:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 22'd0;
-reg    [14:0] litedramcore_bankmachine6_row = 15'd0;
-reg           litedramcore_bankmachine6_row_opened = 1'd0;
-wire          litedramcore_bankmachine6_row_hit;
-reg           litedramcore_bankmachine6_row_open = 1'd0;
-reg           litedramcore_bankmachine6_row_close = 1'd0;
-reg           litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine6_twtpcon_valid;
+reg           main_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine5_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine5_wrport_adr = 4'd0;
+wire   [24:0] main_litedramcore_bankmachine5_wrport_dat_r;
+wire   [24:0] main_litedramcore_bankmachine5_wrport_dat_w;
+wire          main_litedramcore_bankmachine5_wrport_we;
+reg           main_litedramcore_bankmachine6_auto_precharge = 1'd0;
+reg    [14:0] main_litedramcore_bankmachine6_cmd_payload_a = 15'd0;
+wire    [2:0] main_litedramcore_bankmachine6_cmd_payload_ba;
+reg           main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine6_consume = 4'd0;
+wire          main_litedramcore_bankmachine6_do_read;
+wire          main_litedramcore_bankmachine6_fifo_in_first;
+wire          main_litedramcore_bankmachine6_fifo_in_last;
+wire   [21:0] main_litedramcore_bankmachine6_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine6_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine6_fifo_out_first;
+wire          main_litedramcore_bankmachine6_fifo_out_last;
+wire   [21:0] main_litedramcore_bankmachine6_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine6_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine6_level = 5'd0;
+wire          main_litedramcore_bankmachine6_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine6_pipe_valid_sink_last;
+wire   [21:0] main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine6_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine6_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine6_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine6_pipe_valid_source_last = 1'd0;
+reg    [21:0] main_litedramcore_bankmachine6_pipe_valid_source_payload_addr = 22'd0;
+reg           main_litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine6_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine6_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine6_rdport_adr;
+wire   [24:0] main_litedramcore_bankmachine6_rdport_dat_r;
+reg           main_litedramcore_bankmachine6_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine6_refresh_req;
+reg           main_litedramcore_bankmachine6_replace = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine6_req_addr;
+wire          main_litedramcore_bankmachine6_req_lock;
+reg           main_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine6_req_ready;
+wire          main_litedramcore_bankmachine6_req_valid;
+reg           main_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine6_req_we;
+reg    [14:0] main_litedramcore_bankmachine6_row = 15'd0;
+reg           main_litedramcore_bankmachine6_row_close = 1'd0;
+reg           main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine6_row_hit;
+reg           main_litedramcore_bankmachine6_row_open = 1'd0;
+reg           main_litedramcore_bankmachine6_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine6_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine6_sink_last = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine6_sink_payload_addr;
+wire          main_litedramcore_bankmachine6_sink_payload_we;
+wire          main_litedramcore_bankmachine6_sink_ready;
+wire          main_litedramcore_bankmachine6_sink_sink_first;
+wire          main_litedramcore_bankmachine6_sink_sink_last;
+wire   [21:0] main_litedramcore_bankmachine6_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine6_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine6_sink_sink_ready;
+wire          main_litedramcore_bankmachine6_sink_sink_valid;
+wire          main_litedramcore_bankmachine6_sink_valid;
+wire          main_litedramcore_bankmachine6_source_first;
+wire          main_litedramcore_bankmachine6_source_last;
+wire   [21:0] main_litedramcore_bankmachine6_source_payload_addr;
+wire          main_litedramcore_bankmachine6_source_payload_we;
+wire          main_litedramcore_bankmachine6_source_ready;
+wire          main_litedramcore_bankmachine6_source_source_first;
+wire          main_litedramcore_bankmachine6_source_source_last;
+wire   [21:0] main_litedramcore_bankmachine6_source_source_payload_addr;
+wire          main_litedramcore_bankmachine6_source_source_payload_we;
+wire          main_litedramcore_bankmachine6_source_source_ready;
+wire          main_litedramcore_bankmachine6_source_source_valid;
+wire          main_litedramcore_bankmachine6_source_valid;
+wire   [24:0] main_litedramcore_bankmachine6_syncfifo6_din;
+wire   [24:0] main_litedramcore_bankmachine6_syncfifo6_dout;
+wire          main_litedramcore_bankmachine6_syncfifo6_re;
+wire          main_litedramcore_bankmachine6_syncfifo6_readable;
+wire          main_litedramcore_bankmachine6_syncfifo6_we;
+wire          main_litedramcore_bankmachine6_syncfifo6_writable;
+reg     [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine6_trccon_valid;
+reg           main_litedramcore_bankmachine6_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine6_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
-wire          litedramcore_bankmachine6_trascon_valid;
+reg           main_litedramcore_bankmachine6_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine6_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine6_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
-wire          litedramcore_bankmachine7_req_valid;
-wire          litedramcore_bankmachine7_req_ready;
-wire          litedramcore_bankmachine7_req_we;
-wire   [21:0] litedramcore_bankmachine7_req_addr;
-wire          litedramcore_bankmachine7_req_lock;
-reg           litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine7_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine7_refresh_req;
-reg           litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine7_cmd_ready = 1'd0;
-reg    [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0;
-wire    [2:0] litedramcore_bankmachine7_cmd_payload_ba;
-reg           litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine7_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine7_sink_valid;
-wire          litedramcore_bankmachine7_sink_ready;
-reg           litedramcore_bankmachine7_sink_first = 1'd0;
-reg           litedramcore_bankmachine7_sink_last = 1'd0;
-wire          litedramcore_bankmachine7_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine7_sink_payload_addr;
-wire          litedramcore_bankmachine7_source_valid;
-wire          litedramcore_bankmachine7_source_ready;
-wire          litedramcore_bankmachine7_source_first;
-wire          litedramcore_bankmachine7_source_last;
-wire          litedramcore_bankmachine7_source_payload_we;
-wire   [21:0] litedramcore_bankmachine7_source_payload_addr;
-wire          litedramcore_bankmachine7_syncfifo7_we;
-wire          litedramcore_bankmachine7_syncfifo7_writable;
-wire          litedramcore_bankmachine7_syncfifo7_re;
-wire          litedramcore_bankmachine7_syncfifo7_readable;
-wire   [24:0] litedramcore_bankmachine7_syncfifo7_din;
-wire   [24:0] litedramcore_bankmachine7_syncfifo7_dout;
-reg     [4:0] litedramcore_bankmachine7_level = 5'd0;
-reg           litedramcore_bankmachine7_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine7_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine7_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0;
-wire   [24:0] litedramcore_bankmachine7_wrport_dat_r;
-wire          litedramcore_bankmachine7_wrport_we;
-wire   [24:0] litedramcore_bankmachine7_wrport_dat_w;
-wire          litedramcore_bankmachine7_do_read;
-wire    [3:0] litedramcore_bankmachine7_rdport_adr;
-wire   [24:0] litedramcore_bankmachine7_rdport_dat_r;
-wire          litedramcore_bankmachine7_fifo_in_payload_we;
-wire   [21:0] litedramcore_bankmachine7_fifo_in_payload_addr;
-wire          litedramcore_bankmachine7_fifo_in_first;
-wire          litedramcore_bankmachine7_fifo_in_last;
-wire          litedramcore_bankmachine7_fifo_out_payload_we;
-wire   [21:0] litedramcore_bankmachine7_fifo_out_payload_addr;
-wire          litedramcore_bankmachine7_fifo_out_first;
-wire          litedramcore_bankmachine7_fifo_out_last;
-wire          litedramcore_bankmachine7_sink_sink_valid;
-wire          litedramcore_bankmachine7_sink_sink_ready;
-wire          litedramcore_bankmachine7_sink_sink_first;
-wire          litedramcore_bankmachine7_sink_sink_last;
-wire          litedramcore_bankmachine7_sink_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine7_sink_sink_payload_addr;
-wire          litedramcore_bankmachine7_source_source_valid;
-wire          litedramcore_bankmachine7_source_source_ready;
-wire          litedramcore_bankmachine7_source_source_first;
-wire          litedramcore_bankmachine7_source_source_last;
-wire          litedramcore_bankmachine7_source_source_payload_we;
-wire   [21:0] litedramcore_bankmachine7_source_source_payload_addr;
-wire          litedramcore_bankmachine7_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine7_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine7_pipe_valid_sink_first;
-wire          litedramcore_bankmachine7_pipe_valid_sink_last;
-wire          litedramcore_bankmachine7_pipe_valid_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine7_pipe_valid_source_ready;
-reg           litedramcore_bankmachine7_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine7_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0;
-reg    [21:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 22'd0;
-reg    [14:0] litedramcore_bankmachine7_row = 15'd0;
-reg           litedramcore_bankmachine7_row_opened = 1'd0;
-wire          litedramcore_bankmachine7_row_hit;
-reg           litedramcore_bankmachine7_row_open = 1'd0;
-reg           litedramcore_bankmachine7_row_close = 1'd0;
-reg           litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine7_twtpcon_valid;
+reg           main_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine6_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine6_wrport_adr = 4'd0;
+wire   [24:0] main_litedramcore_bankmachine6_wrport_dat_r;
+wire   [24:0] main_litedramcore_bankmachine6_wrport_dat_w;
+wire          main_litedramcore_bankmachine6_wrport_we;
+reg           main_litedramcore_bankmachine7_auto_precharge = 1'd0;
+reg    [14:0] main_litedramcore_bankmachine7_cmd_payload_a = 15'd0;
+wire    [2:0] main_litedramcore_bankmachine7_cmd_payload_ba;
+reg           main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine7_consume = 4'd0;
+wire          main_litedramcore_bankmachine7_do_read;
+wire          main_litedramcore_bankmachine7_fifo_in_first;
+wire          main_litedramcore_bankmachine7_fifo_in_last;
+wire   [21:0] main_litedramcore_bankmachine7_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine7_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine7_fifo_out_first;
+wire          main_litedramcore_bankmachine7_fifo_out_last;
+wire   [21:0] main_litedramcore_bankmachine7_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine7_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine7_level = 5'd0;
+wire          main_litedramcore_bankmachine7_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine7_pipe_valid_sink_last;
+wire   [21:0] main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine7_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine7_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine7_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine7_pipe_valid_source_last = 1'd0;
+reg    [21:0] main_litedramcore_bankmachine7_pipe_valid_source_payload_addr = 22'd0;
+reg           main_litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine7_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine7_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine7_rdport_adr;
+wire   [24:0] main_litedramcore_bankmachine7_rdport_dat_r;
+reg           main_litedramcore_bankmachine7_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine7_refresh_req;
+reg           main_litedramcore_bankmachine7_replace = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine7_req_addr;
+wire          main_litedramcore_bankmachine7_req_lock;
+reg           main_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine7_req_ready;
+wire          main_litedramcore_bankmachine7_req_valid;
+reg           main_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine7_req_we;
+reg    [14:0] main_litedramcore_bankmachine7_row = 15'd0;
+reg           main_litedramcore_bankmachine7_row_close = 1'd0;
+reg           main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine7_row_hit;
+reg           main_litedramcore_bankmachine7_row_open = 1'd0;
+reg           main_litedramcore_bankmachine7_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine7_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine7_sink_last = 1'd0;
+wire   [21:0] main_litedramcore_bankmachine7_sink_payload_addr;
+wire          main_litedramcore_bankmachine7_sink_payload_we;
+wire          main_litedramcore_bankmachine7_sink_ready;
+wire          main_litedramcore_bankmachine7_sink_sink_first;
+wire          main_litedramcore_bankmachine7_sink_sink_last;
+wire   [21:0] main_litedramcore_bankmachine7_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine7_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine7_sink_sink_ready;
+wire          main_litedramcore_bankmachine7_sink_sink_valid;
+wire          main_litedramcore_bankmachine7_sink_valid;
+wire          main_litedramcore_bankmachine7_source_first;
+wire          main_litedramcore_bankmachine7_source_last;
+wire   [21:0] main_litedramcore_bankmachine7_source_payload_addr;
+wire          main_litedramcore_bankmachine7_source_payload_we;
+wire          main_litedramcore_bankmachine7_source_ready;
+wire          main_litedramcore_bankmachine7_source_source_first;
+wire          main_litedramcore_bankmachine7_source_source_last;
+wire   [21:0] main_litedramcore_bankmachine7_source_source_payload_addr;
+wire          main_litedramcore_bankmachine7_source_source_payload_we;
+wire          main_litedramcore_bankmachine7_source_source_ready;
+wire          main_litedramcore_bankmachine7_source_source_valid;
+wire          main_litedramcore_bankmachine7_source_valid;
+wire   [24:0] main_litedramcore_bankmachine7_syncfifo7_din;
+wire   [24:0] main_litedramcore_bankmachine7_syncfifo7_dout;
+wire          main_litedramcore_bankmachine7_syncfifo7_re;
+wire          main_litedramcore_bankmachine7_syncfifo7_readable;
+wire          main_litedramcore_bankmachine7_syncfifo7_we;
+wire          main_litedramcore_bankmachine7_syncfifo7_writable;
+reg     [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine7_trccon_valid;
+reg           main_litedramcore_bankmachine7_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine7_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
-wire          litedramcore_bankmachine7_trascon_valid;
+reg           main_litedramcore_bankmachine7_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine7_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine7_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
-wire          litedramcore_ras_allowed;
-wire          litedramcore_cas_allowed;
-wire    [1:0] litedramcore_rdcmdphase;
-wire    [1:0] litedramcore_wrcmdphase;
-reg           litedramcore_choose_cmd_want_reads = 1'd0;
-reg           litedramcore_choose_cmd_want_writes = 1'd0;
-reg           litedramcore_choose_cmd_want_cmds = 1'd0;
-reg           litedramcore_choose_cmd_want_activates = 1'd0;
-wire          litedramcore_choose_cmd_cmd_valid;
-reg           litedramcore_choose_cmd_cmd_ready = 1'd0;
-wire   [14:0] litedramcore_choose_cmd_cmd_payload_a;
-wire    [2:0] litedramcore_choose_cmd_cmd_payload_ba;
-reg           litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg           litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg           litedramcore_choose_cmd_cmd_payload_we = 1'd0;
-wire          litedramcore_choose_cmd_cmd_payload_is_cmd;
-wire          litedramcore_choose_cmd_cmd_payload_is_read;
-wire          litedramcore_choose_cmd_cmd_payload_is_write;
-reg     [7:0] litedramcore_choose_cmd_valids = 8'd0;
-wire    [7:0] litedramcore_choose_cmd_request;
-reg     [2:0] litedramcore_choose_cmd_grant = 3'd0;
-wire          litedramcore_choose_cmd_ce;
-reg           litedramcore_choose_req_want_reads = 1'd0;
-reg           litedramcore_choose_req_want_writes = 1'd0;
-reg           litedramcore_choose_req_want_cmds = 1'd0;
-reg           litedramcore_choose_req_want_activates = 1'd0;
-wire          litedramcore_choose_req_cmd_valid;
-reg           litedramcore_choose_req_cmd_ready = 1'd0;
-wire   [14:0] litedramcore_choose_req_cmd_payload_a;
-wire    [2:0] litedramcore_choose_req_cmd_payload_ba;
-reg           litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg           litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg           litedramcore_choose_req_cmd_payload_we = 1'd0;
-wire          litedramcore_choose_req_cmd_payload_is_cmd;
-wire          litedramcore_choose_req_cmd_payload_is_read;
-wire          litedramcore_choose_req_cmd_payload_is_write;
-reg     [7:0] litedramcore_choose_req_valids = 8'd0;
-wire    [7:0] litedramcore_choose_req_request;
-reg     [2:0] litedramcore_choose_req_grant = 3'd0;
-wire          litedramcore_choose_req_ce;
-reg    [14:0] litedramcore_nop_a = 15'd0;
-reg     [2:0] litedramcore_nop_ba = 3'd0;
-reg     [1:0] litedramcore_steerer_sel0 = 2'd0;
-reg     [1:0] litedramcore_steerer_sel1 = 2'd0;
-reg     [1:0] litedramcore_steerer_sel2 = 2'd0;
-reg     [1:0] litedramcore_steerer_sel3 = 2'd0;
-reg           litedramcore_steerer0 = 1'd1;
-reg           litedramcore_steerer1 = 1'd1;
-reg           litedramcore_steerer2 = 1'd1;
-reg           litedramcore_steerer3 = 1'd1;
-reg           litedramcore_steerer4 = 1'd1;
-reg           litedramcore_steerer5 = 1'd1;
-reg           litedramcore_steerer6 = 1'd1;
-reg           litedramcore_steerer7 = 1'd1;
-wire          litedramcore_trrdcon_valid;
+reg           main_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine7_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine7_wrport_adr = 4'd0;
+wire   [24:0] main_litedramcore_bankmachine7_wrport_dat_r;
+wire   [24:0] main_litedramcore_bankmachine7_wrport_dat_w;
+wire          main_litedramcore_bankmachine7_wrport_we;
+wire          main_litedramcore_cas_allowed;
+wire          main_litedramcore_choose_cmd_ce;
+wire   [14:0] main_litedramcore_choose_cmd_cmd_payload_a;
+wire    [2:0] main_litedramcore_choose_cmd_cmd_payload_ba;
+reg           main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+wire          main_litedramcore_choose_cmd_cmd_payload_is_cmd;
+wire          main_litedramcore_choose_cmd_cmd_payload_is_read;
+wire          main_litedramcore_choose_cmd_cmd_payload_is_write;
+reg           main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+reg           main_litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire          main_litedramcore_choose_cmd_cmd_valid;
+reg     [2:0] main_litedramcore_choose_cmd_grant = 3'd0;
+wire    [7:0] main_litedramcore_choose_cmd_request;
+reg     [7:0] main_litedramcore_choose_cmd_valids = 8'd0;
+reg           main_litedramcore_choose_cmd_want_activates = 1'd0;
+reg           main_litedramcore_choose_cmd_want_cmds = 1'd0;
+reg           main_litedramcore_choose_cmd_want_reads = 1'd0;
+reg           main_litedramcore_choose_cmd_want_writes = 1'd0;
+wire          main_litedramcore_choose_req_ce;
+wire   [14:0] main_litedramcore_choose_req_cmd_payload_a;
+wire    [2:0] main_litedramcore_choose_req_cmd_payload_ba;
+reg           main_litedramcore_choose_req_cmd_payload_cas = 1'd0;
+wire          main_litedramcore_choose_req_cmd_payload_is_cmd;
+wire          main_litedramcore_choose_req_cmd_payload_is_read;
+wire          main_litedramcore_choose_req_cmd_payload_is_write;
+reg           main_litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_choose_req_cmd_payload_we = 1'd0;
+reg           main_litedramcore_choose_req_cmd_ready = 1'd0;
+wire          main_litedramcore_choose_req_cmd_valid;
+reg     [2:0] main_litedramcore_choose_req_grant = 3'd0;
+wire    [7:0] main_litedramcore_choose_req_request;
+reg     [7:0] main_litedramcore_choose_req_valids = 8'd0;
+reg           main_litedramcore_choose_req_want_activates = 1'd0;
+reg           main_litedramcore_choose_req_want_cmds = 1'd0;
+reg           main_litedramcore_choose_req_want_reads = 1'd0;
+reg           main_litedramcore_choose_req_want_writes = 1'd0;
+wire          main_litedramcore_cke;
+reg           main_litedramcore_cmd_last = 1'd0;
+reg    [14:0] main_litedramcore_cmd_payload_a = 15'd0;
+reg     [2:0] main_litedramcore_cmd_payload_ba = 3'd0;
+reg           main_litedramcore_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_cmd_payload_we = 1'd0;
+reg           main_litedramcore_cmd_ready = 1'd0;
+reg           main_litedramcore_cmd_valid = 1'd0;
+reg           main_litedramcore_csr_dfi_p0_act_n = 1'd1;
+wire   [14:0] main_litedramcore_csr_dfi_p0_address;
+wire    [2:0] main_litedramcore_csr_dfi_p0_bank;
+reg           main_litedramcore_csr_dfi_p0_cas_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p0_cke = 1'd0;
+reg           main_litedramcore_csr_dfi_p0_cs_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p0_odt = 1'd0;
+reg           main_litedramcore_csr_dfi_p0_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_csr_dfi_p0_rddata = 32'd0;
+wire          main_litedramcore_csr_dfi_p0_rddata_en;
+reg           main_litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
+wire          main_litedramcore_csr_dfi_p0_reset_n;
+reg           main_litedramcore_csr_dfi_p0_we_n = 1'd1;
+wire   [31:0] main_litedramcore_csr_dfi_p0_wrdata;
+wire          main_litedramcore_csr_dfi_p0_wrdata_en;
+wire    [3:0] main_litedramcore_csr_dfi_p0_wrdata_mask;
+reg           main_litedramcore_csr_dfi_p1_act_n = 1'd1;
+wire   [14:0] main_litedramcore_csr_dfi_p1_address;
+wire    [2:0] main_litedramcore_csr_dfi_p1_bank;
+reg           main_litedramcore_csr_dfi_p1_cas_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p1_cke = 1'd0;
+reg           main_litedramcore_csr_dfi_p1_cs_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p1_odt = 1'd0;
+reg           main_litedramcore_csr_dfi_p1_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_csr_dfi_p1_rddata = 32'd0;
+wire          main_litedramcore_csr_dfi_p1_rddata_en;
+reg           main_litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
+wire          main_litedramcore_csr_dfi_p1_reset_n;
+reg           main_litedramcore_csr_dfi_p1_we_n = 1'd1;
+wire   [31:0] main_litedramcore_csr_dfi_p1_wrdata;
+wire          main_litedramcore_csr_dfi_p1_wrdata_en;
+wire    [3:0] main_litedramcore_csr_dfi_p1_wrdata_mask;
+reg           main_litedramcore_csr_dfi_p2_act_n = 1'd1;
+wire   [14:0] main_litedramcore_csr_dfi_p2_address;
+wire    [2:0] main_litedramcore_csr_dfi_p2_bank;
+reg           main_litedramcore_csr_dfi_p2_cas_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p2_cke = 1'd0;
+reg           main_litedramcore_csr_dfi_p2_cs_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p2_odt = 1'd0;
+reg           main_litedramcore_csr_dfi_p2_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_csr_dfi_p2_rddata = 32'd0;
+wire          main_litedramcore_csr_dfi_p2_rddata_en;
+reg           main_litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
+wire          main_litedramcore_csr_dfi_p2_reset_n;
+reg           main_litedramcore_csr_dfi_p2_we_n = 1'd1;
+wire   [31:0] main_litedramcore_csr_dfi_p2_wrdata;
+wire          main_litedramcore_csr_dfi_p2_wrdata_en;
+wire    [3:0] main_litedramcore_csr_dfi_p2_wrdata_mask;
+reg           main_litedramcore_csr_dfi_p3_act_n = 1'd1;
+wire   [14:0] main_litedramcore_csr_dfi_p3_address;
+wire    [2:0] main_litedramcore_csr_dfi_p3_bank;
+reg           main_litedramcore_csr_dfi_p3_cas_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p3_cke = 1'd0;
+reg           main_litedramcore_csr_dfi_p3_cs_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p3_odt = 1'd0;
+reg           main_litedramcore_csr_dfi_p3_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_csr_dfi_p3_rddata = 32'd0;
+wire          main_litedramcore_csr_dfi_p3_rddata_en;
+reg           main_litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
+wire          main_litedramcore_csr_dfi_p3_reset_n;
+reg           main_litedramcore_csr_dfi_p3_we_n = 1'd1;
+wire   [31:0] main_litedramcore_csr_dfi_p3_wrdata;
+wire          main_litedramcore_csr_dfi_p3_wrdata_en;
+wire    [3:0] main_litedramcore_csr_dfi_p3_wrdata_mask;
+reg           main_litedramcore_dfi_p0_act_n = 1'd1;
+reg    [14:0] main_litedramcore_dfi_p0_address = 15'd0;
+reg     [2:0] main_litedramcore_dfi_p0_bank = 3'd0;
+reg           main_litedramcore_dfi_p0_cas_n = 1'd1;
+wire          main_litedramcore_dfi_p0_cke;
+reg           main_litedramcore_dfi_p0_cs_n = 1'd1;
+wire          main_litedramcore_dfi_p0_odt;
+reg           main_litedramcore_dfi_p0_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p0_rddata;
+reg           main_litedramcore_dfi_p0_rddata_en = 1'd0;
+wire          main_litedramcore_dfi_p0_rddata_valid;
+wire          main_litedramcore_dfi_p0_reset_n;
+reg           main_litedramcore_dfi_p0_we_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p0_wrdata;
+reg           main_litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire    [3:0] main_litedramcore_dfi_p0_wrdata_mask;
+reg           main_litedramcore_dfi_p1_act_n = 1'd1;
+reg    [14:0] main_litedramcore_dfi_p1_address = 15'd0;
+reg     [2:0] main_litedramcore_dfi_p1_bank = 3'd0;
+reg           main_litedramcore_dfi_p1_cas_n = 1'd1;
+wire          main_litedramcore_dfi_p1_cke;
+reg           main_litedramcore_dfi_p1_cs_n = 1'd1;
+wire          main_litedramcore_dfi_p1_odt;
+reg           main_litedramcore_dfi_p1_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p1_rddata;
+reg           main_litedramcore_dfi_p1_rddata_en = 1'd0;
+wire          main_litedramcore_dfi_p1_rddata_valid;
+wire          main_litedramcore_dfi_p1_reset_n;
+reg           main_litedramcore_dfi_p1_we_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p1_wrdata;
+reg           main_litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire    [3:0] main_litedramcore_dfi_p1_wrdata_mask;
+reg           main_litedramcore_dfi_p2_act_n = 1'd1;
+reg    [14:0] main_litedramcore_dfi_p2_address = 15'd0;
+reg     [2:0] main_litedramcore_dfi_p2_bank = 3'd0;
+reg           main_litedramcore_dfi_p2_cas_n = 1'd1;
+wire          main_litedramcore_dfi_p2_cke;
+reg           main_litedramcore_dfi_p2_cs_n = 1'd1;
+wire          main_litedramcore_dfi_p2_odt;
+reg           main_litedramcore_dfi_p2_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p2_rddata;
+reg           main_litedramcore_dfi_p2_rddata_en = 1'd0;
+wire          main_litedramcore_dfi_p2_rddata_valid;
+wire          main_litedramcore_dfi_p2_reset_n;
+reg           main_litedramcore_dfi_p2_we_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p2_wrdata;
+reg           main_litedramcore_dfi_p2_wrdata_en = 1'd0;
+wire    [3:0] main_litedramcore_dfi_p2_wrdata_mask;
+reg           main_litedramcore_dfi_p3_act_n = 1'd1;
+reg    [14:0] main_litedramcore_dfi_p3_address = 15'd0;
+reg     [2:0] main_litedramcore_dfi_p3_bank = 3'd0;
+reg           main_litedramcore_dfi_p3_cas_n = 1'd1;
+wire          main_litedramcore_dfi_p3_cke;
+reg           main_litedramcore_dfi_p3_cs_n = 1'd1;
+wire          main_litedramcore_dfi_p3_odt;
+reg           main_litedramcore_dfi_p3_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p3_rddata;
+reg           main_litedramcore_dfi_p3_rddata_en = 1'd0;
+wire          main_litedramcore_dfi_p3_rddata_valid;
+wire          main_litedramcore_dfi_p3_reset_n;
+reg           main_litedramcore_dfi_p3_we_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p3_wrdata;
+reg           main_litedramcore_dfi_p3_wrdata_en = 1'd0;
+wire    [3:0] main_litedramcore_dfi_p3_wrdata_mask;
+reg           main_litedramcore_en0 = 1'd0;
+reg           main_litedramcore_en1 = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_act_n = 1'd1;
+reg    [14:0] main_litedramcore_ext_dfi_p0_address = 15'd0;
+reg     [2:0] main_litedramcore_ext_dfi_p0_bank = 3'd0;
+reg           main_litedramcore_ext_dfi_p0_cas_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p0_cke = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_cs_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p0_odt = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p0_rddata = 32'd0;
+reg           main_litedramcore_ext_dfi_p0_rddata_en = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_reset_n = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_we_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p0_wrdata = 32'd0;
+reg           main_litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
+reg           main_litedramcore_ext_dfi_p1_act_n = 1'd1;
+reg    [14:0] main_litedramcore_ext_dfi_p1_address = 15'd0;
+reg     [2:0] main_litedramcore_ext_dfi_p1_bank = 3'd0;
+reg           main_litedramcore_ext_dfi_p1_cas_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p1_cke = 1'd0;
+reg           main_litedramcore_ext_dfi_p1_cs_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p1_odt = 1'd0;
+reg           main_litedramcore_ext_dfi_p1_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p1_rddata = 32'd0;
+reg           main_litedramcore_ext_dfi_p1_rddata_en = 1'd0;
+reg           main_litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
+reg           main_litedramcore_ext_dfi_p1_reset_n = 1'd0;
+reg           main_litedramcore_ext_dfi_p1_we_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p1_wrdata = 32'd0;
+reg           main_litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
+reg           main_litedramcore_ext_dfi_p2_act_n = 1'd1;
+reg    [14:0] main_litedramcore_ext_dfi_p2_address = 15'd0;
+reg     [2:0] main_litedramcore_ext_dfi_p2_bank = 3'd0;
+reg           main_litedramcore_ext_dfi_p2_cas_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p2_cke = 1'd0;
+reg           main_litedramcore_ext_dfi_p2_cs_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p2_odt = 1'd0;
+reg           main_litedramcore_ext_dfi_p2_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p2_rddata = 32'd0;
+reg           main_litedramcore_ext_dfi_p2_rddata_en = 1'd0;
+reg           main_litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
+reg           main_litedramcore_ext_dfi_p2_reset_n = 1'd0;
+reg           main_litedramcore_ext_dfi_p2_we_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p2_wrdata = 32'd0;
+reg           main_litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
+reg           main_litedramcore_ext_dfi_p3_act_n = 1'd1;
+reg    [14:0] main_litedramcore_ext_dfi_p3_address = 15'd0;
+reg     [2:0] main_litedramcore_ext_dfi_p3_bank = 3'd0;
+reg           main_litedramcore_ext_dfi_p3_cas_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p3_cke = 1'd0;
+reg           main_litedramcore_ext_dfi_p3_cs_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p3_odt = 1'd0;
+reg           main_litedramcore_ext_dfi_p3_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p3_rddata = 32'd0;
+reg           main_litedramcore_ext_dfi_p3_rddata_en = 1'd0;
+reg           main_litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
+reg           main_litedramcore_ext_dfi_p3_reset_n = 1'd0;
+reg           main_litedramcore_ext_dfi_p3_we_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p3_wrdata = 32'd0;
+reg           main_litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
+reg           main_litedramcore_ext_dfi_sel = 1'd0;
+wire          main_litedramcore_go_to_refresh;
+wire   [21:0] main_litedramcore_interface_bank0_addr;
+wire          main_litedramcore_interface_bank0_lock;
+wire          main_litedramcore_interface_bank0_rdata_valid;
+wire          main_litedramcore_interface_bank0_ready;
+wire          main_litedramcore_interface_bank0_valid;
+wire          main_litedramcore_interface_bank0_wdata_ready;
+wire          main_litedramcore_interface_bank0_we;
+wire   [21:0] main_litedramcore_interface_bank1_addr;
+wire          main_litedramcore_interface_bank1_lock;
+wire          main_litedramcore_interface_bank1_rdata_valid;
+wire          main_litedramcore_interface_bank1_ready;
+wire          main_litedramcore_interface_bank1_valid;
+wire          main_litedramcore_interface_bank1_wdata_ready;
+wire          main_litedramcore_interface_bank1_we;
+wire   [21:0] main_litedramcore_interface_bank2_addr;
+wire          main_litedramcore_interface_bank2_lock;
+wire          main_litedramcore_interface_bank2_rdata_valid;
+wire          main_litedramcore_interface_bank2_ready;
+wire          main_litedramcore_interface_bank2_valid;
+wire          main_litedramcore_interface_bank2_wdata_ready;
+wire          main_litedramcore_interface_bank2_we;
+wire   [21:0] main_litedramcore_interface_bank3_addr;
+wire          main_litedramcore_interface_bank3_lock;
+wire          main_litedramcore_interface_bank3_rdata_valid;
+wire          main_litedramcore_interface_bank3_ready;
+wire          main_litedramcore_interface_bank3_valid;
+wire          main_litedramcore_interface_bank3_wdata_ready;
+wire          main_litedramcore_interface_bank3_we;
+wire   [21:0] main_litedramcore_interface_bank4_addr;
+wire          main_litedramcore_interface_bank4_lock;
+wire          main_litedramcore_interface_bank4_rdata_valid;
+wire          main_litedramcore_interface_bank4_ready;
+wire          main_litedramcore_interface_bank4_valid;
+wire          main_litedramcore_interface_bank4_wdata_ready;
+wire          main_litedramcore_interface_bank4_we;
+wire   [21:0] main_litedramcore_interface_bank5_addr;
+wire          main_litedramcore_interface_bank5_lock;
+wire          main_litedramcore_interface_bank5_rdata_valid;
+wire          main_litedramcore_interface_bank5_ready;
+wire          main_litedramcore_interface_bank5_valid;
+wire          main_litedramcore_interface_bank5_wdata_ready;
+wire          main_litedramcore_interface_bank5_we;
+wire   [21:0] main_litedramcore_interface_bank6_addr;
+wire          main_litedramcore_interface_bank6_lock;
+wire          main_litedramcore_interface_bank6_rdata_valid;
+wire          main_litedramcore_interface_bank6_ready;
+wire          main_litedramcore_interface_bank6_valid;
+wire          main_litedramcore_interface_bank6_wdata_ready;
+wire          main_litedramcore_interface_bank6_we;
+wire   [21:0] main_litedramcore_interface_bank7_addr;
+wire          main_litedramcore_interface_bank7_lock;
+wire          main_litedramcore_interface_bank7_rdata_valid;
+wire          main_litedramcore_interface_bank7_ready;
+wire          main_litedramcore_interface_bank7_valid;
+wire          main_litedramcore_interface_bank7_wdata_ready;
+wire          main_litedramcore_interface_bank7_we;
+wire  [127:0] main_litedramcore_interface_rdata;
+reg   [127:0] main_litedramcore_interface_wdata = 128'd0;
+reg    [15:0] main_litedramcore_interface_wdata_we = 16'd0;
+reg           main_litedramcore_master_p0_act_n = 1'd1;
+reg    [14:0] main_litedramcore_master_p0_address = 15'd0;
+reg     [2:0] main_litedramcore_master_p0_bank = 3'd0;
+reg           main_litedramcore_master_p0_cas_n = 1'd1;
+reg           main_litedramcore_master_p0_cke = 1'd0;
+reg           main_litedramcore_master_p0_cs_n = 1'd1;
+reg           main_litedramcore_master_p0_odt = 1'd0;
+reg           main_litedramcore_master_p0_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_master_p0_rddata;
+reg           main_litedramcore_master_p0_rddata_en = 1'd0;
+wire          main_litedramcore_master_p0_rddata_valid;
+reg           main_litedramcore_master_p0_reset_n = 1'd0;
+reg           main_litedramcore_master_p0_we_n = 1'd1;
+reg    [31:0] main_litedramcore_master_p0_wrdata = 32'd0;
+reg           main_litedramcore_master_p0_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0;
+reg           main_litedramcore_master_p1_act_n = 1'd1;
+reg    [14:0] main_litedramcore_master_p1_address = 15'd0;
+reg     [2:0] main_litedramcore_master_p1_bank = 3'd0;
+reg           main_litedramcore_master_p1_cas_n = 1'd1;
+reg           main_litedramcore_master_p1_cke = 1'd0;
+reg           main_litedramcore_master_p1_cs_n = 1'd1;
+reg           main_litedramcore_master_p1_odt = 1'd0;
+reg           main_litedramcore_master_p1_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_master_p1_rddata;
+reg           main_litedramcore_master_p1_rddata_en = 1'd0;
+wire          main_litedramcore_master_p1_rddata_valid;
+reg           main_litedramcore_master_p1_reset_n = 1'd0;
+reg           main_litedramcore_master_p1_we_n = 1'd1;
+reg    [31:0] main_litedramcore_master_p1_wrdata = 32'd0;
+reg           main_litedramcore_master_p1_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0;
+reg           main_litedramcore_master_p2_act_n = 1'd1;
+reg    [14:0] main_litedramcore_master_p2_address = 15'd0;
+reg     [2:0] main_litedramcore_master_p2_bank = 3'd0;
+reg           main_litedramcore_master_p2_cas_n = 1'd1;
+reg           main_litedramcore_master_p2_cke = 1'd0;
+reg           main_litedramcore_master_p2_cs_n = 1'd1;
+reg           main_litedramcore_master_p2_odt = 1'd0;
+reg           main_litedramcore_master_p2_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_master_p2_rddata;
+reg           main_litedramcore_master_p2_rddata_en = 1'd0;
+wire          main_litedramcore_master_p2_rddata_valid;
+reg           main_litedramcore_master_p2_reset_n = 1'd0;
+reg           main_litedramcore_master_p2_we_n = 1'd1;
+reg    [31:0] main_litedramcore_master_p2_wrdata = 32'd0;
+reg           main_litedramcore_master_p2_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0;
+reg           main_litedramcore_master_p3_act_n = 1'd1;
+reg    [14:0] main_litedramcore_master_p3_address = 15'd0;
+reg     [2:0] main_litedramcore_master_p3_bank = 3'd0;
+reg           main_litedramcore_master_p3_cas_n = 1'd1;
+reg           main_litedramcore_master_p3_cke = 1'd0;
+reg           main_litedramcore_master_p3_cs_n = 1'd1;
+reg           main_litedramcore_master_p3_odt = 1'd0;
+reg           main_litedramcore_master_p3_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_master_p3_rddata;
+reg           main_litedramcore_master_p3_rddata_en = 1'd0;
+wire          main_litedramcore_master_p3_rddata_valid;
+reg           main_litedramcore_master_p3_reset_n = 1'd0;
+reg           main_litedramcore_master_p3_we_n = 1'd1;
+reg    [31:0] main_litedramcore_master_p3_wrdata = 32'd0;
+reg           main_litedramcore_master_p3_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0;
+wire          main_litedramcore_max_time0;
+wire          main_litedramcore_max_time1;
+reg    [14:0] main_litedramcore_nop_a = 15'd0;
+reg     [2:0] main_litedramcore_nop_ba = 3'd0;
+wire    [1:0] main_litedramcore_nphases;
+wire          main_litedramcore_odt;
+reg           main_litedramcore_phaseinjector0_address_re = 1'd0;
+reg    [14:0] main_litedramcore_phaseinjector0_address_storage = 15'd0;
+reg           main_litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg     [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0;
+wire          main_litedramcore_phaseinjector0_command_issue_r;
+reg           main_litedramcore_phaseinjector0_command_issue_re = 1'd0;
+reg           main_litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg           main_litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg           main_litedramcore_phaseinjector0_command_re = 1'd0;
+reg     [7:0] main_litedramcore_phaseinjector0_command_storage = 8'd0;
+wire          main_litedramcore_phaseinjector0_csrfield_cas;
+wire          main_litedramcore_phaseinjector0_csrfield_cs;
+wire          main_litedramcore_phaseinjector0_csrfield_cs_bottom;
+wire          main_litedramcore_phaseinjector0_csrfield_cs_top;
+wire          main_litedramcore_phaseinjector0_csrfield_ras;
+wire          main_litedramcore_phaseinjector0_csrfield_rden;
+wire          main_litedramcore_phaseinjector0_csrfield_we;
+wire          main_litedramcore_phaseinjector0_csrfield_wren;
+reg           main_litedramcore_phaseinjector0_rddata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0;
+wire          main_litedramcore_phaseinjector0_rddata_we;
+reg           main_litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
+reg           main_litedramcore_phaseinjector1_address_re = 1'd0;
+reg    [14:0] main_litedramcore_phaseinjector1_address_storage = 15'd0;
+reg           main_litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg     [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0;
+wire          main_litedramcore_phaseinjector1_command_issue_r;
+reg           main_litedramcore_phaseinjector1_command_issue_re = 1'd0;
+reg           main_litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg           main_litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg           main_litedramcore_phaseinjector1_command_re = 1'd0;
+reg     [7:0] main_litedramcore_phaseinjector1_command_storage = 8'd0;
+wire          main_litedramcore_phaseinjector1_csrfield_cas;
+wire          main_litedramcore_phaseinjector1_csrfield_cs;
+wire          main_litedramcore_phaseinjector1_csrfield_cs_bottom;
+wire          main_litedramcore_phaseinjector1_csrfield_cs_top;
+wire          main_litedramcore_phaseinjector1_csrfield_ras;
+wire          main_litedramcore_phaseinjector1_csrfield_rden;
+wire          main_litedramcore_phaseinjector1_csrfield_we;
+wire          main_litedramcore_phaseinjector1_csrfield_wren;
+reg           main_litedramcore_phaseinjector1_rddata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0;
+wire          main_litedramcore_phaseinjector1_rddata_we;
+reg           main_litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
+reg           main_litedramcore_phaseinjector2_address_re = 1'd0;
+reg    [14:0] main_litedramcore_phaseinjector2_address_storage = 15'd0;
+reg           main_litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg     [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0;
+wire          main_litedramcore_phaseinjector2_command_issue_r;
+reg           main_litedramcore_phaseinjector2_command_issue_re = 1'd0;
+reg           main_litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg           main_litedramcore_phaseinjector2_command_issue_we = 1'd0;
+reg           main_litedramcore_phaseinjector2_command_re = 1'd0;
+reg     [7:0] main_litedramcore_phaseinjector2_command_storage = 8'd0;
+wire          main_litedramcore_phaseinjector2_csrfield_cas;
+wire          main_litedramcore_phaseinjector2_csrfield_cs;
+wire          main_litedramcore_phaseinjector2_csrfield_cs_bottom;
+wire          main_litedramcore_phaseinjector2_csrfield_cs_top;
+wire          main_litedramcore_phaseinjector2_csrfield_ras;
+wire          main_litedramcore_phaseinjector2_csrfield_rden;
+wire          main_litedramcore_phaseinjector2_csrfield_we;
+wire          main_litedramcore_phaseinjector2_csrfield_wren;
+reg           main_litedramcore_phaseinjector2_rddata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0;
+wire          main_litedramcore_phaseinjector2_rddata_we;
+reg           main_litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
+reg           main_litedramcore_phaseinjector3_address_re = 1'd0;
+reg    [14:0] main_litedramcore_phaseinjector3_address_storage = 15'd0;
+reg           main_litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg     [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0;
+wire          main_litedramcore_phaseinjector3_command_issue_r;
+reg           main_litedramcore_phaseinjector3_command_issue_re = 1'd0;
+reg           main_litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg           main_litedramcore_phaseinjector3_command_issue_we = 1'd0;
+reg           main_litedramcore_phaseinjector3_command_re = 1'd0;
+reg     [7:0] main_litedramcore_phaseinjector3_command_storage = 8'd0;
+wire          main_litedramcore_phaseinjector3_csrfield_cas;
+wire          main_litedramcore_phaseinjector3_csrfield_cs;
+wire          main_litedramcore_phaseinjector3_csrfield_cs_bottom;
+wire          main_litedramcore_phaseinjector3_csrfield_cs_top;
+wire          main_litedramcore_phaseinjector3_csrfield_ras;
+wire          main_litedramcore_phaseinjector3_csrfield_rden;
+wire          main_litedramcore_phaseinjector3_csrfield_we;
+wire          main_litedramcore_phaseinjector3_csrfield_wren;
+reg           main_litedramcore_phaseinjector3_rddata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0;
+wire          main_litedramcore_phaseinjector3_rddata_we;
+reg           main_litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
+reg           main_litedramcore_postponer_count = 1'd0;
+wire          main_litedramcore_postponer_req_i;
+reg           main_litedramcore_postponer_req_o = 1'd0;
+wire          main_litedramcore_ras_allowed;
+wire    [1:0] main_litedramcore_rdphase;
+reg           main_litedramcore_re = 1'd0;
+wire          main_litedramcore_read_available;
+wire          main_litedramcore_reset_n;
+wire          main_litedramcore_sel;
+reg           main_litedramcore_sequencer_count = 1'd0;
+wire          main_litedramcore_sequencer_done0;
+reg           main_litedramcore_sequencer_done1 = 1'd0;
+reg           main_litedramcore_sequencer_start0 = 1'd0;
+wire          main_litedramcore_sequencer_start1;
+reg     [5:0] main_litedramcore_sequencer_trigger = 6'd0;
+wire          main_litedramcore_slave_p0_act_n;
+wire   [14:0] main_litedramcore_slave_p0_address;
+wire    [2:0] main_litedramcore_slave_p0_bank;
+wire          main_litedramcore_slave_p0_cas_n;
+wire          main_litedramcore_slave_p0_cke;
+wire          main_litedramcore_slave_p0_cs_n;
+wire          main_litedramcore_slave_p0_odt;
+wire          main_litedramcore_slave_p0_ras_n;
+reg    [31:0] main_litedramcore_slave_p0_rddata = 32'd0;
+wire          main_litedramcore_slave_p0_rddata_en;
+reg           main_litedramcore_slave_p0_rddata_valid = 1'd0;
+wire          main_litedramcore_slave_p0_reset_n;
+wire          main_litedramcore_slave_p0_we_n;
+wire   [31:0] main_litedramcore_slave_p0_wrdata;
+wire          main_litedramcore_slave_p0_wrdata_en;
+wire    [3:0] main_litedramcore_slave_p0_wrdata_mask;
+wire          main_litedramcore_slave_p1_act_n;
+wire   [14:0] main_litedramcore_slave_p1_address;
+wire    [2:0] main_litedramcore_slave_p1_bank;
+wire          main_litedramcore_slave_p1_cas_n;
+wire          main_litedramcore_slave_p1_cke;
+wire          main_litedramcore_slave_p1_cs_n;
+wire          main_litedramcore_slave_p1_odt;
+wire          main_litedramcore_slave_p1_ras_n;
+reg    [31:0] main_litedramcore_slave_p1_rddata = 32'd0;
+wire          main_litedramcore_slave_p1_rddata_en;
+reg           main_litedramcore_slave_p1_rddata_valid = 1'd0;
+wire          main_litedramcore_slave_p1_reset_n;
+wire          main_litedramcore_slave_p1_we_n;
+wire   [31:0] main_litedramcore_slave_p1_wrdata;
+wire          main_litedramcore_slave_p1_wrdata_en;
+wire    [3:0] main_litedramcore_slave_p1_wrdata_mask;
+wire          main_litedramcore_slave_p2_act_n;
+wire   [14:0] main_litedramcore_slave_p2_address;
+wire    [2:0] main_litedramcore_slave_p2_bank;
+wire          main_litedramcore_slave_p2_cas_n;
+wire          main_litedramcore_slave_p2_cke;
+wire          main_litedramcore_slave_p2_cs_n;
+wire          main_litedramcore_slave_p2_odt;
+wire          main_litedramcore_slave_p2_ras_n;
+reg    [31:0] main_litedramcore_slave_p2_rddata = 32'd0;
+wire          main_litedramcore_slave_p2_rddata_en;
+reg           main_litedramcore_slave_p2_rddata_valid = 1'd0;
+wire          main_litedramcore_slave_p2_reset_n;
+wire          main_litedramcore_slave_p2_we_n;
+wire   [31:0] main_litedramcore_slave_p2_wrdata;
+wire          main_litedramcore_slave_p2_wrdata_en;
+wire    [3:0] main_litedramcore_slave_p2_wrdata_mask;
+wire          main_litedramcore_slave_p3_act_n;
+wire   [14:0] main_litedramcore_slave_p3_address;
+wire    [2:0] main_litedramcore_slave_p3_bank;
+wire          main_litedramcore_slave_p3_cas_n;
+wire          main_litedramcore_slave_p3_cke;
+wire          main_litedramcore_slave_p3_cs_n;
+wire          main_litedramcore_slave_p3_odt;
+wire          main_litedramcore_slave_p3_ras_n;
+reg    [31:0] main_litedramcore_slave_p3_rddata = 32'd0;
+wire          main_litedramcore_slave_p3_rddata_en;
+reg           main_litedramcore_slave_p3_rddata_valid = 1'd0;
+wire          main_litedramcore_slave_p3_reset_n;
+wire          main_litedramcore_slave_p3_we_n;
+wire   [31:0] main_litedramcore_slave_p3_wrdata;
+wire          main_litedramcore_slave_p3_wrdata_en;
+wire    [3:0] main_litedramcore_slave_p3_wrdata_mask;
+reg     [1:0] main_litedramcore_steerer0 = 2'd0;
+reg     [1:0] main_litedramcore_steerer1 = 2'd0;
+reg           main_litedramcore_steerer10 = 1'd1;
+reg           main_litedramcore_steerer11 = 1'd1;
+reg     [1:0] main_litedramcore_steerer2 = 2'd0;
+reg     [1:0] main_litedramcore_steerer3 = 2'd0;
+reg           main_litedramcore_steerer4 = 1'd1;
+reg           main_litedramcore_steerer5 = 1'd1;
+reg           main_litedramcore_steerer6 = 1'd1;
+reg           main_litedramcore_steerer7 = 1'd1;
+reg           main_litedramcore_steerer8 = 1'd1;
+reg           main_litedramcore_steerer9 = 1'd1;
+reg     [3:0] main_litedramcore_storage = 4'd1;
+reg           main_litedramcore_tccdcon_count = 1'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_trrdcon_ready = 1'd0;
-reg           litedramcore_trrdcon_count = 1'd0;
-wire          litedramcore_tfawcon_valid;
+reg           main_litedramcore_tccdcon_ready = 1'd0;
+wire          main_litedramcore_tccdcon_valid;
+wire    [2:0] main_litedramcore_tfawcon_count;
 (* dont_touch = "true" *)
-reg           litedramcore_tfawcon_ready = 1'd1;
-wire    [2:0] litedramcore_tfawcon_count;
-reg     [4:0] litedramcore_tfawcon_window = 5'd0;
-wire          litedramcore_tccdcon_valid;
+reg           main_litedramcore_tfawcon_ready = 1'd1;
+wire          main_litedramcore_tfawcon_valid;
+reg     [4:0] main_litedramcore_tfawcon_window = 5'd0;
+reg     [4:0] main_litedramcore_time0 = 5'd0;
+reg     [3:0] main_litedramcore_time1 = 4'd0;
+wire    [9:0] main_litedramcore_timer_count0;
+reg     [9:0] main_litedramcore_timer_count1 = 10'd781;
+wire          main_litedramcore_timer_done0;
+wire          main_litedramcore_timer_done1;
+wire          main_litedramcore_timer_wait;
+reg           main_litedramcore_trrdcon_count = 1'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_tccdcon_ready = 1'd0;
-reg           litedramcore_tccdcon_count = 1'd0;
-wire          litedramcore_twtrcon_valid;
+reg           main_litedramcore_trrdcon_ready = 1'd0;
+wire          main_litedramcore_trrdcon_valid;
+reg     [2:0] main_litedramcore_twtrcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_twtrcon_ready = 1'd0;
-reg     [2:0] litedramcore_twtrcon_count = 3'd0;
-wire          litedramcore_read_available;
-wire          litedramcore_write_available;
-reg           litedramcore_en0 = 1'd0;
-wire          litedramcore_max_time0;
-reg     [4:0] litedramcore_time0 = 5'd0;
-reg           litedramcore_en1 = 1'd0;
-wire          litedramcore_max_time1;
-reg     [3:0] litedramcore_time1 = 4'd0;
-wire          litedramcore_go_to_refresh;
-reg           init_done_storage = 1'd0;
-reg           init_done_re = 1'd0;
-reg           init_error_storage = 1'd0;
-reg           init_error_re = 1'd0;
-wire   [29:0] wb_bus_adr;
-wire   [31:0] wb_bus_dat_w;
-wire   [31:0] wb_bus_dat_r;
-wire    [3:0] wb_bus_sel;
-wire          wb_bus_cyc;
-wire          wb_bus_stb;
-wire          wb_bus_ack;
-wire          wb_bus_we;
-wire    [2:0] wb_bus_cti;
-wire    [1:0] wb_bus_bte;
-wire          wb_bus_err;
-wire          user_enable;
-wire          user_port_cmd_valid;
-wire          user_port_cmd_ready;
-wire          user_port_cmd_payload_we;
-wire   [24:0] user_port_cmd_payload_addr;
-wire          user_port_wdata_valid;
-wire          user_port_wdata_ready;
-wire  [127:0] user_port_wdata_payload_data;
-wire   [15:0] user_port_wdata_payload_we;
-wire          user_port_rdata_valid;
-wire          user_port_rdata_ready;
-wire  [127:0] user_port_rdata_payload_data;
-reg    [13:0] litedramcore_adr = 14'd0;
-reg           litedramcore_we = 1'd0;
-reg    [31:0] litedramcore_dat_w = 32'd0;
-wire   [31:0] litedramcore_dat_r;
-wire   [29:0] litedramcore_wishbone_adr;
-wire   [31:0] litedramcore_wishbone_dat_w;
-reg    [31:0] litedramcore_wishbone_dat_r = 32'd0;
-wire    [3:0] litedramcore_wishbone_sel;
-wire          litedramcore_wishbone_cyc;
-wire          litedramcore_wishbone_stb;
-reg           litedramcore_wishbone_ack = 1'd0;
-wire          litedramcore_wishbone_we;
-wire    [2:0] litedramcore_wishbone_cti;
-wire    [1:0] litedramcore_wishbone_bte;
-reg           litedramcore_wishbone_err = 1'd0;
-wire   [13:0] interface0_bank_bus_adr;
-wire          interface0_bank_bus_we;
-wire   [31:0] interface0_bank_bus_dat_w;
-reg    [31:0] interface0_bank_bus_dat_r = 32'd0;
-reg           csrbank0_init_done0_re = 1'd0;
-wire          csrbank0_init_done0_r;
-reg           csrbank0_init_done0_we = 1'd0;
-wire          csrbank0_init_done0_w;
-reg           csrbank0_init_error0_re = 1'd0;
-wire          csrbank0_init_error0_r;
-reg           csrbank0_init_error0_we = 1'd0;
-wire          csrbank0_init_error0_w;
-wire          csrbank0_sel;
-wire   [13:0] interface1_bank_bus_adr;
-wire          interface1_bank_bus_we;
-wire   [31:0] interface1_bank_bus_dat_w;
-reg    [31:0] interface1_bank_bus_dat_r = 32'd0;
-reg           csrbank1_rst0_re = 1'd0;
-wire          csrbank1_rst0_r;
-reg           csrbank1_rst0_we = 1'd0;
-wire          csrbank1_rst0_w;
-reg           csrbank1_dly_sel0_re = 1'd0;
-wire    [1:0] csrbank1_dly_sel0_r;
-reg           csrbank1_dly_sel0_we = 1'd0;
-wire    [1:0] csrbank1_dly_sel0_w;
-reg           csrbank1_half_sys8x_taps0_re = 1'd0;
-wire    [4:0] csrbank1_half_sys8x_taps0_r;
-reg           csrbank1_half_sys8x_taps0_we = 1'd0;
-wire    [4:0] csrbank1_half_sys8x_taps0_w;
-reg           csrbank1_wlevel_en0_re = 1'd0;
-wire          csrbank1_wlevel_en0_r;
-reg           csrbank1_wlevel_en0_we = 1'd0;
-wire          csrbank1_wlevel_en0_w;
-reg           csrbank1_rdphase0_re = 1'd0;
-wire    [1:0] csrbank1_rdphase0_r;
-reg           csrbank1_rdphase0_we = 1'd0;
-wire    [1:0] csrbank1_rdphase0_w;
-reg           csrbank1_wrphase0_re = 1'd0;
-wire    [1:0] csrbank1_wrphase0_r;
-reg           csrbank1_wrphase0_we = 1'd0;
-wire    [1:0] csrbank1_wrphase0_w;
-wire          csrbank1_sel;
-wire   [13:0] interface2_bank_bus_adr;
-wire          interface2_bank_bus_we;
-wire   [31:0] interface2_bank_bus_dat_w;
-reg    [31:0] interface2_bank_bus_dat_r = 32'd0;
-reg           csrbank2_dfii_control0_re = 1'd0;
-wire    [3:0] csrbank2_dfii_control0_r;
-reg           csrbank2_dfii_control0_we = 1'd0;
-wire    [3:0] csrbank2_dfii_control0_w;
-reg           csrbank2_dfii_pi0_command0_re = 1'd0;
-wire    [5:0] csrbank2_dfii_pi0_command0_r;
-reg           csrbank2_dfii_pi0_command0_we = 1'd0;
-wire    [5:0] csrbank2_dfii_pi0_command0_w;
-reg           csrbank2_dfii_pi0_address0_re = 1'd0;
-wire   [14:0] csrbank2_dfii_pi0_address0_r;
-reg           csrbank2_dfii_pi0_address0_we = 1'd0;
-wire   [14:0] csrbank2_dfii_pi0_address0_w;
-reg           csrbank2_dfii_pi0_baddress0_re = 1'd0;
-wire    [2:0] csrbank2_dfii_pi0_baddress0_r;
-reg           csrbank2_dfii_pi0_baddress0_we = 1'd0;
-wire    [2:0] csrbank2_dfii_pi0_baddress0_w;
-reg           csrbank2_dfii_pi0_wrdata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_wrdata0_r;
-reg           csrbank2_dfii_pi0_wrdata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_wrdata0_w;
-reg           csrbank2_dfii_pi0_rddata_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_rddata_r;
-reg           csrbank2_dfii_pi0_rddata_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_rddata_w;
-reg           csrbank2_dfii_pi1_command0_re = 1'd0;
-wire    [5:0] csrbank2_dfii_pi1_command0_r;
-reg           csrbank2_dfii_pi1_command0_we = 1'd0;
-wire    [5:0] csrbank2_dfii_pi1_command0_w;
-reg           csrbank2_dfii_pi1_address0_re = 1'd0;
-wire   [14:0] csrbank2_dfii_pi1_address0_r;
-reg           csrbank2_dfii_pi1_address0_we = 1'd0;
-wire   [14:0] csrbank2_dfii_pi1_address0_w;
-reg           csrbank2_dfii_pi1_baddress0_re = 1'd0;
-wire    [2:0] csrbank2_dfii_pi1_baddress0_r;
-reg           csrbank2_dfii_pi1_baddress0_we = 1'd0;
-wire    [2:0] csrbank2_dfii_pi1_baddress0_w;
-reg           csrbank2_dfii_pi1_wrdata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_wrdata0_r;
-reg           csrbank2_dfii_pi1_wrdata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_wrdata0_w;
-reg           csrbank2_dfii_pi1_rddata_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_rddata_r;
-reg           csrbank2_dfii_pi1_rddata_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_rddata_w;
-reg           csrbank2_dfii_pi2_command0_re = 1'd0;
-wire    [5:0] csrbank2_dfii_pi2_command0_r;
-reg           csrbank2_dfii_pi2_command0_we = 1'd0;
-wire    [5:0] csrbank2_dfii_pi2_command0_w;
-reg           csrbank2_dfii_pi2_address0_re = 1'd0;
-wire   [14:0] csrbank2_dfii_pi2_address0_r;
-reg           csrbank2_dfii_pi2_address0_we = 1'd0;
-wire   [14:0] csrbank2_dfii_pi2_address0_w;
-reg           csrbank2_dfii_pi2_baddress0_re = 1'd0;
-wire    [2:0] csrbank2_dfii_pi2_baddress0_r;
-reg           csrbank2_dfii_pi2_baddress0_we = 1'd0;
-wire    [2:0] csrbank2_dfii_pi2_baddress0_w;
-reg           csrbank2_dfii_pi2_wrdata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi2_wrdata0_r;
-reg           csrbank2_dfii_pi2_wrdata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi2_wrdata0_w;
-reg           csrbank2_dfii_pi2_rddata_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi2_rddata_r;
-reg           csrbank2_dfii_pi2_rddata_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi2_rddata_w;
-reg           csrbank2_dfii_pi3_command0_re = 1'd0;
-wire    [5:0] csrbank2_dfii_pi3_command0_r;
-reg           csrbank2_dfii_pi3_command0_we = 1'd0;
-wire    [5:0] csrbank2_dfii_pi3_command0_w;
-reg           csrbank2_dfii_pi3_address0_re = 1'd0;
-wire   [14:0] csrbank2_dfii_pi3_address0_r;
-reg           csrbank2_dfii_pi3_address0_we = 1'd0;
-wire   [14:0] csrbank2_dfii_pi3_address0_w;
-reg           csrbank2_dfii_pi3_baddress0_re = 1'd0;
-wire    [2:0] csrbank2_dfii_pi3_baddress0_r;
-reg           csrbank2_dfii_pi3_baddress0_we = 1'd0;
-wire    [2:0] csrbank2_dfii_pi3_baddress0_w;
-reg           csrbank2_dfii_pi3_wrdata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi3_wrdata0_r;
-reg           csrbank2_dfii_pi3_wrdata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi3_wrdata0_w;
-reg           csrbank2_dfii_pi3_rddata_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi3_rddata_r;
-reg           csrbank2_dfii_pi3_rddata_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi3_rddata_w;
-wire          csrbank2_sel;
-wire   [13:0] csr_interconnect_adr;
-wire          csr_interconnect_we;
-wire   [31:0] csr_interconnect_dat_w;
-wire   [31:0] csr_interconnect_dat_r;
-wire          litedramcore_reset0;
-wire          litedramcore_reset1;
-wire          litedramcore_reset2;
-wire          litedramcore_reset3;
-wire          litedramcore_reset4;
-wire          litedramcore_reset5;
-wire          litedramcore_reset6;
-wire          litedramcore_reset7;
-wire          litedramcore_pll_fb;
-reg     [1:0] litedramcore_refresher_state = 2'd0;
-reg     [1:0] litedramcore_refresher_next_state = 2'd0;
-reg     [3:0] litedramcore_bankmachine0_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine0_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine1_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine1_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine2_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine2_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine3_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine3_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine4_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine4_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine5_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine5_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine6_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine6_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine7_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine7_next_state = 4'd0;
-reg     [3:0] litedramcore_multiplexer_state = 4'd0;
-reg     [3:0] litedramcore_multiplexer_next_state = 4'd0;
-wire          litedramcore_roundrobin0_request;
-wire          litedramcore_roundrobin0_grant;
-wire          litedramcore_roundrobin0_ce;
-wire          litedramcore_roundrobin1_request;
-wire          litedramcore_roundrobin1_grant;
-wire          litedramcore_roundrobin1_ce;
-wire          litedramcore_roundrobin2_request;
-wire          litedramcore_roundrobin2_grant;
-wire          litedramcore_roundrobin2_ce;
-wire          litedramcore_roundrobin3_request;
-wire          litedramcore_roundrobin3_grant;
-wire          litedramcore_roundrobin3_ce;
-wire          litedramcore_roundrobin4_request;
-wire          litedramcore_roundrobin4_grant;
-wire          litedramcore_roundrobin4_ce;
-wire          litedramcore_roundrobin5_request;
-wire          litedramcore_roundrobin5_grant;
-wire          litedramcore_roundrobin5_ce;
-wire          litedramcore_roundrobin6_request;
-wire          litedramcore_roundrobin6_grant;
-wire          litedramcore_roundrobin6_ce;
-wire          litedramcore_roundrobin7_request;
-wire          litedramcore_roundrobin7_grant;
-wire          litedramcore_roundrobin7_ce;
-reg           litedramcore_locked0 = 1'd0;
-reg           litedramcore_locked1 = 1'd0;
-reg           litedramcore_locked2 = 1'd0;
-reg           litedramcore_locked3 = 1'd0;
-reg           litedramcore_locked4 = 1'd0;
-reg           litedramcore_locked5 = 1'd0;
-reg           litedramcore_locked6 = 1'd0;
-reg           litedramcore_locked7 = 1'd0;
-reg           litedramcore_new_master_wdata_ready0 = 1'd0;
-reg           litedramcore_new_master_wdata_ready1 = 1'd0;
-reg           litedramcore_new_master_rdata_valid0 = 1'd0;
-reg           litedramcore_new_master_rdata_valid1 = 1'd0;
-reg           litedramcore_new_master_rdata_valid2 = 1'd0;
-reg           litedramcore_new_master_rdata_valid3 = 1'd0;
-reg           litedramcore_new_master_rdata_valid4 = 1'd0;
-reg           litedramcore_new_master_rdata_valid5 = 1'd0;
-reg           litedramcore_new_master_rdata_valid6 = 1'd0;
-reg           litedramcore_new_master_rdata_valid7 = 1'd0;
-reg           litedramcore_new_master_rdata_valid8 = 1'd0;
-reg     [1:0] litedramcore_state = 2'd0;
-reg     [1:0] litedramcore_next_state = 2'd0;
-reg    [31:0] litedramcore_dat_w_next_value0 = 32'd0;
-reg           litedramcore_dat_w_next_value_ce0 = 1'd0;
-reg    [13:0] litedramcore_adr_next_value1 = 14'd0;
-reg           litedramcore_adr_next_value_ce1 = 1'd0;
-reg           litedramcore_we_next_value2 = 1'd0;
-reg           litedramcore_we_next_value_ce2 = 1'd0;
-reg           rhs_array_muxed0 = 1'd0;
-reg    [14:0] rhs_array_muxed1 = 15'd0;
-reg     [2:0] rhs_array_muxed2 = 3'd0;
-reg           rhs_array_muxed3 = 1'd0;
-reg           rhs_array_muxed4 = 1'd0;
-reg           rhs_array_muxed5 = 1'd0;
-reg           t_array_muxed0 = 1'd0;
-reg           t_array_muxed1 = 1'd0;
-reg           t_array_muxed2 = 1'd0;
-reg           rhs_array_muxed6 = 1'd0;
-reg    [14:0] rhs_array_muxed7 = 15'd0;
-reg     [2:0] rhs_array_muxed8 = 3'd0;
-reg           rhs_array_muxed9 = 1'd0;
-reg           rhs_array_muxed10 = 1'd0;
-reg           rhs_array_muxed11 = 1'd0;
-reg           t_array_muxed3 = 1'd0;
-reg           t_array_muxed4 = 1'd0;
-reg           t_array_muxed5 = 1'd0;
-reg    [21:0] rhs_array_muxed12 = 22'd0;
-reg           rhs_array_muxed13 = 1'd0;
-reg           rhs_array_muxed14 = 1'd0;
-reg    [21:0] rhs_array_muxed15 = 22'd0;
-reg           rhs_array_muxed16 = 1'd0;
-reg           rhs_array_muxed17 = 1'd0;
-reg    [21:0] rhs_array_muxed18 = 22'd0;
-reg           rhs_array_muxed19 = 1'd0;
-reg           rhs_array_muxed20 = 1'd0;
-reg    [21:0] rhs_array_muxed21 = 22'd0;
-reg           rhs_array_muxed22 = 1'd0;
-reg           rhs_array_muxed23 = 1'd0;
-reg    [21:0] rhs_array_muxed24 = 22'd0;
-reg           rhs_array_muxed25 = 1'd0;
-reg           rhs_array_muxed26 = 1'd0;
-reg    [21:0] rhs_array_muxed27 = 22'd0;
-reg           rhs_array_muxed28 = 1'd0;
-reg           rhs_array_muxed29 = 1'd0;
-reg    [21:0] rhs_array_muxed30 = 22'd0;
-reg           rhs_array_muxed31 = 1'd0;
-reg           rhs_array_muxed32 = 1'd0;
-reg    [21:0] rhs_array_muxed33 = 22'd0;
-reg           rhs_array_muxed34 = 1'd0;
-reg           rhs_array_muxed35 = 1'd0;
-reg     [2:0] array_muxed0 = 3'd0;
-reg    [14:0] array_muxed1 = 15'd0;
-reg           array_muxed2 = 1'd0;
-reg           array_muxed3 = 1'd0;
-reg           array_muxed4 = 1'd0;
-reg           array_muxed5 = 1'd0;
-reg           array_muxed6 = 1'd0;
-reg     [2:0] array_muxed7 = 3'd0;
-reg    [14:0] array_muxed8 = 15'd0;
-reg           array_muxed9 = 1'd0;
-reg           array_muxed10 = 1'd0;
-reg           array_muxed11 = 1'd0;
-reg           array_muxed12 = 1'd0;
-reg           array_muxed13 = 1'd0;
-reg     [2:0] array_muxed14 = 3'd0;
-reg    [14:0] array_muxed15 = 15'd0;
-reg           array_muxed16 = 1'd0;
-reg           array_muxed17 = 1'd0;
-reg           array_muxed18 = 1'd0;
-reg           array_muxed19 = 1'd0;
-reg           array_muxed20 = 1'd0;
-reg     [2:0] array_muxed21 = 3'd0;
-reg    [14:0] array_muxed22 = 15'd0;
-reg           array_muxed23 = 1'd0;
-reg           array_muxed24 = 1'd0;
-reg           array_muxed25 = 1'd0;
-reg           array_muxed26 = 1'd0;
-reg           array_muxed27 = 1'd0;
-wire          xilinxasyncresetsynchronizerimpl0;
-wire          xilinxasyncresetsynchronizerimpl0_rst_meta;
-wire          xilinxasyncresetsynchronizerimpl1;
-wire          xilinxasyncresetsynchronizerimpl1_rst_meta;
-wire          xilinxasyncresetsynchronizerimpl2;
-wire          xilinxasyncresetsynchronizerimpl2_rst_meta;
-wire          xilinxasyncresetsynchronizerimpl2_expr;
-wire          xilinxasyncresetsynchronizerimpl3;
-wire          xilinxasyncresetsynchronizerimpl3_rst_meta;
-wire          xilinxasyncresetsynchronizerimpl3_expr;
+reg           main_litedramcore_twtrcon_ready = 1'd0;
+wire          main_litedramcore_twtrcon_valid;
+wire          main_litedramcore_wants_refresh;
+wire          main_litedramcore_wants_zqcs;
+wire          main_litedramcore_write_available;
+reg           main_litedramcore_zqcs_executer_done = 1'd0;
+reg           main_litedramcore_zqcs_executer_start = 1'd0;
+reg     [4:0] main_litedramcore_zqcs_executer_trigger = 5'd0;
+wire   [26:0] main_litedramcore_zqcs_timer_count0;
+reg    [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999;
+wire          main_litedramcore_zqcs_timer_done0;
+wire          main_litedramcore_zqcs_timer_done1;
+wire          main_litedramcore_zqcs_timer_wait;
+wire          main_locked;
+reg           main_power_down = 1'd0;
+wire          main_reset;
+reg     [3:0] main_reset_counter = 4'd15;
+reg           main_rst = 1'd0;
+wire          main_user_enable;
+wire   [24:0] main_user_port_cmd_payload_addr;
+wire          main_user_port_cmd_payload_we;
+wire          main_user_port_cmd_ready;
+wire          main_user_port_cmd_valid;
+wire  [127:0] main_user_port_rdata_payload_data;
+wire          main_user_port_rdata_ready;
+wire          main_user_port_rdata_valid;
+wire  [127:0] main_user_port_wdata_payload_data;
+wire   [15:0] main_user_port_wdata_payload_we;
+wire          main_user_port_wdata_ready;
+wire          main_user_port_wdata_valid;
+wire          main_wb_bus_ack;
+wire   [29:0] main_wb_bus_adr;
+wire    [1:0] main_wb_bus_bte;
+wire    [2:0] main_wb_bus_cti;
+wire          main_wb_bus_cyc;
+wire   [31:0] main_wb_bus_dat_r;
+wire   [31:0] main_wb_bus_dat_w;
+wire          main_wb_bus_err;
+wire    [3:0] main_wb_bus_sel;
+wire          main_wb_bus_stb;
+wire          main_wb_bus_we;
+wire          sys4x_clk;
+wire          sys4x_dqs_clk;
+wire          sys_clk;
+wire          sys_rst;
 
 //------------------------------------------------------------------------------
 // Combinatorial Logic
 //------------------------------------------------------------------------------
 
-assign init_done = init_done_storage;
-assign init_error = init_error_storage;
-assign wb_bus_adr = wb_ctrl_adr;
-assign wb_bus_dat_w = wb_ctrl_dat_w;
-assign wb_ctrl_dat_r = wb_bus_dat_r;
-assign wb_bus_sel = wb_ctrl_sel;
-assign wb_bus_cyc = wb_ctrl_cyc;
-assign wb_bus_stb = wb_ctrl_stb;
-assign wb_ctrl_ack = wb_bus_ack;
-assign wb_bus_we = wb_ctrl_we;
-assign wb_bus_cti = wb_ctrl_cti;
-assign wb_bus_bte = wb_ctrl_bte;
-assign wb_ctrl_err = wb_bus_err;
+assign init_done = main_init_done_storage;
+assign init_error = main_init_error_storage;
+assign main_wb_bus_adr = wb_ctrl_adr;
+assign main_wb_bus_dat_w = wb_ctrl_dat_w;
+assign wb_ctrl_dat_r = main_wb_bus_dat_r;
+assign main_wb_bus_sel = wb_ctrl_sel;
+assign main_wb_bus_cyc = wb_ctrl_cyc;
+assign main_wb_bus_stb = wb_ctrl_stb;
+assign wb_ctrl_ack = main_wb_bus_ack;
+assign main_wb_bus_we = wb_ctrl_we;
+assign main_wb_bus_cti = wb_ctrl_cti;
+assign main_wb_bus_bte = wb_ctrl_bte;
+assign wb_ctrl_err = main_wb_bus_err;
 assign user_clk = sys_clk;
 assign user_rst = sys_rst;
-assign user_enable = 1'd1;
-assign user_port_cmd_valid = (user_port_native_0_cmd_valid & user_enable);
-assign user_port_native_0_cmd_ready = (user_port_cmd_ready & user_enable);
-assign user_port_cmd_payload_we = user_port_native_0_cmd_we;
-assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
-assign user_port_wdata_valid = (user_port_native_0_wdata_valid & user_enable);
-assign user_port_native_0_wdata_ready = (user_port_wdata_ready & user_enable);
-assign user_port_wdata_payload_we = user_port_native_0_wdata_we;
-assign user_port_wdata_payload_data = user_port_native_0_wdata_data;
-assign user_port_native_0_rdata_valid = (user_port_rdata_valid & user_enable);
-assign user_port_rdata_ready = (user_port_native_0_rdata_ready & user_enable);
-assign user_port_native_0_rdata_data = user_port_rdata_payload_data;
-assign reset = (rst | rst_1);
-assign pll_locked = locked;
-assign clkin = clk;
-assign iodelay_clk = clkout_buf0;
-assign sys_clk = clkout_buf1;
-assign sys4x_clk = clkout_buf2;
-assign sys4x_dqs_clk = clkout_buf3;
-assign ddram_ba = a7ddrphy_pads_ba;
-assign a7ddrphy_dqs_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dqs_oe) | a7ddrphy_dqs_postamble);
-assign a7ddrphy_dq_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dq_oe) | a7ddrphy_dqs_postamble);
-always @(*) begin
-    a7ddrphy_dfi_p0_rddata <= 32'd0;
-    a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0];
-    a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1];
-    a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0];
-    a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1];
-    a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0];
-    a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1];
-    a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0];
-    a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1];
-    a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0];
-    a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1];
-    a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0];
-    a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1];
-    a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0];
-    a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1];
-    a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0];
-    a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1];
-    a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0];
-    a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1];
-    a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0];
-    a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1];
-    a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0];
-    a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1];
-    a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0];
-    a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1];
-    a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0];
-    a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1];
-    a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0];
-    a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1];
-    a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0];
-    a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1];
-    a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0];
-    a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1];
-end
-always @(*) begin
-    a7ddrphy_dfi_p1_rddata <= 32'd0;
-    a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2];
-    a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3];
-    a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2];
-    a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3];
-    a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2];
-    a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3];
-    a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2];
-    a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3];
-    a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2];
-    a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3];
-    a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2];
-    a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3];
-    a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2];
-    a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3];
-    a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2];
-    a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3];
-    a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2];
-    a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3];
-    a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2];
-    a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3];
-    a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2];
-    a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3];
-    a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2];
-    a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3];
-    a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2];
-    a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3];
-    a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2];
-    a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3];
-    a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2];
-    a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3];
-    a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2];
-    a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3];
-end
-always @(*) begin
-    a7ddrphy_dfi_p2_rddata <= 32'd0;
-    a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4];
-    a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5];
-    a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4];
-    a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5];
-    a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4];
-    a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5];
-    a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4];
-    a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5];
-    a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4];
-    a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5];
-    a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4];
-    a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5];
-    a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4];
-    a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5];
-    a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4];
-    a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5];
-    a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4];
-    a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5];
-    a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4];
-    a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5];
-    a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4];
-    a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5];
-    a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4];
-    a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5];
-    a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4];
-    a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5];
-    a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4];
-    a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5];
-    a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4];
-    a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5];
-    a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4];
-    a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5];
-end
-always @(*) begin
-    a7ddrphy_dfi_p3_rddata <= 32'd0;
-    a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6];
-    a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7];
-    a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6];
-    a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7];
-    a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6];
-    a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7];
-    a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6];
-    a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7];
-    a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6];
-    a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7];
-    a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6];
-    a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7];
-    a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6];
-    a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7];
-    a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6];
-    a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7];
-    a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6];
-    a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7];
-    a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6];
-    a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7];
-    a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6];
-    a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7];
-    a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6];
-    a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7];
-    a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6];
-    a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7];
-    a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6];
-    a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7];
-    a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6];
-    a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7];
-    a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6];
-    a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7];
-end
-assign a7ddrphy_dfi_p0_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
-assign a7ddrphy_dfi_p1_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
-assign a7ddrphy_dfi_p2_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
-assign a7ddrphy_dfi_p3_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
-assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en_tappeddelayline1;
-always @(*) begin
-    a7ddrphy_dqs_oe <= 1'd0;
-    if (a7ddrphy_wlevel_en_storage) begin
-        a7ddrphy_dqs_oe <= 1'd1;
-    end else begin
-        a7ddrphy_dqs_oe <= a7ddrphy_dq_oe;
-    end
-end
-assign a7ddrphy_dqs_preamble = (a7ddrphy_wrdata_en_tappeddelayline0 & (~a7ddrphy_wrdata_en_tappeddelayline1));
-assign a7ddrphy_dqs_postamble = (a7ddrphy_wrdata_en_tappeddelayline2 & (~a7ddrphy_wrdata_en_tappeddelayline1));
-always @(*) begin
-    a7ddrphy_dqspattern_o0 <= 8'd0;
-    a7ddrphy_dqspattern_o0 <= 7'd85;
-    if (a7ddrphy_dqspattern0) begin
-        a7ddrphy_dqspattern_o0 <= 5'd21;
-    end
-    if (a7ddrphy_dqspattern1) begin
-        a7ddrphy_dqspattern_o0 <= 7'd84;
-    end
-    if (a7ddrphy_wlevel_en_storage) begin
-        a7ddrphy_dqspattern_o0 <= 1'd0;
-        if (a7ddrphy_wlevel_strobe_re) begin
-            a7ddrphy_dqspattern_o0 <= 1'd1;
-        end
-    end
-end
-always @(*) begin
-    a7ddrphy_bitslip00 <= 8'd0;
-    case (a7ddrphy_bitslip0_value0)
+assign main_user_enable = 1'd1;
+assign main_user_port_cmd_valid = (user_port_native_0_cmd_valid & main_user_enable);
+assign user_port_native_0_cmd_ready = (main_user_port_cmd_ready & main_user_enable);
+assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we;
+assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
+assign main_user_port_wdata_valid = (user_port_native_0_wdata_valid & main_user_enable);
+assign user_port_native_0_wdata_ready = (main_user_port_wdata_ready & main_user_enable);
+assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we;
+assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data;
+assign user_port_native_0_rdata_valid = (main_user_port_rdata_valid & main_user_enable);
+assign main_user_port_rdata_ready = (user_port_native_0_rdata_ready & main_user_enable);
+assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data;
+assign builder_interface0_adr = main_wb_bus_adr;
+assign builder_interface0_dat_w = main_wb_bus_dat_w;
+assign main_wb_bus_dat_r = builder_interface0_dat_r;
+assign builder_interface0_sel = main_wb_bus_sel;
+assign builder_interface0_cyc = main_wb_bus_cyc;
+assign builder_interface0_stb = main_wb_bus_stb;
+assign main_wb_bus_ack = builder_interface0_ack;
+assign builder_interface0_we = main_wb_bus_we;
+assign builder_interface0_cti = main_wb_bus_cti;
+assign builder_interface0_bte = main_wb_bus_bte;
+assign main_wb_bus_err = builder_interface0_err;
+assign main_reset = (rst | main_rst);
+assign pll_locked = main_locked;
+assign main_clkin = clk;
+assign iodelay_clk = main_clkout_buf0;
+assign sys_clk = main_clkout_buf1;
+assign sys4x_clk = main_clkout_buf2;
+assign sys4x_dqs_clk = main_clkout_buf3;
+assign ddram_ba = main_a7ddrphy_pads_ba;
+assign main_a7ddrphy_dqs_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_oe) | main_a7ddrphy_dqs_postamble);
+assign main_a7ddrphy_dq_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dq_oe) | main_a7ddrphy_dqs_postamble);
+always @(*) begin
+    main_a7ddrphy_dfi_p0_rddata <= 32'd0;
+    main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip04[0];
+    main_a7ddrphy_dfi_p0_rddata[16] <= main_a7ddrphy_bitslip04[1];
+    main_a7ddrphy_dfi_p0_rddata[1] <= main_a7ddrphy_bitslip14[0];
+    main_a7ddrphy_dfi_p0_rddata[17] <= main_a7ddrphy_bitslip14[1];
+    main_a7ddrphy_dfi_p0_rddata[2] <= main_a7ddrphy_bitslip22[0];
+    main_a7ddrphy_dfi_p0_rddata[18] <= main_a7ddrphy_bitslip22[1];
+    main_a7ddrphy_dfi_p0_rddata[3] <= main_a7ddrphy_bitslip32[0];
+    main_a7ddrphy_dfi_p0_rddata[19] <= main_a7ddrphy_bitslip32[1];
+    main_a7ddrphy_dfi_p0_rddata[4] <= main_a7ddrphy_bitslip42[0];
+    main_a7ddrphy_dfi_p0_rddata[20] <= main_a7ddrphy_bitslip42[1];
+    main_a7ddrphy_dfi_p0_rddata[5] <= main_a7ddrphy_bitslip52[0];
+    main_a7ddrphy_dfi_p0_rddata[21] <= main_a7ddrphy_bitslip52[1];
+    main_a7ddrphy_dfi_p0_rddata[6] <= main_a7ddrphy_bitslip62[0];
+    main_a7ddrphy_dfi_p0_rddata[22] <= main_a7ddrphy_bitslip62[1];
+    main_a7ddrphy_dfi_p0_rddata[7] <= main_a7ddrphy_bitslip72[0];
+    main_a7ddrphy_dfi_p0_rddata[23] <= main_a7ddrphy_bitslip72[1];
+    main_a7ddrphy_dfi_p0_rddata[8] <= main_a7ddrphy_bitslip82[0];
+    main_a7ddrphy_dfi_p0_rddata[24] <= main_a7ddrphy_bitslip82[1];
+    main_a7ddrphy_dfi_p0_rddata[9] <= main_a7ddrphy_bitslip92[0];
+    main_a7ddrphy_dfi_p0_rddata[25] <= main_a7ddrphy_bitslip92[1];
+    main_a7ddrphy_dfi_p0_rddata[10] <= main_a7ddrphy_bitslip102[0];
+    main_a7ddrphy_dfi_p0_rddata[26] <= main_a7ddrphy_bitslip102[1];
+    main_a7ddrphy_dfi_p0_rddata[11] <= main_a7ddrphy_bitslip112[0];
+    main_a7ddrphy_dfi_p0_rddata[27] <= main_a7ddrphy_bitslip112[1];
+    main_a7ddrphy_dfi_p0_rddata[12] <= main_a7ddrphy_bitslip122[0];
+    main_a7ddrphy_dfi_p0_rddata[28] <= main_a7ddrphy_bitslip122[1];
+    main_a7ddrphy_dfi_p0_rddata[13] <= main_a7ddrphy_bitslip132[0];
+    main_a7ddrphy_dfi_p0_rddata[29] <= main_a7ddrphy_bitslip132[1];
+    main_a7ddrphy_dfi_p0_rddata[14] <= main_a7ddrphy_bitslip142[0];
+    main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip142[1];
+    main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip152[0];
+    main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip152[1];
+end
+always @(*) begin
+    main_a7ddrphy_dfi_p1_rddata <= 32'd0;
+    main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip04[2];
+    main_a7ddrphy_dfi_p1_rddata[16] <= main_a7ddrphy_bitslip04[3];
+    main_a7ddrphy_dfi_p1_rddata[1] <= main_a7ddrphy_bitslip14[2];
+    main_a7ddrphy_dfi_p1_rddata[17] <= main_a7ddrphy_bitslip14[3];
+    main_a7ddrphy_dfi_p1_rddata[2] <= main_a7ddrphy_bitslip22[2];
+    main_a7ddrphy_dfi_p1_rddata[18] <= main_a7ddrphy_bitslip22[3];
+    main_a7ddrphy_dfi_p1_rddata[3] <= main_a7ddrphy_bitslip32[2];
+    main_a7ddrphy_dfi_p1_rddata[19] <= main_a7ddrphy_bitslip32[3];
+    main_a7ddrphy_dfi_p1_rddata[4] <= main_a7ddrphy_bitslip42[2];
+    main_a7ddrphy_dfi_p1_rddata[20] <= main_a7ddrphy_bitslip42[3];
+    main_a7ddrphy_dfi_p1_rddata[5] <= main_a7ddrphy_bitslip52[2];
+    main_a7ddrphy_dfi_p1_rddata[21] <= main_a7ddrphy_bitslip52[3];
+    main_a7ddrphy_dfi_p1_rddata[6] <= main_a7ddrphy_bitslip62[2];
+    main_a7ddrphy_dfi_p1_rddata[22] <= main_a7ddrphy_bitslip62[3];
+    main_a7ddrphy_dfi_p1_rddata[7] <= main_a7ddrphy_bitslip72[2];
+    main_a7ddrphy_dfi_p1_rddata[23] <= main_a7ddrphy_bitslip72[3];
+    main_a7ddrphy_dfi_p1_rddata[8] <= main_a7ddrphy_bitslip82[2];
+    main_a7ddrphy_dfi_p1_rddata[24] <= main_a7ddrphy_bitslip82[3];
+    main_a7ddrphy_dfi_p1_rddata[9] <= main_a7ddrphy_bitslip92[2];
+    main_a7ddrphy_dfi_p1_rddata[25] <= main_a7ddrphy_bitslip92[3];
+    main_a7ddrphy_dfi_p1_rddata[10] <= main_a7ddrphy_bitslip102[2];
+    main_a7ddrphy_dfi_p1_rddata[26] <= main_a7ddrphy_bitslip102[3];
+    main_a7ddrphy_dfi_p1_rddata[11] <= main_a7ddrphy_bitslip112[2];
+    main_a7ddrphy_dfi_p1_rddata[27] <= main_a7ddrphy_bitslip112[3];
+    main_a7ddrphy_dfi_p1_rddata[12] <= main_a7ddrphy_bitslip122[2];
+    main_a7ddrphy_dfi_p1_rddata[28] <= main_a7ddrphy_bitslip122[3];
+    main_a7ddrphy_dfi_p1_rddata[13] <= main_a7ddrphy_bitslip132[2];
+    main_a7ddrphy_dfi_p1_rddata[29] <= main_a7ddrphy_bitslip132[3];
+    main_a7ddrphy_dfi_p1_rddata[14] <= main_a7ddrphy_bitslip142[2];
+    main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip142[3];
+    main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip152[2];
+    main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip152[3];
+end
+always @(*) begin
+    main_a7ddrphy_dfi_p2_rddata <= 32'd0;
+    main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip04[4];
+    main_a7ddrphy_dfi_p2_rddata[16] <= main_a7ddrphy_bitslip04[5];
+    main_a7ddrphy_dfi_p2_rddata[1] <= main_a7ddrphy_bitslip14[4];
+    main_a7ddrphy_dfi_p2_rddata[17] <= main_a7ddrphy_bitslip14[5];
+    main_a7ddrphy_dfi_p2_rddata[2] <= main_a7ddrphy_bitslip22[4];
+    main_a7ddrphy_dfi_p2_rddata[18] <= main_a7ddrphy_bitslip22[5];
+    main_a7ddrphy_dfi_p2_rddata[3] <= main_a7ddrphy_bitslip32[4];
+    main_a7ddrphy_dfi_p2_rddata[19] <= main_a7ddrphy_bitslip32[5];
+    main_a7ddrphy_dfi_p2_rddata[4] <= main_a7ddrphy_bitslip42[4];
+    main_a7ddrphy_dfi_p2_rddata[20] <= main_a7ddrphy_bitslip42[5];
+    main_a7ddrphy_dfi_p2_rddata[5] <= main_a7ddrphy_bitslip52[4];
+    main_a7ddrphy_dfi_p2_rddata[21] <= main_a7ddrphy_bitslip52[5];
+    main_a7ddrphy_dfi_p2_rddata[6] <= main_a7ddrphy_bitslip62[4];
+    main_a7ddrphy_dfi_p2_rddata[22] <= main_a7ddrphy_bitslip62[5];
+    main_a7ddrphy_dfi_p2_rddata[7] <= main_a7ddrphy_bitslip72[4];
+    main_a7ddrphy_dfi_p2_rddata[23] <= main_a7ddrphy_bitslip72[5];
+    main_a7ddrphy_dfi_p2_rddata[8] <= main_a7ddrphy_bitslip82[4];
+    main_a7ddrphy_dfi_p2_rddata[24] <= main_a7ddrphy_bitslip82[5];
+    main_a7ddrphy_dfi_p2_rddata[9] <= main_a7ddrphy_bitslip92[4];
+    main_a7ddrphy_dfi_p2_rddata[25] <= main_a7ddrphy_bitslip92[5];
+    main_a7ddrphy_dfi_p2_rddata[10] <= main_a7ddrphy_bitslip102[4];
+    main_a7ddrphy_dfi_p2_rddata[26] <= main_a7ddrphy_bitslip102[5];
+    main_a7ddrphy_dfi_p2_rddata[11] <= main_a7ddrphy_bitslip112[4];
+    main_a7ddrphy_dfi_p2_rddata[27] <= main_a7ddrphy_bitslip112[5];
+    main_a7ddrphy_dfi_p2_rddata[12] <= main_a7ddrphy_bitslip122[4];
+    main_a7ddrphy_dfi_p2_rddata[28] <= main_a7ddrphy_bitslip122[5];
+    main_a7ddrphy_dfi_p2_rddata[13] <= main_a7ddrphy_bitslip132[4];
+    main_a7ddrphy_dfi_p2_rddata[29] <= main_a7ddrphy_bitslip132[5];
+    main_a7ddrphy_dfi_p2_rddata[14] <= main_a7ddrphy_bitslip142[4];
+    main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip142[5];
+    main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip152[4];
+    main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip152[5];
+end
+always @(*) begin
+    main_a7ddrphy_dfi_p3_rddata <= 32'd0;
+    main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip04[6];
+    main_a7ddrphy_dfi_p3_rddata[16] <= main_a7ddrphy_bitslip04[7];
+    main_a7ddrphy_dfi_p3_rddata[1] <= main_a7ddrphy_bitslip14[6];
+    main_a7ddrphy_dfi_p3_rddata[17] <= main_a7ddrphy_bitslip14[7];
+    main_a7ddrphy_dfi_p3_rddata[2] <= main_a7ddrphy_bitslip22[6];
+    main_a7ddrphy_dfi_p3_rddata[18] <= main_a7ddrphy_bitslip22[7];
+    main_a7ddrphy_dfi_p3_rddata[3] <= main_a7ddrphy_bitslip32[6];
+    main_a7ddrphy_dfi_p3_rddata[19] <= main_a7ddrphy_bitslip32[7];
+    main_a7ddrphy_dfi_p3_rddata[4] <= main_a7ddrphy_bitslip42[6];
+    main_a7ddrphy_dfi_p3_rddata[20] <= main_a7ddrphy_bitslip42[7];
+    main_a7ddrphy_dfi_p3_rddata[5] <= main_a7ddrphy_bitslip52[6];
+    main_a7ddrphy_dfi_p3_rddata[21] <= main_a7ddrphy_bitslip52[7];
+    main_a7ddrphy_dfi_p3_rddata[6] <= main_a7ddrphy_bitslip62[6];
+    main_a7ddrphy_dfi_p3_rddata[22] <= main_a7ddrphy_bitslip62[7];
+    main_a7ddrphy_dfi_p3_rddata[7] <= main_a7ddrphy_bitslip72[6];
+    main_a7ddrphy_dfi_p3_rddata[23] <= main_a7ddrphy_bitslip72[7];
+    main_a7ddrphy_dfi_p3_rddata[8] <= main_a7ddrphy_bitslip82[6];
+    main_a7ddrphy_dfi_p3_rddata[24] <= main_a7ddrphy_bitslip82[7];
+    main_a7ddrphy_dfi_p3_rddata[9] <= main_a7ddrphy_bitslip92[6];
+    main_a7ddrphy_dfi_p3_rddata[25] <= main_a7ddrphy_bitslip92[7];
+    main_a7ddrphy_dfi_p3_rddata[10] <= main_a7ddrphy_bitslip102[6];
+    main_a7ddrphy_dfi_p3_rddata[26] <= main_a7ddrphy_bitslip102[7];
+    main_a7ddrphy_dfi_p3_rddata[11] <= main_a7ddrphy_bitslip112[6];
+    main_a7ddrphy_dfi_p3_rddata[27] <= main_a7ddrphy_bitslip112[7];
+    main_a7ddrphy_dfi_p3_rddata[12] <= main_a7ddrphy_bitslip122[6];
+    main_a7ddrphy_dfi_p3_rddata[28] <= main_a7ddrphy_bitslip122[7];
+    main_a7ddrphy_dfi_p3_rddata[13] <= main_a7ddrphy_bitslip132[6];
+    main_a7ddrphy_dfi_p3_rddata[29] <= main_a7ddrphy_bitslip132[7];
+    main_a7ddrphy_dfi_p3_rddata[14] <= main_a7ddrphy_bitslip142[6];
+    main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip142[7];
+    main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip152[6];
+    main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip152[7];
+end
+assign main_a7ddrphy_dfi_p0_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
+assign main_a7ddrphy_dfi_p1_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
+assign main_a7ddrphy_dfi_p2_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
+assign main_a7ddrphy_dfi_p3_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
+assign main_a7ddrphy_dq_oe = main_a7ddrphy_wrdata_en_tappeddelayline1;
+always @(*) begin
+    main_a7ddrphy_dqs_oe <= 1'd0;
+    if (main_a7ddrphy_wlevel_en_storage) begin
+        main_a7ddrphy_dqs_oe <= 1'd1;
+    end else begin
+        main_a7ddrphy_dqs_oe <= main_a7ddrphy_dq_oe;
+    end
+end
+assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_wrdata_en_tappeddelayline0 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
+assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_wrdata_en_tappeddelayline2 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
+always @(*) begin
+    main_a7ddrphy_dqspattern_o0 <= 8'd0;
+    main_a7ddrphy_dqspattern_o0 <= 7'd85;
+    if (main_a7ddrphy_dqspattern0) begin
+        main_a7ddrphy_dqspattern_o0 <= 5'd21;
+    end
+    if (main_a7ddrphy_dqspattern1) begin
+        main_a7ddrphy_dqspattern_o0 <= 7'd84;
+    end
+    if (main_a7ddrphy_wlevel_en_storage) begin
+        main_a7ddrphy_dqspattern_o0 <= 1'd0;
+        if (main_a7ddrphy_wlevel_strobe_re) begin
+            main_a7ddrphy_dqspattern_o0 <= 1'd1;
+        end
+    end
+end
+always @(*) begin
+    main_a7ddrphy_bitslip00 <= 8'd0;
+    case (main_a7ddrphy_bitslip0_value0)
         1'd0: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip10 <= 8'd0;
-    case (a7ddrphy_bitslip1_value0)
+    main_a7ddrphy_bitslip10 <= 8'd0;
+    case (main_a7ddrphy_bitslip1_value0)
         1'd0: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip01 <= 8'd0;
-    case (a7ddrphy_bitslip0_value1)
+    main_a7ddrphy_bitslip01 <= 8'd0;
+    case (main_a7ddrphy_bitslip0_value1)
         1'd0: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip11 <= 8'd0;
-    case (a7ddrphy_bitslip1_value1)
+    main_a7ddrphy_bitslip11 <= 8'd0;
+    case (main_a7ddrphy_bitslip1_value1)
         1'd0: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip02 <= 8'd0;
-    case (a7ddrphy_bitslip0_value2)
+    main_a7ddrphy_bitslip02 <= 8'd0;
+    case (main_a7ddrphy_bitslip0_value2)
         1'd0: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip04 <= 8'd0;
-    case (a7ddrphy_bitslip0_value3)
+    main_a7ddrphy_bitslip04 <= 8'd0;
+    case (main_a7ddrphy_bitslip0_value3)
         1'd0: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip12 <= 8'd0;
-    case (a7ddrphy_bitslip1_value2)
+    main_a7ddrphy_bitslip12 <= 8'd0;
+    case (main_a7ddrphy_bitslip1_value2)
         1'd0: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip14 <= 8'd0;
-    case (a7ddrphy_bitslip1_value3)
+    main_a7ddrphy_bitslip14 <= 8'd0;
+    case (main_a7ddrphy_bitslip1_value3)
         1'd0: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip20 <= 8'd0;
-    case (a7ddrphy_bitslip2_value0)
+    main_a7ddrphy_bitslip20 <= 8'd0;
+    case (main_a7ddrphy_bitslip2_value0)
         1'd0: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip22 <= 8'd0;
-    case (a7ddrphy_bitslip2_value1)
+    main_a7ddrphy_bitslip22 <= 8'd0;
+    case (main_a7ddrphy_bitslip2_value1)
         1'd0: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip30 <= 8'd0;
-    case (a7ddrphy_bitslip3_value0)
+    main_a7ddrphy_bitslip30 <= 8'd0;
+    case (main_a7ddrphy_bitslip3_value0)
         1'd0: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip32 <= 8'd0;
-    case (a7ddrphy_bitslip3_value1)
+    main_a7ddrphy_bitslip32 <= 8'd0;
+    case (main_a7ddrphy_bitslip3_value1)
         1'd0: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip40 <= 8'd0;
-    case (a7ddrphy_bitslip4_value0)
+    main_a7ddrphy_bitslip40 <= 8'd0;
+    case (main_a7ddrphy_bitslip4_value0)
         1'd0: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip42 <= 8'd0;
-    case (a7ddrphy_bitslip4_value1)
+    main_a7ddrphy_bitslip42 <= 8'd0;
+    case (main_a7ddrphy_bitslip4_value1)
         1'd0: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip50 <= 8'd0;
-    case (a7ddrphy_bitslip5_value0)
+    main_a7ddrphy_bitslip50 <= 8'd0;
+    case (main_a7ddrphy_bitslip5_value0)
         1'd0: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip52 <= 8'd0;
-    case (a7ddrphy_bitslip5_value1)
+    main_a7ddrphy_bitslip52 <= 8'd0;
+    case (main_a7ddrphy_bitslip5_value1)
         1'd0: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip60 <= 8'd0;
-    case (a7ddrphy_bitslip6_value0)
+    main_a7ddrphy_bitslip60 <= 8'd0;
+    case (main_a7ddrphy_bitslip6_value0)
         1'd0: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip62 <= 8'd0;
-    case (a7ddrphy_bitslip6_value1)
+    main_a7ddrphy_bitslip62 <= 8'd0;
+    case (main_a7ddrphy_bitslip6_value1)
         1'd0: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip70 <= 8'd0;
-    case (a7ddrphy_bitslip7_value0)
+    main_a7ddrphy_bitslip70 <= 8'd0;
+    case (main_a7ddrphy_bitslip7_value0)
         1'd0: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip72 <= 8'd0;
-    case (a7ddrphy_bitslip7_value1)
+    main_a7ddrphy_bitslip72 <= 8'd0;
+    case (main_a7ddrphy_bitslip7_value1)
         1'd0: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip80 <= 8'd0;
-    case (a7ddrphy_bitslip8_value0)
+    main_a7ddrphy_bitslip80 <= 8'd0;
+    case (main_a7ddrphy_bitslip8_value0)
         1'd0: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip82 <= 8'd0;
-    case (a7ddrphy_bitslip8_value1)
+    main_a7ddrphy_bitslip82 <= 8'd0;
+    case (main_a7ddrphy_bitslip8_value1)
         1'd0: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip90 <= 8'd0;
-    case (a7ddrphy_bitslip9_value0)
+    main_a7ddrphy_bitslip90 <= 8'd0;
+    case (main_a7ddrphy_bitslip9_value0)
         1'd0: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip92 <= 8'd0;
-    case (a7ddrphy_bitslip9_value1)
+    main_a7ddrphy_bitslip92 <= 8'd0;
+    case (main_a7ddrphy_bitslip9_value1)
         1'd0: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip100 <= 8'd0;
-    case (a7ddrphy_bitslip10_value0)
+    main_a7ddrphy_bitslip100 <= 8'd0;
+    case (main_a7ddrphy_bitslip10_value0)
         1'd0: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip102 <= 8'd0;
-    case (a7ddrphy_bitslip10_value1)
+    main_a7ddrphy_bitslip102 <= 8'd0;
+    case (main_a7ddrphy_bitslip10_value1)
         1'd0: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip110 <= 8'd0;
-    case (a7ddrphy_bitslip11_value0)
+    main_a7ddrphy_bitslip110 <= 8'd0;
+    case (main_a7ddrphy_bitslip11_value0)
         1'd0: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip112 <= 8'd0;
-    case (a7ddrphy_bitslip11_value1)
+    main_a7ddrphy_bitslip112 <= 8'd0;
+    case (main_a7ddrphy_bitslip11_value1)
         1'd0: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip120 <= 8'd0;
-    case (a7ddrphy_bitslip12_value0)
+    main_a7ddrphy_bitslip120 <= 8'd0;
+    case (main_a7ddrphy_bitslip12_value0)
         1'd0: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip122 <= 8'd0;
-    case (a7ddrphy_bitslip12_value1)
+    main_a7ddrphy_bitslip122 <= 8'd0;
+    case (main_a7ddrphy_bitslip12_value1)
         1'd0: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip130 <= 8'd0;
-    case (a7ddrphy_bitslip13_value0)
+    main_a7ddrphy_bitslip130 <= 8'd0;
+    case (main_a7ddrphy_bitslip13_value0)
         1'd0: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip132 <= 8'd0;
-    case (a7ddrphy_bitslip13_value1)
+    main_a7ddrphy_bitslip132 <= 8'd0;
+    case (main_a7ddrphy_bitslip13_value1)
         1'd0: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip140 <= 8'd0;
-    case (a7ddrphy_bitslip14_value0)
+    main_a7ddrphy_bitslip140 <= 8'd0;
+    case (main_a7ddrphy_bitslip14_value0)
         1'd0: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip142 <= 8'd0;
-    case (a7ddrphy_bitslip14_value1)
+    main_a7ddrphy_bitslip142 <= 8'd0;
+    case (main_a7ddrphy_bitslip14_value1)
         1'd0: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip150 <= 8'd0;
-    case (a7ddrphy_bitslip15_value0)
+    main_a7ddrphy_bitslip150 <= 8'd0;
+    case (main_a7ddrphy_bitslip15_value0)
         1'd0: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip152 <= 8'd0;
-    case (a7ddrphy_bitslip15_value1)
+    main_a7ddrphy_bitslip152 <= 8'd0;
+    case (main_a7ddrphy_bitslip15_value1)
         1'd0: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1];
-        end
-        1'd1: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2];
-        end
-        2'd2: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3];
-        end
-        2'd3: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4];
-        end
-        3'd4: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5];
-        end
-        3'd5: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6];
-        end
-        3'd6: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7];
-        end
-        3'd7: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8];
-        end
-    endcase
-end
-assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address;
-assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
-assign a7ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n;
-assign a7ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n;
-assign a7ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n;
-assign a7ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n;
-assign a7ddrphy_dfi_p0_cke = litedramcore_master_p0_cke;
-assign a7ddrphy_dfi_p0_odt = litedramcore_master_p0_odt;
-assign a7ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n;
-assign a7ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n;
-assign a7ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata;
-assign a7ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en;
-assign a7ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask;
-assign a7ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en;
-assign litedramcore_master_p0_rddata = a7ddrphy_dfi_p0_rddata;
-assign litedramcore_master_p0_rddata_valid = a7ddrphy_dfi_p0_rddata_valid;
-assign a7ddrphy_dfi_p1_address = litedramcore_master_p1_address;
-assign a7ddrphy_dfi_p1_bank = litedramcore_master_p1_bank;
-assign a7ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n;
-assign a7ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n;
-assign a7ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n;
-assign a7ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n;
-assign a7ddrphy_dfi_p1_cke = litedramcore_master_p1_cke;
-assign a7ddrphy_dfi_p1_odt = litedramcore_master_p1_odt;
-assign a7ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n;
-assign a7ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n;
-assign a7ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata;
-assign a7ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en;
-assign a7ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask;
-assign a7ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en;
-assign litedramcore_master_p1_rddata = a7ddrphy_dfi_p1_rddata;
-assign litedramcore_master_p1_rddata_valid = a7ddrphy_dfi_p1_rddata_valid;
-assign a7ddrphy_dfi_p2_address = litedramcore_master_p2_address;
-assign a7ddrphy_dfi_p2_bank = litedramcore_master_p2_bank;
-assign a7ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n;
-assign a7ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n;
-assign a7ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n;
-assign a7ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n;
-assign a7ddrphy_dfi_p2_cke = litedramcore_master_p2_cke;
-assign a7ddrphy_dfi_p2_odt = litedramcore_master_p2_odt;
-assign a7ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n;
-assign a7ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n;
-assign a7ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata;
-assign a7ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en;
-assign a7ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask;
-assign a7ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en;
-assign litedramcore_master_p2_rddata = a7ddrphy_dfi_p2_rddata;
-assign litedramcore_master_p2_rddata_valid = a7ddrphy_dfi_p2_rddata_valid;
-assign a7ddrphy_dfi_p3_address = litedramcore_master_p3_address;
-assign a7ddrphy_dfi_p3_bank = litedramcore_master_p3_bank;
-assign a7ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n;
-assign a7ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n;
-assign a7ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n;
-assign a7ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n;
-assign a7ddrphy_dfi_p3_cke = litedramcore_master_p3_cke;
-assign a7ddrphy_dfi_p3_odt = litedramcore_master_p3_odt;
-assign a7ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n;
-assign a7ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n;
-assign a7ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata;
-assign a7ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en;
-assign a7ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask;
-assign a7ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en;
-assign litedramcore_master_p3_rddata = a7ddrphy_dfi_p3_rddata;
-assign litedramcore_master_p3_rddata_valid = a7ddrphy_dfi_p3_rddata_valid;
-assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address;
-assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank;
-assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n;
-assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n;
-assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n;
-assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n;
-assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke;
-assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt;
-assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n;
-assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n;
-assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata;
-assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en;
-assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask;
-assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en;
-assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata;
-assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid;
-assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address;
-assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank;
-assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n;
-assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n;
-assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n;
-assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n;
-assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke;
-assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt;
-assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n;
-assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n;
-assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata;
-assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en;
-assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask;
-assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en;
-assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata;
-assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid;
-assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address;
-assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank;
-assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n;
-assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n;
-assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n;
-assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n;
-assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke;
-assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt;
-assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n;
-assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n;
-assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata;
-assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en;
-assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask;
-assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en;
-assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata;
-assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid;
-assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address;
-assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank;
-assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n;
-assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n;
-assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n;
-assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n;
-assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke;
-assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt;
-assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n;
-assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n;
-assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata;
-assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en;
-assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask;
-assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en;
-assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
-assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;
-always @(*) begin
-    litedramcore_csr_dfi_p0_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-    end else begin
-        litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata;
-    end
-end
-always @(*) begin
-    litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-    end else begin
-        litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
-    end
-end
-always @(*) begin
-    litedramcore_csr_dfi_p1_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-    end else begin
-        litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
-    end
-end
-always @(*) begin
-    litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-    end else begin
-        litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[8:1];
+        end
+        1'd1: begin
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[9:2];
+        end
+        2'd2: begin
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[10:3];
+        end
+        2'd3: begin
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[11:4];
+        end
+        3'd4: begin
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[12:5];
+        end
+        3'd5: begin
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[13:6];
+        end
+        3'd6: begin
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[14:7];
+        end
+        3'd7: begin
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[15:8];
+        end
+    endcase
+end
+assign main_a7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address;
+assign main_a7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank;
+assign main_a7ddrphy_dfi_p0_cas_n = main_litedramcore_master_p0_cas_n;
+assign main_a7ddrphy_dfi_p0_cs_n = main_litedramcore_master_p0_cs_n;
+assign main_a7ddrphy_dfi_p0_ras_n = main_litedramcore_master_p0_ras_n;
+assign main_a7ddrphy_dfi_p0_we_n = main_litedramcore_master_p0_we_n;
+assign main_a7ddrphy_dfi_p0_cke = main_litedramcore_master_p0_cke;
+assign main_a7ddrphy_dfi_p0_odt = main_litedramcore_master_p0_odt;
+assign main_a7ddrphy_dfi_p0_reset_n = main_litedramcore_master_p0_reset_n;
+assign main_a7ddrphy_dfi_p0_act_n = main_litedramcore_master_p0_act_n;
+assign main_a7ddrphy_dfi_p0_wrdata = main_litedramcore_master_p0_wrdata;
+assign main_a7ddrphy_dfi_p0_wrdata_en = main_litedramcore_master_p0_wrdata_en;
+assign main_a7ddrphy_dfi_p0_wrdata_mask = main_litedramcore_master_p0_wrdata_mask;
+assign main_a7ddrphy_dfi_p0_rddata_en = main_litedramcore_master_p0_rddata_en;
+assign main_litedramcore_master_p0_rddata = main_a7ddrphy_dfi_p0_rddata;
+assign main_litedramcore_master_p0_rddata_valid = main_a7ddrphy_dfi_p0_rddata_valid;
+assign main_a7ddrphy_dfi_p1_address = main_litedramcore_master_p1_address;
+assign main_a7ddrphy_dfi_p1_bank = main_litedramcore_master_p1_bank;
+assign main_a7ddrphy_dfi_p1_cas_n = main_litedramcore_master_p1_cas_n;
+assign main_a7ddrphy_dfi_p1_cs_n = main_litedramcore_master_p1_cs_n;
+assign main_a7ddrphy_dfi_p1_ras_n = main_litedramcore_master_p1_ras_n;
+assign main_a7ddrphy_dfi_p1_we_n = main_litedramcore_master_p1_we_n;
+assign main_a7ddrphy_dfi_p1_cke = main_litedramcore_master_p1_cke;
+assign main_a7ddrphy_dfi_p1_odt = main_litedramcore_master_p1_odt;
+assign main_a7ddrphy_dfi_p1_reset_n = main_litedramcore_master_p1_reset_n;
+assign main_a7ddrphy_dfi_p1_act_n = main_litedramcore_master_p1_act_n;
+assign main_a7ddrphy_dfi_p1_wrdata = main_litedramcore_master_p1_wrdata;
+assign main_a7ddrphy_dfi_p1_wrdata_en = main_litedramcore_master_p1_wrdata_en;
+assign main_a7ddrphy_dfi_p1_wrdata_mask = main_litedramcore_master_p1_wrdata_mask;
+assign main_a7ddrphy_dfi_p1_rddata_en = main_litedramcore_master_p1_rddata_en;
+assign main_litedramcore_master_p1_rddata = main_a7ddrphy_dfi_p1_rddata;
+assign main_litedramcore_master_p1_rddata_valid = main_a7ddrphy_dfi_p1_rddata_valid;
+assign main_a7ddrphy_dfi_p2_address = main_litedramcore_master_p2_address;
+assign main_a7ddrphy_dfi_p2_bank = main_litedramcore_master_p2_bank;
+assign main_a7ddrphy_dfi_p2_cas_n = main_litedramcore_master_p2_cas_n;
+assign main_a7ddrphy_dfi_p2_cs_n = main_litedramcore_master_p2_cs_n;
+assign main_a7ddrphy_dfi_p2_ras_n = main_litedramcore_master_p2_ras_n;
+assign main_a7ddrphy_dfi_p2_we_n = main_litedramcore_master_p2_we_n;
+assign main_a7ddrphy_dfi_p2_cke = main_litedramcore_master_p2_cke;
+assign main_a7ddrphy_dfi_p2_odt = main_litedramcore_master_p2_odt;
+assign main_a7ddrphy_dfi_p2_reset_n = main_litedramcore_master_p2_reset_n;
+assign main_a7ddrphy_dfi_p2_act_n = main_litedramcore_master_p2_act_n;
+assign main_a7ddrphy_dfi_p2_wrdata = main_litedramcore_master_p2_wrdata;
+assign main_a7ddrphy_dfi_p2_wrdata_en = main_litedramcore_master_p2_wrdata_en;
+assign main_a7ddrphy_dfi_p2_wrdata_mask = main_litedramcore_master_p2_wrdata_mask;
+assign main_a7ddrphy_dfi_p2_rddata_en = main_litedramcore_master_p2_rddata_en;
+assign main_litedramcore_master_p2_rddata = main_a7ddrphy_dfi_p2_rddata;
+assign main_litedramcore_master_p2_rddata_valid = main_a7ddrphy_dfi_p2_rddata_valid;
+assign main_a7ddrphy_dfi_p3_address = main_litedramcore_master_p3_address;
+assign main_a7ddrphy_dfi_p3_bank = main_litedramcore_master_p3_bank;
+assign main_a7ddrphy_dfi_p3_cas_n = main_litedramcore_master_p3_cas_n;
+assign main_a7ddrphy_dfi_p3_cs_n = main_litedramcore_master_p3_cs_n;
+assign main_a7ddrphy_dfi_p3_ras_n = main_litedramcore_master_p3_ras_n;
+assign main_a7ddrphy_dfi_p3_we_n = main_litedramcore_master_p3_we_n;
+assign main_a7ddrphy_dfi_p3_cke = main_litedramcore_master_p3_cke;
+assign main_a7ddrphy_dfi_p3_odt = main_litedramcore_master_p3_odt;
+assign main_a7ddrphy_dfi_p3_reset_n = main_litedramcore_master_p3_reset_n;
+assign main_a7ddrphy_dfi_p3_act_n = main_litedramcore_master_p3_act_n;
+assign main_a7ddrphy_dfi_p3_wrdata = main_litedramcore_master_p3_wrdata;
+assign main_a7ddrphy_dfi_p3_wrdata_en = main_litedramcore_master_p3_wrdata_en;
+assign main_a7ddrphy_dfi_p3_wrdata_mask = main_litedramcore_master_p3_wrdata_mask;
+assign main_a7ddrphy_dfi_p3_rddata_en = main_litedramcore_master_p3_rddata_en;
+assign main_litedramcore_master_p3_rddata = main_a7ddrphy_dfi_p3_rddata;
+assign main_litedramcore_master_p3_rddata_valid = main_a7ddrphy_dfi_p3_rddata_valid;
+assign main_litedramcore_slave_p0_address = main_litedramcore_dfi_p0_address;
+assign main_litedramcore_slave_p0_bank = main_litedramcore_dfi_p0_bank;
+assign main_litedramcore_slave_p0_cas_n = main_litedramcore_dfi_p0_cas_n;
+assign main_litedramcore_slave_p0_cs_n = main_litedramcore_dfi_p0_cs_n;
+assign main_litedramcore_slave_p0_ras_n = main_litedramcore_dfi_p0_ras_n;
+assign main_litedramcore_slave_p0_we_n = main_litedramcore_dfi_p0_we_n;
+assign main_litedramcore_slave_p0_cke = main_litedramcore_dfi_p0_cke;
+assign main_litedramcore_slave_p0_odt = main_litedramcore_dfi_p0_odt;
+assign main_litedramcore_slave_p0_reset_n = main_litedramcore_dfi_p0_reset_n;
+assign main_litedramcore_slave_p0_act_n = main_litedramcore_dfi_p0_act_n;
+assign main_litedramcore_slave_p0_wrdata = main_litedramcore_dfi_p0_wrdata;
+assign main_litedramcore_slave_p0_wrdata_en = main_litedramcore_dfi_p0_wrdata_en;
+assign main_litedramcore_slave_p0_wrdata_mask = main_litedramcore_dfi_p0_wrdata_mask;
+assign main_litedramcore_slave_p0_rddata_en = main_litedramcore_dfi_p0_rddata_en;
+assign main_litedramcore_dfi_p0_rddata = main_litedramcore_slave_p0_rddata;
+assign main_litedramcore_dfi_p0_rddata_valid = main_litedramcore_slave_p0_rddata_valid;
+assign main_litedramcore_slave_p1_address = main_litedramcore_dfi_p1_address;
+assign main_litedramcore_slave_p1_bank = main_litedramcore_dfi_p1_bank;
+assign main_litedramcore_slave_p1_cas_n = main_litedramcore_dfi_p1_cas_n;
+assign main_litedramcore_slave_p1_cs_n = main_litedramcore_dfi_p1_cs_n;
+assign main_litedramcore_slave_p1_ras_n = main_litedramcore_dfi_p1_ras_n;
+assign main_litedramcore_slave_p1_we_n = main_litedramcore_dfi_p1_we_n;
+assign main_litedramcore_slave_p1_cke = main_litedramcore_dfi_p1_cke;
+assign main_litedramcore_slave_p1_odt = main_litedramcore_dfi_p1_odt;
+assign main_litedramcore_slave_p1_reset_n = main_litedramcore_dfi_p1_reset_n;
+assign main_litedramcore_slave_p1_act_n = main_litedramcore_dfi_p1_act_n;
+assign main_litedramcore_slave_p1_wrdata = main_litedramcore_dfi_p1_wrdata;
+assign main_litedramcore_slave_p1_wrdata_en = main_litedramcore_dfi_p1_wrdata_en;
+assign main_litedramcore_slave_p1_wrdata_mask = main_litedramcore_dfi_p1_wrdata_mask;
+assign main_litedramcore_slave_p1_rddata_en = main_litedramcore_dfi_p1_rddata_en;
+assign main_litedramcore_dfi_p1_rddata = main_litedramcore_slave_p1_rddata;
+assign main_litedramcore_dfi_p1_rddata_valid = main_litedramcore_slave_p1_rddata_valid;
+assign main_litedramcore_slave_p2_address = main_litedramcore_dfi_p2_address;
+assign main_litedramcore_slave_p2_bank = main_litedramcore_dfi_p2_bank;
+assign main_litedramcore_slave_p2_cas_n = main_litedramcore_dfi_p2_cas_n;
+assign main_litedramcore_slave_p2_cs_n = main_litedramcore_dfi_p2_cs_n;
+assign main_litedramcore_slave_p2_ras_n = main_litedramcore_dfi_p2_ras_n;
+assign main_litedramcore_slave_p2_we_n = main_litedramcore_dfi_p2_we_n;
+assign main_litedramcore_slave_p2_cke = main_litedramcore_dfi_p2_cke;
+assign main_litedramcore_slave_p2_odt = main_litedramcore_dfi_p2_odt;
+assign main_litedramcore_slave_p2_reset_n = main_litedramcore_dfi_p2_reset_n;
+assign main_litedramcore_slave_p2_act_n = main_litedramcore_dfi_p2_act_n;
+assign main_litedramcore_slave_p2_wrdata = main_litedramcore_dfi_p2_wrdata;
+assign main_litedramcore_slave_p2_wrdata_en = main_litedramcore_dfi_p2_wrdata_en;
+assign main_litedramcore_slave_p2_wrdata_mask = main_litedramcore_dfi_p2_wrdata_mask;
+assign main_litedramcore_slave_p2_rddata_en = main_litedramcore_dfi_p2_rddata_en;
+assign main_litedramcore_dfi_p2_rddata = main_litedramcore_slave_p2_rddata;
+assign main_litedramcore_dfi_p2_rddata_valid = main_litedramcore_slave_p2_rddata_valid;
+assign main_litedramcore_slave_p3_address = main_litedramcore_dfi_p3_address;
+assign main_litedramcore_slave_p3_bank = main_litedramcore_dfi_p3_bank;
+assign main_litedramcore_slave_p3_cas_n = main_litedramcore_dfi_p3_cas_n;
+assign main_litedramcore_slave_p3_cs_n = main_litedramcore_dfi_p3_cs_n;
+assign main_litedramcore_slave_p3_ras_n = main_litedramcore_dfi_p3_ras_n;
+assign main_litedramcore_slave_p3_we_n = main_litedramcore_dfi_p3_we_n;
+assign main_litedramcore_slave_p3_cke = main_litedramcore_dfi_p3_cke;
+assign main_litedramcore_slave_p3_odt = main_litedramcore_dfi_p3_odt;
+assign main_litedramcore_slave_p3_reset_n = main_litedramcore_dfi_p3_reset_n;
+assign main_litedramcore_slave_p3_act_n = main_litedramcore_dfi_p3_act_n;
+assign main_litedramcore_slave_p3_wrdata = main_litedramcore_dfi_p3_wrdata;
+assign main_litedramcore_slave_p3_wrdata_en = main_litedramcore_dfi_p3_wrdata_en;
+assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_mask;
+assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en;
+assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata;
+assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid;
+always @(*) begin
+    main_litedramcore_csr_dfi_p0_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+    end else begin
+        main_litedramcore_csr_dfi_p0_rddata <= main_litedramcore_master_p0_rddata;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p2_rddata <= 32'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata;
+        main_litedramcore_csr_dfi_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p1_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+        main_litedramcore_csr_dfi_p1_rddata <= main_litedramcore_master_p1_rddata;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p3_rddata <= 32'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata;
+        main_litedramcore_csr_dfi_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p2_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+        main_litedramcore_csr_dfi_p2_rddata <= main_litedramcore_master_p2_rddata;
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p0_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata;
-        end else begin
-        end
+    main_litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+    end else begin
+        main_litedramcore_csr_dfi_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
+    end
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p3_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
     end else begin
+        main_litedramcore_csr_dfi_p3_rddata <= main_litedramcore_master_p3_rddata;
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+    main_litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+    end else begin
+        main_litedramcore_csr_dfi_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
+    end
+end
+always @(*) begin
+    main_litedramcore_ext_dfi_p0_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p0_rddata <= main_litedramcore_master_p0_rddata;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p1_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+    main_litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+    main_litedramcore_ext_dfi_p1_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p1_rddata <= main_litedramcore_master_p1_rddata;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p2_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata;
+    main_litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+    main_litedramcore_ext_dfi_p2_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p2_rddata <= main_litedramcore_master_p2_rddata;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p0_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
         end else begin
-            litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p0_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p0_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+            main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p3_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata;
+    main_litedramcore_slave_p0_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
+            main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+    main_litedramcore_ext_dfi_p3_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p3_rddata <= main_litedramcore_master_p3_rddata;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p1_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
         end else begin
-            litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p1_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p1_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+            main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p2_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p1_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
+            main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p2_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p2_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+            main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p3_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p2_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
+            main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p3_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p3_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+            main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_master_p0_address <= 15'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address;
+    main_litedramcore_slave_p3_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_master_p0_address <= litedramcore_slave_p0_address;
+            main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
         end
     end else begin
-        litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_bank <= 3'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank;
+    main_litedramcore_master_p0_address <= 15'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_address <= main_litedramcore_ext_dfi_p0_address;
         end else begin
-            litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
+            main_litedramcore_master_p0_address <= main_litedramcore_slave_p0_address;
         end
     end else begin
-        litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank;
+        main_litedramcore_master_p0_address <= main_litedramcore_csr_dfi_p0_address;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_cas_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n;
+    main_litedramcore_master_p0_bank <= 3'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_bank <= main_litedramcore_ext_dfi_p0_bank;
         end else begin
-            litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
+            main_litedramcore_master_p0_bank <= main_litedramcore_slave_p0_bank;
         end
     end else begin
-        litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n;
+        main_litedramcore_master_p0_bank <= main_litedramcore_csr_dfi_p0_bank;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_cs_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
+    main_litedramcore_master_p0_cas_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_cas_n <= main_litedramcore_ext_dfi_p0_cas_n;
         end else begin
-            litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+            main_litedramcore_master_p0_cas_n <= main_litedramcore_slave_p0_cas_n;
         end
     end else begin
-        litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
+        main_litedramcore_master_p0_cas_n <= main_litedramcore_csr_dfi_p0_cas_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_ras_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
+    main_litedramcore_master_p0_cs_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_cs_n <= main_litedramcore_ext_dfi_p0_cs_n;
         end else begin
-            litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+            main_litedramcore_master_p0_cs_n <= main_litedramcore_slave_p0_cs_n;
+            if (1'd0) begin
+                main_litedramcore_master_p0_cs_n <= {2{main_litedramcore_slave_p0_cs_n}};
+            end
         end
     end else begin
-        litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
+        main_litedramcore_master_p0_cs_n <= main_litedramcore_csr_dfi_p0_cs_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_we_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
+    main_litedramcore_master_p0_ras_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_ras_n <= main_litedramcore_ext_dfi_p0_ras_n;
         end else begin
-            litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+            main_litedramcore_master_p0_ras_n <= main_litedramcore_slave_p0_ras_n;
         end
     end else begin
-        litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
+        main_litedramcore_master_p0_ras_n <= main_litedramcore_csr_dfi_p0_ras_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_cke <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke;
+    main_litedramcore_master_p0_we_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_we_n <= main_litedramcore_ext_dfi_p0_we_n;
         end else begin
-            litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
+            main_litedramcore_master_p0_we_n <= main_litedramcore_slave_p0_we_n;
         end
     end else begin
-        litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke;
+        main_litedramcore_master_p0_we_n <= main_litedramcore_csr_dfi_p0_we_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_odt <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt;
+    main_litedramcore_master_p0_cke <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_cke <= main_litedramcore_ext_dfi_p0_cke;
         end else begin
-            litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
+            main_litedramcore_master_p0_cke <= main_litedramcore_slave_p0_cke;
         end
     end else begin
-        litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt;
+        main_litedramcore_master_p0_cke <= main_litedramcore_csr_dfi_p0_cke;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_reset_n <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n;
+    main_litedramcore_master_p0_odt <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_odt <= main_litedramcore_ext_dfi_p0_odt;
         end else begin
-            litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
+            main_litedramcore_master_p0_odt <= main_litedramcore_slave_p0_odt;
         end
     end else begin
-        litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n;
+        main_litedramcore_master_p0_odt <= main_litedramcore_csr_dfi_p0_odt;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_act_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n;
+    main_litedramcore_master_p0_reset_n <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_reset_n <= main_litedramcore_ext_dfi_p0_reset_n;
         end else begin
-            litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
+            main_litedramcore_master_p0_reset_n <= main_litedramcore_slave_p0_reset_n;
         end
     end else begin
-        litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n;
+        main_litedramcore_master_p0_reset_n <= main_litedramcore_csr_dfi_p0_reset_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_wrdata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata;
+    main_litedramcore_master_p0_act_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_act_n <= main_litedramcore_ext_dfi_p0_act_n;
         end else begin
-            litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
+            main_litedramcore_master_p0_act_n <= main_litedramcore_slave_p0_act_n;
         end
     end else begin
-        litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata;
+        main_litedramcore_master_p0_act_n <= main_litedramcore_csr_dfi_p0_act_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_wrdata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en;
+    main_litedramcore_master_p0_wrdata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_wrdata <= main_litedramcore_ext_dfi_p0_wrdata;
         end else begin
-            litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
+            main_litedramcore_master_p0_wrdata <= main_litedramcore_slave_p0_wrdata;
         end
     end else begin
-        litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en;
+        main_litedramcore_master_p0_wrdata <= main_litedramcore_csr_dfi_p0_wrdata;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_wrdata_mask <= 4'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask;
+    main_litedramcore_master_p0_wrdata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_wrdata_en <= main_litedramcore_ext_dfi_p0_wrdata_en;
         end else begin
-            litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
+            main_litedramcore_master_p0_wrdata_en <= main_litedramcore_slave_p0_wrdata_en;
         end
     end else begin
-        litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask;
+        main_litedramcore_master_p0_wrdata_en <= main_litedramcore_csr_dfi_p0_wrdata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_rddata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en;
+    main_litedramcore_master_p0_wrdata_mask <= 4'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_ext_dfi_p0_wrdata_mask;
         end else begin
-            litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
+            main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_slave_p0_wrdata_mask;
         end
     end else begin
-        litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en;
+        main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_csr_dfi_p0_wrdata_mask;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_address <= 15'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address;
+    main_litedramcore_master_p0_rddata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_rddata_en <= main_litedramcore_ext_dfi_p0_rddata_en;
         end else begin
-            litedramcore_master_p1_address <= litedramcore_slave_p1_address;
+            main_litedramcore_master_p0_rddata_en <= main_litedramcore_slave_p0_rddata_en;
         end
     end else begin
-        litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address;
+        main_litedramcore_master_p0_rddata_en <= main_litedramcore_csr_dfi_p0_rddata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_bank <= 3'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank;
+    main_litedramcore_master_p1_address <= 15'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_address <= main_litedramcore_ext_dfi_p1_address;
         end else begin
-            litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
+            main_litedramcore_master_p1_address <= main_litedramcore_slave_p1_address;
         end
     end else begin
-        litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank;
+        main_litedramcore_master_p1_address <= main_litedramcore_csr_dfi_p1_address;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_cas_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n;
+    main_litedramcore_master_p1_bank <= 3'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_bank <= main_litedramcore_ext_dfi_p1_bank;
         end else begin
-            litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
+            main_litedramcore_master_p1_bank <= main_litedramcore_slave_p1_bank;
         end
     end else begin
-        litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n;
+        main_litedramcore_master_p1_bank <= main_litedramcore_csr_dfi_p1_bank;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_cs_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n;
+    main_litedramcore_master_p1_cas_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_cas_n <= main_litedramcore_ext_dfi_p1_cas_n;
         end else begin
-            litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
+            main_litedramcore_master_p1_cas_n <= main_litedramcore_slave_p1_cas_n;
         end
     end else begin
-        litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n;
+        main_litedramcore_master_p1_cas_n <= main_litedramcore_csr_dfi_p1_cas_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_ras_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n;
+    main_litedramcore_master_p1_cs_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_cs_n <= main_litedramcore_ext_dfi_p1_cs_n;
         end else begin
-            litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
+            main_litedramcore_master_p1_cs_n <= main_litedramcore_slave_p1_cs_n;
+            if (1'd0) begin
+                main_litedramcore_master_p1_cs_n <= {2{main_litedramcore_slave_p1_cs_n}};
+            end
         end
     end else begin
-        litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n;
+        main_litedramcore_master_p1_cs_n <= main_litedramcore_csr_dfi_p1_cs_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_we_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n;
+    main_litedramcore_master_p1_ras_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_ras_n <= main_litedramcore_ext_dfi_p1_ras_n;
         end else begin
-            litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
+            main_litedramcore_master_p1_ras_n <= main_litedramcore_slave_p1_ras_n;
         end
     end else begin
-        litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n;
+        main_litedramcore_master_p1_ras_n <= main_litedramcore_csr_dfi_p1_ras_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_cke <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke;
+    main_litedramcore_master_p1_we_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_we_n <= main_litedramcore_ext_dfi_p1_we_n;
         end else begin
-            litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
+            main_litedramcore_master_p1_we_n <= main_litedramcore_slave_p1_we_n;
         end
     end else begin
-        litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke;
+        main_litedramcore_master_p1_we_n <= main_litedramcore_csr_dfi_p1_we_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_odt <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt;
+    main_litedramcore_master_p1_cke <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_cke <= main_litedramcore_ext_dfi_p1_cke;
         end else begin
-            litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
+            main_litedramcore_master_p1_cke <= main_litedramcore_slave_p1_cke;
         end
     end else begin
-        litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt;
+        main_litedramcore_master_p1_cke <= main_litedramcore_csr_dfi_p1_cke;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_reset_n <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n;
+    main_litedramcore_master_p1_odt <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_odt <= main_litedramcore_ext_dfi_p1_odt;
         end else begin
-            litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+            main_litedramcore_master_p1_odt <= main_litedramcore_slave_p1_odt;
         end
     end else begin
-        litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n;
+        main_litedramcore_master_p1_odt <= main_litedramcore_csr_dfi_p1_odt;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_act_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n;
+    main_litedramcore_master_p1_reset_n <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_reset_n <= main_litedramcore_ext_dfi_p1_reset_n;
         end else begin
-            litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
+            main_litedramcore_master_p1_reset_n <= main_litedramcore_slave_p1_reset_n;
         end
     end else begin
-        litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n;
+        main_litedramcore_master_p1_reset_n <= main_litedramcore_csr_dfi_p1_reset_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_wrdata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata;
+    main_litedramcore_master_p1_act_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_act_n <= main_litedramcore_ext_dfi_p1_act_n;
         end else begin
-            litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
+            main_litedramcore_master_p1_act_n <= main_litedramcore_slave_p1_act_n;
         end
     end else begin
-        litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata;
+        main_litedramcore_master_p1_act_n <= main_litedramcore_csr_dfi_p1_act_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_wrdata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en;
+    main_litedramcore_master_p1_wrdata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_wrdata <= main_litedramcore_ext_dfi_p1_wrdata;
         end else begin
-            litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
+            main_litedramcore_master_p1_wrdata <= main_litedramcore_slave_p1_wrdata;
         end
     end else begin
-        litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en;
+        main_litedramcore_master_p1_wrdata <= main_litedramcore_csr_dfi_p1_wrdata;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_wrdata_mask <= 4'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask;
+    main_litedramcore_master_p1_wrdata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_wrdata_en <= main_litedramcore_ext_dfi_p1_wrdata_en;
         end else begin
-            litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
+            main_litedramcore_master_p1_wrdata_en <= main_litedramcore_slave_p1_wrdata_en;
         end
     end else begin
-        litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask;
+        main_litedramcore_master_p1_wrdata_en <= main_litedramcore_csr_dfi_p1_wrdata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_rddata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en;
+    main_litedramcore_master_p1_wrdata_mask <= 4'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_ext_dfi_p1_wrdata_mask;
         end else begin
-            litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
+            main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_slave_p1_wrdata_mask;
         end
     end else begin
-        litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en;
+        main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_csr_dfi_p1_wrdata_mask;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_address <= 15'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address;
+    main_litedramcore_master_p1_rddata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_rddata_en <= main_litedramcore_ext_dfi_p1_rddata_en;
         end else begin
-            litedramcore_master_p2_address <= litedramcore_slave_p2_address;
+            main_litedramcore_master_p1_rddata_en <= main_litedramcore_slave_p1_rddata_en;
         end
     end else begin
-        litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address;
+        main_litedramcore_master_p1_rddata_en <= main_litedramcore_csr_dfi_p1_rddata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_bank <= 3'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank;
+    main_litedramcore_master_p2_address <= 15'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_address <= main_litedramcore_ext_dfi_p2_address;
         end else begin
-            litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
+            main_litedramcore_master_p2_address <= main_litedramcore_slave_p2_address;
         end
     end else begin
-        litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank;
+        main_litedramcore_master_p2_address <= main_litedramcore_csr_dfi_p2_address;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_cas_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n;
+    main_litedramcore_master_p2_bank <= 3'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_bank <= main_litedramcore_ext_dfi_p2_bank;
         end else begin
-            litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
+            main_litedramcore_master_p2_bank <= main_litedramcore_slave_p2_bank;
         end
     end else begin
-        litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n;
+        main_litedramcore_master_p2_bank <= main_litedramcore_csr_dfi_p2_bank;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_cs_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n;
+    main_litedramcore_master_p2_cas_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_cas_n <= main_litedramcore_ext_dfi_p2_cas_n;
         end else begin
-            litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
+            main_litedramcore_master_p2_cas_n <= main_litedramcore_slave_p2_cas_n;
         end
     end else begin
-        litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n;
+        main_litedramcore_master_p2_cas_n <= main_litedramcore_csr_dfi_p2_cas_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_ras_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n;
+    main_litedramcore_master_p2_cs_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_cs_n <= main_litedramcore_ext_dfi_p2_cs_n;
         end else begin
-            litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
+            main_litedramcore_master_p2_cs_n <= main_litedramcore_slave_p2_cs_n;
+            if (1'd0) begin
+                main_litedramcore_master_p2_cs_n <= {2{main_litedramcore_slave_p2_cs_n}};
+            end
         end
     end else begin
-        litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n;
+        main_litedramcore_master_p2_cs_n <= main_litedramcore_csr_dfi_p2_cs_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_we_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n;
+    main_litedramcore_master_p2_ras_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_ras_n <= main_litedramcore_ext_dfi_p2_ras_n;
         end else begin
-            litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
+            main_litedramcore_master_p2_ras_n <= main_litedramcore_slave_p2_ras_n;
         end
     end else begin
-        litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n;
+        main_litedramcore_master_p2_ras_n <= main_litedramcore_csr_dfi_p2_ras_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_cke <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke;
+    main_litedramcore_master_p2_we_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_we_n <= main_litedramcore_ext_dfi_p2_we_n;
         end else begin
-            litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
+            main_litedramcore_master_p2_we_n <= main_litedramcore_slave_p2_we_n;
         end
     end else begin
-        litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke;
+        main_litedramcore_master_p2_we_n <= main_litedramcore_csr_dfi_p2_we_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_odt <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt;
+    main_litedramcore_master_p2_cke <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_cke <= main_litedramcore_ext_dfi_p2_cke;
         end else begin
-            litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
+            main_litedramcore_master_p2_cke <= main_litedramcore_slave_p2_cke;
         end
     end else begin
-        litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt;
+        main_litedramcore_master_p2_cke <= main_litedramcore_csr_dfi_p2_cke;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_reset_n <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n;
+    main_litedramcore_master_p2_odt <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_odt <= main_litedramcore_ext_dfi_p2_odt;
         end else begin
-            litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
+            main_litedramcore_master_p2_odt <= main_litedramcore_slave_p2_odt;
         end
     end else begin
-        litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n;
+        main_litedramcore_master_p2_odt <= main_litedramcore_csr_dfi_p2_odt;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_act_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n;
+    main_litedramcore_master_p2_reset_n <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_reset_n <= main_litedramcore_ext_dfi_p2_reset_n;
         end else begin
-            litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
+            main_litedramcore_master_p2_reset_n <= main_litedramcore_slave_p2_reset_n;
         end
     end else begin
-        litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n;
+        main_litedramcore_master_p2_reset_n <= main_litedramcore_csr_dfi_p2_reset_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_wrdata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata;
+    main_litedramcore_master_p2_act_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_act_n <= main_litedramcore_ext_dfi_p2_act_n;
         end else begin
-            litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
+            main_litedramcore_master_p2_act_n <= main_litedramcore_slave_p2_act_n;
         end
     end else begin
-        litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata;
+        main_litedramcore_master_p2_act_n <= main_litedramcore_csr_dfi_p2_act_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_wrdata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en;
+    main_litedramcore_master_p2_wrdata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_wrdata <= main_litedramcore_ext_dfi_p2_wrdata;
         end else begin
-            litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
+            main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata;
         end
     end else begin
-        litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en;
+        main_litedramcore_master_p2_wrdata <= main_litedramcore_csr_dfi_p2_wrdata;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_wrdata_mask <= 4'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask;
+    main_litedramcore_master_p2_wrdata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_wrdata_en <= main_litedramcore_ext_dfi_p2_wrdata_en;
         end else begin
-            litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
+            main_litedramcore_master_p2_wrdata_en <= main_litedramcore_slave_p2_wrdata_en;
         end
     end else begin
-        litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask;
+        main_litedramcore_master_p2_wrdata_en <= main_litedramcore_csr_dfi_p2_wrdata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_rddata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en;
+    main_litedramcore_master_p2_wrdata_mask <= 4'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_ext_dfi_p2_wrdata_mask;
         end else begin
-            litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
+            main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_slave_p2_wrdata_mask;
         end
     end else begin
-        litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en;
+        main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_csr_dfi_p2_wrdata_mask;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_address <= 15'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address;
+    main_litedramcore_master_p2_rddata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_rddata_en <= main_litedramcore_ext_dfi_p2_rddata_en;
         end else begin
-            litedramcore_master_p3_address <= litedramcore_slave_p3_address;
+            main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en;
         end
     end else begin
-        litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address;
+        main_litedramcore_master_p2_rddata_en <= main_litedramcore_csr_dfi_p2_rddata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_bank <= 3'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank;
+    main_litedramcore_master_p3_address <= 15'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_address <= main_litedramcore_ext_dfi_p3_address;
         end else begin
-            litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
+            main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address;
         end
     end else begin
-        litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank;
+        main_litedramcore_master_p3_address <= main_litedramcore_csr_dfi_p3_address;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_cas_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n;
+    main_litedramcore_master_p3_bank <= 3'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_bank <= main_litedramcore_ext_dfi_p3_bank;
         end else begin
-            litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
+            main_litedramcore_master_p3_bank <= main_litedramcore_slave_p3_bank;
         end
     end else begin
-        litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n;
+        main_litedramcore_master_p3_bank <= main_litedramcore_csr_dfi_p3_bank;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_cs_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n;
+    main_litedramcore_master_p3_cas_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_cas_n <= main_litedramcore_ext_dfi_p3_cas_n;
         end else begin
-            litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
+            main_litedramcore_master_p3_cas_n <= main_litedramcore_slave_p3_cas_n;
         end
     end else begin
-        litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n;
+        main_litedramcore_master_p3_cas_n <= main_litedramcore_csr_dfi_p3_cas_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_ras_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n;
+    main_litedramcore_master_p3_cs_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_cs_n <= main_litedramcore_ext_dfi_p3_cs_n;
         end else begin
-            litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
+            main_litedramcore_master_p3_cs_n <= main_litedramcore_slave_p3_cs_n;
+            if (1'd0) begin
+                main_litedramcore_master_p3_cs_n <= {2{main_litedramcore_slave_p3_cs_n}};
+            end
         end
     end else begin
-        litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n;
+        main_litedramcore_master_p3_cs_n <= main_litedramcore_csr_dfi_p3_cs_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_we_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n;
+    main_litedramcore_master_p3_ras_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_ras_n <= main_litedramcore_ext_dfi_p3_ras_n;
         end else begin
-            litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
+            main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n;
         end
     end else begin
-        litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n;
+        main_litedramcore_master_p3_ras_n <= main_litedramcore_csr_dfi_p3_ras_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_cke <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke;
+    main_litedramcore_master_p3_we_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_we_n <= main_litedramcore_ext_dfi_p3_we_n;
         end else begin
-            litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
+            main_litedramcore_master_p3_we_n <= main_litedramcore_slave_p3_we_n;
         end
     end else begin
-        litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke;
+        main_litedramcore_master_p3_we_n <= main_litedramcore_csr_dfi_p3_we_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_odt <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt;
+    main_litedramcore_master_p3_cke <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_cke <= main_litedramcore_ext_dfi_p3_cke;
         end else begin
-            litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
+            main_litedramcore_master_p3_cke <= main_litedramcore_slave_p3_cke;
         end
     end else begin
-        litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt;
+        main_litedramcore_master_p3_cke <= main_litedramcore_csr_dfi_p3_cke;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_reset_n <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n;
+    main_litedramcore_master_p3_odt <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_odt <= main_litedramcore_ext_dfi_p3_odt;
         end else begin
-            litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
+            main_litedramcore_master_p3_odt <= main_litedramcore_slave_p3_odt;
         end
     end else begin
-        litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n;
+        main_litedramcore_master_p3_odt <= main_litedramcore_csr_dfi_p3_odt;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_act_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n;
+    main_litedramcore_master_p3_reset_n <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_reset_n <= main_litedramcore_ext_dfi_p3_reset_n;
         end else begin
-            litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
+            main_litedramcore_master_p3_reset_n <= main_litedramcore_slave_p3_reset_n;
         end
     end else begin
-        litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n;
+        main_litedramcore_master_p3_reset_n <= main_litedramcore_csr_dfi_p3_reset_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_wrdata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata;
+    main_litedramcore_master_p3_act_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_act_n <= main_litedramcore_ext_dfi_p3_act_n;
         end else begin
-            litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
+            main_litedramcore_master_p3_act_n <= main_litedramcore_slave_p3_act_n;
         end
     end else begin
-        litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata;
+        main_litedramcore_master_p3_act_n <= main_litedramcore_csr_dfi_p3_act_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_wrdata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en;
+    main_litedramcore_master_p3_wrdata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_wrdata <= main_litedramcore_ext_dfi_p3_wrdata;
         end else begin
-            litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
+            main_litedramcore_master_p3_wrdata <= main_litedramcore_slave_p3_wrdata;
         end
     end else begin
-        litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en;
+        main_litedramcore_master_p3_wrdata <= main_litedramcore_csr_dfi_p3_wrdata;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_wrdata_mask <= 4'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask;
+    main_litedramcore_master_p3_wrdata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_wrdata_en <= main_litedramcore_ext_dfi_p3_wrdata_en;
         end else begin
-            litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
+            main_litedramcore_master_p3_wrdata_en <= main_litedramcore_slave_p3_wrdata_en;
         end
     end else begin
-        litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask;
+        main_litedramcore_master_p3_wrdata_en <= main_litedramcore_csr_dfi_p3_wrdata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_rddata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en;
+    main_litedramcore_master_p3_wrdata_mask <= 4'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_ext_dfi_p3_wrdata_mask;
         end else begin
-            litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
+            main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_slave_p3_wrdata_mask;
         end
     end else begin
-        litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en;
+        main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_csr_dfi_p3_wrdata_mask;
     end
 end
-assign litedramcore_csr_dfi_p0_cke = litedramcore_cke;
-assign litedramcore_csr_dfi_p1_cke = litedramcore_cke;
-assign litedramcore_csr_dfi_p2_cke = litedramcore_cke;
-assign litedramcore_csr_dfi_p3_cke = litedramcore_cke;
-assign litedramcore_csr_dfi_p0_odt = litedramcore_odt;
-assign litedramcore_csr_dfi_p1_odt = litedramcore_odt;
-assign litedramcore_csr_dfi_p2_odt = litedramcore_odt;
-assign litedramcore_csr_dfi_p3_odt = litedramcore_odt;
-assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n;
-assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n;
-assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n;
-assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n;
 always @(*) begin
-    litedramcore_csr_dfi_p0_ras_n <= 1'd1;
-    if (litedramcore_phaseinjector0_command_issue_re) begin
-        litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras);
+    main_litedramcore_master_p3_rddata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_rddata_en <= main_litedramcore_ext_dfi_p3_rddata_en;
+        end else begin
+            main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en;
+        end
     end else begin
-        litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+        main_litedramcore_master_p3_rddata_en <= main_litedramcore_csr_dfi_p3_rddata_en;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p0_we_n <= 1'd1;
-    if (litedramcore_phaseinjector0_command_issue_re) begin
-        litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
+    main_litedramcore_csr_dfi_p0_cke <= 1'd0;
+    main_litedramcore_csr_dfi_p0_cke <= main_litedramcore_cke;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p1_cke <= 1'd0;
+    main_litedramcore_csr_dfi_p1_cke <= main_litedramcore_cke;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p2_cke <= 1'd0;
+    main_litedramcore_csr_dfi_p2_cke <= main_litedramcore_cke;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p3_cke <= 1'd0;
+    main_litedramcore_csr_dfi_p3_cke <= main_litedramcore_cke;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p0_odt <= 1'd0;
+    main_litedramcore_csr_dfi_p0_odt <= main_litedramcore_odt;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p1_odt <= 1'd0;
+    main_litedramcore_csr_dfi_p1_odt <= main_litedramcore_odt;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p2_odt <= 1'd0;
+    main_litedramcore_csr_dfi_p2_odt <= main_litedramcore_odt;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p3_odt <= 1'd0;
+    main_litedramcore_csr_dfi_p3_odt <= main_litedramcore_odt;
+end
+assign main_litedramcore_csr_dfi_p0_reset_n = main_litedramcore_reset_n;
+assign main_litedramcore_csr_dfi_p1_reset_n = main_litedramcore_reset_n;
+assign main_litedramcore_csr_dfi_p2_reset_n = main_litedramcore_reset_n;
+assign main_litedramcore_csr_dfi_p3_reset_n = main_litedramcore_reset_n;
+always @(*) begin
+    main_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        main_litedramcore_csr_dfi_p0_ras_n <= (~main_litedramcore_phaseinjector0_csrfield_ras);
     end else begin
-        litedramcore_csr_dfi_p0_we_n <= 1'd1;
+        main_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p0_cas_n <= 1'd1;
-    if (litedramcore_phaseinjector0_command_issue_re) begin
-        litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas);
+    main_litedramcore_csr_dfi_p0_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        main_litedramcore_csr_dfi_p0_we_n <= (~main_litedramcore_phaseinjector0_csrfield_we);
     end else begin
-        litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+        main_litedramcore_csr_dfi_p0_we_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p0_cs_n <= 1'd1;
-    if (litedramcore_phaseinjector0_command_issue_re) begin
-        litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}};
+    main_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        main_litedramcore_csr_dfi_p0_cas_n <= (~main_litedramcore_phaseinjector0_csrfield_cas);
     end else begin
-        litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
+        main_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
     end
 end
-assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage;
-assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage;
-assign litedramcore_csr_dfi_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_wren);
-assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_rden);
-assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
-assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
 always @(*) begin
-    litedramcore_csr_dfi_p1_ras_n <= 1'd1;
-    if (litedramcore_phaseinjector1_command_issue_re) begin
-        litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras);
+    main_litedramcore_csr_dfi_p0_cs_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        if (main_litedramcore_phaseinjector0_csrfield_cs_top) begin
+            main_litedramcore_csr_dfi_p0_cs_n <= 2'd2;
+        end else begin
+            if (main_litedramcore_phaseinjector0_csrfield_cs_bottom) begin
+                main_litedramcore_csr_dfi_p0_cs_n <= 1'd1;
+            end else begin
+                main_litedramcore_csr_dfi_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_csrfield_cs)}};
+            end
+        end
     end else begin
-        litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+        main_litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
     end
 end
+assign main_litedramcore_csr_dfi_p0_address = main_litedramcore_phaseinjector0_address_storage;
+assign main_litedramcore_csr_dfi_p0_bank = main_litedramcore_phaseinjector0_baddress_storage;
+assign main_litedramcore_csr_dfi_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_wren);
+assign main_litedramcore_csr_dfi_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_rden);
+assign main_litedramcore_csr_dfi_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage;
+assign main_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
 always @(*) begin
-    litedramcore_csr_dfi_p1_we_n <= 1'd1;
-    if (litedramcore_phaseinjector1_command_issue_re) begin
-        litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
+    main_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        main_litedramcore_csr_dfi_p1_ras_n <= (~main_litedramcore_phaseinjector1_csrfield_ras);
     end else begin
-        litedramcore_csr_dfi_p1_we_n <= 1'd1;
+        main_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p1_cas_n <= 1'd1;
-    if (litedramcore_phaseinjector1_command_issue_re) begin
-        litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas);
+    main_litedramcore_csr_dfi_p1_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        main_litedramcore_csr_dfi_p1_we_n <= (~main_litedramcore_phaseinjector1_csrfield_we);
     end else begin
-        litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+        main_litedramcore_csr_dfi_p1_we_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p1_cs_n <= 1'd1;
-    if (litedramcore_phaseinjector1_command_issue_re) begin
-        litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}};
+    main_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        main_litedramcore_csr_dfi_p1_cas_n <= (~main_litedramcore_phaseinjector1_csrfield_cas);
     end else begin
-        litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
+        main_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
     end
 end
-assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage;
-assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage;
-assign litedramcore_csr_dfi_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_wren);
-assign litedramcore_csr_dfi_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_rden);
-assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
-assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
 always @(*) begin
-    litedramcore_csr_dfi_p2_ras_n <= 1'd1;
-    if (litedramcore_phaseinjector2_command_issue_re) begin
-        litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras);
+    main_litedramcore_csr_dfi_p1_cs_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        if (main_litedramcore_phaseinjector1_csrfield_cs_top) begin
+            main_litedramcore_csr_dfi_p1_cs_n <= 2'd2;
+        end else begin
+            if (main_litedramcore_phaseinjector1_csrfield_cs_bottom) begin
+                main_litedramcore_csr_dfi_p1_cs_n <= 1'd1;
+            end else begin
+                main_litedramcore_csr_dfi_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_csrfield_cs)}};
+            end
+        end
     end else begin
-        litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+        main_litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
     end
 end
+assign main_litedramcore_csr_dfi_p1_address = main_litedramcore_phaseinjector1_address_storage;
+assign main_litedramcore_csr_dfi_p1_bank = main_litedramcore_phaseinjector1_baddress_storage;
+assign main_litedramcore_csr_dfi_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_wren);
+assign main_litedramcore_csr_dfi_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_rden);
+assign main_litedramcore_csr_dfi_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage;
+assign main_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
 always @(*) begin
-    litedramcore_csr_dfi_p2_we_n <= 1'd1;
-    if (litedramcore_phaseinjector2_command_issue_re) begin
-        litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we);
+    main_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        main_litedramcore_csr_dfi_p2_ras_n <= (~main_litedramcore_phaseinjector2_csrfield_ras);
     end else begin
-        litedramcore_csr_dfi_p2_we_n <= 1'd1;
+        main_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p2_cas_n <= 1'd1;
-    if (litedramcore_phaseinjector2_command_issue_re) begin
-        litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas);
+    main_litedramcore_csr_dfi_p2_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        main_litedramcore_csr_dfi_p2_we_n <= (~main_litedramcore_phaseinjector2_csrfield_we);
     end else begin
-        litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+        main_litedramcore_csr_dfi_p2_we_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p2_cs_n <= 1'd1;
-    if (litedramcore_phaseinjector2_command_issue_re) begin
-        litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}};
+    main_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        main_litedramcore_csr_dfi_p2_cas_n <= (~main_litedramcore_phaseinjector2_csrfield_cas);
     end else begin
-        litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
+        main_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
     end
 end
-assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage;
-assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage;
-assign litedramcore_csr_dfi_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_wren);
-assign litedramcore_csr_dfi_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_rden);
-assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
-assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
 always @(*) begin
-    litedramcore_csr_dfi_p3_ras_n <= 1'd1;
-    if (litedramcore_phaseinjector3_command_issue_re) begin
-        litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras);
+    main_litedramcore_csr_dfi_p2_cs_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        if (main_litedramcore_phaseinjector2_csrfield_cs_top) begin
+            main_litedramcore_csr_dfi_p2_cs_n <= 2'd2;
+        end else begin
+            if (main_litedramcore_phaseinjector2_csrfield_cs_bottom) begin
+                main_litedramcore_csr_dfi_p2_cs_n <= 1'd1;
+            end else begin
+                main_litedramcore_csr_dfi_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_csrfield_cs)}};
+            end
+        end
     end else begin
-        litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+        main_litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
     end
 end
+assign main_litedramcore_csr_dfi_p2_address = main_litedramcore_phaseinjector2_address_storage;
+assign main_litedramcore_csr_dfi_p2_bank = main_litedramcore_phaseinjector2_baddress_storage;
+assign main_litedramcore_csr_dfi_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_wren);
+assign main_litedramcore_csr_dfi_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_rden);
+assign main_litedramcore_csr_dfi_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage;
+assign main_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
 always @(*) begin
-    litedramcore_csr_dfi_p3_we_n <= 1'd1;
-    if (litedramcore_phaseinjector3_command_issue_re) begin
-        litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we);
+    main_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        main_litedramcore_csr_dfi_p3_ras_n <= (~main_litedramcore_phaseinjector3_csrfield_ras);
     end else begin
-        litedramcore_csr_dfi_p3_we_n <= 1'd1;
+        main_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p3_cas_n <= 1'd1;
-    if (litedramcore_phaseinjector3_command_issue_re) begin
-        litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas);
+    main_litedramcore_csr_dfi_p3_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        main_litedramcore_csr_dfi_p3_we_n <= (~main_litedramcore_phaseinjector3_csrfield_we);
     end else begin
-        litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+        main_litedramcore_csr_dfi_p3_we_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p3_cs_n <= 1'd1;
-    if (litedramcore_phaseinjector3_command_issue_re) begin
-        litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}};
+    main_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        main_litedramcore_csr_dfi_p3_cas_n <= (~main_litedramcore_phaseinjector3_csrfield_cas);
     end else begin
-        litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
+        main_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
     end
 end
-assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage;
-assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage;
-assign litedramcore_csr_dfi_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_wren);
-assign litedramcore_csr_dfi_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_rden);
-assign litedramcore_csr_dfi_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage;
-assign litedramcore_csr_dfi_p3_wrdata_mask = 1'd0;
-assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid;
-assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready;
-assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we;
-assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr;
-assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock;
-assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready;
-assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid;
-assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid;
-assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready;
-assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we;
-assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr;
-assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock;
-assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready;
-assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid;
-assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid;
-assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready;
-assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we;
-assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr;
-assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock;
-assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready;
-assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid;
-assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid;
-assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready;
-assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we;
-assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr;
-assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock;
-assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready;
-assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid;
-assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid;
-assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready;
-assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we;
-assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr;
-assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock;
-assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready;
-assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid;
-assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid;
-assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready;
-assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we;
-assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr;
-assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock;
-assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready;
-assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid;
-assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid;
-assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready;
-assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we;
-assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr;
-assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock;
-assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready;
-assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid;
-assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid;
-assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready;
-assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we;
-assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr;
-assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock;
-assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready;
-assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid;
-assign litedramcore_timer_wait = (~litedramcore_timer_done0);
-assign litedramcore_postponer_req_i = litedramcore_timer_done0;
-assign litedramcore_wants_refresh = litedramcore_postponer_req_o;
-assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0;
-assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done);
-assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0);
-assign litedramcore_timer_done0 = litedramcore_timer_done1;
-assign litedramcore_timer_count0 = litedramcore_timer_count1;
-assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0));
-assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0));
-assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0);
-assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
-assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
-always @(*) begin
-    litedramcore_refresher_next_state <= 2'd0;
-    litedramcore_refresher_next_state <= litedramcore_refresher_state;
-    case (litedramcore_refresher_state)
-        1'd1: begin
-            if (litedramcore_cmd_ready) begin
-                litedramcore_refresher_next_state <= 2'd2;
-            end
-        end
-        2'd2: begin
-            if (litedramcore_sequencer_done0) begin
-                if (litedramcore_wants_zqcs) begin
-                    litedramcore_refresher_next_state <= 2'd3;
+always @(*) begin
+    main_litedramcore_csr_dfi_p3_cs_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        if (main_litedramcore_phaseinjector3_csrfield_cs_top) begin
+            main_litedramcore_csr_dfi_p3_cs_n <= 2'd2;
+        end else begin
+            if (main_litedramcore_phaseinjector3_csrfield_cs_bottom) begin
+                main_litedramcore_csr_dfi_p3_cs_n <= 1'd1;
+            end else begin
+                main_litedramcore_csr_dfi_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_csrfield_cs)}};
+            end
+        end
+    end else begin
+        main_litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
+    end
+end
+assign main_litedramcore_csr_dfi_p3_address = main_litedramcore_phaseinjector3_address_storage;
+assign main_litedramcore_csr_dfi_p3_bank = main_litedramcore_phaseinjector3_baddress_storage;
+assign main_litedramcore_csr_dfi_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_wren);
+assign main_litedramcore_csr_dfi_p3_rddata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_rden);
+assign main_litedramcore_csr_dfi_p3_wrdata = main_litedramcore_phaseinjector3_wrdata_storage;
+assign main_litedramcore_csr_dfi_p3_wrdata_mask = 1'd0;
+assign main_litedramcore_bankmachine0_req_valid = main_litedramcore_interface_bank0_valid;
+assign main_litedramcore_interface_bank0_ready = main_litedramcore_bankmachine0_req_ready;
+assign main_litedramcore_bankmachine0_req_we = main_litedramcore_interface_bank0_we;
+assign main_litedramcore_bankmachine0_req_addr = main_litedramcore_interface_bank0_addr;
+assign main_litedramcore_interface_bank0_lock = main_litedramcore_bankmachine0_req_lock;
+assign main_litedramcore_interface_bank0_wdata_ready = main_litedramcore_bankmachine0_req_wdata_ready;
+assign main_litedramcore_interface_bank0_rdata_valid = main_litedramcore_bankmachine0_req_rdata_valid;
+assign main_litedramcore_bankmachine1_req_valid = main_litedramcore_interface_bank1_valid;
+assign main_litedramcore_interface_bank1_ready = main_litedramcore_bankmachine1_req_ready;
+assign main_litedramcore_bankmachine1_req_we = main_litedramcore_interface_bank1_we;
+assign main_litedramcore_bankmachine1_req_addr = main_litedramcore_interface_bank1_addr;
+assign main_litedramcore_interface_bank1_lock = main_litedramcore_bankmachine1_req_lock;
+assign main_litedramcore_interface_bank1_wdata_ready = main_litedramcore_bankmachine1_req_wdata_ready;
+assign main_litedramcore_interface_bank1_rdata_valid = main_litedramcore_bankmachine1_req_rdata_valid;
+assign main_litedramcore_bankmachine2_req_valid = main_litedramcore_interface_bank2_valid;
+assign main_litedramcore_interface_bank2_ready = main_litedramcore_bankmachine2_req_ready;
+assign main_litedramcore_bankmachine2_req_we = main_litedramcore_interface_bank2_we;
+assign main_litedramcore_bankmachine2_req_addr = main_litedramcore_interface_bank2_addr;
+assign main_litedramcore_interface_bank2_lock = main_litedramcore_bankmachine2_req_lock;
+assign main_litedramcore_interface_bank2_wdata_ready = main_litedramcore_bankmachine2_req_wdata_ready;
+assign main_litedramcore_interface_bank2_rdata_valid = main_litedramcore_bankmachine2_req_rdata_valid;
+assign main_litedramcore_bankmachine3_req_valid = main_litedramcore_interface_bank3_valid;
+assign main_litedramcore_interface_bank3_ready = main_litedramcore_bankmachine3_req_ready;
+assign main_litedramcore_bankmachine3_req_we = main_litedramcore_interface_bank3_we;
+assign main_litedramcore_bankmachine3_req_addr = main_litedramcore_interface_bank3_addr;
+assign main_litedramcore_interface_bank3_lock = main_litedramcore_bankmachine3_req_lock;
+assign main_litedramcore_interface_bank3_wdata_ready = main_litedramcore_bankmachine3_req_wdata_ready;
+assign main_litedramcore_interface_bank3_rdata_valid = main_litedramcore_bankmachine3_req_rdata_valid;
+assign main_litedramcore_bankmachine4_req_valid = main_litedramcore_interface_bank4_valid;
+assign main_litedramcore_interface_bank4_ready = main_litedramcore_bankmachine4_req_ready;
+assign main_litedramcore_bankmachine4_req_we = main_litedramcore_interface_bank4_we;
+assign main_litedramcore_bankmachine4_req_addr = main_litedramcore_interface_bank4_addr;
+assign main_litedramcore_interface_bank4_lock = main_litedramcore_bankmachine4_req_lock;
+assign main_litedramcore_interface_bank4_wdata_ready = main_litedramcore_bankmachine4_req_wdata_ready;
+assign main_litedramcore_interface_bank4_rdata_valid = main_litedramcore_bankmachine4_req_rdata_valid;
+assign main_litedramcore_bankmachine5_req_valid = main_litedramcore_interface_bank5_valid;
+assign main_litedramcore_interface_bank5_ready = main_litedramcore_bankmachine5_req_ready;
+assign main_litedramcore_bankmachine5_req_we = main_litedramcore_interface_bank5_we;
+assign main_litedramcore_bankmachine5_req_addr = main_litedramcore_interface_bank5_addr;
+assign main_litedramcore_interface_bank5_lock = main_litedramcore_bankmachine5_req_lock;
+assign main_litedramcore_interface_bank5_wdata_ready = main_litedramcore_bankmachine5_req_wdata_ready;
+assign main_litedramcore_interface_bank5_rdata_valid = main_litedramcore_bankmachine5_req_rdata_valid;
+assign main_litedramcore_bankmachine6_req_valid = main_litedramcore_interface_bank6_valid;
+assign main_litedramcore_interface_bank6_ready = main_litedramcore_bankmachine6_req_ready;
+assign main_litedramcore_bankmachine6_req_we = main_litedramcore_interface_bank6_we;
+assign main_litedramcore_bankmachine6_req_addr = main_litedramcore_interface_bank6_addr;
+assign main_litedramcore_interface_bank6_lock = main_litedramcore_bankmachine6_req_lock;
+assign main_litedramcore_interface_bank6_wdata_ready = main_litedramcore_bankmachine6_req_wdata_ready;
+assign main_litedramcore_interface_bank6_rdata_valid = main_litedramcore_bankmachine6_req_rdata_valid;
+assign main_litedramcore_bankmachine7_req_valid = main_litedramcore_interface_bank7_valid;
+assign main_litedramcore_interface_bank7_ready = main_litedramcore_bankmachine7_req_ready;
+assign main_litedramcore_bankmachine7_req_we = main_litedramcore_interface_bank7_we;
+assign main_litedramcore_bankmachine7_req_addr = main_litedramcore_interface_bank7_addr;
+assign main_litedramcore_interface_bank7_lock = main_litedramcore_bankmachine7_req_lock;
+assign main_litedramcore_interface_bank7_wdata_ready = main_litedramcore_bankmachine7_req_wdata_ready;
+assign main_litedramcore_interface_bank7_rdata_valid = main_litedramcore_bankmachine7_req_rdata_valid;
+assign main_litedramcore_timer_wait = (~main_litedramcore_timer_done0);
+assign main_litedramcore_postponer_req_i = main_litedramcore_timer_done0;
+assign main_litedramcore_wants_refresh = main_litedramcore_postponer_req_o;
+assign main_litedramcore_wants_zqcs = main_litedramcore_zqcs_timer_done0;
+assign main_litedramcore_zqcs_timer_wait = (~main_litedramcore_zqcs_executer_done);
+assign main_litedramcore_timer_done1 = (main_litedramcore_timer_count1 == 1'd0);
+assign main_litedramcore_timer_done0 = main_litedramcore_timer_done1;
+assign main_litedramcore_timer_count0 = main_litedramcore_timer_count1;
+assign main_litedramcore_sequencer_start1 = (main_litedramcore_sequencer_start0 | (main_litedramcore_sequencer_count != 1'd0));
+assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 & (main_litedramcore_sequencer_count == 1'd0));
+assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0);
+assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1;
+assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1;
+always @(*) begin
+    builder_refresher_next_state <= 2'd0;
+    builder_refresher_next_state <= builder_refresher_state;
+    case (builder_refresher_state)
+        1'd1: begin
+            if (main_litedramcore_cmd_ready) begin
+                builder_refresher_next_state <= 2'd2;
+            end
+        end
+        2'd2: begin
+            if (main_litedramcore_sequencer_done0) begin
+                if (main_litedramcore_wants_zqcs) begin
+                    builder_refresher_next_state <= 2'd3;
                 end else begin
-                    litedramcore_refresher_next_state <= 1'd0;
+                    builder_refresher_next_state <= 1'd0;
                 end
             end
         end
         2'd3: begin
-            if (litedramcore_zqcs_executer_done) begin
-                litedramcore_refresher_next_state <= 1'd0;
+            if (main_litedramcore_zqcs_executer_done) begin
+                builder_refresher_next_state <= 1'd0;
             end
         end
         default: begin
             if (1'd1) begin
-                if (litedramcore_wants_refresh) begin
-                    litedramcore_refresher_next_state <= 1'd1;
+                if (main_litedramcore_wants_refresh) begin
+                    builder_refresher_next_state <= 1'd1;
                 end
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_sequencer_start0 <= 1'd0;
-    case (litedramcore_refresher_state)
+    main_litedramcore_sequencer_start0 <= 1'd0;
+    case (builder_refresher_state)
         1'd1: begin
-            if (litedramcore_cmd_ready) begin
-                litedramcore_sequencer_start0 <= 1'd1;
+            if (main_litedramcore_cmd_ready) begin
+                main_litedramcore_sequencer_start0 <= 1'd1;
             end
         end
         2'd2: begin
@@ -4683,24 +5102,24 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_cmd_valid <= 1'd0;
-    case (litedramcore_refresher_state)
+    main_litedramcore_cmd_valid <= 1'd0;
+    case (builder_refresher_state)
         1'd1: begin
-            litedramcore_cmd_valid <= 1'd1;
+            main_litedramcore_cmd_valid <= 1'd1;
         end
         2'd2: begin
-            litedramcore_cmd_valid <= 1'd1;
-            if (litedramcore_sequencer_done0) begin
-                if (litedramcore_wants_zqcs) begin
+            main_litedramcore_cmd_valid <= 1'd1;
+            if (main_litedramcore_sequencer_done0) begin
+                if (main_litedramcore_wants_zqcs) begin
                 end else begin
-                    litedramcore_cmd_valid <= 1'd0;
+                    main_litedramcore_cmd_valid <= 1'd0;
                 end
             end
         end
         2'd3: begin
-            litedramcore_cmd_valid <= 1'd1;
-            if (litedramcore_zqcs_executer_done) begin
-                litedramcore_cmd_valid <= 1'd0;
+            main_litedramcore_cmd_valid <= 1'd1;
+            if (main_litedramcore_zqcs_executer_done) begin
+                main_litedramcore_cmd_valid <= 1'd0;
             end
         end
         default: begin
@@ -4708,14 +5127,14 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_zqcs_executer_start <= 1'd0;
-    case (litedramcore_refresher_state)
+    main_litedramcore_zqcs_executer_start <= 1'd0;
+    case (builder_refresher_state)
         1'd1: begin
         end
         2'd2: begin
-            if (litedramcore_sequencer_done0) begin
-                if (litedramcore_wants_zqcs) begin
-                    litedramcore_zqcs_executer_start <= 1'd1;
+            if (main_litedramcore_sequencer_done0) begin
+                if (main_litedramcore_wants_zqcs) begin
+                    main_litedramcore_zqcs_executer_start <= 1'd1;
                 end else begin
                 end
             end
@@ -4727,160 +5146,160 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_cmd_last <= 1'd0;
-    case (litedramcore_refresher_state)
+    main_litedramcore_cmd_last <= 1'd0;
+    case (builder_refresher_state)
         1'd1: begin
         end
         2'd2: begin
-            if (litedramcore_sequencer_done0) begin
-                if (litedramcore_wants_zqcs) begin
+            if (main_litedramcore_sequencer_done0) begin
+                if (main_litedramcore_wants_zqcs) begin
                 end else begin
-                    litedramcore_cmd_last <= 1'd1;
+                    main_litedramcore_cmd_last <= 1'd1;
                 end
             end
         end
         2'd3: begin
-            if (litedramcore_zqcs_executer_done) begin
-                litedramcore_cmd_last <= 1'd1;
-            end
-        end
-        default: begin
-        end
-    endcase
-end
-assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid;
-assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready;
-assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we;
-assign litedramcore_bankmachine0_sink_payload_addr = litedramcore_bankmachine0_req_addr;
-assign litedramcore_bankmachine0_sink_sink_valid = litedramcore_bankmachine0_source_valid;
-assign litedramcore_bankmachine0_source_ready = litedramcore_bankmachine0_sink_sink_ready;
-assign litedramcore_bankmachine0_sink_sink_first = litedramcore_bankmachine0_source_first;
-assign litedramcore_bankmachine0_sink_sink_last = litedramcore_bankmachine0_source_last;
-assign litedramcore_bankmachine0_sink_sink_payload_we = litedramcore_bankmachine0_source_payload_we;
-assign litedramcore_bankmachine0_sink_sink_payload_addr = litedramcore_bankmachine0_source_payload_addr;
-assign litedramcore_bankmachine0_source_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
-assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_source_valid | litedramcore_bankmachine0_source_source_valid);
-assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_source_source_payload_addr[21:7]);
-assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
-always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_a <= 15'd0;
-    if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
-        litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_source_source_payload_addr[21:7];
-    end else begin
-        litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
-assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
-assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
-always @(*) begin
-    litedramcore_bankmachine0_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine0_source_valid & litedramcore_bankmachine0_source_source_valid)) begin
-        if ((litedramcore_bankmachine0_source_payload_addr[21:7] != litedramcore_bankmachine0_source_source_payload_addr[21:7])) begin
-            litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine0_syncfifo0_din = {litedramcore_bankmachine0_fifo_in_last, litedramcore_bankmachine0_fifo_in_first, litedramcore_bankmachine0_fifo_in_payload_addr, litedramcore_bankmachine0_fifo_in_payload_we};
-assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
-assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
-assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
-assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
-assign litedramcore_bankmachine0_sink_ready = litedramcore_bankmachine0_syncfifo0_writable;
-assign litedramcore_bankmachine0_syncfifo0_we = litedramcore_bankmachine0_sink_valid;
-assign litedramcore_bankmachine0_fifo_in_first = litedramcore_bankmachine0_sink_first;
-assign litedramcore_bankmachine0_fifo_in_last = litedramcore_bankmachine0_sink_last;
-assign litedramcore_bankmachine0_fifo_in_payload_we = litedramcore_bankmachine0_sink_payload_we;
-assign litedramcore_bankmachine0_fifo_in_payload_addr = litedramcore_bankmachine0_sink_payload_addr;
-assign litedramcore_bankmachine0_source_valid = litedramcore_bankmachine0_syncfifo0_readable;
-assign litedramcore_bankmachine0_source_first = litedramcore_bankmachine0_fifo_out_first;
-assign litedramcore_bankmachine0_source_last = litedramcore_bankmachine0_fifo_out_last;
-assign litedramcore_bankmachine0_source_payload_we = litedramcore_bankmachine0_fifo_out_payload_we;
-assign litedramcore_bankmachine0_source_payload_addr = litedramcore_bankmachine0_fifo_out_payload_addr;
-assign litedramcore_bankmachine0_syncfifo0_re = litedramcore_bankmachine0_source_ready;
-always @(*) begin
-    litedramcore_bankmachine0_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine0_replace) begin
-        litedramcore_bankmachine0_wrport_adr <= (litedramcore_bankmachine0_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine0_wrport_adr <= litedramcore_bankmachine0_produce;
-    end
-end
-assign litedramcore_bankmachine0_wrport_dat_w = litedramcore_bankmachine0_syncfifo0_din;
-assign litedramcore_bankmachine0_wrport_we = (litedramcore_bankmachine0_syncfifo0_we & (litedramcore_bankmachine0_syncfifo0_writable | litedramcore_bankmachine0_replace));
-assign litedramcore_bankmachine0_do_read = (litedramcore_bankmachine0_syncfifo0_readable & litedramcore_bankmachine0_syncfifo0_re);
-assign litedramcore_bankmachine0_rdport_adr = litedramcore_bankmachine0_consume;
-assign litedramcore_bankmachine0_syncfifo0_dout = litedramcore_bankmachine0_rdport_dat_r;
-assign litedramcore_bankmachine0_syncfifo0_writable = (litedramcore_bankmachine0_level != 5'd16);
-assign litedramcore_bankmachine0_syncfifo0_readable = (litedramcore_bankmachine0_level != 1'd0);
-assign litedramcore_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready);
-assign litedramcore_bankmachine0_pipe_valid_sink_valid = litedramcore_bankmachine0_sink_sink_valid;
-assign litedramcore_bankmachine0_sink_sink_ready = litedramcore_bankmachine0_pipe_valid_sink_ready;
-assign litedramcore_bankmachine0_pipe_valid_sink_first = litedramcore_bankmachine0_sink_sink_first;
-assign litedramcore_bankmachine0_pipe_valid_sink_last = litedramcore_bankmachine0_sink_sink_last;
-assign litedramcore_bankmachine0_pipe_valid_sink_payload_we = litedramcore_bankmachine0_sink_sink_payload_we;
-assign litedramcore_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_bankmachine0_sink_sink_payload_addr;
-assign litedramcore_bankmachine0_source_source_valid = litedramcore_bankmachine0_pipe_valid_source_valid;
-assign litedramcore_bankmachine0_pipe_valid_source_ready = litedramcore_bankmachine0_source_source_ready;
-assign litedramcore_bankmachine0_source_source_first = litedramcore_bankmachine0_pipe_valid_source_first;
-assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_pipe_valid_source_last;
-assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine0_next_state <= 4'd0;
-    litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
-    case (litedramcore_bankmachine0_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                if (litedramcore_bankmachine0_cmd_ready) begin
-                    litedramcore_bankmachine0_next_state <= 3'd5;
+            if (main_litedramcore_zqcs_executer_done) begin
+                main_litedramcore_cmd_last <= 1'd1;
+            end
+        end
+        default: begin
+        end
+    endcase
+end
+assign main_litedramcore_bankmachine0_sink_valid = main_litedramcore_bankmachine0_req_valid;
+assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_sink_ready;
+assign main_litedramcore_bankmachine0_sink_payload_we = main_litedramcore_bankmachine0_req_we;
+assign main_litedramcore_bankmachine0_sink_payload_addr = main_litedramcore_bankmachine0_req_addr;
+assign main_litedramcore_bankmachine0_sink_sink_valid = main_litedramcore_bankmachine0_source_valid;
+assign main_litedramcore_bankmachine0_source_ready = main_litedramcore_bankmachine0_sink_sink_ready;
+assign main_litedramcore_bankmachine0_sink_sink_first = main_litedramcore_bankmachine0_source_first;
+assign main_litedramcore_bankmachine0_sink_sink_last = main_litedramcore_bankmachine0_source_last;
+assign main_litedramcore_bankmachine0_sink_sink_payload_we = main_litedramcore_bankmachine0_source_payload_we;
+assign main_litedramcore_bankmachine0_sink_sink_payload_addr = main_litedramcore_bankmachine0_source_payload_addr;
+assign main_litedramcore_bankmachine0_source_source_ready = (main_litedramcore_bankmachine0_req_wdata_ready | main_litedramcore_bankmachine0_req_rdata_valid);
+assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_source_valid | main_litedramcore_bankmachine0_source_source_valid);
+assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_source_source_payload_addr[21:7]);
+assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
+always @(*) begin
+    main_litedramcore_bankmachine0_cmd_payload_a <= 15'd0;
+    if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine0_cmd_payload_a <= main_litedramcore_bankmachine0_source_source_payload_addr[21:7];
+    end else begin
+        main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write);
+assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
+assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine0_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine0_source_valid & main_litedramcore_bankmachine0_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine0_source_payload_addr[21:7] != main_litedramcore_bankmachine0_source_source_payload_addr[21:7])) begin
+            main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine0_syncfifo0_din = {main_litedramcore_bankmachine0_fifo_in_last, main_litedramcore_bankmachine0_fifo_in_first, main_litedramcore_bankmachine0_fifo_in_payload_addr, main_litedramcore_bankmachine0_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout;
+assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout;
+assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout;
+assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout;
+assign main_litedramcore_bankmachine0_sink_ready = main_litedramcore_bankmachine0_syncfifo0_writable;
+assign main_litedramcore_bankmachine0_syncfifo0_we = main_litedramcore_bankmachine0_sink_valid;
+assign main_litedramcore_bankmachine0_fifo_in_first = main_litedramcore_bankmachine0_sink_first;
+assign main_litedramcore_bankmachine0_fifo_in_last = main_litedramcore_bankmachine0_sink_last;
+assign main_litedramcore_bankmachine0_fifo_in_payload_we = main_litedramcore_bankmachine0_sink_payload_we;
+assign main_litedramcore_bankmachine0_fifo_in_payload_addr = main_litedramcore_bankmachine0_sink_payload_addr;
+assign main_litedramcore_bankmachine0_source_valid = main_litedramcore_bankmachine0_syncfifo0_readable;
+assign main_litedramcore_bankmachine0_source_first = main_litedramcore_bankmachine0_fifo_out_first;
+assign main_litedramcore_bankmachine0_source_last = main_litedramcore_bankmachine0_fifo_out_last;
+assign main_litedramcore_bankmachine0_source_payload_we = main_litedramcore_bankmachine0_fifo_out_payload_we;
+assign main_litedramcore_bankmachine0_source_payload_addr = main_litedramcore_bankmachine0_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine0_syncfifo0_re = main_litedramcore_bankmachine0_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine0_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine0_replace) begin
+        main_litedramcore_bankmachine0_wrport_adr <= (main_litedramcore_bankmachine0_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine0_wrport_adr <= main_litedramcore_bankmachine0_produce;
+    end
+end
+assign main_litedramcore_bankmachine0_wrport_dat_w = main_litedramcore_bankmachine0_syncfifo0_din;
+assign main_litedramcore_bankmachine0_wrport_we = (main_litedramcore_bankmachine0_syncfifo0_we & (main_litedramcore_bankmachine0_syncfifo0_writable | main_litedramcore_bankmachine0_replace));
+assign main_litedramcore_bankmachine0_do_read = (main_litedramcore_bankmachine0_syncfifo0_readable & main_litedramcore_bankmachine0_syncfifo0_re);
+assign main_litedramcore_bankmachine0_rdport_adr = main_litedramcore_bankmachine0_consume;
+assign main_litedramcore_bankmachine0_syncfifo0_dout = main_litedramcore_bankmachine0_rdport_dat_r;
+assign main_litedramcore_bankmachine0_syncfifo0_writable = (main_litedramcore_bankmachine0_level != 5'd16);
+assign main_litedramcore_bankmachine0_syncfifo0_readable = (main_litedramcore_bankmachine0_level != 1'd0);
+assign main_litedramcore_bankmachine0_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine0_pipe_valid_source_valid) | main_litedramcore_bankmachine0_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine0_pipe_valid_sink_valid = main_litedramcore_bankmachine0_sink_sink_valid;
+assign main_litedramcore_bankmachine0_sink_sink_ready = main_litedramcore_bankmachine0_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine0_pipe_valid_sink_first = main_litedramcore_bankmachine0_sink_sink_first;
+assign main_litedramcore_bankmachine0_pipe_valid_sink_last = main_litedramcore_bankmachine0_sink_sink_last;
+assign main_litedramcore_bankmachine0_pipe_valid_sink_payload_we = main_litedramcore_bankmachine0_sink_sink_payload_we;
+assign main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine0_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine0_source_source_valid = main_litedramcore_bankmachine0_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine0_pipe_valid_source_ready = main_litedramcore_bankmachine0_source_source_ready;
+assign main_litedramcore_bankmachine0_source_source_first = main_litedramcore_bankmachine0_pipe_valid_source_first;
+assign main_litedramcore_bankmachine0_source_source_last = main_litedramcore_bankmachine0_pipe_valid_source_last;
+assign main_litedramcore_bankmachine0_source_source_payload_we = main_litedramcore_bankmachine0_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine0_source_source_payload_addr = main_litedramcore_bankmachine0_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine0_next_state <= 4'd0;
+    builder_bankmachine0_next_state <= builder_bankmachine0_state;
+    case (builder_bankmachine0_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                if (main_litedramcore_bankmachine0_cmd_ready) begin
+                    builder_bankmachine0_next_state <= 3'd5;
                 end
             end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_next_state <= 3'd5;
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                builder_bankmachine0_next_state <= 3'd5;
             end
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                if (litedramcore_bankmachine0_cmd_ready) begin
-                    litedramcore_bankmachine0_next_state <= 3'd7;
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                if (main_litedramcore_bankmachine0_cmd_ready) begin
+                    builder_bankmachine0_next_state <= 3'd7;
                 end
             end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine0_refresh_req)) begin
-                litedramcore_bankmachine0_next_state <= 1'd0;
+            if ((~main_litedramcore_bankmachine0_refresh_req)) begin
+                builder_bankmachine0_next_state <= 1'd0;
             end
         end
         3'd5: begin
-            litedramcore_bankmachine0_next_state <= 3'd6;
+            builder_bankmachine0_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine0_next_state <= 2'd3;
+            builder_bankmachine0_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine0_next_state <= 4'd8;
+            builder_bankmachine0_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine0_next_state <= 1'd0;
+            builder_bankmachine0_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
-                litedramcore_bankmachine0_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine0_refresh_req) begin
+                builder_bankmachine0_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
-                                litedramcore_bankmachine0_next_state <= 2'd2;
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if ((main_litedramcore_bankmachine0_cmd_ready & main_litedramcore_bankmachine0_auto_precharge)) begin
+                                builder_bankmachine0_next_state <= 2'd2;
                             end
                         end else begin
-                            litedramcore_bankmachine0_next_state <= 1'd1;
+                            builder_bankmachine0_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine0_next_state <= 2'd3;
+                        builder_bankmachine0_next_state <= 2'd3;
                     end
                 end
             end
@@ -4888,15 +5307,41 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_row_close <= 1'd0;
+    case (builder_bankmachine0_state)
+        1'd1: begin
+            main_litedramcore_bankmachine0_row_close <= 1'd1;
+        end
+        2'd2: begin
+            main_litedramcore_bankmachine0_row_close <= 1'd1;
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            main_litedramcore_bankmachine0_row_close <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -4914,8 +5359,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -4933,12 +5378,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -4949,18 +5394,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -4978,11 +5423,11 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
@@ -5000,13 +5445,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
-                                litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
+                                main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -5019,22 +5464,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -5049,8 +5494,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5068,14 +5513,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -5087,8 +5532,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5106,13 +5551,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
-                                litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
+                                main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -5125,8 +5570,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5144,13 +5589,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
-                                litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
+                                main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -5163,8 +5608,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5182,14 +5627,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
+                                main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
                             end
                         end else begin
                         end
@@ -5201,8 +5646,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5210,8 +5655,8 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine0_twtpcon_ready) begin
-                litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+            if (main_litedramcore_bankmachine0_twtpcon_ready) begin
+                main_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
             end
         end
         3'd5: begin
@@ -5227,15 +5672,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_row_open <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_row_open <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -5253,18 +5698,21 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_row_close <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_valid <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
-            litedramcore_bankmachine0_row_close <= 1'd1;
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+            end
         end
         2'd2: begin
-            litedramcore_bankmachine0_row_close <= 1'd1;
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+            end
         end
         3'd4: begin
-            litedramcore_bankmachine0_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -5275,183 +5723,189 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine0_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+assign main_litedramcore_bankmachine1_sink_valid = main_litedramcore_bankmachine1_req_valid;
+assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_sink_ready;
+assign main_litedramcore_bankmachine1_sink_payload_we = main_litedramcore_bankmachine1_req_we;
+assign main_litedramcore_bankmachine1_sink_payload_addr = main_litedramcore_bankmachine1_req_addr;
+assign main_litedramcore_bankmachine1_sink_sink_valid = main_litedramcore_bankmachine1_source_valid;
+assign main_litedramcore_bankmachine1_source_ready = main_litedramcore_bankmachine1_sink_sink_ready;
+assign main_litedramcore_bankmachine1_sink_sink_first = main_litedramcore_bankmachine1_source_first;
+assign main_litedramcore_bankmachine1_sink_sink_last = main_litedramcore_bankmachine1_source_last;
+assign main_litedramcore_bankmachine1_sink_sink_payload_we = main_litedramcore_bankmachine1_source_payload_we;
+assign main_litedramcore_bankmachine1_sink_sink_payload_addr = main_litedramcore_bankmachine1_source_payload_addr;
+assign main_litedramcore_bankmachine1_source_source_ready = (main_litedramcore_bankmachine1_req_wdata_ready | main_litedramcore_bankmachine1_req_rdata_valid);
+assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_source_valid | main_litedramcore_bankmachine1_source_source_valid);
+assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_source_source_payload_addr[21:7]);
+assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
+always @(*) begin
+    main_litedramcore_bankmachine1_cmd_payload_a <= 15'd0;
+    if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine1_cmd_payload_a <= main_litedramcore_bankmachine1_source_source_payload_addr[21:7];
+    end else begin
+        main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write);
+assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
+assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine1_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine1_source_valid & main_litedramcore_bankmachine1_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine1_source_payload_addr[21:7] != main_litedramcore_bankmachine1_source_source_payload_addr[21:7])) begin
+            main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine1_syncfifo1_din = {main_litedramcore_bankmachine1_fifo_in_last, main_litedramcore_bankmachine1_fifo_in_first, main_litedramcore_bankmachine1_fifo_in_payload_addr, main_litedramcore_bankmachine1_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout;
+assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout;
+assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout;
+assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout;
+assign main_litedramcore_bankmachine1_sink_ready = main_litedramcore_bankmachine1_syncfifo1_writable;
+assign main_litedramcore_bankmachine1_syncfifo1_we = main_litedramcore_bankmachine1_sink_valid;
+assign main_litedramcore_bankmachine1_fifo_in_first = main_litedramcore_bankmachine1_sink_first;
+assign main_litedramcore_bankmachine1_fifo_in_last = main_litedramcore_bankmachine1_sink_last;
+assign main_litedramcore_bankmachine1_fifo_in_payload_we = main_litedramcore_bankmachine1_sink_payload_we;
+assign main_litedramcore_bankmachine1_fifo_in_payload_addr = main_litedramcore_bankmachine1_sink_payload_addr;
+assign main_litedramcore_bankmachine1_source_valid = main_litedramcore_bankmachine1_syncfifo1_readable;
+assign main_litedramcore_bankmachine1_source_first = main_litedramcore_bankmachine1_fifo_out_first;
+assign main_litedramcore_bankmachine1_source_last = main_litedramcore_bankmachine1_fifo_out_last;
+assign main_litedramcore_bankmachine1_source_payload_we = main_litedramcore_bankmachine1_fifo_out_payload_we;
+assign main_litedramcore_bankmachine1_source_payload_addr = main_litedramcore_bankmachine1_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine1_syncfifo1_re = main_litedramcore_bankmachine1_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine1_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine1_replace) begin
+        main_litedramcore_bankmachine1_wrport_adr <= (main_litedramcore_bankmachine1_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine1_wrport_adr <= main_litedramcore_bankmachine1_produce;
+    end
+end
+assign main_litedramcore_bankmachine1_wrport_dat_w = main_litedramcore_bankmachine1_syncfifo1_din;
+assign main_litedramcore_bankmachine1_wrport_we = (main_litedramcore_bankmachine1_syncfifo1_we & (main_litedramcore_bankmachine1_syncfifo1_writable | main_litedramcore_bankmachine1_replace));
+assign main_litedramcore_bankmachine1_do_read = (main_litedramcore_bankmachine1_syncfifo1_readable & main_litedramcore_bankmachine1_syncfifo1_re);
+assign main_litedramcore_bankmachine1_rdport_adr = main_litedramcore_bankmachine1_consume;
+assign main_litedramcore_bankmachine1_syncfifo1_dout = main_litedramcore_bankmachine1_rdport_dat_r;
+assign main_litedramcore_bankmachine1_syncfifo1_writable = (main_litedramcore_bankmachine1_level != 5'd16);
+assign main_litedramcore_bankmachine1_syncfifo1_readable = (main_litedramcore_bankmachine1_level != 1'd0);
+assign main_litedramcore_bankmachine1_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine1_pipe_valid_source_valid) | main_litedramcore_bankmachine1_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine1_pipe_valid_sink_valid = main_litedramcore_bankmachine1_sink_sink_valid;
+assign main_litedramcore_bankmachine1_sink_sink_ready = main_litedramcore_bankmachine1_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine1_pipe_valid_sink_first = main_litedramcore_bankmachine1_sink_sink_first;
+assign main_litedramcore_bankmachine1_pipe_valid_sink_last = main_litedramcore_bankmachine1_sink_sink_last;
+assign main_litedramcore_bankmachine1_pipe_valid_sink_payload_we = main_litedramcore_bankmachine1_sink_sink_payload_we;
+assign main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine1_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine1_source_source_valid = main_litedramcore_bankmachine1_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine1_pipe_valid_source_ready = main_litedramcore_bankmachine1_source_source_ready;
+assign main_litedramcore_bankmachine1_source_source_first = main_litedramcore_bankmachine1_pipe_valid_source_first;
+assign main_litedramcore_bankmachine1_source_source_last = main_litedramcore_bankmachine1_pipe_valid_source_last;
+assign main_litedramcore_bankmachine1_source_source_payload_we = main_litedramcore_bankmachine1_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine1_source_source_payload_addr = main_litedramcore_bankmachine1_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine1_next_state <= 4'd0;
+    builder_bankmachine1_next_state <= builder_bankmachine1_state;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                if (main_litedramcore_bankmachine1_cmd_ready) begin
+                    builder_bankmachine1_next_state <= 3'd5;
+                end
             end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                builder_bankmachine1_next_state <= 3'd5;
+            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                if (main_litedramcore_bankmachine1_cmd_ready) begin
+                    builder_bankmachine1_next_state <= 3'd7;
+                end
             end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine1_refresh_req)) begin
+                builder_bankmachine1_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine1_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine1_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine1_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine1_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
+                builder_bankmachine1_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            litedramcore_bankmachine0_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if ((main_litedramcore_bankmachine1_cmd_ready & main_litedramcore_bankmachine1_auto_precharge)) begin
+                                builder_bankmachine1_next_state <= 2'd2;
+                            end
                         end else begin
+                            builder_bankmachine1_next_state <= 1'd1;
                         end
                     end else begin
+                        builder_bankmachine1_next_state <= 2'd3;
                     end
                 end
             end
         end
     endcase
 end
-assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid;
-assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready;
-assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we;
-assign litedramcore_bankmachine1_sink_payload_addr = litedramcore_bankmachine1_req_addr;
-assign litedramcore_bankmachine1_sink_sink_valid = litedramcore_bankmachine1_source_valid;
-assign litedramcore_bankmachine1_source_ready = litedramcore_bankmachine1_sink_sink_ready;
-assign litedramcore_bankmachine1_sink_sink_first = litedramcore_bankmachine1_source_first;
-assign litedramcore_bankmachine1_sink_sink_last = litedramcore_bankmachine1_source_last;
-assign litedramcore_bankmachine1_sink_sink_payload_we = litedramcore_bankmachine1_source_payload_we;
-assign litedramcore_bankmachine1_sink_sink_payload_addr = litedramcore_bankmachine1_source_payload_addr;
-assign litedramcore_bankmachine1_source_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
-assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_source_valid | litedramcore_bankmachine1_source_source_valid);
-assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_source_source_payload_addr[21:7]);
-assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
-always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_a <= 15'd0;
-    if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
-        litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_source_source_payload_addr[21:7];
-    end else begin
-        litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
-assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
-assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
-always @(*) begin
-    litedramcore_bankmachine1_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine1_source_valid & litedramcore_bankmachine1_source_source_valid)) begin
-        if ((litedramcore_bankmachine1_source_payload_addr[21:7] != litedramcore_bankmachine1_source_source_payload_addr[21:7])) begin
-            litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine1_syncfifo1_din = {litedramcore_bankmachine1_fifo_in_last, litedramcore_bankmachine1_fifo_in_first, litedramcore_bankmachine1_fifo_in_payload_addr, litedramcore_bankmachine1_fifo_in_payload_we};
-assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
-assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
-assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
-assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
-assign litedramcore_bankmachine1_sink_ready = litedramcore_bankmachine1_syncfifo1_writable;
-assign litedramcore_bankmachine1_syncfifo1_we = litedramcore_bankmachine1_sink_valid;
-assign litedramcore_bankmachine1_fifo_in_first = litedramcore_bankmachine1_sink_first;
-assign litedramcore_bankmachine1_fifo_in_last = litedramcore_bankmachine1_sink_last;
-assign litedramcore_bankmachine1_fifo_in_payload_we = litedramcore_bankmachine1_sink_payload_we;
-assign litedramcore_bankmachine1_fifo_in_payload_addr = litedramcore_bankmachine1_sink_payload_addr;
-assign litedramcore_bankmachine1_source_valid = litedramcore_bankmachine1_syncfifo1_readable;
-assign litedramcore_bankmachine1_source_first = litedramcore_bankmachine1_fifo_out_first;
-assign litedramcore_bankmachine1_source_last = litedramcore_bankmachine1_fifo_out_last;
-assign litedramcore_bankmachine1_source_payload_we = litedramcore_bankmachine1_fifo_out_payload_we;
-assign litedramcore_bankmachine1_source_payload_addr = litedramcore_bankmachine1_fifo_out_payload_addr;
-assign litedramcore_bankmachine1_syncfifo1_re = litedramcore_bankmachine1_source_ready;
-always @(*) begin
-    litedramcore_bankmachine1_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine1_replace) begin
-        litedramcore_bankmachine1_wrport_adr <= (litedramcore_bankmachine1_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine1_wrport_adr <= litedramcore_bankmachine1_produce;
-    end
-end
-assign litedramcore_bankmachine1_wrport_dat_w = litedramcore_bankmachine1_syncfifo1_din;
-assign litedramcore_bankmachine1_wrport_we = (litedramcore_bankmachine1_syncfifo1_we & (litedramcore_bankmachine1_syncfifo1_writable | litedramcore_bankmachine1_replace));
-assign litedramcore_bankmachine1_do_read = (litedramcore_bankmachine1_syncfifo1_readable & litedramcore_bankmachine1_syncfifo1_re);
-assign litedramcore_bankmachine1_rdport_adr = litedramcore_bankmachine1_consume;
-assign litedramcore_bankmachine1_syncfifo1_dout = litedramcore_bankmachine1_rdport_dat_r;
-assign litedramcore_bankmachine1_syncfifo1_writable = (litedramcore_bankmachine1_level != 5'd16);
-assign litedramcore_bankmachine1_syncfifo1_readable = (litedramcore_bankmachine1_level != 1'd0);
-assign litedramcore_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready);
-assign litedramcore_bankmachine1_pipe_valid_sink_valid = litedramcore_bankmachine1_sink_sink_valid;
-assign litedramcore_bankmachine1_sink_sink_ready = litedramcore_bankmachine1_pipe_valid_sink_ready;
-assign litedramcore_bankmachine1_pipe_valid_sink_first = litedramcore_bankmachine1_sink_sink_first;
-assign litedramcore_bankmachine1_pipe_valid_sink_last = litedramcore_bankmachine1_sink_sink_last;
-assign litedramcore_bankmachine1_pipe_valid_sink_payload_we = litedramcore_bankmachine1_sink_sink_payload_we;
-assign litedramcore_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_bankmachine1_sink_sink_payload_addr;
-assign litedramcore_bankmachine1_source_source_valid = litedramcore_bankmachine1_pipe_valid_source_valid;
-assign litedramcore_bankmachine1_pipe_valid_source_ready = litedramcore_bankmachine1_source_source_ready;
-assign litedramcore_bankmachine1_source_source_first = litedramcore_bankmachine1_pipe_valid_source_first;
-assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_pipe_valid_source_last;
-assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine1_next_state <= 4'd0;
-    litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
-    case (litedramcore_bankmachine1_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                if (litedramcore_bankmachine1_cmd_ready) begin
-                    litedramcore_bankmachine1_next_state <= 3'd5;
-                end
-            end
+always @(*) begin
+    main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine1_state)
+        1'd1: begin
         end
         2'd2: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                if (litedramcore_bankmachine1_cmd_ready) begin
-                    litedramcore_bankmachine1_next_state <= 3'd7;
-                end
-            end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine1_refresh_req)) begin
-                litedramcore_bankmachine1_next_state <= 1'd0;
-            end
         end
         3'd5: begin
-            litedramcore_bankmachine1_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine1_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine1_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine1_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
-                litedramcore_bankmachine1_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine1_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
-                                litedramcore_bankmachine1_next_state <= 2'd2;
-                            end
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
                         end else begin
-                            litedramcore_bankmachine1_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine1_next_state <= 2'd3;
                     end
                 end
             end
@@ -5459,11 +5913,40 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine1_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
@@ -5481,13 +5964,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                                litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
+                                main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -5500,22 +5983,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -5530,8 +6013,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5549,14 +6032,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -5568,8 +6051,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5587,13 +6070,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                                litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
+                                main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -5606,8 +6089,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5625,13 +6108,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                                litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
+                                main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -5644,8 +6127,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5663,14 +6146,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
+                                main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
                             end
                         end else begin
                         end
@@ -5682,18 +6165,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
-            end
         end
         3'd4: begin
+            if (main_litedramcore_bankmachine1_twtpcon_ready) begin
+                main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -5708,15 +6191,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_row_open <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_row_open <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -5734,18 +6217,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -5759,12 +6242,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            litedramcore_bankmachine1_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -5775,18 +6258,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_row_close <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_row_close <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            litedramcore_bankmachine1_row_close <= 1'd1;
+            main_litedramcore_bankmachine1_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine1_row_close <= 1'd1;
+            main_litedramcore_bankmachine1_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine1_row_close <= 1'd1;
+            main_litedramcore_bankmachine1_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -5801,18 +6284,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
+            end
         end
         3'd4: begin
-            if (litedramcore_bankmachine1_twtpcon_ready) begin
-                litedramcore_bankmachine1_refresh_gnt <= 1'd1;
-            end
         end
         3'd5: begin
         end
@@ -5826,35 +6309,139 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid;
+assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready;
+assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we;
+assign main_litedramcore_bankmachine2_sink_payload_addr = main_litedramcore_bankmachine2_req_addr;
+assign main_litedramcore_bankmachine2_sink_sink_valid = main_litedramcore_bankmachine2_source_valid;
+assign main_litedramcore_bankmachine2_source_ready = main_litedramcore_bankmachine2_sink_sink_ready;
+assign main_litedramcore_bankmachine2_sink_sink_first = main_litedramcore_bankmachine2_source_first;
+assign main_litedramcore_bankmachine2_sink_sink_last = main_litedramcore_bankmachine2_source_last;
+assign main_litedramcore_bankmachine2_sink_sink_payload_we = main_litedramcore_bankmachine2_source_payload_we;
+assign main_litedramcore_bankmachine2_sink_sink_payload_addr = main_litedramcore_bankmachine2_source_payload_addr;
+assign main_litedramcore_bankmachine2_source_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid);
+assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_source_valid | main_litedramcore_bankmachine2_source_source_valid);
+assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_source_source_payload_addr[21:7]);
+assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
+always @(*) begin
+    main_litedramcore_bankmachine2_cmd_payload_a <= 15'd0;
+    if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine2_cmd_payload_a <= main_litedramcore_bankmachine2_source_source_payload_addr[21:7];
+    end else begin
+        main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write);
+assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
+assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine2_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine2_source_valid & main_litedramcore_bankmachine2_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine2_source_payload_addr[21:7] != main_litedramcore_bankmachine2_source_source_payload_addr[21:7])) begin
+            main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine2_syncfifo2_din = {main_litedramcore_bankmachine2_fifo_in_last, main_litedramcore_bankmachine2_fifo_in_first, main_litedramcore_bankmachine2_fifo_in_payload_addr, main_litedramcore_bankmachine2_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
+assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
+assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
+assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
+assign main_litedramcore_bankmachine2_sink_ready = main_litedramcore_bankmachine2_syncfifo2_writable;
+assign main_litedramcore_bankmachine2_syncfifo2_we = main_litedramcore_bankmachine2_sink_valid;
+assign main_litedramcore_bankmachine2_fifo_in_first = main_litedramcore_bankmachine2_sink_first;
+assign main_litedramcore_bankmachine2_fifo_in_last = main_litedramcore_bankmachine2_sink_last;
+assign main_litedramcore_bankmachine2_fifo_in_payload_we = main_litedramcore_bankmachine2_sink_payload_we;
+assign main_litedramcore_bankmachine2_fifo_in_payload_addr = main_litedramcore_bankmachine2_sink_payload_addr;
+assign main_litedramcore_bankmachine2_source_valid = main_litedramcore_bankmachine2_syncfifo2_readable;
+assign main_litedramcore_bankmachine2_source_first = main_litedramcore_bankmachine2_fifo_out_first;
+assign main_litedramcore_bankmachine2_source_last = main_litedramcore_bankmachine2_fifo_out_last;
+assign main_litedramcore_bankmachine2_source_payload_we = main_litedramcore_bankmachine2_fifo_out_payload_we;
+assign main_litedramcore_bankmachine2_source_payload_addr = main_litedramcore_bankmachine2_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine2_syncfifo2_re = main_litedramcore_bankmachine2_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine2_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine2_replace) begin
+        main_litedramcore_bankmachine2_wrport_adr <= (main_litedramcore_bankmachine2_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine2_wrport_adr <= main_litedramcore_bankmachine2_produce;
+    end
+end
+assign main_litedramcore_bankmachine2_wrport_dat_w = main_litedramcore_bankmachine2_syncfifo2_din;
+assign main_litedramcore_bankmachine2_wrport_we = (main_litedramcore_bankmachine2_syncfifo2_we & (main_litedramcore_bankmachine2_syncfifo2_writable | main_litedramcore_bankmachine2_replace));
+assign main_litedramcore_bankmachine2_do_read = (main_litedramcore_bankmachine2_syncfifo2_readable & main_litedramcore_bankmachine2_syncfifo2_re);
+assign main_litedramcore_bankmachine2_rdport_adr = main_litedramcore_bankmachine2_consume;
+assign main_litedramcore_bankmachine2_syncfifo2_dout = main_litedramcore_bankmachine2_rdport_dat_r;
+assign main_litedramcore_bankmachine2_syncfifo2_writable = (main_litedramcore_bankmachine2_level != 5'd16);
+assign main_litedramcore_bankmachine2_syncfifo2_readable = (main_litedramcore_bankmachine2_level != 1'd0);
+assign main_litedramcore_bankmachine2_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine2_pipe_valid_source_valid) | main_litedramcore_bankmachine2_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine2_pipe_valid_sink_valid = main_litedramcore_bankmachine2_sink_sink_valid;
+assign main_litedramcore_bankmachine2_sink_sink_ready = main_litedramcore_bankmachine2_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine2_pipe_valid_sink_first = main_litedramcore_bankmachine2_sink_sink_first;
+assign main_litedramcore_bankmachine2_pipe_valid_sink_last = main_litedramcore_bankmachine2_sink_sink_last;
+assign main_litedramcore_bankmachine2_pipe_valid_sink_payload_we = main_litedramcore_bankmachine2_sink_sink_payload_we;
+assign main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine2_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine2_source_source_valid = main_litedramcore_bankmachine2_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine2_pipe_valid_source_ready = main_litedramcore_bankmachine2_source_source_ready;
+assign main_litedramcore_bankmachine2_source_source_first = main_litedramcore_bankmachine2_pipe_valid_source_first;
+assign main_litedramcore_bankmachine2_source_source_last = main_litedramcore_bankmachine2_pipe_valid_source_last;
+assign main_litedramcore_bankmachine2_source_source_payload_we = main_litedramcore_bankmachine2_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine2_source_source_payload_addr = main_litedramcore_bankmachine2_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine2_next_state <= 4'd0;
+    builder_bankmachine2_next_state <= builder_bankmachine2_state;
+    case (builder_bankmachine2_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                if (main_litedramcore_bankmachine2_cmd_ready) begin
+                    builder_bankmachine2_next_state <= 3'd5;
+                end
+            end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                builder_bankmachine2_next_state <= 3'd5;
+            end
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                if (main_litedramcore_bankmachine2_cmd_ready) begin
+                    builder_bankmachine2_next_state <= 3'd7;
+                end
+            end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine2_refresh_req)) begin
+                builder_bankmachine2_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine2_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine2_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine2_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine2_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
+                builder_bankmachine2_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if ((main_litedramcore_bankmachine2_cmd_ready & main_litedramcore_bankmachine2_auto_precharge)) begin
+                                builder_bankmachine2_next_state <= 2'd2;
+                            end
                         end else begin
+                            builder_bankmachine2_next_state <= 1'd1;
                         end
                     end else begin
+                        builder_bankmachine2_next_state <= 2'd3;
                     end
                 end
             end
@@ -5862,21 +6449,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
+            main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -5890,139 +6478,38 @@ always @(*) begin
         end
     endcase
 end
-assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid;
-assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready;
-assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we;
-assign litedramcore_bankmachine2_sink_payload_addr = litedramcore_bankmachine2_req_addr;
-assign litedramcore_bankmachine2_sink_sink_valid = litedramcore_bankmachine2_source_valid;
-assign litedramcore_bankmachine2_source_ready = litedramcore_bankmachine2_sink_sink_ready;
-assign litedramcore_bankmachine2_sink_sink_first = litedramcore_bankmachine2_source_first;
-assign litedramcore_bankmachine2_sink_sink_last = litedramcore_bankmachine2_source_last;
-assign litedramcore_bankmachine2_sink_sink_payload_we = litedramcore_bankmachine2_source_payload_we;
-assign litedramcore_bankmachine2_sink_sink_payload_addr = litedramcore_bankmachine2_source_payload_addr;
-assign litedramcore_bankmachine2_source_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
-assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_source_valid | litedramcore_bankmachine2_source_source_valid);
-assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_source_source_payload_addr[21:7]);
-assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
-always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_a <= 15'd0;
-    if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
-        litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_source_source_payload_addr[21:7];
-    end else begin
-        litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
-assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
-assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
-always @(*) begin
-    litedramcore_bankmachine2_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine2_source_valid & litedramcore_bankmachine2_source_source_valid)) begin
-        if ((litedramcore_bankmachine2_source_payload_addr[21:7] != litedramcore_bankmachine2_source_source_payload_addr[21:7])) begin
-            litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine2_syncfifo2_din = {litedramcore_bankmachine2_fifo_in_last, litedramcore_bankmachine2_fifo_in_first, litedramcore_bankmachine2_fifo_in_payload_addr, litedramcore_bankmachine2_fifo_in_payload_we};
-assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
-assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
-assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
-assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
-assign litedramcore_bankmachine2_sink_ready = litedramcore_bankmachine2_syncfifo2_writable;
-assign litedramcore_bankmachine2_syncfifo2_we = litedramcore_bankmachine2_sink_valid;
-assign litedramcore_bankmachine2_fifo_in_first = litedramcore_bankmachine2_sink_first;
-assign litedramcore_bankmachine2_fifo_in_last = litedramcore_bankmachine2_sink_last;
-assign litedramcore_bankmachine2_fifo_in_payload_we = litedramcore_bankmachine2_sink_payload_we;
-assign litedramcore_bankmachine2_fifo_in_payload_addr = litedramcore_bankmachine2_sink_payload_addr;
-assign litedramcore_bankmachine2_source_valid = litedramcore_bankmachine2_syncfifo2_readable;
-assign litedramcore_bankmachine2_source_first = litedramcore_bankmachine2_fifo_out_first;
-assign litedramcore_bankmachine2_source_last = litedramcore_bankmachine2_fifo_out_last;
-assign litedramcore_bankmachine2_source_payload_we = litedramcore_bankmachine2_fifo_out_payload_we;
-assign litedramcore_bankmachine2_source_payload_addr = litedramcore_bankmachine2_fifo_out_payload_addr;
-assign litedramcore_bankmachine2_syncfifo2_re = litedramcore_bankmachine2_source_ready;
-always @(*) begin
-    litedramcore_bankmachine2_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine2_replace) begin
-        litedramcore_bankmachine2_wrport_adr <= (litedramcore_bankmachine2_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine2_wrport_adr <= litedramcore_bankmachine2_produce;
-    end
-end
-assign litedramcore_bankmachine2_wrport_dat_w = litedramcore_bankmachine2_syncfifo2_din;
-assign litedramcore_bankmachine2_wrport_we = (litedramcore_bankmachine2_syncfifo2_we & (litedramcore_bankmachine2_syncfifo2_writable | litedramcore_bankmachine2_replace));
-assign litedramcore_bankmachine2_do_read = (litedramcore_bankmachine2_syncfifo2_readable & litedramcore_bankmachine2_syncfifo2_re);
-assign litedramcore_bankmachine2_rdport_adr = litedramcore_bankmachine2_consume;
-assign litedramcore_bankmachine2_syncfifo2_dout = litedramcore_bankmachine2_rdport_dat_r;
-assign litedramcore_bankmachine2_syncfifo2_writable = (litedramcore_bankmachine2_level != 5'd16);
-assign litedramcore_bankmachine2_syncfifo2_readable = (litedramcore_bankmachine2_level != 1'd0);
-assign litedramcore_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready);
-assign litedramcore_bankmachine2_pipe_valid_sink_valid = litedramcore_bankmachine2_sink_sink_valid;
-assign litedramcore_bankmachine2_sink_sink_ready = litedramcore_bankmachine2_pipe_valid_sink_ready;
-assign litedramcore_bankmachine2_pipe_valid_sink_first = litedramcore_bankmachine2_sink_sink_first;
-assign litedramcore_bankmachine2_pipe_valid_sink_last = litedramcore_bankmachine2_sink_sink_last;
-assign litedramcore_bankmachine2_pipe_valid_sink_payload_we = litedramcore_bankmachine2_sink_sink_payload_we;
-assign litedramcore_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_bankmachine2_sink_sink_payload_addr;
-assign litedramcore_bankmachine2_source_source_valid = litedramcore_bankmachine2_pipe_valid_source_valid;
-assign litedramcore_bankmachine2_pipe_valid_source_ready = litedramcore_bankmachine2_source_source_ready;
-assign litedramcore_bankmachine2_source_source_first = litedramcore_bankmachine2_pipe_valid_source_first;
-assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_pipe_valid_source_last;
-assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine2_next_state <= 4'd0;
-    litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
-    case (litedramcore_bankmachine2_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                if (litedramcore_bankmachine2_cmd_ready) begin
-                    litedramcore_bankmachine2_next_state <= 3'd5;
-                end
-            end
+always @(*) begin
+    main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine2_state)
+        1'd1: begin
         end
         2'd2: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                if (litedramcore_bankmachine2_cmd_ready) begin
-                    litedramcore_bankmachine2_next_state <= 3'd7;
-                end
-            end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine2_refresh_req)) begin
-                litedramcore_bankmachine2_next_state <= 1'd0;
-            end
         end
         3'd5: begin
-            litedramcore_bankmachine2_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine2_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine2_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine2_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
-                litedramcore_bankmachine2_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
-                                litedramcore_bankmachine2_next_state <= 2'd2;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
+                            end else begin
+                                main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
-                            litedramcore_bankmachine2_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine2_next_state <= 2'd3;
                     end
                 end
             end
@@ -6030,8 +6517,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6049,13 +6536,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
-                                litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
+                                main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -6068,8 +6555,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6087,14 +6574,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
+                                main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready;
                             end else begin
-                                litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
                             end
                         end else begin
                         end
@@ -6106,8 +6593,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6115,9 +6602,6 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine2_twtpcon_ready) begin
-                litedramcore_bankmachine2_refresh_gnt <= 1'd1;
-            end
         end
         3'd5: begin
         end
@@ -6128,22 +6612,37 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-        end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine2_row_open <= 1'd0;
-    case (litedramcore_bankmachine2_state)
-        1'd1: begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
+                            end else begin
+                                main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+    case (builder_bankmachine2_state)
+        1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_row_open <= 1'd1;
-            end
         end
         3'd4: begin
+            if (main_litedramcore_bankmachine2_twtpcon_ready) begin
+                main_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -6158,18 +6657,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_row_open <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_cmd_valid <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -6183,34 +6679,25 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            litedramcore_bankmachine2_cmd_valid <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_row_close <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
-            litedramcore_bankmachine2_row_close <= 1'd1;
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+            end
         end
         2'd2: begin
-            litedramcore_bankmachine2_row_close <= 1'd1;
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+            end
         end
         3'd4: begin
-            litedramcore_bankmachine2_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -6221,22 +6708,34 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_row_close <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
+            main_litedramcore_bankmachine2_row_close <= 1'd1;
         end
         2'd2: begin
+            main_litedramcore_bankmachine2_row_close <= 1'd1;
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
-            end
         end
         3'd4: begin
+            main_litedramcore_bankmachine2_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -6251,16 +6750,16 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -6273,27 +6772,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
-                                litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6311,12 +6795,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -6327,18 +6811,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -6356,22 +6840,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         3'd4: begin
-            litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -6382,41 +6862,157 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
+                                main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+assign main_litedramcore_bankmachine3_sink_valid = main_litedramcore_bankmachine3_req_valid;
+assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_sink_ready;
+assign main_litedramcore_bankmachine3_sink_payload_we = main_litedramcore_bankmachine3_req_we;
+assign main_litedramcore_bankmachine3_sink_payload_addr = main_litedramcore_bankmachine3_req_addr;
+assign main_litedramcore_bankmachine3_sink_sink_valid = main_litedramcore_bankmachine3_source_valid;
+assign main_litedramcore_bankmachine3_source_ready = main_litedramcore_bankmachine3_sink_sink_ready;
+assign main_litedramcore_bankmachine3_sink_sink_first = main_litedramcore_bankmachine3_source_first;
+assign main_litedramcore_bankmachine3_sink_sink_last = main_litedramcore_bankmachine3_source_last;
+assign main_litedramcore_bankmachine3_sink_sink_payload_we = main_litedramcore_bankmachine3_source_payload_we;
+assign main_litedramcore_bankmachine3_sink_sink_payload_addr = main_litedramcore_bankmachine3_source_payload_addr;
+assign main_litedramcore_bankmachine3_source_source_ready = (main_litedramcore_bankmachine3_req_wdata_ready | main_litedramcore_bankmachine3_req_rdata_valid);
+assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_source_valid | main_litedramcore_bankmachine3_source_source_valid);
+assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_source_source_payload_addr[21:7]);
+assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
+always @(*) begin
+    main_litedramcore_bankmachine3_cmd_payload_a <= 15'd0;
+    if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine3_cmd_payload_a <= main_litedramcore_bankmachine3_source_source_payload_addr[21:7];
+    end else begin
+        main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write);
+assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
+assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine3_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine3_source_valid & main_litedramcore_bankmachine3_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine3_source_payload_addr[21:7] != main_litedramcore_bankmachine3_source_source_payload_addr[21:7])) begin
+            main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine3_syncfifo3_din = {main_litedramcore_bankmachine3_fifo_in_last, main_litedramcore_bankmachine3_fifo_in_first, main_litedramcore_bankmachine3_fifo_in_payload_addr, main_litedramcore_bankmachine3_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout;
+assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout;
+assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout;
+assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout;
+assign main_litedramcore_bankmachine3_sink_ready = main_litedramcore_bankmachine3_syncfifo3_writable;
+assign main_litedramcore_bankmachine3_syncfifo3_we = main_litedramcore_bankmachine3_sink_valid;
+assign main_litedramcore_bankmachine3_fifo_in_first = main_litedramcore_bankmachine3_sink_first;
+assign main_litedramcore_bankmachine3_fifo_in_last = main_litedramcore_bankmachine3_sink_last;
+assign main_litedramcore_bankmachine3_fifo_in_payload_we = main_litedramcore_bankmachine3_sink_payload_we;
+assign main_litedramcore_bankmachine3_fifo_in_payload_addr = main_litedramcore_bankmachine3_sink_payload_addr;
+assign main_litedramcore_bankmachine3_source_valid = main_litedramcore_bankmachine3_syncfifo3_readable;
+assign main_litedramcore_bankmachine3_source_first = main_litedramcore_bankmachine3_fifo_out_first;
+assign main_litedramcore_bankmachine3_source_last = main_litedramcore_bankmachine3_fifo_out_last;
+assign main_litedramcore_bankmachine3_source_payload_we = main_litedramcore_bankmachine3_fifo_out_payload_we;
+assign main_litedramcore_bankmachine3_source_payload_addr = main_litedramcore_bankmachine3_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine3_syncfifo3_re = main_litedramcore_bankmachine3_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine3_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine3_replace) begin
+        main_litedramcore_bankmachine3_wrport_adr <= (main_litedramcore_bankmachine3_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine3_wrport_adr <= main_litedramcore_bankmachine3_produce;
+    end
+end
+assign main_litedramcore_bankmachine3_wrport_dat_w = main_litedramcore_bankmachine3_syncfifo3_din;
+assign main_litedramcore_bankmachine3_wrport_we = (main_litedramcore_bankmachine3_syncfifo3_we & (main_litedramcore_bankmachine3_syncfifo3_writable | main_litedramcore_bankmachine3_replace));
+assign main_litedramcore_bankmachine3_do_read = (main_litedramcore_bankmachine3_syncfifo3_readable & main_litedramcore_bankmachine3_syncfifo3_re);
+assign main_litedramcore_bankmachine3_rdport_adr = main_litedramcore_bankmachine3_consume;
+assign main_litedramcore_bankmachine3_syncfifo3_dout = main_litedramcore_bankmachine3_rdport_dat_r;
+assign main_litedramcore_bankmachine3_syncfifo3_writable = (main_litedramcore_bankmachine3_level != 5'd16);
+assign main_litedramcore_bankmachine3_syncfifo3_readable = (main_litedramcore_bankmachine3_level != 1'd0);
+assign main_litedramcore_bankmachine3_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine3_pipe_valid_source_valid) | main_litedramcore_bankmachine3_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine3_pipe_valid_sink_valid = main_litedramcore_bankmachine3_sink_sink_valid;
+assign main_litedramcore_bankmachine3_sink_sink_ready = main_litedramcore_bankmachine3_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine3_pipe_valid_sink_first = main_litedramcore_bankmachine3_sink_sink_first;
+assign main_litedramcore_bankmachine3_pipe_valid_sink_last = main_litedramcore_bankmachine3_sink_sink_last;
+assign main_litedramcore_bankmachine3_pipe_valid_sink_payload_we = main_litedramcore_bankmachine3_sink_sink_payload_we;
+assign main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine3_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine3_source_source_valid = main_litedramcore_bankmachine3_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine3_pipe_valid_source_ready = main_litedramcore_bankmachine3_source_source_ready;
+assign main_litedramcore_bankmachine3_source_source_first = main_litedramcore_bankmachine3_pipe_valid_source_first;
+assign main_litedramcore_bankmachine3_source_source_last = main_litedramcore_bankmachine3_pipe_valid_source_last;
+assign main_litedramcore_bankmachine3_source_source_payload_we = main_litedramcore_bankmachine3_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine3_source_source_payload_addr = main_litedramcore_bankmachine3_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine3_next_state <= 4'd0;
+    builder_bankmachine3_next_state <= builder_bankmachine3_state;
+    case (builder_bankmachine3_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                if (main_litedramcore_bankmachine3_cmd_ready) begin
+                    builder_bankmachine3_next_state <= 3'd5;
+                end
+            end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                builder_bankmachine3_next_state <= 3'd5;
+            end
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                if (main_litedramcore_bankmachine3_cmd_ready) begin
+                    builder_bankmachine3_next_state <= 3'd7;
+                end
+            end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine3_refresh_req)) begin
+                builder_bankmachine3_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine3_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine3_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine3_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine3_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
+                builder_bankmachine3_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin
+                                builder_bankmachine3_next_state <= 2'd2;
                             end
                         end else begin
+                            builder_bankmachine3_next_state <= 1'd1;
                         end
                     end else begin
+                        builder_bankmachine3_next_state <= 2'd3;
                     end
                 end
             end
@@ -6424,8 +7020,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6443,14 +7039,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
-                                litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
                             end else begin
+                                main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
                             end
                         end else begin
                         end
@@ -6461,155 +7057,42 @@ always @(*) begin
         end
     endcase
 end
-assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid;
-assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready;
-assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we;
-assign litedramcore_bankmachine3_sink_payload_addr = litedramcore_bankmachine3_req_addr;
-assign litedramcore_bankmachine3_sink_sink_valid = litedramcore_bankmachine3_source_valid;
-assign litedramcore_bankmachine3_source_ready = litedramcore_bankmachine3_sink_sink_ready;
-assign litedramcore_bankmachine3_sink_sink_first = litedramcore_bankmachine3_source_first;
-assign litedramcore_bankmachine3_sink_sink_last = litedramcore_bankmachine3_source_last;
-assign litedramcore_bankmachine3_sink_sink_payload_we = litedramcore_bankmachine3_source_payload_we;
-assign litedramcore_bankmachine3_sink_sink_payload_addr = litedramcore_bankmachine3_source_payload_addr;
-assign litedramcore_bankmachine3_source_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
-assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_source_valid | litedramcore_bankmachine3_source_source_valid);
-assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_source_source_payload_addr[21:7]);
-assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
-always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_a <= 15'd0;
-    if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
-        litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_source_source_payload_addr[21:7];
-    end else begin
-        litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
-assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
-assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
-always @(*) begin
-    litedramcore_bankmachine3_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine3_source_valid & litedramcore_bankmachine3_source_source_valid)) begin
-        if ((litedramcore_bankmachine3_source_payload_addr[21:7] != litedramcore_bankmachine3_source_source_payload_addr[21:7])) begin
-            litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine3_syncfifo3_din = {litedramcore_bankmachine3_fifo_in_last, litedramcore_bankmachine3_fifo_in_first, litedramcore_bankmachine3_fifo_in_payload_addr, litedramcore_bankmachine3_fifo_in_payload_we};
-assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
-assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
-assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
-assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
-assign litedramcore_bankmachine3_sink_ready = litedramcore_bankmachine3_syncfifo3_writable;
-assign litedramcore_bankmachine3_syncfifo3_we = litedramcore_bankmachine3_sink_valid;
-assign litedramcore_bankmachine3_fifo_in_first = litedramcore_bankmachine3_sink_first;
-assign litedramcore_bankmachine3_fifo_in_last = litedramcore_bankmachine3_sink_last;
-assign litedramcore_bankmachine3_fifo_in_payload_we = litedramcore_bankmachine3_sink_payload_we;
-assign litedramcore_bankmachine3_fifo_in_payload_addr = litedramcore_bankmachine3_sink_payload_addr;
-assign litedramcore_bankmachine3_source_valid = litedramcore_bankmachine3_syncfifo3_readable;
-assign litedramcore_bankmachine3_source_first = litedramcore_bankmachine3_fifo_out_first;
-assign litedramcore_bankmachine3_source_last = litedramcore_bankmachine3_fifo_out_last;
-assign litedramcore_bankmachine3_source_payload_we = litedramcore_bankmachine3_fifo_out_payload_we;
-assign litedramcore_bankmachine3_source_payload_addr = litedramcore_bankmachine3_fifo_out_payload_addr;
-assign litedramcore_bankmachine3_syncfifo3_re = litedramcore_bankmachine3_source_ready;
-always @(*) begin
-    litedramcore_bankmachine3_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine3_replace) begin
-        litedramcore_bankmachine3_wrport_adr <= (litedramcore_bankmachine3_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine3_wrport_adr <= litedramcore_bankmachine3_produce;
-    end
-end
-assign litedramcore_bankmachine3_wrport_dat_w = litedramcore_bankmachine3_syncfifo3_din;
-assign litedramcore_bankmachine3_wrport_we = (litedramcore_bankmachine3_syncfifo3_we & (litedramcore_bankmachine3_syncfifo3_writable | litedramcore_bankmachine3_replace));
-assign litedramcore_bankmachine3_do_read = (litedramcore_bankmachine3_syncfifo3_readable & litedramcore_bankmachine3_syncfifo3_re);
-assign litedramcore_bankmachine3_rdport_adr = litedramcore_bankmachine3_consume;
-assign litedramcore_bankmachine3_syncfifo3_dout = litedramcore_bankmachine3_rdport_dat_r;
-assign litedramcore_bankmachine3_syncfifo3_writable = (litedramcore_bankmachine3_level != 5'd16);
-assign litedramcore_bankmachine3_syncfifo3_readable = (litedramcore_bankmachine3_level != 1'd0);
-assign litedramcore_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready);
-assign litedramcore_bankmachine3_pipe_valid_sink_valid = litedramcore_bankmachine3_sink_sink_valid;
-assign litedramcore_bankmachine3_sink_sink_ready = litedramcore_bankmachine3_pipe_valid_sink_ready;
-assign litedramcore_bankmachine3_pipe_valid_sink_first = litedramcore_bankmachine3_sink_sink_first;
-assign litedramcore_bankmachine3_pipe_valid_sink_last = litedramcore_bankmachine3_sink_sink_last;
-assign litedramcore_bankmachine3_pipe_valid_sink_payload_we = litedramcore_bankmachine3_sink_sink_payload_we;
-assign litedramcore_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_bankmachine3_sink_sink_payload_addr;
-assign litedramcore_bankmachine3_source_source_valid = litedramcore_bankmachine3_pipe_valid_source_valid;
-assign litedramcore_bankmachine3_pipe_valid_source_ready = litedramcore_bankmachine3_source_source_ready;
-assign litedramcore_bankmachine3_source_source_first = litedramcore_bankmachine3_pipe_valid_source_first;
-assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_pipe_valid_source_last;
-assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine3_next_state <= 4'd0;
-    litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
-    case (litedramcore_bankmachine3_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                if (litedramcore_bankmachine3_cmd_ready) begin
-                    litedramcore_bankmachine3_next_state <= 3'd5;
-                end
-            end
+always @(*) begin
+    main_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+    case (builder_bankmachine3_state)
+        1'd1: begin
         end
         2'd2: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                if (litedramcore_bankmachine3_cmd_ready) begin
-                    litedramcore_bankmachine3_next_state <= 3'd7;
-                end
-            end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine3_refresh_req)) begin
-                litedramcore_bankmachine3_next_state <= 1'd0;
+            if (main_litedramcore_bankmachine3_twtpcon_ready) begin
+                main_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
             end
         end
         3'd5: begin
-            litedramcore_bankmachine3_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine3_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine3_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine3_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
-                litedramcore_bankmachine3_next_state <= 3'd4;
-            end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
-                                litedramcore_bankmachine3_next_state <= 2'd2;
-                            end
-                        end else begin
-                            litedramcore_bankmachine3_next_state <= 1'd1;
-                        end
-                    end else begin
-                        litedramcore_bankmachine3_next_state <= 2'd3;
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_row_open <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_row_open <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -6627,18 +7110,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -6652,12 +7135,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            litedramcore_bankmachine3_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -6668,18 +7151,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_row_close <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_row_close <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
-            litedramcore_bankmachine3_row_close <= 1'd1;
+            main_litedramcore_bankmachine3_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine3_row_close <= 1'd1;
+            main_litedramcore_bankmachine3_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine3_row_close <= 1'd1;
+            main_litedramcore_bankmachine3_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -6694,15 +7177,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -6720,8 +7203,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6739,12 +7222,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -6755,18 +7238,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -6784,11 +7267,11 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
@@ -6806,13 +7289,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
-                                litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
+                                main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -6825,22 +7308,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -6855,8 +7338,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6874,14 +7357,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -6893,8 +7376,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6912,13 +7395,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
-                                litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
+                                main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -6931,8 +7414,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6950,14 +7433,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
+                                main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready;
                             end else begin
-                                litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
                             end
                         end else begin
                         end
@@ -6968,38 +7451,139 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+assign main_litedramcore_bankmachine4_sink_valid = main_litedramcore_bankmachine4_req_valid;
+assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_sink_ready;
+assign main_litedramcore_bankmachine4_sink_payload_we = main_litedramcore_bankmachine4_req_we;
+assign main_litedramcore_bankmachine4_sink_payload_addr = main_litedramcore_bankmachine4_req_addr;
+assign main_litedramcore_bankmachine4_sink_sink_valid = main_litedramcore_bankmachine4_source_valid;
+assign main_litedramcore_bankmachine4_source_ready = main_litedramcore_bankmachine4_sink_sink_ready;
+assign main_litedramcore_bankmachine4_sink_sink_first = main_litedramcore_bankmachine4_source_first;
+assign main_litedramcore_bankmachine4_sink_sink_last = main_litedramcore_bankmachine4_source_last;
+assign main_litedramcore_bankmachine4_sink_sink_payload_we = main_litedramcore_bankmachine4_source_payload_we;
+assign main_litedramcore_bankmachine4_sink_sink_payload_addr = main_litedramcore_bankmachine4_source_payload_addr;
+assign main_litedramcore_bankmachine4_source_source_ready = (main_litedramcore_bankmachine4_req_wdata_ready | main_litedramcore_bankmachine4_req_rdata_valid);
+assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_source_valid | main_litedramcore_bankmachine4_source_source_valid);
+assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_source_source_payload_addr[21:7]);
+assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
+always @(*) begin
+    main_litedramcore_bankmachine4_cmd_payload_a <= 15'd0;
+    if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine4_cmd_payload_a <= main_litedramcore_bankmachine4_source_source_payload_addr[21:7];
+    end else begin
+        main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write);
+assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
+assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine4_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine4_source_valid & main_litedramcore_bankmachine4_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine4_source_payload_addr[21:7] != main_litedramcore_bankmachine4_source_source_payload_addr[21:7])) begin
+            main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine4_syncfifo4_din = {main_litedramcore_bankmachine4_fifo_in_last, main_litedramcore_bankmachine4_fifo_in_first, main_litedramcore_bankmachine4_fifo_in_payload_addr, main_litedramcore_bankmachine4_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout;
+assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout;
+assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout;
+assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout;
+assign main_litedramcore_bankmachine4_sink_ready = main_litedramcore_bankmachine4_syncfifo4_writable;
+assign main_litedramcore_bankmachine4_syncfifo4_we = main_litedramcore_bankmachine4_sink_valid;
+assign main_litedramcore_bankmachine4_fifo_in_first = main_litedramcore_bankmachine4_sink_first;
+assign main_litedramcore_bankmachine4_fifo_in_last = main_litedramcore_bankmachine4_sink_last;
+assign main_litedramcore_bankmachine4_fifo_in_payload_we = main_litedramcore_bankmachine4_sink_payload_we;
+assign main_litedramcore_bankmachine4_fifo_in_payload_addr = main_litedramcore_bankmachine4_sink_payload_addr;
+assign main_litedramcore_bankmachine4_source_valid = main_litedramcore_bankmachine4_syncfifo4_readable;
+assign main_litedramcore_bankmachine4_source_first = main_litedramcore_bankmachine4_fifo_out_first;
+assign main_litedramcore_bankmachine4_source_last = main_litedramcore_bankmachine4_fifo_out_last;
+assign main_litedramcore_bankmachine4_source_payload_we = main_litedramcore_bankmachine4_fifo_out_payload_we;
+assign main_litedramcore_bankmachine4_source_payload_addr = main_litedramcore_bankmachine4_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine4_syncfifo4_re = main_litedramcore_bankmachine4_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine4_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine4_replace) begin
+        main_litedramcore_bankmachine4_wrport_adr <= (main_litedramcore_bankmachine4_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine4_wrport_adr <= main_litedramcore_bankmachine4_produce;
+    end
+end
+assign main_litedramcore_bankmachine4_wrport_dat_w = main_litedramcore_bankmachine4_syncfifo4_din;
+assign main_litedramcore_bankmachine4_wrport_we = (main_litedramcore_bankmachine4_syncfifo4_we & (main_litedramcore_bankmachine4_syncfifo4_writable | main_litedramcore_bankmachine4_replace));
+assign main_litedramcore_bankmachine4_do_read = (main_litedramcore_bankmachine4_syncfifo4_readable & main_litedramcore_bankmachine4_syncfifo4_re);
+assign main_litedramcore_bankmachine4_rdport_adr = main_litedramcore_bankmachine4_consume;
+assign main_litedramcore_bankmachine4_syncfifo4_dout = main_litedramcore_bankmachine4_rdport_dat_r;
+assign main_litedramcore_bankmachine4_syncfifo4_writable = (main_litedramcore_bankmachine4_level != 5'd16);
+assign main_litedramcore_bankmachine4_syncfifo4_readable = (main_litedramcore_bankmachine4_level != 1'd0);
+assign main_litedramcore_bankmachine4_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine4_pipe_valid_source_valid) | main_litedramcore_bankmachine4_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine4_pipe_valid_sink_valid = main_litedramcore_bankmachine4_sink_sink_valid;
+assign main_litedramcore_bankmachine4_sink_sink_ready = main_litedramcore_bankmachine4_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine4_pipe_valid_sink_first = main_litedramcore_bankmachine4_sink_sink_first;
+assign main_litedramcore_bankmachine4_pipe_valid_sink_last = main_litedramcore_bankmachine4_sink_sink_last;
+assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_we = main_litedramcore_bankmachine4_sink_sink_payload_we;
+assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine4_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine4_source_source_valid = main_litedramcore_bankmachine4_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine4_pipe_valid_source_ready = main_litedramcore_bankmachine4_source_source_ready;
+assign main_litedramcore_bankmachine4_source_source_first = main_litedramcore_bankmachine4_pipe_valid_source_first;
+assign main_litedramcore_bankmachine4_source_source_last = main_litedramcore_bankmachine4_pipe_valid_source_last;
+assign main_litedramcore_bankmachine4_source_source_payload_we = main_litedramcore_bankmachine4_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine4_source_source_payload_addr = main_litedramcore_bankmachine4_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine4_next_state <= 4'd0;
+    builder_bankmachine4_next_state <= builder_bankmachine4_state;
+    case (builder_bankmachine4_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                if (main_litedramcore_bankmachine4_cmd_ready) begin
+                    builder_bankmachine4_next_state <= 3'd5;
+                end
+            end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                builder_bankmachine4_next_state <= 3'd5;
+            end
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                if (main_litedramcore_bankmachine4_cmd_ready) begin
+                    builder_bankmachine4_next_state <= 3'd7;
+                end
+            end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine4_refresh_req)) begin
+                builder_bankmachine4_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine4_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine4_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine4_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine4_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
+                builder_bankmachine4_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
-                                litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
-                            end else begin
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if ((main_litedramcore_bankmachine4_cmd_ready & main_litedramcore_bankmachine4_auto_precharge)) begin
+                                builder_bankmachine4_next_state <= 2'd2;
                             end
                         end else begin
+                            builder_bankmachine4_next_state <= 1'd1;
                         end
                     end else begin
+                        builder_bankmachine4_next_state <= 2'd3;
                     end
                 end
             end
@@ -7007,18 +7591,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+            end
         end
         3'd4: begin
-            if (litedramcore_bankmachine3_twtpcon_ready) begin
-                litedramcore_bankmachine3_refresh_gnt <= 1'd1;
-            end
         end
         3'd5: begin
         end
@@ -7032,139 +7616,35 @@ always @(*) begin
         end
     endcase
 end
-assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid;
-assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready;
-assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we;
-assign litedramcore_bankmachine4_sink_payload_addr = litedramcore_bankmachine4_req_addr;
-assign litedramcore_bankmachine4_sink_sink_valid = litedramcore_bankmachine4_source_valid;
-assign litedramcore_bankmachine4_source_ready = litedramcore_bankmachine4_sink_sink_ready;
-assign litedramcore_bankmachine4_sink_sink_first = litedramcore_bankmachine4_source_first;
-assign litedramcore_bankmachine4_sink_sink_last = litedramcore_bankmachine4_source_last;
-assign litedramcore_bankmachine4_sink_sink_payload_we = litedramcore_bankmachine4_source_payload_we;
-assign litedramcore_bankmachine4_sink_sink_payload_addr = litedramcore_bankmachine4_source_payload_addr;
-assign litedramcore_bankmachine4_source_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
-assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_source_valid | litedramcore_bankmachine4_source_source_valid);
-assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_source_source_payload_addr[21:7]);
-assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
-always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_a <= 15'd0;
-    if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
-        litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_source_source_payload_addr[21:7];
-    end else begin
-        litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
-assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
-assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
-always @(*) begin
-    litedramcore_bankmachine4_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine4_source_valid & litedramcore_bankmachine4_source_source_valid)) begin
-        if ((litedramcore_bankmachine4_source_payload_addr[21:7] != litedramcore_bankmachine4_source_source_payload_addr[21:7])) begin
-            litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine4_syncfifo4_din = {litedramcore_bankmachine4_fifo_in_last, litedramcore_bankmachine4_fifo_in_first, litedramcore_bankmachine4_fifo_in_payload_addr, litedramcore_bankmachine4_fifo_in_payload_we};
-assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
-assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
-assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
-assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
-assign litedramcore_bankmachine4_sink_ready = litedramcore_bankmachine4_syncfifo4_writable;
-assign litedramcore_bankmachine4_syncfifo4_we = litedramcore_bankmachine4_sink_valid;
-assign litedramcore_bankmachine4_fifo_in_first = litedramcore_bankmachine4_sink_first;
-assign litedramcore_bankmachine4_fifo_in_last = litedramcore_bankmachine4_sink_last;
-assign litedramcore_bankmachine4_fifo_in_payload_we = litedramcore_bankmachine4_sink_payload_we;
-assign litedramcore_bankmachine4_fifo_in_payload_addr = litedramcore_bankmachine4_sink_payload_addr;
-assign litedramcore_bankmachine4_source_valid = litedramcore_bankmachine4_syncfifo4_readable;
-assign litedramcore_bankmachine4_source_first = litedramcore_bankmachine4_fifo_out_first;
-assign litedramcore_bankmachine4_source_last = litedramcore_bankmachine4_fifo_out_last;
-assign litedramcore_bankmachine4_source_payload_we = litedramcore_bankmachine4_fifo_out_payload_we;
-assign litedramcore_bankmachine4_source_payload_addr = litedramcore_bankmachine4_fifo_out_payload_addr;
-assign litedramcore_bankmachine4_syncfifo4_re = litedramcore_bankmachine4_source_ready;
-always @(*) begin
-    litedramcore_bankmachine4_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine4_replace) begin
-        litedramcore_bankmachine4_wrport_adr <= (litedramcore_bankmachine4_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine4_wrport_adr <= litedramcore_bankmachine4_produce;
-    end
-end
-assign litedramcore_bankmachine4_wrport_dat_w = litedramcore_bankmachine4_syncfifo4_din;
-assign litedramcore_bankmachine4_wrport_we = (litedramcore_bankmachine4_syncfifo4_we & (litedramcore_bankmachine4_syncfifo4_writable | litedramcore_bankmachine4_replace));
-assign litedramcore_bankmachine4_do_read = (litedramcore_bankmachine4_syncfifo4_readable & litedramcore_bankmachine4_syncfifo4_re);
-assign litedramcore_bankmachine4_rdport_adr = litedramcore_bankmachine4_consume;
-assign litedramcore_bankmachine4_syncfifo4_dout = litedramcore_bankmachine4_rdport_dat_r;
-assign litedramcore_bankmachine4_syncfifo4_writable = (litedramcore_bankmachine4_level != 5'd16);
-assign litedramcore_bankmachine4_syncfifo4_readable = (litedramcore_bankmachine4_level != 1'd0);
-assign litedramcore_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready);
-assign litedramcore_bankmachine4_pipe_valid_sink_valid = litedramcore_bankmachine4_sink_sink_valid;
-assign litedramcore_bankmachine4_sink_sink_ready = litedramcore_bankmachine4_pipe_valid_sink_ready;
-assign litedramcore_bankmachine4_pipe_valid_sink_first = litedramcore_bankmachine4_sink_sink_first;
-assign litedramcore_bankmachine4_pipe_valid_sink_last = litedramcore_bankmachine4_sink_sink_last;
-assign litedramcore_bankmachine4_pipe_valid_sink_payload_we = litedramcore_bankmachine4_sink_sink_payload_we;
-assign litedramcore_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_bankmachine4_sink_sink_payload_addr;
-assign litedramcore_bankmachine4_source_source_valid = litedramcore_bankmachine4_pipe_valid_source_valid;
-assign litedramcore_bankmachine4_pipe_valid_source_ready = litedramcore_bankmachine4_source_source_ready;
-assign litedramcore_bankmachine4_source_source_first = litedramcore_bankmachine4_pipe_valid_source_first;
-assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_pipe_valid_source_last;
-assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine4_next_state <= 4'd0;
-    litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
-    case (litedramcore_bankmachine4_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                if (litedramcore_bankmachine4_cmd_ready) begin
-                    litedramcore_bankmachine4_next_state <= 3'd5;
-                end
-            end
+always @(*) begin
+    main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine4_state)
+        1'd1: begin
         end
         2'd2: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                if (litedramcore_bankmachine4_cmd_ready) begin
-                    litedramcore_bankmachine4_next_state <= 3'd7;
-                end
-            end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine4_refresh_req)) begin
-                litedramcore_bankmachine4_next_state <= 1'd0;
-            end
         end
         3'd5: begin
-            litedramcore_bankmachine4_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine4_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine4_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine4_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
-                litedramcore_bankmachine4_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
-                                litedramcore_bankmachine4_next_state <= 2'd2;
-                            end
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
                         end else begin
-                            litedramcore_bankmachine4_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine4_next_state <= 2'd3;
                     end
                 end
             end
@@ -7172,18 +7652,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_row_close <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
+            main_litedramcore_bankmachine4_row_close <= 1'd1;
         end
         2'd2: begin
+            main_litedramcore_bankmachine4_row_close <= 1'd1;
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
-            end
         end
         3'd4: begin
+            main_litedramcore_bankmachine4_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -7198,13 +7678,19 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -7217,35 +7703,20 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_cmd_valid <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -7258,12 +7729,15 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            litedramcore_bankmachine4_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
+                                main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+                            end else begin
+                            end
                         end else begin
                         end
                     end else begin
@@ -7274,21 +7748,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
+            main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -7303,12 +7778,9 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
-            end
         end
         2'd2: begin
         end
@@ -7325,14 +7797,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
-                                litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
                             end else begin
+                                main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -7344,22 +7816,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         3'd4: begin
-            litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -7370,12 +7835,27 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
+                                main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7393,14 +7873,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
+                                main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready;
                             end else begin
-                                litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -7412,8 +7892,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7431,14 +7911,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
-                                litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
                             end else begin
+                                main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready;
                             end
                         end else begin
                         end
@@ -7450,8 +7930,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7459,6 +7939,9 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
+            if (main_litedramcore_bankmachine4_twtpcon_ready) begin
+                main_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -7469,32 +7952,20 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
-                                litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_row_open <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_row_open <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -7507,37 +7978,25 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_valid <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+            end
         end
         3'd4: begin
-            if (litedramcore_bankmachine4_twtpcon_ready) begin
-                litedramcore_bankmachine4_refresh_gnt <= 1'd1;
-            end
         end
         3'd5: begin
         end
@@ -7548,48 +8007,170 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine4_row_open <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+assign main_litedramcore_bankmachine5_sink_valid = main_litedramcore_bankmachine5_req_valid;
+assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_sink_ready;
+assign main_litedramcore_bankmachine5_sink_payload_we = main_litedramcore_bankmachine5_req_we;
+assign main_litedramcore_bankmachine5_sink_payload_addr = main_litedramcore_bankmachine5_req_addr;
+assign main_litedramcore_bankmachine5_sink_sink_valid = main_litedramcore_bankmachine5_source_valid;
+assign main_litedramcore_bankmachine5_source_ready = main_litedramcore_bankmachine5_sink_sink_ready;
+assign main_litedramcore_bankmachine5_sink_sink_first = main_litedramcore_bankmachine5_source_first;
+assign main_litedramcore_bankmachine5_sink_sink_last = main_litedramcore_bankmachine5_source_last;
+assign main_litedramcore_bankmachine5_sink_sink_payload_we = main_litedramcore_bankmachine5_source_payload_we;
+assign main_litedramcore_bankmachine5_sink_sink_payload_addr = main_litedramcore_bankmachine5_source_payload_addr;
+assign main_litedramcore_bankmachine5_source_source_ready = (main_litedramcore_bankmachine5_req_wdata_ready | main_litedramcore_bankmachine5_req_rdata_valid);
+assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_source_valid | main_litedramcore_bankmachine5_source_source_valid);
+assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_source_source_payload_addr[21:7]);
+assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
+always @(*) begin
+    main_litedramcore_bankmachine5_cmd_payload_a <= 15'd0;
+    if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine5_cmd_payload_a <= main_litedramcore_bankmachine5_source_source_payload_addr[21:7];
+    end else begin
+        main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write);
+assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
+assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine5_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine5_source_valid & main_litedramcore_bankmachine5_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine5_source_payload_addr[21:7] != main_litedramcore_bankmachine5_source_source_payload_addr[21:7])) begin
+            main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine5_syncfifo5_din = {main_litedramcore_bankmachine5_fifo_in_last, main_litedramcore_bankmachine5_fifo_in_first, main_litedramcore_bankmachine5_fifo_in_payload_addr, main_litedramcore_bankmachine5_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout;
+assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout;
+assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout;
+assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout;
+assign main_litedramcore_bankmachine5_sink_ready = main_litedramcore_bankmachine5_syncfifo5_writable;
+assign main_litedramcore_bankmachine5_syncfifo5_we = main_litedramcore_bankmachine5_sink_valid;
+assign main_litedramcore_bankmachine5_fifo_in_first = main_litedramcore_bankmachine5_sink_first;
+assign main_litedramcore_bankmachine5_fifo_in_last = main_litedramcore_bankmachine5_sink_last;
+assign main_litedramcore_bankmachine5_fifo_in_payload_we = main_litedramcore_bankmachine5_sink_payload_we;
+assign main_litedramcore_bankmachine5_fifo_in_payload_addr = main_litedramcore_bankmachine5_sink_payload_addr;
+assign main_litedramcore_bankmachine5_source_valid = main_litedramcore_bankmachine5_syncfifo5_readable;
+assign main_litedramcore_bankmachine5_source_first = main_litedramcore_bankmachine5_fifo_out_first;
+assign main_litedramcore_bankmachine5_source_last = main_litedramcore_bankmachine5_fifo_out_last;
+assign main_litedramcore_bankmachine5_source_payload_we = main_litedramcore_bankmachine5_fifo_out_payload_we;
+assign main_litedramcore_bankmachine5_source_payload_addr = main_litedramcore_bankmachine5_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine5_syncfifo5_re = main_litedramcore_bankmachine5_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine5_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine5_replace) begin
+        main_litedramcore_bankmachine5_wrport_adr <= (main_litedramcore_bankmachine5_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine5_wrport_adr <= main_litedramcore_bankmachine5_produce;
+    end
+end
+assign main_litedramcore_bankmachine5_wrport_dat_w = main_litedramcore_bankmachine5_syncfifo5_din;
+assign main_litedramcore_bankmachine5_wrport_we = (main_litedramcore_bankmachine5_syncfifo5_we & (main_litedramcore_bankmachine5_syncfifo5_writable | main_litedramcore_bankmachine5_replace));
+assign main_litedramcore_bankmachine5_do_read = (main_litedramcore_bankmachine5_syncfifo5_readable & main_litedramcore_bankmachine5_syncfifo5_re);
+assign main_litedramcore_bankmachine5_rdport_adr = main_litedramcore_bankmachine5_consume;
+assign main_litedramcore_bankmachine5_syncfifo5_dout = main_litedramcore_bankmachine5_rdport_dat_r;
+assign main_litedramcore_bankmachine5_syncfifo5_writable = (main_litedramcore_bankmachine5_level != 5'd16);
+assign main_litedramcore_bankmachine5_syncfifo5_readable = (main_litedramcore_bankmachine5_level != 1'd0);
+assign main_litedramcore_bankmachine5_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine5_pipe_valid_source_valid) | main_litedramcore_bankmachine5_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine5_pipe_valid_sink_valid = main_litedramcore_bankmachine5_sink_sink_valid;
+assign main_litedramcore_bankmachine5_sink_sink_ready = main_litedramcore_bankmachine5_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine5_pipe_valid_sink_first = main_litedramcore_bankmachine5_sink_sink_first;
+assign main_litedramcore_bankmachine5_pipe_valid_sink_last = main_litedramcore_bankmachine5_sink_sink_last;
+assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_we = main_litedramcore_bankmachine5_sink_sink_payload_we;
+assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine5_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine5_source_source_valid = main_litedramcore_bankmachine5_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine5_pipe_valid_source_ready = main_litedramcore_bankmachine5_source_source_ready;
+assign main_litedramcore_bankmachine5_source_source_first = main_litedramcore_bankmachine5_pipe_valid_source_first;
+assign main_litedramcore_bankmachine5_source_source_last = main_litedramcore_bankmachine5_pipe_valid_source_last;
+assign main_litedramcore_bankmachine5_source_source_payload_we = main_litedramcore_bankmachine5_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine5_source_source_payload_addr = main_litedramcore_bankmachine5_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine5_next_state <= 4'd0;
+    builder_bankmachine5_next_state <= builder_bankmachine5_state;
+    case (builder_bankmachine5_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                if (main_litedramcore_bankmachine5_cmd_ready) begin
+                    builder_bankmachine5_next_state <= 3'd5;
+                end
+            end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                builder_bankmachine5_next_state <= 3'd5;
+            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                if (main_litedramcore_bankmachine5_cmd_ready) begin
+                    builder_bankmachine5_next_state <= 3'd7;
+                end
             end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine5_refresh_req)) begin
+                builder_bankmachine5_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine5_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine5_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine5_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine5_next_state <= 1'd0;
         end
         default: begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
+                builder_bankmachine5_next_state <= 3'd4;
+            end else begin
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin
+                                builder_bankmachine5_next_state <= 2'd2;
+                            end
+                        end else begin
+                            builder_bankmachine5_next_state <= 1'd1;
+                        end
+                    end else begin
+                        builder_bankmachine5_next_state <= 2'd3;
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_row_close <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
-            litedramcore_bankmachine4_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine4_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine4_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -7600,154 +8181,56 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
-assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid;
-assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready;
-assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we;
-assign litedramcore_bankmachine5_sink_payload_addr = litedramcore_bankmachine5_req_addr;
-assign litedramcore_bankmachine5_sink_sink_valid = litedramcore_bankmachine5_source_valid;
-assign litedramcore_bankmachine5_source_ready = litedramcore_bankmachine5_sink_sink_ready;
-assign litedramcore_bankmachine5_sink_sink_first = litedramcore_bankmachine5_source_first;
-assign litedramcore_bankmachine5_sink_sink_last = litedramcore_bankmachine5_source_last;
-assign litedramcore_bankmachine5_sink_sink_payload_we = litedramcore_bankmachine5_source_payload_we;
-assign litedramcore_bankmachine5_sink_sink_payload_addr = litedramcore_bankmachine5_source_payload_addr;
-assign litedramcore_bankmachine5_source_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
-assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_source_valid | litedramcore_bankmachine5_source_source_valid);
-assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_source_source_payload_addr[21:7]);
-assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
-always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_a <= 15'd0;
-    if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
-        litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_source_source_payload_addr[21:7];
-    end else begin
-        litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
-assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
-assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
-always @(*) begin
-    litedramcore_bankmachine5_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine5_source_valid & litedramcore_bankmachine5_source_source_valid)) begin
-        if ((litedramcore_bankmachine5_source_payload_addr[21:7] != litedramcore_bankmachine5_source_source_payload_addr[21:7])) begin
-            litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine5_syncfifo5_din = {litedramcore_bankmachine5_fifo_in_last, litedramcore_bankmachine5_fifo_in_first, litedramcore_bankmachine5_fifo_in_payload_addr, litedramcore_bankmachine5_fifo_in_payload_we};
-assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
-assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
-assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
-assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
-assign litedramcore_bankmachine5_sink_ready = litedramcore_bankmachine5_syncfifo5_writable;
-assign litedramcore_bankmachine5_syncfifo5_we = litedramcore_bankmachine5_sink_valid;
-assign litedramcore_bankmachine5_fifo_in_first = litedramcore_bankmachine5_sink_first;
-assign litedramcore_bankmachine5_fifo_in_last = litedramcore_bankmachine5_sink_last;
-assign litedramcore_bankmachine5_fifo_in_payload_we = litedramcore_bankmachine5_sink_payload_we;
-assign litedramcore_bankmachine5_fifo_in_payload_addr = litedramcore_bankmachine5_sink_payload_addr;
-assign litedramcore_bankmachine5_source_valid = litedramcore_bankmachine5_syncfifo5_readable;
-assign litedramcore_bankmachine5_source_first = litedramcore_bankmachine5_fifo_out_first;
-assign litedramcore_bankmachine5_source_last = litedramcore_bankmachine5_fifo_out_last;
-assign litedramcore_bankmachine5_source_payload_we = litedramcore_bankmachine5_fifo_out_payload_we;
-assign litedramcore_bankmachine5_source_payload_addr = litedramcore_bankmachine5_fifo_out_payload_addr;
-assign litedramcore_bankmachine5_syncfifo5_re = litedramcore_bankmachine5_source_ready;
-always @(*) begin
-    litedramcore_bankmachine5_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine5_replace) begin
-        litedramcore_bankmachine5_wrport_adr <= (litedramcore_bankmachine5_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine5_wrport_adr <= litedramcore_bankmachine5_produce;
-    end
-end
-assign litedramcore_bankmachine5_wrport_dat_w = litedramcore_bankmachine5_syncfifo5_din;
-assign litedramcore_bankmachine5_wrport_we = (litedramcore_bankmachine5_syncfifo5_we & (litedramcore_bankmachine5_syncfifo5_writable | litedramcore_bankmachine5_replace));
-assign litedramcore_bankmachine5_do_read = (litedramcore_bankmachine5_syncfifo5_readable & litedramcore_bankmachine5_syncfifo5_re);
-assign litedramcore_bankmachine5_rdport_adr = litedramcore_bankmachine5_consume;
-assign litedramcore_bankmachine5_syncfifo5_dout = litedramcore_bankmachine5_rdport_dat_r;
-assign litedramcore_bankmachine5_syncfifo5_writable = (litedramcore_bankmachine5_level != 5'd16);
-assign litedramcore_bankmachine5_syncfifo5_readable = (litedramcore_bankmachine5_level != 1'd0);
-assign litedramcore_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready);
-assign litedramcore_bankmachine5_pipe_valid_sink_valid = litedramcore_bankmachine5_sink_sink_valid;
-assign litedramcore_bankmachine5_sink_sink_ready = litedramcore_bankmachine5_pipe_valid_sink_ready;
-assign litedramcore_bankmachine5_pipe_valid_sink_first = litedramcore_bankmachine5_sink_sink_first;
-assign litedramcore_bankmachine5_pipe_valid_sink_last = litedramcore_bankmachine5_sink_sink_last;
-assign litedramcore_bankmachine5_pipe_valid_sink_payload_we = litedramcore_bankmachine5_sink_sink_payload_we;
-assign litedramcore_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_bankmachine5_sink_sink_payload_addr;
-assign litedramcore_bankmachine5_source_source_valid = litedramcore_bankmachine5_pipe_valid_source_valid;
-assign litedramcore_bankmachine5_pipe_valid_source_ready = litedramcore_bankmachine5_source_source_ready;
-assign litedramcore_bankmachine5_source_source_first = litedramcore_bankmachine5_pipe_valid_source_first;
-assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_pipe_valid_source_last;
-assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine5_next_state <= 4'd0;
-    litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
-    case (litedramcore_bankmachine5_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                if (litedramcore_bankmachine5_cmd_ready) begin
-                    litedramcore_bankmachine5_next_state <= 3'd5;
-                end
+always @(*) begin
+    main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine5_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                if (litedramcore_bankmachine5_cmd_ready) begin
-                    litedramcore_bankmachine5_next_state <= 3'd7;
-                end
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine5_refresh_req)) begin
-                litedramcore_bankmachine5_next_state <= 1'd0;
-            end
         end
         3'd5: begin
-            litedramcore_bankmachine5_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine5_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine5_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine5_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
-                litedramcore_bankmachine5_next_state <= 3'd4;
-            end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
-                                litedramcore_bankmachine5_next_state <= 2'd2;
-                            end
-                        end else begin
-                            litedramcore_bankmachine5_next_state <= 1'd1;
-                        end
-                    end else begin
-                        litedramcore_bankmachine5_next_state <= 2'd3;
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
@@ -7765,13 +8248,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
-                                litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
+                                main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -7784,22 +8267,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -7814,8 +8297,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7833,14 +8316,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -7852,8 +8335,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7871,13 +8354,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
-                                litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
+                                main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -7890,8 +8373,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7909,13 +8392,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
-                                litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
+                                main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -7928,8 +8411,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7947,14 +8430,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
+                                main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
                             end
                         end else begin
                         end
@@ -7966,8 +8449,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7975,8 +8458,8 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine5_twtpcon_ready) begin
-                litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+            if (main_litedramcore_bankmachine5_twtpcon_ready) begin
+                main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
             end
         end
         3'd5: begin
@@ -7992,15 +8475,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_row_open <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_row_open <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -8018,18 +8501,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_valid <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -8043,12 +8526,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            litedramcore_bankmachine5_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -8059,18 +8542,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_row_close <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_row_close <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
-            litedramcore_bankmachine5_row_close <= 1'd1;
+            main_litedramcore_bankmachine5_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine5_row_close <= 1'd1;
+            main_litedramcore_bankmachine5_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine5_row_close <= 1'd1;
+            main_litedramcore_bankmachine5_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -8085,15 +8568,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -8110,35 +8593,139 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+assign main_litedramcore_bankmachine6_sink_valid = main_litedramcore_bankmachine6_req_valid;
+assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_sink_ready;
+assign main_litedramcore_bankmachine6_sink_payload_we = main_litedramcore_bankmachine6_req_we;
+assign main_litedramcore_bankmachine6_sink_payload_addr = main_litedramcore_bankmachine6_req_addr;
+assign main_litedramcore_bankmachine6_sink_sink_valid = main_litedramcore_bankmachine6_source_valid;
+assign main_litedramcore_bankmachine6_source_ready = main_litedramcore_bankmachine6_sink_sink_ready;
+assign main_litedramcore_bankmachine6_sink_sink_first = main_litedramcore_bankmachine6_source_first;
+assign main_litedramcore_bankmachine6_sink_sink_last = main_litedramcore_bankmachine6_source_last;
+assign main_litedramcore_bankmachine6_sink_sink_payload_we = main_litedramcore_bankmachine6_source_payload_we;
+assign main_litedramcore_bankmachine6_sink_sink_payload_addr = main_litedramcore_bankmachine6_source_payload_addr;
+assign main_litedramcore_bankmachine6_source_source_ready = (main_litedramcore_bankmachine6_req_wdata_ready | main_litedramcore_bankmachine6_req_rdata_valid);
+assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_source_valid | main_litedramcore_bankmachine6_source_source_valid);
+assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_source_source_payload_addr[21:7]);
+assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
+always @(*) begin
+    main_litedramcore_bankmachine6_cmd_payload_a <= 15'd0;
+    if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine6_cmd_payload_a <= main_litedramcore_bankmachine6_source_source_payload_addr[21:7];
+    end else begin
+        main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write);
+assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
+assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine6_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine6_source_valid & main_litedramcore_bankmachine6_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine6_source_payload_addr[21:7] != main_litedramcore_bankmachine6_source_source_payload_addr[21:7])) begin
+            main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine6_syncfifo6_din = {main_litedramcore_bankmachine6_fifo_in_last, main_litedramcore_bankmachine6_fifo_in_first, main_litedramcore_bankmachine6_fifo_in_payload_addr, main_litedramcore_bankmachine6_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout;
+assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout;
+assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout;
+assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout;
+assign main_litedramcore_bankmachine6_sink_ready = main_litedramcore_bankmachine6_syncfifo6_writable;
+assign main_litedramcore_bankmachine6_syncfifo6_we = main_litedramcore_bankmachine6_sink_valid;
+assign main_litedramcore_bankmachine6_fifo_in_first = main_litedramcore_bankmachine6_sink_first;
+assign main_litedramcore_bankmachine6_fifo_in_last = main_litedramcore_bankmachine6_sink_last;
+assign main_litedramcore_bankmachine6_fifo_in_payload_we = main_litedramcore_bankmachine6_sink_payload_we;
+assign main_litedramcore_bankmachine6_fifo_in_payload_addr = main_litedramcore_bankmachine6_sink_payload_addr;
+assign main_litedramcore_bankmachine6_source_valid = main_litedramcore_bankmachine6_syncfifo6_readable;
+assign main_litedramcore_bankmachine6_source_first = main_litedramcore_bankmachine6_fifo_out_first;
+assign main_litedramcore_bankmachine6_source_last = main_litedramcore_bankmachine6_fifo_out_last;
+assign main_litedramcore_bankmachine6_source_payload_we = main_litedramcore_bankmachine6_fifo_out_payload_we;
+assign main_litedramcore_bankmachine6_source_payload_addr = main_litedramcore_bankmachine6_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine6_syncfifo6_re = main_litedramcore_bankmachine6_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine6_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine6_replace) begin
+        main_litedramcore_bankmachine6_wrport_adr <= (main_litedramcore_bankmachine6_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine6_wrport_adr <= main_litedramcore_bankmachine6_produce;
+    end
+end
+assign main_litedramcore_bankmachine6_wrport_dat_w = main_litedramcore_bankmachine6_syncfifo6_din;
+assign main_litedramcore_bankmachine6_wrport_we = (main_litedramcore_bankmachine6_syncfifo6_we & (main_litedramcore_bankmachine6_syncfifo6_writable | main_litedramcore_bankmachine6_replace));
+assign main_litedramcore_bankmachine6_do_read = (main_litedramcore_bankmachine6_syncfifo6_readable & main_litedramcore_bankmachine6_syncfifo6_re);
+assign main_litedramcore_bankmachine6_rdport_adr = main_litedramcore_bankmachine6_consume;
+assign main_litedramcore_bankmachine6_syncfifo6_dout = main_litedramcore_bankmachine6_rdport_dat_r;
+assign main_litedramcore_bankmachine6_syncfifo6_writable = (main_litedramcore_bankmachine6_level != 5'd16);
+assign main_litedramcore_bankmachine6_syncfifo6_readable = (main_litedramcore_bankmachine6_level != 1'd0);
+assign main_litedramcore_bankmachine6_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine6_pipe_valid_source_valid) | main_litedramcore_bankmachine6_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine6_pipe_valid_sink_valid = main_litedramcore_bankmachine6_sink_sink_valid;
+assign main_litedramcore_bankmachine6_sink_sink_ready = main_litedramcore_bankmachine6_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine6_pipe_valid_sink_first = main_litedramcore_bankmachine6_sink_sink_first;
+assign main_litedramcore_bankmachine6_pipe_valid_sink_last = main_litedramcore_bankmachine6_sink_sink_last;
+assign main_litedramcore_bankmachine6_pipe_valid_sink_payload_we = main_litedramcore_bankmachine6_sink_sink_payload_we;
+assign main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine6_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine6_source_source_valid = main_litedramcore_bankmachine6_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine6_pipe_valid_source_ready = main_litedramcore_bankmachine6_source_source_ready;
+assign main_litedramcore_bankmachine6_source_source_first = main_litedramcore_bankmachine6_pipe_valid_source_first;
+assign main_litedramcore_bankmachine6_source_source_last = main_litedramcore_bankmachine6_pipe_valid_source_last;
+assign main_litedramcore_bankmachine6_source_source_payload_we = main_litedramcore_bankmachine6_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine6_source_source_payload_addr = main_litedramcore_bankmachine6_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine6_next_state <= 4'd0;
+    builder_bankmachine6_next_state <= builder_bankmachine6_state;
+    case (builder_bankmachine6_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                if (main_litedramcore_bankmachine6_cmd_ready) begin
+                    builder_bankmachine6_next_state <= 3'd5;
+                end
+            end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                builder_bankmachine6_next_state <= 3'd5;
+            end
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                if (main_litedramcore_bankmachine6_cmd_ready) begin
+                    builder_bankmachine6_next_state <= 3'd7;
+                end
+            end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine6_refresh_req)) begin
+                builder_bankmachine6_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine6_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine6_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine6_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine6_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
+                builder_bankmachine6_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if ((main_litedramcore_bankmachine6_cmd_ready & main_litedramcore_bankmachine6_auto_precharge)) begin
+                                builder_bankmachine6_next_state <= 2'd2;
+                            end
                         end else begin
+                            builder_bankmachine6_next_state <= 1'd1;
                         end
                     end else begin
+                        builder_bankmachine6_next_state <= 2'd3;
                     end
                 end
             end
@@ -8146,21 +8733,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
+            main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -8174,139 +8762,76 @@ always @(*) begin
         end
     endcase
 end
-assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid;
-assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready;
-assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we;
-assign litedramcore_bankmachine6_sink_payload_addr = litedramcore_bankmachine6_req_addr;
-assign litedramcore_bankmachine6_sink_sink_valid = litedramcore_bankmachine6_source_valid;
-assign litedramcore_bankmachine6_source_ready = litedramcore_bankmachine6_sink_sink_ready;
-assign litedramcore_bankmachine6_sink_sink_first = litedramcore_bankmachine6_source_first;
-assign litedramcore_bankmachine6_sink_sink_last = litedramcore_bankmachine6_source_last;
-assign litedramcore_bankmachine6_sink_sink_payload_we = litedramcore_bankmachine6_source_payload_we;
-assign litedramcore_bankmachine6_sink_sink_payload_addr = litedramcore_bankmachine6_source_payload_addr;
-assign litedramcore_bankmachine6_source_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
-assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_source_valid | litedramcore_bankmachine6_source_source_valid);
-assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_source_source_payload_addr[21:7]);
-assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
-always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_a <= 15'd0;
-    if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
-        litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_source_source_payload_addr[21:7];
-    end else begin
-        litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
-assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
-assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
-always @(*) begin
-    litedramcore_bankmachine6_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine6_source_valid & litedramcore_bankmachine6_source_source_valid)) begin
-        if ((litedramcore_bankmachine6_source_payload_addr[21:7] != litedramcore_bankmachine6_source_source_payload_addr[21:7])) begin
-            litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine6_syncfifo6_din = {litedramcore_bankmachine6_fifo_in_last, litedramcore_bankmachine6_fifo_in_first, litedramcore_bankmachine6_fifo_in_payload_addr, litedramcore_bankmachine6_fifo_in_payload_we};
-assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
-assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
-assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
-assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
-assign litedramcore_bankmachine6_sink_ready = litedramcore_bankmachine6_syncfifo6_writable;
-assign litedramcore_bankmachine6_syncfifo6_we = litedramcore_bankmachine6_sink_valid;
-assign litedramcore_bankmachine6_fifo_in_first = litedramcore_bankmachine6_sink_first;
-assign litedramcore_bankmachine6_fifo_in_last = litedramcore_bankmachine6_sink_last;
-assign litedramcore_bankmachine6_fifo_in_payload_we = litedramcore_bankmachine6_sink_payload_we;
-assign litedramcore_bankmachine6_fifo_in_payload_addr = litedramcore_bankmachine6_sink_payload_addr;
-assign litedramcore_bankmachine6_source_valid = litedramcore_bankmachine6_syncfifo6_readable;
-assign litedramcore_bankmachine6_source_first = litedramcore_bankmachine6_fifo_out_first;
-assign litedramcore_bankmachine6_source_last = litedramcore_bankmachine6_fifo_out_last;
-assign litedramcore_bankmachine6_source_payload_we = litedramcore_bankmachine6_fifo_out_payload_we;
-assign litedramcore_bankmachine6_source_payload_addr = litedramcore_bankmachine6_fifo_out_payload_addr;
-assign litedramcore_bankmachine6_syncfifo6_re = litedramcore_bankmachine6_source_ready;
-always @(*) begin
-    litedramcore_bankmachine6_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine6_replace) begin
-        litedramcore_bankmachine6_wrport_adr <= (litedramcore_bankmachine6_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine6_wrport_adr <= litedramcore_bankmachine6_produce;
-    end
-end
-assign litedramcore_bankmachine6_wrport_dat_w = litedramcore_bankmachine6_syncfifo6_din;
-assign litedramcore_bankmachine6_wrport_we = (litedramcore_bankmachine6_syncfifo6_we & (litedramcore_bankmachine6_syncfifo6_writable | litedramcore_bankmachine6_replace));
-assign litedramcore_bankmachine6_do_read = (litedramcore_bankmachine6_syncfifo6_readable & litedramcore_bankmachine6_syncfifo6_re);
-assign litedramcore_bankmachine6_rdport_adr = litedramcore_bankmachine6_consume;
-assign litedramcore_bankmachine6_syncfifo6_dout = litedramcore_bankmachine6_rdport_dat_r;
-assign litedramcore_bankmachine6_syncfifo6_writable = (litedramcore_bankmachine6_level != 5'd16);
-assign litedramcore_bankmachine6_syncfifo6_readable = (litedramcore_bankmachine6_level != 1'd0);
-assign litedramcore_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready);
-assign litedramcore_bankmachine6_pipe_valid_sink_valid = litedramcore_bankmachine6_sink_sink_valid;
-assign litedramcore_bankmachine6_sink_sink_ready = litedramcore_bankmachine6_pipe_valid_sink_ready;
-assign litedramcore_bankmachine6_pipe_valid_sink_first = litedramcore_bankmachine6_sink_sink_first;
-assign litedramcore_bankmachine6_pipe_valid_sink_last = litedramcore_bankmachine6_sink_sink_last;
-assign litedramcore_bankmachine6_pipe_valid_sink_payload_we = litedramcore_bankmachine6_sink_sink_payload_we;
-assign litedramcore_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_bankmachine6_sink_sink_payload_addr;
-assign litedramcore_bankmachine6_source_source_valid = litedramcore_bankmachine6_pipe_valid_source_valid;
-assign litedramcore_bankmachine6_pipe_valid_source_ready = litedramcore_bankmachine6_source_source_ready;
-assign litedramcore_bankmachine6_source_source_first = litedramcore_bankmachine6_pipe_valid_source_first;
-assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_pipe_valid_source_last;
-assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine6_next_state <= 4'd0;
-    litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
-    case (litedramcore_bankmachine6_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                if (litedramcore_bankmachine6_cmd_ready) begin
-                    litedramcore_bankmachine6_next_state <= 3'd5;
-                end
-            end
+always @(*) begin
+    main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine6_state)
+        1'd1: begin
         end
         2'd2: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                if (litedramcore_bankmachine6_cmd_ready) begin
-                    litedramcore_bankmachine6_next_state <= 3'd7;
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
+                            end else begin
+                                main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
                 end
             end
         end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine6_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
         3'd4: begin
-            if ((~litedramcore_bankmachine6_refresh_req)) begin
-                litedramcore_bankmachine6_next_state <= 1'd0;
-            end
         end
         3'd5: begin
-            litedramcore_bankmachine6_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine6_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine6_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine6_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
-                litedramcore_bankmachine6_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
-                                litedramcore_bankmachine6_next_state <= 2'd2;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
+                                main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
+                            end else begin
                             end
                         end else begin
-                            litedramcore_bankmachine6_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine6_next_state <= 2'd3;
                     end
                 end
             end
@@ -8314,8 +8839,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8333,13 +8858,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
-                                litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
+                                main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -8352,8 +8877,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8371,14 +8896,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
+                                main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
                             end
                         end else begin
                         end
@@ -8390,8 +8915,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8399,8 +8924,8 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine6_twtpcon_ready) begin
-                litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+            if (main_litedramcore_bankmachine6_twtpcon_ready) begin
+                main_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
             end
         end
         3'd5: begin
@@ -8416,15 +8941,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_row_open <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_row_open <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -8442,18 +8967,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -8467,12 +8992,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            litedramcore_bankmachine6_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -8483,18 +9008,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_row_close <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_row_close <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
-            litedramcore_bankmachine6_row_close <= 1'd1;
+            main_litedramcore_bankmachine6_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine6_row_close <= 1'd1;
+            main_litedramcore_bankmachine6_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine6_row_close <= 1'd1;
+            main_litedramcore_bankmachine6_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -8509,15 +9034,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -8535,8 +9060,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8554,12 +9079,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -8570,18 +9095,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -8599,11 +9124,11 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
@@ -8621,13 +9146,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
-                                litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
+                                main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -8639,39 +9164,148 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+assign main_litedramcore_bankmachine7_sink_valid = main_litedramcore_bankmachine7_req_valid;
+assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_sink_ready;
+assign main_litedramcore_bankmachine7_sink_payload_we = main_litedramcore_bankmachine7_req_we;
+assign main_litedramcore_bankmachine7_sink_payload_addr = main_litedramcore_bankmachine7_req_addr;
+assign main_litedramcore_bankmachine7_sink_sink_valid = main_litedramcore_bankmachine7_source_valid;
+assign main_litedramcore_bankmachine7_source_ready = main_litedramcore_bankmachine7_sink_sink_ready;
+assign main_litedramcore_bankmachine7_sink_sink_first = main_litedramcore_bankmachine7_source_first;
+assign main_litedramcore_bankmachine7_sink_sink_last = main_litedramcore_bankmachine7_source_last;
+assign main_litedramcore_bankmachine7_sink_sink_payload_we = main_litedramcore_bankmachine7_source_payload_we;
+assign main_litedramcore_bankmachine7_sink_sink_payload_addr = main_litedramcore_bankmachine7_source_payload_addr;
+assign main_litedramcore_bankmachine7_source_source_ready = (main_litedramcore_bankmachine7_req_wdata_ready | main_litedramcore_bankmachine7_req_rdata_valid);
+assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_source_valid | main_litedramcore_bankmachine7_source_source_valid);
+assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_source_source_payload_addr[21:7]);
+assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
+always @(*) begin
+    main_litedramcore_bankmachine7_cmd_payload_a <= 15'd0;
+    if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine7_cmd_payload_a <= main_litedramcore_bankmachine7_source_source_payload_addr[21:7];
+    end else begin
+        main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write);
+assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
+assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine7_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine7_source_valid & main_litedramcore_bankmachine7_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine7_source_payload_addr[21:7] != main_litedramcore_bankmachine7_source_source_payload_addr[21:7])) begin
+            main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine7_syncfifo7_din = {main_litedramcore_bankmachine7_fifo_in_last, main_litedramcore_bankmachine7_fifo_in_first, main_litedramcore_bankmachine7_fifo_in_payload_addr, main_litedramcore_bankmachine7_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout;
+assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout;
+assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout;
+assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout;
+assign main_litedramcore_bankmachine7_sink_ready = main_litedramcore_bankmachine7_syncfifo7_writable;
+assign main_litedramcore_bankmachine7_syncfifo7_we = main_litedramcore_bankmachine7_sink_valid;
+assign main_litedramcore_bankmachine7_fifo_in_first = main_litedramcore_bankmachine7_sink_first;
+assign main_litedramcore_bankmachine7_fifo_in_last = main_litedramcore_bankmachine7_sink_last;
+assign main_litedramcore_bankmachine7_fifo_in_payload_we = main_litedramcore_bankmachine7_sink_payload_we;
+assign main_litedramcore_bankmachine7_fifo_in_payload_addr = main_litedramcore_bankmachine7_sink_payload_addr;
+assign main_litedramcore_bankmachine7_source_valid = main_litedramcore_bankmachine7_syncfifo7_readable;
+assign main_litedramcore_bankmachine7_source_first = main_litedramcore_bankmachine7_fifo_out_first;
+assign main_litedramcore_bankmachine7_source_last = main_litedramcore_bankmachine7_fifo_out_last;
+assign main_litedramcore_bankmachine7_source_payload_we = main_litedramcore_bankmachine7_fifo_out_payload_we;
+assign main_litedramcore_bankmachine7_source_payload_addr = main_litedramcore_bankmachine7_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine7_syncfifo7_re = main_litedramcore_bankmachine7_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine7_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine7_replace) begin
+        main_litedramcore_bankmachine7_wrport_adr <= (main_litedramcore_bankmachine7_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine7_wrport_adr <= main_litedramcore_bankmachine7_produce;
+    end
+end
+assign main_litedramcore_bankmachine7_wrport_dat_w = main_litedramcore_bankmachine7_syncfifo7_din;
+assign main_litedramcore_bankmachine7_wrport_we = (main_litedramcore_bankmachine7_syncfifo7_we & (main_litedramcore_bankmachine7_syncfifo7_writable | main_litedramcore_bankmachine7_replace));
+assign main_litedramcore_bankmachine7_do_read = (main_litedramcore_bankmachine7_syncfifo7_readable & main_litedramcore_bankmachine7_syncfifo7_re);
+assign main_litedramcore_bankmachine7_rdport_adr = main_litedramcore_bankmachine7_consume;
+assign main_litedramcore_bankmachine7_syncfifo7_dout = main_litedramcore_bankmachine7_rdport_dat_r;
+assign main_litedramcore_bankmachine7_syncfifo7_writable = (main_litedramcore_bankmachine7_level != 5'd16);
+assign main_litedramcore_bankmachine7_syncfifo7_readable = (main_litedramcore_bankmachine7_level != 1'd0);
+assign main_litedramcore_bankmachine7_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine7_pipe_valid_source_valid) | main_litedramcore_bankmachine7_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine7_pipe_valid_sink_valid = main_litedramcore_bankmachine7_sink_sink_valid;
+assign main_litedramcore_bankmachine7_sink_sink_ready = main_litedramcore_bankmachine7_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine7_pipe_valid_sink_first = main_litedramcore_bankmachine7_sink_sink_first;
+assign main_litedramcore_bankmachine7_pipe_valid_sink_last = main_litedramcore_bankmachine7_sink_sink_last;
+assign main_litedramcore_bankmachine7_pipe_valid_sink_payload_we = main_litedramcore_bankmachine7_sink_sink_payload_we;
+assign main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine7_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine7_source_source_valid = main_litedramcore_bankmachine7_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine7_pipe_valid_source_ready = main_litedramcore_bankmachine7_source_source_ready;
+assign main_litedramcore_bankmachine7_source_source_first = main_litedramcore_bankmachine7_pipe_valid_source_first;
+assign main_litedramcore_bankmachine7_source_source_last = main_litedramcore_bankmachine7_pipe_valid_source_last;
+assign main_litedramcore_bankmachine7_source_source_payload_we = main_litedramcore_bankmachine7_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine7_source_source_payload_addr = main_litedramcore_bankmachine7_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine7_next_state <= 4'd0;
+    builder_bankmachine7_next_state <= builder_bankmachine7_state;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                if (main_litedramcore_bankmachine7_cmd_ready) begin
+                    builder_bankmachine7_next_state <= 3'd5;
+                end
             end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                builder_bankmachine7_next_state <= 3'd5;
+            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                if (main_litedramcore_bankmachine7_cmd_ready) begin
+                    builder_bankmachine7_next_state <= 3'd7;
+                end
             end
         end
         3'd4: begin
-            litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+            if ((~main_litedramcore_bankmachine7_refresh_req)) begin
+                builder_bankmachine7_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine7_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine7_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine7_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine7_next_state <= 1'd0;
         end
         default: begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
+                builder_bankmachine7_next_state <= 3'd4;
+            end else begin
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if ((main_litedramcore_bankmachine7_cmd_ready & main_litedramcore_bankmachine7_auto_precharge)) begin
+                                builder_bankmachine7_next_state <= 2'd2;
+                            end
+                        end else begin
+                            builder_bankmachine7_next_state <= 1'd1;
+                        end
+                    end else begin
+                        builder_bankmachine7_next_state <= 2'd3;
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8689,14 +9323,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
                             end
                         end else begin
                         end
@@ -8708,8 +9342,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8717,6 +9351,9 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
+            if (main_litedramcore_bankmachine7_twtpcon_ready) begin
+                main_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -8727,173 +9364,19 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
-                                litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
-assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid;
-assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready;
-assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we;
-assign litedramcore_bankmachine7_sink_payload_addr = litedramcore_bankmachine7_req_addr;
-assign litedramcore_bankmachine7_sink_sink_valid = litedramcore_bankmachine7_source_valid;
-assign litedramcore_bankmachine7_source_ready = litedramcore_bankmachine7_sink_sink_ready;
-assign litedramcore_bankmachine7_sink_sink_first = litedramcore_bankmachine7_source_first;
-assign litedramcore_bankmachine7_sink_sink_last = litedramcore_bankmachine7_source_last;
-assign litedramcore_bankmachine7_sink_sink_payload_we = litedramcore_bankmachine7_source_payload_we;
-assign litedramcore_bankmachine7_sink_sink_payload_addr = litedramcore_bankmachine7_source_payload_addr;
-assign litedramcore_bankmachine7_source_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
-assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_source_valid | litedramcore_bankmachine7_source_source_valid);
-assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_source_source_payload_addr[21:7]);
-assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
-always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_a <= 15'd0;
-    if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
-        litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_source_source_payload_addr[21:7];
-    end else begin
-        litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
-assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
-assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
-always @(*) begin
-    litedramcore_bankmachine7_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine7_source_valid & litedramcore_bankmachine7_source_source_valid)) begin
-        if ((litedramcore_bankmachine7_source_payload_addr[21:7] != litedramcore_bankmachine7_source_source_payload_addr[21:7])) begin
-            litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine7_syncfifo7_din = {litedramcore_bankmachine7_fifo_in_last, litedramcore_bankmachine7_fifo_in_first, litedramcore_bankmachine7_fifo_in_payload_addr, litedramcore_bankmachine7_fifo_in_payload_we};
-assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
-assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
-assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
-assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
-assign litedramcore_bankmachine7_sink_ready = litedramcore_bankmachine7_syncfifo7_writable;
-assign litedramcore_bankmachine7_syncfifo7_we = litedramcore_bankmachine7_sink_valid;
-assign litedramcore_bankmachine7_fifo_in_first = litedramcore_bankmachine7_sink_first;
-assign litedramcore_bankmachine7_fifo_in_last = litedramcore_bankmachine7_sink_last;
-assign litedramcore_bankmachine7_fifo_in_payload_we = litedramcore_bankmachine7_sink_payload_we;
-assign litedramcore_bankmachine7_fifo_in_payload_addr = litedramcore_bankmachine7_sink_payload_addr;
-assign litedramcore_bankmachine7_source_valid = litedramcore_bankmachine7_syncfifo7_readable;
-assign litedramcore_bankmachine7_source_first = litedramcore_bankmachine7_fifo_out_first;
-assign litedramcore_bankmachine7_source_last = litedramcore_bankmachine7_fifo_out_last;
-assign litedramcore_bankmachine7_source_payload_we = litedramcore_bankmachine7_fifo_out_payload_we;
-assign litedramcore_bankmachine7_source_payload_addr = litedramcore_bankmachine7_fifo_out_payload_addr;
-assign litedramcore_bankmachine7_syncfifo7_re = litedramcore_bankmachine7_source_ready;
-always @(*) begin
-    litedramcore_bankmachine7_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine7_replace) begin
-        litedramcore_bankmachine7_wrport_adr <= (litedramcore_bankmachine7_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine7_wrport_adr <= litedramcore_bankmachine7_produce;
-    end
-end
-assign litedramcore_bankmachine7_wrport_dat_w = litedramcore_bankmachine7_syncfifo7_din;
-assign litedramcore_bankmachine7_wrport_we = (litedramcore_bankmachine7_syncfifo7_we & (litedramcore_bankmachine7_syncfifo7_writable | litedramcore_bankmachine7_replace));
-assign litedramcore_bankmachine7_do_read = (litedramcore_bankmachine7_syncfifo7_readable & litedramcore_bankmachine7_syncfifo7_re);
-assign litedramcore_bankmachine7_rdport_adr = litedramcore_bankmachine7_consume;
-assign litedramcore_bankmachine7_syncfifo7_dout = litedramcore_bankmachine7_rdport_dat_r;
-assign litedramcore_bankmachine7_syncfifo7_writable = (litedramcore_bankmachine7_level != 5'd16);
-assign litedramcore_bankmachine7_syncfifo7_readable = (litedramcore_bankmachine7_level != 1'd0);
-assign litedramcore_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready);
-assign litedramcore_bankmachine7_pipe_valid_sink_valid = litedramcore_bankmachine7_sink_sink_valid;
-assign litedramcore_bankmachine7_sink_sink_ready = litedramcore_bankmachine7_pipe_valid_sink_ready;
-assign litedramcore_bankmachine7_pipe_valid_sink_first = litedramcore_bankmachine7_sink_sink_first;
-assign litedramcore_bankmachine7_pipe_valid_sink_last = litedramcore_bankmachine7_sink_sink_last;
-assign litedramcore_bankmachine7_pipe_valid_sink_payload_we = litedramcore_bankmachine7_sink_sink_payload_we;
-assign litedramcore_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_bankmachine7_sink_sink_payload_addr;
-assign litedramcore_bankmachine7_source_source_valid = litedramcore_bankmachine7_pipe_valid_source_valid;
-assign litedramcore_bankmachine7_pipe_valid_source_ready = litedramcore_bankmachine7_source_source_ready;
-assign litedramcore_bankmachine7_source_source_first = litedramcore_bankmachine7_pipe_valid_source_first;
-assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_pipe_valid_source_last;
-assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine7_next_state <= 4'd0;
-    litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
-    case (litedramcore_bankmachine7_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                if (litedramcore_bankmachine7_cmd_ready) begin
-                    litedramcore_bankmachine7_next_state <= 3'd5;
-                end
-            end
-        end
-        2'd2: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_next_state <= 3'd5;
-            end
-        end
-        2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                if (litedramcore_bankmachine7_cmd_ready) begin
-                    litedramcore_bankmachine7_next_state <= 3'd7;
-                end
-            end
-        end
-        3'd4: begin
-            if ((~litedramcore_bankmachine7_refresh_req)) begin
-                litedramcore_bankmachine7_next_state <= 1'd0;
-            end
-        end
-        3'd5: begin
-            litedramcore_bankmachine7_next_state <= 3'd6;
-        end
-        3'd6: begin
-            litedramcore_bankmachine7_next_state <= 2'd3;
-        end
-        3'd7: begin
-            litedramcore_bankmachine7_next_state <= 4'd8;
-        end
-        4'd8: begin
-            litedramcore_bankmachine7_next_state <= 1'd0;
-        end
-        default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
-                litedramcore_bankmachine7_next_state <= 3'd4;
-            end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
-                                litedramcore_bankmachine7_next_state <= 2'd2;
-                            end
-                        end else begin
-                            litedramcore_bankmachine7_next_state <= 1'd1;
-                        end
-                    end else begin
-                        litedramcore_bankmachine7_next_state <= 2'd3;
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_row_open <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_row_open <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -8911,18 +9394,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -8936,12 +9419,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            litedramcore_bankmachine7_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -8952,41 +9435,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_row_close <= 1'd0;
-    case (litedramcore_bankmachine7_state)
-        1'd1: begin
-            litedramcore_bankmachine7_row_close <= 1'd1;
-        end
-        2'd2: begin
-            litedramcore_bankmachine7_row_close <= 1'd1;
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            litedramcore_bankmachine7_row_close <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_row_close <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd2: begin
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -8997,34 +9457,19 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
-                                litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -9042,8 +9487,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9061,12 +9506,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -9077,18 +9522,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -9106,11 +9551,11 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
@@ -9128,13 +9573,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
-                                litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
+                                main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -9147,22 +9592,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -9177,8 +9622,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9196,14 +9641,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -9215,8 +9660,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9234,13 +9679,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
-                                litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
+                                main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -9253,8 +9698,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9272,14 +9717,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
+                                main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready;
                             end else begin
-                                litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
                             end
                         end else begin
                         end
@@ -9290,283 +9735,256 @@ always @(*) begin
         end
     endcase
 end
+assign main_litedramcore_nphases = (main_a7ddrphy_rdphase_storage - 1'd1);
+assign main_litedramcore_rdphase = (main_a7ddrphy_wrphase_storage - 1'd1);
+assign main_litedramcore_trrdcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we)));
+assign main_litedramcore_tfawcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we)));
+assign main_litedramcore_ras_allowed = (main_litedramcore_trrdcon_ready & main_litedramcore_tfawcon_ready);
+assign main_litedramcore_tccdcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_cmd_payload_is_write | main_litedramcore_choose_req_cmd_payload_is_read));
+assign main_litedramcore_cas_allowed = main_litedramcore_tccdcon_ready;
+assign main_litedramcore_twtrcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+assign main_litedramcore_read_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_read) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_read)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_read)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_read)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_read)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_read)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_read)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_read));
+assign main_litedramcore_write_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_write) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_write)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_write)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_write)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_write)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_write)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_write)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_write));
+assign main_litedramcore_max_time0 = (main_litedramcore_time0 == 1'd0);
+assign main_litedramcore_max_time1 = (main_litedramcore_time1 == 1'd0);
+assign main_litedramcore_bankmachine0_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine1_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine2_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine3_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine4_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine5_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine6_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine7_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_go_to_refresh = (((((((main_litedramcore_bankmachine0_refresh_gnt & main_litedramcore_bankmachine1_refresh_gnt) & main_litedramcore_bankmachine2_refresh_gnt) & main_litedramcore_bankmachine3_refresh_gnt) & main_litedramcore_bankmachine4_refresh_gnt) & main_litedramcore_bankmachine5_refresh_gnt) & main_litedramcore_bankmachine6_refresh_gnt) & main_litedramcore_bankmachine7_refresh_gnt);
+assign main_litedramcore_interface_rdata = {main_litedramcore_dfi_p3_rddata, main_litedramcore_dfi_p2_rddata, main_litedramcore_dfi_p1_rddata, main_litedramcore_dfi_p0_rddata};
+assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
+assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
+assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
+assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
+assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
+assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
+assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
+assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
 always @(*) begin
-    litedramcore_bankmachine7_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine7_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            if (litedramcore_bankmachine7_twtpcon_ready) begin
-                litedramcore_bankmachine7_refresh_gnt <= 1'd1;
-            end
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-assign litedramcore_rdcmdphase = (a7ddrphy_rdphase_storage - 1'd1);
-assign litedramcore_wrcmdphase = (a7ddrphy_wrphase_storage - 1'd1);
-assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
-assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
-assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready);
-assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read));
-assign litedramcore_cas_allowed = litedramcore_tccdcon_ready;
-assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
-assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read));
-assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write));
-assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0);
-assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0);
-assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt);
-assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata};
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
-always @(*) begin
-    litedramcore_choose_cmd_valids <= 8'd0;
-    litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids <= 8'd0;
+    main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
 end
-assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
-assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
-assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1;
-assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
-assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
-assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
-assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
+assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids;
+assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_self0;
+assign main_litedramcore_choose_cmd_cmd_payload_a = builder_rhs_self1;
+assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_self2;
+assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_self3;
+assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_self4;
+assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_self5;
 always @(*) begin
-    litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
-    if (litedramcore_choose_cmd_cmd_valid) begin
-        litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
+    main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
+    if (main_litedramcore_choose_cmd_cmd_valid) begin
+        main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_self0;
     end
 end
 always @(*) begin
-    litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
-    if (litedramcore_choose_cmd_cmd_valid) begin
-        litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
+    main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
+    if (main_litedramcore_choose_cmd_cmd_valid) begin
+        main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_self1;
     end
 end
 always @(*) begin
-    litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
-    if (litedramcore_choose_cmd_cmd_valid) begin
-        litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
+    main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
+    if (main_litedramcore_choose_cmd_cmd_valid) begin
+        main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_self2;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
-        litedramcore_bankmachine0_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine0_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin
+        main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
-        litedramcore_bankmachine0_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin
+        main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
-        litedramcore_bankmachine1_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine1_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin
+        main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
-        litedramcore_bankmachine1_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin
+        main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
-        litedramcore_bankmachine2_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine2_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin
+        main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
-        litedramcore_bankmachine2_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin
+        main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
-        litedramcore_bankmachine3_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine3_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin
+        main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
-        litedramcore_bankmachine3_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin
+        main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
-        litedramcore_bankmachine4_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine4_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin
+        main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
-        litedramcore_bankmachine4_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin
+        main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
-        litedramcore_bankmachine5_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine5_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin
+        main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
-        litedramcore_bankmachine5_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin
+        main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
-        litedramcore_bankmachine6_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine6_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin
+        main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
-        litedramcore_bankmachine6_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin
+        main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
-        litedramcore_bankmachine7_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine7_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin
+        main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
-        litedramcore_bankmachine7_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin
+        main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
     end
 end
-assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
+assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid));
 always @(*) begin
-    litedramcore_choose_req_valids <= 8'd0;
-    litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids <= 8'd0;
+    main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
 end
-assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
-assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
-assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7;
-assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8;
-assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9;
-assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
-assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
+assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids;
+assign main_litedramcore_choose_req_cmd_valid = builder_rhs_self6;
+assign main_litedramcore_choose_req_cmd_payload_a = builder_rhs_self7;
+assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_self8;
+assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_self9;
+assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_self10;
+assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_self11;
 always @(*) begin
-    litedramcore_choose_req_cmd_payload_cas <= 1'd0;
-    if (litedramcore_choose_req_cmd_valid) begin
-        litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
+    main_litedramcore_choose_req_cmd_payload_cas <= 1'd0;
+    if (main_litedramcore_choose_req_cmd_valid) begin
+        main_litedramcore_choose_req_cmd_payload_cas <= builder_t_self3;
     end
 end
 always @(*) begin
-    litedramcore_choose_req_cmd_payload_ras <= 1'd0;
-    if (litedramcore_choose_req_cmd_valid) begin
-        litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
+    main_litedramcore_choose_req_cmd_payload_ras <= 1'd0;
+    if (main_litedramcore_choose_req_cmd_valid) begin
+        main_litedramcore_choose_req_cmd_payload_ras <= builder_t_self4;
     end
 end
 always @(*) begin
-    litedramcore_choose_req_cmd_payload_we <= 1'd0;
-    if (litedramcore_choose_req_cmd_valid) begin
-        litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
+    main_litedramcore_choose_req_cmd_payload_we <= 1'd0;
+    if (main_litedramcore_choose_req_cmd_valid) begin
+        main_litedramcore_choose_req_cmd_payload_we <= builder_t_self5;
     end
 end
-assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
-assign litedramcore_dfi_p0_reset_n = 1'd1;
-assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}};
-assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}};
-assign litedramcore_dfi_p1_reset_n = 1'd1;
-assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}};
-assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}};
-assign litedramcore_dfi_p2_reset_n = 1'd1;
-assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}};
-assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}};
-assign litedramcore_dfi_p3_reset_n = 1'd1;
-assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}};
-assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}};
-assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]);
+assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid));
+assign main_litedramcore_dfi_p0_reset_n = 1'd1;
+assign main_litedramcore_dfi_p0_cke = {1{main_litedramcore_steerer4}};
+assign main_litedramcore_dfi_p0_odt = {1{main_litedramcore_steerer5}};
+assign main_litedramcore_dfi_p1_reset_n = 1'd1;
+assign main_litedramcore_dfi_p1_cke = {1{main_litedramcore_steerer6}};
+assign main_litedramcore_dfi_p1_odt = {1{main_litedramcore_steerer7}};
+assign main_litedramcore_dfi_p2_reset_n = 1'd1;
+assign main_litedramcore_dfi_p2_cke = {1{main_litedramcore_steerer8}};
+assign main_litedramcore_dfi_p2_odt = {1{main_litedramcore_steerer9}};
+assign main_litedramcore_dfi_p3_reset_n = 1'd1;
+assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer10}};
+assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer11}};
+assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]);
 always @(*) begin
-    litedramcore_multiplexer_next_state <= 4'd0;
-    litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
-    case (litedramcore_multiplexer_state)
+    builder_multiplexer_next_state <= 4'd0;
+    builder_multiplexer_next_state <= builder_multiplexer_state;
+    case (builder_multiplexer_state)
         1'd1: begin
-            if (litedramcore_read_available) begin
-                if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
-                    litedramcore_multiplexer_next_state <= 2'd3;
+            if (main_litedramcore_read_available) begin
+                if (((~main_litedramcore_write_available) | main_litedramcore_max_time1)) begin
+                    builder_multiplexer_next_state <= 2'd3;
                 end
             end
-            if (litedramcore_go_to_refresh) begin
-                litedramcore_multiplexer_next_state <= 2'd2;
+            if (main_litedramcore_go_to_refresh) begin
+                builder_multiplexer_next_state <= 2'd2;
             end
         end
         2'd2: begin
-            if (litedramcore_cmd_last) begin
-                litedramcore_multiplexer_next_state <= 1'd0;
+            if (main_litedramcore_cmd_last) begin
+                builder_multiplexer_next_state <= 1'd0;
             end
         end
         2'd3: begin
-            if (litedramcore_twtrcon_ready) begin
-                litedramcore_multiplexer_next_state <= 1'd0;
+            if (main_litedramcore_twtrcon_ready) begin
+                builder_multiplexer_next_state <= 1'd0;
             end
         end
         3'd4: begin
-            litedramcore_multiplexer_next_state <= 3'd5;
+            builder_multiplexer_next_state <= 3'd5;
         end
         3'd5: begin
-            litedramcore_multiplexer_next_state <= 3'd6;
+            builder_multiplexer_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_multiplexer_next_state <= 3'd7;
+            builder_multiplexer_next_state <= 3'd7;
         end
         3'd7: begin
-            litedramcore_multiplexer_next_state <= 4'd8;
+            builder_multiplexer_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_multiplexer_next_state <= 4'd9;
+            builder_multiplexer_next_state <= 4'd9;
         end
         4'd9: begin
-            litedramcore_multiplexer_next_state <= 4'd10;
+            builder_multiplexer_next_state <= 4'd10;
         end
         4'd10: begin
-            litedramcore_multiplexer_next_state <= 1'd1;
+            builder_multiplexer_next_state <= 1'd1;
         end
         default: begin
-            if (litedramcore_write_available) begin
-                if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
-                    litedramcore_multiplexer_next_state <= 3'd4;
+            if (main_litedramcore_write_available) begin
+                if (((~main_litedramcore_read_available) | main_litedramcore_max_time0)) begin
+                    builder_multiplexer_next_state <= 3'd4;
                 end
             end
-            if (litedramcore_go_to_refresh) begin
-                litedramcore_multiplexer_next_state <= 2'd2;
+            if (main_litedramcore_go_to_refresh) begin
+                builder_multiplexer_next_state <= 2'd2;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_req_want_writes <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_en0 <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_choose_req_want_writes <= 1'd1;
         end
         2'd2: begin
         end
@@ -9587,19 +10005,17 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
+            main_litedramcore_en0 <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_steerer_sel3 <= 2'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer_sel3 <= 1'd0;
-            if ((a7ddrphy_wrphase_storage == 2'd3)) begin
-                litedramcore_steerer_sel3 <= 2'd2;
-            end
-            if ((litedramcore_wrcmdphase == 2'd3)) begin
-                litedramcore_steerer_sel3 <= 1'd1;
+            if (1'd0) begin
+            end else begin
+                main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
             end
         end
         2'd2: begin
@@ -9621,25 +10037,17 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_steerer_sel3 <= 1'd0;
-            if ((a7ddrphy_rdphase_storage == 2'd3)) begin
-                litedramcore_steerer_sel3 <= 2'd2;
-            end
-            if ((litedramcore_rdcmdphase == 2'd3)) begin
-                litedramcore_steerer_sel3 <= 1'd1;
+            if (1'd0) begin
+            end else begin
+                main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_req_cmd_ready <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_choose_req_want_reads <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            if (1'd0) begin
-                litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
-            end else begin
-                litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
-            end
         end
         2'd2: begin
         end
@@ -9660,19 +10068,15 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            if (1'd0) begin
-                litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
-            end else begin
-                litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
-            end
+            main_litedramcore_choose_req_want_reads <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_en1 <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_choose_req_want_writes <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_en1 <= 1'd1;
+            main_litedramcore_choose_req_want_writes <= 1'd1;
         end
         2'd2: begin
         end
@@ -9697,19 +10101,16 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_steerer_sel0 <= 2'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_choose_req_cmd_ready <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer_sel0 <= 1'd0;
-            if ((a7ddrphy_wrphase_storage == 1'd0)) begin
-                litedramcore_steerer_sel0 <= 2'd2;
-            end
-            if ((litedramcore_wrcmdphase == 1'd0)) begin
-                litedramcore_steerer_sel0 <= 1'd1;
+            if (1'd0) begin
+                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+            end else begin
+                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
             end
         end
         2'd2: begin
-            litedramcore_steerer_sel0 <= 2'd3;
         end
         2'd3: begin
         end
@@ -9728,23 +10129,21 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_steerer_sel0 <= 1'd0;
-            if ((a7ddrphy_rdphase_storage == 1'd0)) begin
-                litedramcore_steerer_sel0 <= 2'd2;
-            end
-            if ((litedramcore_rdcmdphase == 1'd0)) begin
-                litedramcore_steerer_sel0 <= 1'd1;
+            if (1'd0) begin
+                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+            end else begin
+                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_cmd_ready <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_en1 <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
+            main_litedramcore_en1 <= 1'd1;
         end
         2'd2: begin
-            litedramcore_cmd_ready <= 1'd1;
         end
         2'd3: begin
         end
@@ -9767,15 +10166,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_steerer_sel1 <= 2'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_steerer3 <= 2'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer_sel1 <= 1'd0;
-            if ((a7ddrphy_wrphase_storage == 1'd1)) begin
-                litedramcore_steerer_sel1 <= 2'd2;
+            main_litedramcore_steerer3 <= 1'd0;
+            if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin
+                main_litedramcore_steerer3 <= 2'd2;
             end
-            if ((litedramcore_wrcmdphase == 1'd1)) begin
-                litedramcore_steerer_sel1 <= 1'd1;
+            if ((main_litedramcore_rdphase == 2'd3)) begin
+                main_litedramcore_steerer3 <= 1'd1;
             end
         end
         2'd2: begin
@@ -9797,29 +10196,30 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_steerer_sel1 <= 1'd0;
-            if ((a7ddrphy_rdphase_storage == 1'd1)) begin
-                litedramcore_steerer_sel1 <= 2'd2;
+            main_litedramcore_steerer3 <= 1'd0;
+            if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin
+                main_litedramcore_steerer3 <= 2'd2;
             end
-            if ((litedramcore_rdcmdphase == 1'd1)) begin
-                litedramcore_steerer_sel1 <= 1'd1;
+            if ((main_litedramcore_nphases == 2'd3)) begin
+                main_litedramcore_steerer3 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_steerer_sel2 <= 2'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_steerer0 <= 2'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer_sel2 <= 1'd0;
-            if ((a7ddrphy_wrphase_storage == 2'd2)) begin
-                litedramcore_steerer_sel2 <= 2'd2;
+            main_litedramcore_steerer0 <= 1'd0;
+            if ((main_a7ddrphy_wrphase_storage == 1'd0)) begin
+                main_litedramcore_steerer0 <= 2'd2;
             end
-            if ((litedramcore_wrcmdphase == 2'd2)) begin
-                litedramcore_steerer_sel2 <= 1'd1;
+            if ((main_litedramcore_rdphase == 1'd0)) begin
+                main_litedramcore_steerer0 <= 1'd1;
             end
         end
         2'd2: begin
+            main_litedramcore_steerer0 <= 2'd3;
         end
         2'd3: begin
         end
@@ -9838,26 +10238,23 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_steerer_sel2 <= 1'd0;
-            if ((a7ddrphy_rdphase_storage == 2'd2)) begin
-                litedramcore_steerer_sel2 <= 2'd2;
+            main_litedramcore_steerer0 <= 1'd0;
+            if ((main_a7ddrphy_rdphase_storage == 1'd0)) begin
+                main_litedramcore_steerer0 <= 2'd2;
             end
-            if ((litedramcore_rdcmdphase == 2'd2)) begin
-                litedramcore_steerer_sel2 <= 1'd1;
+            if ((main_litedramcore_nphases == 1'd0)) begin
+                main_litedramcore_steerer0 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_cmd_want_activates <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_cmd_ready <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            if (1'd0) begin
-            end else begin
-                litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
-            end
         end
         2'd2: begin
+            main_litedramcore_cmd_ready <= 1'd1;
         end
         2'd3: begin
         end
@@ -9876,17 +10273,20 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            if (1'd0) begin
-            end else begin
-                litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_en0 <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_steerer1 <= 2'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
+            main_litedramcore_steerer1 <= 1'd0;
+            if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin
+                main_litedramcore_steerer1 <= 2'd2;
+            end
+            if ((main_litedramcore_rdphase == 1'd1)) begin
+                main_litedramcore_steerer1 <= 1'd1;
+            end
         end
         2'd2: begin
         end
@@ -9907,17 +10307,26 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_en0 <= 1'd1;
+            main_litedramcore_steerer1 <= 1'd0;
+            if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin
+                main_litedramcore_steerer1 <= 2'd2;
+            end
+            if ((main_litedramcore_nphases == 1'd1)) begin
+                main_litedramcore_steerer1 <= 1'd1;
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_cmd_cmd_ready <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_steerer2 <= 2'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            if (1'd0) begin
-            end else begin
-                litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+            main_litedramcore_steerer2 <= 1'd0;
+            if ((main_a7ddrphy_wrphase_storage == 2'd2)) begin
+                main_litedramcore_steerer2 <= 2'd2;
+            end
+            if ((main_litedramcore_rdphase == 2'd2)) begin
+                main_litedramcore_steerer2 <= 1'd1;
             end
         end
         2'd2: begin
@@ -9939,17 +10348,24 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            if (1'd0) begin
-            end else begin
-                litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+            main_litedramcore_steerer2 <= 1'd0;
+            if ((main_a7ddrphy_rdphase_storage == 2'd2)) begin
+                main_litedramcore_steerer2 <= 2'd2;
+            end
+            if ((main_litedramcore_nphases == 2'd2)) begin
+                main_litedramcore_steerer2 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_req_want_reads <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_choose_cmd_want_activates <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
+            if (1'd0) begin
+            end else begin
+                main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
+            end
         end
         2'd2: begin
         end
@@ -9970,2012 +10386,2012 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_choose_req_want_reads <= 1'd1;
+            if (1'd0) begin
+            end else begin
+                main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
+            end
         end
     endcase
 end
-assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
-assign litedramcore_interface_bank0_addr = rhs_array_muxed12;
-assign litedramcore_interface_bank0_we = rhs_array_muxed13;
-assign litedramcore_interface_bank0_valid = rhs_array_muxed14;
-assign litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock));
-assign litedramcore_interface_bank1_addr = rhs_array_muxed15;
-assign litedramcore_interface_bank1_we = rhs_array_muxed16;
-assign litedramcore_interface_bank1_valid = rhs_array_muxed17;
-assign litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock));
-assign litedramcore_interface_bank2_addr = rhs_array_muxed18;
-assign litedramcore_interface_bank2_we = rhs_array_muxed19;
-assign litedramcore_interface_bank2_valid = rhs_array_muxed20;
-assign litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock));
-assign litedramcore_interface_bank3_addr = rhs_array_muxed21;
-assign litedramcore_interface_bank3_we = rhs_array_muxed22;
-assign litedramcore_interface_bank3_valid = rhs_array_muxed23;
-assign litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock));
-assign litedramcore_interface_bank4_addr = rhs_array_muxed24;
-assign litedramcore_interface_bank4_we = rhs_array_muxed25;
-assign litedramcore_interface_bank4_valid = rhs_array_muxed26;
-assign litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock));
-assign litedramcore_interface_bank5_addr = rhs_array_muxed27;
-assign litedramcore_interface_bank5_we = rhs_array_muxed28;
-assign litedramcore_interface_bank5_valid = rhs_array_muxed29;
-assign litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock));
-assign litedramcore_interface_bank6_addr = rhs_array_muxed30;
-assign litedramcore_interface_bank6_we = rhs_array_muxed31;
-assign litedramcore_interface_bank6_valid = rhs_array_muxed32;
-assign litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock));
-assign litedramcore_interface_bank7_addr = rhs_array_muxed33;
-assign litedramcore_interface_bank7_we = rhs_array_muxed34;
-assign litedramcore_interface_bank7_valid = rhs_array_muxed35;
-assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready));
-assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1;
-assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8;
-always @(*) begin
-    litedramcore_interface_wdata <= 128'd0;
-    case ({litedramcore_new_master_wdata_ready1})
+assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock));
+assign main_litedramcore_interface_bank0_addr = builder_rhs_self12;
+assign main_litedramcore_interface_bank0_we = builder_rhs_self13;
+assign main_litedramcore_interface_bank0_valid = builder_rhs_self14;
+assign builder_roundrobin1_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin1_ce = ((~main_litedramcore_interface_bank1_valid) & (~main_litedramcore_interface_bank1_lock));
+assign main_litedramcore_interface_bank1_addr = builder_rhs_self15;
+assign main_litedramcore_interface_bank1_we = builder_rhs_self16;
+assign main_litedramcore_interface_bank1_valid = builder_rhs_self17;
+assign builder_roundrobin2_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin2_ce = ((~main_litedramcore_interface_bank2_valid) & (~main_litedramcore_interface_bank2_lock));
+assign main_litedramcore_interface_bank2_addr = builder_rhs_self18;
+assign main_litedramcore_interface_bank2_we = builder_rhs_self19;
+assign main_litedramcore_interface_bank2_valid = builder_rhs_self20;
+assign builder_roundrobin3_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin3_ce = ((~main_litedramcore_interface_bank3_valid) & (~main_litedramcore_interface_bank3_lock));
+assign main_litedramcore_interface_bank3_addr = builder_rhs_self21;
+assign main_litedramcore_interface_bank3_we = builder_rhs_self22;
+assign main_litedramcore_interface_bank3_valid = builder_rhs_self23;
+assign builder_roundrobin4_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin4_ce = ((~main_litedramcore_interface_bank4_valid) & (~main_litedramcore_interface_bank4_lock));
+assign main_litedramcore_interface_bank4_addr = builder_rhs_self24;
+assign main_litedramcore_interface_bank4_we = builder_rhs_self25;
+assign main_litedramcore_interface_bank4_valid = builder_rhs_self26;
+assign builder_roundrobin5_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin5_ce = ((~main_litedramcore_interface_bank5_valid) & (~main_litedramcore_interface_bank5_lock));
+assign main_litedramcore_interface_bank5_addr = builder_rhs_self27;
+assign main_litedramcore_interface_bank5_we = builder_rhs_self28;
+assign main_litedramcore_interface_bank5_valid = builder_rhs_self29;
+assign builder_roundrobin6_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin6_ce = ((~main_litedramcore_interface_bank6_valid) & (~main_litedramcore_interface_bank6_lock));
+assign main_litedramcore_interface_bank6_addr = builder_rhs_self30;
+assign main_litedramcore_interface_bank6_we = builder_rhs_self31;
+assign main_litedramcore_interface_bank6_valid = builder_rhs_self32;
+assign builder_roundrobin7_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin7_ce = ((~main_litedramcore_interface_bank7_valid) & (~main_litedramcore_interface_bank7_lock));
+assign main_litedramcore_interface_bank7_addr = builder_rhs_self33;
+assign main_litedramcore_interface_bank7_we = builder_rhs_self34;
+assign main_litedramcore_interface_bank7_valid = builder_rhs_self35;
+assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready));
+assign main_user_port_wdata_ready = builder_new_master_wdata_ready1;
+assign main_user_port_rdata_valid = builder_new_master_rdata_valid8;
+always @(*) begin
+    main_litedramcore_interface_wdata <= 128'd0;
+    case ({builder_new_master_wdata_ready1})
         1'd1: begin
-            litedramcore_interface_wdata <= user_port_wdata_payload_data;
+            main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data;
         end
         default: begin
-            litedramcore_interface_wdata <= 1'd0;
+            main_litedramcore_interface_wdata <= 1'd0;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_interface_wdata_we <= 16'd0;
-    case ({litedramcore_new_master_wdata_ready1})
+    main_litedramcore_interface_wdata_we <= 16'd0;
+    case ({builder_new_master_wdata_ready1})
         1'd1: begin
-            litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
+            main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we;
         end
         default: begin
-            litedramcore_interface_wdata_we <= 1'd0;
+            main_litedramcore_interface_wdata_we <= 1'd0;
         end
     endcase
 end
-assign user_port_rdata_payload_data = litedramcore_interface_rdata;
-assign litedramcore_roundrobin0_grant = 1'd0;
-assign litedramcore_roundrobin1_grant = 1'd0;
-assign litedramcore_roundrobin2_grant = 1'd0;
-assign litedramcore_roundrobin3_grant = 1'd0;
-assign litedramcore_roundrobin4_grant = 1'd0;
-assign litedramcore_roundrobin5_grant = 1'd0;
-assign litedramcore_roundrobin6_grant = 1'd0;
-assign litedramcore_roundrobin7_grant = 1'd0;
-always @(*) begin
-    litedramcore_next_state <= 2'd0;
-    litedramcore_next_state <= litedramcore_state;
-    case (litedramcore_state)
+assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata;
+assign builder_roundrobin0_grant = 1'd0;
+assign builder_roundrobin1_grant = 1'd0;
+assign builder_roundrobin2_grant = 1'd0;
+assign builder_roundrobin3_grant = 1'd0;
+assign builder_roundrobin4_grant = 1'd0;
+assign builder_roundrobin5_grant = 1'd0;
+assign builder_roundrobin6_grant = 1'd0;
+assign builder_roundrobin7_grant = 1'd0;
+always @(*) begin
+    builder_next_state <= 2'd0;
+    builder_next_state <= builder_state;
+    case (builder_state)
         1'd1: begin
-            litedramcore_next_state <= 2'd2;
+            builder_next_state <= 2'd2;
         end
         2'd2: begin
-            litedramcore_next_state <= 1'd0;
+            builder_next_state <= 1'd0;
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_next_state <= 1'd1;
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_next_state <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_dat_w_next_value0 <= 32'd0;
-    case (litedramcore_state)
+    builder_interface0_dat_r <= 32'd0;
+    case (builder_state)
         1'd1: begin
         end
         2'd2: begin
+            builder_interface0_dat_r <= builder_interface1_dat_r;
         end
         default: begin
-            litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_dat_w_next_value_ce0 <= 1'd0;
-    case (litedramcore_state)
+    builder_interface1_dat_w_next_value0 <= 32'd0;
+    case (builder_state)
         1'd1: begin
         end
         2'd2: begin
         end
         default: begin
-            litedramcore_dat_w_next_value_ce0 <= 1'd1;
+            builder_interface1_dat_w_next_value0 <= builder_interface0_dat_w;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_adr_next_value1 <= 14'd0;
-    case (litedramcore_state)
+    builder_interface1_dat_w_next_value_ce0 <= 1'd0;
+    case (builder_state)
         1'd1: begin
-            litedramcore_adr_next_value1 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
-            end
+            builder_interface1_dat_w_next_value_ce0 <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_adr_next_value_ce1 <= 1'd0;
-    case (litedramcore_state)
+    builder_interface1_adr_next_value1 <= 14'd0;
+    case (builder_state)
         1'd1: begin
-            litedramcore_adr_next_value_ce1 <= 1'd1;
+            builder_interface1_adr_next_value1 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_adr_next_value_ce1 <= 1'd1;
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_adr_next_value1 <= builder_interface0_adr[29:0];
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_wishbone_dat_r <= 32'd0;
-    case (litedramcore_state)
+    builder_interface0_ack <= 1'd0;
+    case (builder_state)
         1'd1: begin
         end
         2'd2: begin
-            litedramcore_wishbone_dat_r <= litedramcore_dat_r;
+            builder_interface0_ack <= 1'd1;
         end
         default: begin
         end
     endcase
 end
 always @(*) begin
-    litedramcore_we_next_value2 <= 1'd0;
-    case (litedramcore_state)
+    builder_interface1_adr_next_value_ce1 <= 1'd0;
+    case (builder_state)
         1'd1: begin
-            litedramcore_we_next_value2 <= 1'd0;
+            builder_interface1_adr_next_value_ce1 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_adr_next_value_ce1 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_we_next_value_ce2 <= 1'd0;
-    case (litedramcore_state)
+    builder_interface1_we_next_value2 <= 1'd0;
+    case (builder_state)
         1'd1: begin
-            litedramcore_we_next_value_ce2 <= 1'd1;
+            builder_interface1_we_next_value2 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_we_next_value_ce2 <= 1'd1;
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_we_next_value2 <= (builder_interface0_we & (builder_interface0_sel != 1'd0));
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_wishbone_ack <= 1'd0;
-    case (litedramcore_state)
+    builder_interface1_we_next_value_ce2 <= 1'd0;
+    case (builder_state)
         1'd1: begin
+            builder_interface1_we_next_value_ce2 <= 1'd1;
         end
         2'd2: begin
-            litedramcore_wishbone_ack <= 1'd1;
         end
         default: begin
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_we_next_value_ce2 <= 1'd1;
+            end
         end
     endcase
 end
-assign litedramcore_wishbone_adr = wb_bus_adr;
-assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
-assign wb_bus_dat_r = litedramcore_wishbone_dat_r;
-assign litedramcore_wishbone_sel = wb_bus_sel;
-assign litedramcore_wishbone_cyc = wb_bus_cyc;
-assign litedramcore_wishbone_stb = wb_bus_stb;
-assign wb_bus_ack = litedramcore_wishbone_ack;
-assign litedramcore_wishbone_we = wb_bus_we;
-assign litedramcore_wishbone_cti = wb_bus_cti;
-assign litedramcore_wishbone_bte = wb_bus_bte;
-assign wb_bus_err = litedramcore_wishbone_err;
-assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
-assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
+assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0);
+assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank0_init_done0_re <= 1'd0;
-    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank0_init_done0_re <= interface0_bank_bus_we;
+    builder_csrbank0_init_done0_we <= 1'd0;
+    if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank0_init_done0_we <= 1'd0;
-    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank0_init_done0_we <= (~interface0_bank_bus_we);
+    builder_csrbank0_init_done0_re <= 1'd0;
+    if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
     end
 end
-assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
+assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank0_init_error0_we <= 1'd0;
-    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank0_init_error0_we <= (~interface0_bank_bus_we);
+    builder_csrbank0_init_error0_re <= 1'd0;
+    if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank0_init_error0_re <= 1'd0;
-    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank0_init_error0_re <= interface0_bank_bus_we;
+    builder_csrbank0_init_error0_we <= 1'd0;
+    if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
     end
 end
-assign csrbank0_init_done0_w = init_done_storage;
-assign csrbank0_init_error0_w = init_error_storage;
-assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
-assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0];
+assign builder_csrbank0_init_done0_w = main_init_done_storage;
+assign builder_csrbank0_init_error0_w = main_init_error_storage;
+assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
+assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank1_rst0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank1_rst0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_rst0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_rst0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank1_rst0_re <= interface1_bank_bus_we;
+    builder_csrbank1_rst0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
+assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    csrbank1_dly_sel0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_dly_sel0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank1_dly_sel0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank1_dly_sel0_re <= interface1_bank_bus_we;
+    builder_csrbank1_dly_sel0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
     end
 end
-assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
+assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0];
 always @(*) begin
-    csrbank1_half_sys8x_taps0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we;
+    builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
+        builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_half_sys8x_taps0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
+        builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0];
+assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank1_wlevel_en0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_wlevel_en0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
+        builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_wlevel_en0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank1_wlevel_en0_re <= interface1_bank_bus_we;
+    builder_csrbank1_wlevel_en0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
+        builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_wlevel_strobe_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
-        a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we;
+    main_a7ddrphy_wlevel_strobe_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
+        main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    a7ddrphy_wlevel_strobe_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
-        a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_wlevel_strobe_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
+        main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_rdly_dq_rst_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
+    main_a7ddrphy_rdly_dq_rst_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
+        main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    a7ddrphy_rdly_dq_rst_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_rdly_dq_rst_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
+        main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_rdly_dq_inc_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
+    main_a7ddrphy_rdly_dq_inc_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
+        main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    a7ddrphy_rdly_dq_inc_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_rdly_dq_inc_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
+        main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
-        a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
+        main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
-        a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
+    main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
+        main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
     end
 end
-assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
-        a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
+        main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
-        a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we;
+    main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
+        main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
     end
 end
-assign a7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
-        a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
+        main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
-        a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
+    main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
+        main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
     end
 end
-assign a7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
-        a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
+        main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
-        a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we;
+    main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
+        main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
     end
 end
-assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0];
+assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    csrbank1_rdphase0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
-        csrbank1_rdphase0_re <= interface1_bank_bus_we;
+    builder_csrbank1_rdphase0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
+        builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank1_rdphase0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
-        csrbank1_rdphase0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_rdphase0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
+        builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
     end
 end
-assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0];
+assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    csrbank1_wrphase0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
-        csrbank1_wrphase0_re <= interface1_bank_bus_we;
+    builder_csrbank1_wrphase0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
+        builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_wrphase0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
-        csrbank1_wrphase0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_wrphase0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
+        builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign csrbank1_rst0_w = a7ddrphy_rst_storage;
-assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0];
-assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0];
-assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage;
-assign csrbank1_rdphase0_w = a7ddrphy_rdphase_storage[1:0];
-assign csrbank1_wrphase0_w = a7ddrphy_wrphase_storage[1:0];
-assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2);
-assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
+assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage;
+assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0];
+assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0];
+assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage;
+assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0];
+assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0];
+assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
+assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
 always @(*) begin
-    csrbank2_dfii_control0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank2_dfii_control0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_control0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_control0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_control0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
+assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi0_command0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_command0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_command0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
+assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    litedramcore_phaseinjector0_command_issue_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
-        litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
+    main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
+        main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    litedramcore_phaseinjector0_command_issue_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
-        litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
+    main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
+        main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0];
+assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-    csrbank2_dfii_pi0_address0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
+        builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_address0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_address0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
+        builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank2_dfii_pi0_baddress0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
-        csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
+        builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_baddress0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
-        csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
+        builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
-        csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
+        builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
-        csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
+        builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi0_rddata_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
-        csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_rddata_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
+        builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_rddata_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
-        csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_rddata_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
+        builder_csrbank2_dfii_pi0_rddata_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
+assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi1_command0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
-        csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
+        builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_command0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
-        csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_command0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
+        builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
+assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    litedramcore_phaseinjector1_command_issue_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
-        litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
+    main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
+        main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    litedramcore_phaseinjector1_command_issue_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
-        litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we;
+    main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
+        main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0];
+assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-    csrbank2_dfii_pi1_address0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
-        csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_address0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
+        builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_address0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
-        csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
+        builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank2_dfii_pi1_baddress0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
-        csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
+        builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_baddress0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
-        csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
+        builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
-        csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
+        builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
-        csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
+        builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi1_rddata_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
-        csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_rddata_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
+        builder_csrbank2_dfii_pi1_rddata_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_rddata_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
-        csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_rddata_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
+        builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0];
+assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi2_command0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
-        csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_command0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
+        builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_command0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
-        csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_command0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
+        builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0];
+assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    litedramcore_phaseinjector2_command_issue_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
-        litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we;
+    main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
+        main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    litedramcore_phaseinjector2_command_issue_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
-        litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we);
+    main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
+        main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[14:0];
+assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-    csrbank2_dfii_pi2_address0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
-        csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_address0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
+        builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_address0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
-        csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
+        builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank2_dfii_pi2_baddress0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
-        csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
+        builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_baddress0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
-        csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
+        builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
-        csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+        builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
-        csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+        builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi2_rddata_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
-        csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_rddata_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+        builder_csrbank2_dfii_pi2_rddata_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_rddata_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
-        csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_rddata_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+        builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0];
+assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi3_command0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
-        csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_command0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
+        builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_command0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
-        csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
+        builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0];
+assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    litedramcore_phaseinjector3_command_issue_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
-        litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we);
+    main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
+        main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    litedramcore_phaseinjector3_command_issue_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
-        litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we;
+    main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
+        main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[14:0];
+assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-    csrbank2_dfii_pi3_address0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
-        csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
+        builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_address0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
-        csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_address0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
+        builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank2_dfii_pi3_baddress0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
-        csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+        builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_baddress0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
-        csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+        builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
-        csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
+        builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
-        csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
+        builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi3_rddata_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
-        csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_rddata_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
+        builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_rddata_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
-        csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_rddata_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
+        builder_csrbank2_dfii_pi3_rddata_re <= builder_interface2_bank_bus_we;
     end
 end
-assign litedramcore_sel = litedramcore_storage[0];
-assign litedramcore_cke = litedramcore_storage[1];
-assign litedramcore_odt = litedramcore_storage[2];
-assign litedramcore_reset_n = litedramcore_storage[3];
-assign csrbank2_dfii_control0_w = litedramcore_storage[3:0];
-assign litedramcore_phaseinjector0_csrfield_cs = litedramcore_phaseinjector0_command_storage[0];
-assign litedramcore_phaseinjector0_csrfield_we = litedramcore_phaseinjector0_command_storage[1];
-assign litedramcore_phaseinjector0_csrfield_cas = litedramcore_phaseinjector0_command_storage[2];
-assign litedramcore_phaseinjector0_csrfield_ras = litedramcore_phaseinjector0_command_storage[3];
-assign litedramcore_phaseinjector0_csrfield_wren = litedramcore_phaseinjector0_command_storage[4];
-assign litedramcore_phaseinjector0_csrfield_rden = litedramcore_phaseinjector0_command_storage[5];
-assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
-assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0];
-assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
-assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
-assign csrbank2_dfii_pi0_rddata_w = litedramcore_phaseinjector0_rddata_status[31:0];
-assign litedramcore_phaseinjector0_rddata_we = csrbank2_dfii_pi0_rddata_we;
-assign litedramcore_phaseinjector1_csrfield_cs = litedramcore_phaseinjector1_command_storage[0];
-assign litedramcore_phaseinjector1_csrfield_we = litedramcore_phaseinjector1_command_storage[1];
-assign litedramcore_phaseinjector1_csrfield_cas = litedramcore_phaseinjector1_command_storage[2];
-assign litedramcore_phaseinjector1_csrfield_ras = litedramcore_phaseinjector1_command_storage[3];
-assign litedramcore_phaseinjector1_csrfield_wren = litedramcore_phaseinjector1_command_storage[4];
-assign litedramcore_phaseinjector1_csrfield_rden = litedramcore_phaseinjector1_command_storage[5];
-assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
-assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[14:0];
-assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
-assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
-assign csrbank2_dfii_pi1_rddata_w = litedramcore_phaseinjector1_rddata_status[31:0];
-assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata_we;
-assign litedramcore_phaseinjector2_csrfield_cs = litedramcore_phaseinjector2_command_storage[0];
-assign litedramcore_phaseinjector2_csrfield_we = litedramcore_phaseinjector2_command_storage[1];
-assign litedramcore_phaseinjector2_csrfield_cas = litedramcore_phaseinjector2_command_storage[2];
-assign litedramcore_phaseinjector2_csrfield_ras = litedramcore_phaseinjector2_command_storage[3];
-assign litedramcore_phaseinjector2_csrfield_wren = litedramcore_phaseinjector2_command_storage[4];
-assign litedramcore_phaseinjector2_csrfield_rden = litedramcore_phaseinjector2_command_storage[5];
-assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
-assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[14:0];
-assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
-assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0];
-assign csrbank2_dfii_pi2_rddata_w = litedramcore_phaseinjector2_rddata_status[31:0];
-assign litedramcore_phaseinjector2_rddata_we = csrbank2_dfii_pi2_rddata_we;
-assign litedramcore_phaseinjector3_csrfield_cs = litedramcore_phaseinjector3_command_storage[0];
-assign litedramcore_phaseinjector3_csrfield_we = litedramcore_phaseinjector3_command_storage[1];
-assign litedramcore_phaseinjector3_csrfield_cas = litedramcore_phaseinjector3_command_storage[2];
-assign litedramcore_phaseinjector3_csrfield_ras = litedramcore_phaseinjector3_command_storage[3];
-assign litedramcore_phaseinjector3_csrfield_wren = litedramcore_phaseinjector3_command_storage[4];
-assign litedramcore_phaseinjector3_csrfield_rden = litedramcore_phaseinjector3_command_storage[5];
-assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
-assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[14:0];
-assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
-assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0];
-assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_rddata_status[31:0];
-assign litedramcore_phaseinjector3_rddata_we = csrbank2_dfii_pi3_rddata_we;
-assign csr_interconnect_adr = litedramcore_adr;
-assign csr_interconnect_we = litedramcore_we;
-assign csr_interconnect_dat_w = litedramcore_dat_w;
-assign litedramcore_dat_r = csr_interconnect_dat_r;
-assign interface0_bank_bus_adr = csr_interconnect_adr;
-assign interface1_bank_bus_adr = csr_interconnect_adr;
-assign interface2_bank_bus_adr = csr_interconnect_adr;
-assign interface0_bank_bus_we = csr_interconnect_we;
-assign interface1_bank_bus_we = csr_interconnect_we;
-assign interface2_bank_bus_we = csr_interconnect_we;
-assign interface0_bank_bus_dat_w = csr_interconnect_dat_w;
-assign interface1_bank_bus_dat_w = csr_interconnect_dat_w;
-assign interface2_bank_bus_dat_w = csr_interconnect_dat_w;
-assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
-always @(*) begin
-    rhs_array_muxed0 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+assign main_litedramcore_sel = main_litedramcore_storage[0];
+assign main_litedramcore_cke = main_litedramcore_storage[1];
+assign main_litedramcore_odt = main_litedramcore_storage[2];
+assign main_litedramcore_reset_n = main_litedramcore_storage[3];
+assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0];
+assign main_litedramcore_phaseinjector0_csrfield_cs = main_litedramcore_phaseinjector0_command_storage[0];
+assign main_litedramcore_phaseinjector0_csrfield_we = main_litedramcore_phaseinjector0_command_storage[1];
+assign main_litedramcore_phaseinjector0_csrfield_cas = main_litedramcore_phaseinjector0_command_storage[2];
+assign main_litedramcore_phaseinjector0_csrfield_ras = main_litedramcore_phaseinjector0_command_storage[3];
+assign main_litedramcore_phaseinjector0_csrfield_wren = main_litedramcore_phaseinjector0_command_storage[4];
+assign main_litedramcore_phaseinjector0_csrfield_rden = main_litedramcore_phaseinjector0_command_storage[5];
+assign main_litedramcore_phaseinjector0_csrfield_cs_top = main_litedramcore_phaseinjector0_command_storage[6];
+assign main_litedramcore_phaseinjector0_csrfield_cs_bottom = main_litedramcore_phaseinjector0_command_storage[7];
+assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[7:0];
+assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[14:0];
+assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0];
+assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we;
+assign main_litedramcore_phaseinjector1_csrfield_cs = main_litedramcore_phaseinjector1_command_storage[0];
+assign main_litedramcore_phaseinjector1_csrfield_we = main_litedramcore_phaseinjector1_command_storage[1];
+assign main_litedramcore_phaseinjector1_csrfield_cas = main_litedramcore_phaseinjector1_command_storage[2];
+assign main_litedramcore_phaseinjector1_csrfield_ras = main_litedramcore_phaseinjector1_command_storage[3];
+assign main_litedramcore_phaseinjector1_csrfield_wren = main_litedramcore_phaseinjector1_command_storage[4];
+assign main_litedramcore_phaseinjector1_csrfield_rden = main_litedramcore_phaseinjector1_command_storage[5];
+assign main_litedramcore_phaseinjector1_csrfield_cs_top = main_litedramcore_phaseinjector1_command_storage[6];
+assign main_litedramcore_phaseinjector1_csrfield_cs_bottom = main_litedramcore_phaseinjector1_command_storage[7];
+assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[7:0];
+assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[14:0];
+assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0];
+assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we;
+assign main_litedramcore_phaseinjector2_csrfield_cs = main_litedramcore_phaseinjector2_command_storage[0];
+assign main_litedramcore_phaseinjector2_csrfield_we = main_litedramcore_phaseinjector2_command_storage[1];
+assign main_litedramcore_phaseinjector2_csrfield_cas = main_litedramcore_phaseinjector2_command_storage[2];
+assign main_litedramcore_phaseinjector2_csrfield_ras = main_litedramcore_phaseinjector2_command_storage[3];
+assign main_litedramcore_phaseinjector2_csrfield_wren = main_litedramcore_phaseinjector2_command_storage[4];
+assign main_litedramcore_phaseinjector2_csrfield_rden = main_litedramcore_phaseinjector2_command_storage[5];
+assign main_litedramcore_phaseinjector2_csrfield_cs_top = main_litedramcore_phaseinjector2_command_storage[6];
+assign main_litedramcore_phaseinjector2_csrfield_cs_bottom = main_litedramcore_phaseinjector2_command_storage[7];
+assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[7:0];
+assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[14:0];
+assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0];
+assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we;
+assign main_litedramcore_phaseinjector3_csrfield_cs = main_litedramcore_phaseinjector3_command_storage[0];
+assign main_litedramcore_phaseinjector3_csrfield_we = main_litedramcore_phaseinjector3_command_storage[1];
+assign main_litedramcore_phaseinjector3_csrfield_cas = main_litedramcore_phaseinjector3_command_storage[2];
+assign main_litedramcore_phaseinjector3_csrfield_ras = main_litedramcore_phaseinjector3_command_storage[3];
+assign main_litedramcore_phaseinjector3_csrfield_wren = main_litedramcore_phaseinjector3_command_storage[4];
+assign main_litedramcore_phaseinjector3_csrfield_rden = main_litedramcore_phaseinjector3_command_storage[5];
+assign main_litedramcore_phaseinjector3_csrfield_cs_top = main_litedramcore_phaseinjector3_command_storage[6];
+assign main_litedramcore_phaseinjector3_csrfield_cs_bottom = main_litedramcore_phaseinjector3_command_storage[7];
+assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[7:0];
+assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[14:0];
+assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0];
+assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we;
+assign builder_adr = builder_interface1_adr;
+assign builder_we = builder_interface1_we;
+assign builder_dat_w = builder_interface1_dat_w;
+assign builder_interface1_dat_r = builder_dat_r;
+assign builder_interface0_bank_bus_adr = builder_adr;
+assign builder_interface1_bank_bus_adr = builder_adr;
+assign builder_interface2_bank_bus_adr = builder_adr;
+assign builder_interface0_bank_bus_we = builder_we;
+assign builder_interface1_bank_bus_we = builder_we;
+assign builder_interface2_bank_bus_we = builder_we;
+assign builder_interface0_bank_bus_dat_w = builder_dat_w;
+assign builder_interface1_bank_bus_dat_w = builder_dat_w;
+assign builder_interface2_bank_bus_dat_w = builder_dat_w;
+assign builder_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r);
+always @(*) begin
+    builder_rhs_self0 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[0];
         end
         1'd1: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[1];
         end
         2'd2: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[2];
         end
         2'd3: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[3];
         end
         3'd4: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[4];
         end
         3'd5: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[5];
         end
         3'd6: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[6];
         end
         default: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[7];
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed1 <= 15'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_rhs_self1 <= 15'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine0_cmd_payload_a;
         end
         1'd1: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine1_cmd_payload_a;
         end
         2'd2: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine2_cmd_payload_a;
         end
         2'd3: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine3_cmd_payload_a;
         end
         3'd4: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine4_cmd_payload_a;
         end
         3'd5: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine5_cmd_payload_a;
         end
         3'd6: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine6_cmd_payload_a;
         end
         default: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine7_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed2 <= 3'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_rhs_self2 <= 3'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine0_cmd_payload_ba;
         end
         1'd1: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine1_cmd_payload_ba;
         end
         2'd2: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine2_cmd_payload_ba;
         end
         2'd3: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine3_cmd_payload_ba;
         end
         3'd4: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine4_cmd_payload_ba;
         end
         3'd5: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine5_cmd_payload_ba;
         end
         3'd6: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine6_cmd_payload_ba;
         end
         default: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine7_cmd_payload_ba;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed3 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_rhs_self3 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine0_cmd_payload_is_read;
         end
         1'd1: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine1_cmd_payload_is_read;
         end
         2'd2: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine2_cmd_payload_is_read;
         end
         2'd3: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine3_cmd_payload_is_read;
         end
         3'd4: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine4_cmd_payload_is_read;
         end
         3'd5: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine5_cmd_payload_is_read;
         end
         3'd6: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine6_cmd_payload_is_read;
         end
         default: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed4 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_rhs_self4 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine0_cmd_payload_is_write;
         end
         1'd1: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine1_cmd_payload_is_write;
         end
         2'd2: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine2_cmd_payload_is_write;
         end
         2'd3: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine3_cmd_payload_is_write;
         end
         3'd4: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine4_cmd_payload_is_write;
         end
         3'd5: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine5_cmd_payload_is_write;
         end
         3'd6: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine6_cmd_payload_is_write;
         end
         default: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed5 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_rhs_self5 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd;
         end
         1'd1: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd;
         end
         2'd2: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd;
         end
         2'd3: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd;
         end
         3'd4: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd;
         end
         3'd5: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd;
         end
         3'd6: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd;
         end
         default: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed0 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_t_self0 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine0_cmd_payload_cas;
         end
         1'd1: begin
-            t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine1_cmd_payload_cas;
         end
         2'd2: begin
-            t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine2_cmd_payload_cas;
         end
         2'd3: begin
-            t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine3_cmd_payload_cas;
         end
         3'd4: begin
-            t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine4_cmd_payload_cas;
         end
         3'd5: begin
-            t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine5_cmd_payload_cas;
         end
         3'd6: begin
-            t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine6_cmd_payload_cas;
         end
         default: begin
-            t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine7_cmd_payload_cas;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed1 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_t_self1 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine0_cmd_payload_ras;
         end
         1'd1: begin
-            t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine1_cmd_payload_ras;
         end
         2'd2: begin
-            t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine2_cmd_payload_ras;
         end
         2'd3: begin
-            t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine3_cmd_payload_ras;
         end
         3'd4: begin
-            t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine4_cmd_payload_ras;
         end
         3'd5: begin
-            t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine5_cmd_payload_ras;
         end
         3'd6: begin
-            t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine6_cmd_payload_ras;
         end
         default: begin
-            t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine7_cmd_payload_ras;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed2 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_t_self2 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine0_cmd_payload_we;
         end
         1'd1: begin
-            t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine1_cmd_payload_we;
         end
         2'd2: begin
-            t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine2_cmd_payload_we;
         end
         2'd3: begin
-            t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine3_cmd_payload_we;
         end
         3'd4: begin
-            t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine4_cmd_payload_we;
         end
         3'd5: begin
-            t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine5_cmd_payload_we;
         end
         3'd6: begin
-            t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine6_cmd_payload_we;
         end
         default: begin
-            t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine7_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed6 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self6 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[0];
         end
         1'd1: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[1];
         end
         2'd2: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[2];
         end
         2'd3: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[3];
         end
         3'd4: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[4];
         end
         3'd5: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[5];
         end
         3'd6: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[6];
         end
         default: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[7];
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed7 <= 15'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self7 <= 15'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine0_cmd_payload_a;
         end
         1'd1: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine1_cmd_payload_a;
         end
         2'd2: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine2_cmd_payload_a;
         end
         2'd3: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine3_cmd_payload_a;
         end
         3'd4: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine4_cmd_payload_a;
         end
         3'd5: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine5_cmd_payload_a;
         end
         3'd6: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine6_cmd_payload_a;
         end
         default: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine7_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed8 <= 3'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self8 <= 3'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine0_cmd_payload_ba;
         end
         1'd1: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine1_cmd_payload_ba;
         end
         2'd2: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine2_cmd_payload_ba;
         end
         2'd3: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine3_cmd_payload_ba;
         end
         3'd4: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine4_cmd_payload_ba;
         end
         3'd5: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine5_cmd_payload_ba;
         end
         3'd6: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine6_cmd_payload_ba;
         end
         default: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine7_cmd_payload_ba;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed9 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self9 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine0_cmd_payload_is_read;
         end
         1'd1: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine1_cmd_payload_is_read;
         end
         2'd2: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine2_cmd_payload_is_read;
         end
         2'd3: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine3_cmd_payload_is_read;
         end
         3'd4: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine4_cmd_payload_is_read;
         end
         3'd5: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine5_cmd_payload_is_read;
         end
         3'd6: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine6_cmd_payload_is_read;
         end
         default: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed10 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self10 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine0_cmd_payload_is_write;
         end
         1'd1: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine1_cmd_payload_is_write;
         end
         2'd2: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine2_cmd_payload_is_write;
         end
         2'd3: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine3_cmd_payload_is_write;
         end
         3'd4: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine4_cmd_payload_is_write;
         end
         3'd5: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine5_cmd_payload_is_write;
         end
         3'd6: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine6_cmd_payload_is_write;
         end
         default: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed11 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self11 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd;
         end
         1'd1: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd;
         end
         2'd2: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd;
         end
         2'd3: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd;
         end
         3'd4: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd;
         end
         3'd5: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd;
         end
         3'd6: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd;
         end
         default: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed3 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_t_self3 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine0_cmd_payload_cas;
         end
         1'd1: begin
-            t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine1_cmd_payload_cas;
         end
         2'd2: begin
-            t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine2_cmd_payload_cas;
         end
         2'd3: begin
-            t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine3_cmd_payload_cas;
         end
         3'd4: begin
-            t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine4_cmd_payload_cas;
         end
         3'd5: begin
-            t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine5_cmd_payload_cas;
         end
         3'd6: begin
-            t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine6_cmd_payload_cas;
         end
         default: begin
-            t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine7_cmd_payload_cas;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed4 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_t_self4 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine0_cmd_payload_ras;
         end
         1'd1: begin
-            t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine1_cmd_payload_ras;
         end
         2'd2: begin
-            t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine2_cmd_payload_ras;
         end
         2'd3: begin
-            t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine3_cmd_payload_ras;
         end
         3'd4: begin
-            t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine4_cmd_payload_ras;
         end
         3'd5: begin
-            t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine5_cmd_payload_ras;
         end
         3'd6: begin
-            t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine6_cmd_payload_ras;
         end
         default: begin
-            t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine7_cmd_payload_ras;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed5 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_t_self5 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine0_cmd_payload_we;
         end
         1'd1: begin
-            t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine1_cmd_payload_we;
         end
         2'd2: begin
-            t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine2_cmd_payload_we;
         end
         2'd3: begin
-            t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine3_cmd_payload_we;
         end
         3'd4: begin
-            t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine4_cmd_payload_we;
         end
         3'd5: begin
-            t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine5_cmd_payload_we;
         end
         3'd6: begin
-            t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine6_cmd_payload_we;
         end
         default: begin
-            t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine7_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed12 <= 22'd0;
-    case (litedramcore_roundrobin0_grant)
+    builder_rhs_self12 <= 22'd0;
+    case (builder_roundrobin0_grant)
         default: begin
-            rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self12 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed13 <= 1'd0;
-    case (litedramcore_roundrobin0_grant)
+    builder_rhs_self13 <= 1'd0;
+    case (builder_roundrobin0_grant)
         default: begin
-            rhs_array_muxed13 <= user_port_cmd_payload_we;
+            builder_rhs_self13 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed14 <= 1'd0;
-    case (litedramcore_roundrobin0_grant)
+    builder_rhs_self14 <= 1'd0;
+    case (builder_roundrobin0_grant)
         default: begin
-            rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed15 <= 22'd0;
-    case (litedramcore_roundrobin1_grant)
+    builder_rhs_self15 <= 22'd0;
+    case (builder_roundrobin1_grant)
         default: begin
-            rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self15 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed16 <= 1'd0;
-    case (litedramcore_roundrobin1_grant)
+    builder_rhs_self16 <= 1'd0;
+    case (builder_roundrobin1_grant)
         default: begin
-            rhs_array_muxed16 <= user_port_cmd_payload_we;
+            builder_rhs_self16 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed17 <= 1'd0;
-    case (litedramcore_roundrobin1_grant)
+    builder_rhs_self17 <= 1'd0;
+    case (builder_roundrobin1_grant)
         default: begin
-            rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed18 <= 22'd0;
-    case (litedramcore_roundrobin2_grant)
+    builder_rhs_self18 <= 22'd0;
+    case (builder_roundrobin2_grant)
         default: begin
-            rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self18 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed19 <= 1'd0;
-    case (litedramcore_roundrobin2_grant)
+    builder_rhs_self19 <= 1'd0;
+    case (builder_roundrobin2_grant)
         default: begin
-            rhs_array_muxed19 <= user_port_cmd_payload_we;
+            builder_rhs_self19 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed20 <= 1'd0;
-    case (litedramcore_roundrobin2_grant)
+    builder_rhs_self20 <= 1'd0;
+    case (builder_roundrobin2_grant)
         default: begin
-            rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed21 <= 22'd0;
-    case (litedramcore_roundrobin3_grant)
+    builder_rhs_self21 <= 22'd0;
+    case (builder_roundrobin3_grant)
         default: begin
-            rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self21 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed22 <= 1'd0;
-    case (litedramcore_roundrobin3_grant)
+    builder_rhs_self22 <= 1'd0;
+    case (builder_roundrobin3_grant)
         default: begin
-            rhs_array_muxed22 <= user_port_cmd_payload_we;
+            builder_rhs_self22 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed23 <= 1'd0;
-    case (litedramcore_roundrobin3_grant)
+    builder_rhs_self23 <= 1'd0;
+    case (builder_roundrobin3_grant)
         default: begin
-            rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed24 <= 22'd0;
-    case (litedramcore_roundrobin4_grant)
+    builder_rhs_self24 <= 22'd0;
+    case (builder_roundrobin4_grant)
         default: begin
-            rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self24 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed25 <= 1'd0;
-    case (litedramcore_roundrobin4_grant)
+    builder_rhs_self25 <= 1'd0;
+    case (builder_roundrobin4_grant)
         default: begin
-            rhs_array_muxed25 <= user_port_cmd_payload_we;
+            builder_rhs_self25 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed26 <= 1'd0;
-    case (litedramcore_roundrobin4_grant)
+    builder_rhs_self26 <= 1'd0;
+    case (builder_roundrobin4_grant)
         default: begin
-            rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed27 <= 22'd0;
-    case (litedramcore_roundrobin5_grant)
+    builder_rhs_self27 <= 22'd0;
+    case (builder_roundrobin5_grant)
         default: begin
-            rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self27 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed28 <= 1'd0;
-    case (litedramcore_roundrobin5_grant)
+    builder_rhs_self28 <= 1'd0;
+    case (builder_roundrobin5_grant)
         default: begin
-            rhs_array_muxed28 <= user_port_cmd_payload_we;
+            builder_rhs_self28 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed29 <= 1'd0;
-    case (litedramcore_roundrobin5_grant)
+    builder_rhs_self29 <= 1'd0;
+    case (builder_roundrobin5_grant)
         default: begin
-            rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed30 <= 22'd0;
-    case (litedramcore_roundrobin6_grant)
+    builder_rhs_self30 <= 22'd0;
+    case (builder_roundrobin6_grant)
         default: begin
-            rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self30 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed31 <= 1'd0;
-    case (litedramcore_roundrobin6_grant)
+    builder_rhs_self31 <= 1'd0;
+    case (builder_roundrobin6_grant)
         default: begin
-            rhs_array_muxed31 <= user_port_cmd_payload_we;
+            builder_rhs_self31 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed32 <= 1'd0;
-    case (litedramcore_roundrobin6_grant)
+    builder_rhs_self32 <= 1'd0;
+    case (builder_roundrobin6_grant)
         default: begin
-            rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed33 <= 22'd0;
-    case (litedramcore_roundrobin7_grant)
+    builder_rhs_self33 <= 22'd0;
+    case (builder_roundrobin7_grant)
         default: begin
-            rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self33 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed34 <= 1'd0;
-    case (litedramcore_roundrobin7_grant)
+    builder_rhs_self34 <= 1'd0;
+    case (builder_roundrobin7_grant)
         default: begin
-            rhs_array_muxed34 <= user_port_cmd_payload_we;
+            builder_rhs_self34 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed35 <= 1'd0;
-    case (litedramcore_roundrobin7_grant)
+    builder_rhs_self35 <= 1'd0;
+    case (builder_roundrobin7_grant)
         default: begin
-            rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    array_muxed0 <= 3'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self0 <= 3'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed0 <= litedramcore_nop_ba[2:0];
+            builder_self0 <= main_litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed1 <= 15'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self1 <= 15'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed1 <= litedramcore_nop_a;
+            builder_self1 <= main_litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
+            builder_self1 <= main_litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
+            builder_self1 <= main_litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed1 <= litedramcore_cmd_payload_a;
+            builder_self1 <= main_litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed2 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self2 <= 1'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed2 <= 1'd0;
+            builder_self2 <= 1'd0;
         end
         1'd1: begin
-            array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+            builder_self2 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+            builder_self2 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+            builder_self2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed3 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self3 <= 1'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed3 <= 1'd0;
+            builder_self3 <= 1'd0;
         end
         1'd1: begin
-            array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+            builder_self3 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+            builder_self3 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+            builder_self3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed4 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self4 <= 1'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed4 <= 1'd0;
+            builder_self4 <= 1'd0;
         end
         1'd1: begin
-            array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+            builder_self4 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+            builder_self4 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+            builder_self4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed5 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self5 <= 1'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed5 <= 1'd0;
+            builder_self5 <= 1'd0;
         end
         1'd1: begin
-            array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+            builder_self5 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+            builder_self5 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+            builder_self5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed6 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self6 <= 1'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed6 <= 1'd0;
+            builder_self6 <= 1'd0;
         end
         1'd1: begin
-            array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+            builder_self6 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+            builder_self6 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+            builder_self6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
         end
     endcase
 end
 always @(*) begin
-    array_muxed7 <= 3'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self7 <= 3'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed7 <= litedramcore_nop_ba[2:0];
+            builder_self7 <= main_litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed8 <= 15'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self8 <= 15'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed8 <= litedramcore_nop_a;
+            builder_self8 <= main_litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
+            builder_self8 <= main_litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
+            builder_self8 <= main_litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed8 <= litedramcore_cmd_payload_a;
+            builder_self8 <= main_litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed9 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self9 <= 1'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed9 <= 1'd0;
+            builder_self9 <= 1'd0;
         end
         1'd1: begin
-            array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+            builder_self9 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+            builder_self9 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+            builder_self9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed10 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self10 <= 1'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed10 <= 1'd0;
+            builder_self10 <= 1'd0;
         end
         1'd1: begin
-            array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+            builder_self10 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+            builder_self10 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+            builder_self10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed11 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self11 <= 1'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed11 <= 1'd0;
+            builder_self11 <= 1'd0;
         end
         1'd1: begin
-            array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+            builder_self11 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+            builder_self11 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+            builder_self11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed12 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self12 <= 1'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed12 <= 1'd0;
+            builder_self12 <= 1'd0;
         end
         1'd1: begin
-            array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+            builder_self12 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+            builder_self12 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+            builder_self12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed13 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self13 <= 1'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed13 <= 1'd0;
+            builder_self13 <= 1'd0;
         end
         1'd1: begin
-            array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+            builder_self13 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+            builder_self13 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+            builder_self13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
         end
     endcase
 end
 always @(*) begin
-    array_muxed14 <= 3'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self14 <= 3'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed14 <= litedramcore_nop_ba[2:0];
+            builder_self14 <= main_litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed14 <= litedramcore_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed15 <= 15'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self15 <= 15'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed15 <= litedramcore_nop_a;
+            builder_self15 <= main_litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a;
+            builder_self15 <= main_litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed15 <= litedramcore_choose_req_cmd_payload_a;
+            builder_self15 <= main_litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed15 <= litedramcore_cmd_payload_a;
+            builder_self15 <= main_litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed16 <= 1'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self16 <= 1'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed16 <= 1'd0;
+            builder_self16 <= 1'd0;
         end
         1'd1: begin
-            array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+            builder_self16 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+            builder_self16 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+            builder_self16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed17 <= 1'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self17 <= 1'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed17 <= 1'd0;
+            builder_self17 <= 1'd0;
         end
         1'd1: begin
-            array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+            builder_self17 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+            builder_self17 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+            builder_self17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed18 <= 1'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self18 <= 1'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed18 <= 1'd0;
+            builder_self18 <= 1'd0;
         end
         1'd1: begin
-            array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+            builder_self18 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+            builder_self18 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+            builder_self18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed19 <= 1'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self19 <= 1'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed19 <= 1'd0;
+            builder_self19 <= 1'd0;
         end
         1'd1: begin
-            array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+            builder_self19 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+            builder_self19 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+            builder_self19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed20 <= 1'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self20 <= 1'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed20 <= 1'd0;
+            builder_self20 <= 1'd0;
         end
         1'd1: begin
-            array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+            builder_self20 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+            builder_self20 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+            builder_self20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
         end
     endcase
 end
 always @(*) begin
-    array_muxed21 <= 3'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self21 <= 3'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed21 <= litedramcore_nop_ba[2:0];
+            builder_self21 <= main_litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed21 <= litedramcore_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed22 <= 15'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self22 <= 15'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed22 <= litedramcore_nop_a;
+            builder_self22 <= main_litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a;
+            builder_self22 <= main_litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed22 <= litedramcore_choose_req_cmd_payload_a;
+            builder_self22 <= main_litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed22 <= litedramcore_cmd_payload_a;
+            builder_self22 <= main_litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed23 <= 1'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self23 <= 1'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed23 <= 1'd0;
+            builder_self23 <= 1'd0;
         end
         1'd1: begin
-            array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+            builder_self23 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+            builder_self23 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+            builder_self23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed24 <= 1'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self24 <= 1'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed24 <= 1'd0;
+            builder_self24 <= 1'd0;
         end
         1'd1: begin
-            array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+            builder_self24 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+            builder_self24 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+            builder_self24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed25 <= 1'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self25 <= 1'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed25 <= 1'd0;
+            builder_self25 <= 1'd0;
         end
         1'd1: begin
-            array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+            builder_self25 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+            builder_self25 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+            builder_self25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed26 <= 1'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self26 <= 1'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed26 <= 1'd0;
+            builder_self26 <= 1'd0;
         end
         1'd1: begin
-            array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+            builder_self26 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+            builder_self26 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+            builder_self26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed27 <= 1'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self27 <= 1'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed27 <= 1'd0;
+            builder_self27 <= 1'd0;
         end
         1'd1: begin
-            array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+            builder_self27 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+            builder_self27 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+            builder_self27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
         end
     endcase
 end
-assign xilinxasyncresetsynchronizerimpl0 = (~locked);
-assign xilinxasyncresetsynchronizerimpl1 = (~locked);
-assign xilinxasyncresetsynchronizerimpl2 = (~locked);
-assign xilinxasyncresetsynchronizerimpl3 = (~locked);
+assign builder_xilinxasyncresetsynchronizerimpl0_async_reset = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl1_async_reset = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl2_async_reset = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl3_async_reset = (~main_locked);
 
 
 //------------------------------------------------------------------------------
@@ -11983,1044 +12399,1044 @@ assign xilinxasyncresetsynchronizerimpl3 = (~locked);
 //------------------------------------------------------------------------------
 
 always @(posedge iodelay_clk) begin
-    if ((reset_counter != 1'd0)) begin
-        reset_counter <= (reset_counter - 1'd1);
+    if ((main_reset_counter != 1'd0)) begin
+        main_reset_counter <= (main_reset_counter - 1'd1);
     end else begin
-        ic_reset <= 1'd0;
+        main_ic_reset <= 1'd0;
     end
     if (iodelay_rst) begin
-        reset_counter <= 4'd15;
-        ic_reset <= 1'd1;
+        main_reset_counter <= 4'd15;
+        main_ic_reset <= 1'd1;
     end
 end
 
 always @(posedge sys_clk) begin
-    a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline;
-    a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
-    a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0;
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1);
+    main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline;
+    main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
+    main_a7ddrphy_dqspattern_o1 <= main_a7ddrphy_dqspattern_o0;
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip0_value0 <= (main_a7ddrphy_bitslip0_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip0_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip0_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1);
+    main_a7ddrphy_bitslip0_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip0_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip1_value0 <= (main_a7ddrphy_bitslip1_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip1_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip1_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1);
+    main_a7ddrphy_bitslip1_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip1_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip0_value1 <= (main_a7ddrphy_bitslip0_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip0_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip0_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1);
+    main_a7ddrphy_bitslip0_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[2], main_a7ddrphy_dfi_p3_wrdata_mask[0], main_a7ddrphy_dfi_p2_wrdata_mask[2], main_a7ddrphy_dfi_p2_wrdata_mask[0], main_a7ddrphy_dfi_p1_wrdata_mask[2], main_a7ddrphy_dfi_p1_wrdata_mask[0], main_a7ddrphy_dfi_p0_wrdata_mask[2], main_a7ddrphy_dfi_p0_wrdata_mask[0]}, main_a7ddrphy_bitslip0_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip1_value1 <= (main_a7ddrphy_bitslip1_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip1_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip1_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]};
-    a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline;
-    a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1);
+    main_a7ddrphy_bitslip1_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[3], main_a7ddrphy_dfi_p3_wrdata_mask[1], main_a7ddrphy_dfi_p2_wrdata_mask[3], main_a7ddrphy_dfi_p2_wrdata_mask[1], main_a7ddrphy_dfi_p1_wrdata_mask[3], main_a7ddrphy_dfi_p1_wrdata_mask[1], main_a7ddrphy_dfi_p0_wrdata_mask[3], main_a7ddrphy_dfi_p0_wrdata_mask[1]}, main_a7ddrphy_bitslip1_r1[15:8]};
+    main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dq_oe_delay_tappeddelayline;
+    main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip0_value2 <= (main_a7ddrphy_bitslip0_value2 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip0_value2 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip0_value2 <= 3'd7;
     end
-    a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1);
+    main_a7ddrphy_bitslip0_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[16], main_a7ddrphy_dfi_p3_wrdata[0], main_a7ddrphy_dfi_p2_wrdata[16], main_a7ddrphy_dfi_p2_wrdata[0], main_a7ddrphy_dfi_p1_wrdata[16], main_a7ddrphy_dfi_p1_wrdata[0], main_a7ddrphy_dfi_p0_wrdata[16], main_a7ddrphy_dfi_p0_wrdata[0]}, main_a7ddrphy_bitslip0_r2[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip0_value3 <= (main_a7ddrphy_bitslip0_value3 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip0_value3 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip0_value3 <= 3'd7;
     end
-    a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1);
+    main_a7ddrphy_bitslip0_r3 <= {main_a7ddrphy_bitslip03, main_a7ddrphy_bitslip0_r3[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip1_value2 <= (main_a7ddrphy_bitslip1_value2 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip1_value2 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip1_value2 <= 3'd7;
     end
-    a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1);
+    main_a7ddrphy_bitslip1_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[17], main_a7ddrphy_dfi_p3_wrdata[1], main_a7ddrphy_dfi_p2_wrdata[17], main_a7ddrphy_dfi_p2_wrdata[1], main_a7ddrphy_dfi_p1_wrdata[17], main_a7ddrphy_dfi_p1_wrdata[1], main_a7ddrphy_dfi_p0_wrdata[17], main_a7ddrphy_dfi_p0_wrdata[1]}, main_a7ddrphy_bitslip1_r2[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip1_value3 <= (main_a7ddrphy_bitslip1_value3 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip1_value3 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip1_value3 <= 3'd7;
     end
-    a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1);
+    main_a7ddrphy_bitslip1_r3 <= {main_a7ddrphy_bitslip13, main_a7ddrphy_bitslip1_r3[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip2_value0 <= (main_a7ddrphy_bitslip2_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip2_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip2_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1);
+    main_a7ddrphy_bitslip2_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[18], main_a7ddrphy_dfi_p3_wrdata[2], main_a7ddrphy_dfi_p2_wrdata[18], main_a7ddrphy_dfi_p2_wrdata[2], main_a7ddrphy_dfi_p1_wrdata[18], main_a7ddrphy_dfi_p1_wrdata[2], main_a7ddrphy_dfi_p0_wrdata[18], main_a7ddrphy_dfi_p0_wrdata[2]}, main_a7ddrphy_bitslip2_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip2_value1 <= (main_a7ddrphy_bitslip2_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip2_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip2_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1);
+    main_a7ddrphy_bitslip2_r1 <= {main_a7ddrphy_bitslip21, main_a7ddrphy_bitslip2_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip3_value0 <= (main_a7ddrphy_bitslip3_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip3_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip3_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1);
+    main_a7ddrphy_bitslip3_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[19], main_a7ddrphy_dfi_p3_wrdata[3], main_a7ddrphy_dfi_p2_wrdata[19], main_a7ddrphy_dfi_p2_wrdata[3], main_a7ddrphy_dfi_p1_wrdata[19], main_a7ddrphy_dfi_p1_wrdata[3], main_a7ddrphy_dfi_p0_wrdata[19], main_a7ddrphy_dfi_p0_wrdata[3]}, main_a7ddrphy_bitslip3_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip3_value1 <= (main_a7ddrphy_bitslip3_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip3_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip3_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1);
+    main_a7ddrphy_bitslip3_r1 <= {main_a7ddrphy_bitslip31, main_a7ddrphy_bitslip3_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip4_value0 <= (main_a7ddrphy_bitslip4_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip4_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip4_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1);
+    main_a7ddrphy_bitslip4_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[20], main_a7ddrphy_dfi_p3_wrdata[4], main_a7ddrphy_dfi_p2_wrdata[20], main_a7ddrphy_dfi_p2_wrdata[4], main_a7ddrphy_dfi_p1_wrdata[20], main_a7ddrphy_dfi_p1_wrdata[4], main_a7ddrphy_dfi_p0_wrdata[20], main_a7ddrphy_dfi_p0_wrdata[4]}, main_a7ddrphy_bitslip4_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip4_value1 <= (main_a7ddrphy_bitslip4_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip4_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip4_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1);
+    main_a7ddrphy_bitslip4_r1 <= {main_a7ddrphy_bitslip41, main_a7ddrphy_bitslip4_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip5_value0 <= (main_a7ddrphy_bitslip5_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip5_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip5_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1);
+    main_a7ddrphy_bitslip5_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[21], main_a7ddrphy_dfi_p3_wrdata[5], main_a7ddrphy_dfi_p2_wrdata[21], main_a7ddrphy_dfi_p2_wrdata[5], main_a7ddrphy_dfi_p1_wrdata[21], main_a7ddrphy_dfi_p1_wrdata[5], main_a7ddrphy_dfi_p0_wrdata[21], main_a7ddrphy_dfi_p0_wrdata[5]}, main_a7ddrphy_bitslip5_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip5_value1 <= (main_a7ddrphy_bitslip5_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip5_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip5_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1);
+    main_a7ddrphy_bitslip5_r1 <= {main_a7ddrphy_bitslip51, main_a7ddrphy_bitslip5_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip6_value0 <= (main_a7ddrphy_bitslip6_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip6_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip6_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1);
+    main_a7ddrphy_bitslip6_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[22], main_a7ddrphy_dfi_p3_wrdata[6], main_a7ddrphy_dfi_p2_wrdata[22], main_a7ddrphy_dfi_p2_wrdata[6], main_a7ddrphy_dfi_p1_wrdata[22], main_a7ddrphy_dfi_p1_wrdata[6], main_a7ddrphy_dfi_p0_wrdata[22], main_a7ddrphy_dfi_p0_wrdata[6]}, main_a7ddrphy_bitslip6_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip6_value1 <= (main_a7ddrphy_bitslip6_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip6_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip6_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1);
+    main_a7ddrphy_bitslip6_r1 <= {main_a7ddrphy_bitslip61, main_a7ddrphy_bitslip6_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip7_value0 <= (main_a7ddrphy_bitslip7_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip7_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip7_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1);
+    main_a7ddrphy_bitslip7_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[23], main_a7ddrphy_dfi_p3_wrdata[7], main_a7ddrphy_dfi_p2_wrdata[23], main_a7ddrphy_dfi_p2_wrdata[7], main_a7ddrphy_dfi_p1_wrdata[23], main_a7ddrphy_dfi_p1_wrdata[7], main_a7ddrphy_dfi_p0_wrdata[23], main_a7ddrphy_dfi_p0_wrdata[7]}, main_a7ddrphy_bitslip7_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip7_value1 <= (main_a7ddrphy_bitslip7_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip7_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip7_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1);
+    main_a7ddrphy_bitslip7_r1 <= {main_a7ddrphy_bitslip71, main_a7ddrphy_bitslip7_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip8_value0 <= (main_a7ddrphy_bitslip8_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip8_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip8_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1);
+    main_a7ddrphy_bitslip8_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[24], main_a7ddrphy_dfi_p3_wrdata[8], main_a7ddrphy_dfi_p2_wrdata[24], main_a7ddrphy_dfi_p2_wrdata[8], main_a7ddrphy_dfi_p1_wrdata[24], main_a7ddrphy_dfi_p1_wrdata[8], main_a7ddrphy_dfi_p0_wrdata[24], main_a7ddrphy_dfi_p0_wrdata[8]}, main_a7ddrphy_bitslip8_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip8_value1 <= (main_a7ddrphy_bitslip8_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip8_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip8_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1);
+    main_a7ddrphy_bitslip8_r1 <= {main_a7ddrphy_bitslip81, main_a7ddrphy_bitslip8_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip9_value0 <= (main_a7ddrphy_bitslip9_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip9_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip9_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1);
+    main_a7ddrphy_bitslip9_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[25], main_a7ddrphy_dfi_p3_wrdata[9], main_a7ddrphy_dfi_p2_wrdata[25], main_a7ddrphy_dfi_p2_wrdata[9], main_a7ddrphy_dfi_p1_wrdata[25], main_a7ddrphy_dfi_p1_wrdata[9], main_a7ddrphy_dfi_p0_wrdata[25], main_a7ddrphy_dfi_p0_wrdata[9]}, main_a7ddrphy_bitslip9_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip9_value1 <= (main_a7ddrphy_bitslip9_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip9_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip9_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1);
+    main_a7ddrphy_bitslip9_r1 <= {main_a7ddrphy_bitslip91, main_a7ddrphy_bitslip9_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip10_value0 <= (main_a7ddrphy_bitslip10_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip10_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip10_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1);
+    main_a7ddrphy_bitslip10_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[26], main_a7ddrphy_dfi_p3_wrdata[10], main_a7ddrphy_dfi_p2_wrdata[26], main_a7ddrphy_dfi_p2_wrdata[10], main_a7ddrphy_dfi_p1_wrdata[26], main_a7ddrphy_dfi_p1_wrdata[10], main_a7ddrphy_dfi_p0_wrdata[26], main_a7ddrphy_dfi_p0_wrdata[10]}, main_a7ddrphy_bitslip10_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip10_value1 <= (main_a7ddrphy_bitslip10_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip10_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip10_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1);
+    main_a7ddrphy_bitslip10_r1 <= {main_a7ddrphy_bitslip101, main_a7ddrphy_bitslip10_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip11_value0 <= (main_a7ddrphy_bitslip11_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip11_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip11_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1);
+    main_a7ddrphy_bitslip11_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[27], main_a7ddrphy_dfi_p3_wrdata[11], main_a7ddrphy_dfi_p2_wrdata[27], main_a7ddrphy_dfi_p2_wrdata[11], main_a7ddrphy_dfi_p1_wrdata[27], main_a7ddrphy_dfi_p1_wrdata[11], main_a7ddrphy_dfi_p0_wrdata[27], main_a7ddrphy_dfi_p0_wrdata[11]}, main_a7ddrphy_bitslip11_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip11_value1 <= (main_a7ddrphy_bitslip11_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip11_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip11_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1);
+    main_a7ddrphy_bitslip11_r1 <= {main_a7ddrphy_bitslip111, main_a7ddrphy_bitslip11_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip12_value0 <= (main_a7ddrphy_bitslip12_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip12_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip12_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1);
+    main_a7ddrphy_bitslip12_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[28], main_a7ddrphy_dfi_p3_wrdata[12], main_a7ddrphy_dfi_p2_wrdata[28], main_a7ddrphy_dfi_p2_wrdata[12], main_a7ddrphy_dfi_p1_wrdata[28], main_a7ddrphy_dfi_p1_wrdata[12], main_a7ddrphy_dfi_p0_wrdata[28], main_a7ddrphy_dfi_p0_wrdata[12]}, main_a7ddrphy_bitslip12_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip12_value1 <= (main_a7ddrphy_bitslip12_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip12_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip12_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1);
+    main_a7ddrphy_bitslip12_r1 <= {main_a7ddrphy_bitslip121, main_a7ddrphy_bitslip12_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip13_value0 <= (main_a7ddrphy_bitslip13_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip13_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip13_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1);
+    main_a7ddrphy_bitslip13_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[29], main_a7ddrphy_dfi_p3_wrdata[13], main_a7ddrphy_dfi_p2_wrdata[29], main_a7ddrphy_dfi_p2_wrdata[13], main_a7ddrphy_dfi_p1_wrdata[29], main_a7ddrphy_dfi_p1_wrdata[13], main_a7ddrphy_dfi_p0_wrdata[29], main_a7ddrphy_dfi_p0_wrdata[13]}, main_a7ddrphy_bitslip13_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip13_value1 <= (main_a7ddrphy_bitslip13_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip13_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip13_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1);
+    main_a7ddrphy_bitslip13_r1 <= {main_a7ddrphy_bitslip131, main_a7ddrphy_bitslip13_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip14_value0 <= (main_a7ddrphy_bitslip14_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip14_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip14_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1);
+    main_a7ddrphy_bitslip14_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[30], main_a7ddrphy_dfi_p3_wrdata[14], main_a7ddrphy_dfi_p2_wrdata[30], main_a7ddrphy_dfi_p2_wrdata[14], main_a7ddrphy_dfi_p1_wrdata[30], main_a7ddrphy_dfi_p1_wrdata[14], main_a7ddrphy_dfi_p0_wrdata[30], main_a7ddrphy_dfi_p0_wrdata[14]}, main_a7ddrphy_bitslip14_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip14_value1 <= (main_a7ddrphy_bitslip14_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip14_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip14_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1);
+    main_a7ddrphy_bitslip14_r1 <= {main_a7ddrphy_bitslip141, main_a7ddrphy_bitslip14_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip15_value0 <= (main_a7ddrphy_bitslip15_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip15_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip15_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1);
+    main_a7ddrphy_bitslip15_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[31], main_a7ddrphy_dfi_p3_wrdata[15], main_a7ddrphy_dfi_p2_wrdata[31], main_a7ddrphy_dfi_p2_wrdata[15], main_a7ddrphy_dfi_p1_wrdata[31], main_a7ddrphy_dfi_p1_wrdata[15], main_a7ddrphy_dfi_p0_wrdata[31], main_a7ddrphy_dfi_p0_wrdata[15]}, main_a7ddrphy_bitslip15_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip15_value1 <= (main_a7ddrphy_bitslip15_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip15_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip15_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]};
-    a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en);
-    a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0;
-    a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1;
-    a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2;
-    a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3;
-    a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4;
-    a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5;
-    a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6;
-    a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en);
-    a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0;
-    a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1;
-    if (litedramcore_csr_dfi_p0_rddata_valid) begin
-        litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata;
+    main_a7ddrphy_bitslip15_r1 <= {main_a7ddrphy_bitslip151, main_a7ddrphy_bitslip15_r1[15:8]};
+    main_a7ddrphy_rddata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_rddata_en | main_a7ddrphy_dfi_p1_rddata_en) | main_a7ddrphy_dfi_p2_rddata_en) | main_a7ddrphy_dfi_p3_rddata_en);
+    main_a7ddrphy_rddata_en_tappeddelayline1 <= main_a7ddrphy_rddata_en_tappeddelayline0;
+    main_a7ddrphy_rddata_en_tappeddelayline2 <= main_a7ddrphy_rddata_en_tappeddelayline1;
+    main_a7ddrphy_rddata_en_tappeddelayline3 <= main_a7ddrphy_rddata_en_tappeddelayline2;
+    main_a7ddrphy_rddata_en_tappeddelayline4 <= main_a7ddrphy_rddata_en_tappeddelayline3;
+    main_a7ddrphy_rddata_en_tappeddelayline5 <= main_a7ddrphy_rddata_en_tappeddelayline4;
+    main_a7ddrphy_rddata_en_tappeddelayline6 <= main_a7ddrphy_rddata_en_tappeddelayline5;
+    main_a7ddrphy_rddata_en_tappeddelayline7 <= main_a7ddrphy_rddata_en_tappeddelayline6;
+    main_a7ddrphy_wrdata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_wrdata_en | main_a7ddrphy_dfi_p1_wrdata_en) | main_a7ddrphy_dfi_p2_wrdata_en) | main_a7ddrphy_dfi_p3_wrdata_en);
+    main_a7ddrphy_wrdata_en_tappeddelayline1 <= main_a7ddrphy_wrdata_en_tappeddelayline0;
+    main_a7ddrphy_wrdata_en_tappeddelayline2 <= main_a7ddrphy_wrdata_en_tappeddelayline1;
+    if (main_litedramcore_csr_dfi_p0_rddata_valid) begin
+        main_litedramcore_phaseinjector0_rddata_status <= main_litedramcore_csr_dfi_p0_rddata;
     end
-    if (litedramcore_csr_dfi_p1_rddata_valid) begin
-        litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata;
+    if (main_litedramcore_csr_dfi_p1_rddata_valid) begin
+        main_litedramcore_phaseinjector1_rddata_status <= main_litedramcore_csr_dfi_p1_rddata;
     end
-    if (litedramcore_csr_dfi_p2_rddata_valid) begin
-        litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata;
+    if (main_litedramcore_csr_dfi_p2_rddata_valid) begin
+        main_litedramcore_phaseinjector2_rddata_status <= main_litedramcore_csr_dfi_p2_rddata;
     end
-    if (litedramcore_csr_dfi_p3_rddata_valid) begin
-        litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata;
-    end
-    if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
-        litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
+    if (main_litedramcore_csr_dfi_p3_rddata_valid) begin
+        main_litedramcore_phaseinjector3_rddata_status <= main_litedramcore_csr_dfi_p3_rddata;
+    end
+    if ((main_litedramcore_timer_wait & (~main_litedramcore_timer_done0))) begin
+        main_litedramcore_timer_count1 <= (main_litedramcore_timer_count1 - 1'd1);
     end else begin
-        litedramcore_timer_count1 <= 10'd781;
+        main_litedramcore_timer_count1 <= 10'd781;
     end
-    litedramcore_postponer_req_o <= 1'd0;
-    if (litedramcore_postponer_req_i) begin
-        litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
-        if ((litedramcore_postponer_count == 1'd0)) begin
-            litedramcore_postponer_count <= 1'd0;
-            litedramcore_postponer_req_o <= 1'd1;
-        end
+    main_litedramcore_postponer_req_o <= 1'd0;
+    if (main_litedramcore_postponer_req_i) begin
+        main_litedramcore_postponer_count <= (main_litedramcore_postponer_count - 1'd1);
+        if ((main_litedramcore_postponer_count == 1'd0)) begin
+            main_litedramcore_postponer_count <= 1'd0;
+            main_litedramcore_postponer_req_o <= 1'd1;
+        end
     end
-    if (litedramcore_sequencer_start0) begin
-        litedramcore_sequencer_count <= 1'd0;
-    end else begin
-        if (litedramcore_sequencer_done1) begin
-            if ((litedramcore_sequencer_count != 1'd0)) begin
-                litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
-            end
-        end
-    end
-    litedramcore_cmd_payload_a <= 1'd0;
-    litedramcore_cmd_payload_ba <= 1'd0;
-    litedramcore_cmd_payload_cas <= 1'd0;
-    litedramcore_cmd_payload_ras <= 1'd0;
-    litedramcore_cmd_payload_we <= 1'd0;
-    litedramcore_sequencer_done1 <= 1'd0;
-    if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
-        litedramcore_cmd_payload_a <= 11'd1024;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd1;
-        litedramcore_cmd_payload_we <= 1'd1;
-    end
-    if ((litedramcore_sequencer_counter == 2'd3)) begin
-        litedramcore_cmd_payload_a <= 11'd1024;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd1;
-        litedramcore_cmd_payload_ras <= 1'd1;
-        litedramcore_cmd_payload_we <= 1'd0;
-    end
-    if ((litedramcore_sequencer_counter == 6'd55)) begin
-        litedramcore_cmd_payload_a <= 1'd0;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd0;
-        litedramcore_cmd_payload_we <= 1'd0;
-        litedramcore_sequencer_done1 <= 1'd1;
-    end
-    if ((litedramcore_sequencer_counter == 6'd55)) begin
-        litedramcore_sequencer_counter <= 1'd0;
-    end else begin
-        if ((litedramcore_sequencer_counter != 1'd0)) begin
-            litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
+    if (main_litedramcore_sequencer_start0) begin
+        main_litedramcore_sequencer_count <= 1'd0;
+    end else begin
+        if (main_litedramcore_sequencer_done1) begin
+            if ((main_litedramcore_sequencer_count != 1'd0)) begin
+                main_litedramcore_sequencer_count <= (main_litedramcore_sequencer_count - 1'd1);
+            end
+        end
+    end
+    main_litedramcore_cmd_payload_a <= 1'd0;
+    main_litedramcore_cmd_payload_ba <= 1'd0;
+    main_litedramcore_cmd_payload_cas <= 1'd0;
+    main_litedramcore_cmd_payload_ras <= 1'd0;
+    main_litedramcore_cmd_payload_we <= 1'd0;
+    main_litedramcore_sequencer_done1 <= 1'd0;
+    if ((main_litedramcore_sequencer_start1 & (main_litedramcore_sequencer_trigger == 1'd0))) begin
+        main_litedramcore_cmd_payload_a <= 11'd1024;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd1;
+        main_litedramcore_cmd_payload_we <= 1'd1;
+    end
+    if ((main_litedramcore_sequencer_trigger == 2'd3)) begin
+        main_litedramcore_cmd_payload_a <= 11'd1024;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd1;
+        main_litedramcore_cmd_payload_ras <= 1'd1;
+        main_litedramcore_cmd_payload_we <= 1'd0;
+    end
+    if ((main_litedramcore_sequencer_trigger == 6'd55)) begin
+        main_litedramcore_cmd_payload_a <= 1'd0;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd0;
+        main_litedramcore_cmd_payload_we <= 1'd0;
+        main_litedramcore_sequencer_done1 <= 1'd1;
+    end
+    if ((main_litedramcore_sequencer_trigger == 6'd55)) begin
+        main_litedramcore_sequencer_trigger <= 1'd0;
+    end else begin
+        if ((main_litedramcore_sequencer_trigger != 1'd0)) begin
+            main_litedramcore_sequencer_trigger <= (main_litedramcore_sequencer_trigger + 1'd1);
         end else begin
-            if (litedramcore_sequencer_start1) begin
-                litedramcore_sequencer_counter <= 1'd1;
+            if (main_litedramcore_sequencer_start1) begin
+                main_litedramcore_sequencer_trigger <= 1'd1;
             end
         end
     end
-    if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
-        litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
+    if ((main_litedramcore_zqcs_timer_wait & (~main_litedramcore_zqcs_timer_done0))) begin
+        main_litedramcore_zqcs_timer_count1 <= (main_litedramcore_zqcs_timer_count1 - 1'd1);
     end else begin
-        litedramcore_zqcs_timer_count1 <= 27'd99999999;
-    end
-    litedramcore_zqcs_executer_done <= 1'd0;
-    if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
-        litedramcore_cmd_payload_a <= 11'd1024;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd1;
-        litedramcore_cmd_payload_we <= 1'd1;
-    end
-    if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
-        litedramcore_cmd_payload_a <= 1'd0;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd0;
-        litedramcore_cmd_payload_we <= 1'd1;
-    end
-    if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
-        litedramcore_cmd_payload_a <= 1'd0;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd0;
-        litedramcore_cmd_payload_we <= 1'd0;
-        litedramcore_zqcs_executer_done <= 1'd1;
-    end
-    if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
-        litedramcore_zqcs_executer_counter <= 1'd0;
+        main_litedramcore_zqcs_timer_count1 <= 27'd99999999;
+    end
+    main_litedramcore_zqcs_executer_done <= 1'd0;
+    if ((main_litedramcore_zqcs_executer_start & (main_litedramcore_zqcs_executer_trigger == 1'd0))) begin
+        main_litedramcore_cmd_payload_a <= 11'd1024;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd1;
+        main_litedramcore_cmd_payload_we <= 1'd1;
+    end
+    if ((main_litedramcore_zqcs_executer_trigger == 2'd3)) begin
+        main_litedramcore_cmd_payload_a <= 1'd0;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd0;
+        main_litedramcore_cmd_payload_we <= 1'd1;
+    end
+    if ((main_litedramcore_zqcs_executer_trigger == 5'd19)) begin
+        main_litedramcore_cmd_payload_a <= 1'd0;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd0;
+        main_litedramcore_cmd_payload_we <= 1'd0;
+        main_litedramcore_zqcs_executer_done <= 1'd1;
+    end
+    if ((main_litedramcore_zqcs_executer_trigger == 5'd19)) begin
+        main_litedramcore_zqcs_executer_trigger <= 1'd0;
     end else begin
-        if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
-            litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
+        if ((main_litedramcore_zqcs_executer_trigger != 1'd0)) begin
+            main_litedramcore_zqcs_executer_trigger <= (main_litedramcore_zqcs_executer_trigger + 1'd1);
         end else begin
-            if (litedramcore_zqcs_executer_start) begin
-                litedramcore_zqcs_executer_counter <= 1'd1;
+            if (main_litedramcore_zqcs_executer_start) begin
+                main_litedramcore_zqcs_executer_trigger <= 1'd1;
             end
         end
     end
-    litedramcore_refresher_state <= litedramcore_refresher_next_state;
-    if (litedramcore_bankmachine0_row_close) begin
-        litedramcore_bankmachine0_row_opened <= 1'd0;
+    builder_refresher_state <= builder_refresher_next_state;
+    if (main_litedramcore_bankmachine0_row_close) begin
+        main_litedramcore_bankmachine0_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine0_row_open) begin
-            litedramcore_bankmachine0_row_opened <= 1'd1;
-            litedramcore_bankmachine0_row <= litedramcore_bankmachine0_source_source_payload_addr[21:7];
+        if (main_litedramcore_bankmachine0_row_open) begin
+            main_litedramcore_bankmachine0_row_opened <= 1'd1;
+            main_litedramcore_bankmachine0_row <= main_litedramcore_bankmachine0_source_source_payload_addr[21:7];
         end
     end
-    if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin
-        litedramcore_bankmachine0_produce <= (litedramcore_bankmachine0_produce + 1'd1);
+    if (((main_litedramcore_bankmachine0_syncfifo0_we & main_litedramcore_bankmachine0_syncfifo0_writable) & (~main_litedramcore_bankmachine0_replace))) begin
+        main_litedramcore_bankmachine0_produce <= (main_litedramcore_bankmachine0_produce + 1'd1);
     end
-    if (litedramcore_bankmachine0_do_read) begin
-        litedramcore_bankmachine0_consume <= (litedramcore_bankmachine0_consume + 1'd1);
+    if (main_litedramcore_bankmachine0_do_read) begin
+        main_litedramcore_bankmachine0_consume <= (main_litedramcore_bankmachine0_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin
-        if ((~litedramcore_bankmachine0_do_read)) begin
-            litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level + 1'd1);
+    if (((main_litedramcore_bankmachine0_syncfifo0_we & main_litedramcore_bankmachine0_syncfifo0_writable) & (~main_litedramcore_bankmachine0_replace))) begin
+        if ((~main_litedramcore_bankmachine0_do_read)) begin
+            main_litedramcore_bankmachine0_level <= (main_litedramcore_bankmachine0_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine0_do_read) begin
-            litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level - 1'd1);
+        if (main_litedramcore_bankmachine0_do_read) begin
+            main_litedramcore_bankmachine0_level <= (main_litedramcore_bankmachine0_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine0_pipe_valid_source_valid <= litedramcore_bankmachine0_pipe_valid_sink_valid;
-        litedramcore_bankmachine0_pipe_valid_source_first <= litedramcore_bankmachine0_pipe_valid_sink_first;
-        litedramcore_bankmachine0_pipe_valid_source_last <= litedramcore_bankmachine0_pipe_valid_sink_last;
-        litedramcore_bankmachine0_pipe_valid_source_payload_we <= litedramcore_bankmachine0_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine0_pipe_valid_source_valid) | main_litedramcore_bankmachine0_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine0_pipe_valid_source_valid <= main_litedramcore_bankmachine0_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine0_pipe_valid_source_first <= main_litedramcore_bankmachine0_pipe_valid_sink_first;
+        main_litedramcore_bankmachine0_pipe_valid_source_last <= main_litedramcore_bankmachine0_pipe_valid_sink_last;
+        main_litedramcore_bankmachine0_pipe_valid_source_payload_we <= main_litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine0_twtpcon_valid) begin
-        litedramcore_bankmachine0_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine0_twtpcon_valid) begin
+        main_litedramcore_bankmachine0_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
-            litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine0_twtpcon_ready)) begin
+            main_litedramcore_bankmachine0_twtpcon_count <= (main_litedramcore_bankmachine0_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine0_trccon_valid) begin
-        litedramcore_bankmachine0_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine0_trccon_valid) begin
+        main_litedramcore_bankmachine0_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine0_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine0_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine0_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine0_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine0_trccon_ready)) begin
-            litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine0_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine0_trccon_ready)) begin
+            main_litedramcore_bankmachine0_trccon_count <= (main_litedramcore_bankmachine0_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine0_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine0_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine0_trascon_valid) begin
-        litedramcore_bankmachine0_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine0_trascon_valid) begin
+        main_litedramcore_bankmachine0_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine0_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine0_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine0_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine0_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine0_trascon_ready)) begin
-            litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine0_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine0_trascon_ready)) begin
+            main_litedramcore_bankmachine0_trascon_count <= (main_litedramcore_bankmachine0_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine0_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine0_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
-    if (litedramcore_bankmachine1_row_close) begin
-        litedramcore_bankmachine1_row_opened <= 1'd0;
+    builder_bankmachine0_state <= builder_bankmachine0_next_state;
+    if (main_litedramcore_bankmachine1_row_close) begin
+        main_litedramcore_bankmachine1_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine1_row_open) begin
-            litedramcore_bankmachine1_row_opened <= 1'd1;
-            litedramcore_bankmachine1_row <= litedramcore_bankmachine1_source_source_payload_addr[21:7];
+        if (main_litedramcore_bankmachine1_row_open) begin
+            main_litedramcore_bankmachine1_row_opened <= 1'd1;
+            main_litedramcore_bankmachine1_row <= main_litedramcore_bankmachine1_source_source_payload_addr[21:7];
         end
     end
-    if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin
-        litedramcore_bankmachine1_produce <= (litedramcore_bankmachine1_produce + 1'd1);
+    if (((main_litedramcore_bankmachine1_syncfifo1_we & main_litedramcore_bankmachine1_syncfifo1_writable) & (~main_litedramcore_bankmachine1_replace))) begin
+        main_litedramcore_bankmachine1_produce <= (main_litedramcore_bankmachine1_produce + 1'd1);
     end
-    if (litedramcore_bankmachine1_do_read) begin
-        litedramcore_bankmachine1_consume <= (litedramcore_bankmachine1_consume + 1'd1);
+    if (main_litedramcore_bankmachine1_do_read) begin
+        main_litedramcore_bankmachine1_consume <= (main_litedramcore_bankmachine1_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin
-        if ((~litedramcore_bankmachine1_do_read)) begin
-            litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level + 1'd1);
+    if (((main_litedramcore_bankmachine1_syncfifo1_we & main_litedramcore_bankmachine1_syncfifo1_writable) & (~main_litedramcore_bankmachine1_replace))) begin
+        if ((~main_litedramcore_bankmachine1_do_read)) begin
+            main_litedramcore_bankmachine1_level <= (main_litedramcore_bankmachine1_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine1_do_read) begin
-            litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level - 1'd1);
+        if (main_litedramcore_bankmachine1_do_read) begin
+            main_litedramcore_bankmachine1_level <= (main_litedramcore_bankmachine1_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine1_pipe_valid_source_valid <= litedramcore_bankmachine1_pipe_valid_sink_valid;
-        litedramcore_bankmachine1_pipe_valid_source_first <= litedramcore_bankmachine1_pipe_valid_sink_first;
-        litedramcore_bankmachine1_pipe_valid_source_last <= litedramcore_bankmachine1_pipe_valid_sink_last;
-        litedramcore_bankmachine1_pipe_valid_source_payload_we <= litedramcore_bankmachine1_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine1_pipe_valid_source_valid) | main_litedramcore_bankmachine1_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine1_pipe_valid_source_valid <= main_litedramcore_bankmachine1_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine1_pipe_valid_source_first <= main_litedramcore_bankmachine1_pipe_valid_sink_first;
+        main_litedramcore_bankmachine1_pipe_valid_source_last <= main_litedramcore_bankmachine1_pipe_valid_sink_last;
+        main_litedramcore_bankmachine1_pipe_valid_source_payload_we <= main_litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine1_twtpcon_valid) begin
-        litedramcore_bankmachine1_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine1_twtpcon_valid) begin
+        main_litedramcore_bankmachine1_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
-            litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine1_twtpcon_ready)) begin
+            main_litedramcore_bankmachine1_twtpcon_count <= (main_litedramcore_bankmachine1_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine1_trccon_valid) begin
-        litedramcore_bankmachine1_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine1_trccon_valid) begin
+        main_litedramcore_bankmachine1_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine1_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine1_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine1_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine1_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine1_trccon_ready)) begin
-            litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine1_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine1_trccon_ready)) begin
+            main_litedramcore_bankmachine1_trccon_count <= (main_litedramcore_bankmachine1_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine1_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine1_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine1_trascon_valid) begin
-        litedramcore_bankmachine1_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine1_trascon_valid) begin
+        main_litedramcore_bankmachine1_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine1_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine1_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine1_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine1_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine1_trascon_ready)) begin
-            litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine1_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine1_trascon_ready)) begin
+            main_litedramcore_bankmachine1_trascon_count <= (main_litedramcore_bankmachine1_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine1_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine1_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
-    if (litedramcore_bankmachine2_row_close) begin
-        litedramcore_bankmachine2_row_opened <= 1'd0;
+    builder_bankmachine1_state <= builder_bankmachine1_next_state;
+    if (main_litedramcore_bankmachine2_row_close) begin
+        main_litedramcore_bankmachine2_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine2_row_open) begin
-            litedramcore_bankmachine2_row_opened <= 1'd1;
-            litedramcore_bankmachine2_row <= litedramcore_bankmachine2_source_source_payload_addr[21:7];
+        if (main_litedramcore_bankmachine2_row_open) begin
+            main_litedramcore_bankmachine2_row_opened <= 1'd1;
+            main_litedramcore_bankmachine2_row <= main_litedramcore_bankmachine2_source_source_payload_addr[21:7];
         end
     end
-    if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin
-        litedramcore_bankmachine2_produce <= (litedramcore_bankmachine2_produce + 1'd1);
+    if (((main_litedramcore_bankmachine2_syncfifo2_we & main_litedramcore_bankmachine2_syncfifo2_writable) & (~main_litedramcore_bankmachine2_replace))) begin
+        main_litedramcore_bankmachine2_produce <= (main_litedramcore_bankmachine2_produce + 1'd1);
     end
-    if (litedramcore_bankmachine2_do_read) begin
-        litedramcore_bankmachine2_consume <= (litedramcore_bankmachine2_consume + 1'd1);
+    if (main_litedramcore_bankmachine2_do_read) begin
+        main_litedramcore_bankmachine2_consume <= (main_litedramcore_bankmachine2_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin
-        if ((~litedramcore_bankmachine2_do_read)) begin
-            litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level + 1'd1);
+    if (((main_litedramcore_bankmachine2_syncfifo2_we & main_litedramcore_bankmachine2_syncfifo2_writable) & (~main_litedramcore_bankmachine2_replace))) begin
+        if ((~main_litedramcore_bankmachine2_do_read)) begin
+            main_litedramcore_bankmachine2_level <= (main_litedramcore_bankmachine2_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine2_do_read) begin
-            litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level - 1'd1);
+        if (main_litedramcore_bankmachine2_do_read) begin
+            main_litedramcore_bankmachine2_level <= (main_litedramcore_bankmachine2_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine2_pipe_valid_source_valid <= litedramcore_bankmachine2_pipe_valid_sink_valid;
-        litedramcore_bankmachine2_pipe_valid_source_first <= litedramcore_bankmachine2_pipe_valid_sink_first;
-        litedramcore_bankmachine2_pipe_valid_source_last <= litedramcore_bankmachine2_pipe_valid_sink_last;
-        litedramcore_bankmachine2_pipe_valid_source_payload_we <= litedramcore_bankmachine2_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine2_pipe_valid_source_valid) | main_litedramcore_bankmachine2_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine2_pipe_valid_source_valid <= main_litedramcore_bankmachine2_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine2_pipe_valid_source_first <= main_litedramcore_bankmachine2_pipe_valid_sink_first;
+        main_litedramcore_bankmachine2_pipe_valid_source_last <= main_litedramcore_bankmachine2_pipe_valid_sink_last;
+        main_litedramcore_bankmachine2_pipe_valid_source_payload_we <= main_litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine2_twtpcon_valid) begin
-        litedramcore_bankmachine2_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine2_twtpcon_valid) begin
+        main_litedramcore_bankmachine2_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
-            litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine2_twtpcon_ready)) begin
+            main_litedramcore_bankmachine2_twtpcon_count <= (main_litedramcore_bankmachine2_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine2_trccon_valid) begin
-        litedramcore_bankmachine2_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine2_trccon_valid) begin
+        main_litedramcore_bankmachine2_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine2_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine2_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine2_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine2_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine2_trccon_ready)) begin
-            litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine2_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine2_trccon_ready)) begin
+            main_litedramcore_bankmachine2_trccon_count <= (main_litedramcore_bankmachine2_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine2_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine2_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine2_trascon_valid) begin
-        litedramcore_bankmachine2_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine2_trascon_valid) begin
+        main_litedramcore_bankmachine2_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine2_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine2_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine2_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine2_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine2_trascon_ready)) begin
-            litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine2_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine2_trascon_ready)) begin
+            main_litedramcore_bankmachine2_trascon_count <= (main_litedramcore_bankmachine2_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine2_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine2_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
-    if (litedramcore_bankmachine3_row_close) begin
-        litedramcore_bankmachine3_row_opened <= 1'd0;
+    builder_bankmachine2_state <= builder_bankmachine2_next_state;
+    if (main_litedramcore_bankmachine3_row_close) begin
+        main_litedramcore_bankmachine3_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine3_row_open) begin
-            litedramcore_bankmachine3_row_opened <= 1'd1;
-            litedramcore_bankmachine3_row <= litedramcore_bankmachine3_source_source_payload_addr[21:7];
+        if (main_litedramcore_bankmachine3_row_open) begin
+            main_litedramcore_bankmachine3_row_opened <= 1'd1;
+            main_litedramcore_bankmachine3_row <= main_litedramcore_bankmachine3_source_source_payload_addr[21:7];
         end
     end
-    if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin
-        litedramcore_bankmachine3_produce <= (litedramcore_bankmachine3_produce + 1'd1);
+    if (((main_litedramcore_bankmachine3_syncfifo3_we & main_litedramcore_bankmachine3_syncfifo3_writable) & (~main_litedramcore_bankmachine3_replace))) begin
+        main_litedramcore_bankmachine3_produce <= (main_litedramcore_bankmachine3_produce + 1'd1);
     end
-    if (litedramcore_bankmachine3_do_read) begin
-        litedramcore_bankmachine3_consume <= (litedramcore_bankmachine3_consume + 1'd1);
+    if (main_litedramcore_bankmachine3_do_read) begin
+        main_litedramcore_bankmachine3_consume <= (main_litedramcore_bankmachine3_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin
-        if ((~litedramcore_bankmachine3_do_read)) begin
-            litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level + 1'd1);
+    if (((main_litedramcore_bankmachine3_syncfifo3_we & main_litedramcore_bankmachine3_syncfifo3_writable) & (~main_litedramcore_bankmachine3_replace))) begin
+        if ((~main_litedramcore_bankmachine3_do_read)) begin
+            main_litedramcore_bankmachine3_level <= (main_litedramcore_bankmachine3_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine3_do_read) begin
-            litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level - 1'd1);
+        if (main_litedramcore_bankmachine3_do_read) begin
+            main_litedramcore_bankmachine3_level <= (main_litedramcore_bankmachine3_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine3_pipe_valid_source_valid <= litedramcore_bankmachine3_pipe_valid_sink_valid;
-        litedramcore_bankmachine3_pipe_valid_source_first <= litedramcore_bankmachine3_pipe_valid_sink_first;
-        litedramcore_bankmachine3_pipe_valid_source_last <= litedramcore_bankmachine3_pipe_valid_sink_last;
-        litedramcore_bankmachine3_pipe_valid_source_payload_we <= litedramcore_bankmachine3_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine3_pipe_valid_source_valid) | main_litedramcore_bankmachine3_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine3_pipe_valid_source_valid <= main_litedramcore_bankmachine3_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine3_pipe_valid_source_first <= main_litedramcore_bankmachine3_pipe_valid_sink_first;
+        main_litedramcore_bankmachine3_pipe_valid_source_last <= main_litedramcore_bankmachine3_pipe_valid_sink_last;
+        main_litedramcore_bankmachine3_pipe_valid_source_payload_we <= main_litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine3_twtpcon_valid) begin
-        litedramcore_bankmachine3_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine3_twtpcon_valid) begin
+        main_litedramcore_bankmachine3_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
-            litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine3_twtpcon_ready)) begin
+            main_litedramcore_bankmachine3_twtpcon_count <= (main_litedramcore_bankmachine3_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine3_trccon_valid) begin
-        litedramcore_bankmachine3_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine3_trccon_valid) begin
+        main_litedramcore_bankmachine3_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine3_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine3_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine3_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine3_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine3_trccon_ready)) begin
-            litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine3_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine3_trccon_ready)) begin
+            main_litedramcore_bankmachine3_trccon_count <= (main_litedramcore_bankmachine3_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine3_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine3_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine3_trascon_valid) begin
-        litedramcore_bankmachine3_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine3_trascon_valid) begin
+        main_litedramcore_bankmachine3_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine3_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine3_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine3_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine3_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine3_trascon_ready)) begin
-            litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine3_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine3_trascon_ready)) begin
+            main_litedramcore_bankmachine3_trascon_count <= (main_litedramcore_bankmachine3_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine3_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine3_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
-    if (litedramcore_bankmachine4_row_close) begin
-        litedramcore_bankmachine4_row_opened <= 1'd0;
+    builder_bankmachine3_state <= builder_bankmachine3_next_state;
+    if (main_litedramcore_bankmachine4_row_close) begin
+        main_litedramcore_bankmachine4_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine4_row_open) begin
-            litedramcore_bankmachine4_row_opened <= 1'd1;
-            litedramcore_bankmachine4_row <= litedramcore_bankmachine4_source_source_payload_addr[21:7];
+        if (main_litedramcore_bankmachine4_row_open) begin
+            main_litedramcore_bankmachine4_row_opened <= 1'd1;
+            main_litedramcore_bankmachine4_row <= main_litedramcore_bankmachine4_source_source_payload_addr[21:7];
         end
     end
-    if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin
-        litedramcore_bankmachine4_produce <= (litedramcore_bankmachine4_produce + 1'd1);
+    if (((main_litedramcore_bankmachine4_syncfifo4_we & main_litedramcore_bankmachine4_syncfifo4_writable) & (~main_litedramcore_bankmachine4_replace))) begin
+        main_litedramcore_bankmachine4_produce <= (main_litedramcore_bankmachine4_produce + 1'd1);
     end
-    if (litedramcore_bankmachine4_do_read) begin
-        litedramcore_bankmachine4_consume <= (litedramcore_bankmachine4_consume + 1'd1);
+    if (main_litedramcore_bankmachine4_do_read) begin
+        main_litedramcore_bankmachine4_consume <= (main_litedramcore_bankmachine4_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin
-        if ((~litedramcore_bankmachine4_do_read)) begin
-            litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level + 1'd1);
+    if (((main_litedramcore_bankmachine4_syncfifo4_we & main_litedramcore_bankmachine4_syncfifo4_writable) & (~main_litedramcore_bankmachine4_replace))) begin
+        if ((~main_litedramcore_bankmachine4_do_read)) begin
+            main_litedramcore_bankmachine4_level <= (main_litedramcore_bankmachine4_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine4_do_read) begin
-            litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level - 1'd1);
+        if (main_litedramcore_bankmachine4_do_read) begin
+            main_litedramcore_bankmachine4_level <= (main_litedramcore_bankmachine4_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine4_pipe_valid_source_valid <= litedramcore_bankmachine4_pipe_valid_sink_valid;
-        litedramcore_bankmachine4_pipe_valid_source_first <= litedramcore_bankmachine4_pipe_valid_sink_first;
-        litedramcore_bankmachine4_pipe_valid_source_last <= litedramcore_bankmachine4_pipe_valid_sink_last;
-        litedramcore_bankmachine4_pipe_valid_source_payload_we <= litedramcore_bankmachine4_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine4_pipe_valid_source_valid) | main_litedramcore_bankmachine4_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine4_pipe_valid_source_valid <= main_litedramcore_bankmachine4_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine4_pipe_valid_source_first <= main_litedramcore_bankmachine4_pipe_valid_sink_first;
+        main_litedramcore_bankmachine4_pipe_valid_source_last <= main_litedramcore_bankmachine4_pipe_valid_sink_last;
+        main_litedramcore_bankmachine4_pipe_valid_source_payload_we <= main_litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine4_twtpcon_valid) begin
-        litedramcore_bankmachine4_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine4_twtpcon_valid) begin
+        main_litedramcore_bankmachine4_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
-            litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine4_twtpcon_ready)) begin
+            main_litedramcore_bankmachine4_twtpcon_count <= (main_litedramcore_bankmachine4_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine4_trccon_valid) begin
-        litedramcore_bankmachine4_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine4_trccon_valid) begin
+        main_litedramcore_bankmachine4_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine4_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine4_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine4_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine4_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine4_trccon_ready)) begin
-            litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine4_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine4_trccon_ready)) begin
+            main_litedramcore_bankmachine4_trccon_count <= (main_litedramcore_bankmachine4_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine4_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine4_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine4_trascon_valid) begin
-        litedramcore_bankmachine4_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine4_trascon_valid) begin
+        main_litedramcore_bankmachine4_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine4_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine4_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine4_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine4_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine4_trascon_ready)) begin
-            litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine4_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine4_trascon_ready)) begin
+            main_litedramcore_bankmachine4_trascon_count <= (main_litedramcore_bankmachine4_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine4_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine4_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
-    if (litedramcore_bankmachine5_row_close) begin
-        litedramcore_bankmachine5_row_opened <= 1'd0;
+    builder_bankmachine4_state <= builder_bankmachine4_next_state;
+    if (main_litedramcore_bankmachine5_row_close) begin
+        main_litedramcore_bankmachine5_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine5_row_open) begin
-            litedramcore_bankmachine5_row_opened <= 1'd1;
-            litedramcore_bankmachine5_row <= litedramcore_bankmachine5_source_source_payload_addr[21:7];
+        if (main_litedramcore_bankmachine5_row_open) begin
+            main_litedramcore_bankmachine5_row_opened <= 1'd1;
+            main_litedramcore_bankmachine5_row <= main_litedramcore_bankmachine5_source_source_payload_addr[21:7];
         end
     end
-    if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin
-        litedramcore_bankmachine5_produce <= (litedramcore_bankmachine5_produce + 1'd1);
+    if (((main_litedramcore_bankmachine5_syncfifo5_we & main_litedramcore_bankmachine5_syncfifo5_writable) & (~main_litedramcore_bankmachine5_replace))) begin
+        main_litedramcore_bankmachine5_produce <= (main_litedramcore_bankmachine5_produce + 1'd1);
     end
-    if (litedramcore_bankmachine5_do_read) begin
-        litedramcore_bankmachine5_consume <= (litedramcore_bankmachine5_consume + 1'd1);
+    if (main_litedramcore_bankmachine5_do_read) begin
+        main_litedramcore_bankmachine5_consume <= (main_litedramcore_bankmachine5_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin
-        if ((~litedramcore_bankmachine5_do_read)) begin
-            litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level + 1'd1);
+    if (((main_litedramcore_bankmachine5_syncfifo5_we & main_litedramcore_bankmachine5_syncfifo5_writable) & (~main_litedramcore_bankmachine5_replace))) begin
+        if ((~main_litedramcore_bankmachine5_do_read)) begin
+            main_litedramcore_bankmachine5_level <= (main_litedramcore_bankmachine5_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine5_do_read) begin
-            litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level - 1'd1);
+        if (main_litedramcore_bankmachine5_do_read) begin
+            main_litedramcore_bankmachine5_level <= (main_litedramcore_bankmachine5_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine5_pipe_valid_source_valid <= litedramcore_bankmachine5_pipe_valid_sink_valid;
-        litedramcore_bankmachine5_pipe_valid_source_first <= litedramcore_bankmachine5_pipe_valid_sink_first;
-        litedramcore_bankmachine5_pipe_valid_source_last <= litedramcore_bankmachine5_pipe_valid_sink_last;
-        litedramcore_bankmachine5_pipe_valid_source_payload_we <= litedramcore_bankmachine5_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine5_pipe_valid_source_valid) | main_litedramcore_bankmachine5_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine5_pipe_valid_source_valid <= main_litedramcore_bankmachine5_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine5_pipe_valid_source_first <= main_litedramcore_bankmachine5_pipe_valid_sink_first;
+        main_litedramcore_bankmachine5_pipe_valid_source_last <= main_litedramcore_bankmachine5_pipe_valid_sink_last;
+        main_litedramcore_bankmachine5_pipe_valid_source_payload_we <= main_litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine5_twtpcon_valid) begin
-        litedramcore_bankmachine5_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine5_twtpcon_valid) begin
+        main_litedramcore_bankmachine5_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
-            litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine5_twtpcon_ready)) begin
+            main_litedramcore_bankmachine5_twtpcon_count <= (main_litedramcore_bankmachine5_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine5_trccon_valid) begin
-        litedramcore_bankmachine5_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine5_trccon_valid) begin
+        main_litedramcore_bankmachine5_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine5_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine5_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine5_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine5_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine5_trccon_ready)) begin
-            litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine5_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine5_trccon_ready)) begin
+            main_litedramcore_bankmachine5_trccon_count <= (main_litedramcore_bankmachine5_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine5_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine5_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine5_trascon_valid) begin
-        litedramcore_bankmachine5_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine5_trascon_valid) begin
+        main_litedramcore_bankmachine5_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine5_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine5_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine5_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine5_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine5_trascon_ready)) begin
-            litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine5_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine5_trascon_ready)) begin
+            main_litedramcore_bankmachine5_trascon_count <= (main_litedramcore_bankmachine5_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine5_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine5_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
-    if (litedramcore_bankmachine6_row_close) begin
-        litedramcore_bankmachine6_row_opened <= 1'd0;
+    builder_bankmachine5_state <= builder_bankmachine5_next_state;
+    if (main_litedramcore_bankmachine6_row_close) begin
+        main_litedramcore_bankmachine6_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine6_row_open) begin
-            litedramcore_bankmachine6_row_opened <= 1'd1;
-            litedramcore_bankmachine6_row <= litedramcore_bankmachine6_source_source_payload_addr[21:7];
+        if (main_litedramcore_bankmachine6_row_open) begin
+            main_litedramcore_bankmachine6_row_opened <= 1'd1;
+            main_litedramcore_bankmachine6_row <= main_litedramcore_bankmachine6_source_source_payload_addr[21:7];
         end
     end
-    if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin
-        litedramcore_bankmachine6_produce <= (litedramcore_bankmachine6_produce + 1'd1);
+    if (((main_litedramcore_bankmachine6_syncfifo6_we & main_litedramcore_bankmachine6_syncfifo6_writable) & (~main_litedramcore_bankmachine6_replace))) begin
+        main_litedramcore_bankmachine6_produce <= (main_litedramcore_bankmachine6_produce + 1'd1);
     end
-    if (litedramcore_bankmachine6_do_read) begin
-        litedramcore_bankmachine6_consume <= (litedramcore_bankmachine6_consume + 1'd1);
+    if (main_litedramcore_bankmachine6_do_read) begin
+        main_litedramcore_bankmachine6_consume <= (main_litedramcore_bankmachine6_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin
-        if ((~litedramcore_bankmachine6_do_read)) begin
-            litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level + 1'd1);
+    if (((main_litedramcore_bankmachine6_syncfifo6_we & main_litedramcore_bankmachine6_syncfifo6_writable) & (~main_litedramcore_bankmachine6_replace))) begin
+        if ((~main_litedramcore_bankmachine6_do_read)) begin
+            main_litedramcore_bankmachine6_level <= (main_litedramcore_bankmachine6_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine6_do_read) begin
-            litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level - 1'd1);
+        if (main_litedramcore_bankmachine6_do_read) begin
+            main_litedramcore_bankmachine6_level <= (main_litedramcore_bankmachine6_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine6_pipe_valid_source_valid <= litedramcore_bankmachine6_pipe_valid_sink_valid;
-        litedramcore_bankmachine6_pipe_valid_source_first <= litedramcore_bankmachine6_pipe_valid_sink_first;
-        litedramcore_bankmachine6_pipe_valid_source_last <= litedramcore_bankmachine6_pipe_valid_sink_last;
-        litedramcore_bankmachine6_pipe_valid_source_payload_we <= litedramcore_bankmachine6_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine6_pipe_valid_source_valid) | main_litedramcore_bankmachine6_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine6_pipe_valid_source_valid <= main_litedramcore_bankmachine6_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine6_pipe_valid_source_first <= main_litedramcore_bankmachine6_pipe_valid_sink_first;
+        main_litedramcore_bankmachine6_pipe_valid_source_last <= main_litedramcore_bankmachine6_pipe_valid_sink_last;
+        main_litedramcore_bankmachine6_pipe_valid_source_payload_we <= main_litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine6_twtpcon_valid) begin
-        litedramcore_bankmachine6_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine6_twtpcon_valid) begin
+        main_litedramcore_bankmachine6_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
-            litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine6_twtpcon_ready)) begin
+            main_litedramcore_bankmachine6_twtpcon_count <= (main_litedramcore_bankmachine6_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine6_trccon_valid) begin
-        litedramcore_bankmachine6_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine6_trccon_valid) begin
+        main_litedramcore_bankmachine6_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine6_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine6_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine6_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine6_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine6_trccon_ready)) begin
-            litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine6_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine6_trccon_ready)) begin
+            main_litedramcore_bankmachine6_trccon_count <= (main_litedramcore_bankmachine6_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine6_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine6_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine6_trascon_valid) begin
-        litedramcore_bankmachine6_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine6_trascon_valid) begin
+        main_litedramcore_bankmachine6_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine6_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine6_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine6_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine6_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine6_trascon_ready)) begin
-            litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine6_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine6_trascon_ready)) begin
+            main_litedramcore_bankmachine6_trascon_count <= (main_litedramcore_bankmachine6_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine6_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine6_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
-    if (litedramcore_bankmachine7_row_close) begin
-        litedramcore_bankmachine7_row_opened <= 1'd0;
+    builder_bankmachine6_state <= builder_bankmachine6_next_state;
+    if (main_litedramcore_bankmachine7_row_close) begin
+        main_litedramcore_bankmachine7_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine7_row_open) begin
-            litedramcore_bankmachine7_row_opened <= 1'd1;
-            litedramcore_bankmachine7_row <= litedramcore_bankmachine7_source_source_payload_addr[21:7];
+        if (main_litedramcore_bankmachine7_row_open) begin
+            main_litedramcore_bankmachine7_row_opened <= 1'd1;
+            main_litedramcore_bankmachine7_row <= main_litedramcore_bankmachine7_source_source_payload_addr[21:7];
         end
     end
-    if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin
-        litedramcore_bankmachine7_produce <= (litedramcore_bankmachine7_produce + 1'd1);
+    if (((main_litedramcore_bankmachine7_syncfifo7_we & main_litedramcore_bankmachine7_syncfifo7_writable) & (~main_litedramcore_bankmachine7_replace))) begin
+        main_litedramcore_bankmachine7_produce <= (main_litedramcore_bankmachine7_produce + 1'd1);
     end
-    if (litedramcore_bankmachine7_do_read) begin
-        litedramcore_bankmachine7_consume <= (litedramcore_bankmachine7_consume + 1'd1);
+    if (main_litedramcore_bankmachine7_do_read) begin
+        main_litedramcore_bankmachine7_consume <= (main_litedramcore_bankmachine7_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin
-        if ((~litedramcore_bankmachine7_do_read)) begin
-            litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level + 1'd1);
+    if (((main_litedramcore_bankmachine7_syncfifo7_we & main_litedramcore_bankmachine7_syncfifo7_writable) & (~main_litedramcore_bankmachine7_replace))) begin
+        if ((~main_litedramcore_bankmachine7_do_read)) begin
+            main_litedramcore_bankmachine7_level <= (main_litedramcore_bankmachine7_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine7_do_read) begin
-            litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level - 1'd1);
+        if (main_litedramcore_bankmachine7_do_read) begin
+            main_litedramcore_bankmachine7_level <= (main_litedramcore_bankmachine7_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine7_pipe_valid_source_valid <= litedramcore_bankmachine7_pipe_valid_sink_valid;
-        litedramcore_bankmachine7_pipe_valid_source_first <= litedramcore_bankmachine7_pipe_valid_sink_first;
-        litedramcore_bankmachine7_pipe_valid_source_last <= litedramcore_bankmachine7_pipe_valid_sink_last;
-        litedramcore_bankmachine7_pipe_valid_source_payload_we <= litedramcore_bankmachine7_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine7_pipe_valid_source_valid) | main_litedramcore_bankmachine7_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine7_pipe_valid_source_valid <= main_litedramcore_bankmachine7_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine7_pipe_valid_source_first <= main_litedramcore_bankmachine7_pipe_valid_sink_first;
+        main_litedramcore_bankmachine7_pipe_valid_source_last <= main_litedramcore_bankmachine7_pipe_valid_sink_last;
+        main_litedramcore_bankmachine7_pipe_valid_source_payload_we <= main_litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine7_twtpcon_valid) begin
-        litedramcore_bankmachine7_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine7_twtpcon_valid) begin
+        main_litedramcore_bankmachine7_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
-            litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine7_twtpcon_ready)) begin
+            main_litedramcore_bankmachine7_twtpcon_count <= (main_litedramcore_bankmachine7_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine7_trccon_valid) begin
-        litedramcore_bankmachine7_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine7_trccon_valid) begin
+        main_litedramcore_bankmachine7_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine7_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine7_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine7_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine7_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine7_trccon_ready)) begin
-            litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine7_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine7_trccon_ready)) begin
+            main_litedramcore_bankmachine7_trccon_count <= (main_litedramcore_bankmachine7_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine7_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine7_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine7_trascon_valid) begin
-        litedramcore_bankmachine7_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine7_trascon_valid) begin
+        main_litedramcore_bankmachine7_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine7_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine7_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine7_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine7_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine7_trascon_ready)) begin
-            litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine7_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine7_trascon_ready)) begin
+            main_litedramcore_bankmachine7_trascon_count <= (main_litedramcore_bankmachine7_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine7_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine7_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
-    if ((~litedramcore_en0)) begin
-        litedramcore_time0 <= 5'd31;
+    builder_bankmachine7_state <= builder_bankmachine7_next_state;
+    if ((~main_litedramcore_en0)) begin
+        main_litedramcore_time0 <= 5'd31;
     end else begin
-        if ((~litedramcore_max_time0)) begin
-            litedramcore_time0 <= (litedramcore_time0 - 1'd1);
+        if ((~main_litedramcore_max_time0)) begin
+            main_litedramcore_time0 <= (main_litedramcore_time0 - 1'd1);
         end
     end
-    if ((~litedramcore_en1)) begin
-        litedramcore_time1 <= 4'd15;
+    if ((~main_litedramcore_en1)) begin
+        main_litedramcore_time1 <= 4'd15;
     end else begin
-        if ((~litedramcore_max_time1)) begin
-            litedramcore_time1 <= (litedramcore_time1 - 1'd1);
+        if ((~main_litedramcore_max_time1)) begin
+            main_litedramcore_time1 <= (main_litedramcore_time1 - 1'd1);
         end
     end
-    if (litedramcore_choose_cmd_ce) begin
-        case (litedramcore_choose_cmd_grant)
+    if (main_litedramcore_choose_cmd_ce) begin
+        case (main_litedramcore_choose_cmd_grant)
             1'd0: begin
-                if (litedramcore_choose_cmd_request[1]) begin
-                    litedramcore_choose_cmd_grant <= 1'd1;
+                if (main_litedramcore_choose_cmd_request[1]) begin
+                    main_litedramcore_choose_cmd_grant <= 1'd1;
                 end else begin
-                    if (litedramcore_choose_cmd_request[2]) begin
-                        litedramcore_choose_cmd_grant <= 2'd2;
+                    if (main_litedramcore_choose_cmd_request[2]) begin
+                        main_litedramcore_choose_cmd_grant <= 2'd2;
                     end else begin
-                        if (litedramcore_choose_cmd_request[3]) begin
-                            litedramcore_choose_cmd_grant <= 2'd3;
+                        if (main_litedramcore_choose_cmd_request[3]) begin
+                            main_litedramcore_choose_cmd_grant <= 2'd3;
                         end else begin
-                            if (litedramcore_choose_cmd_request[4]) begin
-                                litedramcore_choose_cmd_grant <= 3'd4;
+                            if (main_litedramcore_choose_cmd_request[4]) begin
+                                main_litedramcore_choose_cmd_grant <= 3'd4;
                             end else begin
-                                if (litedramcore_choose_cmd_request[5]) begin
-                                    litedramcore_choose_cmd_grant <= 3'd5;
+                                if (main_litedramcore_choose_cmd_request[5]) begin
+                                    main_litedramcore_choose_cmd_grant <= 3'd5;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[6]) begin
-                                        litedramcore_choose_cmd_grant <= 3'd6;
+                                    if (main_litedramcore_choose_cmd_request[6]) begin
+                                        main_litedramcore_choose_cmd_grant <= 3'd6;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[7]) begin
-                                            litedramcore_choose_cmd_grant <= 3'd7;
+                                        if (main_litedramcore_choose_cmd_request[7]) begin
+                                            main_litedramcore_choose_cmd_grant <= 3'd7;
                                         end
                                     end
                                 end
@@ -13030,26 +13446,26 @@ always @(posedge sys_clk) begin
                 end
             end
             1'd1: begin
-                if (litedramcore_choose_cmd_request[2]) begin
-                    litedramcore_choose_cmd_grant <= 2'd2;
+                if (main_litedramcore_choose_cmd_request[2]) begin
+                    main_litedramcore_choose_cmd_grant <= 2'd2;
                 end else begin
-                    if (litedramcore_choose_cmd_request[3]) begin
-                        litedramcore_choose_cmd_grant <= 2'd3;
+                    if (main_litedramcore_choose_cmd_request[3]) begin
+                        main_litedramcore_choose_cmd_grant <= 2'd3;
                     end else begin
-                        if (litedramcore_choose_cmd_request[4]) begin
-                            litedramcore_choose_cmd_grant <= 3'd4;
+                        if (main_litedramcore_choose_cmd_request[4]) begin
+                            main_litedramcore_choose_cmd_grant <= 3'd4;
                         end else begin
-                            if (litedramcore_choose_cmd_request[5]) begin
-                                litedramcore_choose_cmd_grant <= 3'd5;
+                            if (main_litedramcore_choose_cmd_request[5]) begin
+                                main_litedramcore_choose_cmd_grant <= 3'd5;
                             end else begin
-                                if (litedramcore_choose_cmd_request[6]) begin
-                                    litedramcore_choose_cmd_grant <= 3'd6;
+                                if (main_litedramcore_choose_cmd_request[6]) begin
+                                    main_litedramcore_choose_cmd_grant <= 3'd6;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[7]) begin
-                                        litedramcore_choose_cmd_grant <= 3'd7;
+                                    if (main_litedramcore_choose_cmd_request[7]) begin
+                                        main_litedramcore_choose_cmd_grant <= 3'd7;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[0]) begin
-                                            litedramcore_choose_cmd_grant <= 1'd0;
+                                        if (main_litedramcore_choose_cmd_request[0]) begin
+                                            main_litedramcore_choose_cmd_grant <= 1'd0;
                                         end
                                     end
                                 end
@@ -13059,26 +13475,26 @@ always @(posedge sys_clk) begin
                 end
             end
             2'd2: begin
-                if (litedramcore_choose_cmd_request[3]) begin
-                    litedramcore_choose_cmd_grant <= 2'd3;
+                if (main_litedramcore_choose_cmd_request[3]) begin
+                    main_litedramcore_choose_cmd_grant <= 2'd3;
                 end else begin
-                    if (litedramcore_choose_cmd_request[4]) begin
-                        litedramcore_choose_cmd_grant <= 3'd4;
+                    if (main_litedramcore_choose_cmd_request[4]) begin
+                        main_litedramcore_choose_cmd_grant <= 3'd4;
                     end else begin
-                        if (litedramcore_choose_cmd_request[5]) begin
-                            litedramcore_choose_cmd_grant <= 3'd5;
+                        if (main_litedramcore_choose_cmd_request[5]) begin
+                            main_litedramcore_choose_cmd_grant <= 3'd5;
                         end else begin
-                            if (litedramcore_choose_cmd_request[6]) begin
-                                litedramcore_choose_cmd_grant <= 3'd6;
+                            if (main_litedramcore_choose_cmd_request[6]) begin
+                                main_litedramcore_choose_cmd_grant <= 3'd6;
                             end else begin
-                                if (litedramcore_choose_cmd_request[7]) begin
-                                    litedramcore_choose_cmd_grant <= 3'd7;
+                                if (main_litedramcore_choose_cmd_request[7]) begin
+                                    main_litedramcore_choose_cmd_grant <= 3'd7;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[0]) begin
-                                        litedramcore_choose_cmd_grant <= 1'd0;
+                                    if (main_litedramcore_choose_cmd_request[0]) begin
+                                        main_litedramcore_choose_cmd_grant <= 1'd0;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[1]) begin
-                                            litedramcore_choose_cmd_grant <= 1'd1;
+                                        if (main_litedramcore_choose_cmd_request[1]) begin
+                                            main_litedramcore_choose_cmd_grant <= 1'd1;
                                         end
                                     end
                                 end
@@ -13088,26 +13504,26 @@ always @(posedge sys_clk) begin
                 end
             end
             2'd3: begin
-                if (litedramcore_choose_cmd_request[4]) begin
-                    litedramcore_choose_cmd_grant <= 3'd4;
+                if (main_litedramcore_choose_cmd_request[4]) begin
+                    main_litedramcore_choose_cmd_grant <= 3'd4;
                 end else begin
-                    if (litedramcore_choose_cmd_request[5]) begin
-                        litedramcore_choose_cmd_grant <= 3'd5;
+                    if (main_litedramcore_choose_cmd_request[5]) begin
+                        main_litedramcore_choose_cmd_grant <= 3'd5;
                     end else begin
-                        if (litedramcore_choose_cmd_request[6]) begin
-                            litedramcore_choose_cmd_grant <= 3'd6;
+                        if (main_litedramcore_choose_cmd_request[6]) begin
+                            main_litedramcore_choose_cmd_grant <= 3'd6;
                         end else begin
-                            if (litedramcore_choose_cmd_request[7]) begin
-                                litedramcore_choose_cmd_grant <= 3'd7;
+                            if (main_litedramcore_choose_cmd_request[7]) begin
+                                main_litedramcore_choose_cmd_grant <= 3'd7;
                             end else begin
-                                if (litedramcore_choose_cmd_request[0]) begin
-                                    litedramcore_choose_cmd_grant <= 1'd0;
+                                if (main_litedramcore_choose_cmd_request[0]) begin
+                                    main_litedramcore_choose_cmd_grant <= 1'd0;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[1]) begin
-                                        litedramcore_choose_cmd_grant <= 1'd1;
+                                    if (main_litedramcore_choose_cmd_request[1]) begin
+                                        main_litedramcore_choose_cmd_grant <= 1'd1;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[2]) begin
-                                            litedramcore_choose_cmd_grant <= 2'd2;
+                                        if (main_litedramcore_choose_cmd_request[2]) begin
+                                            main_litedramcore_choose_cmd_grant <= 2'd2;
                                         end
                                     end
                                 end
@@ -13117,26 +13533,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd4: begin
-                if (litedramcore_choose_cmd_request[5]) begin
-                    litedramcore_choose_cmd_grant <= 3'd5;
+                if (main_litedramcore_choose_cmd_request[5]) begin
+                    main_litedramcore_choose_cmd_grant <= 3'd5;
                 end else begin
-                    if (litedramcore_choose_cmd_request[6]) begin
-                        litedramcore_choose_cmd_grant <= 3'd6;
+                    if (main_litedramcore_choose_cmd_request[6]) begin
+                        main_litedramcore_choose_cmd_grant <= 3'd6;
                     end else begin
-                        if (litedramcore_choose_cmd_request[7]) begin
-                            litedramcore_choose_cmd_grant <= 3'd7;
+                        if (main_litedramcore_choose_cmd_request[7]) begin
+                            main_litedramcore_choose_cmd_grant <= 3'd7;
                         end else begin
-                            if (litedramcore_choose_cmd_request[0]) begin
-                                litedramcore_choose_cmd_grant <= 1'd0;
+                            if (main_litedramcore_choose_cmd_request[0]) begin
+                                main_litedramcore_choose_cmd_grant <= 1'd0;
                             end else begin
-                                if (litedramcore_choose_cmd_request[1]) begin
-                                    litedramcore_choose_cmd_grant <= 1'd1;
+                                if (main_litedramcore_choose_cmd_request[1]) begin
+                                    main_litedramcore_choose_cmd_grant <= 1'd1;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[2]) begin
-                                        litedramcore_choose_cmd_grant <= 2'd2;
+                                    if (main_litedramcore_choose_cmd_request[2]) begin
+                                        main_litedramcore_choose_cmd_grant <= 2'd2;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[3]) begin
-                                            litedramcore_choose_cmd_grant <= 2'd3;
+                                        if (main_litedramcore_choose_cmd_request[3]) begin
+                                            main_litedramcore_choose_cmd_grant <= 2'd3;
                                         end
                                     end
                                 end
@@ -13146,26 +13562,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd5: begin
-                if (litedramcore_choose_cmd_request[6]) begin
-                    litedramcore_choose_cmd_grant <= 3'd6;
+                if (main_litedramcore_choose_cmd_request[6]) begin
+                    main_litedramcore_choose_cmd_grant <= 3'd6;
                 end else begin
-                    if (litedramcore_choose_cmd_request[7]) begin
-                        litedramcore_choose_cmd_grant <= 3'd7;
+                    if (main_litedramcore_choose_cmd_request[7]) begin
+                        main_litedramcore_choose_cmd_grant <= 3'd7;
                     end else begin
-                        if (litedramcore_choose_cmd_request[0]) begin
-                            litedramcore_choose_cmd_grant <= 1'd0;
+                        if (main_litedramcore_choose_cmd_request[0]) begin
+                            main_litedramcore_choose_cmd_grant <= 1'd0;
                         end else begin
-                            if (litedramcore_choose_cmd_request[1]) begin
-                                litedramcore_choose_cmd_grant <= 1'd1;
+                            if (main_litedramcore_choose_cmd_request[1]) begin
+                                main_litedramcore_choose_cmd_grant <= 1'd1;
                             end else begin
-                                if (litedramcore_choose_cmd_request[2]) begin
-                                    litedramcore_choose_cmd_grant <= 2'd2;
+                                if (main_litedramcore_choose_cmd_request[2]) begin
+                                    main_litedramcore_choose_cmd_grant <= 2'd2;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[3]) begin
-                                        litedramcore_choose_cmd_grant <= 2'd3;
+                                    if (main_litedramcore_choose_cmd_request[3]) begin
+                                        main_litedramcore_choose_cmd_grant <= 2'd3;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[4]) begin
-                                            litedramcore_choose_cmd_grant <= 3'd4;
+                                        if (main_litedramcore_choose_cmd_request[4]) begin
+                                            main_litedramcore_choose_cmd_grant <= 3'd4;
                                         end
                                     end
                                 end
@@ -13175,26 +13591,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd6: begin
-                if (litedramcore_choose_cmd_request[7]) begin
-                    litedramcore_choose_cmd_grant <= 3'd7;
+                if (main_litedramcore_choose_cmd_request[7]) begin
+                    main_litedramcore_choose_cmd_grant <= 3'd7;
                 end else begin
-                    if (litedramcore_choose_cmd_request[0]) begin
-                        litedramcore_choose_cmd_grant <= 1'd0;
+                    if (main_litedramcore_choose_cmd_request[0]) begin
+                        main_litedramcore_choose_cmd_grant <= 1'd0;
                     end else begin
-                        if (litedramcore_choose_cmd_request[1]) begin
-                            litedramcore_choose_cmd_grant <= 1'd1;
+                        if (main_litedramcore_choose_cmd_request[1]) begin
+                            main_litedramcore_choose_cmd_grant <= 1'd1;
                         end else begin
-                            if (litedramcore_choose_cmd_request[2]) begin
-                                litedramcore_choose_cmd_grant <= 2'd2;
+                            if (main_litedramcore_choose_cmd_request[2]) begin
+                                main_litedramcore_choose_cmd_grant <= 2'd2;
                             end else begin
-                                if (litedramcore_choose_cmd_request[3]) begin
-                                    litedramcore_choose_cmd_grant <= 2'd3;
+                                if (main_litedramcore_choose_cmd_request[3]) begin
+                                    main_litedramcore_choose_cmd_grant <= 2'd3;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[4]) begin
-                                        litedramcore_choose_cmd_grant <= 3'd4;
+                                    if (main_litedramcore_choose_cmd_request[4]) begin
+                                        main_litedramcore_choose_cmd_grant <= 3'd4;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[5]) begin
-                                            litedramcore_choose_cmd_grant <= 3'd5;
+                                        if (main_litedramcore_choose_cmd_request[5]) begin
+                                            main_litedramcore_choose_cmd_grant <= 3'd5;
                                         end
                                     end
                                 end
@@ -13204,26 +13620,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd7: begin
-                if (litedramcore_choose_cmd_request[0]) begin
-                    litedramcore_choose_cmd_grant <= 1'd0;
+                if (main_litedramcore_choose_cmd_request[0]) begin
+                    main_litedramcore_choose_cmd_grant <= 1'd0;
                 end else begin
-                    if (litedramcore_choose_cmd_request[1]) begin
-                        litedramcore_choose_cmd_grant <= 1'd1;
+                    if (main_litedramcore_choose_cmd_request[1]) begin
+                        main_litedramcore_choose_cmd_grant <= 1'd1;
                     end else begin
-                        if (litedramcore_choose_cmd_request[2]) begin
-                            litedramcore_choose_cmd_grant <= 2'd2;
+                        if (main_litedramcore_choose_cmd_request[2]) begin
+                            main_litedramcore_choose_cmd_grant <= 2'd2;
                         end else begin
-                            if (litedramcore_choose_cmd_request[3]) begin
-                                litedramcore_choose_cmd_grant <= 2'd3;
+                            if (main_litedramcore_choose_cmd_request[3]) begin
+                                main_litedramcore_choose_cmd_grant <= 2'd3;
                             end else begin
-                                if (litedramcore_choose_cmd_request[4]) begin
-                                    litedramcore_choose_cmd_grant <= 3'd4;
+                                if (main_litedramcore_choose_cmd_request[4]) begin
+                                    main_litedramcore_choose_cmd_grant <= 3'd4;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[5]) begin
-                                        litedramcore_choose_cmd_grant <= 3'd5;
+                                    if (main_litedramcore_choose_cmd_request[5]) begin
+                                        main_litedramcore_choose_cmd_grant <= 3'd5;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[6]) begin
-                                            litedramcore_choose_cmd_grant <= 3'd6;
+                                        if (main_litedramcore_choose_cmd_request[6]) begin
+                                            main_litedramcore_choose_cmd_grant <= 3'd6;
                                         end
                                     end
                                 end
@@ -13234,29 +13650,29 @@ always @(posedge sys_clk) begin
             end
         endcase
     end
-    if (litedramcore_choose_req_ce) begin
-        case (litedramcore_choose_req_grant)
+    if (main_litedramcore_choose_req_ce) begin
+        case (main_litedramcore_choose_req_grant)
             1'd0: begin
-                if (litedramcore_choose_req_request[1]) begin
-                    litedramcore_choose_req_grant <= 1'd1;
+                if (main_litedramcore_choose_req_request[1]) begin
+                    main_litedramcore_choose_req_grant <= 1'd1;
                 end else begin
-                    if (litedramcore_choose_req_request[2]) begin
-                        litedramcore_choose_req_grant <= 2'd2;
+                    if (main_litedramcore_choose_req_request[2]) begin
+                        main_litedramcore_choose_req_grant <= 2'd2;
                     end else begin
-                        if (litedramcore_choose_req_request[3]) begin
-                            litedramcore_choose_req_grant <= 2'd3;
+                        if (main_litedramcore_choose_req_request[3]) begin
+                            main_litedramcore_choose_req_grant <= 2'd3;
                         end else begin
-                            if (litedramcore_choose_req_request[4]) begin
-                                litedramcore_choose_req_grant <= 3'd4;
+                            if (main_litedramcore_choose_req_request[4]) begin
+                                main_litedramcore_choose_req_grant <= 3'd4;
                             end else begin
-                                if (litedramcore_choose_req_request[5]) begin
-                                    litedramcore_choose_req_grant <= 3'd5;
+                                if (main_litedramcore_choose_req_request[5]) begin
+                                    main_litedramcore_choose_req_grant <= 3'd5;
                                 end else begin
-                                    if (litedramcore_choose_req_request[6]) begin
-                                        litedramcore_choose_req_grant <= 3'd6;
+                                    if (main_litedramcore_choose_req_request[6]) begin
+                                        main_litedramcore_choose_req_grant <= 3'd6;
                                     end else begin
-                                        if (litedramcore_choose_req_request[7]) begin
-                                            litedramcore_choose_req_grant <= 3'd7;
+                                        if (main_litedramcore_choose_req_request[7]) begin
+                                            main_litedramcore_choose_req_grant <= 3'd7;
                                         end
                                     end
                                 end
@@ -13266,26 +13682,26 @@ always @(posedge sys_clk) begin
                 end
             end
             1'd1: begin
-                if (litedramcore_choose_req_request[2]) begin
-                    litedramcore_choose_req_grant <= 2'd2;
+                if (main_litedramcore_choose_req_request[2]) begin
+                    main_litedramcore_choose_req_grant <= 2'd2;
                 end else begin
-                    if (litedramcore_choose_req_request[3]) begin
-                        litedramcore_choose_req_grant <= 2'd3;
+                    if (main_litedramcore_choose_req_request[3]) begin
+                        main_litedramcore_choose_req_grant <= 2'd3;
                     end else begin
-                        if (litedramcore_choose_req_request[4]) begin
-                            litedramcore_choose_req_grant <= 3'd4;
+                        if (main_litedramcore_choose_req_request[4]) begin
+                            main_litedramcore_choose_req_grant <= 3'd4;
                         end else begin
-                            if (litedramcore_choose_req_request[5]) begin
-                                litedramcore_choose_req_grant <= 3'd5;
+                            if (main_litedramcore_choose_req_request[5]) begin
+                                main_litedramcore_choose_req_grant <= 3'd5;
                             end else begin
-                                if (litedramcore_choose_req_request[6]) begin
-                                    litedramcore_choose_req_grant <= 3'd6;
+                                if (main_litedramcore_choose_req_request[6]) begin
+                                    main_litedramcore_choose_req_grant <= 3'd6;
                                 end else begin
-                                    if (litedramcore_choose_req_request[7]) begin
-                                        litedramcore_choose_req_grant <= 3'd7;
+                                    if (main_litedramcore_choose_req_request[7]) begin
+                                        main_litedramcore_choose_req_grant <= 3'd7;
                                     end else begin
-                                        if (litedramcore_choose_req_request[0]) begin
-                                            litedramcore_choose_req_grant <= 1'd0;
+                                        if (main_litedramcore_choose_req_request[0]) begin
+                                            main_litedramcore_choose_req_grant <= 1'd0;
                                         end
                                     end
                                 end
@@ -13295,26 +13711,26 @@ always @(posedge sys_clk) begin
                 end
             end
             2'd2: begin
-                if (litedramcore_choose_req_request[3]) begin
-                    litedramcore_choose_req_grant <= 2'd3;
+                if (main_litedramcore_choose_req_request[3]) begin
+                    main_litedramcore_choose_req_grant <= 2'd3;
                 end else begin
-                    if (litedramcore_choose_req_request[4]) begin
-                        litedramcore_choose_req_grant <= 3'd4;
+                    if (main_litedramcore_choose_req_request[4]) begin
+                        main_litedramcore_choose_req_grant <= 3'd4;
                     end else begin
-                        if (litedramcore_choose_req_request[5]) begin
-                            litedramcore_choose_req_grant <= 3'd5;
+                        if (main_litedramcore_choose_req_request[5]) begin
+                            main_litedramcore_choose_req_grant <= 3'd5;
                         end else begin
-                            if (litedramcore_choose_req_request[6]) begin
-                                litedramcore_choose_req_grant <= 3'd6;
+                            if (main_litedramcore_choose_req_request[6]) begin
+                                main_litedramcore_choose_req_grant <= 3'd6;
                             end else begin
-                                if (litedramcore_choose_req_request[7]) begin
-                                    litedramcore_choose_req_grant <= 3'd7;
+                                if (main_litedramcore_choose_req_request[7]) begin
+                                    main_litedramcore_choose_req_grant <= 3'd7;
                                 end else begin
-                                    if (litedramcore_choose_req_request[0]) begin
-                                        litedramcore_choose_req_grant <= 1'd0;
+                                    if (main_litedramcore_choose_req_request[0]) begin
+                                        main_litedramcore_choose_req_grant <= 1'd0;
                                     end else begin
-                                        if (litedramcore_choose_req_request[1]) begin
-                                            litedramcore_choose_req_grant <= 1'd1;
+                                        if (main_litedramcore_choose_req_request[1]) begin
+                                            main_litedramcore_choose_req_grant <= 1'd1;
                                         end
                                     end
                                 end
@@ -13324,26 +13740,26 @@ always @(posedge sys_clk) begin
                 end
             end
             2'd3: begin
-                if (litedramcore_choose_req_request[4]) begin
-                    litedramcore_choose_req_grant <= 3'd4;
+                if (main_litedramcore_choose_req_request[4]) begin
+                    main_litedramcore_choose_req_grant <= 3'd4;
                 end else begin
-                    if (litedramcore_choose_req_request[5]) begin
-                        litedramcore_choose_req_grant <= 3'd5;
+                    if (main_litedramcore_choose_req_request[5]) begin
+                        main_litedramcore_choose_req_grant <= 3'd5;
                     end else begin
-                        if (litedramcore_choose_req_request[6]) begin
-                            litedramcore_choose_req_grant <= 3'd6;
+                        if (main_litedramcore_choose_req_request[6]) begin
+                            main_litedramcore_choose_req_grant <= 3'd6;
                         end else begin
-                            if (litedramcore_choose_req_request[7]) begin
-                                litedramcore_choose_req_grant <= 3'd7;
+                            if (main_litedramcore_choose_req_request[7]) begin
+                                main_litedramcore_choose_req_grant <= 3'd7;
                             end else begin
-                                if (litedramcore_choose_req_request[0]) begin
-                                    litedramcore_choose_req_grant <= 1'd0;
+                                if (main_litedramcore_choose_req_request[0]) begin
+                                    main_litedramcore_choose_req_grant <= 1'd0;
                                 end else begin
-                                    if (litedramcore_choose_req_request[1]) begin
-                                        litedramcore_choose_req_grant <= 1'd1;
+                                    if (main_litedramcore_choose_req_request[1]) begin
+                                        main_litedramcore_choose_req_grant <= 1'd1;
                                     end else begin
-                                        if (litedramcore_choose_req_request[2]) begin
-                                            litedramcore_choose_req_grant <= 2'd2;
+                                        if (main_litedramcore_choose_req_request[2]) begin
+                                            main_litedramcore_choose_req_grant <= 2'd2;
                                         end
                                     end
                                 end
@@ -13353,26 +13769,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd4: begin
-                if (litedramcore_choose_req_request[5]) begin
-                    litedramcore_choose_req_grant <= 3'd5;
+                if (main_litedramcore_choose_req_request[5]) begin
+                    main_litedramcore_choose_req_grant <= 3'd5;
                 end else begin
-                    if (litedramcore_choose_req_request[6]) begin
-                        litedramcore_choose_req_grant <= 3'd6;
+                    if (main_litedramcore_choose_req_request[6]) begin
+                        main_litedramcore_choose_req_grant <= 3'd6;
                     end else begin
-                        if (litedramcore_choose_req_request[7]) begin
-                            litedramcore_choose_req_grant <= 3'd7;
+                        if (main_litedramcore_choose_req_request[7]) begin
+                            main_litedramcore_choose_req_grant <= 3'd7;
                         end else begin
-                            if (litedramcore_choose_req_request[0]) begin
-                                litedramcore_choose_req_grant <= 1'd0;
+                            if (main_litedramcore_choose_req_request[0]) begin
+                                main_litedramcore_choose_req_grant <= 1'd0;
                             end else begin
-                                if (litedramcore_choose_req_request[1]) begin
-                                    litedramcore_choose_req_grant <= 1'd1;
+                                if (main_litedramcore_choose_req_request[1]) begin
+                                    main_litedramcore_choose_req_grant <= 1'd1;
                                 end else begin
-                                    if (litedramcore_choose_req_request[2]) begin
-                                        litedramcore_choose_req_grant <= 2'd2;
+                                    if (main_litedramcore_choose_req_request[2]) begin
+                                        main_litedramcore_choose_req_grant <= 2'd2;
                                     end else begin
-                                        if (litedramcore_choose_req_request[3]) begin
-                                            litedramcore_choose_req_grant <= 2'd3;
+                                        if (main_litedramcore_choose_req_request[3]) begin
+                                            main_litedramcore_choose_req_grant <= 2'd3;
                                         end
                                     end
                                 end
@@ -13382,26 +13798,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd5: begin
-                if (litedramcore_choose_req_request[6]) begin
-                    litedramcore_choose_req_grant <= 3'd6;
+                if (main_litedramcore_choose_req_request[6]) begin
+                    main_litedramcore_choose_req_grant <= 3'd6;
                 end else begin
-                    if (litedramcore_choose_req_request[7]) begin
-                        litedramcore_choose_req_grant <= 3'd7;
+                    if (main_litedramcore_choose_req_request[7]) begin
+                        main_litedramcore_choose_req_grant <= 3'd7;
                     end else begin
-                        if (litedramcore_choose_req_request[0]) begin
-                            litedramcore_choose_req_grant <= 1'd0;
+                        if (main_litedramcore_choose_req_request[0]) begin
+                            main_litedramcore_choose_req_grant <= 1'd0;
                         end else begin
-                            if (litedramcore_choose_req_request[1]) begin
-                                litedramcore_choose_req_grant <= 1'd1;
+                            if (main_litedramcore_choose_req_request[1]) begin
+                                main_litedramcore_choose_req_grant <= 1'd1;
                             end else begin
-                                if (litedramcore_choose_req_request[2]) begin
-                                    litedramcore_choose_req_grant <= 2'd2;
+                                if (main_litedramcore_choose_req_request[2]) begin
+                                    main_litedramcore_choose_req_grant <= 2'd2;
                                 end else begin
-                                    if (litedramcore_choose_req_request[3]) begin
-                                        litedramcore_choose_req_grant <= 2'd3;
+                                    if (main_litedramcore_choose_req_request[3]) begin
+                                        main_litedramcore_choose_req_grant <= 2'd3;
                                     end else begin
-                                        if (litedramcore_choose_req_request[4]) begin
-                                            litedramcore_choose_req_grant <= 3'd4;
+                                        if (main_litedramcore_choose_req_request[4]) begin
+                                            main_litedramcore_choose_req_grant <= 3'd4;
                                         end
                                     end
                                 end
@@ -13411,26 +13827,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd6: begin
-                if (litedramcore_choose_req_request[7]) begin
-                    litedramcore_choose_req_grant <= 3'd7;
+                if (main_litedramcore_choose_req_request[7]) begin
+                    main_litedramcore_choose_req_grant <= 3'd7;
                 end else begin
-                    if (litedramcore_choose_req_request[0]) begin
-                        litedramcore_choose_req_grant <= 1'd0;
+                    if (main_litedramcore_choose_req_request[0]) begin
+                        main_litedramcore_choose_req_grant <= 1'd0;
                     end else begin
-                        if (litedramcore_choose_req_request[1]) begin
-                            litedramcore_choose_req_grant <= 1'd1;
+                        if (main_litedramcore_choose_req_request[1]) begin
+                            main_litedramcore_choose_req_grant <= 1'd1;
                         end else begin
-                            if (litedramcore_choose_req_request[2]) begin
-                                litedramcore_choose_req_grant <= 2'd2;
+                            if (main_litedramcore_choose_req_request[2]) begin
+                                main_litedramcore_choose_req_grant <= 2'd2;
                             end else begin
-                                if (litedramcore_choose_req_request[3]) begin
-                                    litedramcore_choose_req_grant <= 2'd3;
+                                if (main_litedramcore_choose_req_request[3]) begin
+                                    main_litedramcore_choose_req_grant <= 2'd3;
                                 end else begin
-                                    if (litedramcore_choose_req_request[4]) begin
-                                        litedramcore_choose_req_grant <= 3'd4;
+                                    if (main_litedramcore_choose_req_request[4]) begin
+                                        main_litedramcore_choose_req_grant <= 3'd4;
                                     end else begin
-                                        if (litedramcore_choose_req_request[5]) begin
-                                            litedramcore_choose_req_grant <= 3'd5;
+                                        if (main_litedramcore_choose_req_request[5]) begin
+                                            main_litedramcore_choose_req_grant <= 3'd5;
                                         end
                                     end
                                 end
@@ -13440,26 +13856,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd7: begin
-                if (litedramcore_choose_req_request[0]) begin
-                    litedramcore_choose_req_grant <= 1'd0;
+                if (main_litedramcore_choose_req_request[0]) begin
+                    main_litedramcore_choose_req_grant <= 1'd0;
                 end else begin
-                    if (litedramcore_choose_req_request[1]) begin
-                        litedramcore_choose_req_grant <= 1'd1;
+                    if (main_litedramcore_choose_req_request[1]) begin
+                        main_litedramcore_choose_req_grant <= 1'd1;
                     end else begin
-                        if (litedramcore_choose_req_request[2]) begin
-                            litedramcore_choose_req_grant <= 2'd2;
+                        if (main_litedramcore_choose_req_request[2]) begin
+                            main_litedramcore_choose_req_grant <= 2'd2;
                         end else begin
-                            if (litedramcore_choose_req_request[3]) begin
-                                litedramcore_choose_req_grant <= 2'd3;
+                            if (main_litedramcore_choose_req_request[3]) begin
+                                main_litedramcore_choose_req_grant <= 2'd3;
                             end else begin
-                                if (litedramcore_choose_req_request[4]) begin
-                                    litedramcore_choose_req_grant <= 3'd4;
+                                if (main_litedramcore_choose_req_request[4]) begin
+                                    main_litedramcore_choose_req_grant <= 3'd4;
                                 end else begin
-                                    if (litedramcore_choose_req_request[5]) begin
-                                        litedramcore_choose_req_grant <= 3'd5;
+                                    if (main_litedramcore_choose_req_request[5]) begin
+                                        main_litedramcore_choose_req_grant <= 3'd5;
                                     end else begin
-                                        if (litedramcore_choose_req_request[6]) begin
-                                            litedramcore_choose_req_grant <= 3'd6;
+                                        if (main_litedramcore_choose_req_request[6]) begin
+                                            main_litedramcore_choose_req_grant <= 3'd6;
                                         end
                                     end
                                 end
@@ -13470,644 +13886,644 @@ always @(posedge sys_clk) begin
             end
         endcase
     end
-    litedramcore_dfi_p0_cs_n <= 1'd0;
-    litedramcore_dfi_p0_bank <= array_muxed0;
-    litedramcore_dfi_p0_address <= array_muxed1;
-    litedramcore_dfi_p0_cas_n <= (~array_muxed2);
-    litedramcore_dfi_p0_ras_n <= (~array_muxed3);
-    litedramcore_dfi_p0_we_n <= (~array_muxed4);
-    litedramcore_dfi_p0_rddata_en <= array_muxed5;
-    litedramcore_dfi_p0_wrdata_en <= array_muxed6;
-    litedramcore_dfi_p1_cs_n <= 1'd0;
-    litedramcore_dfi_p1_bank <= array_muxed7;
-    litedramcore_dfi_p1_address <= array_muxed8;
-    litedramcore_dfi_p1_cas_n <= (~array_muxed9);
-    litedramcore_dfi_p1_ras_n <= (~array_muxed10);
-    litedramcore_dfi_p1_we_n <= (~array_muxed11);
-    litedramcore_dfi_p1_rddata_en <= array_muxed12;
-    litedramcore_dfi_p1_wrdata_en <= array_muxed13;
-    litedramcore_dfi_p2_cs_n <= 1'd0;
-    litedramcore_dfi_p2_bank <= array_muxed14;
-    litedramcore_dfi_p2_address <= array_muxed15;
-    litedramcore_dfi_p2_cas_n <= (~array_muxed16);
-    litedramcore_dfi_p2_ras_n <= (~array_muxed17);
-    litedramcore_dfi_p2_we_n <= (~array_muxed18);
-    litedramcore_dfi_p2_rddata_en <= array_muxed19;
-    litedramcore_dfi_p2_wrdata_en <= array_muxed20;
-    litedramcore_dfi_p3_cs_n <= 1'd0;
-    litedramcore_dfi_p3_bank <= array_muxed21;
-    litedramcore_dfi_p3_address <= array_muxed22;
-    litedramcore_dfi_p3_cas_n <= (~array_muxed23);
-    litedramcore_dfi_p3_ras_n <= (~array_muxed24);
-    litedramcore_dfi_p3_we_n <= (~array_muxed25);
-    litedramcore_dfi_p3_rddata_en <= array_muxed26;
-    litedramcore_dfi_p3_wrdata_en <= array_muxed27;
-    if (litedramcore_trrdcon_valid) begin
-        litedramcore_trrdcon_count <= 1'd1;
+    main_litedramcore_dfi_p0_cs_n <= 1'd0;
+    main_litedramcore_dfi_p0_bank <= builder_self0;
+    main_litedramcore_dfi_p0_address <= builder_self1;
+    main_litedramcore_dfi_p0_cas_n <= (~builder_self2);
+    main_litedramcore_dfi_p0_ras_n <= (~builder_self3);
+    main_litedramcore_dfi_p0_we_n <= (~builder_self4);
+    main_litedramcore_dfi_p0_rddata_en <= builder_self5;
+    main_litedramcore_dfi_p0_wrdata_en <= builder_self6;
+    main_litedramcore_dfi_p1_cs_n <= 1'd0;
+    main_litedramcore_dfi_p1_bank <= builder_self7;
+    main_litedramcore_dfi_p1_address <= builder_self8;
+    main_litedramcore_dfi_p1_cas_n <= (~builder_self9);
+    main_litedramcore_dfi_p1_ras_n <= (~builder_self10);
+    main_litedramcore_dfi_p1_we_n <= (~builder_self11);
+    main_litedramcore_dfi_p1_rddata_en <= builder_self12;
+    main_litedramcore_dfi_p1_wrdata_en <= builder_self13;
+    main_litedramcore_dfi_p2_cs_n <= 1'd0;
+    main_litedramcore_dfi_p2_bank <= builder_self14;
+    main_litedramcore_dfi_p2_address <= builder_self15;
+    main_litedramcore_dfi_p2_cas_n <= (~builder_self16);
+    main_litedramcore_dfi_p2_ras_n <= (~builder_self17);
+    main_litedramcore_dfi_p2_we_n <= (~builder_self18);
+    main_litedramcore_dfi_p2_rddata_en <= builder_self19;
+    main_litedramcore_dfi_p2_wrdata_en <= builder_self20;
+    main_litedramcore_dfi_p3_cs_n <= 1'd0;
+    main_litedramcore_dfi_p3_bank <= builder_self21;
+    main_litedramcore_dfi_p3_address <= builder_self22;
+    main_litedramcore_dfi_p3_cas_n <= (~builder_self23);
+    main_litedramcore_dfi_p3_ras_n <= (~builder_self24);
+    main_litedramcore_dfi_p3_we_n <= (~builder_self25);
+    main_litedramcore_dfi_p3_rddata_en <= builder_self26;
+    main_litedramcore_dfi_p3_wrdata_en <= builder_self27;
+    if (main_litedramcore_trrdcon_valid) begin
+        main_litedramcore_trrdcon_count <= 1'd1;
         if (1'd0) begin
-            litedramcore_trrdcon_ready <= 1'd1;
+            main_litedramcore_trrdcon_ready <= 1'd1;
         end else begin
-            litedramcore_trrdcon_ready <= 1'd0;
+            main_litedramcore_trrdcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_trrdcon_ready)) begin
-            litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
-            if ((litedramcore_trrdcon_count == 1'd1)) begin
-                litedramcore_trrdcon_ready <= 1'd1;
+        if ((~main_litedramcore_trrdcon_ready)) begin
+            main_litedramcore_trrdcon_count <= (main_litedramcore_trrdcon_count - 1'd1);
+            if ((main_litedramcore_trrdcon_count == 1'd1)) begin
+                main_litedramcore_trrdcon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
-    if ((litedramcore_tfawcon_count < 3'd4)) begin
-        if ((litedramcore_tfawcon_count == 2'd3)) begin
-            litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
+    main_litedramcore_tfawcon_window <= {main_litedramcore_tfawcon_window, main_litedramcore_tfawcon_valid};
+    if ((main_litedramcore_tfawcon_count < 3'd4)) begin
+        if ((main_litedramcore_tfawcon_count == 2'd3)) begin
+            main_litedramcore_tfawcon_ready <= (~main_litedramcore_tfawcon_valid);
         end else begin
-            litedramcore_tfawcon_ready <= 1'd1;
+            main_litedramcore_tfawcon_ready <= 1'd1;
         end
     end
-    if (litedramcore_tccdcon_valid) begin
-        litedramcore_tccdcon_count <= 1'd0;
+    if (main_litedramcore_tccdcon_valid) begin
+        main_litedramcore_tccdcon_count <= 1'd0;
         if (1'd1) begin
-            litedramcore_tccdcon_ready <= 1'd1;
+            main_litedramcore_tccdcon_ready <= 1'd1;
         end else begin
-            litedramcore_tccdcon_ready <= 1'd0;
+            main_litedramcore_tccdcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_tccdcon_ready)) begin
-            litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
-            if ((litedramcore_tccdcon_count == 1'd1)) begin
-                litedramcore_tccdcon_ready <= 1'd1;
+        if ((~main_litedramcore_tccdcon_ready)) begin
+            main_litedramcore_tccdcon_count <= (main_litedramcore_tccdcon_count - 1'd1);
+            if ((main_litedramcore_tccdcon_count == 1'd1)) begin
+                main_litedramcore_tccdcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_twtrcon_valid) begin
-        litedramcore_twtrcon_count <= 3'd4;
+    if (main_litedramcore_twtrcon_valid) begin
+        main_litedramcore_twtrcon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_twtrcon_ready <= 1'd1;
+            main_litedramcore_twtrcon_ready <= 1'd1;
         end else begin
-            litedramcore_twtrcon_ready <= 1'd0;
+            main_litedramcore_twtrcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_twtrcon_ready)) begin
-            litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
-            if ((litedramcore_twtrcon_count == 1'd1)) begin
-                litedramcore_twtrcon_ready <= 1'd1;
-            end
-        end
-    end
-    litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
-    litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
-    litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
-    litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
-    litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
-    litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
-    litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
-    litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
-    litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
-    litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
-    litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
-    litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
-    litedramcore_state <= litedramcore_next_state;
-    if (litedramcore_dat_w_next_value_ce0) begin
-        litedramcore_dat_w <= litedramcore_dat_w_next_value0;
-    end
-    if (litedramcore_adr_next_value_ce1) begin
-        litedramcore_adr <= litedramcore_adr_next_value1;
-    end
-    if (litedramcore_we_next_value_ce2) begin
-        litedramcore_we <= litedramcore_we_next_value2;
-    end
-    interface0_bank_bus_dat_r <= 1'd0;
-    if (csrbank0_sel) begin
-        case (interface0_bank_bus_adr[8:0])
+        if ((~main_litedramcore_twtrcon_ready)) begin
+            main_litedramcore_twtrcon_count <= (main_litedramcore_twtrcon_count - 1'd1);
+            if ((main_litedramcore_twtrcon_count == 1'd1)) begin
+                main_litedramcore_twtrcon_ready <= 1'd1;
+            end
+        end
+    end
+    builder_multiplexer_state <= builder_multiplexer_next_state;
+    builder_new_master_wdata_ready0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_wdata_ready)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_wdata_ready)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_wdata_ready)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_wdata_ready)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_wdata_ready)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_wdata_ready)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_wdata_ready)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_wdata_ready));
+    builder_new_master_wdata_ready1 <= builder_new_master_wdata_ready0;
+    builder_new_master_rdata_valid0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_rdata_valid)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_rdata_valid)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_rdata_valid)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_rdata_valid)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_rdata_valid)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_rdata_valid)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_rdata_valid)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_rdata_valid));
+    builder_new_master_rdata_valid1 <= builder_new_master_rdata_valid0;
+    builder_new_master_rdata_valid2 <= builder_new_master_rdata_valid1;
+    builder_new_master_rdata_valid3 <= builder_new_master_rdata_valid2;
+    builder_new_master_rdata_valid4 <= builder_new_master_rdata_valid3;
+    builder_new_master_rdata_valid5 <= builder_new_master_rdata_valid4;
+    builder_new_master_rdata_valid6 <= builder_new_master_rdata_valid5;
+    builder_new_master_rdata_valid7 <= builder_new_master_rdata_valid6;
+    builder_new_master_rdata_valid8 <= builder_new_master_rdata_valid7;
+    builder_state <= builder_next_state;
+    if (builder_interface1_dat_w_next_value_ce0) begin
+        builder_interface1_dat_w <= builder_interface1_dat_w_next_value0;
+    end
+    if (builder_interface1_adr_next_value_ce1) begin
+        builder_interface1_adr <= builder_interface1_adr_next_value1;
+    end
+    if (builder_interface1_we_next_value_ce2) begin
+        builder_interface1_we <= builder_interface1_we_next_value2;
+    end
+    builder_interface0_bank_bus_dat_r <= 1'd0;
+    if (builder_csrbank0_sel) begin
+        case (builder_interface0_bank_bus_adr[8:0])
             1'd0: begin
-                interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
+                builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_done0_w;
             end
             1'd1: begin
-                interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
+                builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_error0_w;
             end
         endcase
     end
-    if (csrbank0_init_done0_re) begin
-        init_done_storage <= csrbank0_init_done0_r;
+    if (builder_csrbank0_init_done0_re) begin
+        main_init_done_storage <= builder_csrbank0_init_done0_r;
     end
-    init_done_re <= csrbank0_init_done0_re;
-    if (csrbank0_init_error0_re) begin
-        init_error_storage <= csrbank0_init_error0_r;
+    main_init_done_re <= builder_csrbank0_init_done0_re;
+    if (builder_csrbank0_init_error0_re) begin
+        main_init_error_storage <= builder_csrbank0_init_error0_r;
     end
-    init_error_re <= csrbank0_init_error0_re;
-    interface1_bank_bus_dat_r <= 1'd0;
-    if (csrbank1_sel) begin
-        case (interface1_bank_bus_adr[8:0])
+    main_init_error_re <= builder_csrbank0_init_error0_re;
+    builder_interface1_bank_bus_dat_r <= 1'd0;
+    if (builder_csrbank1_sel) begin
+        case (builder_interface1_bank_bus_adr[8:0])
             1'd0: begin
-                interface1_bank_bus_dat_r <= csrbank1_rst0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_rst0_w;
             end
             1'd1: begin
-                interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_dly_sel0_w;
             end
             2'd2: begin
-                interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_half_sys8x_taps0_w;
             end
             2'd3: begin
-                interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_wlevel_en0_w;
             end
             3'd4: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wlevel_strobe_w;
             end
             3'd5: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_rst_w;
             end
             3'd6: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_inc_w;
             end
             3'd7: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_rst_w;
             end
             4'd8: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_w;
             end
             4'd9: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_rst_w;
             end
             4'd10: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_w;
             end
             4'd11: begin
-                interface1_bank_bus_dat_r <= csrbank1_rdphase0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_rdphase0_w;
             end
             4'd12: begin
-                interface1_bank_bus_dat_r <= csrbank1_wrphase0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_wrphase0_w;
             end
         endcase
     end
-    if (csrbank1_rst0_re) begin
-        a7ddrphy_rst_storage <= csrbank1_rst0_r;
+    if (builder_csrbank1_rst0_re) begin
+        main_a7ddrphy_rst_storage <= builder_csrbank1_rst0_r;
     end
-    a7ddrphy_rst_re <= csrbank1_rst0_re;
-    if (csrbank1_dly_sel0_re) begin
-        a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r;
+    main_a7ddrphy_rst_re <= builder_csrbank1_rst0_re;
+    if (builder_csrbank1_dly_sel0_re) begin
+        main_a7ddrphy_dly_sel_storage[1:0] <= builder_csrbank1_dly_sel0_r;
     end
-    a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
-    if (csrbank1_half_sys8x_taps0_re) begin
-        a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r;
+    main_a7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re;
+    if (builder_csrbank1_half_sys8x_taps0_re) begin
+        main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r;
     end
-    a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re;
-    if (csrbank1_wlevel_en0_re) begin
-        a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r;
+    main_a7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re;
+    if (builder_csrbank1_wlevel_en0_re) begin
+        main_a7ddrphy_wlevel_en_storage <= builder_csrbank1_wlevel_en0_r;
     end
-    a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re;
-    if (csrbank1_rdphase0_re) begin
-        a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r;
+    main_a7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re;
+    if (builder_csrbank1_rdphase0_re) begin
+        main_a7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r;
     end
-    a7ddrphy_rdphase_re <= csrbank1_rdphase0_re;
-    if (csrbank1_wrphase0_re) begin
-        a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r;
+    main_a7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re;
+    if (builder_csrbank1_wrphase0_re) begin
+        main_a7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r;
     end
-    a7ddrphy_wrphase_re <= csrbank1_wrphase0_re;
-    interface2_bank_bus_dat_r <= 1'd0;
-    if (csrbank2_sel) begin
-        case (interface2_bank_bus_adr[8:0])
+    main_a7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re;
+    builder_interface2_bank_bus_dat_r <= 1'd0;
+    if (builder_csrbank2_sel) begin
+        case (builder_interface2_bank_bus_adr[8:0])
             1'd0: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_control0_w;
             end
             1'd1: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_command0_w;
             end
             2'd2: begin
-                interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
+                builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w;
             end
             2'd3: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w;
             end
             3'd4: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w;
             end
             3'd5: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w;
             end
             3'd6: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata_w;
             end
             3'd7: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w;
             end
             4'd8: begin
-                interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
+                builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w;
             end
             4'd9: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w;
             end
             4'd10: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w;
             end
             4'd11: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w;
             end
             4'd12: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata_w;
             end
             4'd13: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w;
             end
             4'd14: begin
-                interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
+                builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w;
             end
             4'd15: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w;
             end
             5'd16: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w;
             end
             5'd17: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w;
             end
             5'd18: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata_w;
             end
             5'd19: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w;
             end
             5'd20: begin
-                interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
+                builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w;
             end
             5'd21: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w;
             end
             5'd22: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w;
             end
             5'd23: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w;
             end
             5'd24: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata_w;
             end
         endcase
     end
-    if (csrbank2_dfii_control0_re) begin
-        litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
+    if (builder_csrbank2_dfii_control0_re) begin
+        main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r;
     end
-    litedramcore_re <= csrbank2_dfii_control0_re;
-    if (csrbank2_dfii_pi0_command0_re) begin
-        litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
+    main_litedramcore_re <= builder_csrbank2_dfii_control0_re;
+    if (builder_csrbank2_dfii_pi0_command0_re) begin
+        main_litedramcore_phaseinjector0_command_storage[7:0] <= builder_csrbank2_dfii_pi0_command0_r;
     end
-    litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
-    if (csrbank2_dfii_pi0_address0_re) begin
-        litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r;
+    main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re;
+    if (builder_csrbank2_dfii_pi0_address0_re) begin
+        main_litedramcore_phaseinjector0_address_storage[14:0] <= builder_csrbank2_dfii_pi0_address0_r;
     end
-    litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
-    if (csrbank2_dfii_pi0_baddress0_re) begin
-        litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
+    main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re;
+    if (builder_csrbank2_dfii_pi0_baddress0_re) begin
+        main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r;
     end
-    litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
-    if (csrbank2_dfii_pi0_wrdata0_re) begin
-        litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
+    main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re;
+    if (builder_csrbank2_dfii_pi0_wrdata0_re) begin
+        main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r;
     end
-    litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
-    litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re;
-    if (csrbank2_dfii_pi1_command0_re) begin
-        litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
+    main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re;
+    main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re;
+    if (builder_csrbank2_dfii_pi1_command0_re) begin
+        main_litedramcore_phaseinjector1_command_storage[7:0] <= builder_csrbank2_dfii_pi1_command0_r;
     end
-    litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
-    if (csrbank2_dfii_pi1_address0_re) begin
-        litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r;
+    main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re;
+    if (builder_csrbank2_dfii_pi1_address0_re) begin
+        main_litedramcore_phaseinjector1_address_storage[14:0] <= builder_csrbank2_dfii_pi1_address0_r;
     end
-    litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
-    if (csrbank2_dfii_pi1_baddress0_re) begin
-        litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
+    main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re;
+    if (builder_csrbank2_dfii_pi1_baddress0_re) begin
+        main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r;
     end
-    litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
-    if (csrbank2_dfii_pi1_wrdata0_re) begin
-        litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
+    main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re;
+    if (builder_csrbank2_dfii_pi1_wrdata0_re) begin
+        main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r;
     end
-    litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
-    litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re;
-    if (csrbank2_dfii_pi2_command0_re) begin
-        litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
+    main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re;
+    main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re;
+    if (builder_csrbank2_dfii_pi2_command0_re) begin
+        main_litedramcore_phaseinjector2_command_storage[7:0] <= builder_csrbank2_dfii_pi2_command0_r;
     end
-    litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
-    if (csrbank2_dfii_pi2_address0_re) begin
-        litedramcore_phaseinjector2_address_storage[14:0] <= csrbank2_dfii_pi2_address0_r;
+    main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re;
+    if (builder_csrbank2_dfii_pi2_address0_re) begin
+        main_litedramcore_phaseinjector2_address_storage[14:0] <= builder_csrbank2_dfii_pi2_address0_r;
     end
-    litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
-    if (csrbank2_dfii_pi2_baddress0_re) begin
-        litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
+    main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re;
+    if (builder_csrbank2_dfii_pi2_baddress0_re) begin
+        main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r;
     end
-    litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
-    if (csrbank2_dfii_pi2_wrdata0_re) begin
-        litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
+    main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re;
+    if (builder_csrbank2_dfii_pi2_wrdata0_re) begin
+        main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r;
     end
-    litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
-    litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re;
-    if (csrbank2_dfii_pi3_command0_re) begin
-        litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
+    main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re;
+    main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re;
+    if (builder_csrbank2_dfii_pi3_command0_re) begin
+        main_litedramcore_phaseinjector3_command_storage[7:0] <= builder_csrbank2_dfii_pi3_command0_r;
     end
-    litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
-    if (csrbank2_dfii_pi3_address0_re) begin
-        litedramcore_phaseinjector3_address_storage[14:0] <= csrbank2_dfii_pi3_address0_r;
+    main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re;
+    if (builder_csrbank2_dfii_pi3_address0_re) begin
+        main_litedramcore_phaseinjector3_address_storage[14:0] <= builder_csrbank2_dfii_pi3_address0_r;
     end
-    litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
-    if (csrbank2_dfii_pi3_baddress0_re) begin
-        litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
+    main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re;
+    if (builder_csrbank2_dfii_pi3_baddress0_re) begin
+        main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r;
     end
-    litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
-    if (csrbank2_dfii_pi3_wrdata0_re) begin
-        litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
+    main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re;
+    if (builder_csrbank2_dfii_pi3_wrdata0_re) begin
+        main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r;
     end
-    litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
-    litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re;
+    main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re;
+    main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re;
     if (sys_rst) begin
-        a7ddrphy_rst_storage <= 1'd0;
-        a7ddrphy_rst_re <= 1'd0;
-        a7ddrphy_dly_sel_storage <= 2'd0;
-        a7ddrphy_dly_sel_re <= 1'd0;
-        a7ddrphy_half_sys8x_taps_storage <= 5'd8;
-        a7ddrphy_half_sys8x_taps_re <= 1'd0;
-        a7ddrphy_wlevel_en_storage <= 1'd0;
-        a7ddrphy_wlevel_en_re <= 1'd0;
-        a7ddrphy_rdphase_storage <= 2'd2;
-        a7ddrphy_rdphase_re <= 1'd0;
-        a7ddrphy_wrphase_storage <= 2'd3;
-        a7ddrphy_wrphase_re <= 1'd0;
-        a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
-        a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
-        a7ddrphy_dqspattern_o1 <= 8'd0;
-        a7ddrphy_bitslip0_value0 <= 3'd7;
-        a7ddrphy_bitslip1_value0 <= 3'd7;
-        a7ddrphy_bitslip0_value1 <= 3'd7;
-        a7ddrphy_bitslip1_value1 <= 3'd7;
-        a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
-        a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
-        a7ddrphy_bitslip0_value2 <= 3'd7;
-        a7ddrphy_bitslip0_value3 <= 3'd7;
-        a7ddrphy_bitslip1_value2 <= 3'd7;
-        a7ddrphy_bitslip1_value3 <= 3'd7;
-        a7ddrphy_bitslip2_value0 <= 3'd7;
-        a7ddrphy_bitslip2_value1 <= 3'd7;
-        a7ddrphy_bitslip3_value0 <= 3'd7;
-        a7ddrphy_bitslip3_value1 <= 3'd7;
-        a7ddrphy_bitslip4_value0 <= 3'd7;
-        a7ddrphy_bitslip4_value1 <= 3'd7;
-        a7ddrphy_bitslip5_value0 <= 3'd7;
-        a7ddrphy_bitslip5_value1 <= 3'd7;
-        a7ddrphy_bitslip6_value0 <= 3'd7;
-        a7ddrphy_bitslip6_value1 <= 3'd7;
-        a7ddrphy_bitslip7_value0 <= 3'd7;
-        a7ddrphy_bitslip7_value1 <= 3'd7;
-        a7ddrphy_bitslip8_value0 <= 3'd7;
-        a7ddrphy_bitslip8_value1 <= 3'd7;
-        a7ddrphy_bitslip9_value0 <= 3'd7;
-        a7ddrphy_bitslip9_value1 <= 3'd7;
-        a7ddrphy_bitslip10_value0 <= 3'd7;
-        a7ddrphy_bitslip10_value1 <= 3'd7;
-        a7ddrphy_bitslip11_value0 <= 3'd7;
-        a7ddrphy_bitslip11_value1 <= 3'd7;
-        a7ddrphy_bitslip12_value0 <= 3'd7;
-        a7ddrphy_bitslip12_value1 <= 3'd7;
-        a7ddrphy_bitslip13_value0 <= 3'd7;
-        a7ddrphy_bitslip13_value1 <= 3'd7;
-        a7ddrphy_bitslip14_value0 <= 3'd7;
-        a7ddrphy_bitslip14_value1 <= 3'd7;
-        a7ddrphy_bitslip15_value0 <= 3'd7;
-        a7ddrphy_bitslip15_value1 <= 3'd7;
-        a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
-        a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
-        a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
-        a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
-        litedramcore_storage <= 4'd1;
-        litedramcore_re <= 1'd0;
-        litedramcore_phaseinjector0_command_storage <= 6'd0;
-        litedramcore_phaseinjector0_command_re <= 1'd0;
-        litedramcore_phaseinjector0_address_re <= 1'd0;
-        litedramcore_phaseinjector0_baddress_re <= 1'd0;
-        litedramcore_phaseinjector0_wrdata_re <= 1'd0;
-        litedramcore_phaseinjector0_rddata_status <= 32'd0;
-        litedramcore_phaseinjector0_rddata_re <= 1'd0;
-        litedramcore_phaseinjector1_command_storage <= 6'd0;
-        litedramcore_phaseinjector1_command_re <= 1'd0;
-        litedramcore_phaseinjector1_address_re <= 1'd0;
-        litedramcore_phaseinjector1_baddress_re <= 1'd0;
-        litedramcore_phaseinjector1_wrdata_re <= 1'd0;
-        litedramcore_phaseinjector1_rddata_status <= 32'd0;
-        litedramcore_phaseinjector1_rddata_re <= 1'd0;
-        litedramcore_phaseinjector2_command_storage <= 6'd0;
-        litedramcore_phaseinjector2_command_re <= 1'd0;
-        litedramcore_phaseinjector2_address_re <= 1'd0;
-        litedramcore_phaseinjector2_baddress_re <= 1'd0;
-        litedramcore_phaseinjector2_wrdata_re <= 1'd0;
-        litedramcore_phaseinjector2_rddata_status <= 32'd0;
-        litedramcore_phaseinjector2_rddata_re <= 1'd0;
-        litedramcore_phaseinjector3_command_storage <= 6'd0;
-        litedramcore_phaseinjector3_command_re <= 1'd0;
-        litedramcore_phaseinjector3_address_re <= 1'd0;
-        litedramcore_phaseinjector3_baddress_re <= 1'd0;
-        litedramcore_phaseinjector3_wrdata_re <= 1'd0;
-        litedramcore_phaseinjector3_rddata_status <= 32'd0;
-        litedramcore_phaseinjector3_rddata_re <= 1'd0;
-        litedramcore_dfi_p0_address <= 15'd0;
-        litedramcore_dfi_p0_bank <= 3'd0;
-        litedramcore_dfi_p0_cas_n <= 1'd1;
-        litedramcore_dfi_p0_cs_n <= 1'd1;
-        litedramcore_dfi_p0_ras_n <= 1'd1;
-        litedramcore_dfi_p0_we_n <= 1'd1;
-        litedramcore_dfi_p0_wrdata_en <= 1'd0;
-        litedramcore_dfi_p0_rddata_en <= 1'd0;
-        litedramcore_dfi_p1_address <= 15'd0;
-        litedramcore_dfi_p1_bank <= 3'd0;
-        litedramcore_dfi_p1_cas_n <= 1'd1;
-        litedramcore_dfi_p1_cs_n <= 1'd1;
-        litedramcore_dfi_p1_ras_n <= 1'd1;
-        litedramcore_dfi_p1_we_n <= 1'd1;
-        litedramcore_dfi_p1_wrdata_en <= 1'd0;
-        litedramcore_dfi_p1_rddata_en <= 1'd0;
-        litedramcore_dfi_p2_address <= 15'd0;
-        litedramcore_dfi_p2_bank <= 3'd0;
-        litedramcore_dfi_p2_cas_n <= 1'd1;
-        litedramcore_dfi_p2_cs_n <= 1'd1;
-        litedramcore_dfi_p2_ras_n <= 1'd1;
-        litedramcore_dfi_p2_we_n <= 1'd1;
-        litedramcore_dfi_p2_wrdata_en <= 1'd0;
-        litedramcore_dfi_p2_rddata_en <= 1'd0;
-        litedramcore_dfi_p3_address <= 15'd0;
-        litedramcore_dfi_p3_bank <= 3'd0;
-        litedramcore_dfi_p3_cas_n <= 1'd1;
-        litedramcore_dfi_p3_cs_n <= 1'd1;
-        litedramcore_dfi_p3_ras_n <= 1'd1;
-        litedramcore_dfi_p3_we_n <= 1'd1;
-        litedramcore_dfi_p3_wrdata_en <= 1'd0;
-        litedramcore_dfi_p3_rddata_en <= 1'd0;
-        litedramcore_cmd_payload_a <= 15'd0;
-        litedramcore_cmd_payload_ba <= 3'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd0;
-        litedramcore_cmd_payload_we <= 1'd0;
-        litedramcore_timer_count1 <= 10'd781;
-        litedramcore_postponer_req_o <= 1'd0;
-        litedramcore_postponer_count <= 1'd0;
-        litedramcore_sequencer_done1 <= 1'd0;
-        litedramcore_sequencer_counter <= 6'd0;
-        litedramcore_sequencer_count <= 1'd0;
-        litedramcore_zqcs_timer_count1 <= 27'd99999999;
-        litedramcore_zqcs_executer_done <= 1'd0;
-        litedramcore_zqcs_executer_counter <= 5'd0;
-        litedramcore_bankmachine0_level <= 5'd0;
-        litedramcore_bankmachine0_produce <= 4'd0;
-        litedramcore_bankmachine0_consume <= 4'd0;
-        litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 22'd0;
-        litedramcore_bankmachine0_row <= 15'd0;
-        litedramcore_bankmachine0_row_opened <= 1'd0;
-        litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine0_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine0_trccon_ready <= 1'd0;
-        litedramcore_bankmachine0_trccon_count <= 3'd0;
-        litedramcore_bankmachine0_trascon_ready <= 1'd0;
-        litedramcore_bankmachine0_trascon_count <= 3'd0;
-        litedramcore_bankmachine1_level <= 5'd0;
-        litedramcore_bankmachine1_produce <= 4'd0;
-        litedramcore_bankmachine1_consume <= 4'd0;
-        litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 22'd0;
-        litedramcore_bankmachine1_row <= 15'd0;
-        litedramcore_bankmachine1_row_opened <= 1'd0;
-        litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine1_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine1_trccon_ready <= 1'd0;
-        litedramcore_bankmachine1_trccon_count <= 3'd0;
-        litedramcore_bankmachine1_trascon_ready <= 1'd0;
-        litedramcore_bankmachine1_trascon_count <= 3'd0;
-        litedramcore_bankmachine2_level <= 5'd0;
-        litedramcore_bankmachine2_produce <= 4'd0;
-        litedramcore_bankmachine2_consume <= 4'd0;
-        litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 22'd0;
-        litedramcore_bankmachine2_row <= 15'd0;
-        litedramcore_bankmachine2_row_opened <= 1'd0;
-        litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine2_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine2_trccon_ready <= 1'd0;
-        litedramcore_bankmachine2_trccon_count <= 3'd0;
-        litedramcore_bankmachine2_trascon_ready <= 1'd0;
-        litedramcore_bankmachine2_trascon_count <= 3'd0;
-        litedramcore_bankmachine3_level <= 5'd0;
-        litedramcore_bankmachine3_produce <= 4'd0;
-        litedramcore_bankmachine3_consume <= 4'd0;
-        litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 22'd0;
-        litedramcore_bankmachine3_row <= 15'd0;
-        litedramcore_bankmachine3_row_opened <= 1'd0;
-        litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine3_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine3_trccon_ready <= 1'd0;
-        litedramcore_bankmachine3_trccon_count <= 3'd0;
-        litedramcore_bankmachine3_trascon_ready <= 1'd0;
-        litedramcore_bankmachine3_trascon_count <= 3'd0;
-        litedramcore_bankmachine4_level <= 5'd0;
-        litedramcore_bankmachine4_produce <= 4'd0;
-        litedramcore_bankmachine4_consume <= 4'd0;
-        litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 22'd0;
-        litedramcore_bankmachine4_row <= 15'd0;
-        litedramcore_bankmachine4_row_opened <= 1'd0;
-        litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine4_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine4_trccon_ready <= 1'd0;
-        litedramcore_bankmachine4_trccon_count <= 3'd0;
-        litedramcore_bankmachine4_trascon_ready <= 1'd0;
-        litedramcore_bankmachine4_trascon_count <= 3'd0;
-        litedramcore_bankmachine5_level <= 5'd0;
-        litedramcore_bankmachine5_produce <= 4'd0;
-        litedramcore_bankmachine5_consume <= 4'd0;
-        litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 22'd0;
-        litedramcore_bankmachine5_row <= 15'd0;
-        litedramcore_bankmachine5_row_opened <= 1'd0;
-        litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine5_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine5_trccon_ready <= 1'd0;
-        litedramcore_bankmachine5_trccon_count <= 3'd0;
-        litedramcore_bankmachine5_trascon_ready <= 1'd0;
-        litedramcore_bankmachine5_trascon_count <= 3'd0;
-        litedramcore_bankmachine6_level <= 5'd0;
-        litedramcore_bankmachine6_produce <= 4'd0;
-        litedramcore_bankmachine6_consume <= 4'd0;
-        litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 22'd0;
-        litedramcore_bankmachine6_row <= 15'd0;
-        litedramcore_bankmachine6_row_opened <= 1'd0;
-        litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine6_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine6_trccon_ready <= 1'd0;
-        litedramcore_bankmachine6_trccon_count <= 3'd0;
-        litedramcore_bankmachine6_trascon_ready <= 1'd0;
-        litedramcore_bankmachine6_trascon_count <= 3'd0;
-        litedramcore_bankmachine7_level <= 5'd0;
-        litedramcore_bankmachine7_produce <= 4'd0;
-        litedramcore_bankmachine7_consume <= 4'd0;
-        litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 22'd0;
-        litedramcore_bankmachine7_row <= 15'd0;
-        litedramcore_bankmachine7_row_opened <= 1'd0;
-        litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine7_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine7_trccon_ready <= 1'd0;
-        litedramcore_bankmachine7_trccon_count <= 3'd0;
-        litedramcore_bankmachine7_trascon_ready <= 1'd0;
-        litedramcore_bankmachine7_trascon_count <= 3'd0;
-        litedramcore_choose_cmd_grant <= 3'd0;
-        litedramcore_choose_req_grant <= 3'd0;
-        litedramcore_trrdcon_ready <= 1'd0;
-        litedramcore_trrdcon_count <= 1'd0;
-        litedramcore_tfawcon_ready <= 1'd1;
-        litedramcore_tfawcon_window <= 5'd0;
-        litedramcore_tccdcon_ready <= 1'd0;
-        litedramcore_tccdcon_count <= 1'd0;
-        litedramcore_twtrcon_ready <= 1'd0;
-        litedramcore_twtrcon_count <= 3'd0;
-        litedramcore_time0 <= 5'd0;
-        litedramcore_time1 <= 4'd0;
-        init_done_storage <= 1'd0;
-        init_done_re <= 1'd0;
-        init_error_storage <= 1'd0;
-        init_error_re <= 1'd0;
-        litedramcore_we <= 1'd0;
-        litedramcore_refresher_state <= 2'd0;
-        litedramcore_bankmachine0_state <= 4'd0;
-        litedramcore_bankmachine1_state <= 4'd0;
-        litedramcore_bankmachine2_state <= 4'd0;
-        litedramcore_bankmachine3_state <= 4'd0;
-        litedramcore_bankmachine4_state <= 4'd0;
-        litedramcore_bankmachine5_state <= 4'd0;
-        litedramcore_bankmachine6_state <= 4'd0;
-        litedramcore_bankmachine7_state <= 4'd0;
-        litedramcore_multiplexer_state <= 4'd0;
-        litedramcore_new_master_wdata_ready0 <= 1'd0;
-        litedramcore_new_master_wdata_ready1 <= 1'd0;
-        litedramcore_new_master_rdata_valid0 <= 1'd0;
-        litedramcore_new_master_rdata_valid1 <= 1'd0;
-        litedramcore_new_master_rdata_valid2 <= 1'd0;
-        litedramcore_new_master_rdata_valid3 <= 1'd0;
-        litedramcore_new_master_rdata_valid4 <= 1'd0;
-        litedramcore_new_master_rdata_valid5 <= 1'd0;
-        litedramcore_new_master_rdata_valid6 <= 1'd0;
-        litedramcore_new_master_rdata_valid7 <= 1'd0;
-        litedramcore_new_master_rdata_valid8 <= 1'd0;
-        litedramcore_state <= 2'd0;
+        main_a7ddrphy_rst_storage <= 1'd0;
+        main_a7ddrphy_rst_re <= 1'd0;
+        main_a7ddrphy_dly_sel_storage <= 2'd0;
+        main_a7ddrphy_dly_sel_re <= 1'd0;
+        main_a7ddrphy_half_sys8x_taps_storage <= 5'd8;
+        main_a7ddrphy_half_sys8x_taps_re <= 1'd0;
+        main_a7ddrphy_wlevel_en_storage <= 1'd0;
+        main_a7ddrphy_wlevel_en_re <= 1'd0;
+        main_a7ddrphy_rdphase_storage <= 2'd2;
+        main_a7ddrphy_rdphase_re <= 1'd0;
+        main_a7ddrphy_wrphase_storage <= 2'd3;
+        main_a7ddrphy_wrphase_re <= 1'd0;
+        main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+        main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+        main_a7ddrphy_dqspattern_o1 <= 8'd0;
+        main_a7ddrphy_bitslip0_value0 <= 3'd7;
+        main_a7ddrphy_bitslip1_value0 <= 3'd7;
+        main_a7ddrphy_bitslip0_value1 <= 3'd7;
+        main_a7ddrphy_bitslip1_value1 <= 3'd7;
+        main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+        main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+        main_a7ddrphy_bitslip0_value2 <= 3'd7;
+        main_a7ddrphy_bitslip0_value3 <= 3'd7;
+        main_a7ddrphy_bitslip1_value2 <= 3'd7;
+        main_a7ddrphy_bitslip1_value3 <= 3'd7;
+        main_a7ddrphy_bitslip2_value0 <= 3'd7;
+        main_a7ddrphy_bitslip2_value1 <= 3'd7;
+        main_a7ddrphy_bitslip3_value0 <= 3'd7;
+        main_a7ddrphy_bitslip3_value1 <= 3'd7;
+        main_a7ddrphy_bitslip4_value0 <= 3'd7;
+        main_a7ddrphy_bitslip4_value1 <= 3'd7;
+        main_a7ddrphy_bitslip5_value0 <= 3'd7;
+        main_a7ddrphy_bitslip5_value1 <= 3'd7;
+        main_a7ddrphy_bitslip6_value0 <= 3'd7;
+        main_a7ddrphy_bitslip6_value1 <= 3'd7;
+        main_a7ddrphy_bitslip7_value0 <= 3'd7;
+        main_a7ddrphy_bitslip7_value1 <= 3'd7;
+        main_a7ddrphy_bitslip8_value0 <= 3'd7;
+        main_a7ddrphy_bitslip8_value1 <= 3'd7;
+        main_a7ddrphy_bitslip9_value0 <= 3'd7;
+        main_a7ddrphy_bitslip9_value1 <= 3'd7;
+        main_a7ddrphy_bitslip10_value0 <= 3'd7;
+        main_a7ddrphy_bitslip10_value1 <= 3'd7;
+        main_a7ddrphy_bitslip11_value0 <= 3'd7;
+        main_a7ddrphy_bitslip11_value1 <= 3'd7;
+        main_a7ddrphy_bitslip12_value0 <= 3'd7;
+        main_a7ddrphy_bitslip12_value1 <= 3'd7;
+        main_a7ddrphy_bitslip13_value0 <= 3'd7;
+        main_a7ddrphy_bitslip13_value1 <= 3'd7;
+        main_a7ddrphy_bitslip14_value0 <= 3'd7;
+        main_a7ddrphy_bitslip14_value1 <= 3'd7;
+        main_a7ddrphy_bitslip15_value0 <= 3'd7;
+        main_a7ddrphy_bitslip15_value1 <= 3'd7;
+        main_a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
+        main_a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
+        main_a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
+        main_a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
+        main_litedramcore_storage <= 4'd1;
+        main_litedramcore_re <= 1'd0;
+        main_litedramcore_phaseinjector0_command_storage <= 8'd0;
+        main_litedramcore_phaseinjector0_command_re <= 1'd0;
+        main_litedramcore_phaseinjector0_address_re <= 1'd0;
+        main_litedramcore_phaseinjector0_baddress_re <= 1'd0;
+        main_litedramcore_phaseinjector0_wrdata_re <= 1'd0;
+        main_litedramcore_phaseinjector0_rddata_status <= 32'd0;
+        main_litedramcore_phaseinjector0_rddata_re <= 1'd0;
+        main_litedramcore_phaseinjector1_command_storage <= 8'd0;
+        main_litedramcore_phaseinjector1_command_re <= 1'd0;
+        main_litedramcore_phaseinjector1_address_re <= 1'd0;
+        main_litedramcore_phaseinjector1_baddress_re <= 1'd0;
+        main_litedramcore_phaseinjector1_wrdata_re <= 1'd0;
+        main_litedramcore_phaseinjector1_rddata_status <= 32'd0;
+        main_litedramcore_phaseinjector1_rddata_re <= 1'd0;
+        main_litedramcore_phaseinjector2_command_storage <= 8'd0;
+        main_litedramcore_phaseinjector2_command_re <= 1'd0;
+        main_litedramcore_phaseinjector2_address_re <= 1'd0;
+        main_litedramcore_phaseinjector2_baddress_re <= 1'd0;
+        main_litedramcore_phaseinjector2_wrdata_re <= 1'd0;
+        main_litedramcore_phaseinjector2_rddata_status <= 32'd0;
+        main_litedramcore_phaseinjector2_rddata_re <= 1'd0;
+        main_litedramcore_phaseinjector3_command_storage <= 8'd0;
+        main_litedramcore_phaseinjector3_command_re <= 1'd0;
+        main_litedramcore_phaseinjector3_address_re <= 1'd0;
+        main_litedramcore_phaseinjector3_baddress_re <= 1'd0;
+        main_litedramcore_phaseinjector3_wrdata_re <= 1'd0;
+        main_litedramcore_phaseinjector3_rddata_status <= 32'd0;
+        main_litedramcore_phaseinjector3_rddata_re <= 1'd0;
+        main_litedramcore_dfi_p0_address <= 15'd0;
+        main_litedramcore_dfi_p0_bank <= 3'd0;
+        main_litedramcore_dfi_p0_cas_n <= 1'd1;
+        main_litedramcore_dfi_p0_cs_n <= 1'd1;
+        main_litedramcore_dfi_p0_ras_n <= 1'd1;
+        main_litedramcore_dfi_p0_we_n <= 1'd1;
+        main_litedramcore_dfi_p0_wrdata_en <= 1'd0;
+        main_litedramcore_dfi_p0_rddata_en <= 1'd0;
+        main_litedramcore_dfi_p1_address <= 15'd0;
+        main_litedramcore_dfi_p1_bank <= 3'd0;
+        main_litedramcore_dfi_p1_cas_n <= 1'd1;
+        main_litedramcore_dfi_p1_cs_n <= 1'd1;
+        main_litedramcore_dfi_p1_ras_n <= 1'd1;
+        main_litedramcore_dfi_p1_we_n <= 1'd1;
+        main_litedramcore_dfi_p1_wrdata_en <= 1'd0;
+        main_litedramcore_dfi_p1_rddata_en <= 1'd0;
+        main_litedramcore_dfi_p2_address <= 15'd0;
+        main_litedramcore_dfi_p2_bank <= 3'd0;
+        main_litedramcore_dfi_p2_cas_n <= 1'd1;
+        main_litedramcore_dfi_p2_cs_n <= 1'd1;
+        main_litedramcore_dfi_p2_ras_n <= 1'd1;
+        main_litedramcore_dfi_p2_we_n <= 1'd1;
+        main_litedramcore_dfi_p2_wrdata_en <= 1'd0;
+        main_litedramcore_dfi_p2_rddata_en <= 1'd0;
+        main_litedramcore_dfi_p3_address <= 15'd0;
+        main_litedramcore_dfi_p3_bank <= 3'd0;
+        main_litedramcore_dfi_p3_cas_n <= 1'd1;
+        main_litedramcore_dfi_p3_cs_n <= 1'd1;
+        main_litedramcore_dfi_p3_ras_n <= 1'd1;
+        main_litedramcore_dfi_p3_we_n <= 1'd1;
+        main_litedramcore_dfi_p3_wrdata_en <= 1'd0;
+        main_litedramcore_dfi_p3_rddata_en <= 1'd0;
+        main_litedramcore_cmd_payload_a <= 15'd0;
+        main_litedramcore_cmd_payload_ba <= 3'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd0;
+        main_litedramcore_cmd_payload_we <= 1'd0;
+        main_litedramcore_timer_count1 <= 10'd781;
+        main_litedramcore_postponer_req_o <= 1'd0;
+        main_litedramcore_postponer_count <= 1'd0;
+        main_litedramcore_sequencer_done1 <= 1'd0;
+        main_litedramcore_sequencer_trigger <= 6'd0;
+        main_litedramcore_sequencer_count <= 1'd0;
+        main_litedramcore_zqcs_timer_count1 <= 27'd99999999;
+        main_litedramcore_zqcs_executer_done <= 1'd0;
+        main_litedramcore_zqcs_executer_trigger <= 5'd0;
+        main_litedramcore_bankmachine0_level <= 5'd0;
+        main_litedramcore_bankmachine0_produce <= 4'd0;
+        main_litedramcore_bankmachine0_consume <= 4'd0;
+        main_litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 22'd0;
+        main_litedramcore_bankmachine0_row <= 15'd0;
+        main_litedramcore_bankmachine0_row_opened <= 1'd0;
+        main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine0_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine0_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine0_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine0_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine0_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine1_level <= 5'd0;
+        main_litedramcore_bankmachine1_produce <= 4'd0;
+        main_litedramcore_bankmachine1_consume <= 4'd0;
+        main_litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 22'd0;
+        main_litedramcore_bankmachine1_row <= 15'd0;
+        main_litedramcore_bankmachine1_row_opened <= 1'd0;
+        main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine1_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine1_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine1_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine1_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine1_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine2_level <= 5'd0;
+        main_litedramcore_bankmachine2_produce <= 4'd0;
+        main_litedramcore_bankmachine2_consume <= 4'd0;
+        main_litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 22'd0;
+        main_litedramcore_bankmachine2_row <= 15'd0;
+        main_litedramcore_bankmachine2_row_opened <= 1'd0;
+        main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine2_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine2_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine2_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine2_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine2_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine3_level <= 5'd0;
+        main_litedramcore_bankmachine3_produce <= 4'd0;
+        main_litedramcore_bankmachine3_consume <= 4'd0;
+        main_litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 22'd0;
+        main_litedramcore_bankmachine3_row <= 15'd0;
+        main_litedramcore_bankmachine3_row_opened <= 1'd0;
+        main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine3_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine3_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine3_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine3_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine3_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine4_level <= 5'd0;
+        main_litedramcore_bankmachine4_produce <= 4'd0;
+        main_litedramcore_bankmachine4_consume <= 4'd0;
+        main_litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 22'd0;
+        main_litedramcore_bankmachine4_row <= 15'd0;
+        main_litedramcore_bankmachine4_row_opened <= 1'd0;
+        main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine4_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine4_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine4_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine4_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine4_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine5_level <= 5'd0;
+        main_litedramcore_bankmachine5_produce <= 4'd0;
+        main_litedramcore_bankmachine5_consume <= 4'd0;
+        main_litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 22'd0;
+        main_litedramcore_bankmachine5_row <= 15'd0;
+        main_litedramcore_bankmachine5_row_opened <= 1'd0;
+        main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine5_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine5_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine5_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine5_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine5_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine6_level <= 5'd0;
+        main_litedramcore_bankmachine6_produce <= 4'd0;
+        main_litedramcore_bankmachine6_consume <= 4'd0;
+        main_litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 22'd0;
+        main_litedramcore_bankmachine6_row <= 15'd0;
+        main_litedramcore_bankmachine6_row_opened <= 1'd0;
+        main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine6_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine6_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine6_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine6_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine6_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine7_level <= 5'd0;
+        main_litedramcore_bankmachine7_produce <= 4'd0;
+        main_litedramcore_bankmachine7_consume <= 4'd0;
+        main_litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 22'd0;
+        main_litedramcore_bankmachine7_row <= 15'd0;
+        main_litedramcore_bankmachine7_row_opened <= 1'd0;
+        main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine7_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine7_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine7_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine7_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine7_trascon_count <= 3'd0;
+        main_litedramcore_choose_cmd_grant <= 3'd0;
+        main_litedramcore_choose_req_grant <= 3'd0;
+        main_litedramcore_trrdcon_ready <= 1'd0;
+        main_litedramcore_trrdcon_count <= 1'd0;
+        main_litedramcore_tfawcon_ready <= 1'd1;
+        main_litedramcore_tfawcon_window <= 5'd0;
+        main_litedramcore_tccdcon_ready <= 1'd0;
+        main_litedramcore_tccdcon_count <= 1'd0;
+        main_litedramcore_twtrcon_ready <= 1'd0;
+        main_litedramcore_twtrcon_count <= 3'd0;
+        main_litedramcore_time0 <= 5'd0;
+        main_litedramcore_time1 <= 4'd0;
+        main_init_done_storage <= 1'd0;
+        main_init_done_re <= 1'd0;
+        main_init_error_storage <= 1'd0;
+        main_init_error_re <= 1'd0;
+        builder_interface1_we <= 1'd0;
+        builder_refresher_state <= 2'd0;
+        builder_bankmachine0_state <= 4'd0;
+        builder_bankmachine1_state <= 4'd0;
+        builder_bankmachine2_state <= 4'd0;
+        builder_bankmachine3_state <= 4'd0;
+        builder_bankmachine4_state <= 4'd0;
+        builder_bankmachine5_state <= 4'd0;
+        builder_bankmachine6_state <= 4'd0;
+        builder_bankmachine7_state <= 4'd0;
+        builder_multiplexer_state <= 4'd0;
+        builder_new_master_wdata_ready0 <= 1'd0;
+        builder_new_master_wdata_ready1 <= 1'd0;
+        builder_new_master_rdata_valid0 <= 1'd0;
+        builder_new_master_rdata_valid1 <= 1'd0;
+        builder_new_master_rdata_valid2 <= 1'd0;
+        builder_new_master_rdata_valid3 <= 1'd0;
+        builder_new_master_rdata_valid4 <= 1'd0;
+        builder_new_master_rdata_valid5 <= 1'd0;
+        builder_new_master_rdata_valid6 <= 1'd0;
+        builder_new_master_rdata_valid7 <= 1'd0;
+        builder_new_master_rdata_valid8 <= 1'd0;
+        builder_state <= 2'd0;
     end
 end
 
@@ -14116,1933 +14532,2653 @@ end
 // Specialized Logic
 //------------------------------------------------------------------------------
 
+//------------------------------------------------------------------------------
+// Instance BUFG of BUFG Module.
+//------------------------------------------------------------------------------
 BUFG BUFG(
-	.I(clkout0),
-	.O(clkout_buf0)
+	// Inputs.
+	.I (main_clkout0),
+
+	// Outputs.
+	.O (main_clkout_buf0)
 );
 
+//------------------------------------------------------------------------------
+// Instance BUFG_1 of BUFG Module.
+//------------------------------------------------------------------------------
 BUFG BUFG_1(
-	.I(clkout1),
-	.O(clkout_buf1)
+	// Inputs.
+	.I (main_clkout1),
+
+	// Outputs.
+	.O (main_clkout_buf1)
 );
 
+//------------------------------------------------------------------------------
+// Instance BUFG_2 of BUFG Module.
+//------------------------------------------------------------------------------
 BUFG BUFG_2(
-	.I(clkout2),
-	.O(clkout_buf2)
+	// Inputs.
+	.I (main_clkout2),
+
+	// Outputs.
+	.O (main_clkout_buf2)
 );
 
+//------------------------------------------------------------------------------
+// Instance BUFG_3 of BUFG Module.
+//------------------------------------------------------------------------------
 BUFG BUFG_3(
-	.I(clkout3),
-	.O(clkout_buf3)
+	// Inputs.
+	.I (main_clkout3),
+
+	// Outputs.
+	.O (main_clkout_buf3)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYCTRL of IDELAYCTRL Module.
+//------------------------------------------------------------------------------
 IDELAYCTRL IDELAYCTRL(
-	.REFCLK(iodelay_clk),
-	.RST(ic_reset)
+	// Inputs.
+	.REFCLK (iodelay_clk),
+	.RST    (main_ic_reset)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(1'd0),
-	.D2(1'd1),
-	.D3(1'd0),
-	.D4(1'd1),
-	.D5(1'd0),
-	.D6(1'd1),
-	.D7(1'd0),
-	.D8(1'd1),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(a7ddrphy_sd_clk_se_nodelay)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (1'd0),
+	.D2     (1'd1),
+	.D3     (1'd0),
+	.D4     (1'd1),
+	.D5     (1'd0),
+	.D6     (1'd1),
+	.D7     (1'd0),
+	.D8     (1'd1),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_sd_clk_se_nodelay)
 );
 
+//------------------------------------------------------------------------------
+// Instance OBUFDS of OBUFDS Module.
+//------------------------------------------------------------------------------
 OBUFDS OBUFDS(
-	.I(a7ddrphy_sd_clk_se_nodelay),
-	.O(ddram_clk_p),
-	.OB(ddram_clk_n)
+	// Inputs.
+	.I  (main_a7ddrphy_sd_clk_se_nodelay),
+
+	// Outputs.
+	.O  (ddram_clk_p),
+	.OB (ddram_clk_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_1 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_1 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_reset_n),
-	.D2(a7ddrphy_dfi_p0_reset_n),
-	.D3(a7ddrphy_dfi_p1_reset_n),
-	.D4(a7ddrphy_dfi_p1_reset_n),
-	.D5(a7ddrphy_dfi_p2_reset_n),
-	.D6(a7ddrphy_dfi_p2_reset_n),
-	.D7(a7ddrphy_dfi_p3_reset_n),
-	.D8(a7ddrphy_dfi_p3_reset_n),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_reset_n)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_reset_n),
+	.D2     (main_a7ddrphy_dfi_p0_reset_n),
+	.D3     (main_a7ddrphy_dfi_p1_reset_n),
+	.D4     (main_a7ddrphy_dfi_p1_reset_n),
+	.D5     (main_a7ddrphy_dfi_p2_reset_n),
+	.D6     (main_a7ddrphy_dfi_p2_reset_n),
+	.D7     (main_a7ddrphy_dfi_p3_reset_n),
+	.D8     (main_a7ddrphy_dfi_p3_reset_n),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_reset_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_2 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_2 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_cs_n),
-	.D2(a7ddrphy_dfi_p0_cs_n),
-	.D3(a7ddrphy_dfi_p1_cs_n),
-	.D4(a7ddrphy_dfi_p1_cs_n),
-	.D5(a7ddrphy_dfi_p2_cs_n),
-	.D6(a7ddrphy_dfi_p2_cs_n),
-	.D7(a7ddrphy_dfi_p3_cs_n),
-	.D8(a7ddrphy_dfi_p3_cs_n),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_cs_n)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_cs_n),
+	.D2     (main_a7ddrphy_dfi_p0_cs_n),
+	.D3     (main_a7ddrphy_dfi_p1_cs_n),
+	.D4     (main_a7ddrphy_dfi_p1_cs_n),
+	.D5     (main_a7ddrphy_dfi_p2_cs_n),
+	.D6     (main_a7ddrphy_dfi_p2_cs_n),
+	.D7     (main_a7ddrphy_dfi_p3_cs_n),
+	.D8     (main_a7ddrphy_dfi_p3_cs_n),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_cs_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_3 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_3 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[0]),
-	.D2(a7ddrphy_dfi_p0_address[0]),
-	.D3(a7ddrphy_dfi_p1_address[0]),
-	.D4(a7ddrphy_dfi_p1_address[0]),
-	.D5(a7ddrphy_dfi_p2_address[0]),
-	.D6(a7ddrphy_dfi_p2_address[0]),
-	.D7(a7ddrphy_dfi_p3_address[0]),
-	.D8(a7ddrphy_dfi_p3_address[0]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[0])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[0]),
+	.D2     (main_a7ddrphy_dfi_p0_address[0]),
+	.D3     (main_a7ddrphy_dfi_p1_address[0]),
+	.D4     (main_a7ddrphy_dfi_p1_address[0]),
+	.D5     (main_a7ddrphy_dfi_p2_address[0]),
+	.D6     (main_a7ddrphy_dfi_p2_address[0]),
+	.D7     (main_a7ddrphy_dfi_p3_address[0]),
+	.D8     (main_a7ddrphy_dfi_p3_address[0]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_4 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_4 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[1]),
-	.D2(a7ddrphy_dfi_p0_address[1]),
-	.D3(a7ddrphy_dfi_p1_address[1]),
-	.D4(a7ddrphy_dfi_p1_address[1]),
-	.D5(a7ddrphy_dfi_p2_address[1]),
-	.D6(a7ddrphy_dfi_p2_address[1]),
-	.D7(a7ddrphy_dfi_p3_address[1]),
-	.D8(a7ddrphy_dfi_p3_address[1]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[1])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[1]),
+	.D2     (main_a7ddrphy_dfi_p0_address[1]),
+	.D3     (main_a7ddrphy_dfi_p1_address[1]),
+	.D4     (main_a7ddrphy_dfi_p1_address[1]),
+	.D5     (main_a7ddrphy_dfi_p2_address[1]),
+	.D6     (main_a7ddrphy_dfi_p2_address[1]),
+	.D7     (main_a7ddrphy_dfi_p3_address[1]),
+	.D8     (main_a7ddrphy_dfi_p3_address[1]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[1])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_5 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_5 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[2]),
-	.D2(a7ddrphy_dfi_p0_address[2]),
-	.D3(a7ddrphy_dfi_p1_address[2]),
-	.D4(a7ddrphy_dfi_p1_address[2]),
-	.D5(a7ddrphy_dfi_p2_address[2]),
-	.D6(a7ddrphy_dfi_p2_address[2]),
-	.D7(a7ddrphy_dfi_p3_address[2]),
-	.D8(a7ddrphy_dfi_p3_address[2]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[2])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[2]),
+	.D2     (main_a7ddrphy_dfi_p0_address[2]),
+	.D3     (main_a7ddrphy_dfi_p1_address[2]),
+	.D4     (main_a7ddrphy_dfi_p1_address[2]),
+	.D5     (main_a7ddrphy_dfi_p2_address[2]),
+	.D6     (main_a7ddrphy_dfi_p2_address[2]),
+	.D7     (main_a7ddrphy_dfi_p3_address[2]),
+	.D8     (main_a7ddrphy_dfi_p3_address[2]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[2])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_6 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_6 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[3]),
-	.D2(a7ddrphy_dfi_p0_address[3]),
-	.D3(a7ddrphy_dfi_p1_address[3]),
-	.D4(a7ddrphy_dfi_p1_address[3]),
-	.D5(a7ddrphy_dfi_p2_address[3]),
-	.D6(a7ddrphy_dfi_p2_address[3]),
-	.D7(a7ddrphy_dfi_p3_address[3]),
-	.D8(a7ddrphy_dfi_p3_address[3]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[3])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[3]),
+	.D2     (main_a7ddrphy_dfi_p0_address[3]),
+	.D3     (main_a7ddrphy_dfi_p1_address[3]),
+	.D4     (main_a7ddrphy_dfi_p1_address[3]),
+	.D5     (main_a7ddrphy_dfi_p2_address[3]),
+	.D6     (main_a7ddrphy_dfi_p2_address[3]),
+	.D7     (main_a7ddrphy_dfi_p3_address[3]),
+	.D8     (main_a7ddrphy_dfi_p3_address[3]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_7 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_7 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[4]),
-	.D2(a7ddrphy_dfi_p0_address[4]),
-	.D3(a7ddrphy_dfi_p1_address[4]),
-	.D4(a7ddrphy_dfi_p1_address[4]),
-	.D5(a7ddrphy_dfi_p2_address[4]),
-	.D6(a7ddrphy_dfi_p2_address[4]),
-	.D7(a7ddrphy_dfi_p3_address[4]),
-	.D8(a7ddrphy_dfi_p3_address[4]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[4])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[4]),
+	.D2     (main_a7ddrphy_dfi_p0_address[4]),
+	.D3     (main_a7ddrphy_dfi_p1_address[4]),
+	.D4     (main_a7ddrphy_dfi_p1_address[4]),
+	.D5     (main_a7ddrphy_dfi_p2_address[4]),
+	.D6     (main_a7ddrphy_dfi_p2_address[4]),
+	.D7     (main_a7ddrphy_dfi_p3_address[4]),
+	.D8     (main_a7ddrphy_dfi_p3_address[4]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[4])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_8 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_8 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[5]),
-	.D2(a7ddrphy_dfi_p0_address[5]),
-	.D3(a7ddrphy_dfi_p1_address[5]),
-	.D4(a7ddrphy_dfi_p1_address[5]),
-	.D5(a7ddrphy_dfi_p2_address[5]),
-	.D6(a7ddrphy_dfi_p2_address[5]),
-	.D7(a7ddrphy_dfi_p3_address[5]),
-	.D8(a7ddrphy_dfi_p3_address[5]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[5])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[5]),
+	.D2     (main_a7ddrphy_dfi_p0_address[5]),
+	.D3     (main_a7ddrphy_dfi_p1_address[5]),
+	.D4     (main_a7ddrphy_dfi_p1_address[5]),
+	.D5     (main_a7ddrphy_dfi_p2_address[5]),
+	.D6     (main_a7ddrphy_dfi_p2_address[5]),
+	.D7     (main_a7ddrphy_dfi_p3_address[5]),
+	.D8     (main_a7ddrphy_dfi_p3_address[5]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[5])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_9 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_9 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[6]),
-	.D2(a7ddrphy_dfi_p0_address[6]),
-	.D3(a7ddrphy_dfi_p1_address[6]),
-	.D4(a7ddrphy_dfi_p1_address[6]),
-	.D5(a7ddrphy_dfi_p2_address[6]),
-	.D6(a7ddrphy_dfi_p2_address[6]),
-	.D7(a7ddrphy_dfi_p3_address[6]),
-	.D8(a7ddrphy_dfi_p3_address[6]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[6])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[6]),
+	.D2     (main_a7ddrphy_dfi_p0_address[6]),
+	.D3     (main_a7ddrphy_dfi_p1_address[6]),
+	.D4     (main_a7ddrphy_dfi_p1_address[6]),
+	.D5     (main_a7ddrphy_dfi_p2_address[6]),
+	.D6     (main_a7ddrphy_dfi_p2_address[6]),
+	.D7     (main_a7ddrphy_dfi_p3_address[6]),
+	.D8     (main_a7ddrphy_dfi_p3_address[6]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[6])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_10 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_10 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[7]),
-	.D2(a7ddrphy_dfi_p0_address[7]),
-	.D3(a7ddrphy_dfi_p1_address[7]),
-	.D4(a7ddrphy_dfi_p1_address[7]),
-	.D5(a7ddrphy_dfi_p2_address[7]),
-	.D6(a7ddrphy_dfi_p2_address[7]),
-	.D7(a7ddrphy_dfi_p3_address[7]),
-	.D8(a7ddrphy_dfi_p3_address[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[7])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[7]),
+	.D2     (main_a7ddrphy_dfi_p0_address[7]),
+	.D3     (main_a7ddrphy_dfi_p1_address[7]),
+	.D4     (main_a7ddrphy_dfi_p1_address[7]),
+	.D5     (main_a7ddrphy_dfi_p2_address[7]),
+	.D6     (main_a7ddrphy_dfi_p2_address[7]),
+	.D7     (main_a7ddrphy_dfi_p3_address[7]),
+	.D8     (main_a7ddrphy_dfi_p3_address[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[7])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_11 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_11 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[8]),
-	.D2(a7ddrphy_dfi_p0_address[8]),
-	.D3(a7ddrphy_dfi_p1_address[8]),
-	.D4(a7ddrphy_dfi_p1_address[8]),
-	.D5(a7ddrphy_dfi_p2_address[8]),
-	.D6(a7ddrphy_dfi_p2_address[8]),
-	.D7(a7ddrphy_dfi_p3_address[8]),
-	.D8(a7ddrphy_dfi_p3_address[8]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[8])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[8]),
+	.D2     (main_a7ddrphy_dfi_p0_address[8]),
+	.D3     (main_a7ddrphy_dfi_p1_address[8]),
+	.D4     (main_a7ddrphy_dfi_p1_address[8]),
+	.D5     (main_a7ddrphy_dfi_p2_address[8]),
+	.D6     (main_a7ddrphy_dfi_p2_address[8]),
+	.D7     (main_a7ddrphy_dfi_p3_address[8]),
+	.D8     (main_a7ddrphy_dfi_p3_address[8]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[8])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_12 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_12 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[9]),
-	.D2(a7ddrphy_dfi_p0_address[9]),
-	.D3(a7ddrphy_dfi_p1_address[9]),
-	.D4(a7ddrphy_dfi_p1_address[9]),
-	.D5(a7ddrphy_dfi_p2_address[9]),
-	.D6(a7ddrphy_dfi_p2_address[9]),
-	.D7(a7ddrphy_dfi_p3_address[9]),
-	.D8(a7ddrphy_dfi_p3_address[9]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[9])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[9]),
+	.D2     (main_a7ddrphy_dfi_p0_address[9]),
+	.D3     (main_a7ddrphy_dfi_p1_address[9]),
+	.D4     (main_a7ddrphy_dfi_p1_address[9]),
+	.D5     (main_a7ddrphy_dfi_p2_address[9]),
+	.D6     (main_a7ddrphy_dfi_p2_address[9]),
+	.D7     (main_a7ddrphy_dfi_p3_address[9]),
+	.D8     (main_a7ddrphy_dfi_p3_address[9]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[9])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_13 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_13 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[10]),
-	.D2(a7ddrphy_dfi_p0_address[10]),
-	.D3(a7ddrphy_dfi_p1_address[10]),
-	.D4(a7ddrphy_dfi_p1_address[10]),
-	.D5(a7ddrphy_dfi_p2_address[10]),
-	.D6(a7ddrphy_dfi_p2_address[10]),
-	.D7(a7ddrphy_dfi_p3_address[10]),
-	.D8(a7ddrphy_dfi_p3_address[10]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[10])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[10]),
+	.D2     (main_a7ddrphy_dfi_p0_address[10]),
+	.D3     (main_a7ddrphy_dfi_p1_address[10]),
+	.D4     (main_a7ddrphy_dfi_p1_address[10]),
+	.D5     (main_a7ddrphy_dfi_p2_address[10]),
+	.D6     (main_a7ddrphy_dfi_p2_address[10]),
+	.D7     (main_a7ddrphy_dfi_p3_address[10]),
+	.D8     (main_a7ddrphy_dfi_p3_address[10]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[10])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_14 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_14 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[11]),
-	.D2(a7ddrphy_dfi_p0_address[11]),
-	.D3(a7ddrphy_dfi_p1_address[11]),
-	.D4(a7ddrphy_dfi_p1_address[11]),
-	.D5(a7ddrphy_dfi_p2_address[11]),
-	.D6(a7ddrphy_dfi_p2_address[11]),
-	.D7(a7ddrphy_dfi_p3_address[11]),
-	.D8(a7ddrphy_dfi_p3_address[11]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[11])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[11]),
+	.D2     (main_a7ddrphy_dfi_p0_address[11]),
+	.D3     (main_a7ddrphy_dfi_p1_address[11]),
+	.D4     (main_a7ddrphy_dfi_p1_address[11]),
+	.D5     (main_a7ddrphy_dfi_p2_address[11]),
+	.D6     (main_a7ddrphy_dfi_p2_address[11]),
+	.D7     (main_a7ddrphy_dfi_p3_address[11]),
+	.D8     (main_a7ddrphy_dfi_p3_address[11]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[11])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_15 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_15 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[12]),
-	.D2(a7ddrphy_dfi_p0_address[12]),
-	.D3(a7ddrphy_dfi_p1_address[12]),
-	.D4(a7ddrphy_dfi_p1_address[12]),
-	.D5(a7ddrphy_dfi_p2_address[12]),
-	.D6(a7ddrphy_dfi_p2_address[12]),
-	.D7(a7ddrphy_dfi_p3_address[12]),
-	.D8(a7ddrphy_dfi_p3_address[12]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[12])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[12]),
+	.D2     (main_a7ddrphy_dfi_p0_address[12]),
+	.D3     (main_a7ddrphy_dfi_p1_address[12]),
+	.D4     (main_a7ddrphy_dfi_p1_address[12]),
+	.D5     (main_a7ddrphy_dfi_p2_address[12]),
+	.D6     (main_a7ddrphy_dfi_p2_address[12]),
+	.D7     (main_a7ddrphy_dfi_p3_address[12]),
+	.D8     (main_a7ddrphy_dfi_p3_address[12]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[12])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_16 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_16 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[13]),
-	.D2(a7ddrphy_dfi_p0_address[13]),
-	.D3(a7ddrphy_dfi_p1_address[13]),
-	.D4(a7ddrphy_dfi_p1_address[13]),
-	.D5(a7ddrphy_dfi_p2_address[13]),
-	.D6(a7ddrphy_dfi_p2_address[13]),
-	.D7(a7ddrphy_dfi_p3_address[13]),
-	.D8(a7ddrphy_dfi_p3_address[13]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[13])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[13]),
+	.D2     (main_a7ddrphy_dfi_p0_address[13]),
+	.D3     (main_a7ddrphy_dfi_p1_address[13]),
+	.D4     (main_a7ddrphy_dfi_p1_address[13]),
+	.D5     (main_a7ddrphy_dfi_p2_address[13]),
+	.D6     (main_a7ddrphy_dfi_p2_address[13]),
+	.D7     (main_a7ddrphy_dfi_p3_address[13]),
+	.D8     (main_a7ddrphy_dfi_p3_address[13]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[13])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_17 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_17 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[14]),
-	.D2(a7ddrphy_dfi_p0_address[14]),
-	.D3(a7ddrphy_dfi_p1_address[14]),
-	.D4(a7ddrphy_dfi_p1_address[14]),
-	.D5(a7ddrphy_dfi_p2_address[14]),
-	.D6(a7ddrphy_dfi_p2_address[14]),
-	.D7(a7ddrphy_dfi_p3_address[14]),
-	.D8(a7ddrphy_dfi_p3_address[14]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[14])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[14]),
+	.D2     (main_a7ddrphy_dfi_p0_address[14]),
+	.D3     (main_a7ddrphy_dfi_p1_address[14]),
+	.D4     (main_a7ddrphy_dfi_p1_address[14]),
+	.D5     (main_a7ddrphy_dfi_p2_address[14]),
+	.D6     (main_a7ddrphy_dfi_p2_address[14]),
+	.D7     (main_a7ddrphy_dfi_p3_address[14]),
+	.D8     (main_a7ddrphy_dfi_p3_address[14]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[14])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_18 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_18 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_bank[0]),
-	.D2(a7ddrphy_dfi_p0_bank[0]),
-	.D3(a7ddrphy_dfi_p1_bank[0]),
-	.D4(a7ddrphy_dfi_p1_bank[0]),
-	.D5(a7ddrphy_dfi_p2_bank[0]),
-	.D6(a7ddrphy_dfi_p2_bank[0]),
-	.D7(a7ddrphy_dfi_p3_bank[0]),
-	.D8(a7ddrphy_dfi_p3_bank[0]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(a7ddrphy_pads_ba[0])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_bank[0]),
+	.D2     (main_a7ddrphy_dfi_p0_bank[0]),
+	.D3     (main_a7ddrphy_dfi_p1_bank[0]),
+	.D4     (main_a7ddrphy_dfi_p1_bank[0]),
+	.D5     (main_a7ddrphy_dfi_p2_bank[0]),
+	.D6     (main_a7ddrphy_dfi_p2_bank[0]),
+	.D7     (main_a7ddrphy_dfi_p3_bank[0]),
+	.D8     (main_a7ddrphy_dfi_p3_bank[0]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_pads_ba[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_19 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_19 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_bank[1]),
-	.D2(a7ddrphy_dfi_p0_bank[1]),
-	.D3(a7ddrphy_dfi_p1_bank[1]),
-	.D4(a7ddrphy_dfi_p1_bank[1]),
-	.D5(a7ddrphy_dfi_p2_bank[1]),
-	.D6(a7ddrphy_dfi_p2_bank[1]),
-	.D7(a7ddrphy_dfi_p3_bank[1]),
-	.D8(a7ddrphy_dfi_p3_bank[1]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(a7ddrphy_pads_ba[1])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_bank[1]),
+	.D2     (main_a7ddrphy_dfi_p0_bank[1]),
+	.D3     (main_a7ddrphy_dfi_p1_bank[1]),
+	.D4     (main_a7ddrphy_dfi_p1_bank[1]),
+	.D5     (main_a7ddrphy_dfi_p2_bank[1]),
+	.D6     (main_a7ddrphy_dfi_p2_bank[1]),
+	.D7     (main_a7ddrphy_dfi_p3_bank[1]),
+	.D8     (main_a7ddrphy_dfi_p3_bank[1]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_pads_ba[1])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_20 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_20 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_bank[2]),
-	.D2(a7ddrphy_dfi_p0_bank[2]),
-	.D3(a7ddrphy_dfi_p1_bank[2]),
-	.D4(a7ddrphy_dfi_p1_bank[2]),
-	.D5(a7ddrphy_dfi_p2_bank[2]),
-	.D6(a7ddrphy_dfi_p2_bank[2]),
-	.D7(a7ddrphy_dfi_p3_bank[2]),
-	.D8(a7ddrphy_dfi_p3_bank[2]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(a7ddrphy_pads_ba[2])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_bank[2]),
+	.D2     (main_a7ddrphy_dfi_p0_bank[2]),
+	.D3     (main_a7ddrphy_dfi_p1_bank[2]),
+	.D4     (main_a7ddrphy_dfi_p1_bank[2]),
+	.D5     (main_a7ddrphy_dfi_p2_bank[2]),
+	.D6     (main_a7ddrphy_dfi_p2_bank[2]),
+	.D7     (main_a7ddrphy_dfi_p3_bank[2]),
+	.D8     (main_a7ddrphy_dfi_p3_bank[2]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_pads_ba[2])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_21 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_21 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_ras_n),
-	.D2(a7ddrphy_dfi_p0_ras_n),
-	.D3(a7ddrphy_dfi_p1_ras_n),
-	.D4(a7ddrphy_dfi_p1_ras_n),
-	.D5(a7ddrphy_dfi_p2_ras_n),
-	.D6(a7ddrphy_dfi_p2_ras_n),
-	.D7(a7ddrphy_dfi_p3_ras_n),
-	.D8(a7ddrphy_dfi_p3_ras_n),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_ras_n)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_ras_n),
+	.D2     (main_a7ddrphy_dfi_p0_ras_n),
+	.D3     (main_a7ddrphy_dfi_p1_ras_n),
+	.D4     (main_a7ddrphy_dfi_p1_ras_n),
+	.D5     (main_a7ddrphy_dfi_p2_ras_n),
+	.D6     (main_a7ddrphy_dfi_p2_ras_n),
+	.D7     (main_a7ddrphy_dfi_p3_ras_n),
+	.D8     (main_a7ddrphy_dfi_p3_ras_n),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_ras_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_22 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_22 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_cas_n),
-	.D2(a7ddrphy_dfi_p0_cas_n),
-	.D3(a7ddrphy_dfi_p1_cas_n),
-	.D4(a7ddrphy_dfi_p1_cas_n),
-	.D5(a7ddrphy_dfi_p2_cas_n),
-	.D6(a7ddrphy_dfi_p2_cas_n),
-	.D7(a7ddrphy_dfi_p3_cas_n),
-	.D8(a7ddrphy_dfi_p3_cas_n),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_cas_n)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_cas_n),
+	.D2     (main_a7ddrphy_dfi_p0_cas_n),
+	.D3     (main_a7ddrphy_dfi_p1_cas_n),
+	.D4     (main_a7ddrphy_dfi_p1_cas_n),
+	.D5     (main_a7ddrphy_dfi_p2_cas_n),
+	.D6     (main_a7ddrphy_dfi_p2_cas_n),
+	.D7     (main_a7ddrphy_dfi_p3_cas_n),
+	.D8     (main_a7ddrphy_dfi_p3_cas_n),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_cas_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_23 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_23 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_we_n),
-	.D2(a7ddrphy_dfi_p0_we_n),
-	.D3(a7ddrphy_dfi_p1_we_n),
-	.D4(a7ddrphy_dfi_p1_we_n),
-	.D5(a7ddrphy_dfi_p2_we_n),
-	.D6(a7ddrphy_dfi_p2_we_n),
-	.D7(a7ddrphy_dfi_p3_we_n),
-	.D8(a7ddrphy_dfi_p3_we_n),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_we_n)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_we_n),
+	.D2     (main_a7ddrphy_dfi_p0_we_n),
+	.D3     (main_a7ddrphy_dfi_p1_we_n),
+	.D4     (main_a7ddrphy_dfi_p1_we_n),
+	.D5     (main_a7ddrphy_dfi_p2_we_n),
+	.D6     (main_a7ddrphy_dfi_p2_we_n),
+	.D7     (main_a7ddrphy_dfi_p3_we_n),
+	.D8     (main_a7ddrphy_dfi_p3_we_n),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_we_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_24 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_24 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_cke),
-	.D2(a7ddrphy_dfi_p0_cke),
-	.D3(a7ddrphy_dfi_p1_cke),
-	.D4(a7ddrphy_dfi_p1_cke),
-	.D5(a7ddrphy_dfi_p2_cke),
-	.D6(a7ddrphy_dfi_p2_cke),
-	.D7(a7ddrphy_dfi_p3_cke),
-	.D8(a7ddrphy_dfi_p3_cke),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_cke)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_cke),
+	.D2     (main_a7ddrphy_dfi_p0_cke),
+	.D3     (main_a7ddrphy_dfi_p1_cke),
+	.D4     (main_a7ddrphy_dfi_p1_cke),
+	.D5     (main_a7ddrphy_dfi_p2_cke),
+	.D6     (main_a7ddrphy_dfi_p2_cke),
+	.D7     (main_a7ddrphy_dfi_p3_cke),
+	.D8     (main_a7ddrphy_dfi_p3_cke),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_cke)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_25 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_25 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_odt),
-	.D2(a7ddrphy_dfi_p0_odt),
-	.D3(a7ddrphy_dfi_p1_odt),
-	.D4(a7ddrphy_dfi_p1_odt),
-	.D5(a7ddrphy_dfi_p2_odt),
-	.D6(a7ddrphy_dfi_p2_odt),
-	.D7(a7ddrphy_dfi_p3_odt),
-	.D8(a7ddrphy_dfi_p3_odt),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_odt)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_odt),
+	.D2     (main_a7ddrphy_dfi_p0_odt),
+	.D3     (main_a7ddrphy_dfi_p1_odt),
+	.D4     (main_a7ddrphy_dfi_p1_odt),
+	.D5     (main_a7ddrphy_dfi_p2_odt),
+	.D6     (main_a7ddrphy_dfi_p2_odt),
+	.D7     (main_a7ddrphy_dfi_p3_odt),
+	.D8     (main_a7ddrphy_dfi_p3_odt),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_odt)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_26 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_26 (
-	.CLK(sys4x_dqs_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip00[0]),
-	.D2(a7ddrphy_bitslip00[1]),
-	.D3(a7ddrphy_bitslip00[2]),
-	.D4(a7ddrphy_bitslip00[3]),
-	.D5(a7ddrphy_bitslip00[4]),
-	.D6(a7ddrphy_bitslip00[5]),
-	.D7(a7ddrphy_bitslip00[6]),
-	.D8(a7ddrphy_bitslip00[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OFB(a7ddrphy0),
-	.OQ(a7ddrphy_dqs_o_no_delay0),
-	.TQ(a7ddrphy_dqs_t0)
+	// Inputs.
+	.CLK    (sys4x_dqs_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip00[0]),
+	.D2     (main_a7ddrphy_bitslip00[1]),
+	.D3     (main_a7ddrphy_bitslip00[2]),
+	.D4     (main_a7ddrphy_bitslip00[3]),
+	.D5     (main_a7ddrphy_bitslip00[4]),
+	.D6     (main_a7ddrphy_bitslip00[5]),
+	.D7     (main_a7ddrphy_bitslip00[6]),
+	.D8     (main_a7ddrphy_bitslip00[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OFB    (main_a7ddrphy0),
+	.OQ     (main_a7ddrphy_dqs_o_no_delay0),
+	.TQ     (main_a7ddrphy_dqs_t0)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUFDS of IOBUFDS Module.
+//------------------------------------------------------------------------------
 IOBUFDS IOBUFDS(
-	.I(a7ddrphy_dqs_o_no_delay0),
-	.T(a7ddrphy_dqs_t0),
-	.IO(ddram_dqs_p[0]),
-	.IOB(ddram_dqs_n[0])
+	// Inputs.
+	.I   (main_a7ddrphy_dqs_o_no_delay0),
+	.T   (main_a7ddrphy_dqs_t0),
+
+	// InOuts.
+	.IO  (ddram_dqs_p[0]),
+	.IOB (ddram_dqs_n[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_27 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_27 (
-	.CLK(sys4x_dqs_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip10[0]),
-	.D2(a7ddrphy_bitslip10[1]),
-	.D3(a7ddrphy_bitslip10[2]),
-	.D4(a7ddrphy_bitslip10[3]),
-	.D5(a7ddrphy_bitslip10[4]),
-	.D6(a7ddrphy_bitslip10[5]),
-	.D7(a7ddrphy_bitslip10[6]),
-	.D8(a7ddrphy_bitslip10[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OFB(a7ddrphy1),
-	.OQ(a7ddrphy_dqs_o_no_delay1),
-	.TQ(a7ddrphy_dqs_t1)
-);
+	// Inputs.
+	.CLK    (sys4x_dqs_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip10[0]),
+	.D2     (main_a7ddrphy_bitslip10[1]),
+	.D3     (main_a7ddrphy_bitslip10[2]),
+	.D4     (main_a7ddrphy_bitslip10[3]),
+	.D5     (main_a7ddrphy_bitslip10[4]),
+	.D6     (main_a7ddrphy_bitslip10[5]),
+	.D7     (main_a7ddrphy_bitslip10[6]),
+	.D8     (main_a7ddrphy_bitslip10[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
 
-IOBUFDS IOBUFDS_1(
-	.I(a7ddrphy_dqs_o_no_delay1),
-	.T(a7ddrphy_dqs_t1),
-	.IO(ddram_dqs_p[1]),
-	.IOB(ddram_dqs_n[1])
+	// Outputs.
+	.OFB    (main_a7ddrphy1),
+	.OQ     (main_a7ddrphy_dqs_o_no_delay1),
+	.TQ     (main_a7ddrphy_dqs_t1)
 );
 
-OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+//------------------------------------------------------------------------------
+// Instance IOBUFDS_1 of IOBUFDS Module.
+//------------------------------------------------------------------------------
+IOBUFDS IOBUFDS_1(
+	// Inputs.
+	.I   (main_a7ddrphy_dqs_o_no_delay1),
+	.T   (main_a7ddrphy_dqs_t1),
+
+	// InOuts.
+	.IO  (ddram_dqs_p[1]),
+	.IOB (ddram_dqs_n[1])
+);
+
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_28 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
+OSERDESE2 #(
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_28 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip01[0]),
-	.D2(a7ddrphy_bitslip01[1]),
-	.D3(a7ddrphy_bitslip01[2]),
-	.D4(a7ddrphy_bitslip01[3]),
-	.D5(a7ddrphy_bitslip01[4]),
-	.D6(a7ddrphy_bitslip01[5]),
-	.D7(a7ddrphy_bitslip01[6]),
-	.D8(a7ddrphy_bitslip01[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_dm[0])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip01[0]),
+	.D2     (main_a7ddrphy_bitslip01[1]),
+	.D3     (main_a7ddrphy_bitslip01[2]),
+	.D4     (main_a7ddrphy_bitslip01[3]),
+	.D5     (main_a7ddrphy_bitslip01[4]),
+	.D6     (main_a7ddrphy_bitslip01[5]),
+	.D7     (main_a7ddrphy_bitslip01[6]),
+	.D8     (main_a7ddrphy_bitslip01[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_dm[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_29 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_29 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip11[0]),
-	.D2(a7ddrphy_bitslip11[1]),
-	.D3(a7ddrphy_bitslip11[2]),
-	.D4(a7ddrphy_bitslip11[3]),
-	.D5(a7ddrphy_bitslip11[4]),
-	.D6(a7ddrphy_bitslip11[5]),
-	.D7(a7ddrphy_bitslip11[6]),
-	.D8(a7ddrphy_bitslip11[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_dm[1])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip11[0]),
+	.D2     (main_a7ddrphy_bitslip11[1]),
+	.D3     (main_a7ddrphy_bitslip11[2]),
+	.D4     (main_a7ddrphy_bitslip11[3]),
+	.D5     (main_a7ddrphy_bitslip11[4]),
+	.D6     (main_a7ddrphy_bitslip11[5]),
+	.D7     (main_a7ddrphy_bitslip11[6]),
+	.D8     (main_a7ddrphy_bitslip11[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_dm[1])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_30 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_30 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip02[0]),
-	.D2(a7ddrphy_bitslip02[1]),
-	.D3(a7ddrphy_bitslip02[2]),
-	.D4(a7ddrphy_bitslip02[3]),
-	.D5(a7ddrphy_bitslip02[4]),
-	.D6(a7ddrphy_bitslip02[5]),
-	.D7(a7ddrphy_bitslip02[6]),
-	.D8(a7ddrphy_bitslip02[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay0),
-	.TQ(a7ddrphy_dq_t0)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip02[0]),
+	.D2     (main_a7ddrphy_bitslip02[1]),
+	.D3     (main_a7ddrphy_bitslip02[2]),
+	.D4     (main_a7ddrphy_bitslip02[3]),
+	.D5     (main_a7ddrphy_bitslip02[4]),
+	.D6     (main_a7ddrphy_bitslip02[5]),
+	.D7     (main_a7ddrphy_bitslip02[6]),
+	.D8     (main_a7ddrphy_bitslip02[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay0),
+	.TQ     (main_a7ddrphy_dq_t0)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed0),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip03[7]),
-	.Q2(a7ddrphy_bitslip03[6]),
-	.Q3(a7ddrphy_bitslip03[5]),
-	.Q4(a7ddrphy_bitslip03[4]),
-	.Q5(a7ddrphy_bitslip03[3]),
-	.Q6(a7ddrphy_bitslip03[2]),
-	.Q7(a7ddrphy_bitslip03[1]),
-	.Q8(a7ddrphy_bitslip03[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed0),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip03[7]),
+	.Q2      (main_a7ddrphy_bitslip03[6]),
+	.Q3      (main_a7ddrphy_bitslip03[5]),
+	.Q4      (main_a7ddrphy_bitslip03[4]),
+	.Q5      (main_a7ddrphy_bitslip03[3]),
+	.Q6      (main_a7ddrphy_bitslip03[2]),
+	.Q7      (main_a7ddrphy_bitslip03[1]),
+	.Q8      (main_a7ddrphy_bitslip03[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay0),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed0)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay0),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed0)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF(
-	.I(a7ddrphy_dq_o_nodelay0),
-	.T(a7ddrphy_dq_t0),
-	.IO(ddram_dq[0]),
-	.O(a7ddrphy_dq_i_nodelay0)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay0),
+	.T  (main_a7ddrphy_dq_t0),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay0),
+
+	// InOuts.
+	.IO (ddram_dq[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_31 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_31 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip12[0]),
-	.D2(a7ddrphy_bitslip12[1]),
-	.D3(a7ddrphy_bitslip12[2]),
-	.D4(a7ddrphy_bitslip12[3]),
-	.D5(a7ddrphy_bitslip12[4]),
-	.D6(a7ddrphy_bitslip12[5]),
-	.D7(a7ddrphy_bitslip12[6]),
-	.D8(a7ddrphy_bitslip12[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay1),
-	.TQ(a7ddrphy_dq_t1)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip12[0]),
+	.D2     (main_a7ddrphy_bitslip12[1]),
+	.D3     (main_a7ddrphy_bitslip12[2]),
+	.D4     (main_a7ddrphy_bitslip12[3]),
+	.D5     (main_a7ddrphy_bitslip12[4]),
+	.D6     (main_a7ddrphy_bitslip12[5]),
+	.D7     (main_a7ddrphy_bitslip12[6]),
+	.D8     (main_a7ddrphy_bitslip12[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay1),
+	.TQ     (main_a7ddrphy_dq_t1)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_1 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_1 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip13[7]),
-	.Q2(a7ddrphy_bitslip13[6]),
-	.Q3(a7ddrphy_bitslip13[5]),
-	.Q4(a7ddrphy_bitslip13[4]),
-	.Q5(a7ddrphy_bitslip13[3]),
-	.Q6(a7ddrphy_bitslip13[2]),
-	.Q7(a7ddrphy_bitslip13[1]),
-	.Q8(a7ddrphy_bitslip13[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed1),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip13[7]),
+	.Q2      (main_a7ddrphy_bitslip13[6]),
+	.Q3      (main_a7ddrphy_bitslip13[5]),
+	.Q4      (main_a7ddrphy_bitslip13[4]),
+	.Q5      (main_a7ddrphy_bitslip13[3]),
+	.Q6      (main_a7ddrphy_bitslip13[2]),
+	.Q7      (main_a7ddrphy_bitslip13[1]),
+	.Q8      (main_a7ddrphy_bitslip13[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_1 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_1 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay1),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed1)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay1),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed1)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_1 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_1(
-	.I(a7ddrphy_dq_o_nodelay1),
-	.T(a7ddrphy_dq_t1),
-	.IO(ddram_dq[1]),
-	.O(a7ddrphy_dq_i_nodelay1)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay1),
+	.T  (main_a7ddrphy_dq_t1),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay1),
+
+	// InOuts.
+	.IO (ddram_dq[1])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_32 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_32 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip20[0]),
-	.D2(a7ddrphy_bitslip20[1]),
-	.D3(a7ddrphy_bitslip20[2]),
-	.D4(a7ddrphy_bitslip20[3]),
-	.D5(a7ddrphy_bitslip20[4]),
-	.D6(a7ddrphy_bitslip20[5]),
-	.D7(a7ddrphy_bitslip20[6]),
-	.D8(a7ddrphy_bitslip20[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay2),
-	.TQ(a7ddrphy_dq_t2)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip20[0]),
+	.D2     (main_a7ddrphy_bitslip20[1]),
+	.D3     (main_a7ddrphy_bitslip20[2]),
+	.D4     (main_a7ddrphy_bitslip20[3]),
+	.D5     (main_a7ddrphy_bitslip20[4]),
+	.D6     (main_a7ddrphy_bitslip20[5]),
+	.D7     (main_a7ddrphy_bitslip20[6]),
+	.D8     (main_a7ddrphy_bitslip20[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay2),
+	.TQ     (main_a7ddrphy_dq_t2)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_2 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_2 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed2),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip21[7]),
-	.Q2(a7ddrphy_bitslip21[6]),
-	.Q3(a7ddrphy_bitslip21[5]),
-	.Q4(a7ddrphy_bitslip21[4]),
-	.Q5(a7ddrphy_bitslip21[3]),
-	.Q6(a7ddrphy_bitslip21[2]),
-	.Q7(a7ddrphy_bitslip21[1]),
-	.Q8(a7ddrphy_bitslip21[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed2),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip21[7]),
+	.Q2      (main_a7ddrphy_bitslip21[6]),
+	.Q3      (main_a7ddrphy_bitslip21[5]),
+	.Q4      (main_a7ddrphy_bitslip21[4]),
+	.Q5      (main_a7ddrphy_bitslip21[3]),
+	.Q6      (main_a7ddrphy_bitslip21[2]),
+	.Q7      (main_a7ddrphy_bitslip21[1]),
+	.Q8      (main_a7ddrphy_bitslip21[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_2 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_2 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay2),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed2)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay2),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed2)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_2 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_2(
-	.I(a7ddrphy_dq_o_nodelay2),
-	.T(a7ddrphy_dq_t2),
-	.IO(ddram_dq[2]),
-	.O(a7ddrphy_dq_i_nodelay2)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay2),
+	.T  (main_a7ddrphy_dq_t2),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay2),
+
+	// InOuts.
+	.IO (ddram_dq[2])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_33 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_33 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip30[0]),
-	.D2(a7ddrphy_bitslip30[1]),
-	.D3(a7ddrphy_bitslip30[2]),
-	.D4(a7ddrphy_bitslip30[3]),
-	.D5(a7ddrphy_bitslip30[4]),
-	.D6(a7ddrphy_bitslip30[5]),
-	.D7(a7ddrphy_bitslip30[6]),
-	.D8(a7ddrphy_bitslip30[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay3),
-	.TQ(a7ddrphy_dq_t3)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip30[0]),
+	.D2     (main_a7ddrphy_bitslip30[1]),
+	.D3     (main_a7ddrphy_bitslip30[2]),
+	.D4     (main_a7ddrphy_bitslip30[3]),
+	.D5     (main_a7ddrphy_bitslip30[4]),
+	.D6     (main_a7ddrphy_bitslip30[5]),
+	.D7     (main_a7ddrphy_bitslip30[6]),
+	.D8     (main_a7ddrphy_bitslip30[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay3),
+	.TQ     (main_a7ddrphy_dq_t3)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_3 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_3 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed3),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip31[7]),
-	.Q2(a7ddrphy_bitslip31[6]),
-	.Q3(a7ddrphy_bitslip31[5]),
-	.Q4(a7ddrphy_bitslip31[4]),
-	.Q5(a7ddrphy_bitslip31[3]),
-	.Q6(a7ddrphy_bitslip31[2]),
-	.Q7(a7ddrphy_bitslip31[1]),
-	.Q8(a7ddrphy_bitslip31[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed3),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip31[7]),
+	.Q2      (main_a7ddrphy_bitslip31[6]),
+	.Q3      (main_a7ddrphy_bitslip31[5]),
+	.Q4      (main_a7ddrphy_bitslip31[4]),
+	.Q5      (main_a7ddrphy_bitslip31[3]),
+	.Q6      (main_a7ddrphy_bitslip31[2]),
+	.Q7      (main_a7ddrphy_bitslip31[1]),
+	.Q8      (main_a7ddrphy_bitslip31[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_3 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_3 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay3),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed3)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay3),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed3)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_3 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_3(
-	.I(a7ddrphy_dq_o_nodelay3),
-	.T(a7ddrphy_dq_t3),
-	.IO(ddram_dq[3]),
-	.O(a7ddrphy_dq_i_nodelay3)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay3),
+	.T  (main_a7ddrphy_dq_t3),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay3),
+
+	// InOuts.
+	.IO (ddram_dq[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_34 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_34 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip40[0]),
-	.D2(a7ddrphy_bitslip40[1]),
-	.D3(a7ddrphy_bitslip40[2]),
-	.D4(a7ddrphy_bitslip40[3]),
-	.D5(a7ddrphy_bitslip40[4]),
-	.D6(a7ddrphy_bitslip40[5]),
-	.D7(a7ddrphy_bitslip40[6]),
-	.D8(a7ddrphy_bitslip40[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay4),
-	.TQ(a7ddrphy_dq_t4)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip40[0]),
+	.D2     (main_a7ddrphy_bitslip40[1]),
+	.D3     (main_a7ddrphy_bitslip40[2]),
+	.D4     (main_a7ddrphy_bitslip40[3]),
+	.D5     (main_a7ddrphy_bitslip40[4]),
+	.D6     (main_a7ddrphy_bitslip40[5]),
+	.D7     (main_a7ddrphy_bitslip40[6]),
+	.D8     (main_a7ddrphy_bitslip40[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay4),
+	.TQ     (main_a7ddrphy_dq_t4)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_4 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_4 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed4),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip41[7]),
-	.Q2(a7ddrphy_bitslip41[6]),
-	.Q3(a7ddrphy_bitslip41[5]),
-	.Q4(a7ddrphy_bitslip41[4]),
-	.Q5(a7ddrphy_bitslip41[3]),
-	.Q6(a7ddrphy_bitslip41[2]),
-	.Q7(a7ddrphy_bitslip41[1]),
-	.Q8(a7ddrphy_bitslip41[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed4),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip41[7]),
+	.Q2      (main_a7ddrphy_bitslip41[6]),
+	.Q3      (main_a7ddrphy_bitslip41[5]),
+	.Q4      (main_a7ddrphy_bitslip41[4]),
+	.Q5      (main_a7ddrphy_bitslip41[3]),
+	.Q6      (main_a7ddrphy_bitslip41[2]),
+	.Q7      (main_a7ddrphy_bitslip41[1]),
+	.Q8      (main_a7ddrphy_bitslip41[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_4 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_4 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay4),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed4)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay4),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed4)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_4 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_4(
-	.I(a7ddrphy_dq_o_nodelay4),
-	.T(a7ddrphy_dq_t4),
-	.IO(ddram_dq[4]),
-	.O(a7ddrphy_dq_i_nodelay4)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay4),
+	.T  (main_a7ddrphy_dq_t4),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay4),
+
+	// InOuts.
+	.IO (ddram_dq[4])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_35 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_35 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip50[0]),
-	.D2(a7ddrphy_bitslip50[1]),
-	.D3(a7ddrphy_bitslip50[2]),
-	.D4(a7ddrphy_bitslip50[3]),
-	.D5(a7ddrphy_bitslip50[4]),
-	.D6(a7ddrphy_bitslip50[5]),
-	.D7(a7ddrphy_bitslip50[6]),
-	.D8(a7ddrphy_bitslip50[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay5),
-	.TQ(a7ddrphy_dq_t5)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip50[0]),
+	.D2     (main_a7ddrphy_bitslip50[1]),
+	.D3     (main_a7ddrphy_bitslip50[2]),
+	.D4     (main_a7ddrphy_bitslip50[3]),
+	.D5     (main_a7ddrphy_bitslip50[4]),
+	.D6     (main_a7ddrphy_bitslip50[5]),
+	.D7     (main_a7ddrphy_bitslip50[6]),
+	.D8     (main_a7ddrphy_bitslip50[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay5),
+	.TQ     (main_a7ddrphy_dq_t5)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_5 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_5 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed5),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip51[7]),
-	.Q2(a7ddrphy_bitslip51[6]),
-	.Q3(a7ddrphy_bitslip51[5]),
-	.Q4(a7ddrphy_bitslip51[4]),
-	.Q5(a7ddrphy_bitslip51[3]),
-	.Q6(a7ddrphy_bitslip51[2]),
-	.Q7(a7ddrphy_bitslip51[1]),
-	.Q8(a7ddrphy_bitslip51[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed5),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip51[7]),
+	.Q2      (main_a7ddrphy_bitslip51[6]),
+	.Q3      (main_a7ddrphy_bitslip51[5]),
+	.Q4      (main_a7ddrphy_bitslip51[4]),
+	.Q5      (main_a7ddrphy_bitslip51[3]),
+	.Q6      (main_a7ddrphy_bitslip51[2]),
+	.Q7      (main_a7ddrphy_bitslip51[1]),
+	.Q8      (main_a7ddrphy_bitslip51[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_5 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_5 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay5),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed5)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay5),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed5)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_5 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_5(
-	.I(a7ddrphy_dq_o_nodelay5),
-	.T(a7ddrphy_dq_t5),
-	.IO(ddram_dq[5]),
-	.O(a7ddrphy_dq_i_nodelay5)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay5),
+	.T  (main_a7ddrphy_dq_t5),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay5),
+
+	// InOuts.
+	.IO (ddram_dq[5])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_36 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_36 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip60[0]),
-	.D2(a7ddrphy_bitslip60[1]),
-	.D3(a7ddrphy_bitslip60[2]),
-	.D4(a7ddrphy_bitslip60[3]),
-	.D5(a7ddrphy_bitslip60[4]),
-	.D6(a7ddrphy_bitslip60[5]),
-	.D7(a7ddrphy_bitslip60[6]),
-	.D8(a7ddrphy_bitslip60[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay6),
-	.TQ(a7ddrphy_dq_t6)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip60[0]),
+	.D2     (main_a7ddrphy_bitslip60[1]),
+	.D3     (main_a7ddrphy_bitslip60[2]),
+	.D4     (main_a7ddrphy_bitslip60[3]),
+	.D5     (main_a7ddrphy_bitslip60[4]),
+	.D6     (main_a7ddrphy_bitslip60[5]),
+	.D7     (main_a7ddrphy_bitslip60[6]),
+	.D8     (main_a7ddrphy_bitslip60[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay6),
+	.TQ     (main_a7ddrphy_dq_t6)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_6 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_6 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed6),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip61[7]),
-	.Q2(a7ddrphy_bitslip61[6]),
-	.Q3(a7ddrphy_bitslip61[5]),
-	.Q4(a7ddrphy_bitslip61[4]),
-	.Q5(a7ddrphy_bitslip61[3]),
-	.Q6(a7ddrphy_bitslip61[2]),
-	.Q7(a7ddrphy_bitslip61[1]),
-	.Q8(a7ddrphy_bitslip61[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed6),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip61[7]),
+	.Q2      (main_a7ddrphy_bitslip61[6]),
+	.Q3      (main_a7ddrphy_bitslip61[5]),
+	.Q4      (main_a7ddrphy_bitslip61[4]),
+	.Q5      (main_a7ddrphy_bitslip61[3]),
+	.Q6      (main_a7ddrphy_bitslip61[2]),
+	.Q7      (main_a7ddrphy_bitslip61[1]),
+	.Q8      (main_a7ddrphy_bitslip61[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_6 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_6 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay6),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed6)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay6),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed6)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_6 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_6(
-	.I(a7ddrphy_dq_o_nodelay6),
-	.T(a7ddrphy_dq_t6),
-	.IO(ddram_dq[6]),
-	.O(a7ddrphy_dq_i_nodelay6)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay6),
+	.T  (main_a7ddrphy_dq_t6),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay6),
+
+	// InOuts.
+	.IO (ddram_dq[6])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_37 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_37 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip70[0]),
-	.D2(a7ddrphy_bitslip70[1]),
-	.D3(a7ddrphy_bitslip70[2]),
-	.D4(a7ddrphy_bitslip70[3]),
-	.D5(a7ddrphy_bitslip70[4]),
-	.D6(a7ddrphy_bitslip70[5]),
-	.D7(a7ddrphy_bitslip70[6]),
-	.D8(a7ddrphy_bitslip70[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay7),
-	.TQ(a7ddrphy_dq_t7)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip70[0]),
+	.D2     (main_a7ddrphy_bitslip70[1]),
+	.D3     (main_a7ddrphy_bitslip70[2]),
+	.D4     (main_a7ddrphy_bitslip70[3]),
+	.D5     (main_a7ddrphy_bitslip70[4]),
+	.D6     (main_a7ddrphy_bitslip70[5]),
+	.D7     (main_a7ddrphy_bitslip70[6]),
+	.D8     (main_a7ddrphy_bitslip70[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay7),
+	.TQ     (main_a7ddrphy_dq_t7)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_7 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_7 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed7),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip71[7]),
-	.Q2(a7ddrphy_bitslip71[6]),
-	.Q3(a7ddrphy_bitslip71[5]),
-	.Q4(a7ddrphy_bitslip71[4]),
-	.Q5(a7ddrphy_bitslip71[3]),
-	.Q6(a7ddrphy_bitslip71[2]),
-	.Q7(a7ddrphy_bitslip71[1]),
-	.Q8(a7ddrphy_bitslip71[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed7),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip71[7]),
+	.Q2      (main_a7ddrphy_bitslip71[6]),
+	.Q3      (main_a7ddrphy_bitslip71[5]),
+	.Q4      (main_a7ddrphy_bitslip71[4]),
+	.Q5      (main_a7ddrphy_bitslip71[3]),
+	.Q6      (main_a7ddrphy_bitslip71[2]),
+	.Q7      (main_a7ddrphy_bitslip71[1]),
+	.Q8      (main_a7ddrphy_bitslip71[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_7 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_7 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay7),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed7)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay7),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed7)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_7 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_7(
-	.I(a7ddrphy_dq_o_nodelay7),
-	.T(a7ddrphy_dq_t7),
-	.IO(ddram_dq[7]),
-	.O(a7ddrphy_dq_i_nodelay7)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay7),
+	.T  (main_a7ddrphy_dq_t7),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay7),
+
+	// InOuts.
+	.IO (ddram_dq[7])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_38 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_38 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip80[0]),
-	.D2(a7ddrphy_bitslip80[1]),
-	.D3(a7ddrphy_bitslip80[2]),
-	.D4(a7ddrphy_bitslip80[3]),
-	.D5(a7ddrphy_bitslip80[4]),
-	.D6(a7ddrphy_bitslip80[5]),
-	.D7(a7ddrphy_bitslip80[6]),
-	.D8(a7ddrphy_bitslip80[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay8),
-	.TQ(a7ddrphy_dq_t8)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip80[0]),
+	.D2     (main_a7ddrphy_bitslip80[1]),
+	.D3     (main_a7ddrphy_bitslip80[2]),
+	.D4     (main_a7ddrphy_bitslip80[3]),
+	.D5     (main_a7ddrphy_bitslip80[4]),
+	.D6     (main_a7ddrphy_bitslip80[5]),
+	.D7     (main_a7ddrphy_bitslip80[6]),
+	.D8     (main_a7ddrphy_bitslip80[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay8),
+	.TQ     (main_a7ddrphy_dq_t8)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_8 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_8 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed8),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip81[7]),
-	.Q2(a7ddrphy_bitslip81[6]),
-	.Q3(a7ddrphy_bitslip81[5]),
-	.Q4(a7ddrphy_bitslip81[4]),
-	.Q5(a7ddrphy_bitslip81[3]),
-	.Q6(a7ddrphy_bitslip81[2]),
-	.Q7(a7ddrphy_bitslip81[1]),
-	.Q8(a7ddrphy_bitslip81[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed8),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip81[7]),
+	.Q2      (main_a7ddrphy_bitslip81[6]),
+	.Q3      (main_a7ddrphy_bitslip81[5]),
+	.Q4      (main_a7ddrphy_bitslip81[4]),
+	.Q5      (main_a7ddrphy_bitslip81[3]),
+	.Q6      (main_a7ddrphy_bitslip81[2]),
+	.Q7      (main_a7ddrphy_bitslip81[1]),
+	.Q8      (main_a7ddrphy_bitslip81[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_8 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_8 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay8),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed8)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay8),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed8)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_8 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_8(
-	.I(a7ddrphy_dq_o_nodelay8),
-	.T(a7ddrphy_dq_t8),
-	.IO(ddram_dq[8]),
-	.O(a7ddrphy_dq_i_nodelay8)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay8),
+	.T  (main_a7ddrphy_dq_t8),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay8),
+
+	// InOuts.
+	.IO (ddram_dq[8])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_39 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_39 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip90[0]),
-	.D2(a7ddrphy_bitslip90[1]),
-	.D3(a7ddrphy_bitslip90[2]),
-	.D4(a7ddrphy_bitslip90[3]),
-	.D5(a7ddrphy_bitslip90[4]),
-	.D6(a7ddrphy_bitslip90[5]),
-	.D7(a7ddrphy_bitslip90[6]),
-	.D8(a7ddrphy_bitslip90[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay9),
-	.TQ(a7ddrphy_dq_t9)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip90[0]),
+	.D2     (main_a7ddrphy_bitslip90[1]),
+	.D3     (main_a7ddrphy_bitslip90[2]),
+	.D4     (main_a7ddrphy_bitslip90[3]),
+	.D5     (main_a7ddrphy_bitslip90[4]),
+	.D6     (main_a7ddrphy_bitslip90[5]),
+	.D7     (main_a7ddrphy_bitslip90[6]),
+	.D8     (main_a7ddrphy_bitslip90[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay9),
+	.TQ     (main_a7ddrphy_dq_t9)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_9 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_9 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed9),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip91[7]),
-	.Q2(a7ddrphy_bitslip91[6]),
-	.Q3(a7ddrphy_bitslip91[5]),
-	.Q4(a7ddrphy_bitslip91[4]),
-	.Q5(a7ddrphy_bitslip91[3]),
-	.Q6(a7ddrphy_bitslip91[2]),
-	.Q7(a7ddrphy_bitslip91[1]),
-	.Q8(a7ddrphy_bitslip91[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed9),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip91[7]),
+	.Q2      (main_a7ddrphy_bitslip91[6]),
+	.Q3      (main_a7ddrphy_bitslip91[5]),
+	.Q4      (main_a7ddrphy_bitslip91[4]),
+	.Q5      (main_a7ddrphy_bitslip91[3]),
+	.Q6      (main_a7ddrphy_bitslip91[2]),
+	.Q7      (main_a7ddrphy_bitslip91[1]),
+	.Q8      (main_a7ddrphy_bitslip91[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_9 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_9 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay9),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed9)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay9),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed9)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_9 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_9(
-	.I(a7ddrphy_dq_o_nodelay9),
-	.T(a7ddrphy_dq_t9),
-	.IO(ddram_dq[9]),
-	.O(a7ddrphy_dq_i_nodelay9)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay9),
+	.T  (main_a7ddrphy_dq_t9),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay9),
+
+	// InOuts.
+	.IO (ddram_dq[9])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_40 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_40 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip100[0]),
-	.D2(a7ddrphy_bitslip100[1]),
-	.D3(a7ddrphy_bitslip100[2]),
-	.D4(a7ddrphy_bitslip100[3]),
-	.D5(a7ddrphy_bitslip100[4]),
-	.D6(a7ddrphy_bitslip100[5]),
-	.D7(a7ddrphy_bitslip100[6]),
-	.D8(a7ddrphy_bitslip100[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay10),
-	.TQ(a7ddrphy_dq_t10)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip100[0]),
+	.D2     (main_a7ddrphy_bitslip100[1]),
+	.D3     (main_a7ddrphy_bitslip100[2]),
+	.D4     (main_a7ddrphy_bitslip100[3]),
+	.D5     (main_a7ddrphy_bitslip100[4]),
+	.D6     (main_a7ddrphy_bitslip100[5]),
+	.D7     (main_a7ddrphy_bitslip100[6]),
+	.D8     (main_a7ddrphy_bitslip100[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay10),
+	.TQ     (main_a7ddrphy_dq_t10)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_10 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_10 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed10),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip101[7]),
-	.Q2(a7ddrphy_bitslip101[6]),
-	.Q3(a7ddrphy_bitslip101[5]),
-	.Q4(a7ddrphy_bitslip101[4]),
-	.Q5(a7ddrphy_bitslip101[3]),
-	.Q6(a7ddrphy_bitslip101[2]),
-	.Q7(a7ddrphy_bitslip101[1]),
-	.Q8(a7ddrphy_bitslip101[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed10),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip101[7]),
+	.Q2      (main_a7ddrphy_bitslip101[6]),
+	.Q3      (main_a7ddrphy_bitslip101[5]),
+	.Q4      (main_a7ddrphy_bitslip101[4]),
+	.Q5      (main_a7ddrphy_bitslip101[3]),
+	.Q6      (main_a7ddrphy_bitslip101[2]),
+	.Q7      (main_a7ddrphy_bitslip101[1]),
+	.Q8      (main_a7ddrphy_bitslip101[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_10 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_10 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay10),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed10)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay10),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed10)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_10 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_10(
-	.I(a7ddrphy_dq_o_nodelay10),
-	.T(a7ddrphy_dq_t10),
-	.IO(ddram_dq[10]),
-	.O(a7ddrphy_dq_i_nodelay10)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay10),
+	.T  (main_a7ddrphy_dq_t10),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay10),
+
+	// InOuts.
+	.IO (ddram_dq[10])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_41 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_41 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip110[0]),
-	.D2(a7ddrphy_bitslip110[1]),
-	.D3(a7ddrphy_bitslip110[2]),
-	.D4(a7ddrphy_bitslip110[3]),
-	.D5(a7ddrphy_bitslip110[4]),
-	.D6(a7ddrphy_bitslip110[5]),
-	.D7(a7ddrphy_bitslip110[6]),
-	.D8(a7ddrphy_bitslip110[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay11),
-	.TQ(a7ddrphy_dq_t11)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip110[0]),
+	.D2     (main_a7ddrphy_bitslip110[1]),
+	.D3     (main_a7ddrphy_bitslip110[2]),
+	.D4     (main_a7ddrphy_bitslip110[3]),
+	.D5     (main_a7ddrphy_bitslip110[4]),
+	.D6     (main_a7ddrphy_bitslip110[5]),
+	.D7     (main_a7ddrphy_bitslip110[6]),
+	.D8     (main_a7ddrphy_bitslip110[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay11),
+	.TQ     (main_a7ddrphy_dq_t11)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_11 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_11 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed11),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip111[7]),
-	.Q2(a7ddrphy_bitslip111[6]),
-	.Q3(a7ddrphy_bitslip111[5]),
-	.Q4(a7ddrphy_bitslip111[4]),
-	.Q5(a7ddrphy_bitslip111[3]),
-	.Q6(a7ddrphy_bitslip111[2]),
-	.Q7(a7ddrphy_bitslip111[1]),
-	.Q8(a7ddrphy_bitslip111[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed11),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip111[7]),
+	.Q2      (main_a7ddrphy_bitslip111[6]),
+	.Q3      (main_a7ddrphy_bitslip111[5]),
+	.Q4      (main_a7ddrphy_bitslip111[4]),
+	.Q5      (main_a7ddrphy_bitslip111[3]),
+	.Q6      (main_a7ddrphy_bitslip111[2]),
+	.Q7      (main_a7ddrphy_bitslip111[1]),
+	.Q8      (main_a7ddrphy_bitslip111[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_11 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_11 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay11),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed11)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay11),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed11)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_11 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_11(
-	.I(a7ddrphy_dq_o_nodelay11),
-	.T(a7ddrphy_dq_t11),
-	.IO(ddram_dq[11]),
-	.O(a7ddrphy_dq_i_nodelay11)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay11),
+	.T  (main_a7ddrphy_dq_t11),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay11),
+
+	// InOuts.
+	.IO (ddram_dq[11])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_42 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_42 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip120[0]),
-	.D2(a7ddrphy_bitslip120[1]),
-	.D3(a7ddrphy_bitslip120[2]),
-	.D4(a7ddrphy_bitslip120[3]),
-	.D5(a7ddrphy_bitslip120[4]),
-	.D6(a7ddrphy_bitslip120[5]),
-	.D7(a7ddrphy_bitslip120[6]),
-	.D8(a7ddrphy_bitslip120[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay12),
-	.TQ(a7ddrphy_dq_t12)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip120[0]),
+	.D2     (main_a7ddrphy_bitslip120[1]),
+	.D3     (main_a7ddrphy_bitslip120[2]),
+	.D4     (main_a7ddrphy_bitslip120[3]),
+	.D5     (main_a7ddrphy_bitslip120[4]),
+	.D6     (main_a7ddrphy_bitslip120[5]),
+	.D7     (main_a7ddrphy_bitslip120[6]),
+	.D8     (main_a7ddrphy_bitslip120[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay12),
+	.TQ     (main_a7ddrphy_dq_t12)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_12 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_12 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed12),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip121[7]),
-	.Q2(a7ddrphy_bitslip121[6]),
-	.Q3(a7ddrphy_bitslip121[5]),
-	.Q4(a7ddrphy_bitslip121[4]),
-	.Q5(a7ddrphy_bitslip121[3]),
-	.Q6(a7ddrphy_bitslip121[2]),
-	.Q7(a7ddrphy_bitslip121[1]),
-	.Q8(a7ddrphy_bitslip121[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed12),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip121[7]),
+	.Q2      (main_a7ddrphy_bitslip121[6]),
+	.Q3      (main_a7ddrphy_bitslip121[5]),
+	.Q4      (main_a7ddrphy_bitslip121[4]),
+	.Q5      (main_a7ddrphy_bitslip121[3]),
+	.Q6      (main_a7ddrphy_bitslip121[2]),
+	.Q7      (main_a7ddrphy_bitslip121[1]),
+	.Q8      (main_a7ddrphy_bitslip121[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_12 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_12 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay12),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed12)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay12),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed12)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_12 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_12(
-	.I(a7ddrphy_dq_o_nodelay12),
-	.T(a7ddrphy_dq_t12),
-	.IO(ddram_dq[12]),
-	.O(a7ddrphy_dq_i_nodelay12)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay12),
+	.T  (main_a7ddrphy_dq_t12),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay12),
+
+	// InOuts.
+	.IO (ddram_dq[12])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_43 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_43 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip130[0]),
-	.D2(a7ddrphy_bitslip130[1]),
-	.D3(a7ddrphy_bitslip130[2]),
-	.D4(a7ddrphy_bitslip130[3]),
-	.D5(a7ddrphy_bitslip130[4]),
-	.D6(a7ddrphy_bitslip130[5]),
-	.D7(a7ddrphy_bitslip130[6]),
-	.D8(a7ddrphy_bitslip130[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay13),
-	.TQ(a7ddrphy_dq_t13)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip130[0]),
+	.D2     (main_a7ddrphy_bitslip130[1]),
+	.D3     (main_a7ddrphy_bitslip130[2]),
+	.D4     (main_a7ddrphy_bitslip130[3]),
+	.D5     (main_a7ddrphy_bitslip130[4]),
+	.D6     (main_a7ddrphy_bitslip130[5]),
+	.D7     (main_a7ddrphy_bitslip130[6]),
+	.D8     (main_a7ddrphy_bitslip130[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay13),
+	.TQ     (main_a7ddrphy_dq_t13)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_13 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_13 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed13),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip131[7]),
-	.Q2(a7ddrphy_bitslip131[6]),
-	.Q3(a7ddrphy_bitslip131[5]),
-	.Q4(a7ddrphy_bitslip131[4]),
-	.Q5(a7ddrphy_bitslip131[3]),
-	.Q6(a7ddrphy_bitslip131[2]),
-	.Q7(a7ddrphy_bitslip131[1]),
-	.Q8(a7ddrphy_bitslip131[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed13),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip131[7]),
+	.Q2      (main_a7ddrphy_bitslip131[6]),
+	.Q3      (main_a7ddrphy_bitslip131[5]),
+	.Q4      (main_a7ddrphy_bitslip131[4]),
+	.Q5      (main_a7ddrphy_bitslip131[3]),
+	.Q6      (main_a7ddrphy_bitslip131[2]),
+	.Q7      (main_a7ddrphy_bitslip131[1]),
+	.Q8      (main_a7ddrphy_bitslip131[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_13 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_13 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay13),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed13)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay13),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed13)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_13 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_13(
-	.I(a7ddrphy_dq_o_nodelay13),
-	.T(a7ddrphy_dq_t13),
-	.IO(ddram_dq[13]),
-	.O(a7ddrphy_dq_i_nodelay13)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay13),
+	.T  (main_a7ddrphy_dq_t13),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay13),
+
+	// InOuts.
+	.IO (ddram_dq[13])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_44 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_44 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip140[0]),
-	.D2(a7ddrphy_bitslip140[1]),
-	.D3(a7ddrphy_bitslip140[2]),
-	.D4(a7ddrphy_bitslip140[3]),
-	.D5(a7ddrphy_bitslip140[4]),
-	.D6(a7ddrphy_bitslip140[5]),
-	.D7(a7ddrphy_bitslip140[6]),
-	.D8(a7ddrphy_bitslip140[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay14),
-	.TQ(a7ddrphy_dq_t14)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip140[0]),
+	.D2     (main_a7ddrphy_bitslip140[1]),
+	.D3     (main_a7ddrphy_bitslip140[2]),
+	.D4     (main_a7ddrphy_bitslip140[3]),
+	.D5     (main_a7ddrphy_bitslip140[4]),
+	.D6     (main_a7ddrphy_bitslip140[5]),
+	.D7     (main_a7ddrphy_bitslip140[6]),
+	.D8     (main_a7ddrphy_bitslip140[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay14),
+	.TQ     (main_a7ddrphy_dq_t14)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_14 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_14 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed14),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip141[7]),
-	.Q2(a7ddrphy_bitslip141[6]),
-	.Q3(a7ddrphy_bitslip141[5]),
-	.Q4(a7ddrphy_bitslip141[4]),
-	.Q5(a7ddrphy_bitslip141[3]),
-	.Q6(a7ddrphy_bitslip141[2]),
-	.Q7(a7ddrphy_bitslip141[1]),
-	.Q8(a7ddrphy_bitslip141[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed14),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip141[7]),
+	.Q2      (main_a7ddrphy_bitslip141[6]),
+	.Q3      (main_a7ddrphy_bitslip141[5]),
+	.Q4      (main_a7ddrphy_bitslip141[4]),
+	.Q5      (main_a7ddrphy_bitslip141[3]),
+	.Q6      (main_a7ddrphy_bitslip141[2]),
+	.Q7      (main_a7ddrphy_bitslip141[1]),
+	.Q8      (main_a7ddrphy_bitslip141[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_14 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_14 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay14),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed14)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay14),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed14)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_14 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_14(
-	.I(a7ddrphy_dq_o_nodelay14),
-	.T(a7ddrphy_dq_t14),
-	.IO(ddram_dq[14]),
-	.O(a7ddrphy_dq_i_nodelay14)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay14),
+	.T  (main_a7ddrphy_dq_t14),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay14),
+
+	// InOuts.
+	.IO (ddram_dq[14])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_45 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_45 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip150[0]),
-	.D2(a7ddrphy_bitslip150[1]),
-	.D3(a7ddrphy_bitslip150[2]),
-	.D4(a7ddrphy_bitslip150[3]),
-	.D5(a7ddrphy_bitslip150[4]),
-	.D6(a7ddrphy_bitslip150[5]),
-	.D7(a7ddrphy_bitslip150[6]),
-	.D8(a7ddrphy_bitslip150[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay15),
-	.TQ(a7ddrphy_dq_t15)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip150[0]),
+	.D2     (main_a7ddrphy_bitslip150[1]),
+	.D3     (main_a7ddrphy_bitslip150[2]),
+	.D4     (main_a7ddrphy_bitslip150[3]),
+	.D5     (main_a7ddrphy_bitslip150[4]),
+	.D6     (main_a7ddrphy_bitslip150[5]),
+	.D7     (main_a7ddrphy_bitslip150[6]),
+	.D8     (main_a7ddrphy_bitslip150[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay15),
+	.TQ     (main_a7ddrphy_dq_t15)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_15 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_15 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed15),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip151[7]),
-	.Q2(a7ddrphy_bitslip151[6]),
-	.Q3(a7ddrphy_bitslip151[5]),
-	.Q4(a7ddrphy_bitslip151[4]),
-	.Q5(a7ddrphy_bitslip151[3]),
-	.Q6(a7ddrphy_bitslip151[2]),
-	.Q7(a7ddrphy_bitslip151[1]),
-	.Q8(a7ddrphy_bitslip151[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed15),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip151[7]),
+	.Q2      (main_a7ddrphy_bitslip151[6]),
+	.Q3      (main_a7ddrphy_bitslip151[5]),
+	.Q4      (main_a7ddrphy_bitslip151[4]),
+	.Q5      (main_a7ddrphy_bitslip151[3]),
+	.Q6      (main_a7ddrphy_bitslip151[2]),
+	.Q7      (main_a7ddrphy_bitslip151[1]),
+	.Q8      (main_a7ddrphy_bitslip151[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_15 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_15 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay15),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed15)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay15),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed15)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_15 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_15(
-	.I(a7ddrphy_dq_o_nodelay15),
-	.T(a7ddrphy_dq_t15),
-	.IO(ddram_dq[15]),
-	.O(a7ddrphy_dq_i_nodelay15)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay15),
+	.T  (main_a7ddrphy_dq_t15),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay15),
+
+	// InOuts.
+	.IO (ddram_dq[15])
 );
 
 //------------------------------------------------------------------------------
@@ -16053,14 +17189,14 @@ IOBUF IOBUF_15(
 reg [24:0] storage[0:15];
 reg [24:0] storage_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine0_wrport_we)
-		storage[litedramcore_bankmachine0_wrport_adr] <= litedramcore_bankmachine0_wrport_dat_w;
-	storage_dat0 <= storage[litedramcore_bankmachine0_wrport_adr];
+	if (main_litedramcore_bankmachine0_wrport_we)
+		storage[main_litedramcore_bankmachine0_wrport_adr] <= main_litedramcore_bankmachine0_wrport_dat_w;
+	storage_dat0 <= storage[main_litedramcore_bankmachine0_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine0_wrport_dat_r = storage_dat0;
-assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine0_rdport_adr];
+assign main_litedramcore_bankmachine0_wrport_dat_r = storage_dat0;
+assign main_litedramcore_bankmachine0_rdport_dat_r = storage[main_litedramcore_bankmachine0_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16071,14 +17207,14 @@ assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine
 reg [24:0] storage_1[0:15];
 reg [24:0] storage_1_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine1_wrport_we)
-		storage_1[litedramcore_bankmachine1_wrport_adr] <= litedramcore_bankmachine1_wrport_dat_w;
-	storage_1_dat0 <= storage_1[litedramcore_bankmachine1_wrport_adr];
+	if (main_litedramcore_bankmachine1_wrport_we)
+		storage_1[main_litedramcore_bankmachine1_wrport_adr] <= main_litedramcore_bankmachine1_wrport_dat_w;
+	storage_1_dat0 <= storage_1[main_litedramcore_bankmachine1_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0;
-assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachine1_rdport_adr];
+assign main_litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0;
+assign main_litedramcore_bankmachine1_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16089,14 +17225,14 @@ assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachi
 reg [24:0] storage_2[0:15];
 reg [24:0] storage_2_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine2_wrport_we)
-		storage_2[litedramcore_bankmachine2_wrport_adr] <= litedramcore_bankmachine2_wrport_dat_w;
-	storage_2_dat0 <= storage_2[litedramcore_bankmachine2_wrport_adr];
+	if (main_litedramcore_bankmachine2_wrport_we)
+		storage_2[main_litedramcore_bankmachine2_wrport_adr] <= main_litedramcore_bankmachine2_wrport_dat_w;
+	storage_2_dat0 <= storage_2[main_litedramcore_bankmachine2_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0;
-assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachine2_rdport_adr];
+assign main_litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0;
+assign main_litedramcore_bankmachine2_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16107,14 +17243,14 @@ assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachi
 reg [24:0] storage_3[0:15];
 reg [24:0] storage_3_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine3_wrport_we)
-		storage_3[litedramcore_bankmachine3_wrport_adr] <= litedramcore_bankmachine3_wrport_dat_w;
-	storage_3_dat0 <= storage_3[litedramcore_bankmachine3_wrport_adr];
+	if (main_litedramcore_bankmachine3_wrport_we)
+		storage_3[main_litedramcore_bankmachine3_wrport_adr] <= main_litedramcore_bankmachine3_wrport_dat_w;
+	storage_3_dat0 <= storage_3[main_litedramcore_bankmachine3_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0;
-assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachine3_rdport_adr];
+assign main_litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0;
+assign main_litedramcore_bankmachine3_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16125,14 +17261,14 @@ assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachi
 reg [24:0] storage_4[0:15];
 reg [24:0] storage_4_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine4_wrport_we)
-		storage_4[litedramcore_bankmachine4_wrport_adr] <= litedramcore_bankmachine4_wrport_dat_w;
-	storage_4_dat0 <= storage_4[litedramcore_bankmachine4_wrport_adr];
+	if (main_litedramcore_bankmachine4_wrport_we)
+		storage_4[main_litedramcore_bankmachine4_wrport_adr] <= main_litedramcore_bankmachine4_wrport_dat_w;
+	storage_4_dat0 <= storage_4[main_litedramcore_bankmachine4_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0;
-assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachine4_rdport_adr];
+assign main_litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0;
+assign main_litedramcore_bankmachine4_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16143,14 +17279,14 @@ assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachi
 reg [24:0] storage_5[0:15];
 reg [24:0] storage_5_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine5_wrport_we)
-		storage_5[litedramcore_bankmachine5_wrport_adr] <= litedramcore_bankmachine5_wrport_dat_w;
-	storage_5_dat0 <= storage_5[litedramcore_bankmachine5_wrport_adr];
+	if (main_litedramcore_bankmachine5_wrport_we)
+		storage_5[main_litedramcore_bankmachine5_wrport_adr] <= main_litedramcore_bankmachine5_wrport_dat_w;
+	storage_5_dat0 <= storage_5[main_litedramcore_bankmachine5_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0;
-assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachine5_rdport_adr];
+assign main_litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0;
+assign main_litedramcore_bankmachine5_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16161,14 +17297,14 @@ assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachi
 reg [24:0] storage_6[0:15];
 reg [24:0] storage_6_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine6_wrport_we)
-		storage_6[litedramcore_bankmachine6_wrport_adr] <= litedramcore_bankmachine6_wrport_dat_w;
-	storage_6_dat0 <= storage_6[litedramcore_bankmachine6_wrport_adr];
+	if (main_litedramcore_bankmachine6_wrport_we)
+		storage_6[main_litedramcore_bankmachine6_wrport_adr] <= main_litedramcore_bankmachine6_wrport_dat_w;
+	storage_6_dat0 <= storage_6[main_litedramcore_bankmachine6_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0;
-assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachine6_rdport_adr];
+assign main_litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0;
+assign main_litedramcore_bankmachine6_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16179,197 +17315,308 @@ assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachi
 reg [24:0] storage_7[0:15];
 reg [24:0] storage_7_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine7_wrport_we)
-		storage_7[litedramcore_bankmachine7_wrport_adr] <= litedramcore_bankmachine7_wrport_dat_w;
-	storage_7_dat0 <= storage_7[litedramcore_bankmachine7_wrport_adr];
+	if (main_litedramcore_bankmachine7_wrport_we)
+		storage_7[main_litedramcore_bankmachine7_wrport_adr] <= main_litedramcore_bankmachine7_wrport_dat_w;
+	storage_7_dat0 <= storage_7[main_litedramcore_bankmachine7_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0;
-assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachine7_rdport_adr];
+assign main_litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0;
+assign main_litedramcore_bankmachine7_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_rdport_adr];
 
 
+//------------------------------------------------------------------------------
+// Instance FDCE of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(reset),
-	.Q(litedramcore_reset0)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (main_reset),
+
+	// Outputs.
+	.Q   (builder_reset0)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_1 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_1(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset0),
-	.Q(litedramcore_reset1)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset0),
+
+	// Outputs.
+	.Q   (builder_reset1)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_2 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_2(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset1),
-	.Q(litedramcore_reset2)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset1),
+
+	// Outputs.
+	.Q   (builder_reset2)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_3 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_3(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset2),
-	.Q(litedramcore_reset3)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset2),
+
+	// Outputs.
+	.Q   (builder_reset3)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_4 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_4(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset3),
-	.Q(litedramcore_reset4)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset3),
+
+	// Outputs.
+	.Q   (builder_reset4)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_5 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_5(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset4),
-	.Q(litedramcore_reset5)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset4),
+
+	// Outputs.
+	.Q   (builder_reset5)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_6 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_6(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset5),
-	.Q(litedramcore_reset6)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset5),
+
+	// Outputs.
+	.Q   (builder_reset6)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_7 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_7(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset6),
-	.Q(litedramcore_reset7)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset6),
+
+	// Outputs.
+	.Q   (builder_reset7)
 );
 
+//------------------------------------------------------------------------------
+// Instance PLLE2_ADV of PLLE2_ADV Module.
+//------------------------------------------------------------------------------
 PLLE2_ADV #(
-	.CLKFBOUT_MULT(5'd16),
-	.CLKIN1_PERIOD(10.0),
-	.CLKOUT0_DIVIDE(4'd8),
-	.CLKOUT0_PHASE(1'd0),
-	.CLKOUT1_DIVIDE(5'd16),
-	.CLKOUT1_PHASE(1'd0),
-	.CLKOUT2_DIVIDE(3'd4),
-	.CLKOUT2_PHASE(1'd0),
-	.CLKOUT3_DIVIDE(3'd4),
-	.CLKOUT3_PHASE(7'd90),
-	.DIVCLK_DIVIDE(1'd1),
-	.REF_JITTER1(0.01),
-	.STARTUP_WAIT("FALSE")
+	// Parameters.
+	.CLKFBOUT_MULT  (5'd16),
+	.CLKIN1_PERIOD  (10.0),
+	.CLKOUT0_DIVIDE (4'd8),
+	.CLKOUT0_PHASE  (1'd0),
+	.CLKOUT1_DIVIDE (5'd16),
+	.CLKOUT1_PHASE  (1'd0),
+	.CLKOUT2_DIVIDE (3'd4),
+	.CLKOUT2_PHASE  (1'd0),
+	.CLKOUT3_DIVIDE (3'd4),
+	.CLKOUT3_PHASE  (7'd90),
+	.DIVCLK_DIVIDE  (1'd1),
+	.REF_JITTER1    (0.01),
+	.STARTUP_WAIT   ("FALSE")
 ) PLLE2_ADV (
-	.CLKFBIN(litedramcore_pll_fb),
-	.CLKIN1(clkin),
-	.PWRDWN(power_down),
-	.RST(litedramcore_reset7),
-	.CLKFBOUT(litedramcore_pll_fb),
-	.CLKOUT0(clkout0),
-	.CLKOUT1(clkout1),
-	.CLKOUT2(clkout2),
-	.CLKOUT3(clkout3),
-	.LOCKED(locked)
+	// Inputs.
+	.CLKFBIN  (builder_pll_fb),
+	.CLKIN1   (main_clkin),
+	.PWRDWN   (main_power_down),
+	.RST      (builder_reset7),
+
+	// Outputs.
+	.CLKFBOUT (builder_pll_fb),
+	.CLKOUT0  (main_clkout0),
+	.CLKOUT1  (main_clkout1),
+	.CLKOUT2  (main_clkout2),
+	.CLKOUT3  (main_clkout3),
+	.LOCKED   (main_locked)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE (
-	.C(iodelay_clk),
-	.CE(1'd1),
-	.D(1'd0),
-	.PRE(xilinxasyncresetsynchronizerimpl0),
-	.Q(xilinxasyncresetsynchronizerimpl0_rst_meta)
+	// Inputs.
+	.C   (iodelay_clk),
+	.CE  (1'd1),
+	.D   (1'd0),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl0_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_1 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_1 (
-	.C(iodelay_clk),
-	.CE(1'd1),
-	.D(xilinxasyncresetsynchronizerimpl0_rst_meta),
-	.PRE(xilinxasyncresetsynchronizerimpl0),
-	.Q(iodelay_rst)
+	// Inputs.
+	.C   (iodelay_clk),
+	.CE  (1'd1),
+	.D   (builder_xilinxasyncresetsynchronizerimpl0_rst_meta),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset),
+
+	// Outputs.
+	.Q   (iodelay_rst)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_2 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_2 (
-	.C(sys_clk),
-	.CE(1'd1),
-	.D(1'd0),
-	.PRE(xilinxasyncresetsynchronizerimpl1),
-	.Q(xilinxasyncresetsynchronizerimpl1_rst_meta)
+	// Inputs.
+	.C   (sys_clk),
+	.CE  (1'd1),
+	.D   (1'd0),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl1_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_3 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_3 (
-	.C(sys_clk),
-	.CE(1'd1),
-	.D(xilinxasyncresetsynchronizerimpl1_rst_meta),
-	.PRE(xilinxasyncresetsynchronizerimpl1),
-	.Q(sys_rst)
+	// Inputs.
+	.C   (sys_clk),
+	.CE  (1'd1),
+	.D   (builder_xilinxasyncresetsynchronizerimpl1_rst_meta),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset),
+
+	// Outputs.
+	.Q   (sys_rst)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_4 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_4 (
-	.C(sys4x_clk),
-	.CE(1'd1),
-	.D(1'd0),
-	.PRE(xilinxasyncresetsynchronizerimpl2),
-	.Q(xilinxasyncresetsynchronizerimpl2_rst_meta)
+	// Inputs.
+	.C   (sys4x_clk),
+	.CE  (1'd1),
+	.D   (1'd0),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl2_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_5 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_5 (
-	.C(sys4x_clk),
-	.CE(1'd1),
-	.D(xilinxasyncresetsynchronizerimpl2_rst_meta),
-	.PRE(xilinxasyncresetsynchronizerimpl2),
-	.Q(xilinxasyncresetsynchronizerimpl2_expr)
+	// Inputs.
+	.C   (sys4x_clk),
+	.CE  (1'd1),
+	.D   (builder_xilinxasyncresetsynchronizerimpl2_rst_meta),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl2_expr)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_6 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_6 (
-	.C(sys4x_dqs_clk),
-	.CE(1'd1),
-	.D(1'd0),
-	.PRE(xilinxasyncresetsynchronizerimpl3),
-	.Q(xilinxasyncresetsynchronizerimpl3_rst_meta)
+	// Inputs.
+	.C   (sys4x_dqs_clk),
+	.CE  (1'd1),
+	.D   (1'd0),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl3_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_7 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_7 (
-	.C(sys4x_dqs_clk),
-	.CE(1'd1),
-	.D(xilinxasyncresetsynchronizerimpl3_rst_meta),
-	.PRE(xilinxasyncresetsynchronizerimpl3),
-	.Q(xilinxasyncresetsynchronizerimpl3_expr)
+	// Inputs.
+	.C   (sys4x_dqs_clk),
+	.CE  (1'd1),
+	.D   (builder_xilinxasyncresetsynchronizerimpl3_rst_meta),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl3_expr)
 );
 
 endmodule
 
 // -----------------------------------------------------------------------------
-//  Auto-Generated by LiteX on 2022-10-28 19:01:20.
+//  Auto-Generated by LiteX on 2024-04-01 10:12:07.
 //------------------------------------------------------------------------------
diff --git a/litedram/generated/orangecrab-85-0.2/litedram_core.init b/litedram/generated/orangecrab-85-0.2/litedram_core.init
index 2a3035b..51e4b9f 100644
--- a/litedram/generated/orangecrab-85-0.2/litedram_core.init
+++ b/litedram/generated/orangecrab-85-0.2/litedram_core.init
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 0000000000000000
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@@ -1915,6 +1913,8 @@ ebe1fff8e8010010
 52445320676e697a
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diff --git a/litedram/generated/orangecrab-85-0.2/litedram_core.v b/litedram/generated/orangecrab-85-0.2/litedram_core.v
index 3bd3682..f5dc552 100644
--- a/litedram/generated/orangecrab-85-0.2/litedram_core.v
+++ b/litedram/generated/orangecrab-85-0.2/litedram_core.v
@@ -8,10 +8,11 @@
 //
 // Filename   : litedram_core.v
 // Device     : LFE5U-85F-8MG285C
-// LiteX sha1 : --------
-// Date       : 2022-10-28 19:01:26
+// LiteX sha1 : 87137c30
+// Date       : 2024-04-01 10:12:11
 //------------------------------------------------------------------------------
 
+`timescale 1ns / 1ps
 
 //------------------------------------------------------------------------------
 // Module
@@ -19,160 +20,765 @@
 
 module litedram_core (
     input  wire          clk,
-    input  wire          rst,
-    output wire          pll_locked,
     output wire   [14:0] ddram_a,
     output wire    [2:0] ddram_ba,
-    output wire          ddram_ras_n,
     output wire          ddram_cas_n,
-    output wire          ddram_we_n,
+    output wire          ddram_cke,
+    input  wire          ddram_clk_n,
+    output wire          ddram_clk_p,
     output wire          ddram_cs_n,
     output wire    [1:0] ddram_dm,
     input  wire   [15:0] ddram_dq,
-    input  wire    [1:0] ddram_dqs_p,
     input  wire    [1:0] ddram_dqs_n,
-    output wire          ddram_clk_p,
-    input  wire          ddram_clk_n,
-    output wire          ddram_cke,
+    input  wire    [1:0] ddram_dqs_p,
     output wire          ddram_odt,
+    output wire          ddram_ras_n,
     output wire          ddram_reset_n,
+    output wire          ddram_we_n,
     output wire          init_done,
     output wire          init_error,
-    input  wire   [29:0] wb_ctrl_adr,
-    input  wire   [31:0] wb_ctrl_dat_w,
-    output wire   [31:0] wb_ctrl_dat_r,
-    input  wire    [3:0] wb_ctrl_sel,
-    input  wire          wb_ctrl_cyc,
-    input  wire          wb_ctrl_stb,
-    output wire          wb_ctrl_ack,
-    input  wire          wb_ctrl_we,
-    input  wire    [2:0] wb_ctrl_cti,
-    input  wire    [1:0] wb_ctrl_bte,
-    output wire          wb_ctrl_err,
+    output wire          pll_locked,
+    input  wire          rst,
     output wire          user_clk,
-    output wire          user_rst,
-    input  wire          user_port_native_0_cmd_valid,
+    input  wire   [24:0] user_port_native_0_cmd_addr,
     output wire          user_port_native_0_cmd_ready,
+    input  wire          user_port_native_0_cmd_valid,
     input  wire          user_port_native_0_cmd_we,
-    input  wire   [24:0] user_port_native_0_cmd_addr,
-    input  wire          user_port_native_0_wdata_valid,
+    output wire  [127:0] user_port_native_0_rdata_data,
+    input  wire          user_port_native_0_rdata_ready,
+    output wire          user_port_native_0_rdata_valid,
+    input  wire  [127:0] user_port_native_0_wdata_data,
     output wire          user_port_native_0_wdata_ready,
+    input  wire          user_port_native_0_wdata_valid,
     input  wire   [15:0] user_port_native_0_wdata_we,
-    input  wire  [127:0] user_port_native_0_wdata_data,
-    output wire          user_port_native_0_rdata_valid,
-    input  wire          user_port_native_0_rdata_ready,
-    output wire  [127:0] user_port_native_0_rdata_data
+    output wire          user_rst,
+    output wire          wb_ctrl_ack,
+    input  wire   [29:0] wb_ctrl_adr,
+    input  wire    [1:0] wb_ctrl_bte,
+    input  wire    [2:0] wb_ctrl_cti,
+    input  wire          wb_ctrl_cyc,
+    output wire   [31:0] wb_ctrl_dat_r,
+    input  wire   [31:0] wb_ctrl_dat_w,
+    output wire          wb_ctrl_err,
+    input  wire    [3:0] wb_ctrl_sel,
+    input  wire          wb_ctrl_stb,
+    input  wire          wb_ctrl_we
 );
 
 
+//------------------------------------------------------------------------------
+// Hierarchy
+//------------------------------------------------------------------------------
+
+/*
+LiteDRAMCore
+└─── bus (SoCBusHandler)
+│    └─── _interconnect (InterconnectPointToPoint)
+└─── csr (SoCCSRHandler)
+└─── irq (SoCIRQHandler)
+└─── cpu (CPUNone)
+└─── crg (LiteDRAMECP5DDRPHYCRG)
+│    └─── pll (ECP5PLL)
+│    │    └─── [EHXPLLL]
+│    └─── [ECLKSYNCB]
+│    └─── [CLKDIVF]
+│    └─── [ECLKBRIDGECS]
+└─── ddrphy (ECP5DDRPHY)
+│    └─── init (ECP5DDRPHYInit)
+│    │    └─── [DDRDLLA]
+│    └─── bitslip_0* (BitSlip)
+│    └─── bitslip_1* (BitSlip)
+│    └─── bitslip_2* (BitSlip)
+│    └─── bitslip_3* (BitSlip)
+│    └─── bitslip_4* (BitSlip)
+│    └─── bitslip_5* (BitSlip)
+│    └─── bitslip_6* (BitSlip)
+│    └─── bitslip_7* (BitSlip)
+│    └─── bitslip_8* (BitSlip)
+│    └─── bitslip_9* (BitSlip)
+│    └─── bitslip_10* (BitSlip)
+│    └─── bitslip_11* (BitSlip)
+│    └─── bitslip_12* (BitSlip)
+│    └─── bitslip_13* (BitSlip)
+│    └─── bitslip_14* (BitSlip)
+│    └─── bitslip_15* (BitSlip)
+│    └─── tappeddelayline_0* (TappedDelayLine)
+│    └─── tappeddelayline_1* (TappedDelayLine)
+│    └─── [TSHX2DQA]
+│    └─── [ODDRX2F]
+│    └─── [TSHX2DQA]
+│    └─── [DELAYG]
+│    └─── [ODDRX2F]
+│    └─── [DELAYG]
+│    └─── [DELAYG]
+│    └─── [ODDRX2F]
+│    └─── [DELAYG]
+│    └─── [TSHX2DQA]
+│    └─── [TSHX2DQA]
+│    └─── [ODDRX2DQSB]
+│    └─── [ODDRX2F]
+│    └─── [DELAYG]
+│    └─── [DELAYG]
+│    └─── [TSHX2DQA]
+│    └─── [ODDRX2DQA]
+│    └─── [ODDRX2F]
+│    └─── [TSHX2DQA]
+│    └─── [DELAYG]
+│    └─── [DELAYG]
+│    └─── [TSHX2DQA]
+│    └─── [ODDRX2DQA]
+│    └─── [ODDRX2F]
+│    └─── [ODDRX2DQA]
+│    └─── [ODDRX2DQA]
+│    └─── [ODDRX2DQA]
+│    └─── [ODDRX2F]
+│    └─── [DELAYG]
+│    └─── [ODDRX2DQA]
+│    └─── [DELAYG]
+│    └─── [DELAYG]
+│    └─── [DELAYG]
+│    └─── [ODDRX2DQA]
+│    └─── [IDDRX2DQA]
+│    └─── [ODDRX2DQA]
+│    └─── [ODDRX2F]
+│    └─── [ODDRX2F]
+│    └─── [DELAYG]
+│    └─── [IDDRX2DQA]
+│    └─── [TSHX2DQSA]
+│    └─── [DELAYG]
+│    └─── [IDDRX2DQA]
+│    └─── [IDDRX2DQA]
+│    └─── [ODDRX2DQA]
+│    └─── [IDDRX2DQA]
+│    └─── [DELAYG]
+│    └─── [DELAYG]
+│    └─── [IDDRX2DQA]
+│    └─── [DQSBUFM]
+│    └─── [DELAYG]
+│    └─── [DELAYG]
+│    └─── [DELAYG]
+│    └─── [ODDRX2F]
+│    └─── [ODDRX2F]
+│    └─── [ODDRX2DQA]
+│    └─── [TSHX2DQA]
+│    └─── [DELAYG]
+│    └─── [IDDRX2DQA]
+│    └─── [TSHX2DQSA]
+│    └─── [DELAYG]
+│    └─── [DELAYG]
+│    └─── [IDDRX2DQA]
+│    └─── [TSHX2DQA]
+│    └─── [TSHX2DQA]
+│    └─── [ODDRX2F]
+│    └─── [DELAYG]
+│    └─── [DELAYG]
+│    └─── [DELAYG]
+│    └─── [ODDRX2F]
+│    └─── [TSHX2DQA]
+│    └─── [TSHX2DQA]
+│    └─── [DELAYG]
+│    └─── [ODDRX2DQA]
+│    └─── [IDDRX2DQA]
+│    └─── [ODDRX2F]
+│    └─── [TSHX2DQA]
+│    └─── [DELAYG]
+│    └─── [TSHX2DQA]
+│    └─── [ODDRX2DQA]
+│    └─── [ODDRX2DQA]
+│    └─── [ODDRX2F]
+│    └─── [ODDRX2F]
+│    └─── [ODDRX2F]
+│    └─── [ODDRX2DQA]
+│    └─── [ODDRX2DQA]
+│    └─── [TSHX2DQA]
+│    └─── [ODDRX2F]
+│    └─── [ODDRX2DQA]
+│    └─── [IDDRX2DQA]
+│    └─── [ODDRX2F]
+│    └─── [ODDRX2DQA]
+│    └─── [DELAYG]
+│    └─── [ODDRX2F]
+│    └─── [DELAYG]
+│    └─── [DELAYG]
+│    └─── [IDDRX2DQA]
+│    └─── [ODDRX2F]
+│    └─── [IDDRX2DQA]
+│    └─── [DELAYG]
+│    └─── [DELAYG]
+│    └─── [IDDRX2DQA]
+│    └─── [ODDRX2DQA]
+│    └─── [ODDRX2F]
+│    └─── [ODDRX2F]
+│    └─── [DELAYG]
+│    └─── [ODDRX2F]
+│    └─── [DELAYG]
+│    └─── [ODDRX2DQSB]
+│    └─── [IDDRX2DQA]
+│    └─── [DELAYG]
+│    └─── [IDDRX2DQA]
+│    └─── [ODDRX2F]
+│    └─── [ODDRX2F]
+│    └─── [DELAYG]
+│    └─── [TSHX2DQA]
+│    └─── [DQSBUFM]
+│    └─── [IDDRX2DQA]
+│    └─── [DELAYG]
+│    └─── [DELAYG]
+│    └─── [DELAYG]
+│    └─── [DELAYG]
+│    └─── [DELAYG]
+│    └─── [DELAYG]
+└─── sdram (LiteDRAMCore)
+│    └─── dfii (DFIInjector)
+│    │    └─── pi0 (PhaseInjector)
+│    │    └─── pi1 (PhaseInjector)
+│    └─── controller (LiteDRAMController)
+│    │    └─── refresher (Refresher)
+│    │    │    └─── timer (RefreshTimer)
+│    │    │    └─── postponer (RefreshPostponer)
+│    │    │    └─── sequencer (RefreshSequencer)
+│    │    │    │    └─── refreshexecuter_0* (RefreshExecuter)
+│    │    │    └─── zqcs_timer (RefreshTimer)
+│    │    │    └─── zqs_executer (ZQCSExecuter)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_0* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_1* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_2* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_3* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_4* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_5* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_6* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_7* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── multiplexer (Multiplexer)
+│    │    │    └─── choose_cmd (_CommandChooser)
+│    │    │    │    └─── roundrobin_0* (RoundRobin)
+│    │    │    └─── choose_req (_CommandChooser)
+│    │    │    │    └─── roundrobin_0* (RoundRobin)
+│    │    │    └─── _steerer_0* (_Steerer)
+│    │    │    └─── trrdcon (tXXDController)
+│    │    │    └─── tfawcon (tFAWController)
+│    │    │    └─── tccdcon (tXXDController)
+│    │    │    └─── twtrcon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    └─── crossbar (LiteDRAMCrossbar)
+│    │    └─── roundrobin_0* (RoundRobin)
+│    │    └─── roundrobin_1* (RoundRobin)
+│    │    └─── roundrobin_2* (RoundRobin)
+│    │    └─── roundrobin_3* (RoundRobin)
+│    │    └─── roundrobin_4* (RoundRobin)
+│    │    └─── roundrobin_5* (RoundRobin)
+│    │    └─── roundrobin_6* (RoundRobin)
+│    │    └─── roundrobin_7* (RoundRobin)
+└─── ddrctrl (LiteDRAMCoreControl)
+└─── csr_bridge (Wishbone2CSR)
+│    └─── fsm (FSM)
+└─── csr_bankarray (CSRBankArray)
+│    └─── csrbank_0* (CSRBank)
+│    │    └─── csrstorage_0* (CSRStorage)
+│    │    └─── csrstorage_1* (CSRStorage)
+│    └─── csrbank_1* (CSRBank)
+│    │    └─── csrstorage_0* (CSRStorage)
+│    │    └─── csrstatus_0* (CSRStatus)
+│    └─── csrbank_2* (CSRBank)
+│    │    └─── csrstorage_0* (CSRStorage)
+│    │    └─── csrstorage_1* (CSRStorage)
+│    │    └─── csrstorage_2* (CSRStorage)
+│    │    └─── csrstorage_3* (CSRStorage)
+│    │    └─── csrstorage_4* (CSRStorage)
+│    │    └─── csrstatus_0* (CSRStatus)
+│    │    └─── csrstorage_5* (CSRStorage)
+│    │    └─── csrstorage_6* (CSRStorage)
+│    │    └─── csrstorage_7* (CSRStorage)
+│    │    └─── csrstorage_8* (CSRStorage)
+│    │    └─── csrstatus_1* (CSRStatus)
+└─── csr_interconnect (InterconnectShared)
+└─── [FD1S3BX]
+└─── [FD1S3BX]
+└─── [TRELLIS_IO]
+└─── [TRELLIS_IO]
+└─── [TRELLIS_IO]
+└─── [TRELLIS_IO]
+└─── [FD1S3BX]
+└─── [FD1S3BX]
+└─── [TRELLIS_IO]
+└─── [TRELLIS_IO]
+└─── [TRELLIS_IO]
+└─── [FD1S3BX]
+└─── [FD1S3BX]
+└─── [TRELLIS_IO]
+└─── [TRELLIS_IO]
+└─── [FD1S3BX]
+└─── [TRELLIS_IO]
+└─── [FD1S3BX]
+└─── [TRELLIS_IO]
+└─── [TRELLIS_IO]
+└─── [TRELLIS_IO]
+└─── [TRELLIS_IO]
+└─── [TRELLIS_IO]
+└─── [TRELLIS_IO]
+└─── [TRELLIS_IO]
+└─── [TRELLIS_IO]
+* : Generated name.
+[]: BlackBox.
+*/
+
 //------------------------------------------------------------------------------
 // Signals
 //------------------------------------------------------------------------------
 
-reg           crg_rst = 1'd0;
-wire          init_clk;
-wire          init_rst;
-wire          por_clk;
-wire          sys_clk;
-wire          sys_rst;
-wire          sys2x_clk;
-wire          sys2x_rst;
-wire          sys2x_i_clk;
-wire          crg_stop;
-wire          crg_reset0;
+wire   [13:0] adr;
+wire          crg_clkin;
+wire          crg_clkout0;
+wire          crg_clkout1;
+wire          crg_locked;
 reg    [15:0] crg_por_count = 16'd65535;
 wire          crg_por_done;
-wire          crg_sys2x_clk_ecsout;
+wire          crg_reset0;
 wire          crg_reset1;
-wire          crg_locked;
+reg           crg_rst = 1'd0;
 reg           crg_stdby = 1'd0;
-wire          crg_clkin;
-wire          crg_clkout0;
-wire          crg_clkout1;
-wire          ddrphy_pause0;
-wire          ddrphy_stop0;
-wire          ddrphy_delay0;
-wire          ddrphy_reset0;
-wire          ddrphy_new_lock;
-reg           ddrphy_update = 1'd0;
-reg           ddrphy_stop1 = 1'd0;
-reg           ddrphy_freeze = 1'd0;
-reg           ddrphy_pause1 = 1'd0;
-reg           ddrphy_reset1 = 1'd0;
-wire          ddrphy_lock0;
-wire          ddrphy_delay1;
-wire          ddrphy_lock1;
-reg           ddrphy_lock_d = 1'd0;
-reg     [6:0] ddrphy_counter = 7'd0;
-reg     [1:0] ddrphy_dly_sel_storage = 2'd0;
-reg           ddrphy_dly_sel_re = 1'd0;
-reg           ddrphy_rdly_dq_rst_re = 1'd0;
-wire          ddrphy_rdly_dq_rst_r;
-reg           ddrphy_rdly_dq_rst_we = 1'd0;
-reg           ddrphy_rdly_dq_rst_w = 1'd0;
-reg           ddrphy_rdly_dq_inc_re = 1'd0;
-wire          ddrphy_rdly_dq_inc_r;
-reg           ddrphy_rdly_dq_inc_we = 1'd0;
-reg           ddrphy_rdly_dq_inc_w = 1'd0;
-reg           ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
-wire          ddrphy_rdly_dq_bitslip_rst_r;
-reg           ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
-reg           ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-reg           ddrphy_rdly_dq_bitslip_re = 1'd0;
-wire          ddrphy_rdly_dq_bitslip_r;
-reg           ddrphy_rdly_dq_bitslip_we = 1'd0;
-reg           ddrphy_rdly_dq_bitslip_w = 1'd0;
-reg           ddrphy_burstdet_clr_re = 1'd0;
+wire          crg_stop;
+wire          crg_sys2x_clk_ecsout;
+wire          csrbank0_init_done0_r;
+reg           csrbank0_init_done0_re = 1'd0;
+wire          csrbank0_init_done0_w;
+reg           csrbank0_init_done0_we = 1'd0;
+wire          csrbank0_init_error0_r;
+reg           csrbank0_init_error0_re = 1'd0;
+wire          csrbank0_init_error0_w;
+reg           csrbank0_init_error0_we = 1'd0;
+wire          csrbank0_sel;
+wire    [1:0] csrbank1_burstdet_seen_r;
+reg           csrbank1_burstdet_seen_re = 1'd0;
+wire    [1:0] csrbank1_burstdet_seen_w;
+reg           csrbank1_burstdet_seen_we = 1'd0;
+wire    [1:0] csrbank1_dly_sel0_r;
+reg           csrbank1_dly_sel0_re = 1'd0;
+wire    [1:0] csrbank1_dly_sel0_w;
+reg           csrbank1_dly_sel0_we = 1'd0;
+wire          csrbank1_sel;
+wire    [3:0] csrbank2_dfii_control0_r;
+reg           csrbank2_dfii_control0_re = 1'd0;
+wire    [3:0] csrbank2_dfii_control0_w;
+reg           csrbank2_dfii_control0_we = 1'd0;
+wire   [14:0] csrbank2_dfii_pi0_address0_r;
+reg           csrbank2_dfii_pi0_address0_re = 1'd0;
+wire   [14:0] csrbank2_dfii_pi0_address0_w;
+reg           csrbank2_dfii_pi0_address0_we = 1'd0;
+wire    [2:0] csrbank2_dfii_pi0_baddress0_r;
+reg           csrbank2_dfii_pi0_baddress0_re = 1'd0;
+wire    [2:0] csrbank2_dfii_pi0_baddress0_w;
+reg           csrbank2_dfii_pi0_baddress0_we = 1'd0;
+wire    [7:0] csrbank2_dfii_pi0_command0_r;
+reg           csrbank2_dfii_pi0_command0_re = 1'd0;
+wire    [7:0] csrbank2_dfii_pi0_command0_w;
+reg           csrbank2_dfii_pi0_command0_we = 1'd0;
+wire   [31:0] csrbank2_dfii_pi0_rddata0_r;
+reg           csrbank2_dfii_pi0_rddata0_re = 1'd0;
+wire   [31:0] csrbank2_dfii_pi0_rddata0_w;
+reg           csrbank2_dfii_pi0_rddata0_we = 1'd0;
+wire   [31:0] csrbank2_dfii_pi0_rddata1_r;
+reg           csrbank2_dfii_pi0_rddata1_re = 1'd0;
+wire   [31:0] csrbank2_dfii_pi0_rddata1_w;
+reg           csrbank2_dfii_pi0_rddata1_we = 1'd0;
+wire   [31:0] csrbank2_dfii_pi0_wrdata0_r;
+reg           csrbank2_dfii_pi0_wrdata0_re = 1'd0;
+wire   [31:0] csrbank2_dfii_pi0_wrdata0_w;
+reg           csrbank2_dfii_pi0_wrdata0_we = 1'd0;
+wire   [31:0] csrbank2_dfii_pi0_wrdata1_r;
+reg           csrbank2_dfii_pi0_wrdata1_re = 1'd0;
+wire   [31:0] csrbank2_dfii_pi0_wrdata1_w;
+reg           csrbank2_dfii_pi0_wrdata1_we = 1'd0;
+wire   [14:0] csrbank2_dfii_pi1_address0_r;
+reg           csrbank2_dfii_pi1_address0_re = 1'd0;
+wire   [14:0] csrbank2_dfii_pi1_address0_w;
+reg           csrbank2_dfii_pi1_address0_we = 1'd0;
+wire    [2:0] csrbank2_dfii_pi1_baddress0_r;
+reg           csrbank2_dfii_pi1_baddress0_re = 1'd0;
+wire    [2:0] csrbank2_dfii_pi1_baddress0_w;
+reg           csrbank2_dfii_pi1_baddress0_we = 1'd0;
+wire    [7:0] csrbank2_dfii_pi1_command0_r;
+reg           csrbank2_dfii_pi1_command0_re = 1'd0;
+wire    [7:0] csrbank2_dfii_pi1_command0_w;
+reg           csrbank2_dfii_pi1_command0_we = 1'd0;
+wire   [31:0] csrbank2_dfii_pi1_rddata0_r;
+reg           csrbank2_dfii_pi1_rddata0_re = 1'd0;
+wire   [31:0] csrbank2_dfii_pi1_rddata0_w;
+reg           csrbank2_dfii_pi1_rddata0_we = 1'd0;
+wire   [31:0] csrbank2_dfii_pi1_rddata1_r;
+reg           csrbank2_dfii_pi1_rddata1_re = 1'd0;
+wire   [31:0] csrbank2_dfii_pi1_rddata1_w;
+reg           csrbank2_dfii_pi1_rddata1_we = 1'd0;
+wire   [31:0] csrbank2_dfii_pi1_wrdata0_r;
+reg           csrbank2_dfii_pi1_wrdata0_re = 1'd0;
+wire   [31:0] csrbank2_dfii_pi1_wrdata0_w;
+reg           csrbank2_dfii_pi1_wrdata0_we = 1'd0;
+wire   [31:0] csrbank2_dfii_pi1_wrdata1_r;
+reg           csrbank2_dfii_pi1_wrdata1_re = 1'd0;
+wire   [31:0] csrbank2_dfii_pi1_wrdata1_w;
+reg           csrbank2_dfii_pi1_wrdata1_we = 1'd0;
+wire          csrbank2_sel;
+wire   [31:0] dat_r;
+wire   [31:0] dat_w;
+wire    [3:0] ddrphy_bitslip0_i;
+reg     [3:0] ddrphy_bitslip0_o = 4'd0;
+reg     [7:0] ddrphy_bitslip0_r = 8'd0;
+reg     [1:0] ddrphy_bitslip0_value = 2'd0;
+wire    [3:0] ddrphy_bitslip10_i;
+reg     [3:0] ddrphy_bitslip10_o = 4'd0;
+reg     [7:0] ddrphy_bitslip10_r = 8'd0;
+reg     [1:0] ddrphy_bitslip10_value = 2'd0;
+wire    [3:0] ddrphy_bitslip11_i;
+reg     [3:0] ddrphy_bitslip11_o = 4'd0;
+reg     [7:0] ddrphy_bitslip11_r = 8'd0;
+reg     [1:0] ddrphy_bitslip11_value = 2'd0;
+wire    [3:0] ddrphy_bitslip12_i;
+reg     [3:0] ddrphy_bitslip12_o = 4'd0;
+reg     [7:0] ddrphy_bitslip12_r = 8'd0;
+reg     [1:0] ddrphy_bitslip12_value = 2'd0;
+wire    [3:0] ddrphy_bitslip13_i;
+reg     [3:0] ddrphy_bitslip13_o = 4'd0;
+reg     [7:0] ddrphy_bitslip13_r = 8'd0;
+reg     [1:0] ddrphy_bitslip13_value = 2'd0;
+wire    [3:0] ddrphy_bitslip14_i;
+reg     [3:0] ddrphy_bitslip14_o = 4'd0;
+reg     [7:0] ddrphy_bitslip14_r = 8'd0;
+reg     [1:0] ddrphy_bitslip14_value = 2'd0;
+wire    [3:0] ddrphy_bitslip15_i;
+reg     [3:0] ddrphy_bitslip15_o = 4'd0;
+reg     [7:0] ddrphy_bitslip15_r = 8'd0;
+reg     [1:0] ddrphy_bitslip15_value = 2'd0;
+wire    [3:0] ddrphy_bitslip1_i;
+reg     [3:0] ddrphy_bitslip1_o = 4'd0;
+reg     [7:0] ddrphy_bitslip1_r = 8'd0;
+reg     [1:0] ddrphy_bitslip1_value = 2'd0;
+wire    [3:0] ddrphy_bitslip2_i;
+reg     [3:0] ddrphy_bitslip2_o = 4'd0;
+reg     [7:0] ddrphy_bitslip2_r = 8'd0;
+reg     [1:0] ddrphy_bitslip2_value = 2'd0;
+wire    [3:0] ddrphy_bitslip3_i;
+reg     [3:0] ddrphy_bitslip3_o = 4'd0;
+reg     [7:0] ddrphy_bitslip3_r = 8'd0;
+reg     [1:0] ddrphy_bitslip3_value = 2'd0;
+wire    [3:0] ddrphy_bitslip4_i;
+reg     [3:0] ddrphy_bitslip4_o = 4'd0;
+reg     [7:0] ddrphy_bitslip4_r = 8'd0;
+reg     [1:0] ddrphy_bitslip4_value = 2'd0;
+wire    [3:0] ddrphy_bitslip5_i;
+reg     [3:0] ddrphy_bitslip5_o = 4'd0;
+reg     [7:0] ddrphy_bitslip5_r = 8'd0;
+reg     [1:0] ddrphy_bitslip5_value = 2'd0;
+wire    [3:0] ddrphy_bitslip6_i;
+reg     [3:0] ddrphy_bitslip6_o = 4'd0;
+reg     [7:0] ddrphy_bitslip6_r = 8'd0;
+reg     [1:0] ddrphy_bitslip6_value = 2'd0;
+wire    [3:0] ddrphy_bitslip7_i;
+reg     [3:0] ddrphy_bitslip7_o = 4'd0;
+reg     [7:0] ddrphy_bitslip7_r = 8'd0;
+reg     [1:0] ddrphy_bitslip7_value = 2'd0;
+wire    [3:0] ddrphy_bitslip8_i;
+reg     [3:0] ddrphy_bitslip8_o = 4'd0;
+reg     [7:0] ddrphy_bitslip8_r = 8'd0;
+reg     [1:0] ddrphy_bitslip8_value = 2'd0;
+wire    [3:0] ddrphy_bitslip9_i;
+reg     [3:0] ddrphy_bitslip9_o = 4'd0;
+reg     [7:0] ddrphy_bitslip9_r = 8'd0;
+reg     [1:0] ddrphy_bitslip9_value = 2'd0;
+wire          ddrphy_bl8_chunk;
+wire          ddrphy_burstdet0;
+wire          ddrphy_burstdet1;
 wire          ddrphy_burstdet_clr_r;
-reg           ddrphy_burstdet_clr_we = 1'd0;
+reg           ddrphy_burstdet_clr_re = 1'd0;
 reg           ddrphy_burstdet_clr_w = 1'd0;
-reg     [1:0] ddrphy_burstdet_seen_status = 2'd0;
-wire          ddrphy_burstdet_seen_we;
+reg           ddrphy_burstdet_clr_we = 1'd0;
+reg           ddrphy_burstdet_d0 = 1'd0;
+reg           ddrphy_burstdet_d1 = 1'd0;
 reg           ddrphy_burstdet_seen_re = 1'd0;
+reg     [1:0] ddrphy_burstdet_seen_status = 2'd0;
+wire          ddrphy_burstdet_seen_we;
 wire    [1:0] ddrphy_datavalid;
+wire          ddrphy_delay0;
+wire          ddrphy_delay1;
+wire          ddrphy_dfi_p0_act_n;
 wire   [14:0] ddrphy_dfi_p0_address;
 wire    [2:0] ddrphy_dfi_p0_bank;
 wire          ddrphy_dfi_p0_cas_n;
-wire          ddrphy_dfi_p0_cs_n;
-wire          ddrphy_dfi_p0_ras_n;
-wire          ddrphy_dfi_p0_we_n;
 wire          ddrphy_dfi_p0_cke;
+wire          ddrphy_dfi_p0_cs_n;
 wire          ddrphy_dfi_p0_odt;
+wire          ddrphy_dfi_p0_ras_n;
+reg    [63:0] ddrphy_dfi_p0_rddata = 64'd0;
+wire          ddrphy_dfi_p0_rddata_en;
+wire          ddrphy_dfi_p0_rddata_valid;
 wire          ddrphy_dfi_p0_reset_n;
-wire          ddrphy_dfi_p0_act_n;
+wire          ddrphy_dfi_p0_we_n;
 wire   [63:0] ddrphy_dfi_p0_wrdata;
 wire          ddrphy_dfi_p0_wrdata_en;
 wire    [7:0] ddrphy_dfi_p0_wrdata_mask;
-wire          ddrphy_dfi_p0_rddata_en;
-reg    [63:0] ddrphy_dfi_p0_rddata = 64'd0;
-wire          ddrphy_dfi_p0_rddata_valid;
+wire          ddrphy_dfi_p1_act_n;
 wire   [14:0] ddrphy_dfi_p1_address;
 wire    [2:0] ddrphy_dfi_p1_bank;
 wire          ddrphy_dfi_p1_cas_n;
-wire          ddrphy_dfi_p1_cs_n;
-wire          ddrphy_dfi_p1_ras_n;
-wire          ddrphy_dfi_p1_we_n;
 wire          ddrphy_dfi_p1_cke;
+wire          ddrphy_dfi_p1_cs_n;
 wire          ddrphy_dfi_p1_odt;
+wire          ddrphy_dfi_p1_ras_n;
+reg    [63:0] ddrphy_dfi_p1_rddata = 64'd0;
+wire          ddrphy_dfi_p1_rddata_en;
+wire          ddrphy_dfi_p1_rddata_valid;
 wire          ddrphy_dfi_p1_reset_n;
-wire          ddrphy_dfi_p1_act_n;
+wire          ddrphy_dfi_p1_we_n;
 wire   [63:0] ddrphy_dfi_p1_wrdata;
 wire          ddrphy_dfi_p1_wrdata_en;
 wire    [7:0] ddrphy_dfi_p1_wrdata_mask;
-wire          ddrphy_dfi_p1_rddata_en;
-reg    [63:0] ddrphy_dfi_p1_rddata = 64'd0;
-wire          ddrphy_dfi_p1_rddata_valid;
-wire          ddrphy_bl8_chunk;
+reg           ddrphy_dly_sel_re = 1'd0;
+reg     [1:0] ddrphy_dly_sel_storage = 2'd0;
+reg     [7:0] ddrphy_dm_o_data0 = 8'd0;
+reg     [7:0] ddrphy_dm_o_data1 = 8'd0;
+reg     [7:0] ddrphy_dm_o_data_d0 = 8'd0;
+reg     [7:0] ddrphy_dm_o_data_d1 = 8'd0;
+reg     [3:0] ddrphy_dm_o_data_muxed0 = 4'd0;
+reg     [3:0] ddrphy_dm_o_data_muxed1 = 4'd0;
+wire          ddrphy_dq_i0;
+wire          ddrphy_dq_i1;
+wire          ddrphy_dq_i10;
+wire          ddrphy_dq_i11;
+wire          ddrphy_dq_i12;
+wire          ddrphy_dq_i13;
+wire          ddrphy_dq_i14;
+wire          ddrphy_dq_i15;
+wire          ddrphy_dq_i2;
+wire          ddrphy_dq_i3;
+wire          ddrphy_dq_i4;
+wire          ddrphy_dq_i5;
+wire          ddrphy_dq_i6;
+wire          ddrphy_dq_i7;
+wire          ddrphy_dq_i8;
+wire          ddrphy_dq_i9;
+reg     [3:0] ddrphy_dq_i_bitslip_o_d0 = 4'd0;
+reg     [3:0] ddrphy_dq_i_bitslip_o_d1 = 4'd0;
+reg     [3:0] ddrphy_dq_i_bitslip_o_d10 = 4'd0;
+reg     [3:0] ddrphy_dq_i_bitslip_o_d11 = 4'd0;
+reg     [3:0] ddrphy_dq_i_bitslip_o_d12 = 4'd0;
+reg     [3:0] ddrphy_dq_i_bitslip_o_d13 = 4'd0;
+reg     [3:0] ddrphy_dq_i_bitslip_o_d14 = 4'd0;
+reg     [3:0] ddrphy_dq_i_bitslip_o_d15 = 4'd0;
+reg     [3:0] ddrphy_dq_i_bitslip_o_d2 = 4'd0;
+reg     [3:0] ddrphy_dq_i_bitslip_o_d3 = 4'd0;
+reg     [3:0] ddrphy_dq_i_bitslip_o_d4 = 4'd0;
+reg     [3:0] ddrphy_dq_i_bitslip_o_d5 = 4'd0;
+reg     [3:0] ddrphy_dq_i_bitslip_o_d6 = 4'd0;
+reg     [3:0] ddrphy_dq_i_bitslip_o_d7 = 4'd0;
+reg     [3:0] ddrphy_dq_i_bitslip_o_d8 = 4'd0;
+reg     [3:0] ddrphy_dq_i_bitslip_o_d9 = 4'd0;
+wire    [7:0] ddrphy_dq_i_data0;
+wire    [7:0] ddrphy_dq_i_data1;
+wire    [7:0] ddrphy_dq_i_data10;
+wire    [7:0] ddrphy_dq_i_data11;
+wire    [7:0] ddrphy_dq_i_data12;
+wire    [7:0] ddrphy_dq_i_data13;
+wire    [7:0] ddrphy_dq_i_data14;
+wire    [7:0] ddrphy_dq_i_data15;
+wire    [7:0] ddrphy_dq_i_data2;
+wire    [7:0] ddrphy_dq_i_data3;
+wire    [7:0] ddrphy_dq_i_data4;
+wire    [7:0] ddrphy_dq_i_data5;
+wire    [7:0] ddrphy_dq_i_data6;
+wire    [7:0] ddrphy_dq_i_data7;
+wire    [7:0] ddrphy_dq_i_data8;
+wire    [7:0] ddrphy_dq_i_data9;
+wire          ddrphy_dq_i_delayed0;
+wire          ddrphy_dq_i_delayed1;
+wire          ddrphy_dq_i_delayed10;
+wire          ddrphy_dq_i_delayed11;
+wire          ddrphy_dq_i_delayed12;
+wire          ddrphy_dq_i_delayed13;
+wire          ddrphy_dq_i_delayed14;
+wire          ddrphy_dq_i_delayed15;
+wire          ddrphy_dq_i_delayed2;
+wire          ddrphy_dq_i_delayed3;
+wire          ddrphy_dq_i_delayed4;
+wire          ddrphy_dq_i_delayed5;
+wire          ddrphy_dq_i_delayed6;
+wire          ddrphy_dq_i_delayed7;
+wire          ddrphy_dq_i_delayed8;
+wire          ddrphy_dq_i_delayed9;
+wire          ddrphy_dq_o0;
+wire          ddrphy_dq_o1;
+wire          ddrphy_dq_o10;
+wire          ddrphy_dq_o11;
+wire          ddrphy_dq_o12;
+wire          ddrphy_dq_o13;
+wire          ddrphy_dq_o14;
+wire          ddrphy_dq_o15;
+wire          ddrphy_dq_o2;
+wire          ddrphy_dq_o3;
+wire          ddrphy_dq_o4;
+wire          ddrphy_dq_o5;
+wire          ddrphy_dq_o6;
+wire          ddrphy_dq_o7;
+wire          ddrphy_dq_o8;
+wire          ddrphy_dq_o9;
+reg     [7:0] ddrphy_dq_o_data0 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data1 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data10 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data11 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data12 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data13 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data14 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data15 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data2 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data3 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data4 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data5 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data6 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data7 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data8 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data9 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data_d0 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data_d1 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data_d10 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data_d11 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data_d12 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data_d13 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data_d14 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data_d15 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data_d2 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data_d3 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data_d4 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data_d5 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data_d6 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data_d7 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data_d8 = 8'd0;
+reg     [7:0] ddrphy_dq_o_data_d9 = 8'd0;
+reg     [3:0] ddrphy_dq_o_data_muxed0 = 4'd0;
+reg     [3:0] ddrphy_dq_o_data_muxed1 = 4'd0;
+reg     [3:0] ddrphy_dq_o_data_muxed10 = 4'd0;
+reg     [3:0] ddrphy_dq_o_data_muxed11 = 4'd0;
+reg     [3:0] ddrphy_dq_o_data_muxed12 = 4'd0;
+reg     [3:0] ddrphy_dq_o_data_muxed13 = 4'd0;
+reg     [3:0] ddrphy_dq_o_data_muxed14 = 4'd0;
+reg     [3:0] ddrphy_dq_o_data_muxed15 = 4'd0;
+reg     [3:0] ddrphy_dq_o_data_muxed2 = 4'd0;
+reg     [3:0] ddrphy_dq_o_data_muxed3 = 4'd0;
+reg     [3:0] ddrphy_dq_o_data_muxed4 = 4'd0;
+reg     [3:0] ddrphy_dq_o_data_muxed5 = 4'd0;
+reg     [3:0] ddrphy_dq_o_data_muxed6 = 4'd0;
+reg     [3:0] ddrphy_dq_o_data_muxed7 = 4'd0;
+reg     [3:0] ddrphy_dq_o_data_muxed8 = 4'd0;
+reg     [3:0] ddrphy_dq_o_data_muxed9 = 4'd0;
+wire          ddrphy_dq_oe;
+wire          ddrphy_dq_oe_n0;
+wire          ddrphy_dq_oe_n1;
+wire          ddrphy_dq_oe_n10;
+wire          ddrphy_dq_oe_n11;
+wire          ddrphy_dq_oe_n12;
+wire          ddrphy_dq_oe_n13;
+wire          ddrphy_dq_oe_n14;
+wire          ddrphy_dq_oe_n15;
+wire          ddrphy_dq_oe_n2;
+wire          ddrphy_dq_oe_n3;
+wire          ddrphy_dq_oe_n4;
+wire          ddrphy_dq_oe_n5;
+wire          ddrphy_dq_oe_n6;
+wire          ddrphy_dq_oe_n7;
+wire          ddrphy_dq_oe_n8;
+wire          ddrphy_dq_oe_n9;
+wire          ddrphy_dqs0;
+wire          ddrphy_dqs1;
+wire          ddrphy_dqs_i0;
+wire          ddrphy_dqs_i1;
+wire          ddrphy_dqs_oe;
+wire          ddrphy_dqs_oe_n0;
+wire          ddrphy_dqs_oe_n1;
+wire          ddrphy_dqs_postamble;
+wire          ddrphy_dqs_preamble;
+wire          ddrphy_dqs_re;
+wire          ddrphy_dqsr900;
+wire          ddrphy_dqsr901;
+wire          ddrphy_dqsw0;
+wire          ddrphy_dqsw1;
+wire          ddrphy_dqsw2700;
+wire          ddrphy_dqsw2701;
+reg           ddrphy_freeze = 1'd0;
+wire          ddrphy_lock0;
+wire          ddrphy_lock1;
+reg           ddrphy_lock_d = 1'd0;
+wire          ddrphy_new_lock;
 wire          ddrphy_pad_oddrx2f0;
 wire          ddrphy_pad_oddrx2f1;
-wire          ddrphy_pad_oddrx2f2;
-wire          ddrphy_pad_oddrx2f3;
-wire          ddrphy_pad_oddrx2f4;
-wire          ddrphy_pad_oddrx2f5;
-wire          ddrphy_pad_oddrx2f6;
-wire          ddrphy_pad_oddrx2f7;
-wire          ddrphy_pad_oddrx2f8;
-wire          ddrphy_pad_oddrx2f9;
 wire          ddrphy_pad_oddrx2f10;
 wire          ddrphy_pad_oddrx2f11;
 wire          ddrphy_pad_oddrx2f12;
@@ -183,1691 +789,1418 @@ wire          ddrphy_pad_oddrx2f16;
 wire          ddrphy_pad_oddrx2f17;
 wire          ddrphy_pad_oddrx2f18;
 wire          ddrphy_pad_oddrx2f19;
+wire          ddrphy_pad_oddrx2f2;
 wire          ddrphy_pad_oddrx2f20;
 wire          ddrphy_pad_oddrx2f21;
 wire          ddrphy_pad_oddrx2f22;
 wire          ddrphy_pad_oddrx2f23;
 wire          ddrphy_pad_oddrx2f24;
 wire          ddrphy_pad_oddrx2f25;
-wire          ddrphy_dq_oe;
-wire          ddrphy_dqs_re;
-wire          ddrphy_dqs_oe;
-wire          ddrphy_dqs_postamble;
-wire          ddrphy_dqs_preamble;
-wire          ddrphy_dqs_i0;
-wire          ddrphy_dqsr900;
-wire          ddrphy_dqsw2700;
-wire          ddrphy_dqsw0;
-wire    [2:0] ddrphy_rdpntr0;
-wire    [2:0] ddrphy_wrpntr0;
+wire          ddrphy_pad_oddrx2f3;
+wire          ddrphy_pad_oddrx2f4;
+wire          ddrphy_pad_oddrx2f5;
+wire          ddrphy_pad_oddrx2f6;
+wire          ddrphy_pad_oddrx2f7;
+wire          ddrphy_pad_oddrx2f8;
+wire          ddrphy_pad_oddrx2f9;
+wire          ddrphy_pause0;
+reg           ddrphy_pause1 = 1'd0;
+reg           ddrphy_rddata_en_tappeddelayline0 = 1'd0;
+reg           ddrphy_rddata_en_tappeddelayline1 = 1'd0;
+reg           ddrphy_rddata_en_tappeddelayline10 = 1'd0;
+reg           ddrphy_rddata_en_tappeddelayline11 = 1'd0;
+reg           ddrphy_rddata_en_tappeddelayline12 = 1'd0;
+reg           ddrphy_rddata_en_tappeddelayline2 = 1'd0;
+reg           ddrphy_rddata_en_tappeddelayline3 = 1'd0;
+reg           ddrphy_rddata_en_tappeddelayline4 = 1'd0;
+reg           ddrphy_rddata_en_tappeddelayline5 = 1'd0;
+reg           ddrphy_rddata_en_tappeddelayline6 = 1'd0;
+reg           ddrphy_rddata_en_tappeddelayline7 = 1'd0;
+reg           ddrphy_rddata_en_tappeddelayline8 = 1'd0;
+reg           ddrphy_rddata_en_tappeddelayline9 = 1'd0;
 reg     [2:0] ddrphy_rdly0 = 3'd0;
-wire          ddrphy_burstdet0;
-reg           ddrphy_burstdet_d0 = 1'd0;
-wire          ddrphy_dqs0;
-wire          ddrphy_dqs_oe_n0;
-reg     [7:0] ddrphy_dm_o_data0 = 8'd0;
-reg     [7:0] ddrphy_dm_o_data_d0 = 8'd0;
-reg     [3:0] ddrphy_dm_o_data_muxed0 = 4'd0;
-wire          ddrphy_dq_o0;
-wire          ddrphy_dq_i0;
-wire          ddrphy_dq_oe_n0;
-wire          ddrphy_dq_i_delayed0;
-wire    [7:0] ddrphy_dq_i_data0;
-reg     [7:0] ddrphy_dq_o_data0 = 8'd0;
-reg     [7:0] ddrphy_dq_o_data_d0 = 8'd0;
-reg     [3:0] ddrphy_dq_o_data_muxed0 = 4'd0;
-wire    [3:0] ddrphy_bitslip0_i;
-reg     [3:0] ddrphy_bitslip0_o = 4'd0;
-reg     [1:0] ddrphy_bitslip0_value = 2'd0;
-reg     [7:0] ddrphy_bitslip0_r = 8'd0;
-reg     [3:0] ddrphy_dq_i_bitslip_o_d0 = 4'd0;
-wire          ddrphy_dq_o1;
-wire          ddrphy_dq_i1;
-wire          ddrphy_dq_oe_n1;
-wire          ddrphy_dq_i_delayed1;
-wire    [7:0] ddrphy_dq_i_data1;
-reg     [7:0] ddrphy_dq_o_data1 = 8'd0;
-reg     [7:0] ddrphy_dq_o_data_d1 = 8'd0;
-reg     [3:0] ddrphy_dq_o_data_muxed1 = 4'd0;
-wire    [3:0] ddrphy_bitslip1_i;
-reg     [3:0] ddrphy_bitslip1_o = 4'd0;
-reg     [1:0] ddrphy_bitslip1_value = 2'd0;
-reg     [7:0] ddrphy_bitslip1_r = 8'd0;
-reg     [3:0] ddrphy_dq_i_bitslip_o_d1 = 4'd0;
-wire          ddrphy_dq_o2;
-wire          ddrphy_dq_i2;
-wire          ddrphy_dq_oe_n2;
-wire          ddrphy_dq_i_delayed2;
-wire    [7:0] ddrphy_dq_i_data2;
-reg     [7:0] ddrphy_dq_o_data2 = 8'd0;
-reg     [7:0] ddrphy_dq_o_data_d2 = 8'd0;
-reg     [3:0] ddrphy_dq_o_data_muxed2 = 4'd0;
-wire    [3:0] ddrphy_bitslip2_i;
-reg     [3:0] ddrphy_bitslip2_o = 4'd0;
-reg     [1:0] ddrphy_bitslip2_value = 2'd0;
-reg     [7:0] ddrphy_bitslip2_r = 8'd0;
-reg     [3:0] ddrphy_dq_i_bitslip_o_d2 = 4'd0;
-wire          ddrphy_dq_o3;
-wire          ddrphy_dq_i3;
-wire          ddrphy_dq_oe_n3;
-wire          ddrphy_dq_i_delayed3;
-wire    [7:0] ddrphy_dq_i_data3;
-reg     [7:0] ddrphy_dq_o_data3 = 8'd0;
-reg     [7:0] ddrphy_dq_o_data_d3 = 8'd0;
-reg     [3:0] ddrphy_dq_o_data_muxed3 = 4'd0;
-wire    [3:0] ddrphy_bitslip3_i;
-reg     [3:0] ddrphy_bitslip3_o = 4'd0;
-reg     [1:0] ddrphy_bitslip3_value = 2'd0;
-reg     [7:0] ddrphy_bitslip3_r = 8'd0;
-reg     [3:0] ddrphy_dq_i_bitslip_o_d3 = 4'd0;
-wire          ddrphy_dq_o4;
-wire          ddrphy_dq_i4;
-wire          ddrphy_dq_oe_n4;
-wire          ddrphy_dq_i_delayed4;
-wire    [7:0] ddrphy_dq_i_data4;
-reg     [7:0] ddrphy_dq_o_data4 = 8'd0;
-reg     [7:0] ddrphy_dq_o_data_d4 = 8'd0;
-reg     [3:0] ddrphy_dq_o_data_muxed4 = 4'd0;
-wire    [3:0] ddrphy_bitslip4_i;
-reg     [3:0] ddrphy_bitslip4_o = 4'd0;
-reg     [1:0] ddrphy_bitslip4_value = 2'd0;
-reg     [7:0] ddrphy_bitslip4_r = 8'd0;
-reg     [3:0] ddrphy_dq_i_bitslip_o_d4 = 4'd0;
-wire          ddrphy_dq_o5;
-wire          ddrphy_dq_i5;
-wire          ddrphy_dq_oe_n5;
-wire          ddrphy_dq_i_delayed5;
-wire    [7:0] ddrphy_dq_i_data5;
-reg     [7:0] ddrphy_dq_o_data5 = 8'd0;
-reg     [7:0] ddrphy_dq_o_data_d5 = 8'd0;
-reg     [3:0] ddrphy_dq_o_data_muxed5 = 4'd0;
-wire    [3:0] ddrphy_bitslip5_i;
-reg     [3:0] ddrphy_bitslip5_o = 4'd0;
-reg     [1:0] ddrphy_bitslip5_value = 2'd0;
-reg     [7:0] ddrphy_bitslip5_r = 8'd0;
-reg     [3:0] ddrphy_dq_i_bitslip_o_d5 = 4'd0;
-wire          ddrphy_dq_o6;
-wire          ddrphy_dq_i6;
-wire          ddrphy_dq_oe_n6;
-wire          ddrphy_dq_i_delayed6;
-wire    [7:0] ddrphy_dq_i_data6;
-reg     [7:0] ddrphy_dq_o_data6 = 8'd0;
-reg     [7:0] ddrphy_dq_o_data_d6 = 8'd0;
-reg     [3:0] ddrphy_dq_o_data_muxed6 = 4'd0;
-wire    [3:0] ddrphy_bitslip6_i;
-reg     [3:0] ddrphy_bitslip6_o = 4'd0;
-reg     [1:0] ddrphy_bitslip6_value = 2'd0;
-reg     [7:0] ddrphy_bitslip6_r = 8'd0;
-reg     [3:0] ddrphy_dq_i_bitslip_o_d6 = 4'd0;
-wire          ddrphy_dq_o7;
-wire          ddrphy_dq_i7;
-wire          ddrphy_dq_oe_n7;
-wire          ddrphy_dq_i_delayed7;
-wire    [7:0] ddrphy_dq_i_data7;
-reg     [7:0] ddrphy_dq_o_data7 = 8'd0;
-reg     [7:0] ddrphy_dq_o_data_d7 = 8'd0;
-reg     [3:0] ddrphy_dq_o_data_muxed7 = 4'd0;
-wire    [3:0] ddrphy_bitslip7_i;
-reg     [3:0] ddrphy_bitslip7_o = 4'd0;
-reg     [1:0] ddrphy_bitslip7_value = 2'd0;
-reg     [7:0] ddrphy_bitslip7_r = 8'd0;
-reg     [3:0] ddrphy_dq_i_bitslip_o_d7 = 4'd0;
-wire          ddrphy_dqs_i1;
-wire          ddrphy_dqsr901;
-wire          ddrphy_dqsw2701;
-wire          ddrphy_dqsw1;
+reg     [2:0] ddrphy_rdly1 = 3'd0;
+wire          ddrphy_rdly_dq_bitslip_r;
+reg           ddrphy_rdly_dq_bitslip_re = 1'd0;
+wire          ddrphy_rdly_dq_bitslip_rst_r;
+reg           ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
+reg           ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+reg           ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
+reg           ddrphy_rdly_dq_bitslip_w = 1'd0;
+reg           ddrphy_rdly_dq_bitslip_we = 1'd0;
+wire          ddrphy_rdly_dq_inc_r;
+reg           ddrphy_rdly_dq_inc_re = 1'd0;
+reg           ddrphy_rdly_dq_inc_w = 1'd0;
+reg           ddrphy_rdly_dq_inc_we = 1'd0;
+wire          ddrphy_rdly_dq_rst_r;
+reg           ddrphy_rdly_dq_rst_re = 1'd0;
+reg           ddrphy_rdly_dq_rst_w = 1'd0;
+reg           ddrphy_rdly_dq_rst_we = 1'd0;
+wire    [2:0] ddrphy_rdpntr0;
 wire    [2:0] ddrphy_rdpntr1;
+wire          ddrphy_reset0;
+reg           ddrphy_reset1 = 1'd0;
+wire          ddrphy_stop0;
+reg           ddrphy_stop1 = 1'd0;
+reg     [6:0] ddrphy_trigger = 7'd0;
+reg           ddrphy_update = 1'd0;
+reg           ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
+reg           ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
+reg           ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
+reg           ddrphy_wrdata_en_tappeddelayline3 = 1'd0;
+reg           ddrphy_wrdata_en_tappeddelayline4 = 1'd0;
+reg           ddrphy_wrdata_en_tappeddelayline5 = 1'd0;
+reg           ddrphy_wrdata_en_tappeddelayline6 = 1'd0;
+wire    [2:0] ddrphy_wrpntr0;
 wire    [2:0] ddrphy_wrpntr1;
-reg     [2:0] ddrphy_rdly1 = 3'd0;
-wire          ddrphy_burstdet1;
-reg           ddrphy_burstdet_d1 = 1'd0;
-wire          ddrphy_dqs1;
-wire          ddrphy_dqs_oe_n1;
-reg     [7:0] ddrphy_dm_o_data1 = 8'd0;
-reg     [7:0] ddrphy_dm_o_data_d1 = 8'd0;
-reg     [3:0] ddrphy_dm_o_data_muxed1 = 4'd0;
-wire          ddrphy_dq_o8;
-wire          ddrphy_dq_i8;
-wire          ddrphy_dq_oe_n8;
-wire          ddrphy_dq_i_delayed8;
-wire    [7:0] ddrphy_dq_i_data8;
-reg     [7:0] ddrphy_dq_o_data8 = 8'd0;
-reg     [7:0] ddrphy_dq_o_data_d8 = 8'd0;
-reg     [3:0] ddrphy_dq_o_data_muxed8 = 4'd0;
-wire    [3:0] ddrphy_bitslip8_i;
-reg     [3:0] ddrphy_bitslip8_o = 4'd0;
-reg     [1:0] ddrphy_bitslip8_value = 2'd0;
-reg     [7:0] ddrphy_bitslip8_r = 8'd0;
-reg     [3:0] ddrphy_dq_i_bitslip_o_d8 = 4'd0;
-wire          ddrphy_dq_o9;
-wire          ddrphy_dq_i9;
-wire          ddrphy_dq_oe_n9;
-wire          ddrphy_dq_i_delayed9;
-wire    [7:0] ddrphy_dq_i_data9;
-reg     [7:0] ddrphy_dq_o_data9 = 8'd0;
-reg     [7:0] ddrphy_dq_o_data_d9 = 8'd0;
-reg     [3:0] ddrphy_dq_o_data_muxed9 = 4'd0;
-wire    [3:0] ddrphy_bitslip9_i;
-reg     [3:0] ddrphy_bitslip9_o = 4'd0;
-reg     [1:0] ddrphy_bitslip9_value = 2'd0;
-reg     [7:0] ddrphy_bitslip9_r = 8'd0;
-reg     [3:0] ddrphy_dq_i_bitslip_o_d9 = 4'd0;
-wire          ddrphy_dq_o10;
-wire          ddrphy_dq_i10;
-wire          ddrphy_dq_oe_n10;
-wire          ddrphy_dq_i_delayed10;
-wire    [7:0] ddrphy_dq_i_data10;
-reg     [7:0] ddrphy_dq_o_data10 = 8'd0;
-reg     [7:0] ddrphy_dq_o_data_d10 = 8'd0;
-reg     [3:0] ddrphy_dq_o_data_muxed10 = 4'd0;
-wire    [3:0] ddrphy_bitslip10_i;
-reg     [3:0] ddrphy_bitslip10_o = 4'd0;
-reg     [1:0] ddrphy_bitslip10_value = 2'd0;
-reg     [7:0] ddrphy_bitslip10_r = 8'd0;
-reg     [3:0] ddrphy_dq_i_bitslip_o_d10 = 4'd0;
-wire          ddrphy_dq_o11;
-wire          ddrphy_dq_i11;
-wire          ddrphy_dq_oe_n11;
-wire          ddrphy_dq_i_delayed11;
-wire    [7:0] ddrphy_dq_i_data11;
-reg     [7:0] ddrphy_dq_o_data11 = 8'd0;
-reg     [7:0] ddrphy_dq_o_data_d11 = 8'd0;
-reg     [3:0] ddrphy_dq_o_data_muxed11 = 4'd0;
-wire    [3:0] ddrphy_bitslip11_i;
-reg     [3:0] ddrphy_bitslip11_o = 4'd0;
-reg     [1:0] ddrphy_bitslip11_value = 2'd0;
-reg     [7:0] ddrphy_bitslip11_r = 8'd0;
-reg     [3:0] ddrphy_dq_i_bitslip_o_d11 = 4'd0;
-wire          ddrphy_dq_o12;
-wire          ddrphy_dq_i12;
-wire          ddrphy_dq_oe_n12;
-wire          ddrphy_dq_i_delayed12;
-wire    [7:0] ddrphy_dq_i_data12;
-reg     [7:0] ddrphy_dq_o_data12 = 8'd0;
-reg     [7:0] ddrphy_dq_o_data_d12 = 8'd0;
-reg     [3:0] ddrphy_dq_o_data_muxed12 = 4'd0;
-wire    [3:0] ddrphy_bitslip12_i;
-reg     [3:0] ddrphy_bitslip12_o = 4'd0;
-reg     [1:0] ddrphy_bitslip12_value = 2'd0;
-reg     [7:0] ddrphy_bitslip12_r = 8'd0;
-reg     [3:0] ddrphy_dq_i_bitslip_o_d12 = 4'd0;
-wire          ddrphy_dq_o13;
-wire          ddrphy_dq_i13;
-wire          ddrphy_dq_oe_n13;
-wire          ddrphy_dq_i_delayed13;
-wire    [7:0] ddrphy_dq_i_data13;
-reg     [7:0] ddrphy_dq_o_data13 = 8'd0;
-reg     [7:0] ddrphy_dq_o_data_d13 = 8'd0;
-reg     [3:0] ddrphy_dq_o_data_muxed13 = 4'd0;
-wire    [3:0] ddrphy_bitslip13_i;
-reg     [3:0] ddrphy_bitslip13_o = 4'd0;
-reg     [1:0] ddrphy_bitslip13_value = 2'd0;
-reg     [7:0] ddrphy_bitslip13_r = 8'd0;
-reg     [3:0] ddrphy_dq_i_bitslip_o_d13 = 4'd0;
-wire          ddrphy_dq_o14;
-wire          ddrphy_dq_i14;
-wire          ddrphy_dq_oe_n14;
-wire          ddrphy_dq_i_delayed14;
-wire    [7:0] ddrphy_dq_i_data14;
-reg     [7:0] ddrphy_dq_o_data14 = 8'd0;
-reg     [7:0] ddrphy_dq_o_data_d14 = 8'd0;
-reg     [3:0] ddrphy_dq_o_data_muxed14 = 4'd0;
-wire    [3:0] ddrphy_bitslip14_i;
-reg     [3:0] ddrphy_bitslip14_o = 4'd0;
-reg     [1:0] ddrphy_bitslip14_value = 2'd0;
-reg     [7:0] ddrphy_bitslip14_r = 8'd0;
-reg     [3:0] ddrphy_dq_i_bitslip_o_d14 = 4'd0;
-wire          ddrphy_dq_o15;
-wire          ddrphy_dq_i15;
-wire          ddrphy_dq_oe_n15;
-wire          ddrphy_dq_i_delayed15;
-wire    [7:0] ddrphy_dq_i_data15;
-reg     [7:0] ddrphy_dq_o_data15 = 8'd0;
-reg     [7:0] ddrphy_dq_o_data_d15 = 8'd0;
-reg     [3:0] ddrphy_dq_o_data_muxed15 = 4'd0;
-wire    [3:0] ddrphy_bitslip15_i;
-reg     [3:0] ddrphy_bitslip15_o = 4'd0;
-reg     [1:0] ddrphy_bitslip15_value = 2'd0;
-reg     [7:0] ddrphy_bitslip15_r = 8'd0;
-reg     [3:0] ddrphy_dq_i_bitslip_o_d15 = 4'd0;
-reg           ddrphy_rddata_en_tappeddelayline0 = 1'd0;
-reg           ddrphy_rddata_en_tappeddelayline1 = 1'd0;
-reg           ddrphy_rddata_en_tappeddelayline2 = 1'd0;
-reg           ddrphy_rddata_en_tappeddelayline3 = 1'd0;
-reg           ddrphy_rddata_en_tappeddelayline4 = 1'd0;
-reg           ddrphy_rddata_en_tappeddelayline5 = 1'd0;
-reg           ddrphy_rddata_en_tappeddelayline6 = 1'd0;
-reg           ddrphy_rddata_en_tappeddelayline7 = 1'd0;
-reg           ddrphy_rddata_en_tappeddelayline8 = 1'd0;
-reg           ddrphy_rddata_en_tappeddelayline9 = 1'd0;
-reg           ddrphy_rddata_en_tappeddelayline10 = 1'd0;
-reg           ddrphy_rddata_en_tappeddelayline11 = 1'd0;
-reg           ddrphy_rddata_en_tappeddelayline12 = 1'd0;
-reg           ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
-reg           ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
-reg           ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
-reg           ddrphy_wrdata_en_tappeddelayline3 = 1'd0;
-reg           ddrphy_wrdata_en_tappeddelayline4 = 1'd0;
-reg           ddrphy_wrdata_en_tappeddelayline5 = 1'd0;
-reg           ddrphy_wrdata_en_tappeddelayline6 = 1'd0;
-wire   [14:0] litedramcore_slave_p0_address;
-wire    [2:0] litedramcore_slave_p0_bank;
-wire          litedramcore_slave_p0_cas_n;
-wire          litedramcore_slave_p0_cs_n;
-wire          litedramcore_slave_p0_ras_n;
-wire          litedramcore_slave_p0_we_n;
-wire          litedramcore_slave_p0_cke;
-wire          litedramcore_slave_p0_odt;
-wire          litedramcore_slave_p0_reset_n;
-wire          litedramcore_slave_p0_act_n;
-wire   [63:0] litedramcore_slave_p0_wrdata;
-wire          litedramcore_slave_p0_wrdata_en;
-wire    [7:0] litedramcore_slave_p0_wrdata_mask;
-wire          litedramcore_slave_p0_rddata_en;
-reg    [63:0] litedramcore_slave_p0_rddata = 64'd0;
-reg           litedramcore_slave_p0_rddata_valid = 1'd0;
-wire   [14:0] litedramcore_slave_p1_address;
-wire    [2:0] litedramcore_slave_p1_bank;
-wire          litedramcore_slave_p1_cas_n;
-wire          litedramcore_slave_p1_cs_n;
-wire          litedramcore_slave_p1_ras_n;
-wire          litedramcore_slave_p1_we_n;
-wire          litedramcore_slave_p1_cke;
-wire          litedramcore_slave_p1_odt;
-wire          litedramcore_slave_p1_reset_n;
-wire          litedramcore_slave_p1_act_n;
-wire   [63:0] litedramcore_slave_p1_wrdata;
-wire          litedramcore_slave_p1_wrdata_en;
-wire    [7:0] litedramcore_slave_p1_wrdata_mask;
-wire          litedramcore_slave_p1_rddata_en;
-reg    [63:0] litedramcore_slave_p1_rddata = 64'd0;
-reg           litedramcore_slave_p1_rddata_valid = 1'd0;
-reg    [14:0] litedramcore_master_p0_address = 15'd0;
-reg     [2:0] litedramcore_master_p0_bank = 3'd0;
-reg           litedramcore_master_p0_cas_n = 1'd1;
-reg           litedramcore_master_p0_cs_n = 1'd1;
-reg           litedramcore_master_p0_ras_n = 1'd1;
-reg           litedramcore_master_p0_we_n = 1'd1;
-reg           litedramcore_master_p0_cke = 1'd0;
-reg           litedramcore_master_p0_odt = 1'd0;
-reg           litedramcore_master_p0_reset_n = 1'd0;
-reg           litedramcore_master_p0_act_n = 1'd1;
-reg    [63:0] litedramcore_master_p0_wrdata = 64'd0;
-reg           litedramcore_master_p0_wrdata_en = 1'd0;
-reg     [7:0] litedramcore_master_p0_wrdata_mask = 8'd0;
-reg           litedramcore_master_p0_rddata_en = 1'd0;
-wire   [63:0] litedramcore_master_p0_rddata;
-wire          litedramcore_master_p0_rddata_valid;
-reg    [14:0] litedramcore_master_p1_address = 15'd0;
-reg     [2:0] litedramcore_master_p1_bank = 3'd0;
-reg           litedramcore_master_p1_cas_n = 1'd1;
-reg           litedramcore_master_p1_cs_n = 1'd1;
-reg           litedramcore_master_p1_ras_n = 1'd1;
-reg           litedramcore_master_p1_we_n = 1'd1;
-reg           litedramcore_master_p1_cke = 1'd0;
-reg           litedramcore_master_p1_odt = 1'd0;
-reg           litedramcore_master_p1_reset_n = 1'd0;
-reg           litedramcore_master_p1_act_n = 1'd1;
-reg    [63:0] litedramcore_master_p1_wrdata = 64'd0;
-reg           litedramcore_master_p1_wrdata_en = 1'd0;
-reg     [7:0] litedramcore_master_p1_wrdata_mask = 8'd0;
-reg           litedramcore_master_p1_rddata_en = 1'd0;
-wire   [63:0] litedramcore_master_p1_rddata;
-wire          litedramcore_master_p1_rddata_valid;
-wire   [14:0] litedramcore_csr_dfi_p0_address;
-wire    [2:0] litedramcore_csr_dfi_p0_bank;
-reg           litedramcore_csr_dfi_p0_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p0_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p0_ras_n = 1'd1;
-reg           litedramcore_csr_dfi_p0_we_n = 1'd1;
-wire          litedramcore_csr_dfi_p0_cke;
-wire          litedramcore_csr_dfi_p0_odt;
-wire          litedramcore_csr_dfi_p0_reset_n;
-reg           litedramcore_csr_dfi_p0_act_n = 1'd1;
-wire   [63:0] litedramcore_csr_dfi_p0_wrdata;
-wire          litedramcore_csr_dfi_p0_wrdata_en;
-wire    [7:0] litedramcore_csr_dfi_p0_wrdata_mask;
-wire          litedramcore_csr_dfi_p0_rddata_en;
-reg    [63:0] litedramcore_csr_dfi_p0_rddata = 64'd0;
-reg           litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
-wire   [14:0] litedramcore_csr_dfi_p1_address;
-wire    [2:0] litedramcore_csr_dfi_p1_bank;
-reg           litedramcore_csr_dfi_p1_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p1_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p1_ras_n = 1'd1;
-reg           litedramcore_csr_dfi_p1_we_n = 1'd1;
-wire          litedramcore_csr_dfi_p1_cke;
-wire          litedramcore_csr_dfi_p1_odt;
-wire          litedramcore_csr_dfi_p1_reset_n;
-reg           litedramcore_csr_dfi_p1_act_n = 1'd1;
-wire   [63:0] litedramcore_csr_dfi_p1_wrdata;
-wire          litedramcore_csr_dfi_p1_wrdata_en;
-wire    [7:0] litedramcore_csr_dfi_p1_wrdata_mask;
-wire          litedramcore_csr_dfi_p1_rddata_en;
-reg    [63:0] litedramcore_csr_dfi_p1_rddata = 64'd0;
-reg           litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
-reg    [14:0] litedramcore_ext_dfi_p0_address = 15'd0;
-reg     [2:0] litedramcore_ext_dfi_p0_bank = 3'd0;
-reg           litedramcore_ext_dfi_p0_cas_n = 1'd1;
-reg           litedramcore_ext_dfi_p0_cs_n = 1'd1;
-reg           litedramcore_ext_dfi_p0_ras_n = 1'd1;
-reg           litedramcore_ext_dfi_p0_we_n = 1'd1;
-reg           litedramcore_ext_dfi_p0_cke = 1'd0;
-reg           litedramcore_ext_dfi_p0_odt = 1'd0;
-reg           litedramcore_ext_dfi_p0_reset_n = 1'd0;
-reg           litedramcore_ext_dfi_p0_act_n = 1'd1;
-reg    [63:0] litedramcore_ext_dfi_p0_wrdata = 64'd0;
-reg           litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
-reg     [7:0] litedramcore_ext_dfi_p0_wrdata_mask = 8'd0;
-reg           litedramcore_ext_dfi_p0_rddata_en = 1'd0;
-reg    [63:0] litedramcore_ext_dfi_p0_rddata = 64'd0;
-reg           litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
-reg    [14:0] litedramcore_ext_dfi_p1_address = 15'd0;
-reg     [2:0] litedramcore_ext_dfi_p1_bank = 3'd0;
-reg           litedramcore_ext_dfi_p1_cas_n = 1'd1;
-reg           litedramcore_ext_dfi_p1_cs_n = 1'd1;
-reg           litedramcore_ext_dfi_p1_ras_n = 1'd1;
-reg           litedramcore_ext_dfi_p1_we_n = 1'd1;
-reg           litedramcore_ext_dfi_p1_cke = 1'd0;
-reg           litedramcore_ext_dfi_p1_odt = 1'd0;
-reg           litedramcore_ext_dfi_p1_reset_n = 1'd0;
-reg           litedramcore_ext_dfi_p1_act_n = 1'd1;
-reg    [63:0] litedramcore_ext_dfi_p1_wrdata = 64'd0;
-reg           litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
-reg     [7:0] litedramcore_ext_dfi_p1_wrdata_mask = 8'd0;
-reg           litedramcore_ext_dfi_p1_rddata_en = 1'd0;
-reg    [63:0] litedramcore_ext_dfi_p1_rddata = 64'd0;
-reg           litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
-reg           litedramcore_ext_dfi_sel = 1'd0;
-wire          litedramcore_sel;
-wire          litedramcore_cke;
-wire          litedramcore_odt;
-wire          litedramcore_reset_n;
-reg     [3:0] litedramcore_storage = 4'd1;
-reg           litedramcore_re = 1'd0;
-wire          litedramcore_phaseinjector0_csrfield_cs;
-wire          litedramcore_phaseinjector0_csrfield_we;
-wire          litedramcore_phaseinjector0_csrfield_cas;
-wire          litedramcore_phaseinjector0_csrfield_ras;
-wire          litedramcore_phaseinjector0_csrfield_wren;
-wire          litedramcore_phaseinjector0_csrfield_rden;
-reg     [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
-reg           litedramcore_phaseinjector0_command_re = 1'd0;
-reg           litedramcore_phaseinjector0_command_issue_re = 1'd0;
-wire          litedramcore_phaseinjector0_command_issue_r;
-reg           litedramcore_phaseinjector0_command_issue_we = 1'd0;
-reg           litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg    [14:0] litedramcore_phaseinjector0_address_storage = 15'd0;
-reg           litedramcore_phaseinjector0_address_re = 1'd0;
-reg     [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg           litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg    [63:0] litedramcore_phaseinjector0_wrdata_storage = 64'd0;
-reg           litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg    [63:0] litedramcore_phaseinjector0_rddata_status = 64'd0;
-wire          litedramcore_phaseinjector0_rddata_we;
-reg           litedramcore_phaseinjector0_rddata_re = 1'd0;
-wire          litedramcore_phaseinjector1_csrfield_cs;
-wire          litedramcore_phaseinjector1_csrfield_we;
-wire          litedramcore_phaseinjector1_csrfield_cas;
-wire          litedramcore_phaseinjector1_csrfield_ras;
-wire          litedramcore_phaseinjector1_csrfield_wren;
-wire          litedramcore_phaseinjector1_csrfield_rden;
-reg     [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
-reg           litedramcore_phaseinjector1_command_re = 1'd0;
-reg           litedramcore_phaseinjector1_command_issue_re = 1'd0;
-wire          litedramcore_phaseinjector1_command_issue_r;
-reg           litedramcore_phaseinjector1_command_issue_we = 1'd0;
-reg           litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg    [14:0] litedramcore_phaseinjector1_address_storage = 15'd0;
-reg           litedramcore_phaseinjector1_address_re = 1'd0;
-reg     [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg           litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg    [63:0] litedramcore_phaseinjector1_wrdata_storage = 64'd0;
-reg           litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg    [63:0] litedramcore_phaseinjector1_rddata_status = 64'd0;
-wire          litedramcore_phaseinjector1_rddata_we;
-reg           litedramcore_phaseinjector1_rddata_re = 1'd0;
-wire          litedramcore_interface_bank0_valid;
-wire          litedramcore_interface_bank0_ready;
-wire          litedramcore_interface_bank0_we;
-wire   [21:0] litedramcore_interface_bank0_addr;
-wire          litedramcore_interface_bank0_lock;
-wire          litedramcore_interface_bank0_wdata_ready;
-wire          litedramcore_interface_bank0_rdata_valid;
-wire          litedramcore_interface_bank1_valid;
-wire          litedramcore_interface_bank1_ready;
-wire          litedramcore_interface_bank1_we;
-wire   [21:0] litedramcore_interface_bank1_addr;
-wire          litedramcore_interface_bank1_lock;
-wire          litedramcore_interface_bank1_wdata_ready;
-wire          litedramcore_interface_bank1_rdata_valid;
-wire          litedramcore_interface_bank2_valid;
-wire          litedramcore_interface_bank2_ready;
-wire          litedramcore_interface_bank2_we;
-wire   [21:0] litedramcore_interface_bank2_addr;
-wire          litedramcore_interface_bank2_lock;
-wire          litedramcore_interface_bank2_wdata_ready;
-wire          litedramcore_interface_bank2_rdata_valid;
-wire          litedramcore_interface_bank3_valid;
-wire          litedramcore_interface_bank3_ready;
-wire          litedramcore_interface_bank3_we;
-wire   [21:0] litedramcore_interface_bank3_addr;
-wire          litedramcore_interface_bank3_lock;
-wire          litedramcore_interface_bank3_wdata_ready;
-wire          litedramcore_interface_bank3_rdata_valid;
-wire          litedramcore_interface_bank4_valid;
-wire          litedramcore_interface_bank4_ready;
-wire          litedramcore_interface_bank4_we;
-wire   [21:0] litedramcore_interface_bank4_addr;
-wire          litedramcore_interface_bank4_lock;
-wire          litedramcore_interface_bank4_wdata_ready;
-wire          litedramcore_interface_bank4_rdata_valid;
-wire          litedramcore_interface_bank5_valid;
-wire          litedramcore_interface_bank5_ready;
-wire          litedramcore_interface_bank5_we;
-wire   [21:0] litedramcore_interface_bank5_addr;
-wire          litedramcore_interface_bank5_lock;
-wire          litedramcore_interface_bank5_wdata_ready;
-wire          litedramcore_interface_bank5_rdata_valid;
-wire          litedramcore_interface_bank6_valid;
-wire          litedramcore_interface_bank6_ready;
-wire          litedramcore_interface_bank6_we;
-wire   [21:0] litedramcore_interface_bank6_addr;
-wire          litedramcore_interface_bank6_lock;
-wire          litedramcore_interface_bank6_wdata_ready;
-wire          litedramcore_interface_bank6_rdata_valid;
-wire          litedramcore_interface_bank7_valid;
-wire          litedramcore_interface_bank7_ready;
-wire          litedramcore_interface_bank7_we;
-wire   [21:0] litedramcore_interface_bank7_addr;
-wire          litedramcore_interface_bank7_lock;
-wire          litedramcore_interface_bank7_wdata_ready;
-wire          litedramcore_interface_bank7_rdata_valid;
-reg   [127:0] litedramcore_interface_wdata = 128'd0;
-reg    [15:0] litedramcore_interface_wdata_we = 16'd0;
-wire  [127:0] litedramcore_interface_rdata;
-reg    [14:0] litedramcore_dfi_p0_address = 15'd0;
-reg     [2:0] litedramcore_dfi_p0_bank = 3'd0;
-reg           litedramcore_dfi_p0_cas_n = 1'd1;
-reg           litedramcore_dfi_p0_cs_n = 1'd1;
-reg           litedramcore_dfi_p0_ras_n = 1'd1;
-reg           litedramcore_dfi_p0_we_n = 1'd1;
-wire          litedramcore_dfi_p0_cke;
-wire          litedramcore_dfi_p0_odt;
-wire          litedramcore_dfi_p0_reset_n;
-reg           litedramcore_dfi_p0_act_n = 1'd1;
-wire   [63:0] litedramcore_dfi_p0_wrdata;
-reg           litedramcore_dfi_p0_wrdata_en = 1'd0;
-wire    [7:0] litedramcore_dfi_p0_wrdata_mask;
-reg           litedramcore_dfi_p0_rddata_en = 1'd0;
-wire   [63:0] litedramcore_dfi_p0_rddata;
-wire          litedramcore_dfi_p0_rddata_valid;
-reg    [14:0] litedramcore_dfi_p1_address = 15'd0;
-reg     [2:0] litedramcore_dfi_p1_bank = 3'd0;
-reg           litedramcore_dfi_p1_cas_n = 1'd1;
-reg           litedramcore_dfi_p1_cs_n = 1'd1;
-reg           litedramcore_dfi_p1_ras_n = 1'd1;
-reg           litedramcore_dfi_p1_we_n = 1'd1;
-wire          litedramcore_dfi_p1_cke;
-wire          litedramcore_dfi_p1_odt;
-wire          litedramcore_dfi_p1_reset_n;
-reg           litedramcore_dfi_p1_act_n = 1'd1;
-wire   [63:0] litedramcore_dfi_p1_wrdata;
-reg           litedramcore_dfi_p1_wrdata_en = 1'd0;
-wire    [7:0] litedramcore_dfi_p1_wrdata_mask;
-reg           litedramcore_dfi_p1_rddata_en = 1'd0;
-wire   [63:0] litedramcore_dfi_p1_rddata;
-wire          litedramcore_dfi_p1_rddata_valid;
-reg           litedramcore_cmd_valid = 1'd0;
-reg           litedramcore_cmd_ready = 1'd0;
-reg           litedramcore_cmd_last = 1'd0;
-reg    [14:0] litedramcore_cmd_payload_a = 15'd0;
-reg     [2:0] litedramcore_cmd_payload_ba = 3'd0;
-reg           litedramcore_cmd_payload_cas = 1'd0;
-reg           litedramcore_cmd_payload_ras = 1'd0;
-reg           litedramcore_cmd_payload_we = 1'd0;
-reg           litedramcore_cmd_payload_is_read = 1'd0;
-reg           litedramcore_cmd_payload_is_write = 1'd0;
-wire          litedramcore_wants_refresh;
-wire          litedramcore_wants_zqcs;
-wire          litedramcore_timer_wait;
-wire          litedramcore_timer_done0;
-wire    [8:0] litedramcore_timer_count0;
-wire          litedramcore_timer_done1;
-reg     [8:0] litedramcore_timer_count1 = 9'd374;
-wire          litedramcore_postponer_req_i;
-reg           litedramcore_postponer_req_o = 1'd0;
-reg           litedramcore_postponer_count = 1'd0;
-reg           litedramcore_sequencer_start0 = 1'd0;
-wire          litedramcore_sequencer_done0;
-wire          litedramcore_sequencer_start1;
-reg           litedramcore_sequencer_done1 = 1'd0;
-reg     [6:0] litedramcore_sequencer_counter = 7'd0;
-reg           litedramcore_sequencer_count = 1'd0;
-wire          litedramcore_zqcs_timer_wait;
-wire          litedramcore_zqcs_timer_done0;
-wire   [25:0] litedramcore_zqcs_timer_count0;
-wire          litedramcore_zqcs_timer_done1;
-reg    [25:0] litedramcore_zqcs_timer_count1 = 26'd47999999;
-reg           litedramcore_zqcs_executer_start = 1'd0;
-reg           litedramcore_zqcs_executer_done = 1'd0;
-reg     [5:0] litedramcore_zqcs_executer_counter = 6'd0;
-wire          litedramcore_bankmachine0_req_valid;
-wire          litedramcore_bankmachine0_req_ready;
-wire          litedramcore_bankmachine0_req_we;
-wire   [21:0] litedramcore_bankmachine0_req_addr;
-wire          litedramcore_bankmachine0_req_lock;
-reg           litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine0_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine0_refresh_req;
-reg           litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg    [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0;
-wire    [2:0] litedramcore_bankmachine0_cmd_payload_ba;
-reg           litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine0_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine0_sink_valid;
-wire          litedramcore_bankmachine0_sink_ready;
-reg           litedramcore_bankmachine0_sink_first = 1'd0;
-reg           litedramcore_bankmachine0_sink_last = 1'd0;
-wire          litedramcore_bankmachine0_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine0_sink_payload_addr;
-wire          litedramcore_bankmachine0_source_valid;
-wire          litedramcore_bankmachine0_source_ready;
-wire          litedramcore_bankmachine0_source_first;
-wire          litedramcore_bankmachine0_source_last;
-wire          litedramcore_bankmachine0_source_payload_we;
-wire   [21:0] litedramcore_bankmachine0_source_payload_addr;
-wire          litedramcore_bankmachine0_syncfifo0_we;
-wire          litedramcore_bankmachine0_syncfifo0_writable;
-wire          litedramcore_bankmachine0_syncfifo0_re;
-wire          litedramcore_bankmachine0_syncfifo0_readable;
-wire   [24:0] litedramcore_bankmachine0_syncfifo0_din;
-wire   [24:0] litedramcore_bankmachine0_syncfifo0_dout;
-reg     [4:0] litedramcore_bankmachine0_level = 5'd0;
-reg           litedramcore_bankmachine0_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine0_produce = 4'd0;
+wire          init_clk;
+reg           init_done_re = 1'd0;
+reg           init_done_storage = 1'd0;
+reg           init_error_re = 1'd0;
+reg           init_error_storage = 1'd0;
+wire          init_rst;
+reg           interface0_ack = 1'd0;
+wire   [29:0] interface0_adr;
+wire   [13:0] interface0_bank_bus_adr;
+reg    [31:0] interface0_bank_bus_dat_r = 32'd0;
+wire   [31:0] interface0_bank_bus_dat_w;
+wire          interface0_bank_bus_we;
+wire    [1:0] interface0_bte;
+wire    [2:0] interface0_cti;
+wire          interface0_cyc;
+reg    [31:0] interface0_dat_r = 32'd0;
+wire   [31:0] interface0_dat_w;
+reg           interface0_err = 1'd0;
+wire    [3:0] interface0_sel;
+wire          interface0_stb;
+wire          interface0_we;
+reg    [13:0] interface1_adr = 14'd0;
+reg    [13:0] interface1_adr_next_value1 = 14'd0;
+reg           interface1_adr_next_value_ce1 = 1'd0;
+wire   [13:0] interface1_bank_bus_adr;
+reg    [31:0] interface1_bank_bus_dat_r = 32'd0;
+wire   [31:0] interface1_bank_bus_dat_w;
+wire          interface1_bank_bus_we;
+wire   [31:0] interface1_dat_r;
+reg    [31:0] interface1_dat_w = 32'd0;
+reg    [31:0] interface1_dat_w_next_value0 = 32'd0;
+reg           interface1_dat_w_next_value_ce0 = 1'd0;
+reg           interface1_we = 1'd0;
+reg           interface1_we_next_value2 = 1'd0;
+reg           interface1_we_next_value_ce2 = 1'd0;
+wire   [13:0] interface2_bank_bus_adr;
+reg    [31:0] interface2_bank_bus_dat_r = 32'd0;
+wire   [31:0] interface2_bank_bus_dat_w;
+wire          interface2_bank_bus_we;
+wire          latticeecp5asyncresetsynchronizerimpl0_expr;
+wire          latticeecp5asyncresetsynchronizerimpl0_rst1;
+wire          latticeecp5asyncresetsynchronizerimpl1_rst1;
+wire          latticeecp5asyncresetsynchronizerimpl2_rst1;
+wire          latticeecp5asyncresetsynchronizerimpl3_rst1;
+reg           litedramcore_bankmachine0_auto_precharge = 1'd0;
+reg    [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0;
+wire    [2:0] litedramcore_bankmachine0_cmd_payload_ba;
+reg           litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg           litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg           litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg           litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg           litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg           litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg           litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg           litedramcore_bankmachine0_cmd_valid = 1'd0;
 reg     [3:0] litedramcore_bankmachine0_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0;
-wire   [24:0] litedramcore_bankmachine0_wrport_dat_r;
-wire          litedramcore_bankmachine0_wrport_we;
-wire   [24:0] litedramcore_bankmachine0_wrport_dat_w;
 wire          litedramcore_bankmachine0_do_read;
-wire    [3:0] litedramcore_bankmachine0_rdport_adr;
-wire   [24:0] litedramcore_bankmachine0_rdport_dat_r;
-wire          litedramcore_bankmachine0_fifo_in_payload_we;
-wire   [21:0] litedramcore_bankmachine0_fifo_in_payload_addr;
 wire          litedramcore_bankmachine0_fifo_in_first;
 wire          litedramcore_bankmachine0_fifo_in_last;
-wire          litedramcore_bankmachine0_fifo_out_payload_we;
-wire   [21:0] litedramcore_bankmachine0_fifo_out_payload_addr;
+wire   [21:0] litedramcore_bankmachine0_fifo_in_payload_addr;
+wire          litedramcore_bankmachine0_fifo_in_payload_we;
 wire          litedramcore_bankmachine0_fifo_out_first;
 wire          litedramcore_bankmachine0_fifo_out_last;
-wire          litedramcore_bankmachine0_sink_sink_valid;
-wire          litedramcore_bankmachine0_sink_sink_ready;
-wire          litedramcore_bankmachine0_sink_sink_first;
-wire          litedramcore_bankmachine0_sink_sink_last;
-wire          litedramcore_bankmachine0_sink_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine0_sink_sink_payload_addr;
-wire          litedramcore_bankmachine0_source_source_valid;
-wire          litedramcore_bankmachine0_source_source_ready;
-wire          litedramcore_bankmachine0_source_source_first;
-wire          litedramcore_bankmachine0_source_source_last;
-wire          litedramcore_bankmachine0_source_source_payload_we;
-wire   [21:0] litedramcore_bankmachine0_source_source_payload_addr;
-wire          litedramcore_bankmachine0_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine0_pipe_valid_sink_ready;
+wire   [21:0] litedramcore_bankmachine0_fifo_out_payload_addr;
+wire          litedramcore_bankmachine0_fifo_out_payload_we;
+reg     [4:0] litedramcore_bankmachine0_level = 5'd0;
+reg     [2:0] litedramcore_bankmachine0_next_state = 3'd0;
 wire          litedramcore_bankmachine0_pipe_valid_sink_first;
 wire          litedramcore_bankmachine0_pipe_valid_sink_last;
-wire          litedramcore_bankmachine0_pipe_valid_sink_payload_we;
 wire   [21:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine0_pipe_valid_source_ready;
+wire          litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+wire          litedramcore_bankmachine0_pipe_valid_sink_ready;
+wire          litedramcore_bankmachine0_pipe_valid_sink_valid;
 reg           litedramcore_bankmachine0_pipe_valid_source_first = 1'd0;
 reg           litedramcore_bankmachine0_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0;
 reg    [21:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 22'd0;
+reg           litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0;
+wire          litedramcore_bankmachine0_pipe_valid_source_ready;
+reg           litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0;
+reg     [3:0] litedramcore_bankmachine0_produce = 4'd0;
+wire    [3:0] litedramcore_bankmachine0_rdport_adr;
+wire   [24:0] litedramcore_bankmachine0_rdport_dat_r;
+reg           litedramcore_bankmachine0_refresh_gnt = 1'd0;
+wire          litedramcore_bankmachine0_refresh_req;
+reg           litedramcore_bankmachine0_replace = 1'd0;
+wire   [21:0] litedramcore_bankmachine0_req_addr;
+wire          litedramcore_bankmachine0_req_lock;
+reg           litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire          litedramcore_bankmachine0_req_ready;
+wire          litedramcore_bankmachine0_req_valid;
+reg           litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+wire          litedramcore_bankmachine0_req_we;
 reg    [14:0] litedramcore_bankmachine0_row = 15'd0;
-reg           litedramcore_bankmachine0_row_opened = 1'd0;
-wire          litedramcore_bankmachine0_row_hit;
-reg           litedramcore_bankmachine0_row_open = 1'd0;
 reg           litedramcore_bankmachine0_row_close = 1'd0;
 reg           litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine0_twtpcon_valid;
-reg           litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine0_trccon_valid;
-reg           litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg     [1:0] litedramcore_bankmachine0_trccon_count = 2'd0;
-wire          litedramcore_bankmachine0_trascon_valid;
-reg           litedramcore_bankmachine0_trascon_ready = 1'd0;
+wire          litedramcore_bankmachine0_row_hit;
+reg           litedramcore_bankmachine0_row_open = 1'd0;
+reg           litedramcore_bankmachine0_row_opened = 1'd0;
+reg           litedramcore_bankmachine0_sink_first = 1'd0;
+reg           litedramcore_bankmachine0_sink_last = 1'd0;
+wire   [21:0] litedramcore_bankmachine0_sink_payload_addr;
+wire          litedramcore_bankmachine0_sink_payload_we;
+wire          litedramcore_bankmachine0_sink_ready;
+wire          litedramcore_bankmachine0_sink_sink_first;
+wire          litedramcore_bankmachine0_sink_sink_last;
+wire   [21:0] litedramcore_bankmachine0_sink_sink_payload_addr;
+wire          litedramcore_bankmachine0_sink_sink_payload_we;
+wire          litedramcore_bankmachine0_sink_sink_ready;
+wire          litedramcore_bankmachine0_sink_sink_valid;
+wire          litedramcore_bankmachine0_sink_valid;
+wire          litedramcore_bankmachine0_source_first;
+wire          litedramcore_bankmachine0_source_last;
+wire   [21:0] litedramcore_bankmachine0_source_payload_addr;
+wire          litedramcore_bankmachine0_source_payload_we;
+wire          litedramcore_bankmachine0_source_ready;
+wire          litedramcore_bankmachine0_source_source_first;
+wire          litedramcore_bankmachine0_source_source_last;
+wire   [21:0] litedramcore_bankmachine0_source_source_payload_addr;
+wire          litedramcore_bankmachine0_source_source_payload_we;
+wire          litedramcore_bankmachine0_source_source_ready;
+wire          litedramcore_bankmachine0_source_source_valid;
+wire          litedramcore_bankmachine0_source_valid;
+reg     [2:0] litedramcore_bankmachine0_state = 3'd0;
+wire   [24:0] litedramcore_bankmachine0_syncfifo0_din;
+wire   [24:0] litedramcore_bankmachine0_syncfifo0_dout;
+wire          litedramcore_bankmachine0_syncfifo0_re;
+wire          litedramcore_bankmachine0_syncfifo0_readable;
+wire          litedramcore_bankmachine0_syncfifo0_we;
+wire          litedramcore_bankmachine0_syncfifo0_writable;
 reg     [1:0] litedramcore_bankmachine0_trascon_count = 2'd0;
-wire          litedramcore_bankmachine1_req_valid;
-wire          litedramcore_bankmachine1_req_ready;
-wire          litedramcore_bankmachine1_req_we;
-wire   [21:0] litedramcore_bankmachine1_req_addr;
-wire          litedramcore_bankmachine1_req_lock;
-reg           litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine1_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine1_refresh_req;
-reg           litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg           litedramcore_bankmachine0_trascon_ready = 1'd0;
+wire          litedramcore_bankmachine0_trascon_valid;
+reg     [1:0] litedramcore_bankmachine0_trccon_count = 2'd0;
+reg           litedramcore_bankmachine0_trccon_ready = 1'd0;
+wire          litedramcore_bankmachine0_trccon_valid;
+reg     [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
+reg           litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+wire          litedramcore_bankmachine0_twtpcon_valid;
+reg     [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0;
+wire   [24:0] litedramcore_bankmachine0_wrport_dat_r;
+wire   [24:0] litedramcore_bankmachine0_wrport_dat_w;
+wire          litedramcore_bankmachine0_wrport_we;
+reg           litedramcore_bankmachine1_auto_precharge = 1'd0;
 reg    [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0;
 wire    [2:0] litedramcore_bankmachine1_cmd_payload_ba;
 reg           litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_we = 1'd0;
 reg           litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
 reg           litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
 reg           litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine1_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine1_sink_valid;
-wire          litedramcore_bankmachine1_sink_ready;
-reg           litedramcore_bankmachine1_sink_first = 1'd0;
-reg           litedramcore_bankmachine1_sink_last = 1'd0;
-wire          litedramcore_bankmachine1_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine1_sink_payload_addr;
-wire          litedramcore_bankmachine1_source_valid;
-wire          litedramcore_bankmachine1_source_ready;
-wire          litedramcore_bankmachine1_source_first;
-wire          litedramcore_bankmachine1_source_last;
-wire          litedramcore_bankmachine1_source_payload_we;
-wire   [21:0] litedramcore_bankmachine1_source_payload_addr;
-wire          litedramcore_bankmachine1_syncfifo1_we;
-wire          litedramcore_bankmachine1_syncfifo1_writable;
-wire          litedramcore_bankmachine1_syncfifo1_re;
-wire          litedramcore_bankmachine1_syncfifo1_readable;
-wire   [24:0] litedramcore_bankmachine1_syncfifo1_din;
-wire   [24:0] litedramcore_bankmachine1_syncfifo1_dout;
-reg     [4:0] litedramcore_bankmachine1_level = 5'd0;
-reg           litedramcore_bankmachine1_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine1_produce = 4'd0;
+reg           litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg           litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg           litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg           litedramcore_bankmachine1_cmd_valid = 1'd0;
 reg     [3:0] litedramcore_bankmachine1_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0;
-wire   [24:0] litedramcore_bankmachine1_wrport_dat_r;
-wire          litedramcore_bankmachine1_wrport_we;
-wire   [24:0] litedramcore_bankmachine1_wrport_dat_w;
 wire          litedramcore_bankmachine1_do_read;
-wire    [3:0] litedramcore_bankmachine1_rdport_adr;
-wire   [24:0] litedramcore_bankmachine1_rdport_dat_r;
-wire          litedramcore_bankmachine1_fifo_in_payload_we;
-wire   [21:0] litedramcore_bankmachine1_fifo_in_payload_addr;
 wire          litedramcore_bankmachine1_fifo_in_first;
 wire          litedramcore_bankmachine1_fifo_in_last;
-wire          litedramcore_bankmachine1_fifo_out_payload_we;
-wire   [21:0] litedramcore_bankmachine1_fifo_out_payload_addr;
+wire   [21:0] litedramcore_bankmachine1_fifo_in_payload_addr;
+wire          litedramcore_bankmachine1_fifo_in_payload_we;
 wire          litedramcore_bankmachine1_fifo_out_first;
 wire          litedramcore_bankmachine1_fifo_out_last;
-wire          litedramcore_bankmachine1_sink_sink_valid;
-wire          litedramcore_bankmachine1_sink_sink_ready;
-wire          litedramcore_bankmachine1_sink_sink_first;
-wire          litedramcore_bankmachine1_sink_sink_last;
-wire          litedramcore_bankmachine1_sink_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine1_sink_sink_payload_addr;
-wire          litedramcore_bankmachine1_source_source_valid;
-wire          litedramcore_bankmachine1_source_source_ready;
-wire          litedramcore_bankmachine1_source_source_first;
-wire          litedramcore_bankmachine1_source_source_last;
-wire          litedramcore_bankmachine1_source_source_payload_we;
-wire   [21:0] litedramcore_bankmachine1_source_source_payload_addr;
-wire          litedramcore_bankmachine1_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine1_pipe_valid_sink_ready;
+wire   [21:0] litedramcore_bankmachine1_fifo_out_payload_addr;
+wire          litedramcore_bankmachine1_fifo_out_payload_we;
+reg     [4:0] litedramcore_bankmachine1_level = 5'd0;
+reg     [2:0] litedramcore_bankmachine1_next_state = 3'd0;
 wire          litedramcore_bankmachine1_pipe_valid_sink_first;
 wire          litedramcore_bankmachine1_pipe_valid_sink_last;
-wire          litedramcore_bankmachine1_pipe_valid_sink_payload_we;
 wire   [21:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine1_pipe_valid_source_ready;
+wire          litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+wire          litedramcore_bankmachine1_pipe_valid_sink_ready;
+wire          litedramcore_bankmachine1_pipe_valid_sink_valid;
 reg           litedramcore_bankmachine1_pipe_valid_source_first = 1'd0;
 reg           litedramcore_bankmachine1_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0;
 reg    [21:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 22'd0;
+reg           litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0;
+wire          litedramcore_bankmachine1_pipe_valid_source_ready;
+reg           litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0;
+reg     [3:0] litedramcore_bankmachine1_produce = 4'd0;
+wire    [3:0] litedramcore_bankmachine1_rdport_adr;
+wire   [24:0] litedramcore_bankmachine1_rdport_dat_r;
+reg           litedramcore_bankmachine1_refresh_gnt = 1'd0;
+wire          litedramcore_bankmachine1_refresh_req;
+reg           litedramcore_bankmachine1_replace = 1'd0;
+wire   [21:0] litedramcore_bankmachine1_req_addr;
+wire          litedramcore_bankmachine1_req_lock;
+reg           litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire          litedramcore_bankmachine1_req_ready;
+wire          litedramcore_bankmachine1_req_valid;
+reg           litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+wire          litedramcore_bankmachine1_req_we;
 reg    [14:0] litedramcore_bankmachine1_row = 15'd0;
-reg           litedramcore_bankmachine1_row_opened = 1'd0;
-wire          litedramcore_bankmachine1_row_hit;
-reg           litedramcore_bankmachine1_row_open = 1'd0;
 reg           litedramcore_bankmachine1_row_close = 1'd0;
 reg           litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine1_twtpcon_valid;
-reg           litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine1_trccon_valid;
-reg           litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg     [1:0] litedramcore_bankmachine1_trccon_count = 2'd0;
-wire          litedramcore_bankmachine1_trascon_valid;
-reg           litedramcore_bankmachine1_trascon_ready = 1'd0;
+wire          litedramcore_bankmachine1_row_hit;
+reg           litedramcore_bankmachine1_row_open = 1'd0;
+reg           litedramcore_bankmachine1_row_opened = 1'd0;
+reg           litedramcore_bankmachine1_sink_first = 1'd0;
+reg           litedramcore_bankmachine1_sink_last = 1'd0;
+wire   [21:0] litedramcore_bankmachine1_sink_payload_addr;
+wire          litedramcore_bankmachine1_sink_payload_we;
+wire          litedramcore_bankmachine1_sink_ready;
+wire          litedramcore_bankmachine1_sink_sink_first;
+wire          litedramcore_bankmachine1_sink_sink_last;
+wire   [21:0] litedramcore_bankmachine1_sink_sink_payload_addr;
+wire          litedramcore_bankmachine1_sink_sink_payload_we;
+wire          litedramcore_bankmachine1_sink_sink_ready;
+wire          litedramcore_bankmachine1_sink_sink_valid;
+wire          litedramcore_bankmachine1_sink_valid;
+wire          litedramcore_bankmachine1_source_first;
+wire          litedramcore_bankmachine1_source_last;
+wire   [21:0] litedramcore_bankmachine1_source_payload_addr;
+wire          litedramcore_bankmachine1_source_payload_we;
+wire          litedramcore_bankmachine1_source_ready;
+wire          litedramcore_bankmachine1_source_source_first;
+wire          litedramcore_bankmachine1_source_source_last;
+wire   [21:0] litedramcore_bankmachine1_source_source_payload_addr;
+wire          litedramcore_bankmachine1_source_source_payload_we;
+wire          litedramcore_bankmachine1_source_source_ready;
+wire          litedramcore_bankmachine1_source_source_valid;
+wire          litedramcore_bankmachine1_source_valid;
+reg     [2:0] litedramcore_bankmachine1_state = 3'd0;
+wire   [24:0] litedramcore_bankmachine1_syncfifo1_din;
+wire   [24:0] litedramcore_bankmachine1_syncfifo1_dout;
+wire          litedramcore_bankmachine1_syncfifo1_re;
+wire          litedramcore_bankmachine1_syncfifo1_readable;
+wire          litedramcore_bankmachine1_syncfifo1_we;
+wire          litedramcore_bankmachine1_syncfifo1_writable;
 reg     [1:0] litedramcore_bankmachine1_trascon_count = 2'd0;
-wire          litedramcore_bankmachine2_req_valid;
-wire          litedramcore_bankmachine2_req_ready;
-wire          litedramcore_bankmachine2_req_we;
-wire   [21:0] litedramcore_bankmachine2_req_addr;
-wire          litedramcore_bankmachine2_req_lock;
-reg           litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine2_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine2_refresh_req;
-reg           litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg           litedramcore_bankmachine1_trascon_ready = 1'd0;
+wire          litedramcore_bankmachine1_trascon_valid;
+reg     [1:0] litedramcore_bankmachine1_trccon_count = 2'd0;
+reg           litedramcore_bankmachine1_trccon_ready = 1'd0;
+wire          litedramcore_bankmachine1_trccon_valid;
+reg     [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
+reg           litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+wire          litedramcore_bankmachine1_twtpcon_valid;
+reg     [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0;
+wire   [24:0] litedramcore_bankmachine1_wrport_dat_r;
+wire   [24:0] litedramcore_bankmachine1_wrport_dat_w;
+wire          litedramcore_bankmachine1_wrport_we;
+reg           litedramcore_bankmachine2_auto_precharge = 1'd0;
 reg    [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0;
 wire    [2:0] litedramcore_bankmachine2_cmd_payload_ba;
 reg           litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_we = 1'd0;
 reg           litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
 reg           litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
 reg           litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine2_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine2_sink_valid;
-wire          litedramcore_bankmachine2_sink_ready;
-reg           litedramcore_bankmachine2_sink_first = 1'd0;
-reg           litedramcore_bankmachine2_sink_last = 1'd0;
-wire          litedramcore_bankmachine2_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine2_sink_payload_addr;
-wire          litedramcore_bankmachine2_source_valid;
-wire          litedramcore_bankmachine2_source_ready;
-wire          litedramcore_bankmachine2_source_first;
-wire          litedramcore_bankmachine2_source_last;
-wire          litedramcore_bankmachine2_source_payload_we;
-wire   [21:0] litedramcore_bankmachine2_source_payload_addr;
-wire          litedramcore_bankmachine2_syncfifo2_we;
-wire          litedramcore_bankmachine2_syncfifo2_writable;
-wire          litedramcore_bankmachine2_syncfifo2_re;
-wire          litedramcore_bankmachine2_syncfifo2_readable;
-wire   [24:0] litedramcore_bankmachine2_syncfifo2_din;
-wire   [24:0] litedramcore_bankmachine2_syncfifo2_dout;
-reg     [4:0] litedramcore_bankmachine2_level = 5'd0;
-reg           litedramcore_bankmachine2_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine2_produce = 4'd0;
+reg           litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg           litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg           litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg           litedramcore_bankmachine2_cmd_valid = 1'd0;
 reg     [3:0] litedramcore_bankmachine2_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0;
-wire   [24:0] litedramcore_bankmachine2_wrport_dat_r;
-wire          litedramcore_bankmachine2_wrport_we;
-wire   [24:0] litedramcore_bankmachine2_wrport_dat_w;
 wire          litedramcore_bankmachine2_do_read;
-wire    [3:0] litedramcore_bankmachine2_rdport_adr;
-wire   [24:0] litedramcore_bankmachine2_rdport_dat_r;
-wire          litedramcore_bankmachine2_fifo_in_payload_we;
-wire   [21:0] litedramcore_bankmachine2_fifo_in_payload_addr;
 wire          litedramcore_bankmachine2_fifo_in_first;
 wire          litedramcore_bankmachine2_fifo_in_last;
-wire          litedramcore_bankmachine2_fifo_out_payload_we;
-wire   [21:0] litedramcore_bankmachine2_fifo_out_payload_addr;
+wire   [21:0] litedramcore_bankmachine2_fifo_in_payload_addr;
+wire          litedramcore_bankmachine2_fifo_in_payload_we;
 wire          litedramcore_bankmachine2_fifo_out_first;
 wire          litedramcore_bankmachine2_fifo_out_last;
-wire          litedramcore_bankmachine2_sink_sink_valid;
-wire          litedramcore_bankmachine2_sink_sink_ready;
-wire          litedramcore_bankmachine2_sink_sink_first;
-wire          litedramcore_bankmachine2_sink_sink_last;
-wire          litedramcore_bankmachine2_sink_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine2_sink_sink_payload_addr;
-wire          litedramcore_bankmachine2_source_source_valid;
-wire          litedramcore_bankmachine2_source_source_ready;
-wire          litedramcore_bankmachine2_source_source_first;
-wire          litedramcore_bankmachine2_source_source_last;
-wire          litedramcore_bankmachine2_source_source_payload_we;
-wire   [21:0] litedramcore_bankmachine2_source_source_payload_addr;
-wire          litedramcore_bankmachine2_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine2_pipe_valid_sink_ready;
+wire   [21:0] litedramcore_bankmachine2_fifo_out_payload_addr;
+wire          litedramcore_bankmachine2_fifo_out_payload_we;
+reg     [4:0] litedramcore_bankmachine2_level = 5'd0;
+reg     [2:0] litedramcore_bankmachine2_next_state = 3'd0;
 wire          litedramcore_bankmachine2_pipe_valid_sink_first;
 wire          litedramcore_bankmachine2_pipe_valid_sink_last;
-wire          litedramcore_bankmachine2_pipe_valid_sink_payload_we;
 wire   [21:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine2_pipe_valid_source_ready;
+wire          litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+wire          litedramcore_bankmachine2_pipe_valid_sink_ready;
+wire          litedramcore_bankmachine2_pipe_valid_sink_valid;
 reg           litedramcore_bankmachine2_pipe_valid_source_first = 1'd0;
 reg           litedramcore_bankmachine2_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0;
 reg    [21:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 22'd0;
+reg           litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0;
+wire          litedramcore_bankmachine2_pipe_valid_source_ready;
+reg           litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0;
+reg     [3:0] litedramcore_bankmachine2_produce = 4'd0;
+wire    [3:0] litedramcore_bankmachine2_rdport_adr;
+wire   [24:0] litedramcore_bankmachine2_rdport_dat_r;
+reg           litedramcore_bankmachine2_refresh_gnt = 1'd0;
+wire          litedramcore_bankmachine2_refresh_req;
+reg           litedramcore_bankmachine2_replace = 1'd0;
+wire   [21:0] litedramcore_bankmachine2_req_addr;
+wire          litedramcore_bankmachine2_req_lock;
+reg           litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire          litedramcore_bankmachine2_req_ready;
+wire          litedramcore_bankmachine2_req_valid;
+reg           litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+wire          litedramcore_bankmachine2_req_we;
 reg    [14:0] litedramcore_bankmachine2_row = 15'd0;
-reg           litedramcore_bankmachine2_row_opened = 1'd0;
-wire          litedramcore_bankmachine2_row_hit;
-reg           litedramcore_bankmachine2_row_open = 1'd0;
 reg           litedramcore_bankmachine2_row_close = 1'd0;
 reg           litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine2_twtpcon_valid;
-reg           litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine2_trccon_valid;
-reg           litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg     [1:0] litedramcore_bankmachine2_trccon_count = 2'd0;
-wire          litedramcore_bankmachine2_trascon_valid;
-reg           litedramcore_bankmachine2_trascon_ready = 1'd0;
+wire          litedramcore_bankmachine2_row_hit;
+reg           litedramcore_bankmachine2_row_open = 1'd0;
+reg           litedramcore_bankmachine2_row_opened = 1'd0;
+reg           litedramcore_bankmachine2_sink_first = 1'd0;
+reg           litedramcore_bankmachine2_sink_last = 1'd0;
+wire   [21:0] litedramcore_bankmachine2_sink_payload_addr;
+wire          litedramcore_bankmachine2_sink_payload_we;
+wire          litedramcore_bankmachine2_sink_ready;
+wire          litedramcore_bankmachine2_sink_sink_first;
+wire          litedramcore_bankmachine2_sink_sink_last;
+wire   [21:0] litedramcore_bankmachine2_sink_sink_payload_addr;
+wire          litedramcore_bankmachine2_sink_sink_payload_we;
+wire          litedramcore_bankmachine2_sink_sink_ready;
+wire          litedramcore_bankmachine2_sink_sink_valid;
+wire          litedramcore_bankmachine2_sink_valid;
+wire          litedramcore_bankmachine2_source_first;
+wire          litedramcore_bankmachine2_source_last;
+wire   [21:0] litedramcore_bankmachine2_source_payload_addr;
+wire          litedramcore_bankmachine2_source_payload_we;
+wire          litedramcore_bankmachine2_source_ready;
+wire          litedramcore_bankmachine2_source_source_first;
+wire          litedramcore_bankmachine2_source_source_last;
+wire   [21:0] litedramcore_bankmachine2_source_source_payload_addr;
+wire          litedramcore_bankmachine2_source_source_payload_we;
+wire          litedramcore_bankmachine2_source_source_ready;
+wire          litedramcore_bankmachine2_source_source_valid;
+wire          litedramcore_bankmachine2_source_valid;
+reg     [2:0] litedramcore_bankmachine2_state = 3'd0;
+wire   [24:0] litedramcore_bankmachine2_syncfifo2_din;
+wire   [24:0] litedramcore_bankmachine2_syncfifo2_dout;
+wire          litedramcore_bankmachine2_syncfifo2_re;
+wire          litedramcore_bankmachine2_syncfifo2_readable;
+wire          litedramcore_bankmachine2_syncfifo2_we;
+wire          litedramcore_bankmachine2_syncfifo2_writable;
 reg     [1:0] litedramcore_bankmachine2_trascon_count = 2'd0;
-wire          litedramcore_bankmachine3_req_valid;
-wire          litedramcore_bankmachine3_req_ready;
-wire          litedramcore_bankmachine3_req_we;
-wire   [21:0] litedramcore_bankmachine3_req_addr;
-wire          litedramcore_bankmachine3_req_lock;
-reg           litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine3_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine3_refresh_req;
-reg           litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg           litedramcore_bankmachine2_trascon_ready = 1'd0;
+wire          litedramcore_bankmachine2_trascon_valid;
+reg     [1:0] litedramcore_bankmachine2_trccon_count = 2'd0;
+reg           litedramcore_bankmachine2_trccon_ready = 1'd0;
+wire          litedramcore_bankmachine2_trccon_valid;
+reg     [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
+reg           litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+wire          litedramcore_bankmachine2_twtpcon_valid;
+reg     [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0;
+wire   [24:0] litedramcore_bankmachine2_wrport_dat_r;
+wire   [24:0] litedramcore_bankmachine2_wrport_dat_w;
+wire          litedramcore_bankmachine2_wrport_we;
+reg           litedramcore_bankmachine3_auto_precharge = 1'd0;
 reg    [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0;
 wire    [2:0] litedramcore_bankmachine3_cmd_payload_ba;
 reg           litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_we = 1'd0;
 reg           litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
 reg           litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
 reg           litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine3_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine3_sink_valid;
-wire          litedramcore_bankmachine3_sink_ready;
-reg           litedramcore_bankmachine3_sink_first = 1'd0;
-reg           litedramcore_bankmachine3_sink_last = 1'd0;
-wire          litedramcore_bankmachine3_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine3_sink_payload_addr;
-wire          litedramcore_bankmachine3_source_valid;
-wire          litedramcore_bankmachine3_source_ready;
-wire          litedramcore_bankmachine3_source_first;
-wire          litedramcore_bankmachine3_source_last;
-wire          litedramcore_bankmachine3_source_payload_we;
-wire   [21:0] litedramcore_bankmachine3_source_payload_addr;
-wire          litedramcore_bankmachine3_syncfifo3_we;
-wire          litedramcore_bankmachine3_syncfifo3_writable;
-wire          litedramcore_bankmachine3_syncfifo3_re;
-wire          litedramcore_bankmachine3_syncfifo3_readable;
-wire   [24:0] litedramcore_bankmachine3_syncfifo3_din;
-wire   [24:0] litedramcore_bankmachine3_syncfifo3_dout;
-reg     [4:0] litedramcore_bankmachine3_level = 5'd0;
-reg           litedramcore_bankmachine3_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine3_produce = 4'd0;
+reg           litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg           litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg           litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg           litedramcore_bankmachine3_cmd_valid = 1'd0;
 reg     [3:0] litedramcore_bankmachine3_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0;
-wire   [24:0] litedramcore_bankmachine3_wrport_dat_r;
-wire          litedramcore_bankmachine3_wrport_we;
-wire   [24:0] litedramcore_bankmachine3_wrport_dat_w;
 wire          litedramcore_bankmachine3_do_read;
-wire    [3:0] litedramcore_bankmachine3_rdport_adr;
-wire   [24:0] litedramcore_bankmachine3_rdport_dat_r;
-wire          litedramcore_bankmachine3_fifo_in_payload_we;
-wire   [21:0] litedramcore_bankmachine3_fifo_in_payload_addr;
 wire          litedramcore_bankmachine3_fifo_in_first;
 wire          litedramcore_bankmachine3_fifo_in_last;
-wire          litedramcore_bankmachine3_fifo_out_payload_we;
-wire   [21:0] litedramcore_bankmachine3_fifo_out_payload_addr;
+wire   [21:0] litedramcore_bankmachine3_fifo_in_payload_addr;
+wire          litedramcore_bankmachine3_fifo_in_payload_we;
 wire          litedramcore_bankmachine3_fifo_out_first;
 wire          litedramcore_bankmachine3_fifo_out_last;
-wire          litedramcore_bankmachine3_sink_sink_valid;
-wire          litedramcore_bankmachine3_sink_sink_ready;
-wire          litedramcore_bankmachine3_sink_sink_first;
-wire          litedramcore_bankmachine3_sink_sink_last;
-wire          litedramcore_bankmachine3_sink_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine3_sink_sink_payload_addr;
-wire          litedramcore_bankmachine3_source_source_valid;
-wire          litedramcore_bankmachine3_source_source_ready;
-wire          litedramcore_bankmachine3_source_source_first;
-wire          litedramcore_bankmachine3_source_source_last;
-wire          litedramcore_bankmachine3_source_source_payload_we;
-wire   [21:0] litedramcore_bankmachine3_source_source_payload_addr;
-wire          litedramcore_bankmachine3_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine3_pipe_valid_sink_ready;
+wire   [21:0] litedramcore_bankmachine3_fifo_out_payload_addr;
+wire          litedramcore_bankmachine3_fifo_out_payload_we;
+reg     [4:0] litedramcore_bankmachine3_level = 5'd0;
+reg     [2:0] litedramcore_bankmachine3_next_state = 3'd0;
 wire          litedramcore_bankmachine3_pipe_valid_sink_first;
 wire          litedramcore_bankmachine3_pipe_valid_sink_last;
-wire          litedramcore_bankmachine3_pipe_valid_sink_payload_we;
 wire   [21:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine3_pipe_valid_source_ready;
+wire          litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+wire          litedramcore_bankmachine3_pipe_valid_sink_ready;
+wire          litedramcore_bankmachine3_pipe_valid_sink_valid;
 reg           litedramcore_bankmachine3_pipe_valid_source_first = 1'd0;
 reg           litedramcore_bankmachine3_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0;
 reg    [21:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 22'd0;
+reg           litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0;
+wire          litedramcore_bankmachine3_pipe_valid_source_ready;
+reg           litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0;
+reg     [3:0] litedramcore_bankmachine3_produce = 4'd0;
+wire    [3:0] litedramcore_bankmachine3_rdport_adr;
+wire   [24:0] litedramcore_bankmachine3_rdport_dat_r;
+reg           litedramcore_bankmachine3_refresh_gnt = 1'd0;
+wire          litedramcore_bankmachine3_refresh_req;
+reg           litedramcore_bankmachine3_replace = 1'd0;
+wire   [21:0] litedramcore_bankmachine3_req_addr;
+wire          litedramcore_bankmachine3_req_lock;
+reg           litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire          litedramcore_bankmachine3_req_ready;
+wire          litedramcore_bankmachine3_req_valid;
+reg           litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+wire          litedramcore_bankmachine3_req_we;
 reg    [14:0] litedramcore_bankmachine3_row = 15'd0;
-reg           litedramcore_bankmachine3_row_opened = 1'd0;
-wire          litedramcore_bankmachine3_row_hit;
-reg           litedramcore_bankmachine3_row_open = 1'd0;
 reg           litedramcore_bankmachine3_row_close = 1'd0;
 reg           litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine3_twtpcon_valid;
-reg           litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine3_trccon_valid;
-reg           litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg     [1:0] litedramcore_bankmachine3_trccon_count = 2'd0;
-wire          litedramcore_bankmachine3_trascon_valid;
-reg           litedramcore_bankmachine3_trascon_ready = 1'd0;
+wire          litedramcore_bankmachine3_row_hit;
+reg           litedramcore_bankmachine3_row_open = 1'd0;
+reg           litedramcore_bankmachine3_row_opened = 1'd0;
+reg           litedramcore_bankmachine3_sink_first = 1'd0;
+reg           litedramcore_bankmachine3_sink_last = 1'd0;
+wire   [21:0] litedramcore_bankmachine3_sink_payload_addr;
+wire          litedramcore_bankmachine3_sink_payload_we;
+wire          litedramcore_bankmachine3_sink_ready;
+wire          litedramcore_bankmachine3_sink_sink_first;
+wire          litedramcore_bankmachine3_sink_sink_last;
+wire   [21:0] litedramcore_bankmachine3_sink_sink_payload_addr;
+wire          litedramcore_bankmachine3_sink_sink_payload_we;
+wire          litedramcore_bankmachine3_sink_sink_ready;
+wire          litedramcore_bankmachine3_sink_sink_valid;
+wire          litedramcore_bankmachine3_sink_valid;
+wire          litedramcore_bankmachine3_source_first;
+wire          litedramcore_bankmachine3_source_last;
+wire   [21:0] litedramcore_bankmachine3_source_payload_addr;
+wire          litedramcore_bankmachine3_source_payload_we;
+wire          litedramcore_bankmachine3_source_ready;
+wire          litedramcore_bankmachine3_source_source_first;
+wire          litedramcore_bankmachine3_source_source_last;
+wire   [21:0] litedramcore_bankmachine3_source_source_payload_addr;
+wire          litedramcore_bankmachine3_source_source_payload_we;
+wire          litedramcore_bankmachine3_source_source_ready;
+wire          litedramcore_bankmachine3_source_source_valid;
+wire          litedramcore_bankmachine3_source_valid;
+reg     [2:0] litedramcore_bankmachine3_state = 3'd0;
+wire   [24:0] litedramcore_bankmachine3_syncfifo3_din;
+wire   [24:0] litedramcore_bankmachine3_syncfifo3_dout;
+wire          litedramcore_bankmachine3_syncfifo3_re;
+wire          litedramcore_bankmachine3_syncfifo3_readable;
+wire          litedramcore_bankmachine3_syncfifo3_we;
+wire          litedramcore_bankmachine3_syncfifo3_writable;
 reg     [1:0] litedramcore_bankmachine3_trascon_count = 2'd0;
-wire          litedramcore_bankmachine4_req_valid;
-wire          litedramcore_bankmachine4_req_ready;
-wire          litedramcore_bankmachine4_req_we;
-wire   [21:0] litedramcore_bankmachine4_req_addr;
-wire          litedramcore_bankmachine4_req_lock;
-reg           litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine4_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine4_refresh_req;
-reg           litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg           litedramcore_bankmachine3_trascon_ready = 1'd0;
+wire          litedramcore_bankmachine3_trascon_valid;
+reg     [1:0] litedramcore_bankmachine3_trccon_count = 2'd0;
+reg           litedramcore_bankmachine3_trccon_ready = 1'd0;
+wire          litedramcore_bankmachine3_trccon_valid;
+reg     [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
+reg           litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+wire          litedramcore_bankmachine3_twtpcon_valid;
+reg     [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0;
+wire   [24:0] litedramcore_bankmachine3_wrport_dat_r;
+wire   [24:0] litedramcore_bankmachine3_wrport_dat_w;
+wire          litedramcore_bankmachine3_wrport_we;
+reg           litedramcore_bankmachine4_auto_precharge = 1'd0;
 reg    [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0;
 wire    [2:0] litedramcore_bankmachine4_cmd_payload_ba;
 reg           litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_we = 1'd0;
 reg           litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
 reg           litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
 reg           litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine4_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine4_sink_valid;
-wire          litedramcore_bankmachine4_sink_ready;
-reg           litedramcore_bankmachine4_sink_first = 1'd0;
-reg           litedramcore_bankmachine4_sink_last = 1'd0;
-wire          litedramcore_bankmachine4_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine4_sink_payload_addr;
-wire          litedramcore_bankmachine4_source_valid;
-wire          litedramcore_bankmachine4_source_ready;
-wire          litedramcore_bankmachine4_source_first;
-wire          litedramcore_bankmachine4_source_last;
-wire          litedramcore_bankmachine4_source_payload_we;
-wire   [21:0] litedramcore_bankmachine4_source_payload_addr;
-wire          litedramcore_bankmachine4_syncfifo4_we;
-wire          litedramcore_bankmachine4_syncfifo4_writable;
-wire          litedramcore_bankmachine4_syncfifo4_re;
-wire          litedramcore_bankmachine4_syncfifo4_readable;
-wire   [24:0] litedramcore_bankmachine4_syncfifo4_din;
-wire   [24:0] litedramcore_bankmachine4_syncfifo4_dout;
-reg     [4:0] litedramcore_bankmachine4_level = 5'd0;
-reg           litedramcore_bankmachine4_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine4_produce = 4'd0;
+reg           litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg           litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg           litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg           litedramcore_bankmachine4_cmd_valid = 1'd0;
 reg     [3:0] litedramcore_bankmachine4_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0;
-wire   [24:0] litedramcore_bankmachine4_wrport_dat_r;
-wire          litedramcore_bankmachine4_wrport_we;
-wire   [24:0] litedramcore_bankmachine4_wrport_dat_w;
 wire          litedramcore_bankmachine4_do_read;
-wire    [3:0] litedramcore_bankmachine4_rdport_adr;
-wire   [24:0] litedramcore_bankmachine4_rdport_dat_r;
-wire          litedramcore_bankmachine4_fifo_in_payload_we;
-wire   [21:0] litedramcore_bankmachine4_fifo_in_payload_addr;
 wire          litedramcore_bankmachine4_fifo_in_first;
 wire          litedramcore_bankmachine4_fifo_in_last;
-wire          litedramcore_bankmachine4_fifo_out_payload_we;
-wire   [21:0] litedramcore_bankmachine4_fifo_out_payload_addr;
+wire   [21:0] litedramcore_bankmachine4_fifo_in_payload_addr;
+wire          litedramcore_bankmachine4_fifo_in_payload_we;
 wire          litedramcore_bankmachine4_fifo_out_first;
 wire          litedramcore_bankmachine4_fifo_out_last;
-wire          litedramcore_bankmachine4_sink_sink_valid;
-wire          litedramcore_bankmachine4_sink_sink_ready;
-wire          litedramcore_bankmachine4_sink_sink_first;
-wire          litedramcore_bankmachine4_sink_sink_last;
-wire          litedramcore_bankmachine4_sink_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine4_sink_sink_payload_addr;
-wire          litedramcore_bankmachine4_source_source_valid;
-wire          litedramcore_bankmachine4_source_source_ready;
-wire          litedramcore_bankmachine4_source_source_first;
-wire          litedramcore_bankmachine4_source_source_last;
-wire          litedramcore_bankmachine4_source_source_payload_we;
-wire   [21:0] litedramcore_bankmachine4_source_source_payload_addr;
-wire          litedramcore_bankmachine4_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine4_pipe_valid_sink_ready;
+wire   [21:0] litedramcore_bankmachine4_fifo_out_payload_addr;
+wire          litedramcore_bankmachine4_fifo_out_payload_we;
+reg     [4:0] litedramcore_bankmachine4_level = 5'd0;
+reg     [2:0] litedramcore_bankmachine4_next_state = 3'd0;
 wire          litedramcore_bankmachine4_pipe_valid_sink_first;
 wire          litedramcore_bankmachine4_pipe_valid_sink_last;
-wire          litedramcore_bankmachine4_pipe_valid_sink_payload_we;
 wire   [21:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine4_pipe_valid_source_ready;
+wire          litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+wire          litedramcore_bankmachine4_pipe_valid_sink_ready;
+wire          litedramcore_bankmachine4_pipe_valid_sink_valid;
 reg           litedramcore_bankmachine4_pipe_valid_source_first = 1'd0;
 reg           litedramcore_bankmachine4_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0;
 reg    [21:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 22'd0;
+reg           litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0;
+wire          litedramcore_bankmachine4_pipe_valid_source_ready;
+reg           litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0;
+reg     [3:0] litedramcore_bankmachine4_produce = 4'd0;
+wire    [3:0] litedramcore_bankmachine4_rdport_adr;
+wire   [24:0] litedramcore_bankmachine4_rdport_dat_r;
+reg           litedramcore_bankmachine4_refresh_gnt = 1'd0;
+wire          litedramcore_bankmachine4_refresh_req;
+reg           litedramcore_bankmachine4_replace = 1'd0;
+wire   [21:0] litedramcore_bankmachine4_req_addr;
+wire          litedramcore_bankmachine4_req_lock;
+reg           litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire          litedramcore_bankmachine4_req_ready;
+wire          litedramcore_bankmachine4_req_valid;
+reg           litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+wire          litedramcore_bankmachine4_req_we;
 reg    [14:0] litedramcore_bankmachine4_row = 15'd0;
-reg           litedramcore_bankmachine4_row_opened = 1'd0;
-wire          litedramcore_bankmachine4_row_hit;
-reg           litedramcore_bankmachine4_row_open = 1'd0;
 reg           litedramcore_bankmachine4_row_close = 1'd0;
 reg           litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine4_twtpcon_valid;
-reg           litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine4_trccon_valid;
-reg           litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg     [1:0] litedramcore_bankmachine4_trccon_count = 2'd0;
-wire          litedramcore_bankmachine4_trascon_valid;
-reg           litedramcore_bankmachine4_trascon_ready = 1'd0;
+wire          litedramcore_bankmachine4_row_hit;
+reg           litedramcore_bankmachine4_row_open = 1'd0;
+reg           litedramcore_bankmachine4_row_opened = 1'd0;
+reg           litedramcore_bankmachine4_sink_first = 1'd0;
+reg           litedramcore_bankmachine4_sink_last = 1'd0;
+wire   [21:0] litedramcore_bankmachine4_sink_payload_addr;
+wire          litedramcore_bankmachine4_sink_payload_we;
+wire          litedramcore_bankmachine4_sink_ready;
+wire          litedramcore_bankmachine4_sink_sink_first;
+wire          litedramcore_bankmachine4_sink_sink_last;
+wire   [21:0] litedramcore_bankmachine4_sink_sink_payload_addr;
+wire          litedramcore_bankmachine4_sink_sink_payload_we;
+wire          litedramcore_bankmachine4_sink_sink_ready;
+wire          litedramcore_bankmachine4_sink_sink_valid;
+wire          litedramcore_bankmachine4_sink_valid;
+wire          litedramcore_bankmachine4_source_first;
+wire          litedramcore_bankmachine4_source_last;
+wire   [21:0] litedramcore_bankmachine4_source_payload_addr;
+wire          litedramcore_bankmachine4_source_payload_we;
+wire          litedramcore_bankmachine4_source_ready;
+wire          litedramcore_bankmachine4_source_source_first;
+wire          litedramcore_bankmachine4_source_source_last;
+wire   [21:0] litedramcore_bankmachine4_source_source_payload_addr;
+wire          litedramcore_bankmachine4_source_source_payload_we;
+wire          litedramcore_bankmachine4_source_source_ready;
+wire          litedramcore_bankmachine4_source_source_valid;
+wire          litedramcore_bankmachine4_source_valid;
+reg     [2:0] litedramcore_bankmachine4_state = 3'd0;
+wire   [24:0] litedramcore_bankmachine4_syncfifo4_din;
+wire   [24:0] litedramcore_bankmachine4_syncfifo4_dout;
+wire          litedramcore_bankmachine4_syncfifo4_re;
+wire          litedramcore_bankmachine4_syncfifo4_readable;
+wire          litedramcore_bankmachine4_syncfifo4_we;
+wire          litedramcore_bankmachine4_syncfifo4_writable;
 reg     [1:0] litedramcore_bankmachine4_trascon_count = 2'd0;
-wire          litedramcore_bankmachine5_req_valid;
-wire          litedramcore_bankmachine5_req_ready;
-wire          litedramcore_bankmachine5_req_we;
-wire   [21:0] litedramcore_bankmachine5_req_addr;
-wire          litedramcore_bankmachine5_req_lock;
-reg           litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine5_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine5_refresh_req;
-reg           litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg           litedramcore_bankmachine4_trascon_ready = 1'd0;
+wire          litedramcore_bankmachine4_trascon_valid;
+reg     [1:0] litedramcore_bankmachine4_trccon_count = 2'd0;
+reg           litedramcore_bankmachine4_trccon_ready = 1'd0;
+wire          litedramcore_bankmachine4_trccon_valid;
+reg     [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
+reg           litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+wire          litedramcore_bankmachine4_twtpcon_valid;
+reg     [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0;
+wire   [24:0] litedramcore_bankmachine4_wrport_dat_r;
+wire   [24:0] litedramcore_bankmachine4_wrport_dat_w;
+wire          litedramcore_bankmachine4_wrport_we;
+reg           litedramcore_bankmachine5_auto_precharge = 1'd0;
 reg    [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0;
 wire    [2:0] litedramcore_bankmachine5_cmd_payload_ba;
 reg           litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_we = 1'd0;
 reg           litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
 reg           litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
 reg           litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine5_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine5_sink_valid;
-wire          litedramcore_bankmachine5_sink_ready;
-reg           litedramcore_bankmachine5_sink_first = 1'd0;
-reg           litedramcore_bankmachine5_sink_last = 1'd0;
-wire          litedramcore_bankmachine5_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine5_sink_payload_addr;
-wire          litedramcore_bankmachine5_source_valid;
-wire          litedramcore_bankmachine5_source_ready;
-wire          litedramcore_bankmachine5_source_first;
-wire          litedramcore_bankmachine5_source_last;
-wire          litedramcore_bankmachine5_source_payload_we;
-wire   [21:0] litedramcore_bankmachine5_source_payload_addr;
-wire          litedramcore_bankmachine5_syncfifo5_we;
-wire          litedramcore_bankmachine5_syncfifo5_writable;
-wire          litedramcore_bankmachine5_syncfifo5_re;
-wire          litedramcore_bankmachine5_syncfifo5_readable;
-wire   [24:0] litedramcore_bankmachine5_syncfifo5_din;
-wire   [24:0] litedramcore_bankmachine5_syncfifo5_dout;
-reg     [4:0] litedramcore_bankmachine5_level = 5'd0;
-reg           litedramcore_bankmachine5_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine5_produce = 4'd0;
+reg           litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg           litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg           litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg           litedramcore_bankmachine5_cmd_valid = 1'd0;
 reg     [3:0] litedramcore_bankmachine5_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0;
-wire   [24:0] litedramcore_bankmachine5_wrport_dat_r;
-wire          litedramcore_bankmachine5_wrport_we;
-wire   [24:0] litedramcore_bankmachine5_wrport_dat_w;
-wire          litedramcore_bankmachine5_do_read;
-wire    [3:0] litedramcore_bankmachine5_rdport_adr;
-wire   [24:0] litedramcore_bankmachine5_rdport_dat_r;
-wire          litedramcore_bankmachine5_fifo_in_payload_we;
-wire   [21:0] litedramcore_bankmachine5_fifo_in_payload_addr;
+wire          litedramcore_bankmachine5_do_read;
 wire          litedramcore_bankmachine5_fifo_in_first;
 wire          litedramcore_bankmachine5_fifo_in_last;
-wire          litedramcore_bankmachine5_fifo_out_payload_we;
-wire   [21:0] litedramcore_bankmachine5_fifo_out_payload_addr;
+wire   [21:0] litedramcore_bankmachine5_fifo_in_payload_addr;
+wire          litedramcore_bankmachine5_fifo_in_payload_we;
 wire          litedramcore_bankmachine5_fifo_out_first;
 wire          litedramcore_bankmachine5_fifo_out_last;
-wire          litedramcore_bankmachine5_sink_sink_valid;
-wire          litedramcore_bankmachine5_sink_sink_ready;
-wire          litedramcore_bankmachine5_sink_sink_first;
-wire          litedramcore_bankmachine5_sink_sink_last;
-wire          litedramcore_bankmachine5_sink_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine5_sink_sink_payload_addr;
-wire          litedramcore_bankmachine5_source_source_valid;
-wire          litedramcore_bankmachine5_source_source_ready;
-wire          litedramcore_bankmachine5_source_source_first;
-wire          litedramcore_bankmachine5_source_source_last;
-wire          litedramcore_bankmachine5_source_source_payload_we;
-wire   [21:0] litedramcore_bankmachine5_source_source_payload_addr;
-wire          litedramcore_bankmachine5_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine5_pipe_valid_sink_ready;
+wire   [21:0] litedramcore_bankmachine5_fifo_out_payload_addr;
+wire          litedramcore_bankmachine5_fifo_out_payload_we;
+reg     [4:0] litedramcore_bankmachine5_level = 5'd0;
+reg     [2:0] litedramcore_bankmachine5_next_state = 3'd0;
 wire          litedramcore_bankmachine5_pipe_valid_sink_first;
 wire          litedramcore_bankmachine5_pipe_valid_sink_last;
-wire          litedramcore_bankmachine5_pipe_valid_sink_payload_we;
 wire   [21:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine5_pipe_valid_source_ready;
+wire          litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+wire          litedramcore_bankmachine5_pipe_valid_sink_ready;
+wire          litedramcore_bankmachine5_pipe_valid_sink_valid;
 reg           litedramcore_bankmachine5_pipe_valid_source_first = 1'd0;
 reg           litedramcore_bankmachine5_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0;
 reg    [21:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 22'd0;
+reg           litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0;
+wire          litedramcore_bankmachine5_pipe_valid_source_ready;
+reg           litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0;
+reg     [3:0] litedramcore_bankmachine5_produce = 4'd0;
+wire    [3:0] litedramcore_bankmachine5_rdport_adr;
+wire   [24:0] litedramcore_bankmachine5_rdport_dat_r;
+reg           litedramcore_bankmachine5_refresh_gnt = 1'd0;
+wire          litedramcore_bankmachine5_refresh_req;
+reg           litedramcore_bankmachine5_replace = 1'd0;
+wire   [21:0] litedramcore_bankmachine5_req_addr;
+wire          litedramcore_bankmachine5_req_lock;
+reg           litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire          litedramcore_bankmachine5_req_ready;
+wire          litedramcore_bankmachine5_req_valid;
+reg           litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+wire          litedramcore_bankmachine5_req_we;
 reg    [14:0] litedramcore_bankmachine5_row = 15'd0;
-reg           litedramcore_bankmachine5_row_opened = 1'd0;
-wire          litedramcore_bankmachine5_row_hit;
-reg           litedramcore_bankmachine5_row_open = 1'd0;
 reg           litedramcore_bankmachine5_row_close = 1'd0;
 reg           litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine5_twtpcon_valid;
-reg           litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine5_trccon_valid;
-reg           litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg     [1:0] litedramcore_bankmachine5_trccon_count = 2'd0;
-wire          litedramcore_bankmachine5_trascon_valid;
-reg           litedramcore_bankmachine5_trascon_ready = 1'd0;
+wire          litedramcore_bankmachine5_row_hit;
+reg           litedramcore_bankmachine5_row_open = 1'd0;
+reg           litedramcore_bankmachine5_row_opened = 1'd0;
+reg           litedramcore_bankmachine5_sink_first = 1'd0;
+reg           litedramcore_bankmachine5_sink_last = 1'd0;
+wire   [21:0] litedramcore_bankmachine5_sink_payload_addr;
+wire          litedramcore_bankmachine5_sink_payload_we;
+wire          litedramcore_bankmachine5_sink_ready;
+wire          litedramcore_bankmachine5_sink_sink_first;
+wire          litedramcore_bankmachine5_sink_sink_last;
+wire   [21:0] litedramcore_bankmachine5_sink_sink_payload_addr;
+wire          litedramcore_bankmachine5_sink_sink_payload_we;
+wire          litedramcore_bankmachine5_sink_sink_ready;
+wire          litedramcore_bankmachine5_sink_sink_valid;
+wire          litedramcore_bankmachine5_sink_valid;
+wire          litedramcore_bankmachine5_source_first;
+wire          litedramcore_bankmachine5_source_last;
+wire   [21:0] litedramcore_bankmachine5_source_payload_addr;
+wire          litedramcore_bankmachine5_source_payload_we;
+wire          litedramcore_bankmachine5_source_ready;
+wire          litedramcore_bankmachine5_source_source_first;
+wire          litedramcore_bankmachine5_source_source_last;
+wire   [21:0] litedramcore_bankmachine5_source_source_payload_addr;
+wire          litedramcore_bankmachine5_source_source_payload_we;
+wire          litedramcore_bankmachine5_source_source_ready;
+wire          litedramcore_bankmachine5_source_source_valid;
+wire          litedramcore_bankmachine5_source_valid;
+reg     [2:0] litedramcore_bankmachine5_state = 3'd0;
+wire   [24:0] litedramcore_bankmachine5_syncfifo5_din;
+wire   [24:0] litedramcore_bankmachine5_syncfifo5_dout;
+wire          litedramcore_bankmachine5_syncfifo5_re;
+wire          litedramcore_bankmachine5_syncfifo5_readable;
+wire          litedramcore_bankmachine5_syncfifo5_we;
+wire          litedramcore_bankmachine5_syncfifo5_writable;
 reg     [1:0] litedramcore_bankmachine5_trascon_count = 2'd0;
-wire          litedramcore_bankmachine6_req_valid;
-wire          litedramcore_bankmachine6_req_ready;
-wire          litedramcore_bankmachine6_req_we;
-wire   [21:0] litedramcore_bankmachine6_req_addr;
-wire          litedramcore_bankmachine6_req_lock;
-reg           litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine6_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine6_refresh_req;
-reg           litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg           litedramcore_bankmachine5_trascon_ready = 1'd0;
+wire          litedramcore_bankmachine5_trascon_valid;
+reg     [1:0] litedramcore_bankmachine5_trccon_count = 2'd0;
+reg           litedramcore_bankmachine5_trccon_ready = 1'd0;
+wire          litedramcore_bankmachine5_trccon_valid;
+reg     [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
+reg           litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+wire          litedramcore_bankmachine5_twtpcon_valid;
+reg     [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0;
+wire   [24:0] litedramcore_bankmachine5_wrport_dat_r;
+wire   [24:0] litedramcore_bankmachine5_wrport_dat_w;
+wire          litedramcore_bankmachine5_wrport_we;
+reg           litedramcore_bankmachine6_auto_precharge = 1'd0;
 reg    [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0;
 wire    [2:0] litedramcore_bankmachine6_cmd_payload_ba;
 reg           litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_we = 1'd0;
 reg           litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
 reg           litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
 reg           litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine6_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine6_sink_valid;
-wire          litedramcore_bankmachine6_sink_ready;
-reg           litedramcore_bankmachine6_sink_first = 1'd0;
-reg           litedramcore_bankmachine6_sink_last = 1'd0;
-wire          litedramcore_bankmachine6_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine6_sink_payload_addr;
-wire          litedramcore_bankmachine6_source_valid;
-wire          litedramcore_bankmachine6_source_ready;
-wire          litedramcore_bankmachine6_source_first;
-wire          litedramcore_bankmachine6_source_last;
-wire          litedramcore_bankmachine6_source_payload_we;
-wire   [21:0] litedramcore_bankmachine6_source_payload_addr;
-wire          litedramcore_bankmachine6_syncfifo6_we;
-wire          litedramcore_bankmachine6_syncfifo6_writable;
-wire          litedramcore_bankmachine6_syncfifo6_re;
-wire          litedramcore_bankmachine6_syncfifo6_readable;
-wire   [24:0] litedramcore_bankmachine6_syncfifo6_din;
-wire   [24:0] litedramcore_bankmachine6_syncfifo6_dout;
-reg     [4:0] litedramcore_bankmachine6_level = 5'd0;
-reg           litedramcore_bankmachine6_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine6_produce = 4'd0;
+reg           litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg           litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg           litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg           litedramcore_bankmachine6_cmd_valid = 1'd0;
 reg     [3:0] litedramcore_bankmachine6_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0;
-wire   [24:0] litedramcore_bankmachine6_wrport_dat_r;
-wire          litedramcore_bankmachine6_wrport_we;
-wire   [24:0] litedramcore_bankmachine6_wrport_dat_w;
 wire          litedramcore_bankmachine6_do_read;
-wire    [3:0] litedramcore_bankmachine6_rdport_adr;
-wire   [24:0] litedramcore_bankmachine6_rdport_dat_r;
-wire          litedramcore_bankmachine6_fifo_in_payload_we;
-wire   [21:0] litedramcore_bankmachine6_fifo_in_payload_addr;
 wire          litedramcore_bankmachine6_fifo_in_first;
 wire          litedramcore_bankmachine6_fifo_in_last;
-wire          litedramcore_bankmachine6_fifo_out_payload_we;
-wire   [21:0] litedramcore_bankmachine6_fifo_out_payload_addr;
+wire   [21:0] litedramcore_bankmachine6_fifo_in_payload_addr;
+wire          litedramcore_bankmachine6_fifo_in_payload_we;
 wire          litedramcore_bankmachine6_fifo_out_first;
 wire          litedramcore_bankmachine6_fifo_out_last;
-wire          litedramcore_bankmachine6_sink_sink_valid;
-wire          litedramcore_bankmachine6_sink_sink_ready;
-wire          litedramcore_bankmachine6_sink_sink_first;
-wire          litedramcore_bankmachine6_sink_sink_last;
-wire          litedramcore_bankmachine6_sink_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine6_sink_sink_payload_addr;
-wire          litedramcore_bankmachine6_source_source_valid;
-wire          litedramcore_bankmachine6_source_source_ready;
-wire          litedramcore_bankmachine6_source_source_first;
-wire          litedramcore_bankmachine6_source_source_last;
-wire          litedramcore_bankmachine6_source_source_payload_we;
-wire   [21:0] litedramcore_bankmachine6_source_source_payload_addr;
-wire          litedramcore_bankmachine6_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine6_pipe_valid_sink_ready;
+wire   [21:0] litedramcore_bankmachine6_fifo_out_payload_addr;
+wire          litedramcore_bankmachine6_fifo_out_payload_we;
+reg     [4:0] litedramcore_bankmachine6_level = 5'd0;
+reg     [2:0] litedramcore_bankmachine6_next_state = 3'd0;
 wire          litedramcore_bankmachine6_pipe_valid_sink_first;
 wire          litedramcore_bankmachine6_pipe_valid_sink_last;
-wire          litedramcore_bankmachine6_pipe_valid_sink_payload_we;
 wire   [21:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine6_pipe_valid_source_ready;
+wire          litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+wire          litedramcore_bankmachine6_pipe_valid_sink_ready;
+wire          litedramcore_bankmachine6_pipe_valid_sink_valid;
 reg           litedramcore_bankmachine6_pipe_valid_source_first = 1'd0;
 reg           litedramcore_bankmachine6_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0;
 reg    [21:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 22'd0;
+reg           litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0;
+wire          litedramcore_bankmachine6_pipe_valid_source_ready;
+reg           litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0;
+reg     [3:0] litedramcore_bankmachine6_produce = 4'd0;
+wire    [3:0] litedramcore_bankmachine6_rdport_adr;
+wire   [24:0] litedramcore_bankmachine6_rdport_dat_r;
+reg           litedramcore_bankmachine6_refresh_gnt = 1'd0;
+wire          litedramcore_bankmachine6_refresh_req;
+reg           litedramcore_bankmachine6_replace = 1'd0;
+wire   [21:0] litedramcore_bankmachine6_req_addr;
+wire          litedramcore_bankmachine6_req_lock;
+reg           litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire          litedramcore_bankmachine6_req_ready;
+wire          litedramcore_bankmachine6_req_valid;
+reg           litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+wire          litedramcore_bankmachine6_req_we;
 reg    [14:0] litedramcore_bankmachine6_row = 15'd0;
-reg           litedramcore_bankmachine6_row_opened = 1'd0;
-wire          litedramcore_bankmachine6_row_hit;
-reg           litedramcore_bankmachine6_row_open = 1'd0;
 reg           litedramcore_bankmachine6_row_close = 1'd0;
 reg           litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine6_twtpcon_valid;
-reg           litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine6_trccon_valid;
-reg           litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg     [1:0] litedramcore_bankmachine6_trccon_count = 2'd0;
-wire          litedramcore_bankmachine6_trascon_valid;
-reg           litedramcore_bankmachine6_trascon_ready = 1'd0;
+wire          litedramcore_bankmachine6_row_hit;
+reg           litedramcore_bankmachine6_row_open = 1'd0;
+reg           litedramcore_bankmachine6_row_opened = 1'd0;
+reg           litedramcore_bankmachine6_sink_first = 1'd0;
+reg           litedramcore_bankmachine6_sink_last = 1'd0;
+wire   [21:0] litedramcore_bankmachine6_sink_payload_addr;
+wire          litedramcore_bankmachine6_sink_payload_we;
+wire          litedramcore_bankmachine6_sink_ready;
+wire          litedramcore_bankmachine6_sink_sink_first;
+wire          litedramcore_bankmachine6_sink_sink_last;
+wire   [21:0] litedramcore_bankmachine6_sink_sink_payload_addr;
+wire          litedramcore_bankmachine6_sink_sink_payload_we;
+wire          litedramcore_bankmachine6_sink_sink_ready;
+wire          litedramcore_bankmachine6_sink_sink_valid;
+wire          litedramcore_bankmachine6_sink_valid;
+wire          litedramcore_bankmachine6_source_first;
+wire          litedramcore_bankmachine6_source_last;
+wire   [21:0] litedramcore_bankmachine6_source_payload_addr;
+wire          litedramcore_bankmachine6_source_payload_we;
+wire          litedramcore_bankmachine6_source_ready;
+wire          litedramcore_bankmachine6_source_source_first;
+wire          litedramcore_bankmachine6_source_source_last;
+wire   [21:0] litedramcore_bankmachine6_source_source_payload_addr;
+wire          litedramcore_bankmachine6_source_source_payload_we;
+wire          litedramcore_bankmachine6_source_source_ready;
+wire          litedramcore_bankmachine6_source_source_valid;
+wire          litedramcore_bankmachine6_source_valid;
+reg     [2:0] litedramcore_bankmachine6_state = 3'd0;
+wire   [24:0] litedramcore_bankmachine6_syncfifo6_din;
+wire   [24:0] litedramcore_bankmachine6_syncfifo6_dout;
+wire          litedramcore_bankmachine6_syncfifo6_re;
+wire          litedramcore_bankmachine6_syncfifo6_readable;
+wire          litedramcore_bankmachine6_syncfifo6_we;
+wire          litedramcore_bankmachine6_syncfifo6_writable;
 reg     [1:0] litedramcore_bankmachine6_trascon_count = 2'd0;
-wire          litedramcore_bankmachine7_req_valid;
-wire          litedramcore_bankmachine7_req_ready;
-wire          litedramcore_bankmachine7_req_we;
-wire   [21:0] litedramcore_bankmachine7_req_addr;
-wire          litedramcore_bankmachine7_req_lock;
-reg           litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine7_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine7_refresh_req;
-reg           litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg           litedramcore_bankmachine6_trascon_ready = 1'd0;
+wire          litedramcore_bankmachine6_trascon_valid;
+reg     [1:0] litedramcore_bankmachine6_trccon_count = 2'd0;
+reg           litedramcore_bankmachine6_trccon_ready = 1'd0;
+wire          litedramcore_bankmachine6_trccon_valid;
+reg     [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
+reg           litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+wire          litedramcore_bankmachine6_twtpcon_valid;
+reg     [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0;
+wire   [24:0] litedramcore_bankmachine6_wrport_dat_r;
+wire   [24:0] litedramcore_bankmachine6_wrport_dat_w;
+wire          litedramcore_bankmachine6_wrport_we;
+reg           litedramcore_bankmachine7_auto_precharge = 1'd0;
 reg    [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0;
 wire    [2:0] litedramcore_bankmachine7_cmd_payload_ba;
 reg           litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_we = 1'd0;
 reg           litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
 reg           litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
 reg           litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine7_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine7_sink_valid;
-wire          litedramcore_bankmachine7_sink_ready;
-reg           litedramcore_bankmachine7_sink_first = 1'd0;
-reg           litedramcore_bankmachine7_sink_last = 1'd0;
-wire          litedramcore_bankmachine7_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine7_sink_payload_addr;
-wire          litedramcore_bankmachine7_source_valid;
-wire          litedramcore_bankmachine7_source_ready;
-wire          litedramcore_bankmachine7_source_first;
-wire          litedramcore_bankmachine7_source_last;
-wire          litedramcore_bankmachine7_source_payload_we;
-wire   [21:0] litedramcore_bankmachine7_source_payload_addr;
-wire          litedramcore_bankmachine7_syncfifo7_we;
-wire          litedramcore_bankmachine7_syncfifo7_writable;
-wire          litedramcore_bankmachine7_syncfifo7_re;
-wire          litedramcore_bankmachine7_syncfifo7_readable;
-wire   [24:0] litedramcore_bankmachine7_syncfifo7_din;
-wire   [24:0] litedramcore_bankmachine7_syncfifo7_dout;
-reg     [4:0] litedramcore_bankmachine7_level = 5'd0;
-reg           litedramcore_bankmachine7_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine7_produce = 4'd0;
+reg           litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg           litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg           litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg           litedramcore_bankmachine7_cmd_valid = 1'd0;
 reg     [3:0] litedramcore_bankmachine7_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0;
-wire   [24:0] litedramcore_bankmachine7_wrport_dat_r;
-wire          litedramcore_bankmachine7_wrport_we;
-wire   [24:0] litedramcore_bankmachine7_wrport_dat_w;
 wire          litedramcore_bankmachine7_do_read;
-wire    [3:0] litedramcore_bankmachine7_rdport_adr;
-wire   [24:0] litedramcore_bankmachine7_rdport_dat_r;
-wire          litedramcore_bankmachine7_fifo_in_payload_we;
-wire   [21:0] litedramcore_bankmachine7_fifo_in_payload_addr;
 wire          litedramcore_bankmachine7_fifo_in_first;
 wire          litedramcore_bankmachine7_fifo_in_last;
-wire          litedramcore_bankmachine7_fifo_out_payload_we;
-wire   [21:0] litedramcore_bankmachine7_fifo_out_payload_addr;
+wire   [21:0] litedramcore_bankmachine7_fifo_in_payload_addr;
+wire          litedramcore_bankmachine7_fifo_in_payload_we;
 wire          litedramcore_bankmachine7_fifo_out_first;
 wire          litedramcore_bankmachine7_fifo_out_last;
-wire          litedramcore_bankmachine7_sink_sink_valid;
-wire          litedramcore_bankmachine7_sink_sink_ready;
-wire          litedramcore_bankmachine7_sink_sink_first;
-wire          litedramcore_bankmachine7_sink_sink_last;
-wire          litedramcore_bankmachine7_sink_sink_payload_we;
-wire   [21:0] litedramcore_bankmachine7_sink_sink_payload_addr;
-wire          litedramcore_bankmachine7_source_source_valid;
-wire          litedramcore_bankmachine7_source_source_ready;
-wire          litedramcore_bankmachine7_source_source_first;
-wire          litedramcore_bankmachine7_source_source_last;
-wire          litedramcore_bankmachine7_source_source_payload_we;
-wire   [21:0] litedramcore_bankmachine7_source_source_payload_addr;
-wire          litedramcore_bankmachine7_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine7_pipe_valid_sink_ready;
+wire   [21:0] litedramcore_bankmachine7_fifo_out_payload_addr;
+wire          litedramcore_bankmachine7_fifo_out_payload_we;
+reg     [4:0] litedramcore_bankmachine7_level = 5'd0;
+reg     [2:0] litedramcore_bankmachine7_next_state = 3'd0;
 wire          litedramcore_bankmachine7_pipe_valid_sink_first;
 wire          litedramcore_bankmachine7_pipe_valid_sink_last;
-wire          litedramcore_bankmachine7_pipe_valid_sink_payload_we;
 wire   [21:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine7_pipe_valid_source_ready;
+wire          litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+wire          litedramcore_bankmachine7_pipe_valid_sink_ready;
+wire          litedramcore_bankmachine7_pipe_valid_sink_valid;
 reg           litedramcore_bankmachine7_pipe_valid_source_first = 1'd0;
 reg           litedramcore_bankmachine7_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0;
 reg    [21:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 22'd0;
+reg           litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0;
+wire          litedramcore_bankmachine7_pipe_valid_source_ready;
+reg           litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0;
+reg     [3:0] litedramcore_bankmachine7_produce = 4'd0;
+wire    [3:0] litedramcore_bankmachine7_rdport_adr;
+wire   [24:0] litedramcore_bankmachine7_rdport_dat_r;
+reg           litedramcore_bankmachine7_refresh_gnt = 1'd0;
+wire          litedramcore_bankmachine7_refresh_req;
+reg           litedramcore_bankmachine7_replace = 1'd0;
+wire   [21:0] litedramcore_bankmachine7_req_addr;
+wire          litedramcore_bankmachine7_req_lock;
+reg           litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire          litedramcore_bankmachine7_req_ready;
+wire          litedramcore_bankmachine7_req_valid;
+reg           litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+wire          litedramcore_bankmachine7_req_we;
 reg    [14:0] litedramcore_bankmachine7_row = 15'd0;
-reg           litedramcore_bankmachine7_row_opened = 1'd0;
-wire          litedramcore_bankmachine7_row_hit;
-reg           litedramcore_bankmachine7_row_open = 1'd0;
 reg           litedramcore_bankmachine7_row_close = 1'd0;
 reg           litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine7_twtpcon_valid;
-reg           litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine7_trccon_valid;
-reg           litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg     [1:0] litedramcore_bankmachine7_trccon_count = 2'd0;
-wire          litedramcore_bankmachine7_trascon_valid;
-reg           litedramcore_bankmachine7_trascon_ready = 1'd0;
+wire          litedramcore_bankmachine7_row_hit;
+reg           litedramcore_bankmachine7_row_open = 1'd0;
+reg           litedramcore_bankmachine7_row_opened = 1'd0;
+reg           litedramcore_bankmachine7_sink_first = 1'd0;
+reg           litedramcore_bankmachine7_sink_last = 1'd0;
+wire   [21:0] litedramcore_bankmachine7_sink_payload_addr;
+wire          litedramcore_bankmachine7_sink_payload_we;
+wire          litedramcore_bankmachine7_sink_ready;
+wire          litedramcore_bankmachine7_sink_sink_first;
+wire          litedramcore_bankmachine7_sink_sink_last;
+wire   [21:0] litedramcore_bankmachine7_sink_sink_payload_addr;
+wire          litedramcore_bankmachine7_sink_sink_payload_we;
+wire          litedramcore_bankmachine7_sink_sink_ready;
+wire          litedramcore_bankmachine7_sink_sink_valid;
+wire          litedramcore_bankmachine7_sink_valid;
+wire          litedramcore_bankmachine7_source_first;
+wire          litedramcore_bankmachine7_source_last;
+wire   [21:0] litedramcore_bankmachine7_source_payload_addr;
+wire          litedramcore_bankmachine7_source_payload_we;
+wire          litedramcore_bankmachine7_source_ready;
+wire          litedramcore_bankmachine7_source_source_first;
+wire          litedramcore_bankmachine7_source_source_last;
+wire   [21:0] litedramcore_bankmachine7_source_source_payload_addr;
+wire          litedramcore_bankmachine7_source_source_payload_we;
+wire          litedramcore_bankmachine7_source_source_ready;
+wire          litedramcore_bankmachine7_source_source_valid;
+wire          litedramcore_bankmachine7_source_valid;
+reg     [2:0] litedramcore_bankmachine7_state = 3'd0;
+wire   [24:0] litedramcore_bankmachine7_syncfifo7_din;
+wire   [24:0] litedramcore_bankmachine7_syncfifo7_dout;
+wire          litedramcore_bankmachine7_syncfifo7_re;
+wire          litedramcore_bankmachine7_syncfifo7_readable;
+wire          litedramcore_bankmachine7_syncfifo7_we;
+wire          litedramcore_bankmachine7_syncfifo7_writable;
 reg     [1:0] litedramcore_bankmachine7_trascon_count = 2'd0;
-wire          litedramcore_ras_allowed;
+reg           litedramcore_bankmachine7_trascon_ready = 1'd0;
+wire          litedramcore_bankmachine7_trascon_valid;
+reg     [1:0] litedramcore_bankmachine7_trccon_count = 2'd0;
+reg           litedramcore_bankmachine7_trccon_ready = 1'd0;
+wire          litedramcore_bankmachine7_trccon_valid;
+reg     [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
+reg           litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+wire          litedramcore_bankmachine7_twtpcon_valid;
+reg     [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0;
+wire   [24:0] litedramcore_bankmachine7_wrport_dat_r;
+wire   [24:0] litedramcore_bankmachine7_wrport_dat_w;
+wire          litedramcore_bankmachine7_wrport_we;
 wire          litedramcore_cas_allowed;
-reg           litedramcore_choose_cmd_want_reads = 1'd0;
-reg           litedramcore_choose_cmd_want_writes = 1'd0;
-reg           litedramcore_choose_cmd_want_cmds = 1'd0;
-reg           litedramcore_choose_cmd_want_activates = 1'd0;
-wire          litedramcore_choose_cmd_cmd_valid;
-reg           litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire          litedramcore_choose_cmd_ce;
 wire   [14:0] litedramcore_choose_cmd_cmd_payload_a;
 wire    [2:0] litedramcore_choose_cmd_cmd_payload_ba;
 reg           litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg           litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg           litedramcore_choose_cmd_cmd_payload_we = 1'd0;
 wire          litedramcore_choose_cmd_cmd_payload_is_cmd;
 wire          litedramcore_choose_cmd_cmd_payload_is_read;
 wire          litedramcore_choose_cmd_cmd_payload_is_write;
-reg     [7:0] litedramcore_choose_cmd_valids = 8'd0;
-wire    [7:0] litedramcore_choose_cmd_request;
+reg           litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg           litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+reg           litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire          litedramcore_choose_cmd_cmd_valid;
 reg     [2:0] litedramcore_choose_cmd_grant = 3'd0;
-wire          litedramcore_choose_cmd_ce;
-reg           litedramcore_choose_req_want_reads = 1'd0;
-reg           litedramcore_choose_req_want_writes = 1'd0;
-reg           litedramcore_choose_req_want_cmds = 1'd0;
-reg           litedramcore_choose_req_want_activates = 1'd0;
-wire          litedramcore_choose_req_cmd_valid;
-reg           litedramcore_choose_req_cmd_ready = 1'd0;
+wire    [7:0] litedramcore_choose_cmd_request;
+reg     [7:0] litedramcore_choose_cmd_valids = 8'd0;
+reg           litedramcore_choose_cmd_want_activates = 1'd0;
+reg           litedramcore_choose_cmd_want_cmds = 1'd0;
+reg           litedramcore_choose_cmd_want_reads = 1'd0;
+reg           litedramcore_choose_cmd_want_writes = 1'd0;
+wire          litedramcore_choose_req_ce;
 wire   [14:0] litedramcore_choose_req_cmd_payload_a;
 wire    [2:0] litedramcore_choose_req_cmd_payload_ba;
 reg           litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg           litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg           litedramcore_choose_req_cmd_payload_we = 1'd0;
 wire          litedramcore_choose_req_cmd_payload_is_cmd;
 wire          litedramcore_choose_req_cmd_payload_is_read;
 wire          litedramcore_choose_req_cmd_payload_is_write;
-reg     [7:0] litedramcore_choose_req_valids = 8'd0;
-wire    [7:0] litedramcore_choose_req_request;
+reg           litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg           litedramcore_choose_req_cmd_payload_we = 1'd0;
+reg           litedramcore_choose_req_cmd_ready = 1'd0;
+wire          litedramcore_choose_req_cmd_valid;
 reg     [2:0] litedramcore_choose_req_grant = 3'd0;
-wire          litedramcore_choose_req_ce;
+wire    [7:0] litedramcore_choose_req_request;
+reg     [7:0] litedramcore_choose_req_valids = 8'd0;
+reg           litedramcore_choose_req_want_activates = 1'd0;
+reg           litedramcore_choose_req_want_cmds = 1'd0;
+reg           litedramcore_choose_req_want_reads = 1'd0;
+reg           litedramcore_choose_req_want_writes = 1'd0;
+wire          litedramcore_cke;
+reg           litedramcore_cmd_last = 1'd0;
+reg    [14:0] litedramcore_cmd_payload_a = 15'd0;
+reg     [2:0] litedramcore_cmd_payload_ba = 3'd0;
+reg           litedramcore_cmd_payload_cas = 1'd0;
+reg           litedramcore_cmd_payload_is_read = 1'd0;
+reg           litedramcore_cmd_payload_is_write = 1'd0;
+reg           litedramcore_cmd_payload_ras = 1'd0;
+reg           litedramcore_cmd_payload_we = 1'd0;
+reg           litedramcore_cmd_ready = 1'd0;
+reg           litedramcore_cmd_valid = 1'd0;
+reg           litedramcore_csr_dfi_p0_act_n = 1'd1;
+wire   [14:0] litedramcore_csr_dfi_p0_address;
+wire    [2:0] litedramcore_csr_dfi_p0_bank;
+reg           litedramcore_csr_dfi_p0_cas_n = 1'd1;
+reg           litedramcore_csr_dfi_p0_cke = 1'd0;
+reg           litedramcore_csr_dfi_p0_cs_n = 1'd1;
+reg           litedramcore_csr_dfi_p0_odt = 1'd0;
+reg           litedramcore_csr_dfi_p0_ras_n = 1'd1;
+reg    [63:0] litedramcore_csr_dfi_p0_rddata = 64'd0;
+wire          litedramcore_csr_dfi_p0_rddata_en;
+reg           litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
+wire          litedramcore_csr_dfi_p0_reset_n;
+reg           litedramcore_csr_dfi_p0_we_n = 1'd1;
+wire   [63:0] litedramcore_csr_dfi_p0_wrdata;
+wire          litedramcore_csr_dfi_p0_wrdata_en;
+wire    [7:0] litedramcore_csr_dfi_p0_wrdata_mask;
+reg           litedramcore_csr_dfi_p1_act_n = 1'd1;
+wire   [14:0] litedramcore_csr_dfi_p1_address;
+wire    [2:0] litedramcore_csr_dfi_p1_bank;
+reg           litedramcore_csr_dfi_p1_cas_n = 1'd1;
+reg           litedramcore_csr_dfi_p1_cke = 1'd0;
+reg           litedramcore_csr_dfi_p1_cs_n = 1'd1;
+reg           litedramcore_csr_dfi_p1_odt = 1'd0;
+reg           litedramcore_csr_dfi_p1_ras_n = 1'd1;
+reg    [63:0] litedramcore_csr_dfi_p1_rddata = 64'd0;
+wire          litedramcore_csr_dfi_p1_rddata_en;
+reg           litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
+wire          litedramcore_csr_dfi_p1_reset_n;
+reg           litedramcore_csr_dfi_p1_we_n = 1'd1;
+wire   [63:0] litedramcore_csr_dfi_p1_wrdata;
+wire          litedramcore_csr_dfi_p1_wrdata_en;
+wire    [7:0] litedramcore_csr_dfi_p1_wrdata_mask;
+reg           litedramcore_dfi_p0_act_n = 1'd1;
+reg    [14:0] litedramcore_dfi_p0_address = 15'd0;
+reg     [2:0] litedramcore_dfi_p0_bank = 3'd0;
+reg           litedramcore_dfi_p0_cas_n = 1'd1;
+wire          litedramcore_dfi_p0_cke;
+reg           litedramcore_dfi_p0_cs_n = 1'd1;
+wire          litedramcore_dfi_p0_odt;
+reg           litedramcore_dfi_p0_ras_n = 1'd1;
+wire   [63:0] litedramcore_dfi_p0_rddata;
+reg           litedramcore_dfi_p0_rddata_en = 1'd0;
+wire          litedramcore_dfi_p0_rddata_valid;
+wire          litedramcore_dfi_p0_reset_n;
+reg           litedramcore_dfi_p0_we_n = 1'd1;
+wire   [63:0] litedramcore_dfi_p0_wrdata;
+reg           litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire    [7:0] litedramcore_dfi_p0_wrdata_mask;
+reg           litedramcore_dfi_p1_act_n = 1'd1;
+reg    [14:0] litedramcore_dfi_p1_address = 15'd0;
+reg     [2:0] litedramcore_dfi_p1_bank = 3'd0;
+reg           litedramcore_dfi_p1_cas_n = 1'd1;
+wire          litedramcore_dfi_p1_cke;
+reg           litedramcore_dfi_p1_cs_n = 1'd1;
+wire          litedramcore_dfi_p1_odt;
+reg           litedramcore_dfi_p1_ras_n = 1'd1;
+wire   [63:0] litedramcore_dfi_p1_rddata;
+reg           litedramcore_dfi_p1_rddata_en = 1'd0;
+wire          litedramcore_dfi_p1_rddata_valid;
+wire          litedramcore_dfi_p1_reset_n;
+reg           litedramcore_dfi_p1_we_n = 1'd1;
+wire   [63:0] litedramcore_dfi_p1_wrdata;
+reg           litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire    [7:0] litedramcore_dfi_p1_wrdata_mask;
+reg           litedramcore_en0 = 1'd0;
+reg           litedramcore_en1 = 1'd0;
+reg           litedramcore_ext_dfi_p0_act_n = 1'd1;
+reg    [14:0] litedramcore_ext_dfi_p0_address = 15'd0;
+reg     [2:0] litedramcore_ext_dfi_p0_bank = 3'd0;
+reg           litedramcore_ext_dfi_p0_cas_n = 1'd1;
+reg           litedramcore_ext_dfi_p0_cke = 1'd0;
+reg           litedramcore_ext_dfi_p0_cs_n = 1'd1;
+reg           litedramcore_ext_dfi_p0_odt = 1'd0;
+reg           litedramcore_ext_dfi_p0_ras_n = 1'd1;
+reg    [63:0] litedramcore_ext_dfi_p0_rddata = 64'd0;
+reg           litedramcore_ext_dfi_p0_rddata_en = 1'd0;
+reg           litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
+reg           litedramcore_ext_dfi_p0_reset_n = 1'd0;
+reg           litedramcore_ext_dfi_p0_we_n = 1'd1;
+reg    [63:0] litedramcore_ext_dfi_p0_wrdata = 64'd0;
+reg           litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
+reg     [7:0] litedramcore_ext_dfi_p0_wrdata_mask = 8'd0;
+reg           litedramcore_ext_dfi_p1_act_n = 1'd1;
+reg    [14:0] litedramcore_ext_dfi_p1_address = 15'd0;
+reg     [2:0] litedramcore_ext_dfi_p1_bank = 3'd0;
+reg           litedramcore_ext_dfi_p1_cas_n = 1'd1;
+reg           litedramcore_ext_dfi_p1_cke = 1'd0;
+reg           litedramcore_ext_dfi_p1_cs_n = 1'd1;
+reg           litedramcore_ext_dfi_p1_odt = 1'd0;
+reg           litedramcore_ext_dfi_p1_ras_n = 1'd1;
+reg    [63:0] litedramcore_ext_dfi_p1_rddata = 64'd0;
+reg           litedramcore_ext_dfi_p1_rddata_en = 1'd0;
+reg           litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
+reg           litedramcore_ext_dfi_p1_reset_n = 1'd0;
+reg           litedramcore_ext_dfi_p1_we_n = 1'd1;
+reg    [63:0] litedramcore_ext_dfi_p1_wrdata = 64'd0;
+reg           litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
+reg     [7:0] litedramcore_ext_dfi_p1_wrdata_mask = 8'd0;
+reg           litedramcore_ext_dfi_sel = 1'd0;
+wire          litedramcore_go_to_refresh;
+wire   [21:0] litedramcore_interface_bank0_addr;
+wire          litedramcore_interface_bank0_lock;
+wire          litedramcore_interface_bank0_rdata_valid;
+wire          litedramcore_interface_bank0_ready;
+wire          litedramcore_interface_bank0_valid;
+wire          litedramcore_interface_bank0_wdata_ready;
+wire          litedramcore_interface_bank0_we;
+wire   [21:0] litedramcore_interface_bank1_addr;
+wire          litedramcore_interface_bank1_lock;
+wire          litedramcore_interface_bank1_rdata_valid;
+wire          litedramcore_interface_bank1_ready;
+wire          litedramcore_interface_bank1_valid;
+wire          litedramcore_interface_bank1_wdata_ready;
+wire          litedramcore_interface_bank1_we;
+wire   [21:0] litedramcore_interface_bank2_addr;
+wire          litedramcore_interface_bank2_lock;
+wire          litedramcore_interface_bank2_rdata_valid;
+wire          litedramcore_interface_bank2_ready;
+wire          litedramcore_interface_bank2_valid;
+wire          litedramcore_interface_bank2_wdata_ready;
+wire          litedramcore_interface_bank2_we;
+wire   [21:0] litedramcore_interface_bank3_addr;
+wire          litedramcore_interface_bank3_lock;
+wire          litedramcore_interface_bank3_rdata_valid;
+wire          litedramcore_interface_bank3_ready;
+wire          litedramcore_interface_bank3_valid;
+wire          litedramcore_interface_bank3_wdata_ready;
+wire          litedramcore_interface_bank3_we;
+wire   [21:0] litedramcore_interface_bank4_addr;
+wire          litedramcore_interface_bank4_lock;
+wire          litedramcore_interface_bank4_rdata_valid;
+wire          litedramcore_interface_bank4_ready;
+wire          litedramcore_interface_bank4_valid;
+wire          litedramcore_interface_bank4_wdata_ready;
+wire          litedramcore_interface_bank4_we;
+wire   [21:0] litedramcore_interface_bank5_addr;
+wire          litedramcore_interface_bank5_lock;
+wire          litedramcore_interface_bank5_rdata_valid;
+wire          litedramcore_interface_bank5_ready;
+wire          litedramcore_interface_bank5_valid;
+wire          litedramcore_interface_bank5_wdata_ready;
+wire          litedramcore_interface_bank5_we;
+wire   [21:0] litedramcore_interface_bank6_addr;
+wire          litedramcore_interface_bank6_lock;
+wire          litedramcore_interface_bank6_rdata_valid;
+wire          litedramcore_interface_bank6_ready;
+wire          litedramcore_interface_bank6_valid;
+wire          litedramcore_interface_bank6_wdata_ready;
+wire          litedramcore_interface_bank6_we;
+wire   [21:0] litedramcore_interface_bank7_addr;
+wire          litedramcore_interface_bank7_lock;
+wire          litedramcore_interface_bank7_rdata_valid;
+wire          litedramcore_interface_bank7_ready;
+wire          litedramcore_interface_bank7_valid;
+wire          litedramcore_interface_bank7_wdata_ready;
+wire          litedramcore_interface_bank7_we;
+wire  [127:0] litedramcore_interface_rdata;
+reg   [127:0] litedramcore_interface_wdata = 128'd0;
+reg    [15:0] litedramcore_interface_wdata_we = 16'd0;
+reg           litedramcore_locked0 = 1'd0;
+reg           litedramcore_locked1 = 1'd0;
+reg           litedramcore_locked2 = 1'd0;
+reg           litedramcore_locked3 = 1'd0;
+reg           litedramcore_locked4 = 1'd0;
+reg           litedramcore_locked5 = 1'd0;
+reg           litedramcore_locked6 = 1'd0;
+reg           litedramcore_locked7 = 1'd0;
+reg           litedramcore_master_p0_act_n = 1'd1;
+reg    [14:0] litedramcore_master_p0_address = 15'd0;
+reg     [2:0] litedramcore_master_p0_bank = 3'd0;
+reg           litedramcore_master_p0_cas_n = 1'd1;
+reg           litedramcore_master_p0_cke = 1'd0;
+reg           litedramcore_master_p0_cs_n = 1'd1;
+reg           litedramcore_master_p0_odt = 1'd0;
+reg           litedramcore_master_p0_ras_n = 1'd1;
+wire   [63:0] litedramcore_master_p0_rddata;
+reg           litedramcore_master_p0_rddata_en = 1'd0;
+wire          litedramcore_master_p0_rddata_valid;
+reg           litedramcore_master_p0_reset_n = 1'd0;
+reg           litedramcore_master_p0_we_n = 1'd1;
+reg    [63:0] litedramcore_master_p0_wrdata = 64'd0;
+reg           litedramcore_master_p0_wrdata_en = 1'd0;
+reg     [7:0] litedramcore_master_p0_wrdata_mask = 8'd0;
+reg           litedramcore_master_p1_act_n = 1'd1;
+reg    [14:0] litedramcore_master_p1_address = 15'd0;
+reg     [2:0] litedramcore_master_p1_bank = 3'd0;
+reg           litedramcore_master_p1_cas_n = 1'd1;
+reg           litedramcore_master_p1_cke = 1'd0;
+reg           litedramcore_master_p1_cs_n = 1'd1;
+reg           litedramcore_master_p1_odt = 1'd0;
+reg           litedramcore_master_p1_ras_n = 1'd1;
+wire   [63:0] litedramcore_master_p1_rddata;
+reg           litedramcore_master_p1_rddata_en = 1'd0;
+wire          litedramcore_master_p1_rddata_valid;
+reg           litedramcore_master_p1_reset_n = 1'd0;
+reg           litedramcore_master_p1_we_n = 1'd1;
+reg    [63:0] litedramcore_master_p1_wrdata = 64'd0;
+reg           litedramcore_master_p1_wrdata_en = 1'd0;
+reg     [7:0] litedramcore_master_p1_wrdata_mask = 8'd0;
+wire          litedramcore_max_time0;
+wire          litedramcore_max_time1;
+reg     [3:0] litedramcore_multiplexer_next_state = 4'd0;
+reg     [3:0] litedramcore_multiplexer_state = 4'd0;
+reg           litedramcore_new_master_rdata_valid0 = 1'd0;
+reg           litedramcore_new_master_rdata_valid1 = 1'd0;
+reg           litedramcore_new_master_rdata_valid10 = 1'd0;
+reg           litedramcore_new_master_rdata_valid11 = 1'd0;
+reg           litedramcore_new_master_rdata_valid12 = 1'd0;
+reg           litedramcore_new_master_rdata_valid13 = 1'd0;
+reg           litedramcore_new_master_rdata_valid2 = 1'd0;
+reg           litedramcore_new_master_rdata_valid3 = 1'd0;
+reg           litedramcore_new_master_rdata_valid4 = 1'd0;
+reg           litedramcore_new_master_rdata_valid5 = 1'd0;
+reg           litedramcore_new_master_rdata_valid6 = 1'd0;
+reg           litedramcore_new_master_rdata_valid7 = 1'd0;
+reg           litedramcore_new_master_rdata_valid8 = 1'd0;
+reg           litedramcore_new_master_rdata_valid9 = 1'd0;
+reg           litedramcore_new_master_wdata_ready0 = 1'd0;
+reg           litedramcore_new_master_wdata_ready1 = 1'd0;
+reg           litedramcore_new_master_wdata_ready2 = 1'd0;
+reg           litedramcore_new_master_wdata_ready3 = 1'd0;
 reg    [14:0] litedramcore_nop_a = 15'd0;
 reg     [2:0] litedramcore_nop_ba = 3'd0;
-reg     [1:0] litedramcore_steerer_sel0 = 2'd0;
-reg     [1:0] litedramcore_steerer_sel1 = 2'd0;
-reg           litedramcore_steerer0 = 1'd1;
-reg           litedramcore_steerer1 = 1'd1;
+wire          litedramcore_odt;
+reg           litedramcore_phaseinjector0_address_re = 1'd0;
+reg    [14:0] litedramcore_phaseinjector0_address_storage = 15'd0;
+reg           litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg     [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
+wire          litedramcore_phaseinjector0_command_issue_r;
+reg           litedramcore_phaseinjector0_command_issue_re = 1'd0;
+reg           litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg           litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg           litedramcore_phaseinjector0_command_re = 1'd0;
+reg     [7:0] litedramcore_phaseinjector0_command_storage = 8'd0;
+wire          litedramcore_phaseinjector0_csrfield_cas;
+wire          litedramcore_phaseinjector0_csrfield_cs;
+wire          litedramcore_phaseinjector0_csrfield_cs_bottom;
+wire          litedramcore_phaseinjector0_csrfield_cs_top;
+wire          litedramcore_phaseinjector0_csrfield_ras;
+wire          litedramcore_phaseinjector0_csrfield_rden;
+wire          litedramcore_phaseinjector0_csrfield_we;
+wire          litedramcore_phaseinjector0_csrfield_wren;
+reg           litedramcore_phaseinjector0_rddata_re = 1'd0;
+reg    [63:0] litedramcore_phaseinjector0_rddata_status = 64'd0;
+wire          litedramcore_phaseinjector0_rddata_we;
+reg           litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg    [63:0] litedramcore_phaseinjector0_wrdata_storage = 64'd0;
+reg           litedramcore_phaseinjector1_address_re = 1'd0;
+reg    [14:0] litedramcore_phaseinjector1_address_storage = 15'd0;
+reg           litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg     [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
+wire          litedramcore_phaseinjector1_command_issue_r;
+reg           litedramcore_phaseinjector1_command_issue_re = 1'd0;
+reg           litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg           litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg           litedramcore_phaseinjector1_command_re = 1'd0;
+reg     [7:0] litedramcore_phaseinjector1_command_storage = 8'd0;
+wire          litedramcore_phaseinjector1_csrfield_cas;
+wire          litedramcore_phaseinjector1_csrfield_cs;
+wire          litedramcore_phaseinjector1_csrfield_cs_bottom;
+wire          litedramcore_phaseinjector1_csrfield_cs_top;
+wire          litedramcore_phaseinjector1_csrfield_ras;
+wire          litedramcore_phaseinjector1_csrfield_rden;
+wire          litedramcore_phaseinjector1_csrfield_we;
+wire          litedramcore_phaseinjector1_csrfield_wren;
+reg           litedramcore_phaseinjector1_rddata_re = 1'd0;
+reg    [63:0] litedramcore_phaseinjector1_rddata_status = 64'd0;
+wire          litedramcore_phaseinjector1_rddata_we;
+reg           litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg    [63:0] litedramcore_phaseinjector1_wrdata_storage = 64'd0;
+reg           litedramcore_postponer_count = 1'd0;
+wire          litedramcore_postponer_req_i;
+reg           litedramcore_postponer_req_o = 1'd0;
+wire          litedramcore_ras_allowed;
+reg           litedramcore_re = 1'd0;
+wire          litedramcore_read_available;
+reg     [1:0] litedramcore_refresher_next_state = 2'd0;
+reg     [1:0] litedramcore_refresher_state = 2'd0;
+wire          litedramcore_reset_n;
+wire          litedramcore_roundrobin0_ce;
+wire          litedramcore_roundrobin0_grant;
+wire          litedramcore_roundrobin0_request;
+wire          litedramcore_roundrobin1_ce;
+wire          litedramcore_roundrobin1_grant;
+wire          litedramcore_roundrobin1_request;
+wire          litedramcore_roundrobin2_ce;
+wire          litedramcore_roundrobin2_grant;
+wire          litedramcore_roundrobin2_request;
+wire          litedramcore_roundrobin3_ce;
+wire          litedramcore_roundrobin3_grant;
+wire          litedramcore_roundrobin3_request;
+wire          litedramcore_roundrobin4_ce;
+wire          litedramcore_roundrobin4_grant;
+wire          litedramcore_roundrobin4_request;
+wire          litedramcore_roundrobin5_ce;
+wire          litedramcore_roundrobin5_grant;
+wire          litedramcore_roundrobin5_request;
+wire          litedramcore_roundrobin6_ce;
+wire          litedramcore_roundrobin6_grant;
+wire          litedramcore_roundrobin6_request;
+wire          litedramcore_roundrobin7_ce;
+wire          litedramcore_roundrobin7_grant;
+wire          litedramcore_roundrobin7_request;
+wire          litedramcore_sel;
+reg           litedramcore_sequencer_count = 1'd0;
+wire          litedramcore_sequencer_done0;
+reg           litedramcore_sequencer_done1 = 1'd0;
+reg           litedramcore_sequencer_start0 = 1'd0;
+wire          litedramcore_sequencer_start1;
+reg     [6:0] litedramcore_sequencer_trigger = 7'd0;
+wire          litedramcore_slave_p0_act_n;
+wire   [14:0] litedramcore_slave_p0_address;
+wire    [2:0] litedramcore_slave_p0_bank;
+wire          litedramcore_slave_p0_cas_n;
+wire          litedramcore_slave_p0_cke;
+wire          litedramcore_slave_p0_cs_n;
+wire          litedramcore_slave_p0_odt;
+wire          litedramcore_slave_p0_ras_n;
+reg    [63:0] litedramcore_slave_p0_rddata = 64'd0;
+wire          litedramcore_slave_p0_rddata_en;
+reg           litedramcore_slave_p0_rddata_valid = 1'd0;
+wire          litedramcore_slave_p0_reset_n;
+wire          litedramcore_slave_p0_we_n;
+wire   [63:0] litedramcore_slave_p0_wrdata;
+wire          litedramcore_slave_p0_wrdata_en;
+wire    [7:0] litedramcore_slave_p0_wrdata_mask;
+wire          litedramcore_slave_p1_act_n;
+wire   [14:0] litedramcore_slave_p1_address;
+wire    [2:0] litedramcore_slave_p1_bank;
+wire          litedramcore_slave_p1_cas_n;
+wire          litedramcore_slave_p1_cke;
+wire          litedramcore_slave_p1_cs_n;
+wire          litedramcore_slave_p1_odt;
+wire          litedramcore_slave_p1_ras_n;
+reg    [63:0] litedramcore_slave_p1_rddata = 64'd0;
+wire          litedramcore_slave_p1_rddata_en;
+reg           litedramcore_slave_p1_rddata_valid = 1'd0;
+wire          litedramcore_slave_p1_reset_n;
+wire          litedramcore_slave_p1_we_n;
+wire   [63:0] litedramcore_slave_p1_wrdata;
+wire          litedramcore_slave_p1_wrdata_en;
+wire    [7:0] litedramcore_slave_p1_wrdata_mask;
+reg     [1:0] litedramcore_steerer0 = 2'd0;
+reg     [1:0] litedramcore_steerer1 = 2'd0;
 reg           litedramcore_steerer2 = 1'd1;
 reg           litedramcore_steerer3 = 1'd1;
-wire          litedramcore_trrdcon_valid;
-reg           litedramcore_trrdcon_ready = 1'd0;
-reg           litedramcore_trrdcon_count = 1'd0;
-wire          litedramcore_tfawcon_valid;
-reg           litedramcore_tfawcon_ready = 1'd1;
+reg           litedramcore_steerer4 = 1'd1;
+reg           litedramcore_steerer5 = 1'd1;
+reg     [3:0] litedramcore_storage = 4'd1;
+reg           litedramcore_tccdcon_count = 1'd0;
+reg           litedramcore_tccdcon_ready = 1'd0;
+wire          litedramcore_tccdcon_valid;
 wire    [1:0] litedramcore_tfawcon_count;
+reg           litedramcore_tfawcon_ready = 1'd1;
+wire          litedramcore_tfawcon_valid;
 reg     [2:0] litedramcore_tfawcon_window = 3'd0;
-wire          litedramcore_tccdcon_valid;
-reg           litedramcore_tccdcon_ready = 1'd0;
-reg           litedramcore_tccdcon_count = 1'd0;
-wire          litedramcore_twtrcon_valid;
-reg           litedramcore_twtrcon_ready = 1'd0;
-reg     [2:0] litedramcore_twtrcon_count = 3'd0;
-wire          litedramcore_read_available;
-wire          litedramcore_write_available;
-reg           litedramcore_en0 = 1'd0;
-wire          litedramcore_max_time0;
 reg     [4:0] litedramcore_time0 = 5'd0;
-reg           litedramcore_en1 = 1'd0;
-wire          litedramcore_max_time1;
 reg     [3:0] litedramcore_time1 = 4'd0;
-wire          litedramcore_go_to_refresh;
-reg           init_done_storage = 1'd0;
-reg           init_done_re = 1'd0;
-reg           init_error_storage = 1'd0;
-reg           init_error_re = 1'd0;
+wire    [8:0] litedramcore_timer_count0;
+reg     [8:0] litedramcore_timer_count1 = 9'd374;
+wire          litedramcore_timer_done0;
+wire          litedramcore_timer_done1;
+wire          litedramcore_timer_wait;
+reg           litedramcore_trrdcon_count = 1'd0;
+reg           litedramcore_trrdcon_ready = 1'd0;
+wire          litedramcore_trrdcon_valid;
+reg     [2:0] litedramcore_twtrcon_count = 3'd0;
+reg           litedramcore_twtrcon_ready = 1'd0;
+wire          litedramcore_twtrcon_valid;
+wire          litedramcore_wants_refresh;
+wire          litedramcore_wants_zqcs;
+wire          litedramcore_write_available;
+reg           litedramcore_zqcs_executer_done = 1'd0;
+reg           litedramcore_zqcs_executer_start = 1'd0;
+reg     [5:0] litedramcore_zqcs_executer_trigger = 6'd0;
+wire   [25:0] litedramcore_zqcs_timer_count0;
+reg    [25:0] litedramcore_zqcs_timer_count1 = 26'd47999999;
+wire          litedramcore_zqcs_timer_done0;
+wire          litedramcore_zqcs_timer_done1;
+wire          litedramcore_zqcs_timer_wait;
+wire          litedramecp5ddrphycrg_ecp5pll;
+wire          litedramecp5ddrphycrg_locked;
+reg           multiregimpl0 = 1'd0;
+reg           multiregimpl1 = 1'd0;
+reg     [1:0] next_state = 2'd0;
+wire          por_clk;
+reg           rhs_self0 = 1'd0;
+reg    [14:0] rhs_self1 = 15'd0;
+reg           rhs_self10 = 1'd0;
+reg           rhs_self11 = 1'd0;
+reg    [21:0] rhs_self12 = 22'd0;
+reg           rhs_self13 = 1'd0;
+reg           rhs_self14 = 1'd0;
+reg    [21:0] rhs_self15 = 22'd0;
+reg           rhs_self16 = 1'd0;
+reg           rhs_self17 = 1'd0;
+reg    [21:0] rhs_self18 = 22'd0;
+reg           rhs_self19 = 1'd0;
+reg     [2:0] rhs_self2 = 3'd0;
+reg           rhs_self20 = 1'd0;
+reg    [21:0] rhs_self21 = 22'd0;
+reg           rhs_self22 = 1'd0;
+reg           rhs_self23 = 1'd0;
+reg    [21:0] rhs_self24 = 22'd0;
+reg           rhs_self25 = 1'd0;
+reg           rhs_self26 = 1'd0;
+reg    [21:0] rhs_self27 = 22'd0;
+reg           rhs_self28 = 1'd0;
+reg           rhs_self29 = 1'd0;
+reg           rhs_self3 = 1'd0;
+reg    [21:0] rhs_self30 = 22'd0;
+reg           rhs_self31 = 1'd0;
+reg           rhs_self32 = 1'd0;
+reg    [21:0] rhs_self33 = 22'd0;
+reg           rhs_self34 = 1'd0;
+reg           rhs_self35 = 1'd0;
+reg           rhs_self4 = 1'd0;
+reg           rhs_self5 = 1'd0;
+reg           rhs_self6 = 1'd0;
+reg    [14:0] rhs_self7 = 15'd0;
+reg     [2:0] rhs_self8 = 3'd0;
+reg           rhs_self9 = 1'd0;
+reg     [2:0] self0 = 3'd0;
+reg    [14:0] self1 = 15'd0;
+reg           self10 = 1'd0;
+reg           self11 = 1'd0;
+reg           self12 = 1'd0;
+reg           self13 = 1'd0;
+reg           self2 = 1'd0;
+reg           self3 = 1'd0;
+reg           self4 = 1'd0;
+reg           self5 = 1'd0;
+reg           self6 = 1'd0;
+reg     [2:0] self7 = 3'd0;
+reg    [14:0] self8 = 15'd0;
+reg           self9 = 1'd0;
+reg     [1:0] state = 2'd0;
+wire          sys2x_clk;
+wire          sys2x_i_clk;
+wire          sys2x_rst;
+wire          sys_clk;
+wire          sys_rst;
+reg           t_self0 = 1'd0;
+reg           t_self1 = 1'd0;
+reg           t_self2 = 1'd0;
+reg           t_self3 = 1'd0;
+reg           t_self4 = 1'd0;
+reg           t_self5 = 1'd0;
+wire          user_enable;
+wire   [24:0] user_port_cmd_payload_addr;
+wire          user_port_cmd_payload_we;
+wire          user_port_cmd_ready;
+wire          user_port_cmd_valid;
+wire  [127:0] user_port_rdata_payload_data;
+wire          user_port_rdata_ready;
+wire          user_port_rdata_valid;
+wire  [127:0] user_port_wdata_payload_data;
+wire   [15:0] user_port_wdata_payload_we;
+wire          user_port_wdata_ready;
+wire          user_port_wdata_valid;
+wire          wb_bus_ack;
 wire   [29:0] wb_bus_adr;
-wire   [31:0] wb_bus_dat_w;
+wire    [1:0] wb_bus_bte;
+wire    [2:0] wb_bus_cti;
+wire          wb_bus_cyc;
 wire   [31:0] wb_bus_dat_r;
+wire   [31:0] wb_bus_dat_w;
+wire          wb_bus_err;
 wire    [3:0] wb_bus_sel;
-wire          wb_bus_cyc;
 wire          wb_bus_stb;
-wire          wb_bus_ack;
 wire          wb_bus_we;
-wire    [2:0] wb_bus_cti;
-wire    [1:0] wb_bus_bte;
-wire          wb_bus_err;
-wire          user_enable;
-wire          user_port_cmd_valid;
-wire          user_port_cmd_ready;
-wire          user_port_cmd_payload_we;
-wire   [24:0] user_port_cmd_payload_addr;
-wire          user_port_wdata_valid;
-wire          user_port_wdata_ready;
-wire  [127:0] user_port_wdata_payload_data;
-wire   [15:0] user_port_wdata_payload_we;
-wire          user_port_rdata_valid;
-wire          user_port_rdata_ready;
-wire  [127:0] user_port_rdata_payload_data;
-reg    [13:0] litedramcore_adr = 14'd0;
-reg           litedramcore_we = 1'd0;
-reg    [31:0] litedramcore_dat_w = 32'd0;
-wire   [31:0] litedramcore_dat_r;
-wire   [29:0] litedramcore_wishbone_adr;
-wire   [31:0] litedramcore_wishbone_dat_w;
-reg    [31:0] litedramcore_wishbone_dat_r = 32'd0;
-wire    [3:0] litedramcore_wishbone_sel;
-wire          litedramcore_wishbone_cyc;
-wire          litedramcore_wishbone_stb;
-reg           litedramcore_wishbone_ack = 1'd0;
-wire          litedramcore_wishbone_we;
-wire    [2:0] litedramcore_wishbone_cti;
-wire    [1:0] litedramcore_wishbone_bte;
-reg           litedramcore_wishbone_err = 1'd0;
-wire   [13:0] interface0_bank_bus_adr;
-wire          interface0_bank_bus_we;
-wire   [31:0] interface0_bank_bus_dat_w;
-reg    [31:0] interface0_bank_bus_dat_r = 32'd0;
-reg           csrbank0_init_done0_re = 1'd0;
-wire          csrbank0_init_done0_r;
-reg           csrbank0_init_done0_we = 1'd0;
-wire          csrbank0_init_done0_w;
-reg           csrbank0_init_error0_re = 1'd0;
-wire          csrbank0_init_error0_r;
-reg           csrbank0_init_error0_we = 1'd0;
-wire          csrbank0_init_error0_w;
-wire          csrbank0_sel;
-wire   [13:0] interface1_bank_bus_adr;
-wire          interface1_bank_bus_we;
-wire   [31:0] interface1_bank_bus_dat_w;
-reg    [31:0] interface1_bank_bus_dat_r = 32'd0;
-reg           csrbank1_dly_sel0_re = 1'd0;
-wire    [1:0] csrbank1_dly_sel0_r;
-reg           csrbank1_dly_sel0_we = 1'd0;
-wire    [1:0] csrbank1_dly_sel0_w;
-reg           csrbank1_burstdet_seen_re = 1'd0;
-wire    [1:0] csrbank1_burstdet_seen_r;
-reg           csrbank1_burstdet_seen_we = 1'd0;
-wire    [1:0] csrbank1_burstdet_seen_w;
-wire          csrbank1_sel;
-wire   [13:0] interface2_bank_bus_adr;
-wire          interface2_bank_bus_we;
-wire   [31:0] interface2_bank_bus_dat_w;
-reg    [31:0] interface2_bank_bus_dat_r = 32'd0;
-reg           csrbank2_dfii_control0_re = 1'd0;
-wire    [3:0] csrbank2_dfii_control0_r;
-reg           csrbank2_dfii_control0_we = 1'd0;
-wire    [3:0] csrbank2_dfii_control0_w;
-reg           csrbank2_dfii_pi0_command0_re = 1'd0;
-wire    [5:0] csrbank2_dfii_pi0_command0_r;
-reg           csrbank2_dfii_pi0_command0_we = 1'd0;
-wire    [5:0] csrbank2_dfii_pi0_command0_w;
-reg           csrbank2_dfii_pi0_address0_re = 1'd0;
-wire   [14:0] csrbank2_dfii_pi0_address0_r;
-reg           csrbank2_dfii_pi0_address0_we = 1'd0;
-wire   [14:0] csrbank2_dfii_pi0_address0_w;
-reg           csrbank2_dfii_pi0_baddress0_re = 1'd0;
-wire    [2:0] csrbank2_dfii_pi0_baddress0_r;
-reg           csrbank2_dfii_pi0_baddress0_we = 1'd0;
-wire    [2:0] csrbank2_dfii_pi0_baddress0_w;
-reg           csrbank2_dfii_pi0_wrdata1_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_wrdata1_r;
-reg           csrbank2_dfii_pi0_wrdata1_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_wrdata1_w;
-reg           csrbank2_dfii_pi0_wrdata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_wrdata0_r;
-reg           csrbank2_dfii_pi0_wrdata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_wrdata0_w;
-reg           csrbank2_dfii_pi0_rddata1_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_rddata1_r;
-reg           csrbank2_dfii_pi0_rddata1_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_rddata1_w;
-reg           csrbank2_dfii_pi0_rddata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_rddata0_r;
-reg           csrbank2_dfii_pi0_rddata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_rddata0_w;
-reg           csrbank2_dfii_pi1_command0_re = 1'd0;
-wire    [5:0] csrbank2_dfii_pi1_command0_r;
-reg           csrbank2_dfii_pi1_command0_we = 1'd0;
-wire    [5:0] csrbank2_dfii_pi1_command0_w;
-reg           csrbank2_dfii_pi1_address0_re = 1'd0;
-wire   [14:0] csrbank2_dfii_pi1_address0_r;
-reg           csrbank2_dfii_pi1_address0_we = 1'd0;
-wire   [14:0] csrbank2_dfii_pi1_address0_w;
-reg           csrbank2_dfii_pi1_baddress0_re = 1'd0;
-wire    [2:0] csrbank2_dfii_pi1_baddress0_r;
-reg           csrbank2_dfii_pi1_baddress0_we = 1'd0;
-wire    [2:0] csrbank2_dfii_pi1_baddress0_w;
-reg           csrbank2_dfii_pi1_wrdata1_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_wrdata1_r;
-reg           csrbank2_dfii_pi1_wrdata1_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_wrdata1_w;
-reg           csrbank2_dfii_pi1_wrdata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_wrdata0_r;
-reg           csrbank2_dfii_pi1_wrdata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_wrdata0_w;
-reg           csrbank2_dfii_pi1_rddata1_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_rddata1_r;
-reg           csrbank2_dfii_pi1_rddata1_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_rddata1_w;
-reg           csrbank2_dfii_pi1_rddata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_rddata0_r;
-reg           csrbank2_dfii_pi1_rddata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_rddata0_w;
-wire          csrbank2_sel;
-wire   [13:0] csr_interconnect_adr;
-wire          csr_interconnect_we;
-wire   [31:0] csr_interconnect_dat_w;
-wire   [31:0] csr_interconnect_dat_r;
-wire          litedramcore_litedramecp5ddrphycrg_ecp5pll;
-wire          litedramcore_litedramecp5ddrphycrg_locked;
-reg     [1:0] litedramcore_litedramcore_refresher_state = 2'd0;
-reg     [1:0] litedramcore_litedramcore_refresher_next_state = 2'd0;
-reg     [2:0] litedramcore_litedramcore_bankmachine0_state = 3'd0;
-reg     [2:0] litedramcore_litedramcore_bankmachine0_next_state = 3'd0;
-reg     [2:0] litedramcore_litedramcore_bankmachine1_state = 3'd0;
-reg     [2:0] litedramcore_litedramcore_bankmachine1_next_state = 3'd0;
-reg     [2:0] litedramcore_litedramcore_bankmachine2_state = 3'd0;
-reg     [2:0] litedramcore_litedramcore_bankmachine2_next_state = 3'd0;
-reg     [2:0] litedramcore_litedramcore_bankmachine3_state = 3'd0;
-reg     [2:0] litedramcore_litedramcore_bankmachine3_next_state = 3'd0;
-reg     [2:0] litedramcore_litedramcore_bankmachine4_state = 3'd0;
-reg     [2:0] litedramcore_litedramcore_bankmachine4_next_state = 3'd0;
-reg     [2:0] litedramcore_litedramcore_bankmachine5_state = 3'd0;
-reg     [2:0] litedramcore_litedramcore_bankmachine5_next_state = 3'd0;
-reg     [2:0] litedramcore_litedramcore_bankmachine6_state = 3'd0;
-reg     [2:0] litedramcore_litedramcore_bankmachine6_next_state = 3'd0;
-reg     [2:0] litedramcore_litedramcore_bankmachine7_state = 3'd0;
-reg     [2:0] litedramcore_litedramcore_bankmachine7_next_state = 3'd0;
-reg     [3:0] litedramcore_litedramcore_multiplexer_state = 4'd0;
-reg     [3:0] litedramcore_litedramcore_multiplexer_next_state = 4'd0;
-wire          litedramcore_litedramcore_roundrobin0_request;
-wire          litedramcore_litedramcore_roundrobin0_grant;
-wire          litedramcore_litedramcore_roundrobin0_ce;
-wire          litedramcore_litedramcore_roundrobin1_request;
-wire          litedramcore_litedramcore_roundrobin1_grant;
-wire          litedramcore_litedramcore_roundrobin1_ce;
-wire          litedramcore_litedramcore_roundrobin2_request;
-wire          litedramcore_litedramcore_roundrobin2_grant;
-wire          litedramcore_litedramcore_roundrobin2_ce;
-wire          litedramcore_litedramcore_roundrobin3_request;
-wire          litedramcore_litedramcore_roundrobin3_grant;
-wire          litedramcore_litedramcore_roundrobin3_ce;
-wire          litedramcore_litedramcore_roundrobin4_request;
-wire          litedramcore_litedramcore_roundrobin4_grant;
-wire          litedramcore_litedramcore_roundrobin4_ce;
-wire          litedramcore_litedramcore_roundrobin5_request;
-wire          litedramcore_litedramcore_roundrobin5_grant;
-wire          litedramcore_litedramcore_roundrobin5_ce;
-wire          litedramcore_litedramcore_roundrobin6_request;
-wire          litedramcore_litedramcore_roundrobin6_grant;
-wire          litedramcore_litedramcore_roundrobin6_ce;
-wire          litedramcore_litedramcore_roundrobin7_request;
-wire          litedramcore_litedramcore_roundrobin7_grant;
-wire          litedramcore_litedramcore_roundrobin7_ce;
-reg           litedramcore_litedramcore_locked0 = 1'd0;
-reg           litedramcore_litedramcore_locked1 = 1'd0;
-reg           litedramcore_litedramcore_locked2 = 1'd0;
-reg           litedramcore_litedramcore_locked3 = 1'd0;
-reg           litedramcore_litedramcore_locked4 = 1'd0;
-reg           litedramcore_litedramcore_locked5 = 1'd0;
-reg           litedramcore_litedramcore_locked6 = 1'd0;
-reg           litedramcore_litedramcore_locked7 = 1'd0;
-reg           litedramcore_litedramcore_new_master_wdata_ready0 = 1'd0;
-reg           litedramcore_litedramcore_new_master_wdata_ready1 = 1'd0;
-reg           litedramcore_litedramcore_new_master_wdata_ready2 = 1'd0;
-reg           litedramcore_litedramcore_new_master_wdata_ready3 = 1'd0;
-reg           litedramcore_litedramcore_new_master_rdata_valid0 = 1'd0;
-reg           litedramcore_litedramcore_new_master_rdata_valid1 = 1'd0;
-reg           litedramcore_litedramcore_new_master_rdata_valid2 = 1'd0;
-reg           litedramcore_litedramcore_new_master_rdata_valid3 = 1'd0;
-reg           litedramcore_litedramcore_new_master_rdata_valid4 = 1'd0;
-reg           litedramcore_litedramcore_new_master_rdata_valid5 = 1'd0;
-reg           litedramcore_litedramcore_new_master_rdata_valid6 = 1'd0;
-reg           litedramcore_litedramcore_new_master_rdata_valid7 = 1'd0;
-reg           litedramcore_litedramcore_new_master_rdata_valid8 = 1'd0;
-reg           litedramcore_litedramcore_new_master_rdata_valid9 = 1'd0;
-reg           litedramcore_litedramcore_new_master_rdata_valid10 = 1'd0;
-reg           litedramcore_litedramcore_new_master_rdata_valid11 = 1'd0;
-reg           litedramcore_litedramcore_new_master_rdata_valid12 = 1'd0;
-reg           litedramcore_litedramcore_new_master_rdata_valid13 = 1'd0;
-reg     [1:0] litedramcore_state = 2'd0;
-reg     [1:0] litedramcore_next_state = 2'd0;
-reg    [31:0] litedramcore_dat_w_next_value0 = 32'd0;
-reg           litedramcore_dat_w_next_value_ce0 = 1'd0;
-reg    [13:0] litedramcore_adr_next_value1 = 14'd0;
-reg           litedramcore_adr_next_value_ce1 = 1'd0;
-reg           litedramcore_we_next_value2 = 1'd0;
-reg           litedramcore_we_next_value_ce2 = 1'd0;
-reg           rhs_array_muxed0 = 1'd0;
-reg    [14:0] rhs_array_muxed1 = 15'd0;
-reg     [2:0] rhs_array_muxed2 = 3'd0;
-reg           rhs_array_muxed3 = 1'd0;
-reg           rhs_array_muxed4 = 1'd0;
-reg           rhs_array_muxed5 = 1'd0;
-reg           t_array_muxed0 = 1'd0;
-reg           t_array_muxed1 = 1'd0;
-reg           t_array_muxed2 = 1'd0;
-reg           rhs_array_muxed6 = 1'd0;
-reg    [14:0] rhs_array_muxed7 = 15'd0;
-reg     [2:0] rhs_array_muxed8 = 3'd0;
-reg           rhs_array_muxed9 = 1'd0;
-reg           rhs_array_muxed10 = 1'd0;
-reg           rhs_array_muxed11 = 1'd0;
-reg           t_array_muxed3 = 1'd0;
-reg           t_array_muxed4 = 1'd0;
-reg           t_array_muxed5 = 1'd0;
-reg    [21:0] rhs_array_muxed12 = 22'd0;
-reg           rhs_array_muxed13 = 1'd0;
-reg           rhs_array_muxed14 = 1'd0;
-reg    [21:0] rhs_array_muxed15 = 22'd0;
-reg           rhs_array_muxed16 = 1'd0;
-reg           rhs_array_muxed17 = 1'd0;
-reg    [21:0] rhs_array_muxed18 = 22'd0;
-reg           rhs_array_muxed19 = 1'd0;
-reg           rhs_array_muxed20 = 1'd0;
-reg    [21:0] rhs_array_muxed21 = 22'd0;
-reg           rhs_array_muxed22 = 1'd0;
-reg           rhs_array_muxed23 = 1'd0;
-reg    [21:0] rhs_array_muxed24 = 22'd0;
-reg           rhs_array_muxed25 = 1'd0;
-reg           rhs_array_muxed26 = 1'd0;
-reg    [21:0] rhs_array_muxed27 = 22'd0;
-reg           rhs_array_muxed28 = 1'd0;
-reg           rhs_array_muxed29 = 1'd0;
-reg    [21:0] rhs_array_muxed30 = 22'd0;
-reg           rhs_array_muxed31 = 1'd0;
-reg           rhs_array_muxed32 = 1'd0;
-reg    [21:0] rhs_array_muxed33 = 22'd0;
-reg           rhs_array_muxed34 = 1'd0;
-reg           rhs_array_muxed35 = 1'd0;
-reg     [2:0] array_muxed0 = 3'd0;
-reg    [14:0] array_muxed1 = 15'd0;
-reg           array_muxed2 = 1'd0;
-reg           array_muxed3 = 1'd0;
-reg           array_muxed4 = 1'd0;
-reg           array_muxed5 = 1'd0;
-reg           array_muxed6 = 1'd0;
-reg     [2:0] array_muxed7 = 3'd0;
-reg    [14:0] array_muxed8 = 15'd0;
-reg           array_muxed9 = 1'd0;
-reg           array_muxed10 = 1'd0;
-reg           array_muxed11 = 1'd0;
-reg           array_muxed12 = 1'd0;
-reg           array_muxed13 = 1'd0;
-wire          latticeecp5asyncresetsynchronizerimpl0_rst1;
-wire          latticeecp5asyncresetsynchronizerimpl0_expr;
-wire          latticeecp5asyncresetsynchronizerimpl1_rst1;
-wire          latticeecp5asyncresetsynchronizerimpl2_rst1;
-wire          latticeecp5asyncresetsynchronizerimpl3_rst1;
-reg           regs0 = 1'd0;
-reg           regs1 = 1'd0;
+wire          we;
 
 //------------------------------------------------------------------------------
 // Combinatorial Logic
@@ -1902,6 +2235,17 @@ assign user_port_wdata_payload_data = user_port_native_0_wdata_data;
 assign user_port_native_0_rdata_valid = (user_port_rdata_valid & user_enable);
 assign user_port_rdata_ready = (user_port_native_0_rdata_ready & user_enable);
 assign user_port_native_0_rdata_data = user_port_rdata_payload_data;
+assign interface0_adr = wb_bus_adr;
+assign interface0_dat_w = wb_bus_dat_w;
+assign wb_bus_dat_r = interface0_dat_r;
+assign interface0_sel = wb_bus_sel;
+assign interface0_cyc = wb_bus_cyc;
+assign interface0_stb = wb_bus_stb;
+assign wb_bus_ack = interface0_ack;
+assign interface0_we = wb_bus_we;
+assign interface0_cti = wb_bus_cti;
+assign interface0_bte = wb_bus_bte;
+assign wb_bus_err = interface0_err;
 assign por_clk = clk;
 assign crg_por_done = (crg_por_count == 1'd0);
 assign crg_reset1 = (((~crg_por_done) | rst) | crg_rst);
@@ -1909,7 +2253,7 @@ assign pll_locked = crg_locked;
 assign crg_clkin = clk;
 assign sys2x_i_clk = crg_clkout0;
 assign init_clk = crg_clkout1;
-assign crg_locked = (litedramcore_litedramecp5ddrphycrg_locked & (~crg_reset1));
+assign crg_locked = (litedramecp5ddrphycrg_locked & (~crg_reset1));
 always @(*) begin
     ddrphy_dm_o_data0 <= 8'd0;
     ddrphy_dm_o_data0[0] <= ddrphy_dfi_p0_wrdata_mask[1];
@@ -2614,6 +2958,9 @@ always @(*) begin
             litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
         end else begin
             litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+            if (1'd0) begin
+                litedramcore_master_p0_cs_n <= {2{litedramcore_slave_p0_cs_n}};
+            end
         end
     end else begin
         litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
@@ -2796,6 +3143,9 @@ always @(*) begin
             litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n;
         end else begin
             litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
+            if (1'd0) begin
+                litedramcore_master_p1_cs_n <= {2{litedramcore_slave_p1_cs_n}};
+            end
         end
     end else begin
         litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n;
@@ -3051,10 +3401,22 @@ always @(*) begin
         litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n;
     end
 end
-assign litedramcore_csr_dfi_p0_cke = litedramcore_cke;
-assign litedramcore_csr_dfi_p1_cke = litedramcore_cke;
-assign litedramcore_csr_dfi_p0_odt = litedramcore_odt;
-assign litedramcore_csr_dfi_p1_odt = litedramcore_odt;
+always @(*) begin
+    litedramcore_csr_dfi_p0_cke <= 1'd0;
+    litedramcore_csr_dfi_p0_cke <= litedramcore_cke;
+end
+always @(*) begin
+    litedramcore_csr_dfi_p1_cke <= 1'd0;
+    litedramcore_csr_dfi_p1_cke <= litedramcore_cke;
+end
+always @(*) begin
+    litedramcore_csr_dfi_p0_odt <= 1'd0;
+    litedramcore_csr_dfi_p0_odt <= litedramcore_odt;
+end
+always @(*) begin
+    litedramcore_csr_dfi_p1_odt <= 1'd0;
+    litedramcore_csr_dfi_p1_odt <= litedramcore_odt;
+end
 assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n;
 assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n;
 always @(*) begin
@@ -3068,7 +3430,15 @@ end
 always @(*) begin
     litedramcore_csr_dfi_p0_cs_n <= 1'd1;
     if (litedramcore_phaseinjector0_command_issue_re) begin
-        litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}};
+        if (litedramcore_phaseinjector0_csrfield_cs_top) begin
+            litedramcore_csr_dfi_p0_cs_n <= 2'd2;
+        end else begin
+            if (litedramcore_phaseinjector0_csrfield_cs_bottom) begin
+                litedramcore_csr_dfi_p0_cs_n <= 1'd1;
+            end else begin
+                litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}};
+            end
+        end
     end else begin
         litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
     end
@@ -3106,7 +3476,15 @@ end
 always @(*) begin
     litedramcore_csr_dfi_p1_cs_n <= 1'd1;
     if (litedramcore_phaseinjector1_command_issue_re) begin
-        litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}};
+        if (litedramcore_phaseinjector1_csrfield_cs_top) begin
+            litedramcore_csr_dfi_p1_cs_n <= 2'd2;
+        end else begin
+            if (litedramcore_phaseinjector1_csrfield_cs_bottom) begin
+                litedramcore_csr_dfi_p1_cs_n <= 1'd1;
+            end else begin
+                litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}};
+            end
+        end
     end else begin
         litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
     end
@@ -3203,32 +3581,32 @@ assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0);
 assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
 assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
 always @(*) begin
-    litedramcore_litedramcore_refresher_next_state <= 2'd0;
-    litedramcore_litedramcore_refresher_next_state <= litedramcore_litedramcore_refresher_state;
-    case (litedramcore_litedramcore_refresher_state)
+    litedramcore_refresher_next_state <= 2'd0;
+    litedramcore_refresher_next_state <= litedramcore_refresher_state;
+    case (litedramcore_refresher_state)
         1'd1: begin
             if (litedramcore_cmd_ready) begin
-                litedramcore_litedramcore_refresher_next_state <= 2'd2;
+                litedramcore_refresher_next_state <= 2'd2;
             end
         end
         2'd2: begin
             if (litedramcore_sequencer_done0) begin
                 if (litedramcore_wants_zqcs) begin
-                    litedramcore_litedramcore_refresher_next_state <= 2'd3;
+                    litedramcore_refresher_next_state <= 2'd3;
                 end else begin
-                    litedramcore_litedramcore_refresher_next_state <= 1'd0;
+                    litedramcore_refresher_next_state <= 1'd0;
                 end
             end
         end
         2'd3: begin
             if (litedramcore_zqcs_executer_done) begin
-                litedramcore_litedramcore_refresher_next_state <= 1'd0;
+                litedramcore_refresher_next_state <= 1'd0;
             end
         end
         default: begin
             if (1'd1) begin
                 if (litedramcore_wants_refresh) begin
-                    litedramcore_litedramcore_refresher_next_state <= 1'd1;
+                    litedramcore_refresher_next_state <= 1'd1;
                 end
             end
         end
@@ -3236,7 +3614,7 @@ always @(*) begin
 end
 always @(*) begin
     litedramcore_sequencer_start0 <= 1'd0;
-    case (litedramcore_litedramcore_refresher_state)
+    case (litedramcore_refresher_state)
         1'd1: begin
             if (litedramcore_cmd_ready) begin
                 litedramcore_sequencer_start0 <= 1'd1;
@@ -3252,7 +3630,7 @@ always @(*) begin
 end
 always @(*) begin
     litedramcore_cmd_valid <= 1'd0;
-    case (litedramcore_litedramcore_refresher_state)
+    case (litedramcore_refresher_state)
         1'd1: begin
             litedramcore_cmd_valid <= 1'd1;
         end
@@ -3277,7 +3655,7 @@ always @(*) begin
 end
 always @(*) begin
     litedramcore_zqcs_executer_start <= 1'd0;
-    case (litedramcore_litedramcore_refresher_state)
+    case (litedramcore_refresher_state)
         1'd1: begin
         end
         2'd2: begin
@@ -3296,7 +3674,7 @@ always @(*) begin
 end
 always @(*) begin
     litedramcore_cmd_last <= 1'd0;
-    case (litedramcore_litedramcore_refresher_state)
+    case (litedramcore_refresher_state)
         1'd1: begin
         end
         2'd2: begin
@@ -3395,169 +3773,54 @@ assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_
 assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we;
 assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr;
 always @(*) begin
-    litedramcore_litedramcore_bankmachine0_next_state <= 3'd0;
-    litedramcore_litedramcore_bankmachine0_next_state <= litedramcore_litedramcore_bankmachine0_state;
-    case (litedramcore_litedramcore_bankmachine0_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                if (litedramcore_bankmachine0_cmd_ready) begin
-                    litedramcore_litedramcore_bankmachine0_next_state <= 3'd5;
-                end
-            end
-        end
-        2'd2: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_litedramcore_bankmachine0_next_state <= 3'd5;
-            end
-        end
-        2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                if (litedramcore_bankmachine0_cmd_ready) begin
-                    litedramcore_litedramcore_bankmachine0_next_state <= 3'd6;
-                end
-            end
-        end
-        3'd4: begin
-            if ((~litedramcore_bankmachine0_refresh_req)) begin
-                litedramcore_litedramcore_bankmachine0_next_state <= 1'd0;
-            end
-        end
-        3'd5: begin
-            litedramcore_litedramcore_bankmachine0_next_state <= 2'd3;
-        end
-        3'd6: begin
-            litedramcore_litedramcore_bankmachine0_next_state <= 1'd0;
-        end
-        default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
-                litedramcore_litedramcore_bankmachine0_next_state <= 3'd4;
-            end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
-                                litedramcore_litedramcore_bankmachine0_next_state <= 2'd2;
-                            end
-                        end else begin
-                            litedramcore_litedramcore_bankmachine0_next_state <= 1'd1;
-                        end
-                    end else begin
-                        litedramcore_litedramcore_bankmachine0_next_state <= 2'd3;
-                    end
-                end
-            end
-        end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine0_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine0_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine0_state)
+    litedramcore_bankmachine0_next_state <= 3'd0;
+    litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
+    case (litedramcore_bankmachine0_state)
         1'd1: begin
             if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+                if (litedramcore_bankmachine0_cmd_ready) begin
+                    litedramcore_bankmachine0_next_state <= 3'd5;
+                end
             end
         end
         2'd2: begin
+            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+                litedramcore_bankmachine0_next_state <= 3'd5;
+            end
         end
         2'd3: begin
             if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+                if (litedramcore_bankmachine0_cmd_ready) begin
+                    litedramcore_bankmachine0_next_state <= 3'd6;
+                end
             end
         end
         3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine0_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+            if ((~litedramcore_bankmachine0_refresh_req)) begin
+                litedramcore_bankmachine0_next_state <= 1'd0;
             end
         end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
         3'd5: begin
+            litedramcore_bankmachine0_next_state <= 2'd3;
         end
         3'd6: begin
+            litedramcore_bankmachine0_next_state <= 1'd0;
         end
         default: begin
             if (litedramcore_bankmachine0_refresh_req) begin
+                litedramcore_bankmachine0_next_state <= 3'd4;
             end else begin
                 if (litedramcore_bankmachine0_source_source_valid) begin
                     if (litedramcore_bankmachine0_row_opened) begin
                         if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
-                                litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
-                            end else begin
+                            if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
+                                litedramcore_bankmachine0_next_state <= 2'd2;
                             end
                         end else begin
+                            litedramcore_bankmachine0_next_state <= 1'd1;
                         end
                     end else begin
+                        litedramcore_bankmachine0_next_state <= 2'd3;
                     end
                 end
             end
@@ -3566,7 +3829,7 @@ always @(*) begin
 end
 always @(*) begin
     litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine0_state)
+    case (litedramcore_bankmachine0_state)
         1'd1: begin
             if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
                 litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
@@ -3592,7 +3855,7 @@ always @(*) begin
 end
 always @(*) begin
     litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine0_state)
+    case (litedramcore_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -3626,7 +3889,7 @@ always @(*) begin
 end
 always @(*) begin
     litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine0_state)
+    case (litedramcore_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -3660,7 +3923,7 @@ always @(*) begin
 end
 always @(*) begin
     litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine0_state)
+    case (litedramcore_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -3694,7 +3957,7 @@ always @(*) begin
 end
 always @(*) begin
     litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine0_state)
+    case (litedramcore_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -3728,7 +3991,7 @@ always @(*) begin
 end
 always @(*) begin
     litedramcore_bankmachine0_refresh_gnt <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine0_state)
+    case (litedramcore_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -3750,7 +4013,7 @@ always @(*) begin
 end
 always @(*) begin
     litedramcore_bankmachine0_row_open <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine0_state)
+    case (litedramcore_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -3772,7 +4035,7 @@ always @(*) begin
 end
 always @(*) begin
     litedramcore_bankmachine0_cmd_valid <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine0_state)
+    case (litedramcore_bankmachine0_state)
         1'd1: begin
             if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
                 litedramcore_bankmachine0_cmd_valid <= 1'd1;
@@ -3809,7 +4072,7 @@ always @(*) begin
 end
 always @(*) begin
     litedramcore_bankmachine0_row_close <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine0_state)
+    case (litedramcore_bankmachine0_state)
         1'd1: begin
             litedramcore_bankmachine0_row_close <= 1'd1;
         end
@@ -3829,6 +4092,121 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+    case (litedramcore_bankmachine0_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (litedramcore_bankmachine0_trccon_ready) begin
+                litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+    case (litedramcore_bankmachine0_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+            if (litedramcore_bankmachine0_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine0_source_source_valid) begin
+                    if (litedramcore_bankmachine0_row_opened) begin
+                        if (litedramcore_bankmachine0_row_hit) begin
+                            litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+    case (litedramcore_bankmachine0_state)
+        1'd1: begin
+            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+                litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (litedramcore_bankmachine0_trccon_ready) begin
+                litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+    case (litedramcore_bankmachine0_state)
+        1'd1: begin
+            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+                litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+            if (litedramcore_bankmachine0_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine0_source_source_valid) begin
+                    if (litedramcore_bankmachine0_row_opened) begin
+                        if (litedramcore_bankmachine0_row_hit) begin
+                            if (litedramcore_bankmachine0_source_source_payload_we) begin
+                                litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid;
 assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready;
 assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we;
@@ -3908,54 +4286,54 @@ assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_
 assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we;
 assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr;
 always @(*) begin
-    litedramcore_litedramcore_bankmachine1_next_state <= 3'd0;
-    litedramcore_litedramcore_bankmachine1_next_state <= litedramcore_litedramcore_bankmachine1_state;
-    case (litedramcore_litedramcore_bankmachine1_state)
+    litedramcore_bankmachine1_next_state <= 3'd0;
+    litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
+    case (litedramcore_bankmachine1_state)
         1'd1: begin
             if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
                 if (litedramcore_bankmachine1_cmd_ready) begin
-                    litedramcore_litedramcore_bankmachine1_next_state <= 3'd5;
+                    litedramcore_bankmachine1_next_state <= 3'd5;
                 end
             end
         end
         2'd2: begin
             if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_litedramcore_bankmachine1_next_state <= 3'd5;
+                litedramcore_bankmachine1_next_state <= 3'd5;
             end
         end
         2'd3: begin
             if (litedramcore_bankmachine1_trccon_ready) begin
                 if (litedramcore_bankmachine1_cmd_ready) begin
-                    litedramcore_litedramcore_bankmachine1_next_state <= 3'd6;
+                    litedramcore_bankmachine1_next_state <= 3'd6;
                 end
             end
         end
         3'd4: begin
             if ((~litedramcore_bankmachine1_refresh_req)) begin
-                litedramcore_litedramcore_bankmachine1_next_state <= 1'd0;
+                litedramcore_bankmachine1_next_state <= 1'd0;
             end
         end
         3'd5: begin
-            litedramcore_litedramcore_bankmachine1_next_state <= 2'd3;
+            litedramcore_bankmachine1_next_state <= 2'd3;
         end
         3'd6: begin
-            litedramcore_litedramcore_bankmachine1_next_state <= 1'd0;
+            litedramcore_bankmachine1_next_state <= 1'd0;
         end
         default: begin
             if (litedramcore_bankmachine1_refresh_req) begin
-                litedramcore_litedramcore_bankmachine1_next_state <= 3'd4;
+                litedramcore_bankmachine1_next_state <= 3'd4;
             end else begin
                 if (litedramcore_bankmachine1_source_source_valid) begin
                     if (litedramcore_bankmachine1_row_opened) begin
                         if (litedramcore_bankmachine1_row_hit) begin
                             if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
-                                litedramcore_litedramcore_bankmachine1_next_state <= 2'd2;
+                                litedramcore_bankmachine1_next_state <= 2'd2;
                             end
                         end else begin
-                            litedramcore_litedramcore_bankmachine1_next_state <= 1'd1;
+                            litedramcore_bankmachine1_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_litedramcore_bankmachine1_next_state <= 2'd3;
+                        litedramcore_bankmachine1_next_state <= 2'd3;
                     end
                 end
             end
@@ -3963,8 +4341,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine1_state)
+    litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+    case (litedramcore_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
@@ -3983,7 +4361,10 @@ always @(*) begin
                 if (litedramcore_bankmachine1_source_source_valid) begin
                     if (litedramcore_bankmachine1_row_opened) begin
                         if (litedramcore_bankmachine1_row_hit) begin
-                            litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+                            if (litedramcore_bankmachine1_source_source_payload_we) begin
+                            end else begin
+                                litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
+                            end
                         end else begin
                         end
                     end else begin
@@ -3994,18 +4375,37 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine1_state)
+    litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+    case (litedramcore_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            if (litedramcore_bankmachine1_twtpcon_ready) begin
+                litedramcore_bankmachine1_refresh_gnt <= 1'd1;
             end
         end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    litedramcore_bankmachine1_row_open <= 1'd0;
+    case (litedramcore_bankmachine1_state)
+        1'd1: begin
+        end
         2'd2: begin
         end
         2'd3: begin
             if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+                litedramcore_bankmachine1_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -4019,16 +4419,19 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine1_state)
+    litedramcore_bankmachine1_cmd_valid <= 1'd0;
+    case (litedramcore_bankmachine1_state)
         1'd1: begin
             if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+                litedramcore_bankmachine1_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (litedramcore_bankmachine1_trccon_ready) begin
+                litedramcore_bankmachine1_cmd_valid <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -4042,10 +4445,7 @@ always @(*) begin
                 if (litedramcore_bankmachine1_source_source_valid) begin
                     if (litedramcore_bankmachine1_row_opened) begin
                         if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                                litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
-                            end else begin
-                            end
+                            litedramcore_bankmachine1_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -4056,22 +4456,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine1_state)
+    litedramcore_bankmachine1_row_close <= 1'd0;
+    case (litedramcore_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
-            end
+            litedramcore_bankmachine1_row_close <= 1'd1;
         end
         2'd2: begin
+            litedramcore_bankmachine1_row_close <= 1'd1;
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         3'd4: begin
-            litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+            litedramcore_bankmachine1_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -4082,13 +4478,16 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine1_state)
+    litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+    case (litedramcore_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (litedramcore_bankmachine1_trccon_ready) begin
+                litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -4097,27 +4496,12 @@ always @(*) begin
         3'd6: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine1_state)
+    litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+    case (litedramcore_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
@@ -4136,10 +4520,7 @@ always @(*) begin
                 if (litedramcore_bankmachine1_source_source_valid) begin
                     if (litedramcore_bankmachine1_row_opened) begin
                         if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                                litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
-                            end else begin
-                            end
+                            litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -4150,43 +4531,37 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine1_state)
+    litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+    case (litedramcore_bankmachine1_state)
         1'd1: begin
+            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+                litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (litedramcore_bankmachine1_trccon_ready) begin
+                litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+            end
         end
         3'd4: begin
         end
         3'd5: begin
         end
-        3'd6: begin
-        end
-        default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                                litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
+        3'd6: begin
+        end
+        default: begin
+        end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine1_state)
+    litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+    case (litedramcore_bankmachine1_state)
         1'd1: begin
+            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+                litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+            end
         end
         2'd2: begin
         end
@@ -4205,8 +4580,8 @@ always @(*) begin
                     if (litedramcore_bankmachine1_row_opened) begin
                         if (litedramcore_bankmachine1_row_hit) begin
                             if (litedramcore_bankmachine1_source_source_payload_we) begin
+                                litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
                             end else begin
-                                litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
                             end
                         end else begin
                         end
@@ -4218,40 +4593,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_refresh_gnt <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine1_state)
+    litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+    case (litedramcore_bankmachine1_state)
         1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            if (litedramcore_bankmachine1_twtpcon_ready) begin
-                litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+                litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
             end
         end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine1_row_open <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine1_state)
-        1'd1: begin
-        end
         2'd2: begin
         end
         2'd3: begin
             if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_row_open <= 1'd1;
+                litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
+            litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -4262,19 +4619,13 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_valid <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine1_state)
+    litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+    case (litedramcore_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_cmd_valid <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_cmd_valid <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -4288,7 +4639,10 @@ always @(*) begin
                 if (litedramcore_bankmachine1_source_source_valid) begin
                     if (litedramcore_bankmachine1_row_opened) begin
                         if (litedramcore_bankmachine1_row_hit) begin
-                            litedramcore_bankmachine1_cmd_valid <= 1'd1;
+                            if (litedramcore_bankmachine1_source_source_payload_we) begin
+                            end else begin
+                                litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+                            end
                         end else begin
                         end
                     end else begin
@@ -4299,38 +4653,47 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_row_close <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine1_state)
+    litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+    case (litedramcore_bankmachine1_state)
         1'd1: begin
-            litedramcore_bankmachine1_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine1_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine1_row_close <= 1'd1;
         end
         3'd5: begin
         end
         3'd6: begin
         end
         default: begin
+            if (litedramcore_bankmachine1_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine1_source_source_valid) begin
+                    if (litedramcore_bankmachine1_row_opened) begin
+                        if (litedramcore_bankmachine1_row_hit) begin
+                            if (litedramcore_bankmachine1_source_source_payload_we) begin
+                                litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine1_state)
+    litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+    case (litedramcore_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -4339,6 +4702,21 @@ always @(*) begin
         3'd6: begin
         end
         default: begin
+            if (litedramcore_bankmachine1_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine1_source_source_valid) begin
+                    if (litedramcore_bankmachine1_row_opened) begin
+                        if (litedramcore_bankmachine1_row_hit) begin
+                            if (litedramcore_bankmachine1_source_source_payload_we) begin
+                                litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
@@ -4421,54 +4799,54 @@ assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_
 assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we;
 assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr;
 always @(*) begin
-    litedramcore_litedramcore_bankmachine2_next_state <= 3'd0;
-    litedramcore_litedramcore_bankmachine2_next_state <= litedramcore_litedramcore_bankmachine2_state;
-    case (litedramcore_litedramcore_bankmachine2_state)
+    litedramcore_bankmachine2_next_state <= 3'd0;
+    litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
+    case (litedramcore_bankmachine2_state)
         1'd1: begin
             if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
                 if (litedramcore_bankmachine2_cmd_ready) begin
-                    litedramcore_litedramcore_bankmachine2_next_state <= 3'd5;
+                    litedramcore_bankmachine2_next_state <= 3'd5;
                 end
             end
         end
         2'd2: begin
             if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_litedramcore_bankmachine2_next_state <= 3'd5;
+                litedramcore_bankmachine2_next_state <= 3'd5;
             end
         end
         2'd3: begin
             if (litedramcore_bankmachine2_trccon_ready) begin
                 if (litedramcore_bankmachine2_cmd_ready) begin
-                    litedramcore_litedramcore_bankmachine2_next_state <= 3'd6;
+                    litedramcore_bankmachine2_next_state <= 3'd6;
                 end
             end
         end
         3'd4: begin
             if ((~litedramcore_bankmachine2_refresh_req)) begin
-                litedramcore_litedramcore_bankmachine2_next_state <= 1'd0;
+                litedramcore_bankmachine2_next_state <= 1'd0;
             end
         end
         3'd5: begin
-            litedramcore_litedramcore_bankmachine2_next_state <= 2'd3;
+            litedramcore_bankmachine2_next_state <= 2'd3;
         end
         3'd6: begin
-            litedramcore_litedramcore_bankmachine2_next_state <= 1'd0;
+            litedramcore_bankmachine2_next_state <= 1'd0;
         end
         default: begin
             if (litedramcore_bankmachine2_refresh_req) begin
-                litedramcore_litedramcore_bankmachine2_next_state <= 3'd4;
+                litedramcore_bankmachine2_next_state <= 3'd4;
             end else begin
                 if (litedramcore_bankmachine2_source_source_valid) begin
                     if (litedramcore_bankmachine2_row_opened) begin
                         if (litedramcore_bankmachine2_row_hit) begin
                             if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
-                                litedramcore_litedramcore_bankmachine2_next_state <= 2'd2;
+                                litedramcore_bankmachine2_next_state <= 2'd2;
                             end
                         end else begin
-                            litedramcore_litedramcore_bankmachine2_next_state <= 1'd1;
+                            litedramcore_bankmachine2_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_litedramcore_bankmachine2_next_state <= 2'd3;
+                        litedramcore_bankmachine2_next_state <= 2'd3;
                     end
                 end
             end
@@ -4476,82 +4854,39 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine2_state)
+    litedramcore_bankmachine2_row_close <= 1'd0;
+    case (litedramcore_bankmachine2_state)
         1'd1: begin
+            litedramcore_bankmachine2_row_close <= 1'd1;
         end
         2'd2: begin
+            litedramcore_bankmachine2_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
+            litedramcore_bankmachine2_row_close <= 1'd1;
         end
         3'd5: begin
         end
         3'd6: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine2_state)
+    litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+    case (litedramcore_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
-                                litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
+            if (litedramcore_bankmachine2_trccon_ready) begin
+                litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
             end
         end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine2_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
         3'd4: begin
         end
         3'd5: begin
@@ -4559,27 +4894,12 @@ always @(*) begin
         3'd6: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
-                                litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine2_state)
+    litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+    case (litedramcore_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -4598,10 +4918,7 @@ always @(*) begin
                 if (litedramcore_bankmachine2_source_source_valid) begin
                     if (litedramcore_bankmachine2_row_opened) begin
                         if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
-                            end
+                            litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -4612,37 +4929,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_refresh_gnt <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine2_state)
+    litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+    case (litedramcore_bankmachine2_state)
         1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            if (litedramcore_bankmachine2_twtpcon_ready) begin
-                litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+                litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
             end
         end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine2_row_open <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine2_state)
-        1'd1: begin
-        end
         2'd2: begin
         end
         2'd3: begin
             if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_row_open <= 1'd1;
+                litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -4656,19 +4954,16 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_valid <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine2_state)
+    litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+    case (litedramcore_bankmachine2_state)
         1'd1: begin
             if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_cmd_valid <= 1'd1;
+                litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_cmd_valid <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -4682,7 +4977,10 @@ always @(*) begin
                 if (litedramcore_bankmachine2_source_source_valid) begin
                     if (litedramcore_bankmachine2_row_opened) begin
                         if (litedramcore_bankmachine2_row_hit) begin
-                            litedramcore_bankmachine2_cmd_valid <= 1'd1;
+                            if (litedramcore_bankmachine2_source_source_payload_we) begin
+                                litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+                            end else begin
+                            end
                         end else begin
                         end
                     end else begin
@@ -4693,18 +4991,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_row_close <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine2_state)
+    litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+    case (litedramcore_bankmachine2_state)
         1'd1: begin
-            litedramcore_bankmachine2_row_close <= 1'd1;
+            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+                litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         2'd2: begin
-            litedramcore_bankmachine2_row_close <= 1'd1;
         end
         2'd3: begin
+            if (litedramcore_bankmachine2_trccon_ready) begin
+                litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         3'd4: begin
-            litedramcore_bankmachine2_row_close <= 1'd1;
+            litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -4715,19 +5017,13 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine2_state)
+    litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+    case (litedramcore_bankmachine2_state)
         1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -4736,20 +5032,32 @@ always @(*) begin
         3'd6: begin
         end
         default: begin
+            if (litedramcore_bankmachine2_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine2_source_source_valid) begin
+                    if (litedramcore_bankmachine2_row_opened) begin
+                        if (litedramcore_bankmachine2_row_hit) begin
+                            if (litedramcore_bankmachine2_source_source_payload_we) begin
+                            end else begin
+                                litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine2_state)
+    litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+    case (litedramcore_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -4758,12 +5066,27 @@ always @(*) begin
         3'd6: begin
         end
         default: begin
+            if (litedramcore_bankmachine2_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine2_source_source_valid) begin
+                    if (litedramcore_bankmachine2_row_opened) begin
+                        if (litedramcore_bankmachine2_row_hit) begin
+                            if (litedramcore_bankmachine2_source_source_payload_we) begin
+                                litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine2_state)
+    litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+    case (litedramcore_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -4782,7 +5105,10 @@ always @(*) begin
                 if (litedramcore_bankmachine2_source_source_valid) begin
                     if (litedramcore_bankmachine2_row_opened) begin
                         if (litedramcore_bankmachine2_row_hit) begin
-                            litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+                            if (litedramcore_bankmachine2_source_source_payload_we) begin
+                                litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
+                            end else begin
+                            end
                         end else begin
                         end
                     end else begin
@@ -4793,12 +5119,9 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine2_state)
+    litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+    case (litedramcore_bankmachine2_state)
         1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
-            end
         end
         2'd2: begin
         end
@@ -4817,8 +5140,8 @@ always @(*) begin
                     if (litedramcore_bankmachine2_row_opened) begin
                         if (litedramcore_bankmachine2_row_hit) begin
                             if (litedramcore_bankmachine2_source_source_payload_we) begin
-                                litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
                             end else begin
+                                litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
                             end
                         end else begin
                         end
@@ -4830,28 +5153,83 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine2_state)
+    litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+    case (litedramcore_bankmachine2_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            if (litedramcore_bankmachine2_twtpcon_ready) begin
+                litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+            end
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    litedramcore_bankmachine2_row_open <= 1'd0;
+    case (litedramcore_bankmachine2_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (litedramcore_bankmachine2_trccon_ready) begin
+                litedramcore_bankmachine2_row_open <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    litedramcore_bankmachine2_cmd_valid <= 1'd0;
+    case (litedramcore_bankmachine2_state)
         1'd1: begin
             if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+                litedramcore_bankmachine2_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
             if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+                litedramcore_bankmachine2_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
         3'd6: begin
         end
         default: begin
+            if (litedramcore_bankmachine2_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine2_source_source_valid) begin
+                    if (litedramcore_bankmachine2_row_opened) begin
+                        if (litedramcore_bankmachine2_row_hit) begin
+                            litedramcore_bankmachine2_cmd_valid <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
@@ -4934,54 +5312,54 @@ assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_
 assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we;
 assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr;
 always @(*) begin
-    litedramcore_litedramcore_bankmachine3_next_state <= 3'd0;
-    litedramcore_litedramcore_bankmachine3_next_state <= litedramcore_litedramcore_bankmachine3_state;
-    case (litedramcore_litedramcore_bankmachine3_state)
+    litedramcore_bankmachine3_next_state <= 3'd0;
+    litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
+    case (litedramcore_bankmachine3_state)
         1'd1: begin
             if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
                 if (litedramcore_bankmachine3_cmd_ready) begin
-                    litedramcore_litedramcore_bankmachine3_next_state <= 3'd5;
+                    litedramcore_bankmachine3_next_state <= 3'd5;
                 end
             end
         end
         2'd2: begin
             if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_litedramcore_bankmachine3_next_state <= 3'd5;
+                litedramcore_bankmachine3_next_state <= 3'd5;
             end
         end
         2'd3: begin
             if (litedramcore_bankmachine3_trccon_ready) begin
                 if (litedramcore_bankmachine3_cmd_ready) begin
-                    litedramcore_litedramcore_bankmachine3_next_state <= 3'd6;
+                    litedramcore_bankmachine3_next_state <= 3'd6;
                 end
             end
         end
         3'd4: begin
             if ((~litedramcore_bankmachine3_refresh_req)) begin
-                litedramcore_litedramcore_bankmachine3_next_state <= 1'd0;
+                litedramcore_bankmachine3_next_state <= 1'd0;
             end
         end
         3'd5: begin
-            litedramcore_litedramcore_bankmachine3_next_state <= 2'd3;
+            litedramcore_bankmachine3_next_state <= 2'd3;
         end
         3'd6: begin
-            litedramcore_litedramcore_bankmachine3_next_state <= 1'd0;
+            litedramcore_bankmachine3_next_state <= 1'd0;
         end
         default: begin
             if (litedramcore_bankmachine3_refresh_req) begin
-                litedramcore_litedramcore_bankmachine3_next_state <= 3'd4;
+                litedramcore_bankmachine3_next_state <= 3'd4;
             end else begin
                 if (litedramcore_bankmachine3_source_source_valid) begin
                     if (litedramcore_bankmachine3_row_opened) begin
                         if (litedramcore_bankmachine3_row_hit) begin
                             if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
-                                litedramcore_litedramcore_bankmachine3_next_state <= 2'd2;
+                                litedramcore_bankmachine3_next_state <= 2'd2;
                             end
                         end else begin
-                            litedramcore_litedramcore_bankmachine3_next_state <= 1'd1;
+                            litedramcore_bankmachine3_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_litedramcore_bankmachine3_next_state <= 2'd3;
+                        litedramcore_bankmachine3_next_state <= 2'd3;
                     end
                 end
             end
@@ -4989,8 +5367,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_refresh_gnt <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine3_state)
+    litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+    case (litedramcore_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -4998,28 +5376,40 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine3_twtpcon_ready) begin
-                litedramcore_bankmachine3_refresh_gnt <= 1'd1;
-            end
         end
         3'd5: begin
         end
         3'd6: begin
         end
         default: begin
+            if (litedramcore_bankmachine3_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine3_source_source_valid) begin
+                    if (litedramcore_bankmachine3_row_opened) begin
+                        if (litedramcore_bankmachine3_row_hit) begin
+                            litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_row_open <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine3_state)
+    litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+    case (litedramcore_bankmachine3_state)
         1'd1: begin
+            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+                litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
             if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_row_open <= 1'd1;
+                litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -5033,19 +5423,16 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_valid <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine3_state)
+    litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+    case (litedramcore_bankmachine3_state)
         1'd1: begin
             if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_cmd_valid <= 1'd1;
+                litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_cmd_valid <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -5059,7 +5446,10 @@ always @(*) begin
                 if (litedramcore_bankmachine3_source_source_valid) begin
                     if (litedramcore_bankmachine3_row_opened) begin
                         if (litedramcore_bankmachine3_row_hit) begin
-                            litedramcore_bankmachine3_cmd_valid <= 1'd1;
+                            if (litedramcore_bankmachine3_source_source_payload_we) begin
+                                litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+                            end else begin
+                            end
                         end else begin
                         end
                     end else begin
@@ -5070,18 +5460,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_row_close <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine3_state)
+    litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+    case (litedramcore_bankmachine3_state)
         1'd1: begin
-            litedramcore_bankmachine3_row_close <= 1'd1;
+            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+                litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         2'd2: begin
-            litedramcore_bankmachine3_row_close <= 1'd1;
         end
         2'd3: begin
+            if (litedramcore_bankmachine3_trccon_ready) begin
+                litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         3'd4: begin
-            litedramcore_bankmachine3_row_close <= 1'd1;
+            litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -5092,16 +5486,13 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine3_state)
+    litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+    case (litedramcore_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -5110,12 +5501,27 @@ always @(*) begin
         3'd6: begin
         end
         default: begin
+            if (litedramcore_bankmachine3_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine3_source_source_valid) begin
+                    if (litedramcore_bankmachine3_row_opened) begin
+                        if (litedramcore_bankmachine3_row_hit) begin
+                            if (litedramcore_bankmachine3_source_source_payload_we) begin
+                            end else begin
+                                litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine3_state)
+    litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+    case (litedramcore_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5134,7 +5540,10 @@ always @(*) begin
                 if (litedramcore_bankmachine3_source_source_valid) begin
                     if (litedramcore_bankmachine3_row_opened) begin
                         if (litedramcore_bankmachine3_row_hit) begin
-                            litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+                            if (litedramcore_bankmachine3_source_source_payload_we) begin
+                                litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
+                            end else begin
+                            end
                         end else begin
                         end
                     end else begin
@@ -5145,19 +5554,13 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine3_state)
+    litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+    case (litedramcore_bankmachine3_state)
         1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -5166,16 +5569,28 @@ always @(*) begin
         3'd6: begin
         end
         default: begin
+            if (litedramcore_bankmachine3_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine3_source_source_valid) begin
+                    if (litedramcore_bankmachine3_row_opened) begin
+                        if (litedramcore_bankmachine3_row_hit) begin
+                            if (litedramcore_bankmachine3_source_source_payload_we) begin
+                                litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine3_state)
+    litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+    case (litedramcore_bankmachine3_state)
         1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
-            end
         end
         2'd2: begin
         end
@@ -5194,8 +5609,8 @@ always @(*) begin
                     if (litedramcore_bankmachine3_row_opened) begin
                         if (litedramcore_bankmachine3_row_hit) begin
                             if (litedramcore_bankmachine3_source_source_payload_we) begin
-                                litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
                             end else begin
+                                litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
                             end
                         end else begin
                         end
@@ -5207,22 +5622,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine3_state)
+    litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+    case (litedramcore_bankmachine3_state)
         1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         3'd4: begin
-            litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+            if (litedramcore_bankmachine3_twtpcon_ready) begin
+                litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -5233,13 +5644,16 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine3_state)
+    litedramcore_bankmachine3_row_open <= 1'd0;
+    case (litedramcore_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (litedramcore_bankmachine3_trccon_ready) begin
+                litedramcore_bankmachine3_row_open <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -5248,32 +5662,23 @@ always @(*) begin
         3'd6: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine3_state)
+    litedramcore_bankmachine3_cmd_valid <= 1'd0;
+    case (litedramcore_bankmachine3_state)
         1'd1: begin
+            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+                litedramcore_bankmachine3_cmd_valid <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (litedramcore_bankmachine3_trccon_ready) begin
+                litedramcore_bankmachine3_cmd_valid <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -5287,10 +5692,7 @@ always @(*) begin
                 if (litedramcore_bankmachine3_source_source_valid) begin
                     if (litedramcore_bankmachine3_row_opened) begin
                         if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
-                                litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
-                            end else begin
-                            end
+                            litedramcore_bankmachine3_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -5301,47 +5703,38 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine3_state)
+    litedramcore_bankmachine3_row_close <= 1'd0;
+    case (litedramcore_bankmachine3_state)
         1'd1: begin
+            litedramcore_bankmachine3_row_close <= 1'd1;
         end
         2'd2: begin
+            litedramcore_bankmachine3_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
+            litedramcore_bankmachine3_row_close <= 1'd1;
         end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
-                                litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine3_state)
+    litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+    case (litedramcore_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (litedramcore_bankmachine3_trccon_ready) begin
+                litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -5350,21 +5743,6 @@ always @(*) begin
         3'd6: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
@@ -5447,54 +5825,54 @@ assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_
 assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we;
 assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr;
 always @(*) begin
-    litedramcore_litedramcore_bankmachine4_next_state <= 3'd0;
-    litedramcore_litedramcore_bankmachine4_next_state <= litedramcore_litedramcore_bankmachine4_state;
-    case (litedramcore_litedramcore_bankmachine4_state)
+    litedramcore_bankmachine4_next_state <= 3'd0;
+    litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
+    case (litedramcore_bankmachine4_state)
         1'd1: begin
             if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
                 if (litedramcore_bankmachine4_cmd_ready) begin
-                    litedramcore_litedramcore_bankmachine4_next_state <= 3'd5;
+                    litedramcore_bankmachine4_next_state <= 3'd5;
                 end
             end
         end
         2'd2: begin
             if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_litedramcore_bankmachine4_next_state <= 3'd5;
+                litedramcore_bankmachine4_next_state <= 3'd5;
             end
         end
         2'd3: begin
             if (litedramcore_bankmachine4_trccon_ready) begin
                 if (litedramcore_bankmachine4_cmd_ready) begin
-                    litedramcore_litedramcore_bankmachine4_next_state <= 3'd6;
+                    litedramcore_bankmachine4_next_state <= 3'd6;
                 end
             end
         end
         3'd4: begin
             if ((~litedramcore_bankmachine4_refresh_req)) begin
-                litedramcore_litedramcore_bankmachine4_next_state <= 1'd0;
+                litedramcore_bankmachine4_next_state <= 1'd0;
             end
         end
         3'd5: begin
-            litedramcore_litedramcore_bankmachine4_next_state <= 2'd3;
+            litedramcore_bankmachine4_next_state <= 2'd3;
         end
         3'd6: begin
-            litedramcore_litedramcore_bankmachine4_next_state <= 1'd0;
+            litedramcore_bankmachine4_next_state <= 1'd0;
         end
         default: begin
             if (litedramcore_bankmachine4_refresh_req) begin
-                litedramcore_litedramcore_bankmachine4_next_state <= 3'd4;
+                litedramcore_bankmachine4_next_state <= 3'd4;
             end else begin
                 if (litedramcore_bankmachine4_source_source_valid) begin
                     if (litedramcore_bankmachine4_row_opened) begin
                         if (litedramcore_bankmachine4_row_hit) begin
                             if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
-                                litedramcore_litedramcore_bankmachine4_next_state <= 2'd2;
+                                litedramcore_bankmachine4_next_state <= 2'd2;
                             end
                         end else begin
-                            litedramcore_litedramcore_bankmachine4_next_state <= 1'd1;
+                            litedramcore_bankmachine4_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_litedramcore_bankmachine4_next_state <= 2'd3;
+                        litedramcore_bankmachine4_next_state <= 2'd3;
                     end
                 end
             end
@@ -5502,18 +5880,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine4_state)
+    litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+    case (litedramcore_bankmachine4_state)
         1'd1: begin
+            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
             if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+                litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
+            litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -5524,8 +5906,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine4_state)
+    litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+    case (litedramcore_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5544,7 +5926,10 @@ always @(*) begin
                 if (litedramcore_bankmachine4_source_source_valid) begin
                     if (litedramcore_bankmachine4_row_opened) begin
                         if (litedramcore_bankmachine4_row_hit) begin
-                            litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
+                            if (litedramcore_bankmachine4_source_source_payload_we) begin
+                            end else begin
+                                litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+                            end
                         end else begin
                         end
                     end else begin
@@ -5555,37 +5940,9 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine4_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine4_state)
+    litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+    case (litedramcore_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
-            end
         end
         2'd2: begin
         end
@@ -5604,7 +5961,7 @@ always @(*) begin
                     if (litedramcore_bankmachine4_row_opened) begin
                         if (litedramcore_bankmachine4_row_hit) begin
                             if (litedramcore_bankmachine4_source_source_payload_we) begin
-                                litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+                                litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -5617,34 +5974,42 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine4_state)
+    litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+    case (litedramcore_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         3'd4: begin
-            litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
         3'd6: begin
         end
         default: begin
+            if (litedramcore_bankmachine4_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine4_source_source_valid) begin
+                    if (litedramcore_bankmachine4_row_opened) begin
+                        if (litedramcore_bankmachine4_row_hit) begin
+                            if (litedramcore_bankmachine4_source_source_payload_we) begin
+                                litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine4_state)
+    litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+    case (litedramcore_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5665,7 +6030,7 @@ always @(*) begin
                         if (litedramcore_bankmachine4_row_hit) begin
                             if (litedramcore_bankmachine4_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+                                litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
                             end
                         end else begin
                         end
@@ -5677,8 +6042,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine4_state)
+    litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+    case (litedramcore_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5686,38 +6051,29 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
+            if (litedramcore_bankmachine4_twtpcon_ready) begin
+                litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
         3'd6: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
-                                litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine4_state)
+    litedramcore_bankmachine4_row_open <= 1'd0;
+    case (litedramcore_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (litedramcore_bankmachine4_trccon_ready) begin
+                litedramcore_bankmachine4_row_open <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -5726,32 +6082,23 @@ always @(*) begin
         3'd6: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
-                                litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine4_state)
+    litedramcore_bankmachine4_cmd_valid <= 1'd0;
+    case (litedramcore_bankmachine4_state)
         1'd1: begin
+            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                litedramcore_bankmachine4_cmd_valid <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (litedramcore_bankmachine4_trccon_ready) begin
+                litedramcore_bankmachine4_cmd_valid <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -5765,10 +6112,7 @@ always @(*) begin
                 if (litedramcore_bankmachine4_source_source_valid) begin
                     if (litedramcore_bankmachine4_row_opened) begin
                         if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
-                            end
+                            litedramcore_bankmachine4_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -5779,18 +6123,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_refresh_gnt <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine4_state)
+    litedramcore_bankmachine4_row_close <= 1'd0;
+    case (litedramcore_bankmachine4_state)
         1'd1: begin
+            litedramcore_bankmachine4_row_close <= 1'd1;
         end
         2'd2: begin
+            litedramcore_bankmachine4_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine4_twtpcon_ready) begin
-                litedramcore_bankmachine4_refresh_gnt <= 1'd1;
-            end
+            litedramcore_bankmachine4_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -5801,15 +6145,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_row_open <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine4_state)
+    litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+    case (litedramcore_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
             if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_row_open <= 1'd1;
+                litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -5823,19 +6167,13 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_valid <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine4_state)
+    litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+    case (litedramcore_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_valid <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_cmd_valid <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -5849,7 +6187,7 @@ always @(*) begin
                 if (litedramcore_bankmachine4_source_source_valid) begin
                     if (litedramcore_bankmachine4_row_opened) begin
                         if (litedramcore_bankmachine4_row_hit) begin
-                            litedramcore_bankmachine4_cmd_valid <= 1'd1;
+                            litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -5860,18 +6198,21 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_row_close <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine4_state)
+    litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+    case (litedramcore_bankmachine4_state)
         1'd1: begin
-            litedramcore_bankmachine4_row_close <= 1'd1;
+            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+            end
         end
         2'd2: begin
-            litedramcore_bankmachine4_row_close <= 1'd1;
         end
         2'd3: begin
+            if (litedramcore_bankmachine4_trccon_ready) begin
+                litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+            end
         end
         3'd4: begin
-            litedramcore_bankmachine4_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -5881,6 +6222,43 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+    case (litedramcore_bankmachine4_state)
+        1'd1: begin
+            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+            if (litedramcore_bankmachine4_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine4_source_source_valid) begin
+                    if (litedramcore_bankmachine4_row_opened) begin
+                        if (litedramcore_bankmachine4_row_hit) begin
+                            if (litedramcore_bankmachine4_source_source_payload_we) begin
+                                litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid;
 assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready;
 assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we;
@@ -5960,54 +6338,54 @@ assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_
 assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we;
 assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr;
 always @(*) begin
-    litedramcore_litedramcore_bankmachine5_next_state <= 3'd0;
-    litedramcore_litedramcore_bankmachine5_next_state <= litedramcore_litedramcore_bankmachine5_state;
-    case (litedramcore_litedramcore_bankmachine5_state)
+    litedramcore_bankmachine5_next_state <= 3'd0;
+    litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
+    case (litedramcore_bankmachine5_state)
         1'd1: begin
             if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
                 if (litedramcore_bankmachine5_cmd_ready) begin
-                    litedramcore_litedramcore_bankmachine5_next_state <= 3'd5;
+                    litedramcore_bankmachine5_next_state <= 3'd5;
                 end
             end
         end
         2'd2: begin
             if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_litedramcore_bankmachine5_next_state <= 3'd5;
+                litedramcore_bankmachine5_next_state <= 3'd5;
             end
         end
         2'd3: begin
             if (litedramcore_bankmachine5_trccon_ready) begin
                 if (litedramcore_bankmachine5_cmd_ready) begin
-                    litedramcore_litedramcore_bankmachine5_next_state <= 3'd6;
+                    litedramcore_bankmachine5_next_state <= 3'd6;
                 end
             end
         end
         3'd4: begin
             if ((~litedramcore_bankmachine5_refresh_req)) begin
-                litedramcore_litedramcore_bankmachine5_next_state <= 1'd0;
+                litedramcore_bankmachine5_next_state <= 1'd0;
             end
         end
         3'd5: begin
-            litedramcore_litedramcore_bankmachine5_next_state <= 2'd3;
+            litedramcore_bankmachine5_next_state <= 2'd3;
         end
         3'd6: begin
-            litedramcore_litedramcore_bankmachine5_next_state <= 1'd0;
+            litedramcore_bankmachine5_next_state <= 1'd0;
         end
         default: begin
             if (litedramcore_bankmachine5_refresh_req) begin
-                litedramcore_litedramcore_bankmachine5_next_state <= 3'd4;
+                litedramcore_bankmachine5_next_state <= 3'd4;
             end else begin
                 if (litedramcore_bankmachine5_source_source_valid) begin
                     if (litedramcore_bankmachine5_row_opened) begin
                         if (litedramcore_bankmachine5_row_hit) begin
                             if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
-                                litedramcore_litedramcore_bankmachine5_next_state <= 2'd2;
+                                litedramcore_bankmachine5_next_state <= 2'd2;
                             end
                         end else begin
-                            litedramcore_litedramcore_bankmachine5_next_state <= 1'd1;
+                            litedramcore_bankmachine5_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_litedramcore_bankmachine5_next_state <= 2'd3;
+                        litedramcore_bankmachine5_next_state <= 2'd3;
                     end
                 end
             end
@@ -6015,8 +6393,42 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine5_state)
+    litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+    case (litedramcore_bankmachine5_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+            if (litedramcore_bankmachine5_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine5_source_source_valid) begin
+                    if (litedramcore_bankmachine5_row_opened) begin
+                        if (litedramcore_bankmachine5_row_hit) begin
+                            if (litedramcore_bankmachine5_source_source_payload_we) begin
+                            end else begin
+                                litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+    case (litedramcore_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6024,40 +6436,28 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
+            if (litedramcore_bankmachine5_twtpcon_ready) begin
+                litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
         3'd6: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine5_state)
+    litedramcore_bankmachine5_row_open <= 1'd0;
+    case (litedramcore_bankmachine5_state)
         1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
             if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+                litedramcore_bankmachine5_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -6071,16 +6471,19 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine5_state)
+    litedramcore_bankmachine5_cmd_valid <= 1'd0;
+    case (litedramcore_bankmachine5_state)
         1'd1: begin
             if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+                litedramcore_bankmachine5_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (litedramcore_bankmachine5_trccon_ready) begin
+                litedramcore_bankmachine5_cmd_valid <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -6094,10 +6497,7 @@ always @(*) begin
                 if (litedramcore_bankmachine5_source_source_valid) begin
                     if (litedramcore_bankmachine5_row_opened) begin
                         if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
-                                litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
-                            end else begin
-                            end
+                            litedramcore_bankmachine5_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -6108,22 +6508,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine5_state)
+    litedramcore_bankmachine5_row_close <= 1'd0;
+    case (litedramcore_bankmachine5_state)
         1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
-            end
+            litedramcore_bankmachine5_row_close <= 1'd1;
         end
         2'd2: begin
+            litedramcore_bankmachine5_row_close <= 1'd1;
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         3'd4: begin
-            litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+            litedramcore_bankmachine5_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -6134,13 +6530,16 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine5_state)
+    litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+    case (litedramcore_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (litedramcore_bankmachine5_trccon_ready) begin
+                litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -6149,27 +6548,12 @@ always @(*) begin
         3'd6: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine5_state)
+    litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+    case (litedramcore_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6188,10 +6572,7 @@ always @(*) begin
                 if (litedramcore_bankmachine5_source_source_valid) begin
                     if (litedramcore_bankmachine5_row_opened) begin
                         if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
-                                litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
-                            end else begin
-                            end
+                            litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -6202,13 +6583,19 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine5_state)
+    litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+    case (litedramcore_bankmachine5_state)
         1'd1: begin
+            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+                litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (litedramcore_bankmachine5_trccon_ready) begin
+                litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -6217,28 +6604,16 @@ always @(*) begin
         3'd6: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
-                                litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine5_state)
+    litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+    case (litedramcore_bankmachine5_state)
         1'd1: begin
+            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+                litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+            end
         end
         2'd2: begin
         end
@@ -6257,8 +6632,8 @@ always @(*) begin
                     if (litedramcore_bankmachine5_row_opened) begin
                         if (litedramcore_bankmachine5_row_hit) begin
                             if (litedramcore_bankmachine5_source_source_payload_we) begin
+                                litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
                             end else begin
-                                litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
                             end
                         end else begin
                         end
@@ -6270,40 +6645,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_refresh_gnt <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine5_state)
+    litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+    case (litedramcore_bankmachine5_state)
         1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            if (litedramcore_bankmachine5_twtpcon_ready) begin
-                litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+                litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
             end
         end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine5_row_open <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine5_state)
-        1'd1: begin
-        end
         2'd2: begin
         end
         2'd3: begin
             if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_row_open <= 1'd1;
+                litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
+            litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -6314,19 +6671,13 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_valid <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine5_state)
+    litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+    case (litedramcore_bankmachine5_state)
         1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_cmd_valid <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_cmd_valid <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -6340,7 +6691,10 @@ always @(*) begin
                 if (litedramcore_bankmachine5_source_source_valid) begin
                     if (litedramcore_bankmachine5_row_opened) begin
                         if (litedramcore_bankmachine5_row_hit) begin
-                            litedramcore_bankmachine5_cmd_valid <= 1'd1;
+                            if (litedramcore_bankmachine5_source_source_payload_we) begin
+                            end else begin
+                                litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
+                            end
                         end else begin
                         end
                     end else begin
@@ -6351,38 +6705,47 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_row_close <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine5_state)
+    litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+    case (litedramcore_bankmachine5_state)
         1'd1: begin
-            litedramcore_bankmachine5_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine5_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine5_row_close <= 1'd1;
         end
         3'd5: begin
         end
         3'd6: begin
         end
         default: begin
+            if (litedramcore_bankmachine5_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine5_source_source_valid) begin
+                    if (litedramcore_bankmachine5_row_opened) begin
+                        if (litedramcore_bankmachine5_row_hit) begin
+                            if (litedramcore_bankmachine5_source_source_payload_we) begin
+                                litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine5_state)
+    litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+    case (litedramcore_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -6391,6 +6754,21 @@ always @(*) begin
         3'd6: begin
         end
         default: begin
+            if (litedramcore_bankmachine5_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine5_source_source_valid) begin
+                    if (litedramcore_bankmachine5_row_opened) begin
+                        if (litedramcore_bankmachine5_row_hit) begin
+                            if (litedramcore_bankmachine5_source_source_payload_we) begin
+                                litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
@@ -6473,54 +6851,54 @@ assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_
 assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we;
 assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr;
 always @(*) begin
-    litedramcore_litedramcore_bankmachine6_next_state <= 3'd0;
-    litedramcore_litedramcore_bankmachine6_next_state <= litedramcore_litedramcore_bankmachine6_state;
-    case (litedramcore_litedramcore_bankmachine6_state)
+    litedramcore_bankmachine6_next_state <= 3'd0;
+    litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
+    case (litedramcore_bankmachine6_state)
         1'd1: begin
             if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
                 if (litedramcore_bankmachine6_cmd_ready) begin
-                    litedramcore_litedramcore_bankmachine6_next_state <= 3'd5;
+                    litedramcore_bankmachine6_next_state <= 3'd5;
                 end
             end
         end
         2'd2: begin
             if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_litedramcore_bankmachine6_next_state <= 3'd5;
+                litedramcore_bankmachine6_next_state <= 3'd5;
             end
         end
         2'd3: begin
             if (litedramcore_bankmachine6_trccon_ready) begin
                 if (litedramcore_bankmachine6_cmd_ready) begin
-                    litedramcore_litedramcore_bankmachine6_next_state <= 3'd6;
+                    litedramcore_bankmachine6_next_state <= 3'd6;
                 end
             end
         end
         3'd4: begin
             if ((~litedramcore_bankmachine6_refresh_req)) begin
-                litedramcore_litedramcore_bankmachine6_next_state <= 1'd0;
+                litedramcore_bankmachine6_next_state <= 1'd0;
             end
         end
         3'd5: begin
-            litedramcore_litedramcore_bankmachine6_next_state <= 2'd3;
+            litedramcore_bankmachine6_next_state <= 2'd3;
         end
         3'd6: begin
-            litedramcore_litedramcore_bankmachine6_next_state <= 1'd0;
+            litedramcore_bankmachine6_next_state <= 1'd0;
         end
         default: begin
             if (litedramcore_bankmachine6_refresh_req) begin
-                litedramcore_litedramcore_bankmachine6_next_state <= 3'd4;
+                litedramcore_bankmachine6_next_state <= 3'd4;
             end else begin
                 if (litedramcore_bankmachine6_source_source_valid) begin
                     if (litedramcore_bankmachine6_row_opened) begin
                         if (litedramcore_bankmachine6_row_hit) begin
                             if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
-                                litedramcore_litedramcore_bankmachine6_next_state <= 2'd2;
+                                litedramcore_bankmachine6_next_state <= 2'd2;
                             end
                         end else begin
-                            litedramcore_litedramcore_bankmachine6_next_state <= 1'd1;
+                            litedramcore_bankmachine6_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_litedramcore_bankmachine6_next_state <= 2'd3;
+                        litedramcore_bankmachine6_next_state <= 2'd3;
                     end
                 end
             end
@@ -6528,82 +6906,39 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine6_state)
+    litedramcore_bankmachine6_row_close <= 1'd0;
+    case (litedramcore_bankmachine6_state)
         1'd1: begin
+            litedramcore_bankmachine6_row_close <= 1'd1;
         end
         2'd2: begin
+            litedramcore_bankmachine6_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
+            litedramcore_bankmachine6_row_close <= 1'd1;
         end
         3'd5: begin
         end
         3'd6: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine6_state)
+    litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+    case (litedramcore_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
-                                litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
+            if (litedramcore_bankmachine6_trccon_ready) begin
+                litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
             end
         end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine6_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
         3'd4: begin
         end
         3'd5: begin
@@ -6611,27 +6946,12 @@ always @(*) begin
         3'd6: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
-                                litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine6_state)
+    litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+    case (litedramcore_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6650,10 +6970,7 @@ always @(*) begin
                 if (litedramcore_bankmachine6_source_source_valid) begin
                     if (litedramcore_bankmachine6_row_opened) begin
                         if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
-                            end
+                            litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -6664,15 +6981,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_row_open <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine6_state)
+    litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+    case (litedramcore_bankmachine6_state)
         1'd1: begin
+            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+                litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
             if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_row_open <= 1'd1;
+                litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -6686,19 +7006,16 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_valid <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine6_state)
+    litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+    case (litedramcore_bankmachine6_state)
         1'd1: begin
             if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_cmd_valid <= 1'd1;
+                litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_cmd_valid <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -6712,7 +7029,10 @@ always @(*) begin
                 if (litedramcore_bankmachine6_source_source_valid) begin
                     if (litedramcore_bankmachine6_row_opened) begin
                         if (litedramcore_bankmachine6_row_hit) begin
-                            litedramcore_bankmachine6_cmd_valid <= 1'd1;
+                            if (litedramcore_bankmachine6_source_source_payload_we) begin
+                                litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+                            end else begin
+                            end
                         end else begin
                         end
                     end else begin
@@ -6723,18 +7043,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_row_close <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine6_state)
+    litedramcore_bankmachine6_row_open <= 1'd0;
+    case (litedramcore_bankmachine6_state)
         1'd1: begin
-            litedramcore_bankmachine6_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine6_row_close <= 1'd1;
         end
         2'd3: begin
+            if (litedramcore_bankmachine6_trccon_ready) begin
+                litedramcore_bankmachine6_row_open <= 1'd1;
+            end
         end
         3'd4: begin
-            litedramcore_bankmachine6_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -6745,18 +7065,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_refresh_gnt <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine6_state)
+    litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+    case (litedramcore_bankmachine6_state)
         1'd1: begin
+            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+                litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (litedramcore_bankmachine6_trccon_ready) begin
+                litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         3'd4: begin
-            if (litedramcore_bankmachine6_twtpcon_ready) begin
-                litedramcore_bankmachine6_refresh_gnt <= 1'd1;
-            end
+            litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -6767,16 +7091,13 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine6_state)
+    litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+    case (litedramcore_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -6785,12 +7106,27 @@ always @(*) begin
         3'd6: begin
         end
         default: begin
+            if (litedramcore_bankmachine6_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine6_source_source_valid) begin
+                    if (litedramcore_bankmachine6_row_opened) begin
+                        if (litedramcore_bankmachine6_row_hit) begin
+                            if (litedramcore_bankmachine6_source_source_payload_we) begin
+                            end else begin
+                                litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine6_state)
+    litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+    case (litedramcore_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6809,7 +7145,10 @@ always @(*) begin
                 if (litedramcore_bankmachine6_source_source_valid) begin
                     if (litedramcore_bankmachine6_row_opened) begin
                         if (litedramcore_bankmachine6_row_hit) begin
-                            litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+                            if (litedramcore_bankmachine6_source_source_payload_we) begin
+                                litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
+                            end else begin
+                            end
                         end else begin
                         end
                     end else begin
@@ -6820,19 +7159,13 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine6_state)
+    litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+    case (litedramcore_bankmachine6_state)
         1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -6841,16 +7174,28 @@ always @(*) begin
         3'd6: begin
         end
         default: begin
+            if (litedramcore_bankmachine6_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine6_source_source_valid) begin
+                    if (litedramcore_bankmachine6_row_opened) begin
+                        if (litedramcore_bankmachine6_row_hit) begin
+                            if (litedramcore_bankmachine6_source_source_payload_we) begin
+                                litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine6_state)
+    litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+    case (litedramcore_bankmachine6_state)
         1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
-            end
         end
         2'd2: begin
         end
@@ -6869,8 +7214,8 @@ always @(*) begin
                     if (litedramcore_bankmachine6_row_opened) begin
                         if (litedramcore_bankmachine6_row_hit) begin
                             if (litedramcore_bankmachine6_source_source_payload_we) begin
-                                litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
                             end else begin
+                                litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
                             end
                         end else begin
                         end
@@ -6882,28 +7227,61 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine6_state)
+    litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+    case (litedramcore_bankmachine6_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            if (litedramcore_bankmachine6_twtpcon_ready) begin
+                litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+            end
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    litedramcore_bankmachine6_cmd_valid <= 1'd0;
+    case (litedramcore_bankmachine6_state)
         1'd1: begin
             if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+                litedramcore_bankmachine6_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
             if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+                litedramcore_bankmachine6_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
         3'd6: begin
         end
         default: begin
+            if (litedramcore_bankmachine6_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine6_source_source_valid) begin
+                    if (litedramcore_bankmachine6_row_opened) begin
+                        if (litedramcore_bankmachine6_row_hit) begin
+                            litedramcore_bankmachine6_cmd_valid <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
@@ -6986,54 +7364,54 @@ assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_
 assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we;
 assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr;
 always @(*) begin
-    litedramcore_litedramcore_bankmachine7_next_state <= 3'd0;
-    litedramcore_litedramcore_bankmachine7_next_state <= litedramcore_litedramcore_bankmachine7_state;
-    case (litedramcore_litedramcore_bankmachine7_state)
+    litedramcore_bankmachine7_next_state <= 3'd0;
+    litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
+    case (litedramcore_bankmachine7_state)
         1'd1: begin
             if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
                 if (litedramcore_bankmachine7_cmd_ready) begin
-                    litedramcore_litedramcore_bankmachine7_next_state <= 3'd5;
+                    litedramcore_bankmachine7_next_state <= 3'd5;
                 end
             end
         end
         2'd2: begin
             if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_litedramcore_bankmachine7_next_state <= 3'd5;
+                litedramcore_bankmachine7_next_state <= 3'd5;
             end
         end
         2'd3: begin
             if (litedramcore_bankmachine7_trccon_ready) begin
                 if (litedramcore_bankmachine7_cmd_ready) begin
-                    litedramcore_litedramcore_bankmachine7_next_state <= 3'd6;
+                    litedramcore_bankmachine7_next_state <= 3'd6;
                 end
             end
         end
         3'd4: begin
             if ((~litedramcore_bankmachine7_refresh_req)) begin
-                litedramcore_litedramcore_bankmachine7_next_state <= 1'd0;
+                litedramcore_bankmachine7_next_state <= 1'd0;
             end
         end
         3'd5: begin
-            litedramcore_litedramcore_bankmachine7_next_state <= 2'd3;
+            litedramcore_bankmachine7_next_state <= 2'd3;
         end
         3'd6: begin
-            litedramcore_litedramcore_bankmachine7_next_state <= 1'd0;
+            litedramcore_bankmachine7_next_state <= 1'd0;
         end
         default: begin
             if (litedramcore_bankmachine7_refresh_req) begin
-                litedramcore_litedramcore_bankmachine7_next_state <= 3'd4;
+                litedramcore_bankmachine7_next_state <= 3'd4;
             end else begin
                 if (litedramcore_bankmachine7_source_source_valid) begin
                     if (litedramcore_bankmachine7_row_opened) begin
                         if (litedramcore_bankmachine7_row_hit) begin
                             if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
-                                litedramcore_litedramcore_bankmachine7_next_state <= 2'd2;
+                                litedramcore_bankmachine7_next_state <= 2'd2;
                             end
                         end else begin
-                            litedramcore_litedramcore_bankmachine7_next_state <= 1'd1;
+                            litedramcore_bankmachine7_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_litedramcore_bankmachine7_next_state <= 2'd3;
+                        litedramcore_bankmachine7_next_state <= 2'd3;
                     end
                 end
             end
@@ -7041,8 +7419,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_refresh_gnt <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine7_state)
+    litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+    case (litedramcore_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7050,28 +7428,40 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine7_twtpcon_ready) begin
-                litedramcore_bankmachine7_refresh_gnt <= 1'd1;
-            end
         end
         3'd5: begin
         end
         3'd6: begin
         end
         default: begin
+            if (litedramcore_bankmachine7_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine7_source_source_valid) begin
+                    if (litedramcore_bankmachine7_row_opened) begin
+                        if (litedramcore_bankmachine7_row_hit) begin
+                            litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_row_open <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine7_state)
+    litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+    case (litedramcore_bankmachine7_state)
         1'd1: begin
+            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+                litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
             if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_row_open <= 1'd1;
+                litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -7085,19 +7475,16 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_valid <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine7_state)
+    litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+    case (litedramcore_bankmachine7_state)
         1'd1: begin
             if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_cmd_valid <= 1'd1;
+                litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_cmd_valid <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -7111,7 +7498,10 @@ always @(*) begin
                 if (litedramcore_bankmachine7_source_source_valid) begin
                     if (litedramcore_bankmachine7_row_opened) begin
                         if (litedramcore_bankmachine7_row_hit) begin
-                            litedramcore_bankmachine7_cmd_valid <= 1'd1;
+                            if (litedramcore_bankmachine7_source_source_payload_we) begin
+                                litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+                            end else begin
+                            end
                         end else begin
                         end
                     end else begin
@@ -7122,18 +7512,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_row_close <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine7_state)
+    litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+    case (litedramcore_bankmachine7_state)
         1'd1: begin
-            litedramcore_bankmachine7_row_close <= 1'd1;
+            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+                litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         2'd2: begin
-            litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd3: begin
+            if (litedramcore_bankmachine7_trccon_ready) begin
+                litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         3'd4: begin
-            litedramcore_bankmachine7_row_close <= 1'd1;
+            litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -7144,16 +7538,13 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine7_state)
+    litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+    case (litedramcore_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -7162,12 +7553,27 @@ always @(*) begin
         3'd6: begin
         end
         default: begin
+            if (litedramcore_bankmachine7_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine7_source_source_valid) begin
+                    if (litedramcore_bankmachine7_row_opened) begin
+                        if (litedramcore_bankmachine7_row_hit) begin
+                            if (litedramcore_bankmachine7_source_source_payload_we) begin
+                            end else begin
+                                litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine7_state)
+    litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+    case (litedramcore_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7186,7 +7592,10 @@ always @(*) begin
                 if (litedramcore_bankmachine7_source_source_valid) begin
                     if (litedramcore_bankmachine7_row_opened) begin
                         if (litedramcore_bankmachine7_row_hit) begin
-                            litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+                            if (litedramcore_bankmachine7_source_source_payload_we) begin
+                                litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+                            end else begin
+                            end
                         end else begin
                         end
                     end else begin
@@ -7197,19 +7606,13 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine7_state)
+    litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+    case (litedramcore_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -7218,16 +7621,28 @@ always @(*) begin
         3'd6: begin
         end
         default: begin
+            if (litedramcore_bankmachine7_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine7_source_source_valid) begin
+                    if (litedramcore_bankmachine7_row_opened) begin
+                        if (litedramcore_bankmachine7_row_hit) begin
+                            if (litedramcore_bankmachine7_source_source_payload_we) begin
+                                litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine7_state)
+    litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+    case (litedramcore_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
-            end
         end
         2'd2: begin
         end
@@ -7246,8 +7661,8 @@ always @(*) begin
                     if (litedramcore_bankmachine7_row_opened) begin
                         if (litedramcore_bankmachine7_row_hit) begin
                             if (litedramcore_bankmachine7_source_source_payload_we) begin
-                                litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
                             end else begin
+                                litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
                             end
                         end else begin
                         end
@@ -7259,22 +7674,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine7_state)
+    litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+    case (litedramcore_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         2'd2: begin
         end
-        2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
-            end
-        end
+        2'd3: begin
+        end
         3'd4: begin
-            litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+            if (litedramcore_bankmachine7_twtpcon_ready) begin
+                litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -7285,13 +7696,16 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine7_state)
+    litedramcore_bankmachine7_row_open <= 1'd0;
+    case (litedramcore_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (litedramcore_bankmachine7_trccon_ready) begin
+                litedramcore_bankmachine7_row_open <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -7300,32 +7714,23 @@ always @(*) begin
         3'd6: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine7_state)
+    litedramcore_bankmachine7_cmd_valid <= 1'd0;
+    case (litedramcore_bankmachine7_state)
         1'd1: begin
+            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+                litedramcore_bankmachine7_cmd_valid <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (litedramcore_bankmachine7_trccon_ready) begin
+                litedramcore_bankmachine7_cmd_valid <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -7339,10 +7744,7 @@ always @(*) begin
                 if (litedramcore_bankmachine7_source_source_valid) begin
                     if (litedramcore_bankmachine7_row_opened) begin
                         if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
-                                litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
-                            end else begin
-                            end
+                            litedramcore_bankmachine7_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -7353,47 +7755,38 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine7_state)
+    litedramcore_bankmachine7_row_close <= 1'd0;
+    case (litedramcore_bankmachine7_state)
         1'd1: begin
+            litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd2: begin
+            litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
+            litedramcore_bankmachine7_row_close <= 1'd1;
         end
         3'd5: begin
         end
         3'd6: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
-                                litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
-    case (litedramcore_litedramcore_bankmachine7_state)
+    litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+    case (litedramcore_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (litedramcore_bankmachine7_trccon_ready) begin
+                litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -7402,21 +7795,6 @@ always @(*) begin
         3'd6: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
@@ -7456,28 +7834,28 @@ always @(*) begin
     litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
 end
 assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
-assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
-assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1;
-assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
-assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
-assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
-assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
+assign litedramcore_choose_cmd_cmd_valid = rhs_self0;
+assign litedramcore_choose_cmd_cmd_payload_a = rhs_self1;
+assign litedramcore_choose_cmd_cmd_payload_ba = rhs_self2;
+assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_self3;
+assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_self4;
+assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_self5;
 always @(*) begin
     litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
     if (litedramcore_choose_cmd_cmd_valid) begin
-        litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
+        litedramcore_choose_cmd_cmd_payload_cas <= t_self0;
     end
 end
 always @(*) begin
     litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
     if (litedramcore_choose_cmd_cmd_valid) begin
-        litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
+        litedramcore_choose_cmd_cmd_payload_ras <= t_self1;
     end
 end
 always @(*) begin
     litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
     if (litedramcore_choose_cmd_cmd_valid) begin
-        litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
+        litedramcore_choose_cmd_cmd_payload_we <= t_self2;
     end
 end
 always @(*) begin
@@ -7565,121 +7943,124 @@ always @(*) begin
     litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
 end
 assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
-assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
-assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7;
-assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8;
-assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9;
-assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
-assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
+assign litedramcore_choose_req_cmd_valid = rhs_self6;
+assign litedramcore_choose_req_cmd_payload_a = rhs_self7;
+assign litedramcore_choose_req_cmd_payload_ba = rhs_self8;
+assign litedramcore_choose_req_cmd_payload_is_read = rhs_self9;
+assign litedramcore_choose_req_cmd_payload_is_write = rhs_self10;
+assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_self11;
 always @(*) begin
     litedramcore_choose_req_cmd_payload_cas <= 1'd0;
     if (litedramcore_choose_req_cmd_valid) begin
-        litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
+        litedramcore_choose_req_cmd_payload_cas <= t_self3;
     end
 end
 always @(*) begin
     litedramcore_choose_req_cmd_payload_ras <= 1'd0;
     if (litedramcore_choose_req_cmd_valid) begin
-        litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
+        litedramcore_choose_req_cmd_payload_ras <= t_self4;
     end
 end
 always @(*) begin
     litedramcore_choose_req_cmd_payload_we <= 1'd0;
     if (litedramcore_choose_req_cmd_valid) begin
-        litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
+        litedramcore_choose_req_cmd_payload_we <= t_self5;
     end
 end
 assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
 assign litedramcore_dfi_p0_reset_n = 1'd1;
-assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}};
-assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}};
+assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer2}};
+assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer3}};
 assign litedramcore_dfi_p1_reset_n = 1'd1;
-assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}};
-assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}};
+assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer4}};
+assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer5}};
 assign litedramcore_tfawcon_count = ((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]);
 always @(*) begin
-    litedramcore_litedramcore_multiplexer_next_state <= 4'd0;
-    litedramcore_litedramcore_multiplexer_next_state <= litedramcore_litedramcore_multiplexer_state;
-    case (litedramcore_litedramcore_multiplexer_state)
+    litedramcore_multiplexer_next_state <= 4'd0;
+    litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
+    case (litedramcore_multiplexer_state)
         1'd1: begin
             if (litedramcore_read_available) begin
                 if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
-                    litedramcore_litedramcore_multiplexer_next_state <= 2'd3;
+                    litedramcore_multiplexer_next_state <= 2'd3;
                 end
             end
             if (litedramcore_go_to_refresh) begin
-                litedramcore_litedramcore_multiplexer_next_state <= 2'd2;
+                litedramcore_multiplexer_next_state <= 2'd2;
             end
         end
         2'd2: begin
             if (litedramcore_cmd_last) begin
-                litedramcore_litedramcore_multiplexer_next_state <= 1'd0;
+                litedramcore_multiplexer_next_state <= 1'd0;
             end
         end
         2'd3: begin
             if (litedramcore_twtrcon_ready) begin
-                litedramcore_litedramcore_multiplexer_next_state <= 1'd0;
+                litedramcore_multiplexer_next_state <= 1'd0;
             end
         end
         3'd4: begin
-            litedramcore_litedramcore_multiplexer_next_state <= 3'd5;
+            litedramcore_multiplexer_next_state <= 3'd5;
         end
         3'd5: begin
-            litedramcore_litedramcore_multiplexer_next_state <= 3'd6;
+            litedramcore_multiplexer_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_litedramcore_multiplexer_next_state <= 3'd7;
+            litedramcore_multiplexer_next_state <= 3'd7;
         end
         3'd7: begin
-            litedramcore_litedramcore_multiplexer_next_state <= 4'd8;
+            litedramcore_multiplexer_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_litedramcore_multiplexer_next_state <= 4'd9;
+            litedramcore_multiplexer_next_state <= 4'd9;
         end
         4'd9: begin
-            litedramcore_litedramcore_multiplexer_next_state <= 4'd10;
+            litedramcore_multiplexer_next_state <= 4'd10;
         end
         4'd10: begin
-            litedramcore_litedramcore_multiplexer_next_state <= 4'd11;
+            litedramcore_multiplexer_next_state <= 4'd11;
         end
         4'd11: begin
-            litedramcore_litedramcore_multiplexer_next_state <= 4'd12;
+            litedramcore_multiplexer_next_state <= 4'd12;
         end
         4'd12: begin
-            litedramcore_litedramcore_multiplexer_next_state <= 4'd13;
+            litedramcore_multiplexer_next_state <= 4'd13;
         end
         4'd13: begin
-            litedramcore_litedramcore_multiplexer_next_state <= 4'd14;
+            litedramcore_multiplexer_next_state <= 4'd14;
         end
         4'd14: begin
-            litedramcore_litedramcore_multiplexer_next_state <= 4'd15;
+            litedramcore_multiplexer_next_state <= 4'd15;
         end
         4'd15: begin
-            litedramcore_litedramcore_multiplexer_next_state <= 1'd1;
+            litedramcore_multiplexer_next_state <= 1'd1;
         end
         default: begin
             if (litedramcore_write_available) begin
                 if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
-                    litedramcore_litedramcore_multiplexer_next_state <= 3'd4;
+                    litedramcore_multiplexer_next_state <= 3'd4;
                 end
             end
             if (litedramcore_go_to_refresh) begin
-                litedramcore_litedramcore_multiplexer_next_state <= 2'd2;
+                litedramcore_multiplexer_next_state <= 2'd2;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_req_cmd_ready <= 1'd0;
-    case (litedramcore_litedramcore_multiplexer_state)
+    litedramcore_steerer0 <= 2'd0;
+    case (litedramcore_multiplexer_state)
         1'd1: begin
+            litedramcore_steerer0 <= 1'd0;
             if (1'd0) begin
-                litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
-            end else begin
-                litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+                litedramcore_steerer0 <= 2'd2;
+            end
+            if (1'd1) begin
+                litedramcore_steerer0 <= 1'd1;
             end
         end
         2'd2: begin
+            litedramcore_steerer0 <= 2'd3;
         end
         2'd3: begin
         end
@@ -7708,19 +8089,27 @@ always @(*) begin
         4'd15: begin
         end
         default: begin
+            litedramcore_steerer0 <= 1'd0;
+            if (1'd1) begin
+                litedramcore_steerer0 <= 2'd2;
+            end
             if (1'd0) begin
-                litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
-            end else begin
-                litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+                litedramcore_steerer0 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_en1 <= 1'd0;
-    case (litedramcore_litedramcore_multiplexer_state)
+    litedramcore_steerer1 <= 2'd0;
+    case (litedramcore_multiplexer_state)
         1'd1: begin
-            litedramcore_en1 <= 1'd1;
+            litedramcore_steerer1 <= 1'd0;
+            if (1'd1) begin
+                litedramcore_steerer1 <= 2'd2;
+            end
+            if (1'd0) begin
+                litedramcore_steerer1 <= 1'd1;
+            end
         end
         2'd2: begin
         end
@@ -7751,23 +8140,26 @@ always @(*) begin
         4'd15: begin
         end
         default: begin
+            litedramcore_steerer1 <= 1'd0;
+            if (1'd0) begin
+                litedramcore_steerer1 <= 2'd2;
+            end
+            if (1'd1) begin
+                litedramcore_steerer1 <= 1'd1;
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_steerer_sel0 <= 2'd0;
-    case (litedramcore_litedramcore_multiplexer_state)
+    litedramcore_choose_cmd_want_activates <= 1'd0;
+    case (litedramcore_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer_sel0 <= 1'd0;
             if (1'd0) begin
-                litedramcore_steerer_sel0 <= 2'd2;
-            end
-            if (1'd1) begin
-                litedramcore_steerer_sel0 <= 1'd1;
+            end else begin
+                litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
             end
         end
         2'd2: begin
-            litedramcore_steerer_sel0 <= 2'd3;
         end
         2'd3: begin
         end
@@ -7796,29 +8188,20 @@ always @(*) begin
         4'd15: begin
         end
         default: begin
-            litedramcore_steerer_sel0 <= 1'd0;
-            if (1'd1) begin
-                litedramcore_steerer_sel0 <= 2'd2;
-            end
             if (1'd0) begin
-                litedramcore_steerer_sel0 <= 1'd1;
+            end else begin
+                litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_steerer_sel1 <= 2'd0;
-    case (litedramcore_litedramcore_multiplexer_state)
+    litedramcore_cmd_ready <= 1'd0;
+    case (litedramcore_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer_sel1 <= 1'd0;
-            if (1'd1) begin
-                litedramcore_steerer_sel1 <= 2'd2;
-            end
-            if (1'd0) begin
-                litedramcore_steerer_sel1 <= 1'd1;
-            end
         end
         2'd2: begin
+            litedramcore_cmd_ready <= 1'd1;
         end
         2'd3: begin
         end
@@ -7847,23 +8230,16 @@ always @(*) begin
         4'd15: begin
         end
         default: begin
-            litedramcore_steerer_sel1 <= 1'd0;
-            if (1'd0) begin
-                litedramcore_steerer_sel1 <= 2'd2;
-            end
-            if (1'd1) begin
-                litedramcore_steerer_sel1 <= 1'd1;
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_cmd_want_activates <= 1'd0;
-    case (litedramcore_litedramcore_multiplexer_state)
+    litedramcore_choose_cmd_cmd_ready <= 1'd0;
+    case (litedramcore_multiplexer_state)
         1'd1: begin
             if (1'd0) begin
             end else begin
-                litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+                litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
             end
         end
         2'd2: begin
@@ -7897,18 +8273,17 @@ always @(*) begin
         default: begin
             if (1'd0) begin
             end else begin
-                litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+                litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_cmd_ready <= 1'd0;
-    case (litedramcore_litedramcore_multiplexer_state)
+    litedramcore_choose_req_want_reads <= 1'd0;
+    case (litedramcore_multiplexer_state)
         1'd1: begin
         end
         2'd2: begin
-            litedramcore_cmd_ready <= 1'd1;
         end
         2'd3: begin
         end
@@ -7937,17 +8312,15 @@ always @(*) begin
         4'd15: begin
         end
         default: begin
+            litedramcore_choose_req_want_reads <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_cmd_cmd_ready <= 1'd0;
-    case (litedramcore_litedramcore_multiplexer_state)
+    litedramcore_choose_req_want_writes <= 1'd0;
+    case (litedramcore_multiplexer_state)
         1'd1: begin
-            if (1'd0) begin
-            end else begin
-                litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
-            end
+            litedramcore_choose_req_want_writes <= 1'd1;
         end
         2'd2: begin
         end
@@ -7978,16 +8351,12 @@ always @(*) begin
         4'd15: begin
         end
         default: begin
-            if (1'd0) begin
-            end else begin
-                litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_req_want_reads <= 1'd0;
-    case (litedramcore_litedramcore_multiplexer_state)
+    litedramcore_en0 <= 1'd0;
+    case (litedramcore_multiplexer_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8019,15 +8388,19 @@ always @(*) begin
         4'd15: begin
         end
         default: begin
-            litedramcore_choose_req_want_reads <= 1'd1;
+            litedramcore_en0 <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_req_want_writes <= 1'd0;
-    case (litedramcore_litedramcore_multiplexer_state)
+    litedramcore_choose_req_cmd_ready <= 1'd0;
+    case (litedramcore_multiplexer_state)
         1'd1: begin
-            litedramcore_choose_req_want_writes <= 1'd1;
+            if (1'd0) begin
+                litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+            end else begin
+                litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+            end
         end
         2'd2: begin
         end
@@ -8058,13 +8431,19 @@ always @(*) begin
         4'd15: begin
         end
         default: begin
+            if (1'd0) begin
+                litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+            end else begin
+                litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_en0 <= 1'd0;
-    case (litedramcore_litedramcore_multiplexer_state)
+    litedramcore_en1 <= 1'd0;
+    case (litedramcore_multiplexer_state)
         1'd1: begin
+            litedramcore_en1 <= 1'd1;
         end
         2'd2: begin
         end
@@ -8095,56 +8474,55 @@ always @(*) begin
         4'd15: begin
         end
         default: begin
-            litedramcore_en0 <= 1'd1;
         end
     endcase
 end
-assign litedramcore_litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
-assign litedramcore_interface_bank0_addr = rhs_array_muxed12;
-assign litedramcore_interface_bank0_we = rhs_array_muxed13;
-assign litedramcore_interface_bank0_valid = rhs_array_muxed14;
-assign litedramcore_litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock));
-assign litedramcore_interface_bank1_addr = rhs_array_muxed15;
-assign litedramcore_interface_bank1_we = rhs_array_muxed16;
-assign litedramcore_interface_bank1_valid = rhs_array_muxed17;
-assign litedramcore_litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock));
-assign litedramcore_interface_bank2_addr = rhs_array_muxed18;
-assign litedramcore_interface_bank2_we = rhs_array_muxed19;
-assign litedramcore_interface_bank2_valid = rhs_array_muxed20;
-assign litedramcore_litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock));
-assign litedramcore_interface_bank3_addr = rhs_array_muxed21;
-assign litedramcore_interface_bank3_we = rhs_array_muxed22;
-assign litedramcore_interface_bank3_valid = rhs_array_muxed23;
-assign litedramcore_litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock));
-assign litedramcore_interface_bank4_addr = rhs_array_muxed24;
-assign litedramcore_interface_bank4_we = rhs_array_muxed25;
-assign litedramcore_interface_bank4_valid = rhs_array_muxed26;
-assign litedramcore_litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock));
-assign litedramcore_interface_bank5_addr = rhs_array_muxed27;
-assign litedramcore_interface_bank5_we = rhs_array_muxed28;
-assign litedramcore_interface_bank5_valid = rhs_array_muxed29;
-assign litedramcore_litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock));
-assign litedramcore_interface_bank6_addr = rhs_array_muxed30;
-assign litedramcore_interface_bank6_we = rhs_array_muxed31;
-assign litedramcore_interface_bank6_valid = rhs_array_muxed32;
-assign litedramcore_litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock));
-assign litedramcore_interface_bank7_addr = rhs_array_muxed33;
-assign litedramcore_interface_bank7_we = rhs_array_muxed34;
-assign litedramcore_interface_bank7_valid = rhs_array_muxed35;
-assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready));
-assign user_port_wdata_ready = litedramcore_litedramcore_new_master_wdata_ready3;
-assign user_port_rdata_valid = litedramcore_litedramcore_new_master_rdata_valid13;
+assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
+assign litedramcore_interface_bank0_addr = rhs_self12;
+assign litedramcore_interface_bank0_we = rhs_self13;
+assign litedramcore_interface_bank0_valid = rhs_self14;
+assign litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock));
+assign litedramcore_interface_bank1_addr = rhs_self15;
+assign litedramcore_interface_bank1_we = rhs_self16;
+assign litedramcore_interface_bank1_valid = rhs_self17;
+assign litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock));
+assign litedramcore_interface_bank2_addr = rhs_self18;
+assign litedramcore_interface_bank2_we = rhs_self19;
+assign litedramcore_interface_bank2_valid = rhs_self20;
+assign litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock));
+assign litedramcore_interface_bank3_addr = rhs_self21;
+assign litedramcore_interface_bank3_we = rhs_self22;
+assign litedramcore_interface_bank3_valid = rhs_self23;
+assign litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock));
+assign litedramcore_interface_bank4_addr = rhs_self24;
+assign litedramcore_interface_bank4_we = rhs_self25;
+assign litedramcore_interface_bank4_valid = rhs_self26;
+assign litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock));
+assign litedramcore_interface_bank5_addr = rhs_self27;
+assign litedramcore_interface_bank5_we = rhs_self28;
+assign litedramcore_interface_bank5_valid = rhs_self29;
+assign litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock));
+assign litedramcore_interface_bank6_addr = rhs_self30;
+assign litedramcore_interface_bank6_we = rhs_self31;
+assign litedramcore_interface_bank6_valid = rhs_self32;
+assign litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)};
+assign litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock));
+assign litedramcore_interface_bank7_addr = rhs_self33;
+assign litedramcore_interface_bank7_we = rhs_self34;
+assign litedramcore_interface_bank7_valid = rhs_self35;
+assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready));
+assign user_port_wdata_ready = litedramcore_new_master_wdata_ready3;
+assign user_port_rdata_valid = litedramcore_new_master_rdata_valid13;
 always @(*) begin
     litedramcore_interface_wdata <= 128'd0;
-    case ({litedramcore_litedramcore_new_master_wdata_ready3})
+    case ({litedramcore_new_master_wdata_ready3})
         1'd1: begin
             litedramcore_interface_wdata <= user_port_wdata_payload_data;
         end
@@ -8155,7 +8533,7 @@ always @(*) begin
 end
 always @(*) begin
     litedramcore_interface_wdata_we <= 16'd0;
-    case ({litedramcore_litedramcore_new_master_wdata_ready3})
+    case ({litedramcore_new_master_wdata_ready3})
         1'd1: begin
             litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
         end
@@ -8165,175 +8543,164 @@ always @(*) begin
     endcase
 end
 assign user_port_rdata_payload_data = litedramcore_interface_rdata;
-assign litedramcore_litedramcore_roundrobin0_grant = 1'd0;
-assign litedramcore_litedramcore_roundrobin1_grant = 1'd0;
-assign litedramcore_litedramcore_roundrobin2_grant = 1'd0;
-assign litedramcore_litedramcore_roundrobin3_grant = 1'd0;
-assign litedramcore_litedramcore_roundrobin4_grant = 1'd0;
-assign litedramcore_litedramcore_roundrobin5_grant = 1'd0;
-assign litedramcore_litedramcore_roundrobin6_grant = 1'd0;
-assign litedramcore_litedramcore_roundrobin7_grant = 1'd0;
+assign litedramcore_roundrobin0_grant = 1'd0;
+assign litedramcore_roundrobin1_grant = 1'd0;
+assign litedramcore_roundrobin2_grant = 1'd0;
+assign litedramcore_roundrobin3_grant = 1'd0;
+assign litedramcore_roundrobin4_grant = 1'd0;
+assign litedramcore_roundrobin5_grant = 1'd0;
+assign litedramcore_roundrobin6_grant = 1'd0;
+assign litedramcore_roundrobin7_grant = 1'd0;
 always @(*) begin
-    litedramcore_next_state <= 2'd0;
-    litedramcore_next_state <= litedramcore_state;
-    case (litedramcore_state)
+    next_state <= 2'd0;
+    next_state <= state;
+    case (state)
         1'd1: begin
-            litedramcore_next_state <= 2'd2;
+            next_state <= 2'd2;
         end
         2'd2: begin
-            litedramcore_next_state <= 1'd0;
+            next_state <= 1'd0;
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_next_state <= 1'd1;
+            if ((interface0_cyc & interface0_stb)) begin
+                next_state <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_adr_next_value1 <= 14'd0;
-    case (litedramcore_state)
+    interface0_ack <= 1'd0;
+    case (state)
         1'd1: begin
-            litedramcore_adr_next_value1 <= 1'd0;
         end
         2'd2: begin
+            interface0_ack <= 1'd1;
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_adr_next_value_ce1 <= 1'd0;
-    case (litedramcore_state)
+    interface0_dat_r <= 32'd0;
+    case (state)
         1'd1: begin
-            litedramcore_adr_next_value_ce1 <= 1'd1;
         end
         2'd2: begin
+            interface0_dat_r <= interface1_dat_r;
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_adr_next_value_ce1 <= 1'd1;
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_we_next_value2 <= 1'd0;
-    case (litedramcore_state)
+    interface1_dat_w_next_value0 <= 32'd0;
+    case (state)
         1'd1: begin
-            litedramcore_we_next_value2 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
-            end
+            interface1_dat_w_next_value0 <= interface0_dat_w;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_we_next_value_ce2 <= 1'd0;
-    case (litedramcore_state)
+    interface1_dat_w_next_value_ce0 <= 1'd0;
+    case (state)
         1'd1: begin
-            litedramcore_we_next_value_ce2 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_we_next_value_ce2 <= 1'd1;
-            end
+            interface1_dat_w_next_value_ce0 <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_wishbone_dat_r <= 32'd0;
-    case (litedramcore_state)
+    interface1_adr_next_value1 <= 14'd0;
+    case (state)
         1'd1: begin
+            interface1_adr_next_value1 <= 1'd0;
         end
         2'd2: begin
-            litedramcore_wishbone_dat_r <= litedramcore_dat_r;
         end
         default: begin
+            if ((interface0_cyc & interface0_stb)) begin
+                interface1_adr_next_value1 <= interface0_adr[29:0];
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_wishbone_ack <= 1'd0;
-    case (litedramcore_state)
+    interface1_adr_next_value_ce1 <= 1'd0;
+    case (state)
         1'd1: begin
+            interface1_adr_next_value_ce1 <= 1'd1;
         end
         2'd2: begin
-            litedramcore_wishbone_ack <= 1'd1;
         end
         default: begin
+            if ((interface0_cyc & interface0_stb)) begin
+                interface1_adr_next_value_ce1 <= 1'd1;
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_dat_w_next_value0 <= 32'd0;
-    case (litedramcore_state)
+    interface1_we_next_value2 <= 1'd0;
+    case (state)
         1'd1: begin
+            interface1_we_next_value2 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
-            litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
+            if ((interface0_cyc & interface0_stb)) begin
+                interface1_we_next_value2 <= (interface0_we & (interface0_sel != 1'd0));
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_dat_w_next_value_ce0 <= 1'd0;
-    case (litedramcore_state)
+    interface1_we_next_value_ce2 <= 1'd0;
+    case (state)
         1'd1: begin
+            interface1_we_next_value_ce2 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
-            litedramcore_dat_w_next_value_ce0 <= 1'd1;
+            if ((interface0_cyc & interface0_stb)) begin
+                interface1_we_next_value_ce2 <= 1'd1;
+            end
         end
     endcase
 end
-assign litedramcore_wishbone_adr = wb_bus_adr;
-assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
-assign wb_bus_dat_r = litedramcore_wishbone_dat_r;
-assign litedramcore_wishbone_sel = wb_bus_sel;
-assign litedramcore_wishbone_cyc = wb_bus_cyc;
-assign litedramcore_wishbone_stb = wb_bus_stb;
-assign wb_bus_ack = litedramcore_wishbone_ack;
-assign litedramcore_wishbone_we = wb_bus_we;
-assign litedramcore_wishbone_cti = wb_bus_cti;
-assign litedramcore_wishbone_bte = wb_bus_bte;
-assign wb_bus_err = litedramcore_wishbone_err;
 assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
 assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank0_init_done0_we <= 1'd0;
+    csrbank0_init_done0_re <= 1'd0;
     if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank0_init_done0_we <= (~interface0_bank_bus_we);
+        csrbank0_init_done0_re <= interface0_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank0_init_done0_re <= 1'd0;
+    csrbank0_init_done0_we <= 1'd0;
     if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank0_init_done0_re <= interface0_bank_bus_we;
+        csrbank0_init_done0_we <= (~interface0_bank_bus_we);
     end
 end
 assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank0_init_error0_re <= 1'd0;
+    csrbank0_init_error0_we <= 1'd0;
     if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank0_init_error0_re <= interface0_bank_bus_we;
+        csrbank0_init_error0_we <= (~interface0_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank0_init_error0_we <= 1'd0;
+    csrbank0_init_error0_re <= 1'd0;
     if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank0_init_error0_we <= (~interface0_bank_bus_we);
+        csrbank0_init_error0_re <= interface0_bank_bus_we;
     end
 end
 assign csrbank0_init_done0_w = init_done_storage;
@@ -8341,15 +8708,15 @@ assign csrbank0_init_error0_w = init_error_storage;
 assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
 assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    csrbank1_dly_sel0_re <= 1'd0;
+    csrbank1_dly_sel0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank1_dly_sel0_re <= interface1_bank_bus_we;
+        csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank1_dly_sel0_we <= 1'd0;
+    csrbank1_dly_sel0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
+        csrbank1_dly_sel0_re <= interface1_bank_bus_we;
     end
 end
 assign ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
@@ -8419,15 +8786,15 @@ always @(*) begin
 end
 assign csrbank1_burstdet_seen_r = interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    csrbank1_burstdet_seen_we <= 1'd0;
+    csrbank1_burstdet_seen_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        csrbank1_burstdet_seen_we <= (~interface1_bank_bus_we);
+        csrbank1_burstdet_seen_re <= interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_burstdet_seen_re <= 1'd0;
+    csrbank1_burstdet_seen_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        csrbank1_burstdet_seen_re <= interface1_bank_bus_we;
+        csrbank1_burstdet_seen_we <= (~interface1_bank_bus_we);
     end
 end
 assign csrbank1_dly_sel0_w = ddrphy_dly_sel_storage[1:0];
@@ -8436,28 +8803,28 @@ assign ddrphy_burstdet_seen_we = csrbank1_burstdet_seen_we;
 assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2);
 assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
 always @(*) begin
-    csrbank2_dfii_control0_we <= 1'd0;
+    csrbank2_dfii_control0_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_control0_re <= interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_control0_re <= 1'd0;
+    csrbank2_dfii_control0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank2_dfii_control0_re <= interface2_bank_bus_we;
+        csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi0_command0_re <= 1'd0;
+    csrbank2_dfii_pi0_command0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_command0_we <= 1'd0;
+    csrbank2_dfii_pi0_command0_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
     end
 end
 assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
@@ -8475,93 +8842,93 @@ always @(*) begin
 end
 assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-    csrbank2_dfii_pi0_address0_we <= 1'd0;
+    csrbank2_dfii_pi0_address0_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_address0_re <= 1'd0;
+    csrbank2_dfii_pi0_address0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
     end
 end
 assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank2_dfii_pi0_baddress0_we <= 1'd0;
+    csrbank2_dfii_pi0_baddress0_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
-        csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_baddress0_re <= 1'd0;
+    csrbank2_dfii_pi0_baddress0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
-        csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
     end
 end
 assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi0_wrdata1_re <= 1'd0;
+    csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
-        csrbank2_dfii_pi0_wrdata1_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi0_wrdata1_we <= (~interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
+    csrbank2_dfii_pi0_wrdata1_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
-        csrbank2_dfii_pi0_wrdata1_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi0_wrdata1_re <= interface2_bank_bus_we;
     end
 end
 assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
+    csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
-        csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
+    csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
-        csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
     end
 end
 assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi0_rddata1_re <= 1'd0;
+    csrbank2_dfii_pi0_rddata1_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
-        csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi0_rddata1_we <= (~interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_rddata1_we <= 1'd0;
+    csrbank2_dfii_pi0_rddata1_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
-        csrbank2_dfii_pi0_rddata1_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we;
     end
 end
 assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi0_rddata0_re <= 1'd0;
+    csrbank2_dfii_pi0_rddata0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
-        csrbank2_dfii_pi0_rddata0_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi0_rddata0_we <= (~interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_rddata0_we <= 1'd0;
+    csrbank2_dfii_pi0_rddata0_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
-        csrbank2_dfii_pi0_rddata0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi0_rddata0_re <= interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi1_command0_we <= 1'd0;
+    csrbank2_dfii_pi1_command0_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
-        csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_command0_re <= 1'd0;
+    csrbank2_dfii_pi1_command0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
-        csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
     end
 end
 assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
@@ -8579,80 +8946,80 @@ always @(*) begin
 end
 assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-    csrbank2_dfii_pi1_address0_we <= 1'd0;
+    csrbank2_dfii_pi1_address0_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
-        csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_address0_re <= 1'd0;
+    csrbank2_dfii_pi1_address0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
-        csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
     end
 end
 assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank2_dfii_pi1_baddress0_re <= 1'd0;
+    csrbank2_dfii_pi1_baddress0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
-        csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_baddress0_we <= 1'd0;
+    csrbank2_dfii_pi1_baddress0_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
-        csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
     end
 end
 assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
+    csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
-        csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
+    csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
-        csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we);
     end
 end
 assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
+    csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
-        csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
+    csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
-        csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
     end
 end
 assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi1_rddata1_re <= 1'd0;
+    csrbank2_dfii_pi1_rddata1_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
-        csrbank2_dfii_pi1_rddata1_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi1_rddata1_we <= (~interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_rddata1_we <= 1'd0;
+    csrbank2_dfii_pi1_rddata1_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
-        csrbank2_dfii_pi1_rddata1_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi1_rddata1_re <= interface2_bank_bus_we;
     end
 end
 assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi1_rddata0_we <= 1'd0;
+    csrbank2_dfii_pi1_rddata0_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
-        csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_rddata0_re <= 1'd0;
+    csrbank2_dfii_pi1_rddata0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
-        csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we);
     end
 end
 assign litedramcore_sel = litedramcore_storage[0];
@@ -8666,7 +9033,9 @@ assign litedramcore_phaseinjector0_csrfield_cas = litedramcore_phaseinjector0_co
 assign litedramcore_phaseinjector0_csrfield_ras = litedramcore_phaseinjector0_command_storage[3];
 assign litedramcore_phaseinjector0_csrfield_wren = litedramcore_phaseinjector0_command_storage[4];
 assign litedramcore_phaseinjector0_csrfield_rden = litedramcore_phaseinjector0_command_storage[5];
-assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
+assign litedramcore_phaseinjector0_csrfield_cs_top = litedramcore_phaseinjector0_command_storage[6];
+assign litedramcore_phaseinjector0_csrfield_cs_bottom = litedramcore_phaseinjector0_command_storage[7];
+assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[7:0];
 assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0];
 assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
 assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[63:32];
@@ -8680,7 +9049,9 @@ assign litedramcore_phaseinjector1_csrfield_cas = litedramcore_phaseinjector1_co
 assign litedramcore_phaseinjector1_csrfield_ras = litedramcore_phaseinjector1_command_storage[3];
 assign litedramcore_phaseinjector1_csrfield_wren = litedramcore_phaseinjector1_command_storage[4];
 assign litedramcore_phaseinjector1_csrfield_rden = litedramcore_phaseinjector1_command_storage[5];
-assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
+assign litedramcore_phaseinjector1_csrfield_cs_top = litedramcore_phaseinjector1_command_storage[6];
+assign litedramcore_phaseinjector1_csrfield_cs_bottom = litedramcore_phaseinjector1_command_storage[7];
+assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[7:0];
 assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[14:0];
 assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
 assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[63:32];
@@ -8688,973 +9059,973 @@ assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[
 assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_rddata_status[63:32];
 assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_rddata_status[31:0];
 assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata0_we;
-assign csr_interconnect_adr = litedramcore_adr;
-assign csr_interconnect_we = litedramcore_we;
-assign csr_interconnect_dat_w = litedramcore_dat_w;
-assign litedramcore_dat_r = csr_interconnect_dat_r;
-assign interface0_bank_bus_adr = csr_interconnect_adr;
-assign interface1_bank_bus_adr = csr_interconnect_adr;
-assign interface2_bank_bus_adr = csr_interconnect_adr;
-assign interface0_bank_bus_we = csr_interconnect_we;
-assign interface1_bank_bus_we = csr_interconnect_we;
-assign interface2_bank_bus_we = csr_interconnect_we;
-assign interface0_bank_bus_dat_w = csr_interconnect_dat_w;
-assign interface1_bank_bus_dat_w = csr_interconnect_dat_w;
-assign interface2_bank_bus_dat_w = csr_interconnect_dat_w;
-assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
-always @(*) begin
-    rhs_array_muxed0 <= 1'd0;
+assign adr = interface1_adr;
+assign we = interface1_we;
+assign dat_w = interface1_dat_w;
+assign interface1_dat_r = dat_r;
+assign interface0_bank_bus_adr = adr;
+assign interface1_bank_bus_adr = adr;
+assign interface2_bank_bus_adr = adr;
+assign interface0_bank_bus_we = we;
+assign interface1_bank_bus_we = we;
+assign interface2_bank_bus_we = we;
+assign interface0_bank_bus_dat_w = dat_w;
+assign interface1_bank_bus_dat_w = dat_w;
+assign interface2_bank_bus_dat_w = dat_w;
+assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
+always @(*) begin
+    rhs_self0 <= 1'd0;
     case (litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
+            rhs_self0 <= litedramcore_choose_cmd_valids[0];
         end
         1'd1: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
+            rhs_self0 <= litedramcore_choose_cmd_valids[1];
         end
         2'd2: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
+            rhs_self0 <= litedramcore_choose_cmd_valids[2];
         end
         2'd3: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
+            rhs_self0 <= litedramcore_choose_cmd_valids[3];
         end
         3'd4: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
+            rhs_self0 <= litedramcore_choose_cmd_valids[4];
         end
         3'd5: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
+            rhs_self0 <= litedramcore_choose_cmd_valids[5];
         end
         3'd6: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
+            rhs_self0 <= litedramcore_choose_cmd_valids[6];
         end
         default: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
+            rhs_self0 <= litedramcore_choose_cmd_valids[7];
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed1 <= 15'd0;
+    rhs_self1 <= 15'd0;
     case (litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
+            rhs_self1 <= litedramcore_bankmachine0_cmd_payload_a;
         end
         1'd1: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
+            rhs_self1 <= litedramcore_bankmachine1_cmd_payload_a;
         end
         2'd2: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
+            rhs_self1 <= litedramcore_bankmachine2_cmd_payload_a;
         end
         2'd3: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
+            rhs_self1 <= litedramcore_bankmachine3_cmd_payload_a;
         end
         3'd4: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
+            rhs_self1 <= litedramcore_bankmachine4_cmd_payload_a;
         end
         3'd5: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
+            rhs_self1 <= litedramcore_bankmachine5_cmd_payload_a;
         end
         3'd6: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
+            rhs_self1 <= litedramcore_bankmachine6_cmd_payload_a;
         end
         default: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
+            rhs_self1 <= litedramcore_bankmachine7_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed2 <= 3'd0;
+    rhs_self2 <= 3'd0;
     case (litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
+            rhs_self2 <= litedramcore_bankmachine0_cmd_payload_ba;
         end
         1'd1: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
+            rhs_self2 <= litedramcore_bankmachine1_cmd_payload_ba;
         end
         2'd2: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
+            rhs_self2 <= litedramcore_bankmachine2_cmd_payload_ba;
         end
         2'd3: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
+            rhs_self2 <= litedramcore_bankmachine3_cmd_payload_ba;
         end
         3'd4: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
+            rhs_self2 <= litedramcore_bankmachine4_cmd_payload_ba;
         end
         3'd5: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
+            rhs_self2 <= litedramcore_bankmachine5_cmd_payload_ba;
         end
         3'd6: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
+            rhs_self2 <= litedramcore_bankmachine6_cmd_payload_ba;
         end
         default: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
+            rhs_self2 <= litedramcore_bankmachine7_cmd_payload_ba;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed3 <= 1'd0;
+    rhs_self3 <= 1'd0;
     case (litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
+            rhs_self3 <= litedramcore_bankmachine0_cmd_payload_is_read;
         end
         1'd1: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
+            rhs_self3 <= litedramcore_bankmachine1_cmd_payload_is_read;
         end
         2'd2: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
+            rhs_self3 <= litedramcore_bankmachine2_cmd_payload_is_read;
         end
         2'd3: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
+            rhs_self3 <= litedramcore_bankmachine3_cmd_payload_is_read;
         end
         3'd4: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
+            rhs_self3 <= litedramcore_bankmachine4_cmd_payload_is_read;
         end
         3'd5: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
+            rhs_self3 <= litedramcore_bankmachine5_cmd_payload_is_read;
         end
         3'd6: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
+            rhs_self3 <= litedramcore_bankmachine6_cmd_payload_is_read;
         end
         default: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
+            rhs_self3 <= litedramcore_bankmachine7_cmd_payload_is_read;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed4 <= 1'd0;
+    rhs_self4 <= 1'd0;
     case (litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
+            rhs_self4 <= litedramcore_bankmachine0_cmd_payload_is_write;
         end
         1'd1: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
+            rhs_self4 <= litedramcore_bankmachine1_cmd_payload_is_write;
         end
         2'd2: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
+            rhs_self4 <= litedramcore_bankmachine2_cmd_payload_is_write;
         end
         2'd3: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
+            rhs_self4 <= litedramcore_bankmachine3_cmd_payload_is_write;
         end
         3'd4: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
+            rhs_self4 <= litedramcore_bankmachine4_cmd_payload_is_write;
         end
         3'd5: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
+            rhs_self4 <= litedramcore_bankmachine5_cmd_payload_is_write;
         end
         3'd6: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
+            rhs_self4 <= litedramcore_bankmachine6_cmd_payload_is_write;
         end
         default: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
+            rhs_self4 <= litedramcore_bankmachine7_cmd_payload_is_write;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed5 <= 1'd0;
+    rhs_self5 <= 1'd0;
     case (litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+            rhs_self5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
         end
         1'd1: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+            rhs_self5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
         end
         2'd2: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+            rhs_self5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
         end
         2'd3: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+            rhs_self5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
         end
         3'd4: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+            rhs_self5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
         end
         3'd5: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+            rhs_self5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
         end
         3'd6: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+            rhs_self5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
         end
         default: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+            rhs_self5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed0 <= 1'd0;
+    t_self0 <= 1'd0;
     case (litedramcore_choose_cmd_grant)
         1'd0: begin
-            t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
+            t_self0 <= litedramcore_bankmachine0_cmd_payload_cas;
         end
         1'd1: begin
-            t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
+            t_self0 <= litedramcore_bankmachine1_cmd_payload_cas;
         end
         2'd2: begin
-            t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
+            t_self0 <= litedramcore_bankmachine2_cmd_payload_cas;
         end
         2'd3: begin
-            t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
+            t_self0 <= litedramcore_bankmachine3_cmd_payload_cas;
         end
         3'd4: begin
-            t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
+            t_self0 <= litedramcore_bankmachine4_cmd_payload_cas;
         end
         3'd5: begin
-            t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
+            t_self0 <= litedramcore_bankmachine5_cmd_payload_cas;
         end
         3'd6: begin
-            t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
+            t_self0 <= litedramcore_bankmachine6_cmd_payload_cas;
         end
         default: begin
-            t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
+            t_self0 <= litedramcore_bankmachine7_cmd_payload_cas;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed1 <= 1'd0;
+    t_self1 <= 1'd0;
     case (litedramcore_choose_cmd_grant)
         1'd0: begin
-            t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
+            t_self1 <= litedramcore_bankmachine0_cmd_payload_ras;
         end
         1'd1: begin
-            t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
+            t_self1 <= litedramcore_bankmachine1_cmd_payload_ras;
         end
         2'd2: begin
-            t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
+            t_self1 <= litedramcore_bankmachine2_cmd_payload_ras;
         end
         2'd3: begin
-            t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
+            t_self1 <= litedramcore_bankmachine3_cmd_payload_ras;
         end
         3'd4: begin
-            t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
+            t_self1 <= litedramcore_bankmachine4_cmd_payload_ras;
         end
         3'd5: begin
-            t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
+            t_self1 <= litedramcore_bankmachine5_cmd_payload_ras;
         end
         3'd6: begin
-            t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
+            t_self1 <= litedramcore_bankmachine6_cmd_payload_ras;
         end
         default: begin
-            t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
+            t_self1 <= litedramcore_bankmachine7_cmd_payload_ras;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed2 <= 1'd0;
+    t_self2 <= 1'd0;
     case (litedramcore_choose_cmd_grant)
         1'd0: begin
-            t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
+            t_self2 <= litedramcore_bankmachine0_cmd_payload_we;
         end
         1'd1: begin
-            t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
+            t_self2 <= litedramcore_bankmachine1_cmd_payload_we;
         end
         2'd2: begin
-            t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
+            t_self2 <= litedramcore_bankmachine2_cmd_payload_we;
         end
         2'd3: begin
-            t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
+            t_self2 <= litedramcore_bankmachine3_cmd_payload_we;
         end
         3'd4: begin
-            t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
+            t_self2 <= litedramcore_bankmachine4_cmd_payload_we;
         end
         3'd5: begin
-            t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
+            t_self2 <= litedramcore_bankmachine5_cmd_payload_we;
         end
         3'd6: begin
-            t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
+            t_self2 <= litedramcore_bankmachine6_cmd_payload_we;
         end
         default: begin
-            t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
+            t_self2 <= litedramcore_bankmachine7_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed6 <= 1'd0;
+    rhs_self6 <= 1'd0;
     case (litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
+            rhs_self6 <= litedramcore_choose_req_valids[0];
         end
         1'd1: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
+            rhs_self6 <= litedramcore_choose_req_valids[1];
         end
         2'd2: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
+            rhs_self6 <= litedramcore_choose_req_valids[2];
         end
         2'd3: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
+            rhs_self6 <= litedramcore_choose_req_valids[3];
         end
         3'd4: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
+            rhs_self6 <= litedramcore_choose_req_valids[4];
         end
         3'd5: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
+            rhs_self6 <= litedramcore_choose_req_valids[5];
         end
         3'd6: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
+            rhs_self6 <= litedramcore_choose_req_valids[6];
         end
         default: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
+            rhs_self6 <= litedramcore_choose_req_valids[7];
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed7 <= 15'd0;
+    rhs_self7 <= 15'd0;
     case (litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
+            rhs_self7 <= litedramcore_bankmachine0_cmd_payload_a;
         end
         1'd1: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
+            rhs_self7 <= litedramcore_bankmachine1_cmd_payload_a;
         end
         2'd2: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
+            rhs_self7 <= litedramcore_bankmachine2_cmd_payload_a;
         end
         2'd3: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
+            rhs_self7 <= litedramcore_bankmachine3_cmd_payload_a;
         end
         3'd4: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
+            rhs_self7 <= litedramcore_bankmachine4_cmd_payload_a;
         end
         3'd5: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
+            rhs_self7 <= litedramcore_bankmachine5_cmd_payload_a;
         end
         3'd6: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
+            rhs_self7 <= litedramcore_bankmachine6_cmd_payload_a;
         end
         default: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
+            rhs_self7 <= litedramcore_bankmachine7_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed8 <= 3'd0;
+    rhs_self8 <= 3'd0;
     case (litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
+            rhs_self8 <= litedramcore_bankmachine0_cmd_payload_ba;
         end
         1'd1: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
+            rhs_self8 <= litedramcore_bankmachine1_cmd_payload_ba;
         end
         2'd2: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
+            rhs_self8 <= litedramcore_bankmachine2_cmd_payload_ba;
         end
         2'd3: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
+            rhs_self8 <= litedramcore_bankmachine3_cmd_payload_ba;
         end
         3'd4: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
+            rhs_self8 <= litedramcore_bankmachine4_cmd_payload_ba;
         end
         3'd5: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
+            rhs_self8 <= litedramcore_bankmachine5_cmd_payload_ba;
         end
         3'd6: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
+            rhs_self8 <= litedramcore_bankmachine6_cmd_payload_ba;
         end
         default: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
+            rhs_self8 <= litedramcore_bankmachine7_cmd_payload_ba;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed9 <= 1'd0;
+    rhs_self9 <= 1'd0;
     case (litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
+            rhs_self9 <= litedramcore_bankmachine0_cmd_payload_is_read;
         end
         1'd1: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
+            rhs_self9 <= litedramcore_bankmachine1_cmd_payload_is_read;
         end
         2'd2: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
+            rhs_self9 <= litedramcore_bankmachine2_cmd_payload_is_read;
         end
         2'd3: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
+            rhs_self9 <= litedramcore_bankmachine3_cmd_payload_is_read;
         end
         3'd4: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
+            rhs_self9 <= litedramcore_bankmachine4_cmd_payload_is_read;
         end
         3'd5: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
+            rhs_self9 <= litedramcore_bankmachine5_cmd_payload_is_read;
         end
         3'd6: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
+            rhs_self9 <= litedramcore_bankmachine6_cmd_payload_is_read;
         end
         default: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
+            rhs_self9 <= litedramcore_bankmachine7_cmd_payload_is_read;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed10 <= 1'd0;
+    rhs_self10 <= 1'd0;
     case (litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
+            rhs_self10 <= litedramcore_bankmachine0_cmd_payload_is_write;
         end
         1'd1: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
+            rhs_self10 <= litedramcore_bankmachine1_cmd_payload_is_write;
         end
         2'd2: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
+            rhs_self10 <= litedramcore_bankmachine2_cmd_payload_is_write;
         end
         2'd3: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
+            rhs_self10 <= litedramcore_bankmachine3_cmd_payload_is_write;
         end
         3'd4: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
+            rhs_self10 <= litedramcore_bankmachine4_cmd_payload_is_write;
         end
         3'd5: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
+            rhs_self10 <= litedramcore_bankmachine5_cmd_payload_is_write;
         end
         3'd6: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
+            rhs_self10 <= litedramcore_bankmachine6_cmd_payload_is_write;
         end
         default: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
+            rhs_self10 <= litedramcore_bankmachine7_cmd_payload_is_write;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed11 <= 1'd0;
+    rhs_self11 <= 1'd0;
     case (litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+            rhs_self11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
         end
         1'd1: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+            rhs_self11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
         end
         2'd2: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+            rhs_self11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
         end
         2'd3: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+            rhs_self11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
         end
         3'd4: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+            rhs_self11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
         end
         3'd5: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+            rhs_self11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
         end
         3'd6: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+            rhs_self11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
         end
         default: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+            rhs_self11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed3 <= 1'd0;
+    t_self3 <= 1'd0;
     case (litedramcore_choose_req_grant)
         1'd0: begin
-            t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
+            t_self3 <= litedramcore_bankmachine0_cmd_payload_cas;
         end
         1'd1: begin
-            t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
+            t_self3 <= litedramcore_bankmachine1_cmd_payload_cas;
         end
         2'd2: begin
-            t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
+            t_self3 <= litedramcore_bankmachine2_cmd_payload_cas;
         end
         2'd3: begin
-            t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
+            t_self3 <= litedramcore_bankmachine3_cmd_payload_cas;
         end
         3'd4: begin
-            t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
+            t_self3 <= litedramcore_bankmachine4_cmd_payload_cas;
         end
         3'd5: begin
-            t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
+            t_self3 <= litedramcore_bankmachine5_cmd_payload_cas;
         end
         3'd6: begin
-            t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
+            t_self3 <= litedramcore_bankmachine6_cmd_payload_cas;
         end
         default: begin
-            t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
+            t_self3 <= litedramcore_bankmachine7_cmd_payload_cas;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed4 <= 1'd0;
+    t_self4 <= 1'd0;
     case (litedramcore_choose_req_grant)
         1'd0: begin
-            t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
+            t_self4 <= litedramcore_bankmachine0_cmd_payload_ras;
         end
         1'd1: begin
-            t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
+            t_self4 <= litedramcore_bankmachine1_cmd_payload_ras;
         end
         2'd2: begin
-            t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
+            t_self4 <= litedramcore_bankmachine2_cmd_payload_ras;
         end
         2'd3: begin
-            t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
+            t_self4 <= litedramcore_bankmachine3_cmd_payload_ras;
         end
         3'd4: begin
-            t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
+            t_self4 <= litedramcore_bankmachine4_cmd_payload_ras;
         end
         3'd5: begin
-            t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
+            t_self4 <= litedramcore_bankmachine5_cmd_payload_ras;
         end
         3'd6: begin
-            t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
+            t_self4 <= litedramcore_bankmachine6_cmd_payload_ras;
         end
         default: begin
-            t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
+            t_self4 <= litedramcore_bankmachine7_cmd_payload_ras;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed5 <= 1'd0;
+    t_self5 <= 1'd0;
     case (litedramcore_choose_req_grant)
         1'd0: begin
-            t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
+            t_self5 <= litedramcore_bankmachine0_cmd_payload_we;
         end
         1'd1: begin
-            t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
+            t_self5 <= litedramcore_bankmachine1_cmd_payload_we;
         end
         2'd2: begin
-            t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
+            t_self5 <= litedramcore_bankmachine2_cmd_payload_we;
         end
         2'd3: begin
-            t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
+            t_self5 <= litedramcore_bankmachine3_cmd_payload_we;
         end
         3'd4: begin
-            t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
+            t_self5 <= litedramcore_bankmachine4_cmd_payload_we;
         end
         3'd5: begin
-            t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
+            t_self5 <= litedramcore_bankmachine5_cmd_payload_we;
         end
         3'd6: begin
-            t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
+            t_self5 <= litedramcore_bankmachine6_cmd_payload_we;
         end
         default: begin
-            t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
+            t_self5 <= litedramcore_bankmachine7_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed12 <= 22'd0;
-    case (litedramcore_litedramcore_roundrobin0_grant)
+    rhs_self12 <= 22'd0;
+    case (litedramcore_roundrobin0_grant)
         default: begin
-            rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+            rhs_self12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed13 <= 1'd0;
-    case (litedramcore_litedramcore_roundrobin0_grant)
+    rhs_self13 <= 1'd0;
+    case (litedramcore_roundrobin0_grant)
         default: begin
-            rhs_array_muxed13 <= user_port_cmd_payload_we;
+            rhs_self13 <= user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed14 <= 1'd0;
-    case (litedramcore_litedramcore_roundrobin0_grant)
+    rhs_self14 <= 1'd0;
+    case (litedramcore_roundrobin0_grant)
         default: begin
-            rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            rhs_self14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed15 <= 22'd0;
-    case (litedramcore_litedramcore_roundrobin1_grant)
+    rhs_self15 <= 22'd0;
+    case (litedramcore_roundrobin1_grant)
         default: begin
-            rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+            rhs_self15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed16 <= 1'd0;
-    case (litedramcore_litedramcore_roundrobin1_grant)
+    rhs_self16 <= 1'd0;
+    case (litedramcore_roundrobin1_grant)
         default: begin
-            rhs_array_muxed16 <= user_port_cmd_payload_we;
+            rhs_self16 <= user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed17 <= 1'd0;
-    case (litedramcore_litedramcore_roundrobin1_grant)
+    rhs_self17 <= 1'd0;
+    case (litedramcore_roundrobin1_grant)
         default: begin
-            rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            rhs_self17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed18 <= 22'd0;
-    case (litedramcore_litedramcore_roundrobin2_grant)
+    rhs_self18 <= 22'd0;
+    case (litedramcore_roundrobin2_grant)
         default: begin
-            rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+            rhs_self18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed19 <= 1'd0;
-    case (litedramcore_litedramcore_roundrobin2_grant)
+    rhs_self19 <= 1'd0;
+    case (litedramcore_roundrobin2_grant)
         default: begin
-            rhs_array_muxed19 <= user_port_cmd_payload_we;
+            rhs_self19 <= user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed20 <= 1'd0;
-    case (litedramcore_litedramcore_roundrobin2_grant)
+    rhs_self20 <= 1'd0;
+    case (litedramcore_roundrobin2_grant)
         default: begin
-            rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            rhs_self20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed21 <= 22'd0;
-    case (litedramcore_litedramcore_roundrobin3_grant)
+    rhs_self21 <= 22'd0;
+    case (litedramcore_roundrobin3_grant)
         default: begin
-            rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+            rhs_self21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed22 <= 1'd0;
-    case (litedramcore_litedramcore_roundrobin3_grant)
+    rhs_self22 <= 1'd0;
+    case (litedramcore_roundrobin3_grant)
         default: begin
-            rhs_array_muxed22 <= user_port_cmd_payload_we;
+            rhs_self22 <= user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed23 <= 1'd0;
-    case (litedramcore_litedramcore_roundrobin3_grant)
+    rhs_self23 <= 1'd0;
+    case (litedramcore_roundrobin3_grant)
         default: begin
-            rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            rhs_self23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed24 <= 22'd0;
-    case (litedramcore_litedramcore_roundrobin4_grant)
+    rhs_self24 <= 22'd0;
+    case (litedramcore_roundrobin4_grant)
         default: begin
-            rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+            rhs_self24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed25 <= 1'd0;
-    case (litedramcore_litedramcore_roundrobin4_grant)
+    rhs_self25 <= 1'd0;
+    case (litedramcore_roundrobin4_grant)
         default: begin
-            rhs_array_muxed25 <= user_port_cmd_payload_we;
+            rhs_self25 <= user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed26 <= 1'd0;
-    case (litedramcore_litedramcore_roundrobin4_grant)
+    rhs_self26 <= 1'd0;
+    case (litedramcore_roundrobin4_grant)
         default: begin
-            rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            rhs_self26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed27 <= 22'd0;
-    case (litedramcore_litedramcore_roundrobin5_grant)
+    rhs_self27 <= 22'd0;
+    case (litedramcore_roundrobin5_grant)
         default: begin
-            rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+            rhs_self27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed28 <= 1'd0;
-    case (litedramcore_litedramcore_roundrobin5_grant)
+    rhs_self28 <= 1'd0;
+    case (litedramcore_roundrobin5_grant)
         default: begin
-            rhs_array_muxed28 <= user_port_cmd_payload_we;
+            rhs_self28 <= user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed29 <= 1'd0;
-    case (litedramcore_litedramcore_roundrobin5_grant)
+    rhs_self29 <= 1'd0;
+    case (litedramcore_roundrobin5_grant)
         default: begin
-            rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            rhs_self29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed30 <= 22'd0;
-    case (litedramcore_litedramcore_roundrobin6_grant)
+    rhs_self30 <= 22'd0;
+    case (litedramcore_roundrobin6_grant)
         default: begin
-            rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+            rhs_self30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed31 <= 1'd0;
-    case (litedramcore_litedramcore_roundrobin6_grant)
+    rhs_self31 <= 1'd0;
+    case (litedramcore_roundrobin6_grant)
         default: begin
-            rhs_array_muxed31 <= user_port_cmd_payload_we;
+            rhs_self31 <= user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed32 <= 1'd0;
-    case (litedramcore_litedramcore_roundrobin6_grant)
+    rhs_self32 <= 1'd0;
+    case (litedramcore_roundrobin6_grant)
         default: begin
-            rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            rhs_self32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed33 <= 22'd0;
-    case (litedramcore_litedramcore_roundrobin7_grant)
+    rhs_self33 <= 22'd0;
+    case (litedramcore_roundrobin7_grant)
         default: begin
-            rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+            rhs_self33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed34 <= 1'd0;
-    case (litedramcore_litedramcore_roundrobin7_grant)
+    rhs_self34 <= 1'd0;
+    case (litedramcore_roundrobin7_grant)
         default: begin
-            rhs_array_muxed34 <= user_port_cmd_payload_we;
+            rhs_self34 <= user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed35 <= 1'd0;
-    case (litedramcore_litedramcore_roundrobin7_grant)
+    rhs_self35 <= 1'd0;
+    case (litedramcore_roundrobin7_grant)
         default: begin
-            rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
+            rhs_self35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    array_muxed0 <= 3'd0;
-    case (litedramcore_steerer_sel0)
+    self0 <= 3'd0;
+    case (litedramcore_steerer0)
         1'd0: begin
-            array_muxed0 <= litedramcore_nop_ba[2:0];
+            self0 <= litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            self0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            self0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
+            self0 <= litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed1 <= 15'd0;
-    case (litedramcore_steerer_sel0)
+    self1 <= 15'd0;
+    case (litedramcore_steerer0)
         1'd0: begin
-            array_muxed1 <= litedramcore_nop_a;
+            self1 <= litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
+            self1 <= litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
+            self1 <= litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed1 <= litedramcore_cmd_payload_a;
+            self1 <= litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed2 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    self2 <= 1'd0;
+    case (litedramcore_steerer0)
         1'd0: begin
-            array_muxed2 <= 1'd0;
+            self2 <= 1'd0;
         end
         1'd1: begin
-            array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+            self2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+            self2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+            self2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed3 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    self3 <= 1'd0;
+    case (litedramcore_steerer0)
         1'd0: begin
-            array_muxed3 <= 1'd0;
+            self3 <= 1'd0;
         end
         1'd1: begin
-            array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+            self3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+            self3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+            self3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed4 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    self4 <= 1'd0;
+    case (litedramcore_steerer0)
         1'd0: begin
-            array_muxed4 <= 1'd0;
+            self4 <= 1'd0;
         end
         1'd1: begin
-            array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+            self4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+            self4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+            self4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed5 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    self5 <= 1'd0;
+    case (litedramcore_steerer0)
         1'd0: begin
-            array_muxed5 <= 1'd0;
+            self5 <= 1'd0;
         end
         1'd1: begin
-            array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+            self5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+            self5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+            self5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed6 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    self6 <= 1'd0;
+    case (litedramcore_steerer0)
         1'd0: begin
-            array_muxed6 <= 1'd0;
+            self6 <= 1'd0;
         end
         1'd1: begin
-            array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+            self6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+            self6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+            self6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
         end
     endcase
 end
 always @(*) begin
-    array_muxed7 <= 3'd0;
-    case (litedramcore_steerer_sel1)
+    self7 <= 3'd0;
+    case (litedramcore_steerer1)
         1'd0: begin
-            array_muxed7 <= litedramcore_nop_ba[2:0];
+            self7 <= litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            self7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            self7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
+            self7 <= litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed8 <= 15'd0;
-    case (litedramcore_steerer_sel1)
+    self8 <= 15'd0;
+    case (litedramcore_steerer1)
         1'd0: begin
-            array_muxed8 <= litedramcore_nop_a;
+            self8 <= litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
+            self8 <= litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
+            self8 <= litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed8 <= litedramcore_cmd_payload_a;
+            self8 <= litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed9 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    self9 <= 1'd0;
+    case (litedramcore_steerer1)
         1'd0: begin
-            array_muxed9 <= 1'd0;
+            self9 <= 1'd0;
         end
         1'd1: begin
-            array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+            self9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+            self9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+            self9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed10 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    self10 <= 1'd0;
+    case (litedramcore_steerer1)
         1'd0: begin
-            array_muxed10 <= 1'd0;
+            self10 <= 1'd0;
         end
         1'd1: begin
-            array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+            self10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+            self10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+            self10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed11 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    self11 <= 1'd0;
+    case (litedramcore_steerer1)
         1'd0: begin
-            array_muxed11 <= 1'd0;
+            self11 <= 1'd0;
         end
         1'd1: begin
-            array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+            self11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+            self11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+            self11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed12 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    self12 <= 1'd0;
+    case (litedramcore_steerer1)
         1'd0: begin
-            array_muxed12 <= 1'd0;
+            self12 <= 1'd0;
         end
         1'd1: begin
-            array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+            self12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+            self12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+            self12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed13 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    self13 <= 1'd0;
+    case (litedramcore_steerer1)
         1'd0: begin
-            array_muxed13 <= 1'd0;
+            self13 <= 1'd0;
         end
         1'd1: begin
-            array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+            self13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+            self13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+            self13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
         end
     endcase
 end
-assign ddrphy_lock1 = regs1;
+assign ddrphy_lock1 = multiregimpl1;
 
 
 //------------------------------------------------------------------------------
@@ -9663,44 +10034,44 @@ assign ddrphy_lock1 = regs1;
 
 always @(posedge init_clk) begin
     ddrphy_lock_d <= ddrphy_lock1;
-    if ((ddrphy_counter == 4'd8)) begin
+    if ((ddrphy_trigger == 4'd8)) begin
         ddrphy_freeze <= 1'd1;
     end
-    if ((ddrphy_counter == 5'd16)) begin
+    if ((ddrphy_trigger == 5'd16)) begin
         ddrphy_stop1 <= 1'd1;
     end
-    if ((ddrphy_counter == 5'd24)) begin
+    if ((ddrphy_trigger == 5'd24)) begin
         ddrphy_reset1 <= 1'd1;
     end
-    if ((ddrphy_counter == 6'd32)) begin
+    if ((ddrphy_trigger == 6'd32)) begin
         ddrphy_reset1 <= 1'd0;
     end
-    if ((ddrphy_counter == 6'd40)) begin
+    if ((ddrphy_trigger == 6'd40)) begin
         ddrphy_stop1 <= 1'd0;
     end
-    if ((ddrphy_counter == 6'd48)) begin
+    if ((ddrphy_trigger == 6'd48)) begin
         ddrphy_freeze <= 1'd0;
     end
-    if ((ddrphy_counter == 6'd56)) begin
+    if ((ddrphy_trigger == 6'd56)) begin
         ddrphy_pause1 <= 1'd1;
     end
-    if ((ddrphy_counter == 7'd64)) begin
+    if ((ddrphy_trigger == 7'd64)) begin
         ddrphy_update <= 1'd1;
     end
-    if ((ddrphy_counter == 7'd72)) begin
+    if ((ddrphy_trigger == 7'd72)) begin
         ddrphy_update <= 1'd0;
     end
-    if ((ddrphy_counter == 7'd80)) begin
+    if ((ddrphy_trigger == 7'd80)) begin
         ddrphy_pause1 <= 1'd0;
     end
-    if ((ddrphy_counter == 7'd80)) begin
-        ddrphy_counter <= 1'd0;
+    if ((ddrphy_trigger == 7'd80)) begin
+        ddrphy_trigger <= 1'd0;
     end else begin
-        if ((ddrphy_counter != 1'd0)) begin
-            ddrphy_counter <= (ddrphy_counter + 1'd1);
+        if ((ddrphy_trigger != 1'd0)) begin
+            ddrphy_trigger <= (ddrphy_trigger + 1'd1);
         end else begin
             if (ddrphy_new_lock) begin
-                ddrphy_counter <= 1'd1;
+                ddrphy_trigger <= 1'd1;
             end
         end
     end
@@ -9711,10 +10082,10 @@ always @(posedge init_clk) begin
         ddrphy_pause1 <= 1'd0;
         ddrphy_reset1 <= 1'd0;
         ddrphy_lock_d <= 1'd0;
-        ddrphy_counter <= 7'd0;
+        ddrphy_trigger <= 7'd0;
     end
-    regs0 <= ddrphy_lock0;
-    regs1 <= regs0;
+    multiregimpl0 <= ddrphy_lock0;
+    multiregimpl1 <= multiregimpl0;
 end
 
 always @(posedge por_clk) begin
@@ -10094,21 +10465,21 @@ always @(posedge sys_clk) begin
     litedramcore_cmd_payload_ras <= 1'd0;
     litedramcore_cmd_payload_we <= 1'd0;
     litedramcore_sequencer_done1 <= 1'd0;
-    if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
+    if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_trigger == 1'd0))) begin
         litedramcore_cmd_payload_a <= 11'd1024;
         litedramcore_cmd_payload_ba <= 1'd0;
         litedramcore_cmd_payload_cas <= 1'd0;
         litedramcore_cmd_payload_ras <= 1'd1;
         litedramcore_cmd_payload_we <= 1'd1;
     end
-    if ((litedramcore_sequencer_counter == 2'd2)) begin
+    if ((litedramcore_sequencer_trigger == 2'd2)) begin
         litedramcore_cmd_payload_a <= 11'd1024;
         litedramcore_cmd_payload_ba <= 1'd0;
         litedramcore_cmd_payload_cas <= 1'd1;
         litedramcore_cmd_payload_ras <= 1'd1;
         litedramcore_cmd_payload_we <= 1'd0;
     end
-    if ((litedramcore_sequencer_counter == 7'd106)) begin
+    if ((litedramcore_sequencer_trigger == 7'd106)) begin
         litedramcore_cmd_payload_a <= 1'd0;
         litedramcore_cmd_payload_ba <= 1'd0;
         litedramcore_cmd_payload_cas <= 1'd0;
@@ -10116,14 +10487,14 @@ always @(posedge sys_clk) begin
         litedramcore_cmd_payload_we <= 1'd0;
         litedramcore_sequencer_done1 <= 1'd1;
     end
-    if ((litedramcore_sequencer_counter == 7'd106)) begin
-        litedramcore_sequencer_counter <= 1'd0;
+    if ((litedramcore_sequencer_trigger == 7'd106)) begin
+        litedramcore_sequencer_trigger <= 1'd0;
     end else begin
-        if ((litedramcore_sequencer_counter != 1'd0)) begin
-            litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
+        if ((litedramcore_sequencer_trigger != 1'd0)) begin
+            litedramcore_sequencer_trigger <= (litedramcore_sequencer_trigger + 1'd1);
         end else begin
             if (litedramcore_sequencer_start1) begin
-                litedramcore_sequencer_counter <= 1'd1;
+                litedramcore_sequencer_trigger <= 1'd1;
             end
         end
     end
@@ -10133,21 +10504,21 @@ always @(posedge sys_clk) begin
         litedramcore_zqcs_timer_count1 <= 26'd47999999;
     end
     litedramcore_zqcs_executer_done <= 1'd0;
-    if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
+    if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_trigger == 1'd0))) begin
         litedramcore_cmd_payload_a <= 11'd1024;
         litedramcore_cmd_payload_ba <= 1'd0;
         litedramcore_cmd_payload_cas <= 1'd0;
         litedramcore_cmd_payload_ras <= 1'd1;
         litedramcore_cmd_payload_we <= 1'd1;
     end
-    if ((litedramcore_zqcs_executer_counter == 2'd2)) begin
+    if ((litedramcore_zqcs_executer_trigger == 2'd2)) begin
         litedramcore_cmd_payload_a <= 1'd0;
         litedramcore_cmd_payload_ba <= 1'd0;
         litedramcore_cmd_payload_cas <= 1'd0;
         litedramcore_cmd_payload_ras <= 1'd0;
         litedramcore_cmd_payload_we <= 1'd1;
     end
-    if ((litedramcore_zqcs_executer_counter == 6'd34)) begin
+    if ((litedramcore_zqcs_executer_trigger == 6'd34)) begin
         litedramcore_cmd_payload_a <= 1'd0;
         litedramcore_cmd_payload_ba <= 1'd0;
         litedramcore_cmd_payload_cas <= 1'd0;
@@ -10155,18 +10526,18 @@ always @(posedge sys_clk) begin
         litedramcore_cmd_payload_we <= 1'd0;
         litedramcore_zqcs_executer_done <= 1'd1;
     end
-    if ((litedramcore_zqcs_executer_counter == 6'd34)) begin
-        litedramcore_zqcs_executer_counter <= 1'd0;
+    if ((litedramcore_zqcs_executer_trigger == 6'd34)) begin
+        litedramcore_zqcs_executer_trigger <= 1'd0;
     end else begin
-        if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
-            litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
+        if ((litedramcore_zqcs_executer_trigger != 1'd0)) begin
+            litedramcore_zqcs_executer_trigger <= (litedramcore_zqcs_executer_trigger + 1'd1);
         end else begin
             if (litedramcore_zqcs_executer_start) begin
-                litedramcore_zqcs_executer_counter <= 1'd1;
+                litedramcore_zqcs_executer_trigger <= 1'd1;
             end
         end
     end
-    litedramcore_litedramcore_refresher_state <= litedramcore_litedramcore_refresher_next_state;
+    litedramcore_refresher_state <= litedramcore_refresher_next_state;
     if (litedramcore_bankmachine0_row_close) begin
         litedramcore_bankmachine0_row_opened <= 1'd0;
     end else begin
@@ -10242,7 +10613,7 @@ always @(posedge sys_clk) begin
             end
         end
     end
-    litedramcore_litedramcore_bankmachine0_state <= litedramcore_litedramcore_bankmachine0_next_state;
+    litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
     if (litedramcore_bankmachine1_row_close) begin
         litedramcore_bankmachine1_row_opened <= 1'd0;
     end else begin
@@ -10318,7 +10689,7 @@ always @(posedge sys_clk) begin
             end
         end
     end
-    litedramcore_litedramcore_bankmachine1_state <= litedramcore_litedramcore_bankmachine1_next_state;
+    litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
     if (litedramcore_bankmachine2_row_close) begin
         litedramcore_bankmachine2_row_opened <= 1'd0;
     end else begin
@@ -10394,7 +10765,7 @@ always @(posedge sys_clk) begin
             end
         end
     end
-    litedramcore_litedramcore_bankmachine2_state <= litedramcore_litedramcore_bankmachine2_next_state;
+    litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
     if (litedramcore_bankmachine3_row_close) begin
         litedramcore_bankmachine3_row_opened <= 1'd0;
     end else begin
@@ -10470,7 +10841,7 @@ always @(posedge sys_clk) begin
             end
         end
     end
-    litedramcore_litedramcore_bankmachine3_state <= litedramcore_litedramcore_bankmachine3_next_state;
+    litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
     if (litedramcore_bankmachine4_row_close) begin
         litedramcore_bankmachine4_row_opened <= 1'd0;
     end else begin
@@ -10546,7 +10917,7 @@ always @(posedge sys_clk) begin
             end
         end
     end
-    litedramcore_litedramcore_bankmachine4_state <= litedramcore_litedramcore_bankmachine4_next_state;
+    litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
     if (litedramcore_bankmachine5_row_close) begin
         litedramcore_bankmachine5_row_opened <= 1'd0;
     end else begin
@@ -10622,7 +10993,7 @@ always @(posedge sys_clk) begin
             end
         end
     end
-    litedramcore_litedramcore_bankmachine5_state <= litedramcore_litedramcore_bankmachine5_next_state;
+    litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
     if (litedramcore_bankmachine6_row_close) begin
         litedramcore_bankmachine6_row_opened <= 1'd0;
     end else begin
@@ -10698,7 +11069,7 @@ always @(posedge sys_clk) begin
             end
         end
     end
-    litedramcore_litedramcore_bankmachine6_state <= litedramcore_litedramcore_bankmachine6_next_state;
+    litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
     if (litedramcore_bankmachine7_row_close) begin
         litedramcore_bankmachine7_row_opened <= 1'd0;
     end else begin
@@ -10774,7 +11145,7 @@ always @(posedge sys_clk) begin
             end
         end
     end
-    litedramcore_litedramcore_bankmachine7_state <= litedramcore_litedramcore_bankmachine7_next_state;
+    litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
     if ((~litedramcore_en0)) begin
         litedramcore_time0 <= 5'd31;
     end else begin
@@ -11262,21 +11633,21 @@ always @(posedge sys_clk) begin
         endcase
     end
     litedramcore_dfi_p0_cs_n <= 1'd0;
-    litedramcore_dfi_p0_bank <= array_muxed0;
-    litedramcore_dfi_p0_address <= array_muxed1;
-    litedramcore_dfi_p0_cas_n <= (~array_muxed2);
-    litedramcore_dfi_p0_ras_n <= (~array_muxed3);
-    litedramcore_dfi_p0_we_n <= (~array_muxed4);
-    litedramcore_dfi_p0_rddata_en <= array_muxed5;
-    litedramcore_dfi_p0_wrdata_en <= array_muxed6;
+    litedramcore_dfi_p0_bank <= self0;
+    litedramcore_dfi_p0_address <= self1;
+    litedramcore_dfi_p0_cas_n <= (~self2);
+    litedramcore_dfi_p0_ras_n <= (~self3);
+    litedramcore_dfi_p0_we_n <= (~self4);
+    litedramcore_dfi_p0_rddata_en <= self5;
+    litedramcore_dfi_p0_wrdata_en <= self6;
     litedramcore_dfi_p1_cs_n <= 1'd0;
-    litedramcore_dfi_p1_bank <= array_muxed7;
-    litedramcore_dfi_p1_address <= array_muxed8;
-    litedramcore_dfi_p1_cas_n <= (~array_muxed9);
-    litedramcore_dfi_p1_ras_n <= (~array_muxed10);
-    litedramcore_dfi_p1_we_n <= (~array_muxed11);
-    litedramcore_dfi_p1_rddata_en <= array_muxed12;
-    litedramcore_dfi_p1_wrdata_en <= array_muxed13;
+    litedramcore_dfi_p1_bank <= self7;
+    litedramcore_dfi_p1_address <= self8;
+    litedramcore_dfi_p1_cas_n <= (~self9);
+    litedramcore_dfi_p1_ras_n <= (~self10);
+    litedramcore_dfi_p1_we_n <= (~self11);
+    litedramcore_dfi_p1_rddata_en <= self12;
+    litedramcore_dfi_p1_wrdata_en <= self13;
     if (litedramcore_trrdcon_valid) begin
         litedramcore_trrdcon_count <= 1'd1;
         if (1'd0) begin
@@ -11330,34 +11701,34 @@ always @(posedge sys_clk) begin
             end
         end
     end
-    litedramcore_litedramcore_multiplexer_state <= litedramcore_litedramcore_multiplexer_next_state;
-    litedramcore_litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
-    litedramcore_litedramcore_new_master_wdata_ready1 <= litedramcore_litedramcore_new_master_wdata_ready0;
-    litedramcore_litedramcore_new_master_wdata_ready2 <= litedramcore_litedramcore_new_master_wdata_ready1;
-    litedramcore_litedramcore_new_master_wdata_ready3 <= litedramcore_litedramcore_new_master_wdata_ready2;
-    litedramcore_litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
-    litedramcore_litedramcore_new_master_rdata_valid1 <= litedramcore_litedramcore_new_master_rdata_valid0;
-    litedramcore_litedramcore_new_master_rdata_valid2 <= litedramcore_litedramcore_new_master_rdata_valid1;
-    litedramcore_litedramcore_new_master_rdata_valid3 <= litedramcore_litedramcore_new_master_rdata_valid2;
-    litedramcore_litedramcore_new_master_rdata_valid4 <= litedramcore_litedramcore_new_master_rdata_valid3;
-    litedramcore_litedramcore_new_master_rdata_valid5 <= litedramcore_litedramcore_new_master_rdata_valid4;
-    litedramcore_litedramcore_new_master_rdata_valid6 <= litedramcore_litedramcore_new_master_rdata_valid5;
-    litedramcore_litedramcore_new_master_rdata_valid7 <= litedramcore_litedramcore_new_master_rdata_valid6;
-    litedramcore_litedramcore_new_master_rdata_valid8 <= litedramcore_litedramcore_new_master_rdata_valid7;
-    litedramcore_litedramcore_new_master_rdata_valid9 <= litedramcore_litedramcore_new_master_rdata_valid8;
-    litedramcore_litedramcore_new_master_rdata_valid10 <= litedramcore_litedramcore_new_master_rdata_valid9;
-    litedramcore_litedramcore_new_master_rdata_valid11 <= litedramcore_litedramcore_new_master_rdata_valid10;
-    litedramcore_litedramcore_new_master_rdata_valid12 <= litedramcore_litedramcore_new_master_rdata_valid11;
-    litedramcore_litedramcore_new_master_rdata_valid13 <= litedramcore_litedramcore_new_master_rdata_valid12;
-    litedramcore_state <= litedramcore_next_state;
-    if (litedramcore_dat_w_next_value_ce0) begin
-        litedramcore_dat_w <= litedramcore_dat_w_next_value0;
-    end
-    if (litedramcore_adr_next_value_ce1) begin
-        litedramcore_adr <= litedramcore_adr_next_value1;
-    end
-    if (litedramcore_we_next_value_ce2) begin
-        litedramcore_we <= litedramcore_we_next_value2;
+    litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
+    litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
+    litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
+    litedramcore_new_master_wdata_ready2 <= litedramcore_new_master_wdata_ready1;
+    litedramcore_new_master_wdata_ready3 <= litedramcore_new_master_wdata_ready2;
+    litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
+    litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
+    litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
+    litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
+    litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
+    litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
+    litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
+    litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
+    litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
+    litedramcore_new_master_rdata_valid9 <= litedramcore_new_master_rdata_valid8;
+    litedramcore_new_master_rdata_valid10 <= litedramcore_new_master_rdata_valid9;
+    litedramcore_new_master_rdata_valid11 <= litedramcore_new_master_rdata_valid10;
+    litedramcore_new_master_rdata_valid12 <= litedramcore_new_master_rdata_valid11;
+    litedramcore_new_master_rdata_valid13 <= litedramcore_new_master_rdata_valid12;
+    state <= next_state;
+    if (interface1_dat_w_next_value_ce0) begin
+        interface1_dat_w <= interface1_dat_w_next_value0;
+    end
+    if (interface1_adr_next_value_ce1) begin
+        interface1_adr <= interface1_adr_next_value1;
+    end
+    if (interface1_we_next_value_ce2) begin
+        interface1_we <= interface1_we_next_value2;
     end
     interface0_bank_bus_dat_r <= 1'd0;
     if (csrbank0_sel) begin
@@ -11470,7 +11841,7 @@ always @(posedge sys_clk) begin
     end
     litedramcore_re <= csrbank2_dfii_control0_re;
     if (csrbank2_dfii_pi0_command0_re) begin
-        litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
+        litedramcore_phaseinjector0_command_storage[7:0] <= csrbank2_dfii_pi0_command0_r;
     end
     litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
     if (csrbank2_dfii_pi0_address0_re) begin
@@ -11490,7 +11861,7 @@ always @(posedge sys_clk) begin
     litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
     litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata0_re;
     if (csrbank2_dfii_pi1_command0_re) begin
-        litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
+        litedramcore_phaseinjector1_command_storage[7:0] <= csrbank2_dfii_pi1_command0_r;
     end
     litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
     if (csrbank2_dfii_pi1_address0_re) begin
@@ -11608,14 +11979,14 @@ always @(posedge sys_clk) begin
         ddrphy_wrdata_en_tappeddelayline6 <= 1'd0;
         litedramcore_storage <= 4'd1;
         litedramcore_re <= 1'd0;
-        litedramcore_phaseinjector0_command_storage <= 6'd0;
+        litedramcore_phaseinjector0_command_storage <= 8'd0;
         litedramcore_phaseinjector0_command_re <= 1'd0;
         litedramcore_phaseinjector0_address_re <= 1'd0;
         litedramcore_phaseinjector0_baddress_re <= 1'd0;
         litedramcore_phaseinjector0_wrdata_re <= 1'd0;
         litedramcore_phaseinjector0_rddata_status <= 64'd0;
         litedramcore_phaseinjector0_rddata_re <= 1'd0;
-        litedramcore_phaseinjector1_command_storage <= 6'd0;
+        litedramcore_phaseinjector1_command_storage <= 8'd0;
         litedramcore_phaseinjector1_command_re <= 1'd0;
         litedramcore_phaseinjector1_address_re <= 1'd0;
         litedramcore_phaseinjector1_baddress_re <= 1'd0;
@@ -11647,11 +12018,11 @@ always @(posedge sys_clk) begin
         litedramcore_postponer_req_o <= 1'd0;
         litedramcore_postponer_count <= 1'd0;
         litedramcore_sequencer_done1 <= 1'd0;
-        litedramcore_sequencer_counter <= 7'd0;
+        litedramcore_sequencer_trigger <= 7'd0;
         litedramcore_sequencer_count <= 1'd0;
         litedramcore_zqcs_timer_count1 <= 26'd47999999;
         litedramcore_zqcs_executer_done <= 1'd0;
-        litedramcore_zqcs_executer_counter <= 6'd0;
+        litedramcore_zqcs_executer_trigger <= 6'd0;
         litedramcore_bankmachine0_level <= 5'd0;
         litedramcore_bankmachine0_produce <= 4'd0;
         litedramcore_bankmachine0_consume <= 4'd0;
@@ -11780,36 +12151,36 @@ always @(posedge sys_clk) begin
         init_done_re <= 1'd0;
         init_error_storage <= 1'd0;
         init_error_re <= 1'd0;
-        litedramcore_we <= 1'd0;
-        litedramcore_litedramcore_refresher_state <= 2'd0;
-        litedramcore_litedramcore_bankmachine0_state <= 3'd0;
-        litedramcore_litedramcore_bankmachine1_state <= 3'd0;
-        litedramcore_litedramcore_bankmachine2_state <= 3'd0;
-        litedramcore_litedramcore_bankmachine3_state <= 3'd0;
-        litedramcore_litedramcore_bankmachine4_state <= 3'd0;
-        litedramcore_litedramcore_bankmachine5_state <= 3'd0;
-        litedramcore_litedramcore_bankmachine6_state <= 3'd0;
-        litedramcore_litedramcore_bankmachine7_state <= 3'd0;
-        litedramcore_litedramcore_multiplexer_state <= 4'd0;
-        litedramcore_litedramcore_new_master_wdata_ready0 <= 1'd0;
-        litedramcore_litedramcore_new_master_wdata_ready1 <= 1'd0;
-        litedramcore_litedramcore_new_master_wdata_ready2 <= 1'd0;
-        litedramcore_litedramcore_new_master_wdata_ready3 <= 1'd0;
-        litedramcore_litedramcore_new_master_rdata_valid0 <= 1'd0;
-        litedramcore_litedramcore_new_master_rdata_valid1 <= 1'd0;
-        litedramcore_litedramcore_new_master_rdata_valid2 <= 1'd0;
-        litedramcore_litedramcore_new_master_rdata_valid3 <= 1'd0;
-        litedramcore_litedramcore_new_master_rdata_valid4 <= 1'd0;
-        litedramcore_litedramcore_new_master_rdata_valid5 <= 1'd0;
-        litedramcore_litedramcore_new_master_rdata_valid6 <= 1'd0;
-        litedramcore_litedramcore_new_master_rdata_valid7 <= 1'd0;
-        litedramcore_litedramcore_new_master_rdata_valid8 <= 1'd0;
-        litedramcore_litedramcore_new_master_rdata_valid9 <= 1'd0;
-        litedramcore_litedramcore_new_master_rdata_valid10 <= 1'd0;
-        litedramcore_litedramcore_new_master_rdata_valid11 <= 1'd0;
-        litedramcore_litedramcore_new_master_rdata_valid12 <= 1'd0;
-        litedramcore_litedramcore_new_master_rdata_valid13 <= 1'd0;
-        litedramcore_state <= 2'd0;
+        interface1_we <= 1'd0;
+        litedramcore_refresher_state <= 2'd0;
+        litedramcore_bankmachine0_state <= 3'd0;
+        litedramcore_bankmachine1_state <= 3'd0;
+        litedramcore_bankmachine2_state <= 3'd0;
+        litedramcore_bankmachine3_state <= 3'd0;
+        litedramcore_bankmachine4_state <= 3'd0;
+        litedramcore_bankmachine5_state <= 3'd0;
+        litedramcore_bankmachine6_state <= 3'd0;
+        litedramcore_bankmachine7_state <= 3'd0;
+        litedramcore_multiplexer_state <= 4'd0;
+        litedramcore_new_master_wdata_ready0 <= 1'd0;
+        litedramcore_new_master_wdata_ready1 <= 1'd0;
+        litedramcore_new_master_wdata_ready2 <= 1'd0;
+        litedramcore_new_master_wdata_ready3 <= 1'd0;
+        litedramcore_new_master_rdata_valid0 <= 1'd0;
+        litedramcore_new_master_rdata_valid1 <= 1'd0;
+        litedramcore_new_master_rdata_valid2 <= 1'd0;
+        litedramcore_new_master_rdata_valid3 <= 1'd0;
+        litedramcore_new_master_rdata_valid4 <= 1'd0;
+        litedramcore_new_master_rdata_valid5 <= 1'd0;
+        litedramcore_new_master_rdata_valid6 <= 1'd0;
+        litedramcore_new_master_rdata_valid7 <= 1'd0;
+        litedramcore_new_master_rdata_valid8 <= 1'd0;
+        litedramcore_new_master_rdata_valid9 <= 1'd0;
+        litedramcore_new_master_rdata_valid10 <= 1'd0;
+        litedramcore_new_master_rdata_valid11 <= 1'd0;
+        litedramcore_new_master_rdata_valid12 <= 1'd0;
+        litedramcore_new_master_rdata_valid13 <= 1'd0;
+        state <= 2'd0;
     end
 end
 
@@ -11818,1394 +12189,2207 @@ end
 // Specialized Logic
 //------------------------------------------------------------------------------
 
+//------------------------------------------------------------------------------
+// Instance ECLKBRIDGECS of ECLKBRIDGECS Module.
+//------------------------------------------------------------------------------
 ECLKBRIDGECS ECLKBRIDGECS(
-	.CLK0(sys2x_i_clk),
-	.SEL(1'd0),
-	.ECSOUT(crg_sys2x_clk_ecsout)
+	// Inputs.
+	.CLK0   (sys2x_i_clk),
+	.SEL    (1'd0),
+
+	// Outputs.
+	.ECSOUT (crg_sys2x_clk_ecsout)
 );
 
+//------------------------------------------------------------------------------
+// Instance ECLKSYNCB of ECLKSYNCB Module.
+//------------------------------------------------------------------------------
 ECLKSYNCB ECLKSYNCB(
-	.ECLKI(crg_sys2x_clk_ecsout),
-	.STOP(crg_stop),
-	.ECLKO(sys2x_clk)
+	// Inputs.
+	.ECLKI (crg_sys2x_clk_ecsout),
+	.STOP  (crg_stop),
+
+	// Outputs.
+	.ECLKO (sys2x_clk)
 );
 
+//------------------------------------------------------------------------------
+// Instance CLKDIVF of CLKDIVF Module.
+//------------------------------------------------------------------------------
 CLKDIVF #(
-	.DIV("2.0")
+	// Parameters.
+	.DIV ("2.0")
 ) CLKDIVF (
-	.ALIGNWD(1'd0),
-	.CLKI(sys2x_clk),
-	.RST(crg_reset0),
-	.CDIVX(sys_clk)
+	// Inputs.
+	.ALIGNWD (1'd0),
+	.CLKI    (sys2x_clk),
+	.RST     (crg_reset0),
+
+	// Outputs.
+	.CDIVX   (sys_clk)
 );
 
+//------------------------------------------------------------------------------
+// Instance DDRDLLA of DDRDLLA Module.
+//------------------------------------------------------------------------------
 DDRDLLA DDRDLLA(
-	.CLK(sys2x_clk),
-	.FREEZE(ddrphy_freeze),
-	.RST(init_rst),
-	.UDDCNTLN((~ddrphy_update)),
-	.DDRDEL(ddrphy_delay1),
-	.LOCK(ddrphy_lock0)
+	// Inputs.
+	.CLK      (sys2x_clk),
+	.FREEZE   (ddrphy_freeze),
+	.RST      (init_rst),
+	.UDDCNTLN ((~ddrphy_update)),
+
+	// Outputs.
+	.DDRDEL   (ddrphy_delay1),
+	.LOCK     (ddrphy_lock0)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F(
-	.D0(1'd0),
-	.D1(1'd1),
-	.D2(1'd0),
-	.D3(1'd1),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f0)
+	// Inputs.
+	.D0   (1'd0),
+	.D1   (1'd1),
+	.D2   (1'd0),
+	.D3   (1'd1),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f0)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG (
-	.A(ddrphy_pad_oddrx2f0),
-	.Z(ddram_clk_p)
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f0),
+
+	// Outputs.
+	.Z (ddram_clk_p)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F_1 of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F_1(
-	.D0(ddrphy_dfi_p0_reset_n),
-	.D1(ddrphy_dfi_p0_reset_n),
-	.D2(ddrphy_dfi_p1_reset_n),
-	.D3(ddrphy_dfi_p1_reset_n),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f1)
+	// Inputs.
+	.D0   (ddrphy_dfi_p0_reset_n),
+	.D1   (ddrphy_dfi_p0_reset_n),
+	.D2   (ddrphy_dfi_p1_reset_n),
+	.D3   (ddrphy_dfi_p1_reset_n),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f1)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_1 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG_1 (
-	.A(ddrphy_pad_oddrx2f1),
-	.Z(ddram_reset_n)
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f1),
+
+	// Outputs.
+	.Z (ddram_reset_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F_2 of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F_2(
-	.D0(ddrphy_dfi_p0_cs_n),
-	.D1(ddrphy_dfi_p0_cs_n),
-	.D2(ddrphy_dfi_p1_cs_n),
-	.D3(ddrphy_dfi_p1_cs_n),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f2)
+	// Inputs.
+	.D0   (ddrphy_dfi_p0_cs_n),
+	.D1   (ddrphy_dfi_p0_cs_n),
+	.D2   (ddrphy_dfi_p1_cs_n),
+	.D3   (ddrphy_dfi_p1_cs_n),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f2)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_2 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG_2 (
-	.A(ddrphy_pad_oddrx2f2),
-	.Z(ddram_cs_n)
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f2),
+
+	// Outputs.
+	.Z (ddram_cs_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F_3 of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F_3(
-	.D0(ddrphy_dfi_p0_address[0]),
-	.D1(ddrphy_dfi_p0_address[0]),
-	.D2(ddrphy_dfi_p1_address[0]),
-	.D3(ddrphy_dfi_p1_address[0]),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f3)
+	// Inputs.
+	.D0   (ddrphy_dfi_p0_address[0]),
+	.D1   (ddrphy_dfi_p0_address[0]),
+	.D2   (ddrphy_dfi_p1_address[0]),
+	.D3   (ddrphy_dfi_p1_address[0]),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f3)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_3 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG_3 (
-	.A(ddrphy_pad_oddrx2f3),
-	.Z(ddram_a[0])
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f3),
+
+	// Outputs.
+	.Z (ddram_a[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F_4 of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F_4(
-	.D0(ddrphy_dfi_p0_address[1]),
-	.D1(ddrphy_dfi_p0_address[1]),
-	.D2(ddrphy_dfi_p1_address[1]),
-	.D3(ddrphy_dfi_p1_address[1]),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f4)
+	// Inputs.
+	.D0   (ddrphy_dfi_p0_address[1]),
+	.D1   (ddrphy_dfi_p0_address[1]),
+	.D2   (ddrphy_dfi_p1_address[1]),
+	.D3   (ddrphy_dfi_p1_address[1]),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f4)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_4 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG_4 (
-	.A(ddrphy_pad_oddrx2f4),
-	.Z(ddram_a[1])
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f4),
+
+	// Outputs.
+	.Z (ddram_a[1])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F_5 of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F_5(
-	.D0(ddrphy_dfi_p0_address[2]),
-	.D1(ddrphy_dfi_p0_address[2]),
-	.D2(ddrphy_dfi_p1_address[2]),
-	.D3(ddrphy_dfi_p1_address[2]),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f5)
+	// Inputs.
+	.D0   (ddrphy_dfi_p0_address[2]),
+	.D1   (ddrphy_dfi_p0_address[2]),
+	.D2   (ddrphy_dfi_p1_address[2]),
+	.D3   (ddrphy_dfi_p1_address[2]),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f5)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_5 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG_5 (
-	.A(ddrphy_pad_oddrx2f5),
-	.Z(ddram_a[2])
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f5),
+
+	// Outputs.
+	.Z (ddram_a[2])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F_6 of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F_6(
-	.D0(ddrphy_dfi_p0_address[3]),
-	.D1(ddrphy_dfi_p0_address[3]),
-	.D2(ddrphy_dfi_p1_address[3]),
-	.D3(ddrphy_dfi_p1_address[3]),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f6)
+	// Inputs.
+	.D0   (ddrphy_dfi_p0_address[3]),
+	.D1   (ddrphy_dfi_p0_address[3]),
+	.D2   (ddrphy_dfi_p1_address[3]),
+	.D3   (ddrphy_dfi_p1_address[3]),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f6)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_6 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG_6 (
-	.A(ddrphy_pad_oddrx2f6),
-	.Z(ddram_a[3])
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f6),
+
+	// Outputs.
+	.Z (ddram_a[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F_7 of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F_7(
-	.D0(ddrphy_dfi_p0_address[4]),
-	.D1(ddrphy_dfi_p0_address[4]),
-	.D2(ddrphy_dfi_p1_address[4]),
-	.D3(ddrphy_dfi_p1_address[4]),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f7)
+	// Inputs.
+	.D0   (ddrphy_dfi_p0_address[4]),
+	.D1   (ddrphy_dfi_p0_address[4]),
+	.D2   (ddrphy_dfi_p1_address[4]),
+	.D3   (ddrphy_dfi_p1_address[4]),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f7)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_7 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG_7 (
-	.A(ddrphy_pad_oddrx2f7),
-	.Z(ddram_a[4])
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f7),
+
+	// Outputs.
+	.Z (ddram_a[4])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F_8 of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F_8(
-	.D0(ddrphy_dfi_p0_address[5]),
-	.D1(ddrphy_dfi_p0_address[5]),
-	.D2(ddrphy_dfi_p1_address[5]),
-	.D3(ddrphy_dfi_p1_address[5]),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f8)
+	// Inputs.
+	.D0   (ddrphy_dfi_p0_address[5]),
+	.D1   (ddrphy_dfi_p0_address[5]),
+	.D2   (ddrphy_dfi_p1_address[5]),
+	.D3   (ddrphy_dfi_p1_address[5]),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f8)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_8 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG_8 (
-	.A(ddrphy_pad_oddrx2f8),
-	.Z(ddram_a[5])
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f8),
+
+	// Outputs.
+	.Z (ddram_a[5])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F_9 of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F_9(
-	.D0(ddrphy_dfi_p0_address[6]),
-	.D1(ddrphy_dfi_p0_address[6]),
-	.D2(ddrphy_dfi_p1_address[6]),
-	.D3(ddrphy_dfi_p1_address[6]),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f9)
+	// Inputs.
+	.D0   (ddrphy_dfi_p0_address[6]),
+	.D1   (ddrphy_dfi_p0_address[6]),
+	.D2   (ddrphy_dfi_p1_address[6]),
+	.D3   (ddrphy_dfi_p1_address[6]),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f9)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_9 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG_9 (
-	.A(ddrphy_pad_oddrx2f9),
-	.Z(ddram_a[6])
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f9),
+
+	// Outputs.
+	.Z (ddram_a[6])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F_10 of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F_10(
-	.D0(ddrphy_dfi_p0_address[7]),
-	.D1(ddrphy_dfi_p0_address[7]),
-	.D2(ddrphy_dfi_p1_address[7]),
-	.D3(ddrphy_dfi_p1_address[7]),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f10)
+	// Inputs.
+	.D0   (ddrphy_dfi_p0_address[7]),
+	.D1   (ddrphy_dfi_p0_address[7]),
+	.D2   (ddrphy_dfi_p1_address[7]),
+	.D3   (ddrphy_dfi_p1_address[7]),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f10)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_10 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG_10 (
-	.A(ddrphy_pad_oddrx2f10),
-	.Z(ddram_a[7])
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f10),
+
+	// Outputs.
+	.Z (ddram_a[7])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F_11 of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F_11(
-	.D0(ddrphy_dfi_p0_address[8]),
-	.D1(ddrphy_dfi_p0_address[8]),
-	.D2(ddrphy_dfi_p1_address[8]),
-	.D3(ddrphy_dfi_p1_address[8]),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f11)
+	// Inputs.
+	.D0   (ddrphy_dfi_p0_address[8]),
+	.D1   (ddrphy_dfi_p0_address[8]),
+	.D2   (ddrphy_dfi_p1_address[8]),
+	.D3   (ddrphy_dfi_p1_address[8]),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f11)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_11 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG_11 (
-	.A(ddrphy_pad_oddrx2f11),
-	.Z(ddram_a[8])
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f11),
+
+	// Outputs.
+	.Z (ddram_a[8])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F_12 of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F_12(
-	.D0(ddrphy_dfi_p0_address[9]),
-	.D1(ddrphy_dfi_p0_address[9]),
-	.D2(ddrphy_dfi_p1_address[9]),
-	.D3(ddrphy_dfi_p1_address[9]),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f12)
+	// Inputs.
+	.D0   (ddrphy_dfi_p0_address[9]),
+	.D1   (ddrphy_dfi_p0_address[9]),
+	.D2   (ddrphy_dfi_p1_address[9]),
+	.D3   (ddrphy_dfi_p1_address[9]),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f12)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_12 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG_12 (
-	.A(ddrphy_pad_oddrx2f12),
-	.Z(ddram_a[9])
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f12),
+
+	// Outputs.
+	.Z (ddram_a[9])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F_13 of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F_13(
-	.D0(ddrphy_dfi_p0_address[10]),
-	.D1(ddrphy_dfi_p0_address[10]),
-	.D2(ddrphy_dfi_p1_address[10]),
-	.D3(ddrphy_dfi_p1_address[10]),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f13)
+	// Inputs.
+	.D0   (ddrphy_dfi_p0_address[10]),
+	.D1   (ddrphy_dfi_p0_address[10]),
+	.D2   (ddrphy_dfi_p1_address[10]),
+	.D3   (ddrphy_dfi_p1_address[10]),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f13)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_13 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG_13 (
-	.A(ddrphy_pad_oddrx2f13),
-	.Z(ddram_a[10])
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f13),
+
+	// Outputs.
+	.Z (ddram_a[10])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F_14 of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F_14(
-	.D0(ddrphy_dfi_p0_address[11]),
-	.D1(ddrphy_dfi_p0_address[11]),
-	.D2(ddrphy_dfi_p1_address[11]),
-	.D3(ddrphy_dfi_p1_address[11]),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f14)
+	// Inputs.
+	.D0   (ddrphy_dfi_p0_address[11]),
+	.D1   (ddrphy_dfi_p0_address[11]),
+	.D2   (ddrphy_dfi_p1_address[11]),
+	.D3   (ddrphy_dfi_p1_address[11]),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f14)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_14 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG_14 (
-	.A(ddrphy_pad_oddrx2f14),
-	.Z(ddram_a[11])
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f14),
+
+	// Outputs.
+	.Z (ddram_a[11])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F_15 of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F_15(
-	.D0(ddrphy_dfi_p0_address[12]),
-	.D1(ddrphy_dfi_p0_address[12]),
-	.D2(ddrphy_dfi_p1_address[12]),
-	.D3(ddrphy_dfi_p1_address[12]),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f15)
+	// Inputs.
+	.D0   (ddrphy_dfi_p0_address[12]),
+	.D1   (ddrphy_dfi_p0_address[12]),
+	.D2   (ddrphy_dfi_p1_address[12]),
+	.D3   (ddrphy_dfi_p1_address[12]),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f15)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_15 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG_15 (
-	.A(ddrphy_pad_oddrx2f15),
-	.Z(ddram_a[12])
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f15),
+
+	// Outputs.
+	.Z (ddram_a[12])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F_16 of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F_16(
-	.D0(ddrphy_dfi_p0_address[13]),
-	.D1(ddrphy_dfi_p0_address[13]),
-	.D2(ddrphy_dfi_p1_address[13]),
-	.D3(ddrphy_dfi_p1_address[13]),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f16)
+	// Inputs.
+	.D0   (ddrphy_dfi_p0_address[13]),
+	.D1   (ddrphy_dfi_p0_address[13]),
+	.D2   (ddrphy_dfi_p1_address[13]),
+	.D3   (ddrphy_dfi_p1_address[13]),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f16)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_16 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG_16 (
-	.A(ddrphy_pad_oddrx2f16),
-	.Z(ddram_a[13])
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f16),
+
+	// Outputs.
+	.Z (ddram_a[13])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F_17 of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F_17(
-	.D0(ddrphy_dfi_p0_address[14]),
-	.D1(ddrphy_dfi_p0_address[14]),
-	.D2(ddrphy_dfi_p1_address[14]),
-	.D3(ddrphy_dfi_p1_address[14]),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f17)
+	// Inputs.
+	.D0   (ddrphy_dfi_p0_address[14]),
+	.D1   (ddrphy_dfi_p0_address[14]),
+	.D2   (ddrphy_dfi_p1_address[14]),
+	.D3   (ddrphy_dfi_p1_address[14]),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f17)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_17 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG_17 (
-	.A(ddrphy_pad_oddrx2f17),
-	.Z(ddram_a[14])
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f17),
+
+	// Outputs.
+	.Z (ddram_a[14])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F_18 of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F_18(
-	.D0(ddrphy_dfi_p0_bank[0]),
-	.D1(ddrphy_dfi_p0_bank[0]),
-	.D2(ddrphy_dfi_p1_bank[0]),
-	.D3(ddrphy_dfi_p1_bank[0]),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f18)
+	// Inputs.
+	.D0   (ddrphy_dfi_p0_bank[0]),
+	.D1   (ddrphy_dfi_p0_bank[0]),
+	.D2   (ddrphy_dfi_p1_bank[0]),
+	.D3   (ddrphy_dfi_p1_bank[0]),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f18)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_18 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG_18 (
-	.A(ddrphy_pad_oddrx2f18),
-	.Z(ddram_ba[0])
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f18),
+
+	// Outputs.
+	.Z (ddram_ba[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F_19 of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F_19(
-	.D0(ddrphy_dfi_p0_bank[1]),
-	.D1(ddrphy_dfi_p0_bank[1]),
-	.D2(ddrphy_dfi_p1_bank[1]),
-	.D3(ddrphy_dfi_p1_bank[1]),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f19)
+	// Inputs.
+	.D0   (ddrphy_dfi_p0_bank[1]),
+	.D1   (ddrphy_dfi_p0_bank[1]),
+	.D2   (ddrphy_dfi_p1_bank[1]),
+	.D3   (ddrphy_dfi_p1_bank[1]),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f19)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_19 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG_19 (
-	.A(ddrphy_pad_oddrx2f19),
-	.Z(ddram_ba[1])
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f19),
+
+	// Outputs.
+	.Z (ddram_ba[1])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F_20 of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F_20(
-	.D0(ddrphy_dfi_p0_bank[2]),
-	.D1(ddrphy_dfi_p0_bank[2]),
-	.D2(ddrphy_dfi_p1_bank[2]),
-	.D3(ddrphy_dfi_p1_bank[2]),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f20)
+	// Inputs.
+	.D0   (ddrphy_dfi_p0_bank[2]),
+	.D1   (ddrphy_dfi_p0_bank[2]),
+	.D2   (ddrphy_dfi_p1_bank[2]),
+	.D3   (ddrphy_dfi_p1_bank[2]),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f20)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_20 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG_20 (
-	.A(ddrphy_pad_oddrx2f20),
-	.Z(ddram_ba[2])
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f20),
+
+	// Outputs.
+	.Z (ddram_ba[2])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F_21 of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F_21(
-	.D0(ddrphy_dfi_p0_ras_n),
-	.D1(ddrphy_dfi_p0_ras_n),
-	.D2(ddrphy_dfi_p1_ras_n),
-	.D3(ddrphy_dfi_p1_ras_n),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f21)
+	// Inputs.
+	.D0   (ddrphy_dfi_p0_ras_n),
+	.D1   (ddrphy_dfi_p0_ras_n),
+	.D2   (ddrphy_dfi_p1_ras_n),
+	.D3   (ddrphy_dfi_p1_ras_n),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f21)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_21 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG_21 (
-	.A(ddrphy_pad_oddrx2f21),
-	.Z(ddram_ras_n)
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f21),
+
+	// Outputs.
+	.Z (ddram_ras_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F_22 of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F_22(
-	.D0(ddrphy_dfi_p0_cas_n),
-	.D1(ddrphy_dfi_p0_cas_n),
-	.D2(ddrphy_dfi_p1_cas_n),
-	.D3(ddrphy_dfi_p1_cas_n),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f22)
+	// Inputs.
+	.D0   (ddrphy_dfi_p0_cas_n),
+	.D1   (ddrphy_dfi_p0_cas_n),
+	.D2   (ddrphy_dfi_p1_cas_n),
+	.D3   (ddrphy_dfi_p1_cas_n),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f22)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_22 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG_22 (
-	.A(ddrphy_pad_oddrx2f22),
-	.Z(ddram_cas_n)
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f22),
+
+	// Outputs.
+	.Z (ddram_cas_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F_23 of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F_23(
-	.D0(ddrphy_dfi_p0_we_n),
-	.D1(ddrphy_dfi_p0_we_n),
-	.D2(ddrphy_dfi_p1_we_n),
-	.D3(ddrphy_dfi_p1_we_n),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f23)
+	// Inputs.
+	.D0   (ddrphy_dfi_p0_we_n),
+	.D1   (ddrphy_dfi_p0_we_n),
+	.D2   (ddrphy_dfi_p1_we_n),
+	.D3   (ddrphy_dfi_p1_we_n),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f23)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_23 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG_23 (
-	.A(ddrphy_pad_oddrx2f23),
-	.Z(ddram_we_n)
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f23),
+
+	// Outputs.
+	.Z (ddram_we_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F_24 of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F_24(
-	.D0(ddrphy_dfi_p0_cke),
-	.D1(ddrphy_dfi_p0_cke),
-	.D2(ddrphy_dfi_p1_cke),
-	.D3(ddrphy_dfi_p1_cke),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f24)
+	// Inputs.
+	.D0   (ddrphy_dfi_p0_cke),
+	.D1   (ddrphy_dfi_p0_cke),
+	.D2   (ddrphy_dfi_p1_cke),
+	.D3   (ddrphy_dfi_p1_cke),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f24)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_24 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG_24 (
-	.A(ddrphy_pad_oddrx2f24),
-	.Z(ddram_cke)
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f24),
+
+	// Outputs.
+	.Z (ddram_cke)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2F_25 of ODDRX2F Module.
+//------------------------------------------------------------------------------
 ODDRX2F ODDRX2F_25(
-	.D0(ddrphy_dfi_p0_odt),
-	.D1(ddrphy_dfi_p0_odt),
-	.D2(ddrphy_dfi_p1_odt),
-	.D3(ddrphy_dfi_p1_odt),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_pad_oddrx2f25)
+	// Inputs.
+	.D0   (ddrphy_dfi_p0_odt),
+	.D1   (ddrphy_dfi_p0_odt),
+	.D2   (ddrphy_dfi_p1_odt),
+	.D3   (ddrphy_dfi_p1_odt),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_pad_oddrx2f25)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_25 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_VALUE(7'd100)
+	// Parameters.
+	.DEL_VALUE (7'd100)
 ) DELAYG_25 (
-	.A(ddrphy_pad_oddrx2f25),
-	.Z(ddram_odt)
+	// Inputs.
+	.A (ddrphy_pad_oddrx2f25),
+
+	// Outputs.
+	.Z (ddram_odt)
 );
 
+//------------------------------------------------------------------------------
+// Instance DQSBUFM of DQSBUFM Module.
+//------------------------------------------------------------------------------
 DQSBUFM #(
-	.DQS_LI_DEL_ADJ("MINUS"),
-	.DQS_LI_DEL_VAL(1'd1),
-	.DQS_LO_DEL_ADJ("MINUS"),
-	.DQS_LO_DEL_VAL(3'd4)
+	// Parameters.
+	.DQS_LI_DEL_ADJ ("MINUS"),
+	.DQS_LI_DEL_VAL (1'd1),
+	.DQS_LO_DEL_ADJ ("MINUS"),
+	.DQS_LO_DEL_VAL (3'd4)
 ) DQSBUFM (
-	.DDRDEL(ddrphy_delay0),
-	.DQSI(ddrphy_dqs_i0),
-	.ECLK(sys2x_clk),
-	.PAUSE((ddrphy_pause0 | ddrphy_dly_sel_storage[0])),
-	.RDDIRECTION(1'd1),
-	.RDLOADN(1'd0),
-	.RDMOVE(1'd0),
-	.READ0(ddrphy_dqs_re),
-	.READ1(ddrphy_dqs_re),
-	.READCLKSEL0(ddrphy_rdly0[0]),
-	.READCLKSEL1(ddrphy_rdly0[1]),
-	.READCLKSEL2(ddrphy_rdly0[2]),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.WRDIRECTION(1'd1),
-	.WRLOADN(1'd0),
-	.WRMOVE(1'd0),
-	.BURSTDET(ddrphy_burstdet0),
-	.DATAVALID(ddrphy_datavalid[0]),
-	.DQSR90(ddrphy_dqsr900),
-	.DQSW(ddrphy_dqsw0),
-	.DQSW270(ddrphy_dqsw2700),
-	.RDPNTR0(ddrphy_rdpntr0[0]),
-	.RDPNTR1(ddrphy_rdpntr0[1]),
-	.RDPNTR2(ddrphy_rdpntr0[2]),
-	.WRPNTR0(ddrphy_wrpntr0[0]),
-	.WRPNTR1(ddrphy_wrpntr0[1]),
-	.WRPNTR2(ddrphy_wrpntr0[2])
+	// Inputs.
+	.DDRDEL      (ddrphy_delay0),
+	.DQSI        (ddrphy_dqs_i0),
+	.ECLK        (sys2x_clk),
+	.PAUSE       ((ddrphy_pause0 | ddrphy_dly_sel_storage[0])),
+	.RDDIRECTION (1'd1),
+	.RDLOADN     (1'd0),
+	.RDMOVE      (1'd0),
+	.READ0       (ddrphy_dqs_re),
+	.READ1       (ddrphy_dqs_re),
+	.READCLKSEL0 (ddrphy_rdly0[0]),
+	.READCLKSEL1 (ddrphy_rdly0[1]),
+	.READCLKSEL2 (ddrphy_rdly0[2]),
+	.RST         (sys_rst),
+	.SCLK        (sys_clk),
+	.WRDIRECTION (1'd1),
+	.WRLOADN     (1'd0),
+	.WRMOVE      (1'd0),
+
+	// Outputs.
+	.BURSTDET    (ddrphy_burstdet0),
+	.DATAVALID   (ddrphy_datavalid[0]),
+	.DQSR90      (ddrphy_dqsr900),
+	.DQSW        (ddrphy_dqsw0),
+	.DQSW270     (ddrphy_dqsw2700),
+	.RDPNTR0     (ddrphy_rdpntr0[0]),
+	.RDPNTR1     (ddrphy_rdpntr0[1]),
+	.RDPNTR2     (ddrphy_rdpntr0[2]),
+	.WRPNTR0     (ddrphy_wrpntr0[0]),
+	.WRPNTR1     (ddrphy_wrpntr0[1]),
+	.WRPNTR2     (ddrphy_wrpntr0[2])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2DQSB of ODDRX2DQSB Module.
+//------------------------------------------------------------------------------
 ODDRX2DQSB ODDRX2DQSB(
-	.D0(1'd0),
-	.D1(1'd1),
-	.D2(1'd0),
-	.D3(1'd1),
-	.DQSW(ddrphy_dqsw0),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_dqs0)
+	// Inputs.
+	.D0   (1'd0),
+	.D1   (1'd1),
+	.D2   (1'd0),
+	.D3   (1'd1),
+	.DQSW (ddrphy_dqsw0),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_dqs0)
 );
 
+//------------------------------------------------------------------------------
+// Instance TSHX2DQSA of TSHX2DQSA Module.
+//------------------------------------------------------------------------------
 TSHX2DQSA TSHX2DQSA(
-	.DQSW(ddrphy_dqsw0),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.T0((~(ddrphy_dqs_oe | ddrphy_dqs_postamble))),
-	.T1((~(ddrphy_dqs_oe | ddrphy_dqs_preamble))),
-	.Q(ddrphy_dqs_oe_n0)
+	// Inputs.
+	.DQSW (ddrphy_dqsw0),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+	.T0   ((~(ddrphy_dqs_oe | ddrphy_dqs_postamble))),
+	.T1   ((~(ddrphy_dqs_oe | ddrphy_dqs_preamble))),
+
+	// Outputs.
+	.Q    (ddrphy_dqs_oe_n0)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2DQA of ODDRX2DQA Module.
+//------------------------------------------------------------------------------
 ODDRX2DQA ODDRX2DQA(
-	.D0(ddrphy_dm_o_data_muxed0[0]),
-	.D1(ddrphy_dm_o_data_muxed0[1]),
-	.D2(ddrphy_dm_o_data_muxed0[2]),
-	.D3(ddrphy_dm_o_data_muxed0[3]),
-	.DQSW270(ddrphy_dqsw2700),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddram_dm[0])
+	// Inputs.
+	.D0      (ddrphy_dm_o_data_muxed0[0]),
+	.D1      (ddrphy_dm_o_data_muxed0[1]),
+	.D2      (ddrphy_dm_o_data_muxed0[2]),
+	.D3      (ddrphy_dm_o_data_muxed0[3]),
+	.DQSW270 (ddrphy_dqsw2700),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+
+	// Outputs.
+	.Q       (ddram_dm[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2DQA_1 of ODDRX2DQA Module.
+//------------------------------------------------------------------------------
 ODDRX2DQA ODDRX2DQA_1(
-	.D0(ddrphy_dq_o_data_muxed0[0]),
-	.D1(ddrphy_dq_o_data_muxed0[1]),
-	.D2(ddrphy_dq_o_data_muxed0[2]),
-	.D3(ddrphy_dq_o_data_muxed0[3]),
-	.DQSW270(ddrphy_dqsw2700),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_dq_o0)
+	// Inputs.
+	.D0      (ddrphy_dq_o_data_muxed0[0]),
+	.D1      (ddrphy_dq_o_data_muxed0[1]),
+	.D2      (ddrphy_dq_o_data_muxed0[2]),
+	.D3      (ddrphy_dq_o_data_muxed0[3]),
+	.DQSW270 (ddrphy_dqsw2700),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+
+	// Outputs.
+	.Q       (ddrphy_dq_o0)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_26 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_MODE("DQS_ALIGNED_X2")
+	// Parameters.
+	.DEL_MODE ("DQS_ALIGNED_X2")
 ) DELAYG_26 (
-	.A(ddrphy_dq_i0),
-	.Z(ddrphy_dq_i_delayed0)
+	// Inputs.
+	.A (ddrphy_dq_i0),
+
+	// Outputs.
+	.Z (ddrphy_dq_i_delayed0)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDDRX2DQA of IDDRX2DQA Module.
+//------------------------------------------------------------------------------
 IDDRX2DQA IDDRX2DQA(
-	.D(ddrphy_dq_i_delayed0),
-	.DQSR90(ddrphy_dqsr900),
-	.ECLK(sys2x_clk),
-	.RDPNTR0(ddrphy_rdpntr0[0]),
-	.RDPNTR1(ddrphy_rdpntr0[1]),
-	.RDPNTR2(ddrphy_rdpntr0[2]),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.WRPNTR0(ddrphy_wrpntr0[0]),
-	.WRPNTR1(ddrphy_wrpntr0[1]),
-	.WRPNTR2(ddrphy_wrpntr0[2]),
-	.Q0(ddrphy_bitslip0_i[0]),
-	.Q1(ddrphy_bitslip0_i[1]),
-	.Q2(ddrphy_bitslip0_i[2]),
-	.Q3(ddrphy_bitslip0_i[3])
+	// Inputs.
+	.D       (ddrphy_dq_i_delayed0),
+	.DQSR90  (ddrphy_dqsr900),
+	.ECLK    (sys2x_clk),
+	.RDPNTR0 (ddrphy_rdpntr0[0]),
+	.RDPNTR1 (ddrphy_rdpntr0[1]),
+	.RDPNTR2 (ddrphy_rdpntr0[2]),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.WRPNTR0 (ddrphy_wrpntr0[0]),
+	.WRPNTR1 (ddrphy_wrpntr0[1]),
+	.WRPNTR2 (ddrphy_wrpntr0[2]),
+
+	// Outputs.
+	.Q0      (ddrphy_bitslip0_i[0]),
+	.Q1      (ddrphy_bitslip0_i[1]),
+	.Q2      (ddrphy_bitslip0_i[2]),
+	.Q3      (ddrphy_bitslip0_i[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance TSHX2DQA of TSHX2DQA Module.
+//------------------------------------------------------------------------------
 TSHX2DQA TSHX2DQA(
-	.DQSW270(ddrphy_dqsw2700),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.T0((~ddrphy_dq_oe)),
-	.T1((~ddrphy_dq_oe)),
-	.Q(ddrphy_dq_oe_n0)
+	// Inputs.
+	.DQSW270 (ddrphy_dqsw2700),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.T0      ((~ddrphy_dq_oe)),
+	.T1      ((~ddrphy_dq_oe)),
+
+	// Outputs.
+	.Q       (ddrphy_dq_oe_n0)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2DQA_2 of ODDRX2DQA Module.
+//------------------------------------------------------------------------------
 ODDRX2DQA ODDRX2DQA_2(
-	.D0(ddrphy_dq_o_data_muxed1[0]),
-	.D1(ddrphy_dq_o_data_muxed1[1]),
-	.D2(ddrphy_dq_o_data_muxed1[2]),
-	.D3(ddrphy_dq_o_data_muxed1[3]),
-	.DQSW270(ddrphy_dqsw2700),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_dq_o1)
+	// Inputs.
+	.D0      (ddrphy_dq_o_data_muxed1[0]),
+	.D1      (ddrphy_dq_o_data_muxed1[1]),
+	.D2      (ddrphy_dq_o_data_muxed1[2]),
+	.D3      (ddrphy_dq_o_data_muxed1[3]),
+	.DQSW270 (ddrphy_dqsw2700),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+
+	// Outputs.
+	.Q       (ddrphy_dq_o1)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_27 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_MODE("DQS_ALIGNED_X2")
+	// Parameters.
+	.DEL_MODE ("DQS_ALIGNED_X2")
 ) DELAYG_27 (
-	.A(ddrphy_dq_i1),
-	.Z(ddrphy_dq_i_delayed1)
+	// Inputs.
+	.A (ddrphy_dq_i1),
+
+	// Outputs.
+	.Z (ddrphy_dq_i_delayed1)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDDRX2DQA_1 of IDDRX2DQA Module.
+//------------------------------------------------------------------------------
 IDDRX2DQA IDDRX2DQA_1(
-	.D(ddrphy_dq_i_delayed1),
-	.DQSR90(ddrphy_dqsr900),
-	.ECLK(sys2x_clk),
-	.RDPNTR0(ddrphy_rdpntr0[0]),
-	.RDPNTR1(ddrphy_rdpntr0[1]),
-	.RDPNTR2(ddrphy_rdpntr0[2]),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.WRPNTR0(ddrphy_wrpntr0[0]),
-	.WRPNTR1(ddrphy_wrpntr0[1]),
-	.WRPNTR2(ddrphy_wrpntr0[2]),
-	.Q0(ddrphy_bitslip1_i[0]),
-	.Q1(ddrphy_bitslip1_i[1]),
-	.Q2(ddrphy_bitslip1_i[2]),
-	.Q3(ddrphy_bitslip1_i[3])
+	// Inputs.
+	.D       (ddrphy_dq_i_delayed1),
+	.DQSR90  (ddrphy_dqsr900),
+	.ECLK    (sys2x_clk),
+	.RDPNTR0 (ddrphy_rdpntr0[0]),
+	.RDPNTR1 (ddrphy_rdpntr0[1]),
+	.RDPNTR2 (ddrphy_rdpntr0[2]),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.WRPNTR0 (ddrphy_wrpntr0[0]),
+	.WRPNTR1 (ddrphy_wrpntr0[1]),
+	.WRPNTR2 (ddrphy_wrpntr0[2]),
+
+	// Outputs.
+	.Q0      (ddrphy_bitslip1_i[0]),
+	.Q1      (ddrphy_bitslip1_i[1]),
+	.Q2      (ddrphy_bitslip1_i[2]),
+	.Q3      (ddrphy_bitslip1_i[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance TSHX2DQA_1 of TSHX2DQA Module.
+//------------------------------------------------------------------------------
 TSHX2DQA TSHX2DQA_1(
-	.DQSW270(ddrphy_dqsw2700),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.T0((~ddrphy_dq_oe)),
-	.T1((~ddrphy_dq_oe)),
-	.Q(ddrphy_dq_oe_n1)
+	// Inputs.
+	.DQSW270 (ddrphy_dqsw2700),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.T0      ((~ddrphy_dq_oe)),
+	.T1      ((~ddrphy_dq_oe)),
+
+	// Outputs.
+	.Q       (ddrphy_dq_oe_n1)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2DQA_3 of ODDRX2DQA Module.
+//------------------------------------------------------------------------------
 ODDRX2DQA ODDRX2DQA_3(
-	.D0(ddrphy_dq_o_data_muxed2[0]),
-	.D1(ddrphy_dq_o_data_muxed2[1]),
-	.D2(ddrphy_dq_o_data_muxed2[2]),
-	.D3(ddrphy_dq_o_data_muxed2[3]),
-	.DQSW270(ddrphy_dqsw2700),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_dq_o2)
+	// Inputs.
+	.D0      (ddrphy_dq_o_data_muxed2[0]),
+	.D1      (ddrphy_dq_o_data_muxed2[1]),
+	.D2      (ddrphy_dq_o_data_muxed2[2]),
+	.D3      (ddrphy_dq_o_data_muxed2[3]),
+	.DQSW270 (ddrphy_dqsw2700),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+
+	// Outputs.
+	.Q       (ddrphy_dq_o2)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_28 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_MODE("DQS_ALIGNED_X2")
+	// Parameters.
+	.DEL_MODE ("DQS_ALIGNED_X2")
 ) DELAYG_28 (
-	.A(ddrphy_dq_i2),
-	.Z(ddrphy_dq_i_delayed2)
+	// Inputs.
+	.A (ddrphy_dq_i2),
+
+	// Outputs.
+	.Z (ddrphy_dq_i_delayed2)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDDRX2DQA_2 of IDDRX2DQA Module.
+//------------------------------------------------------------------------------
 IDDRX2DQA IDDRX2DQA_2(
-	.D(ddrphy_dq_i_delayed2),
-	.DQSR90(ddrphy_dqsr900),
-	.ECLK(sys2x_clk),
-	.RDPNTR0(ddrphy_rdpntr0[0]),
-	.RDPNTR1(ddrphy_rdpntr0[1]),
-	.RDPNTR2(ddrphy_rdpntr0[2]),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.WRPNTR0(ddrphy_wrpntr0[0]),
-	.WRPNTR1(ddrphy_wrpntr0[1]),
-	.WRPNTR2(ddrphy_wrpntr0[2]),
-	.Q0(ddrphy_bitslip2_i[0]),
-	.Q1(ddrphy_bitslip2_i[1]),
-	.Q2(ddrphy_bitslip2_i[2]),
-	.Q3(ddrphy_bitslip2_i[3])
+	// Inputs.
+	.D       (ddrphy_dq_i_delayed2),
+	.DQSR90  (ddrphy_dqsr900),
+	.ECLK    (sys2x_clk),
+	.RDPNTR0 (ddrphy_rdpntr0[0]),
+	.RDPNTR1 (ddrphy_rdpntr0[1]),
+	.RDPNTR2 (ddrphy_rdpntr0[2]),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.WRPNTR0 (ddrphy_wrpntr0[0]),
+	.WRPNTR1 (ddrphy_wrpntr0[1]),
+	.WRPNTR2 (ddrphy_wrpntr0[2]),
+
+	// Outputs.
+	.Q0      (ddrphy_bitslip2_i[0]),
+	.Q1      (ddrphy_bitslip2_i[1]),
+	.Q2      (ddrphy_bitslip2_i[2]),
+	.Q3      (ddrphy_bitslip2_i[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance TSHX2DQA_2 of TSHX2DQA Module.
+//------------------------------------------------------------------------------
 TSHX2DQA TSHX2DQA_2(
-	.DQSW270(ddrphy_dqsw2700),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.T0((~ddrphy_dq_oe)),
-	.T1((~ddrphy_dq_oe)),
-	.Q(ddrphy_dq_oe_n2)
+	// Inputs.
+	.DQSW270 (ddrphy_dqsw2700),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.T0      ((~ddrphy_dq_oe)),
+	.T1      ((~ddrphy_dq_oe)),
+
+	// Outputs.
+	.Q       (ddrphy_dq_oe_n2)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2DQA_4 of ODDRX2DQA Module.
+//------------------------------------------------------------------------------
 ODDRX2DQA ODDRX2DQA_4(
-	.D0(ddrphy_dq_o_data_muxed3[0]),
-	.D1(ddrphy_dq_o_data_muxed3[1]),
-	.D2(ddrphy_dq_o_data_muxed3[2]),
-	.D3(ddrphy_dq_o_data_muxed3[3]),
-	.DQSW270(ddrphy_dqsw2700),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_dq_o3)
+	// Inputs.
+	.D0      (ddrphy_dq_o_data_muxed3[0]),
+	.D1      (ddrphy_dq_o_data_muxed3[1]),
+	.D2      (ddrphy_dq_o_data_muxed3[2]),
+	.D3      (ddrphy_dq_o_data_muxed3[3]),
+	.DQSW270 (ddrphy_dqsw2700),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+
+	// Outputs.
+	.Q       (ddrphy_dq_o3)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_29 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_MODE("DQS_ALIGNED_X2")
+	// Parameters.
+	.DEL_MODE ("DQS_ALIGNED_X2")
 ) DELAYG_29 (
-	.A(ddrphy_dq_i3),
-	.Z(ddrphy_dq_i_delayed3)
+	// Inputs.
+	.A (ddrphy_dq_i3),
+
+	// Outputs.
+	.Z (ddrphy_dq_i_delayed3)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDDRX2DQA_3 of IDDRX2DQA Module.
+//------------------------------------------------------------------------------
 IDDRX2DQA IDDRX2DQA_3(
-	.D(ddrphy_dq_i_delayed3),
-	.DQSR90(ddrphy_dqsr900),
-	.ECLK(sys2x_clk),
-	.RDPNTR0(ddrphy_rdpntr0[0]),
-	.RDPNTR1(ddrphy_rdpntr0[1]),
-	.RDPNTR2(ddrphy_rdpntr0[2]),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.WRPNTR0(ddrphy_wrpntr0[0]),
-	.WRPNTR1(ddrphy_wrpntr0[1]),
-	.WRPNTR2(ddrphy_wrpntr0[2]),
-	.Q0(ddrphy_bitslip3_i[0]),
-	.Q1(ddrphy_bitslip3_i[1]),
-	.Q2(ddrphy_bitslip3_i[2]),
-	.Q3(ddrphy_bitslip3_i[3])
+	// Inputs.
+	.D       (ddrphy_dq_i_delayed3),
+	.DQSR90  (ddrphy_dqsr900),
+	.ECLK    (sys2x_clk),
+	.RDPNTR0 (ddrphy_rdpntr0[0]),
+	.RDPNTR1 (ddrphy_rdpntr0[1]),
+	.RDPNTR2 (ddrphy_rdpntr0[2]),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.WRPNTR0 (ddrphy_wrpntr0[0]),
+	.WRPNTR1 (ddrphy_wrpntr0[1]),
+	.WRPNTR2 (ddrphy_wrpntr0[2]),
+
+	// Outputs.
+	.Q0      (ddrphy_bitslip3_i[0]),
+	.Q1      (ddrphy_bitslip3_i[1]),
+	.Q2      (ddrphy_bitslip3_i[2]),
+	.Q3      (ddrphy_bitslip3_i[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance TSHX2DQA_3 of TSHX2DQA Module.
+//------------------------------------------------------------------------------
 TSHX2DQA TSHX2DQA_3(
-	.DQSW270(ddrphy_dqsw2700),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.T0((~ddrphy_dq_oe)),
-	.T1((~ddrphy_dq_oe)),
-	.Q(ddrphy_dq_oe_n3)
+	// Inputs.
+	.DQSW270 (ddrphy_dqsw2700),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.T0      ((~ddrphy_dq_oe)),
+	.T1      ((~ddrphy_dq_oe)),
+
+	// Outputs.
+	.Q       (ddrphy_dq_oe_n3)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2DQA_5 of ODDRX2DQA Module.
+//------------------------------------------------------------------------------
 ODDRX2DQA ODDRX2DQA_5(
-	.D0(ddrphy_dq_o_data_muxed4[0]),
-	.D1(ddrphy_dq_o_data_muxed4[1]),
-	.D2(ddrphy_dq_o_data_muxed4[2]),
-	.D3(ddrphy_dq_o_data_muxed4[3]),
-	.DQSW270(ddrphy_dqsw2700),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_dq_o4)
+	// Inputs.
+	.D0      (ddrphy_dq_o_data_muxed4[0]),
+	.D1      (ddrphy_dq_o_data_muxed4[1]),
+	.D2      (ddrphy_dq_o_data_muxed4[2]),
+	.D3      (ddrphy_dq_o_data_muxed4[3]),
+	.DQSW270 (ddrphy_dqsw2700),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+
+	// Outputs.
+	.Q       (ddrphy_dq_o4)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_30 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_MODE("DQS_ALIGNED_X2")
+	// Parameters.
+	.DEL_MODE ("DQS_ALIGNED_X2")
 ) DELAYG_30 (
-	.A(ddrphy_dq_i4),
-	.Z(ddrphy_dq_i_delayed4)
+	// Inputs.
+	.A (ddrphy_dq_i4),
+
+	// Outputs.
+	.Z (ddrphy_dq_i_delayed4)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDDRX2DQA_4 of IDDRX2DQA Module.
+//------------------------------------------------------------------------------
 IDDRX2DQA IDDRX2DQA_4(
-	.D(ddrphy_dq_i_delayed4),
-	.DQSR90(ddrphy_dqsr900),
-	.ECLK(sys2x_clk),
-	.RDPNTR0(ddrphy_rdpntr0[0]),
-	.RDPNTR1(ddrphy_rdpntr0[1]),
-	.RDPNTR2(ddrphy_rdpntr0[2]),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.WRPNTR0(ddrphy_wrpntr0[0]),
-	.WRPNTR1(ddrphy_wrpntr0[1]),
-	.WRPNTR2(ddrphy_wrpntr0[2]),
-	.Q0(ddrphy_bitslip4_i[0]),
-	.Q1(ddrphy_bitslip4_i[1]),
-	.Q2(ddrphy_bitslip4_i[2]),
-	.Q3(ddrphy_bitslip4_i[3])
+	// Inputs.
+	.D       (ddrphy_dq_i_delayed4),
+	.DQSR90  (ddrphy_dqsr900),
+	.ECLK    (sys2x_clk),
+	.RDPNTR0 (ddrphy_rdpntr0[0]),
+	.RDPNTR1 (ddrphy_rdpntr0[1]),
+	.RDPNTR2 (ddrphy_rdpntr0[2]),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.WRPNTR0 (ddrphy_wrpntr0[0]),
+	.WRPNTR1 (ddrphy_wrpntr0[1]),
+	.WRPNTR2 (ddrphy_wrpntr0[2]),
+
+	// Outputs.
+	.Q0      (ddrphy_bitslip4_i[0]),
+	.Q1      (ddrphy_bitslip4_i[1]),
+	.Q2      (ddrphy_bitslip4_i[2]),
+	.Q3      (ddrphy_bitslip4_i[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance TSHX2DQA_4 of TSHX2DQA Module.
+//------------------------------------------------------------------------------
 TSHX2DQA TSHX2DQA_4(
-	.DQSW270(ddrphy_dqsw2700),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.T0((~ddrphy_dq_oe)),
-	.T1((~ddrphy_dq_oe)),
-	.Q(ddrphy_dq_oe_n4)
+	// Inputs.
+	.DQSW270 (ddrphy_dqsw2700),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.T0      ((~ddrphy_dq_oe)),
+	.T1      ((~ddrphy_dq_oe)),
+
+	// Outputs.
+	.Q       (ddrphy_dq_oe_n4)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2DQA_6 of ODDRX2DQA Module.
+//------------------------------------------------------------------------------
 ODDRX2DQA ODDRX2DQA_6(
-	.D0(ddrphy_dq_o_data_muxed5[0]),
-	.D1(ddrphy_dq_o_data_muxed5[1]),
-	.D2(ddrphy_dq_o_data_muxed5[2]),
-	.D3(ddrphy_dq_o_data_muxed5[3]),
-	.DQSW270(ddrphy_dqsw2700),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_dq_o5)
+	// Inputs.
+	.D0      (ddrphy_dq_o_data_muxed5[0]),
+	.D1      (ddrphy_dq_o_data_muxed5[1]),
+	.D2      (ddrphy_dq_o_data_muxed5[2]),
+	.D3      (ddrphy_dq_o_data_muxed5[3]),
+	.DQSW270 (ddrphy_dqsw2700),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+
+	// Outputs.
+	.Q       (ddrphy_dq_o5)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_31 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_MODE("DQS_ALIGNED_X2")
+	// Parameters.
+	.DEL_MODE ("DQS_ALIGNED_X2")
 ) DELAYG_31 (
-	.A(ddrphy_dq_i5),
-	.Z(ddrphy_dq_i_delayed5)
+	// Inputs.
+	.A (ddrphy_dq_i5),
+
+	// Outputs.
+	.Z (ddrphy_dq_i_delayed5)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDDRX2DQA_5 of IDDRX2DQA Module.
+//------------------------------------------------------------------------------
 IDDRX2DQA IDDRX2DQA_5(
-	.D(ddrphy_dq_i_delayed5),
-	.DQSR90(ddrphy_dqsr900),
-	.ECLK(sys2x_clk),
-	.RDPNTR0(ddrphy_rdpntr0[0]),
-	.RDPNTR1(ddrphy_rdpntr0[1]),
-	.RDPNTR2(ddrphy_rdpntr0[2]),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.WRPNTR0(ddrphy_wrpntr0[0]),
-	.WRPNTR1(ddrphy_wrpntr0[1]),
-	.WRPNTR2(ddrphy_wrpntr0[2]),
-	.Q0(ddrphy_bitslip5_i[0]),
-	.Q1(ddrphy_bitslip5_i[1]),
-	.Q2(ddrphy_bitslip5_i[2]),
-	.Q3(ddrphy_bitslip5_i[3])
+	// Inputs.
+	.D       (ddrphy_dq_i_delayed5),
+	.DQSR90  (ddrphy_dqsr900),
+	.ECLK    (sys2x_clk),
+	.RDPNTR0 (ddrphy_rdpntr0[0]),
+	.RDPNTR1 (ddrphy_rdpntr0[1]),
+	.RDPNTR2 (ddrphy_rdpntr0[2]),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.WRPNTR0 (ddrphy_wrpntr0[0]),
+	.WRPNTR1 (ddrphy_wrpntr0[1]),
+	.WRPNTR2 (ddrphy_wrpntr0[2]),
+
+	// Outputs.
+	.Q0      (ddrphy_bitslip5_i[0]),
+	.Q1      (ddrphy_bitslip5_i[1]),
+	.Q2      (ddrphy_bitslip5_i[2]),
+	.Q3      (ddrphy_bitslip5_i[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance TSHX2DQA_5 of TSHX2DQA Module.
+//------------------------------------------------------------------------------
 TSHX2DQA TSHX2DQA_5(
-	.DQSW270(ddrphy_dqsw2700),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.T0((~ddrphy_dq_oe)),
-	.T1((~ddrphy_dq_oe)),
-	.Q(ddrphy_dq_oe_n5)
+	// Inputs.
+	.DQSW270 (ddrphy_dqsw2700),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.T0      ((~ddrphy_dq_oe)),
+	.T1      ((~ddrphy_dq_oe)),
+
+	// Outputs.
+	.Q       (ddrphy_dq_oe_n5)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2DQA_7 of ODDRX2DQA Module.
+//------------------------------------------------------------------------------
 ODDRX2DQA ODDRX2DQA_7(
-	.D0(ddrphy_dq_o_data_muxed6[0]),
-	.D1(ddrphy_dq_o_data_muxed6[1]),
-	.D2(ddrphy_dq_o_data_muxed6[2]),
-	.D3(ddrphy_dq_o_data_muxed6[3]),
-	.DQSW270(ddrphy_dqsw2700),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_dq_o6)
+	// Inputs.
+	.D0      (ddrphy_dq_o_data_muxed6[0]),
+	.D1      (ddrphy_dq_o_data_muxed6[1]),
+	.D2      (ddrphy_dq_o_data_muxed6[2]),
+	.D3      (ddrphy_dq_o_data_muxed6[3]),
+	.DQSW270 (ddrphy_dqsw2700),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+
+	// Outputs.
+	.Q       (ddrphy_dq_o6)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_32 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_MODE("DQS_ALIGNED_X2")
+	// Parameters.
+	.DEL_MODE ("DQS_ALIGNED_X2")
 ) DELAYG_32 (
-	.A(ddrphy_dq_i6),
-	.Z(ddrphy_dq_i_delayed6)
+	// Inputs.
+	.A (ddrphy_dq_i6),
+
+	// Outputs.
+	.Z (ddrphy_dq_i_delayed6)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDDRX2DQA_6 of IDDRX2DQA Module.
+//------------------------------------------------------------------------------
 IDDRX2DQA IDDRX2DQA_6(
-	.D(ddrphy_dq_i_delayed6),
-	.DQSR90(ddrphy_dqsr900),
-	.ECLK(sys2x_clk),
-	.RDPNTR0(ddrphy_rdpntr0[0]),
-	.RDPNTR1(ddrphy_rdpntr0[1]),
-	.RDPNTR2(ddrphy_rdpntr0[2]),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.WRPNTR0(ddrphy_wrpntr0[0]),
-	.WRPNTR1(ddrphy_wrpntr0[1]),
-	.WRPNTR2(ddrphy_wrpntr0[2]),
-	.Q0(ddrphy_bitslip6_i[0]),
-	.Q1(ddrphy_bitslip6_i[1]),
-	.Q2(ddrphy_bitslip6_i[2]),
-	.Q3(ddrphy_bitslip6_i[3])
+	// Inputs.
+	.D       (ddrphy_dq_i_delayed6),
+	.DQSR90  (ddrphy_dqsr900),
+	.ECLK    (sys2x_clk),
+	.RDPNTR0 (ddrphy_rdpntr0[0]),
+	.RDPNTR1 (ddrphy_rdpntr0[1]),
+	.RDPNTR2 (ddrphy_rdpntr0[2]),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.WRPNTR0 (ddrphy_wrpntr0[0]),
+	.WRPNTR1 (ddrphy_wrpntr0[1]),
+	.WRPNTR2 (ddrphy_wrpntr0[2]),
+
+	// Outputs.
+	.Q0      (ddrphy_bitslip6_i[0]),
+	.Q1      (ddrphy_bitslip6_i[1]),
+	.Q2      (ddrphy_bitslip6_i[2]),
+	.Q3      (ddrphy_bitslip6_i[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance TSHX2DQA_6 of TSHX2DQA Module.
+//------------------------------------------------------------------------------
 TSHX2DQA TSHX2DQA_6(
-	.DQSW270(ddrphy_dqsw2700),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.T0((~ddrphy_dq_oe)),
-	.T1((~ddrphy_dq_oe)),
-	.Q(ddrphy_dq_oe_n6)
+	// Inputs.
+	.DQSW270 (ddrphy_dqsw2700),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.T0      ((~ddrphy_dq_oe)),
+	.T1      ((~ddrphy_dq_oe)),
+
+	// Outputs.
+	.Q       (ddrphy_dq_oe_n6)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2DQA_8 of ODDRX2DQA Module.
+//------------------------------------------------------------------------------
 ODDRX2DQA ODDRX2DQA_8(
-	.D0(ddrphy_dq_o_data_muxed7[0]),
-	.D1(ddrphy_dq_o_data_muxed7[1]),
-	.D2(ddrphy_dq_o_data_muxed7[2]),
-	.D3(ddrphy_dq_o_data_muxed7[3]),
-	.DQSW270(ddrphy_dqsw2700),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_dq_o7)
+	// Inputs.
+	.D0      (ddrphy_dq_o_data_muxed7[0]),
+	.D1      (ddrphy_dq_o_data_muxed7[1]),
+	.D2      (ddrphy_dq_o_data_muxed7[2]),
+	.D3      (ddrphy_dq_o_data_muxed7[3]),
+	.DQSW270 (ddrphy_dqsw2700),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+
+	// Outputs.
+	.Q       (ddrphy_dq_o7)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_33 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_MODE("DQS_ALIGNED_X2")
+	// Parameters.
+	.DEL_MODE ("DQS_ALIGNED_X2")
 ) DELAYG_33 (
-	.A(ddrphy_dq_i7),
-	.Z(ddrphy_dq_i_delayed7)
+	// Inputs.
+	.A (ddrphy_dq_i7),
+
+	// Outputs.
+	.Z (ddrphy_dq_i_delayed7)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDDRX2DQA_7 of IDDRX2DQA Module.
+//------------------------------------------------------------------------------
 IDDRX2DQA IDDRX2DQA_7(
-	.D(ddrphy_dq_i_delayed7),
-	.DQSR90(ddrphy_dqsr900),
-	.ECLK(sys2x_clk),
-	.RDPNTR0(ddrphy_rdpntr0[0]),
-	.RDPNTR1(ddrphy_rdpntr0[1]),
-	.RDPNTR2(ddrphy_rdpntr0[2]),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.WRPNTR0(ddrphy_wrpntr0[0]),
-	.WRPNTR1(ddrphy_wrpntr0[1]),
-	.WRPNTR2(ddrphy_wrpntr0[2]),
-	.Q0(ddrphy_bitslip7_i[0]),
-	.Q1(ddrphy_bitslip7_i[1]),
-	.Q2(ddrphy_bitslip7_i[2]),
-	.Q3(ddrphy_bitslip7_i[3])
+	// Inputs.
+	.D       (ddrphy_dq_i_delayed7),
+	.DQSR90  (ddrphy_dqsr900),
+	.ECLK    (sys2x_clk),
+	.RDPNTR0 (ddrphy_rdpntr0[0]),
+	.RDPNTR1 (ddrphy_rdpntr0[1]),
+	.RDPNTR2 (ddrphy_rdpntr0[2]),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.WRPNTR0 (ddrphy_wrpntr0[0]),
+	.WRPNTR1 (ddrphy_wrpntr0[1]),
+	.WRPNTR2 (ddrphy_wrpntr0[2]),
+
+	// Outputs.
+	.Q0      (ddrphy_bitslip7_i[0]),
+	.Q1      (ddrphy_bitslip7_i[1]),
+	.Q2      (ddrphy_bitslip7_i[2]),
+	.Q3      (ddrphy_bitslip7_i[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance TSHX2DQA_7 of TSHX2DQA Module.
+//------------------------------------------------------------------------------
 TSHX2DQA TSHX2DQA_7(
-	.DQSW270(ddrphy_dqsw2700),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.T0((~ddrphy_dq_oe)),
-	.T1((~ddrphy_dq_oe)),
-	.Q(ddrphy_dq_oe_n7)
+	// Inputs.
+	.DQSW270 (ddrphy_dqsw2700),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.T0      ((~ddrphy_dq_oe)),
+	.T1      ((~ddrphy_dq_oe)),
+
+	// Outputs.
+	.Q       (ddrphy_dq_oe_n7)
 );
 
+//------------------------------------------------------------------------------
+// Instance DQSBUFM_1 of DQSBUFM Module.
+//------------------------------------------------------------------------------
 DQSBUFM #(
-	.DQS_LI_DEL_ADJ("MINUS"),
-	.DQS_LI_DEL_VAL(1'd1),
-	.DQS_LO_DEL_ADJ("MINUS"),
-	.DQS_LO_DEL_VAL(3'd4)
+	// Parameters.
+	.DQS_LI_DEL_ADJ ("MINUS"),
+	.DQS_LI_DEL_VAL (1'd1),
+	.DQS_LO_DEL_ADJ ("MINUS"),
+	.DQS_LO_DEL_VAL (3'd4)
 ) DQSBUFM_1 (
-	.DDRDEL(ddrphy_delay0),
-	.DQSI(ddrphy_dqs_i1),
-	.ECLK(sys2x_clk),
-	.PAUSE((ddrphy_pause0 | ddrphy_dly_sel_storage[1])),
-	.RDDIRECTION(1'd1),
-	.RDLOADN(1'd0),
-	.RDMOVE(1'd0),
-	.READ0(ddrphy_dqs_re),
-	.READ1(ddrphy_dqs_re),
-	.READCLKSEL0(ddrphy_rdly1[0]),
-	.READCLKSEL1(ddrphy_rdly1[1]),
-	.READCLKSEL2(ddrphy_rdly1[2]),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.WRDIRECTION(1'd1),
-	.WRLOADN(1'd0),
-	.WRMOVE(1'd0),
-	.BURSTDET(ddrphy_burstdet1),
-	.DATAVALID(ddrphy_datavalid[1]),
-	.DQSR90(ddrphy_dqsr901),
-	.DQSW(ddrphy_dqsw1),
-	.DQSW270(ddrphy_dqsw2701),
-	.RDPNTR0(ddrphy_rdpntr1[0]),
-	.RDPNTR1(ddrphy_rdpntr1[1]),
-	.RDPNTR2(ddrphy_rdpntr1[2]),
-	.WRPNTR0(ddrphy_wrpntr1[0]),
-	.WRPNTR1(ddrphy_wrpntr1[1]),
-	.WRPNTR2(ddrphy_wrpntr1[2])
+	// Inputs.
+	.DDRDEL      (ddrphy_delay0),
+	.DQSI        (ddrphy_dqs_i1),
+	.ECLK        (sys2x_clk),
+	.PAUSE       ((ddrphy_pause0 | ddrphy_dly_sel_storage[1])),
+	.RDDIRECTION (1'd1),
+	.RDLOADN     (1'd0),
+	.RDMOVE      (1'd0),
+	.READ0       (ddrphy_dqs_re),
+	.READ1       (ddrphy_dqs_re),
+	.READCLKSEL0 (ddrphy_rdly1[0]),
+	.READCLKSEL1 (ddrphy_rdly1[1]),
+	.READCLKSEL2 (ddrphy_rdly1[2]),
+	.RST         (sys_rst),
+	.SCLK        (sys_clk),
+	.WRDIRECTION (1'd1),
+	.WRLOADN     (1'd0),
+	.WRMOVE      (1'd0),
+
+	// Outputs.
+	.BURSTDET    (ddrphy_burstdet1),
+	.DATAVALID   (ddrphy_datavalid[1]),
+	.DQSR90      (ddrphy_dqsr901),
+	.DQSW        (ddrphy_dqsw1),
+	.DQSW270     (ddrphy_dqsw2701),
+	.RDPNTR0     (ddrphy_rdpntr1[0]),
+	.RDPNTR1     (ddrphy_rdpntr1[1]),
+	.RDPNTR2     (ddrphy_rdpntr1[2]),
+	.WRPNTR0     (ddrphy_wrpntr1[0]),
+	.WRPNTR1     (ddrphy_wrpntr1[1]),
+	.WRPNTR2     (ddrphy_wrpntr1[2])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2DQSB_1 of ODDRX2DQSB Module.
+//------------------------------------------------------------------------------
 ODDRX2DQSB ODDRX2DQSB_1(
-	.D0(1'd0),
-	.D1(1'd1),
-	.D2(1'd0),
-	.D3(1'd1),
-	.DQSW(ddrphy_dqsw1),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_dqs1)
+	// Inputs.
+	.D0   (1'd0),
+	.D1   (1'd1),
+	.D2   (1'd0),
+	.D3   (1'd1),
+	.DQSW (ddrphy_dqsw1),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+
+	// Outputs.
+	.Q    (ddrphy_dqs1)
 );
 
+//------------------------------------------------------------------------------
+// Instance TSHX2DQSA_1 of TSHX2DQSA Module.
+//------------------------------------------------------------------------------
 TSHX2DQSA TSHX2DQSA_1(
-	.DQSW(ddrphy_dqsw1),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.T0((~(ddrphy_dqs_oe | ddrphy_dqs_postamble))),
-	.T1((~(ddrphy_dqs_oe | ddrphy_dqs_preamble))),
-	.Q(ddrphy_dqs_oe_n1)
+	// Inputs.
+	.DQSW (ddrphy_dqsw1),
+	.ECLK (sys2x_clk),
+	.RST  (sys_rst),
+	.SCLK (sys_clk),
+	.T0   ((~(ddrphy_dqs_oe | ddrphy_dqs_postamble))),
+	.T1   ((~(ddrphy_dqs_oe | ddrphy_dqs_preamble))),
+
+	// Outputs.
+	.Q    (ddrphy_dqs_oe_n1)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2DQA_9 of ODDRX2DQA Module.
+//------------------------------------------------------------------------------
 ODDRX2DQA ODDRX2DQA_9(
-	.D0(ddrphy_dm_o_data_muxed1[0]),
-	.D1(ddrphy_dm_o_data_muxed1[1]),
-	.D2(ddrphy_dm_o_data_muxed1[2]),
-	.D3(ddrphy_dm_o_data_muxed1[3]),
-	.DQSW270(ddrphy_dqsw2701),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddram_dm[1])
+	// Inputs.
+	.D0      (ddrphy_dm_o_data_muxed1[0]),
+	.D1      (ddrphy_dm_o_data_muxed1[1]),
+	.D2      (ddrphy_dm_o_data_muxed1[2]),
+	.D3      (ddrphy_dm_o_data_muxed1[3]),
+	.DQSW270 (ddrphy_dqsw2701),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+
+	// Outputs.
+	.Q       (ddram_dm[1])
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2DQA_10 of ODDRX2DQA Module.
+//------------------------------------------------------------------------------
 ODDRX2DQA ODDRX2DQA_10(
-	.D0(ddrphy_dq_o_data_muxed8[0]),
-	.D1(ddrphy_dq_o_data_muxed8[1]),
-	.D2(ddrphy_dq_o_data_muxed8[2]),
-	.D3(ddrphy_dq_o_data_muxed8[3]),
-	.DQSW270(ddrphy_dqsw2701),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_dq_o8)
+	// Inputs.
+	.D0      (ddrphy_dq_o_data_muxed8[0]),
+	.D1      (ddrphy_dq_o_data_muxed8[1]),
+	.D2      (ddrphy_dq_o_data_muxed8[2]),
+	.D3      (ddrphy_dq_o_data_muxed8[3]),
+	.DQSW270 (ddrphy_dqsw2701),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+
+	// Outputs.
+	.Q       (ddrphy_dq_o8)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_34 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_MODE("DQS_ALIGNED_X2")
+	// Parameters.
+	.DEL_MODE ("DQS_ALIGNED_X2")
 ) DELAYG_34 (
-	.A(ddrphy_dq_i8),
-	.Z(ddrphy_dq_i_delayed8)
+	// Inputs.
+	.A (ddrphy_dq_i8),
+
+	// Outputs.
+	.Z (ddrphy_dq_i_delayed8)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDDRX2DQA_8 of IDDRX2DQA Module.
+//------------------------------------------------------------------------------
 IDDRX2DQA IDDRX2DQA_8(
-	.D(ddrphy_dq_i_delayed8),
-	.DQSR90(ddrphy_dqsr901),
-	.ECLK(sys2x_clk),
-	.RDPNTR0(ddrphy_rdpntr1[0]),
-	.RDPNTR1(ddrphy_rdpntr1[1]),
-	.RDPNTR2(ddrphy_rdpntr1[2]),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.WRPNTR0(ddrphy_wrpntr1[0]),
-	.WRPNTR1(ddrphy_wrpntr1[1]),
-	.WRPNTR2(ddrphy_wrpntr1[2]),
-	.Q0(ddrphy_bitslip8_i[0]),
-	.Q1(ddrphy_bitslip8_i[1]),
-	.Q2(ddrphy_bitslip8_i[2]),
-	.Q3(ddrphy_bitslip8_i[3])
+	// Inputs.
+	.D       (ddrphy_dq_i_delayed8),
+	.DQSR90  (ddrphy_dqsr901),
+	.ECLK    (sys2x_clk),
+	.RDPNTR0 (ddrphy_rdpntr1[0]),
+	.RDPNTR1 (ddrphy_rdpntr1[1]),
+	.RDPNTR2 (ddrphy_rdpntr1[2]),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.WRPNTR0 (ddrphy_wrpntr1[0]),
+	.WRPNTR1 (ddrphy_wrpntr1[1]),
+	.WRPNTR2 (ddrphy_wrpntr1[2]),
+
+	// Outputs.
+	.Q0      (ddrphy_bitslip8_i[0]),
+	.Q1      (ddrphy_bitslip8_i[1]),
+	.Q2      (ddrphy_bitslip8_i[2]),
+	.Q3      (ddrphy_bitslip8_i[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance TSHX2DQA_8 of TSHX2DQA Module.
+//------------------------------------------------------------------------------
 TSHX2DQA TSHX2DQA_8(
-	.DQSW270(ddrphy_dqsw2701),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.T0((~ddrphy_dq_oe)),
-	.T1((~ddrphy_dq_oe)),
-	.Q(ddrphy_dq_oe_n8)
+	// Inputs.
+	.DQSW270 (ddrphy_dqsw2701),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.T0      ((~ddrphy_dq_oe)),
+	.T1      ((~ddrphy_dq_oe)),
+
+	// Outputs.
+	.Q       (ddrphy_dq_oe_n8)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2DQA_11 of ODDRX2DQA Module.
+//------------------------------------------------------------------------------
 ODDRX2DQA ODDRX2DQA_11(
-	.D0(ddrphy_dq_o_data_muxed9[0]),
-	.D1(ddrphy_dq_o_data_muxed9[1]),
-	.D2(ddrphy_dq_o_data_muxed9[2]),
-	.D3(ddrphy_dq_o_data_muxed9[3]),
-	.DQSW270(ddrphy_dqsw2701),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_dq_o9)
+	// Inputs.
+	.D0      (ddrphy_dq_o_data_muxed9[0]),
+	.D1      (ddrphy_dq_o_data_muxed9[1]),
+	.D2      (ddrphy_dq_o_data_muxed9[2]),
+	.D3      (ddrphy_dq_o_data_muxed9[3]),
+	.DQSW270 (ddrphy_dqsw2701),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+
+	// Outputs.
+	.Q       (ddrphy_dq_o9)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_35 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_MODE("DQS_ALIGNED_X2")
+	// Parameters.
+	.DEL_MODE ("DQS_ALIGNED_X2")
 ) DELAYG_35 (
-	.A(ddrphy_dq_i9),
-	.Z(ddrphy_dq_i_delayed9)
+	// Inputs.
+	.A (ddrphy_dq_i9),
+
+	// Outputs.
+	.Z (ddrphy_dq_i_delayed9)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDDRX2DQA_9 of IDDRX2DQA Module.
+//------------------------------------------------------------------------------
 IDDRX2DQA IDDRX2DQA_9(
-	.D(ddrphy_dq_i_delayed9),
-	.DQSR90(ddrphy_dqsr901),
-	.ECLK(sys2x_clk),
-	.RDPNTR0(ddrphy_rdpntr1[0]),
-	.RDPNTR1(ddrphy_rdpntr1[1]),
-	.RDPNTR2(ddrphy_rdpntr1[2]),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.WRPNTR0(ddrphy_wrpntr1[0]),
-	.WRPNTR1(ddrphy_wrpntr1[1]),
-	.WRPNTR2(ddrphy_wrpntr1[2]),
-	.Q0(ddrphy_bitslip9_i[0]),
-	.Q1(ddrphy_bitslip9_i[1]),
-	.Q2(ddrphy_bitslip9_i[2]),
-	.Q3(ddrphy_bitslip9_i[3])
+	// Inputs.
+	.D       (ddrphy_dq_i_delayed9),
+	.DQSR90  (ddrphy_dqsr901),
+	.ECLK    (sys2x_clk),
+	.RDPNTR0 (ddrphy_rdpntr1[0]),
+	.RDPNTR1 (ddrphy_rdpntr1[1]),
+	.RDPNTR2 (ddrphy_rdpntr1[2]),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.WRPNTR0 (ddrphy_wrpntr1[0]),
+	.WRPNTR1 (ddrphy_wrpntr1[1]),
+	.WRPNTR2 (ddrphy_wrpntr1[2]),
+
+	// Outputs.
+	.Q0      (ddrphy_bitslip9_i[0]),
+	.Q1      (ddrphy_bitslip9_i[1]),
+	.Q2      (ddrphy_bitslip9_i[2]),
+	.Q3      (ddrphy_bitslip9_i[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance TSHX2DQA_9 of TSHX2DQA Module.
+//------------------------------------------------------------------------------
 TSHX2DQA TSHX2DQA_9(
-	.DQSW270(ddrphy_dqsw2701),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.T0((~ddrphy_dq_oe)),
-	.T1((~ddrphy_dq_oe)),
-	.Q(ddrphy_dq_oe_n9)
+	// Inputs.
+	.DQSW270 (ddrphy_dqsw2701),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.T0      ((~ddrphy_dq_oe)),
+	.T1      ((~ddrphy_dq_oe)),
+
+	// Outputs.
+	.Q       (ddrphy_dq_oe_n9)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2DQA_12 of ODDRX2DQA Module.
+//------------------------------------------------------------------------------
 ODDRX2DQA ODDRX2DQA_12(
-	.D0(ddrphy_dq_o_data_muxed10[0]),
-	.D1(ddrphy_dq_o_data_muxed10[1]),
-	.D2(ddrphy_dq_o_data_muxed10[2]),
-	.D3(ddrphy_dq_o_data_muxed10[3]),
-	.DQSW270(ddrphy_dqsw2701),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_dq_o10)
+	// Inputs.
+	.D0      (ddrphy_dq_o_data_muxed10[0]),
+	.D1      (ddrphy_dq_o_data_muxed10[1]),
+	.D2      (ddrphy_dq_o_data_muxed10[2]),
+	.D3      (ddrphy_dq_o_data_muxed10[3]),
+	.DQSW270 (ddrphy_dqsw2701),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+
+	// Outputs.
+	.Q       (ddrphy_dq_o10)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_36 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_MODE("DQS_ALIGNED_X2")
+	// Parameters.
+	.DEL_MODE ("DQS_ALIGNED_X2")
 ) DELAYG_36 (
-	.A(ddrphy_dq_i10),
-	.Z(ddrphy_dq_i_delayed10)
+	// Inputs.
+	.A (ddrphy_dq_i10),
+
+	// Outputs.
+	.Z (ddrphy_dq_i_delayed10)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDDRX2DQA_10 of IDDRX2DQA Module.
+//------------------------------------------------------------------------------
 IDDRX2DQA IDDRX2DQA_10(
-	.D(ddrphy_dq_i_delayed10),
-	.DQSR90(ddrphy_dqsr901),
-	.ECLK(sys2x_clk),
-	.RDPNTR0(ddrphy_rdpntr1[0]),
-	.RDPNTR1(ddrphy_rdpntr1[1]),
-	.RDPNTR2(ddrphy_rdpntr1[2]),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.WRPNTR0(ddrphy_wrpntr1[0]),
-	.WRPNTR1(ddrphy_wrpntr1[1]),
-	.WRPNTR2(ddrphy_wrpntr1[2]),
-	.Q0(ddrphy_bitslip10_i[0]),
-	.Q1(ddrphy_bitslip10_i[1]),
-	.Q2(ddrphy_bitslip10_i[2]),
-	.Q3(ddrphy_bitslip10_i[3])
+	// Inputs.
+	.D       (ddrphy_dq_i_delayed10),
+	.DQSR90  (ddrphy_dqsr901),
+	.ECLK    (sys2x_clk),
+	.RDPNTR0 (ddrphy_rdpntr1[0]),
+	.RDPNTR1 (ddrphy_rdpntr1[1]),
+	.RDPNTR2 (ddrphy_rdpntr1[2]),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.WRPNTR0 (ddrphy_wrpntr1[0]),
+	.WRPNTR1 (ddrphy_wrpntr1[1]),
+	.WRPNTR2 (ddrphy_wrpntr1[2]),
+
+	// Outputs.
+	.Q0      (ddrphy_bitslip10_i[0]),
+	.Q1      (ddrphy_bitslip10_i[1]),
+	.Q2      (ddrphy_bitslip10_i[2]),
+	.Q3      (ddrphy_bitslip10_i[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance TSHX2DQA_10 of TSHX2DQA Module.
+//------------------------------------------------------------------------------
 TSHX2DQA TSHX2DQA_10(
-	.DQSW270(ddrphy_dqsw2701),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.T0((~ddrphy_dq_oe)),
-	.T1((~ddrphy_dq_oe)),
-	.Q(ddrphy_dq_oe_n10)
+	// Inputs.
+	.DQSW270 (ddrphy_dqsw2701),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.T0      ((~ddrphy_dq_oe)),
+	.T1      ((~ddrphy_dq_oe)),
+
+	// Outputs.
+	.Q       (ddrphy_dq_oe_n10)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2DQA_13 of ODDRX2DQA Module.
+//------------------------------------------------------------------------------
 ODDRX2DQA ODDRX2DQA_13(
-	.D0(ddrphy_dq_o_data_muxed11[0]),
-	.D1(ddrphy_dq_o_data_muxed11[1]),
-	.D2(ddrphy_dq_o_data_muxed11[2]),
-	.D3(ddrphy_dq_o_data_muxed11[3]),
-	.DQSW270(ddrphy_dqsw2701),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_dq_o11)
+	// Inputs.
+	.D0      (ddrphy_dq_o_data_muxed11[0]),
+	.D1      (ddrphy_dq_o_data_muxed11[1]),
+	.D2      (ddrphy_dq_o_data_muxed11[2]),
+	.D3      (ddrphy_dq_o_data_muxed11[3]),
+	.DQSW270 (ddrphy_dqsw2701),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+
+	// Outputs.
+	.Q       (ddrphy_dq_o11)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_37 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_MODE("DQS_ALIGNED_X2")
+	// Parameters.
+	.DEL_MODE ("DQS_ALIGNED_X2")
 ) DELAYG_37 (
-	.A(ddrphy_dq_i11),
-	.Z(ddrphy_dq_i_delayed11)
+	// Inputs.
+	.A (ddrphy_dq_i11),
+
+	// Outputs.
+	.Z (ddrphy_dq_i_delayed11)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDDRX2DQA_11 of IDDRX2DQA Module.
+//------------------------------------------------------------------------------
 IDDRX2DQA IDDRX2DQA_11(
-	.D(ddrphy_dq_i_delayed11),
-	.DQSR90(ddrphy_dqsr901),
-	.ECLK(sys2x_clk),
-	.RDPNTR0(ddrphy_rdpntr1[0]),
-	.RDPNTR1(ddrphy_rdpntr1[1]),
-	.RDPNTR2(ddrphy_rdpntr1[2]),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.WRPNTR0(ddrphy_wrpntr1[0]),
-	.WRPNTR1(ddrphy_wrpntr1[1]),
-	.WRPNTR2(ddrphy_wrpntr1[2]),
-	.Q0(ddrphy_bitslip11_i[0]),
-	.Q1(ddrphy_bitslip11_i[1]),
-	.Q2(ddrphy_bitslip11_i[2]),
-	.Q3(ddrphy_bitslip11_i[3])
+	// Inputs.
+	.D       (ddrphy_dq_i_delayed11),
+	.DQSR90  (ddrphy_dqsr901),
+	.ECLK    (sys2x_clk),
+	.RDPNTR0 (ddrphy_rdpntr1[0]),
+	.RDPNTR1 (ddrphy_rdpntr1[1]),
+	.RDPNTR2 (ddrphy_rdpntr1[2]),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.WRPNTR0 (ddrphy_wrpntr1[0]),
+	.WRPNTR1 (ddrphy_wrpntr1[1]),
+	.WRPNTR2 (ddrphy_wrpntr1[2]),
+
+	// Outputs.
+	.Q0      (ddrphy_bitslip11_i[0]),
+	.Q1      (ddrphy_bitslip11_i[1]),
+	.Q2      (ddrphy_bitslip11_i[2]),
+	.Q3      (ddrphy_bitslip11_i[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance TSHX2DQA_11 of TSHX2DQA Module.
+//------------------------------------------------------------------------------
 TSHX2DQA TSHX2DQA_11(
-	.DQSW270(ddrphy_dqsw2701),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.T0((~ddrphy_dq_oe)),
-	.T1((~ddrphy_dq_oe)),
-	.Q(ddrphy_dq_oe_n11)
+	// Inputs.
+	.DQSW270 (ddrphy_dqsw2701),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.T0      ((~ddrphy_dq_oe)),
+	.T1      ((~ddrphy_dq_oe)),
+
+	// Outputs.
+	.Q       (ddrphy_dq_oe_n11)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2DQA_14 of ODDRX2DQA Module.
+//------------------------------------------------------------------------------
 ODDRX2DQA ODDRX2DQA_14(
-	.D0(ddrphy_dq_o_data_muxed12[0]),
-	.D1(ddrphy_dq_o_data_muxed12[1]),
-	.D2(ddrphy_dq_o_data_muxed12[2]),
-	.D3(ddrphy_dq_o_data_muxed12[3]),
-	.DQSW270(ddrphy_dqsw2701),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_dq_o12)
+	// Inputs.
+	.D0      (ddrphy_dq_o_data_muxed12[0]),
+	.D1      (ddrphy_dq_o_data_muxed12[1]),
+	.D2      (ddrphy_dq_o_data_muxed12[2]),
+	.D3      (ddrphy_dq_o_data_muxed12[3]),
+	.DQSW270 (ddrphy_dqsw2701),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+
+	// Outputs.
+	.Q       (ddrphy_dq_o12)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_38 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_MODE("DQS_ALIGNED_X2")
+	// Parameters.
+	.DEL_MODE ("DQS_ALIGNED_X2")
 ) DELAYG_38 (
-	.A(ddrphy_dq_i12),
-	.Z(ddrphy_dq_i_delayed12)
+	// Inputs.
+	.A (ddrphy_dq_i12),
+
+	// Outputs.
+	.Z (ddrphy_dq_i_delayed12)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDDRX2DQA_12 of IDDRX2DQA Module.
+//------------------------------------------------------------------------------
 IDDRX2DQA IDDRX2DQA_12(
-	.D(ddrphy_dq_i_delayed12),
-	.DQSR90(ddrphy_dqsr901),
-	.ECLK(sys2x_clk),
-	.RDPNTR0(ddrphy_rdpntr1[0]),
-	.RDPNTR1(ddrphy_rdpntr1[1]),
-	.RDPNTR2(ddrphy_rdpntr1[2]),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.WRPNTR0(ddrphy_wrpntr1[0]),
-	.WRPNTR1(ddrphy_wrpntr1[1]),
-	.WRPNTR2(ddrphy_wrpntr1[2]),
-	.Q0(ddrphy_bitslip12_i[0]),
-	.Q1(ddrphy_bitslip12_i[1]),
-	.Q2(ddrphy_bitslip12_i[2]),
-	.Q3(ddrphy_bitslip12_i[3])
+	// Inputs.
+	.D       (ddrphy_dq_i_delayed12),
+	.DQSR90  (ddrphy_dqsr901),
+	.ECLK    (sys2x_clk),
+	.RDPNTR0 (ddrphy_rdpntr1[0]),
+	.RDPNTR1 (ddrphy_rdpntr1[1]),
+	.RDPNTR2 (ddrphy_rdpntr1[2]),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.WRPNTR0 (ddrphy_wrpntr1[0]),
+	.WRPNTR1 (ddrphy_wrpntr1[1]),
+	.WRPNTR2 (ddrphy_wrpntr1[2]),
+
+	// Outputs.
+	.Q0      (ddrphy_bitslip12_i[0]),
+	.Q1      (ddrphy_bitslip12_i[1]),
+	.Q2      (ddrphy_bitslip12_i[2]),
+	.Q3      (ddrphy_bitslip12_i[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance TSHX2DQA_12 of TSHX2DQA Module.
+//------------------------------------------------------------------------------
 TSHX2DQA TSHX2DQA_12(
-	.DQSW270(ddrphy_dqsw2701),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.T0((~ddrphy_dq_oe)),
-	.T1((~ddrphy_dq_oe)),
-	.Q(ddrphy_dq_oe_n12)
+	// Inputs.
+	.DQSW270 (ddrphy_dqsw2701),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.T0      ((~ddrphy_dq_oe)),
+	.T1      ((~ddrphy_dq_oe)),
+
+	// Outputs.
+	.Q       (ddrphy_dq_oe_n12)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2DQA_15 of ODDRX2DQA Module.
+//------------------------------------------------------------------------------
 ODDRX2DQA ODDRX2DQA_15(
-	.D0(ddrphy_dq_o_data_muxed13[0]),
-	.D1(ddrphy_dq_o_data_muxed13[1]),
-	.D2(ddrphy_dq_o_data_muxed13[2]),
-	.D3(ddrphy_dq_o_data_muxed13[3]),
-	.DQSW270(ddrphy_dqsw2701),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_dq_o13)
+	// Inputs.
+	.D0      (ddrphy_dq_o_data_muxed13[0]),
+	.D1      (ddrphy_dq_o_data_muxed13[1]),
+	.D2      (ddrphy_dq_o_data_muxed13[2]),
+	.D3      (ddrphy_dq_o_data_muxed13[3]),
+	.DQSW270 (ddrphy_dqsw2701),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+
+	// Outputs.
+	.Q       (ddrphy_dq_o13)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_39 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_MODE("DQS_ALIGNED_X2")
+	// Parameters.
+	.DEL_MODE ("DQS_ALIGNED_X2")
 ) DELAYG_39 (
-	.A(ddrphy_dq_i13),
-	.Z(ddrphy_dq_i_delayed13)
+	// Inputs.
+	.A (ddrphy_dq_i13),
+
+	// Outputs.
+	.Z (ddrphy_dq_i_delayed13)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDDRX2DQA_13 of IDDRX2DQA Module.
+//------------------------------------------------------------------------------
 IDDRX2DQA IDDRX2DQA_13(
-	.D(ddrphy_dq_i_delayed13),
-	.DQSR90(ddrphy_dqsr901),
-	.ECLK(sys2x_clk),
-	.RDPNTR0(ddrphy_rdpntr1[0]),
-	.RDPNTR1(ddrphy_rdpntr1[1]),
-	.RDPNTR2(ddrphy_rdpntr1[2]),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.WRPNTR0(ddrphy_wrpntr1[0]),
-	.WRPNTR1(ddrphy_wrpntr1[1]),
-	.WRPNTR2(ddrphy_wrpntr1[2]),
-	.Q0(ddrphy_bitslip13_i[0]),
-	.Q1(ddrphy_bitslip13_i[1]),
-	.Q2(ddrphy_bitslip13_i[2]),
-	.Q3(ddrphy_bitslip13_i[3])
+	// Inputs.
+	.D       (ddrphy_dq_i_delayed13),
+	.DQSR90  (ddrphy_dqsr901),
+	.ECLK    (sys2x_clk),
+	.RDPNTR0 (ddrphy_rdpntr1[0]),
+	.RDPNTR1 (ddrphy_rdpntr1[1]),
+	.RDPNTR2 (ddrphy_rdpntr1[2]),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.WRPNTR0 (ddrphy_wrpntr1[0]),
+	.WRPNTR1 (ddrphy_wrpntr1[1]),
+	.WRPNTR2 (ddrphy_wrpntr1[2]),
+
+	// Outputs.
+	.Q0      (ddrphy_bitslip13_i[0]),
+	.Q1      (ddrphy_bitslip13_i[1]),
+	.Q2      (ddrphy_bitslip13_i[2]),
+	.Q3      (ddrphy_bitslip13_i[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance TSHX2DQA_13 of TSHX2DQA Module.
+//------------------------------------------------------------------------------
 TSHX2DQA TSHX2DQA_13(
-	.DQSW270(ddrphy_dqsw2701),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.T0((~ddrphy_dq_oe)),
-	.T1((~ddrphy_dq_oe)),
-	.Q(ddrphy_dq_oe_n13)
+	// Inputs.
+	.DQSW270 (ddrphy_dqsw2701),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.T0      ((~ddrphy_dq_oe)),
+	.T1      ((~ddrphy_dq_oe)),
+
+	// Outputs.
+	.Q       (ddrphy_dq_oe_n13)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2DQA_16 of ODDRX2DQA Module.
+//------------------------------------------------------------------------------
 ODDRX2DQA ODDRX2DQA_16(
-	.D0(ddrphy_dq_o_data_muxed14[0]),
-	.D1(ddrphy_dq_o_data_muxed14[1]),
-	.D2(ddrphy_dq_o_data_muxed14[2]),
-	.D3(ddrphy_dq_o_data_muxed14[3]),
-	.DQSW270(ddrphy_dqsw2701),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_dq_o14)
+	// Inputs.
+	.D0      (ddrphy_dq_o_data_muxed14[0]),
+	.D1      (ddrphy_dq_o_data_muxed14[1]),
+	.D2      (ddrphy_dq_o_data_muxed14[2]),
+	.D3      (ddrphy_dq_o_data_muxed14[3]),
+	.DQSW270 (ddrphy_dqsw2701),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+
+	// Outputs.
+	.Q       (ddrphy_dq_o14)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_40 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_MODE("DQS_ALIGNED_X2")
+	// Parameters.
+	.DEL_MODE ("DQS_ALIGNED_X2")
 ) DELAYG_40 (
-	.A(ddrphy_dq_i14),
-	.Z(ddrphy_dq_i_delayed14)
+	// Inputs.
+	.A (ddrphy_dq_i14),
+
+	// Outputs.
+	.Z (ddrphy_dq_i_delayed14)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDDRX2DQA_14 of IDDRX2DQA Module.
+//------------------------------------------------------------------------------
 IDDRX2DQA IDDRX2DQA_14(
-	.D(ddrphy_dq_i_delayed14),
-	.DQSR90(ddrphy_dqsr901),
-	.ECLK(sys2x_clk),
-	.RDPNTR0(ddrphy_rdpntr1[0]),
-	.RDPNTR1(ddrphy_rdpntr1[1]),
-	.RDPNTR2(ddrphy_rdpntr1[2]),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.WRPNTR0(ddrphy_wrpntr1[0]),
-	.WRPNTR1(ddrphy_wrpntr1[1]),
-	.WRPNTR2(ddrphy_wrpntr1[2]),
-	.Q0(ddrphy_bitslip14_i[0]),
-	.Q1(ddrphy_bitslip14_i[1]),
-	.Q2(ddrphy_bitslip14_i[2]),
-	.Q3(ddrphy_bitslip14_i[3])
+	// Inputs.
+	.D       (ddrphy_dq_i_delayed14),
+	.DQSR90  (ddrphy_dqsr901),
+	.ECLK    (sys2x_clk),
+	.RDPNTR0 (ddrphy_rdpntr1[0]),
+	.RDPNTR1 (ddrphy_rdpntr1[1]),
+	.RDPNTR2 (ddrphy_rdpntr1[2]),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.WRPNTR0 (ddrphy_wrpntr1[0]),
+	.WRPNTR1 (ddrphy_wrpntr1[1]),
+	.WRPNTR2 (ddrphy_wrpntr1[2]),
+
+	// Outputs.
+	.Q0      (ddrphy_bitslip14_i[0]),
+	.Q1      (ddrphy_bitslip14_i[1]),
+	.Q2      (ddrphy_bitslip14_i[2]),
+	.Q3      (ddrphy_bitslip14_i[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance TSHX2DQA_14 of TSHX2DQA Module.
+//------------------------------------------------------------------------------
 TSHX2DQA TSHX2DQA_14(
-	.DQSW270(ddrphy_dqsw2701),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.T0((~ddrphy_dq_oe)),
-	.T1((~ddrphy_dq_oe)),
-	.Q(ddrphy_dq_oe_n14)
+	// Inputs.
+	.DQSW270 (ddrphy_dqsw2701),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.T0      ((~ddrphy_dq_oe)),
+	.T1      ((~ddrphy_dq_oe)),
+
+	// Outputs.
+	.Q       (ddrphy_dq_oe_n14)
 );
 
+//------------------------------------------------------------------------------
+// Instance ODDRX2DQA_17 of ODDRX2DQA Module.
+//------------------------------------------------------------------------------
 ODDRX2DQA ODDRX2DQA_17(
-	.D0(ddrphy_dq_o_data_muxed15[0]),
-	.D1(ddrphy_dq_o_data_muxed15[1]),
-	.D2(ddrphy_dq_o_data_muxed15[2]),
-	.D3(ddrphy_dq_o_data_muxed15[3]),
-	.DQSW270(ddrphy_dqsw2701),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.Q(ddrphy_dq_o15)
+	// Inputs.
+	.D0      (ddrphy_dq_o_data_muxed15[0]),
+	.D1      (ddrphy_dq_o_data_muxed15[1]),
+	.D2      (ddrphy_dq_o_data_muxed15[2]),
+	.D3      (ddrphy_dq_o_data_muxed15[3]),
+	.DQSW270 (ddrphy_dqsw2701),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+
+	// Outputs.
+	.Q       (ddrphy_dq_o15)
 );
 
+//------------------------------------------------------------------------------
+// Instance DELAYG_41 of DELAYG Module.
+//------------------------------------------------------------------------------
 DELAYG #(
-	.DEL_MODE("DQS_ALIGNED_X2")
+	// Parameters.
+	.DEL_MODE ("DQS_ALIGNED_X2")
 ) DELAYG_41 (
-	.A(ddrphy_dq_i15),
-	.Z(ddrphy_dq_i_delayed15)
+	// Inputs.
+	.A (ddrphy_dq_i15),
+
+	// Outputs.
+	.Z (ddrphy_dq_i_delayed15)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDDRX2DQA_15 of IDDRX2DQA Module.
+//------------------------------------------------------------------------------
 IDDRX2DQA IDDRX2DQA_15(
-	.D(ddrphy_dq_i_delayed15),
-	.DQSR90(ddrphy_dqsr901),
-	.ECLK(sys2x_clk),
-	.RDPNTR0(ddrphy_rdpntr1[0]),
-	.RDPNTR1(ddrphy_rdpntr1[1]),
-	.RDPNTR2(ddrphy_rdpntr1[2]),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.WRPNTR0(ddrphy_wrpntr1[0]),
-	.WRPNTR1(ddrphy_wrpntr1[1]),
-	.WRPNTR2(ddrphy_wrpntr1[2]),
-	.Q0(ddrphy_bitslip15_i[0]),
-	.Q1(ddrphy_bitslip15_i[1]),
-	.Q2(ddrphy_bitslip15_i[2]),
-	.Q3(ddrphy_bitslip15_i[3])
+	// Inputs.
+	.D       (ddrphy_dq_i_delayed15),
+	.DQSR90  (ddrphy_dqsr901),
+	.ECLK    (sys2x_clk),
+	.RDPNTR0 (ddrphy_rdpntr1[0]),
+	.RDPNTR1 (ddrphy_rdpntr1[1]),
+	.RDPNTR2 (ddrphy_rdpntr1[2]),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.WRPNTR0 (ddrphy_wrpntr1[0]),
+	.WRPNTR1 (ddrphy_wrpntr1[1]),
+	.WRPNTR2 (ddrphy_wrpntr1[2]),
+
+	// Outputs.
+	.Q0      (ddrphy_bitslip15_i[0]),
+	.Q1      (ddrphy_bitslip15_i[1]),
+	.Q2      (ddrphy_bitslip15_i[2]),
+	.Q3      (ddrphy_bitslip15_i[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance TSHX2DQA_15 of TSHX2DQA Module.
+//------------------------------------------------------------------------------
 TSHX2DQA TSHX2DQA_15(
-	.DQSW270(ddrphy_dqsw2701),
-	.ECLK(sys2x_clk),
-	.RST(sys_rst),
-	.SCLK(sys_clk),
-	.T0((~ddrphy_dq_oe)),
-	.T1((~ddrphy_dq_oe)),
-	.Q(ddrphy_dq_oe_n15)
+	// Inputs.
+	.DQSW270 (ddrphy_dqsw2701),
+	.ECLK    (sys2x_clk),
+	.RST     (sys_rst),
+	.SCLK    (sys_clk),
+	.T0      ((~ddrphy_dq_oe)),
+	.T1      ((~ddrphy_dq_oe)),
+
+	// Outputs.
+	.Q       (ddrphy_dq_oe_n15)
 );
 
 //------------------------------------------------------------------------------
@@ -13353,252 +14537,433 @@ assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachi
 
 
 (* FREQUENCY_PIN_CLKI = "48.0", FREQUENCY_PIN_CLKOP = "96.0", FREQUENCY_PIN_CLKOS = "24.0", ICP_CURRENT = "6", LPF_RESISTOR = "16", MFG_ENABLE_FILTEROPAMP = "1", MFG_GMCREF_SEL = "2" *)
+//------------------------------------------------------------------------------
+// Instance EHXPLLL of EHXPLLL Module.
+//------------------------------------------------------------------------------
 EHXPLLL #(
-	.CLKFB_DIV(4'd10),
-	.CLKI_DIV(1'd1),
-	.CLKOP_CPHASE(3'd4),
-	.CLKOP_DIV(3'd5),
-	.CLKOP_ENABLE("ENABLED"),
-	.CLKOP_FPHASE(1'd0),
-	.CLKOS2_CPHASE(1'd0),
-	.CLKOS2_DIV(1'd1),
-	.CLKOS2_ENABLE("ENABLED"),
-	.CLKOS2_FPHASE(1'd0),
-	.CLKOS_CPHASE(5'd19),
-	.CLKOS_DIV(5'd20),
-	.CLKOS_ENABLE("ENABLED"),
-	.CLKOS_FPHASE(1'd0),
-	.FEEDBK_PATH("INT_OS2")
+	// Parameters.
+	.CLKFB_DIV     (4'd10),
+	.CLKI_DIV      (1'd1),
+	.CLKOP_CPHASE  (3'd4),
+	.CLKOP_DIV     (3'd5),
+	.CLKOP_ENABLE  ("ENABLED"),
+	.CLKOP_FPHASE  (1'd0),
+	.CLKOS2_CPHASE (1'd0),
+	.CLKOS2_DIV    (1'd1),
+	.CLKOS2_ENABLE ("ENABLED"),
+	.CLKOS2_FPHASE (1'd0),
+	.CLKOS_CPHASE  (5'd19),
+	.CLKOS_DIV     (5'd20),
+	.CLKOS_ENABLE  ("ENABLED"),
+	.CLKOS_FPHASE  (1'd0),
+	.FEEDBK_PATH   ("INT_OS2")
 ) EHXPLLL (
-	.CLKI(crg_clkin),
-	.RST(crg_reset1),
-	.STDBY(crg_stdby),
-	.CLKOP(crg_clkout0),
-	.CLKOS(crg_clkout1),
-	.CLKOS2(litedramcore_litedramecp5ddrphycrg_ecp5pll),
-	.LOCK(litedramcore_litedramecp5ddrphycrg_locked)
+	// Inputs.
+	.CLKI   (crg_clkin),
+	.RST    (crg_reset1),
+	.STDBY  (crg_stdby),
+
+	// Outputs.
+	.CLKOP  (crg_clkout0),
+	.CLKOS  (crg_clkout1),
+	.CLKOS2 (litedramecp5ddrphycrg_ecp5pll),
+	.LOCK   (litedramecp5ddrphycrg_locked)
 );
 
+//------------------------------------------------------------------------------
+// Instance FD1S3BX of FD1S3BX Module.
+//------------------------------------------------------------------------------
 FD1S3BX FD1S3BX(
-	.CK(sys2x_i_clk),
-	.D(1'd0),
-	.PD((~crg_locked)),
-	.Q(latticeecp5asyncresetsynchronizerimpl0_rst1)
+	// Inputs.
+	.CK (sys2x_i_clk),
+	.D  (1'd0),
+	.PD ((~crg_locked)),
+
+	// Outputs.
+	.Q  (latticeecp5asyncresetsynchronizerimpl0_rst1)
 );
 
+//------------------------------------------------------------------------------
+// Instance FD1S3BX_1 of FD1S3BX Module.
+//------------------------------------------------------------------------------
 FD1S3BX FD1S3BX_1(
-	.CK(sys2x_i_clk),
-	.D(latticeecp5asyncresetsynchronizerimpl0_rst1),
-	.PD((~crg_locked)),
-	.Q(latticeecp5asyncresetsynchronizerimpl0_expr)
+	// Inputs.
+	.CK (sys2x_i_clk),
+	.D  (latticeecp5asyncresetsynchronizerimpl0_rst1),
+	.PD ((~crg_locked)),
+
+	// Outputs.
+	.Q  (latticeecp5asyncresetsynchronizerimpl0_expr)
 );
 
+//------------------------------------------------------------------------------
+// Instance FD1S3BX_2 of FD1S3BX Module.
+//------------------------------------------------------------------------------
 FD1S3BX FD1S3BX_2(
-	.CK(init_clk),
-	.D(1'd0),
-	.PD((~crg_locked)),
-	.Q(latticeecp5asyncresetsynchronizerimpl1_rst1)
+	// Inputs.
+	.CK (init_clk),
+	.D  (1'd0),
+	.PD ((~crg_locked)),
+
+	// Outputs.
+	.Q  (latticeecp5asyncresetsynchronizerimpl1_rst1)
 );
 
+//------------------------------------------------------------------------------
+// Instance FD1S3BX_3 of FD1S3BX Module.
+//------------------------------------------------------------------------------
 FD1S3BX FD1S3BX_3(
-	.CK(init_clk),
-	.D(latticeecp5asyncresetsynchronizerimpl1_rst1),
-	.PD((~crg_locked)),
-	.Q(init_rst)
+	// Inputs.
+	.CK (init_clk),
+	.D  (latticeecp5asyncresetsynchronizerimpl1_rst1),
+	.PD ((~crg_locked)),
+
+	// Outputs.
+	.Q  (init_rst)
 );
 
+//------------------------------------------------------------------------------
+// Instance FD1S3BX_4 of FD1S3BX Module.
+//------------------------------------------------------------------------------
 FD1S3BX FD1S3BX_4(
-	.CK(sys_clk),
-	.D(1'd0),
-	.PD(((~crg_locked) | crg_reset0)),
-	.Q(latticeecp5asyncresetsynchronizerimpl2_rst1)
+	// Inputs.
+	.CK (sys_clk),
+	.D  (1'd0),
+	.PD (((~crg_locked) | crg_reset0)),
+
+	// Outputs.
+	.Q  (latticeecp5asyncresetsynchronizerimpl2_rst1)
 );
 
+//------------------------------------------------------------------------------
+// Instance FD1S3BX_5 of FD1S3BX Module.
+//------------------------------------------------------------------------------
 FD1S3BX FD1S3BX_5(
-	.CK(sys_clk),
-	.D(latticeecp5asyncresetsynchronizerimpl2_rst1),
-	.PD(((~crg_locked) | crg_reset0)),
-	.Q(sys_rst)
+	// Inputs.
+	.CK (sys_clk),
+	.D  (latticeecp5asyncresetsynchronizerimpl2_rst1),
+	.PD (((~crg_locked) | crg_reset0)),
+
+	// Outputs.
+	.Q  (sys_rst)
 );
 
+//------------------------------------------------------------------------------
+// Instance FD1S3BX_6 of FD1S3BX Module.
+//------------------------------------------------------------------------------
 FD1S3BX FD1S3BX_6(
-	.CK(sys2x_clk),
-	.D(1'd0),
-	.PD(((~crg_locked) | crg_reset0)),
-	.Q(latticeecp5asyncresetsynchronizerimpl3_rst1)
+	// Inputs.
+	.CK (sys2x_clk),
+	.D  (1'd0),
+	.PD (((~crg_locked) | crg_reset0)),
+
+	// Outputs.
+	.Q  (latticeecp5asyncresetsynchronizerimpl3_rst1)
 );
 
+//------------------------------------------------------------------------------
+// Instance FD1S3BX_7 of FD1S3BX Module.
+//------------------------------------------------------------------------------
 FD1S3BX FD1S3BX_7(
-	.CK(sys2x_clk),
-	.D(latticeecp5asyncresetsynchronizerimpl3_rst1),
-	.PD(((~crg_locked) | crg_reset0)),
-	.Q(sys2x_rst)
+	// Inputs.
+	.CK (sys2x_clk),
+	.D  (latticeecp5asyncresetsynchronizerimpl3_rst1),
+	.PD (((~crg_locked) | crg_reset0)),
+
+	// Outputs.
+	.Q  (sys2x_rst)
 );
 
+//------------------------------------------------------------------------------
+// Instance TRELLIS_IO of TRELLIS_IO Module.
+//------------------------------------------------------------------------------
 TRELLIS_IO #(
-	.DIR("BIDIR")
+	// Parameters.
+	.DIR ("BIDIR")
 ) TRELLIS_IO (
-	.B(ddram_dqs_p[0]),
-	.I(ddrphy_dqs0),
-	.T((~(~ddrphy_dqs_oe_n0))),
-	.O(ddrphy_dqs_i0)
+	// Inputs.
+	.B (ddram_dqs_p[0]),
+	.I (ddrphy_dqs0),
+	.T ((~(~ddrphy_dqs_oe_n0))),
+
+	// Outputs.
+	.O (ddrphy_dqs_i0)
 );
 
+//------------------------------------------------------------------------------
+// Instance TRELLIS_IO_1 of TRELLIS_IO Module.
+//------------------------------------------------------------------------------
 TRELLIS_IO #(
-	.DIR("BIDIR")
+	// Parameters.
+	.DIR ("BIDIR")
 ) TRELLIS_IO_1 (
-	.B(ddram_dq[0]),
-	.I(ddrphy_dq_o0),
-	.T((~(~ddrphy_dq_oe_n0))),
-	.O(ddrphy_dq_i0)
+	// Inputs.
+	.B (ddram_dq[0]),
+	.I (ddrphy_dq_o0),
+	.T ((~(~ddrphy_dq_oe_n0))),
+
+	// Outputs.
+	.O (ddrphy_dq_i0)
 );
 
+//------------------------------------------------------------------------------
+// Instance TRELLIS_IO_2 of TRELLIS_IO Module.
+//------------------------------------------------------------------------------
 TRELLIS_IO #(
-	.DIR("BIDIR")
+	// Parameters.
+	.DIR ("BIDIR")
 ) TRELLIS_IO_2 (
-	.B(ddram_dq[1]),
-	.I(ddrphy_dq_o1),
-	.T((~(~ddrphy_dq_oe_n1))),
-	.O(ddrphy_dq_i1)
+	// Inputs.
+	.B (ddram_dq[1]),
+	.I (ddrphy_dq_o1),
+	.T ((~(~ddrphy_dq_oe_n1))),
+
+	// Outputs.
+	.O (ddrphy_dq_i1)
 );
 
+//------------------------------------------------------------------------------
+// Instance TRELLIS_IO_3 of TRELLIS_IO Module.
+//------------------------------------------------------------------------------
 TRELLIS_IO #(
-	.DIR("BIDIR")
+	// Parameters.
+	.DIR ("BIDIR")
 ) TRELLIS_IO_3 (
-	.B(ddram_dq[2]),
-	.I(ddrphy_dq_o2),
-	.T((~(~ddrphy_dq_oe_n2))),
-	.O(ddrphy_dq_i2)
+	// Inputs.
+	.B (ddram_dq[2]),
+	.I (ddrphy_dq_o2),
+	.T ((~(~ddrphy_dq_oe_n2))),
+
+	// Outputs.
+	.O (ddrphy_dq_i2)
 );
 
+//------------------------------------------------------------------------------
+// Instance TRELLIS_IO_4 of TRELLIS_IO Module.
+//------------------------------------------------------------------------------
 TRELLIS_IO #(
-	.DIR("BIDIR")
+	// Parameters.
+	.DIR ("BIDIR")
 ) TRELLIS_IO_4 (
-	.B(ddram_dq[3]),
-	.I(ddrphy_dq_o3),
-	.T((~(~ddrphy_dq_oe_n3))),
-	.O(ddrphy_dq_i3)
+	// Inputs.
+	.B (ddram_dq[3]),
+	.I (ddrphy_dq_o3),
+	.T ((~(~ddrphy_dq_oe_n3))),
+
+	// Outputs.
+	.O (ddrphy_dq_i3)
 );
 
+//------------------------------------------------------------------------------
+// Instance TRELLIS_IO_5 of TRELLIS_IO Module.
+//------------------------------------------------------------------------------
 TRELLIS_IO #(
-	.DIR("BIDIR")
+	// Parameters.
+	.DIR ("BIDIR")
 ) TRELLIS_IO_5 (
-	.B(ddram_dq[4]),
-	.I(ddrphy_dq_o4),
-	.T((~(~ddrphy_dq_oe_n4))),
-	.O(ddrphy_dq_i4)
+	// Inputs.
+	.B (ddram_dq[4]),
+	.I (ddrphy_dq_o4),
+	.T ((~(~ddrphy_dq_oe_n4))),
+
+	// Outputs.
+	.O (ddrphy_dq_i4)
 );
 
+//------------------------------------------------------------------------------
+// Instance TRELLIS_IO_6 of TRELLIS_IO Module.
+//------------------------------------------------------------------------------
 TRELLIS_IO #(
-	.DIR("BIDIR")
+	// Parameters.
+	.DIR ("BIDIR")
 ) TRELLIS_IO_6 (
-	.B(ddram_dq[5]),
-	.I(ddrphy_dq_o5),
-	.T((~(~ddrphy_dq_oe_n5))),
-	.O(ddrphy_dq_i5)
+	// Inputs.
+	.B (ddram_dq[5]),
+	.I (ddrphy_dq_o5),
+	.T ((~(~ddrphy_dq_oe_n5))),
+
+	// Outputs.
+	.O (ddrphy_dq_i5)
 );
 
+//------------------------------------------------------------------------------
+// Instance TRELLIS_IO_7 of TRELLIS_IO Module.
+//------------------------------------------------------------------------------
 TRELLIS_IO #(
-	.DIR("BIDIR")
+	// Parameters.
+	.DIR ("BIDIR")
 ) TRELLIS_IO_7 (
-	.B(ddram_dq[6]),
-	.I(ddrphy_dq_o6),
-	.T((~(~ddrphy_dq_oe_n6))),
-	.O(ddrphy_dq_i6)
+	// Inputs.
+	.B (ddram_dq[6]),
+	.I (ddrphy_dq_o6),
+	.T ((~(~ddrphy_dq_oe_n6))),
+
+	// Outputs.
+	.O (ddrphy_dq_i6)
 );
 
+//------------------------------------------------------------------------------
+// Instance TRELLIS_IO_8 of TRELLIS_IO Module.
+//------------------------------------------------------------------------------
 TRELLIS_IO #(
-	.DIR("BIDIR")
+	// Parameters.
+	.DIR ("BIDIR")
 ) TRELLIS_IO_8 (
-	.B(ddram_dq[7]),
-	.I(ddrphy_dq_o7),
-	.T((~(~ddrphy_dq_oe_n7))),
-	.O(ddrphy_dq_i7)
+	// Inputs.
+	.B (ddram_dq[7]),
+	.I (ddrphy_dq_o7),
+	.T ((~(~ddrphy_dq_oe_n7))),
+
+	// Outputs.
+	.O (ddrphy_dq_i7)
 );
 
+//------------------------------------------------------------------------------
+// Instance TRELLIS_IO_9 of TRELLIS_IO Module.
+//------------------------------------------------------------------------------
 TRELLIS_IO #(
-	.DIR("BIDIR")
+	// Parameters.
+	.DIR ("BIDIR")
 ) TRELLIS_IO_9 (
-	.B(ddram_dqs_p[1]),
-	.I(ddrphy_dqs1),
-	.T((~(~ddrphy_dqs_oe_n1))),
-	.O(ddrphy_dqs_i1)
+	// Inputs.
+	.B (ddram_dqs_p[1]),
+	.I (ddrphy_dqs1),
+	.T ((~(~ddrphy_dqs_oe_n1))),
+
+	// Outputs.
+	.O (ddrphy_dqs_i1)
 );
 
+//------------------------------------------------------------------------------
+// Instance TRELLIS_IO_10 of TRELLIS_IO Module.
+//------------------------------------------------------------------------------
 TRELLIS_IO #(
-	.DIR("BIDIR")
+	// Parameters.
+	.DIR ("BIDIR")
 ) TRELLIS_IO_10 (
-	.B(ddram_dq[8]),
-	.I(ddrphy_dq_o8),
-	.T((~(~ddrphy_dq_oe_n8))),
-	.O(ddrphy_dq_i8)
+	// Inputs.
+	.B (ddram_dq[8]),
+	.I (ddrphy_dq_o8),
+	.T ((~(~ddrphy_dq_oe_n8))),
+
+	// Outputs.
+	.O (ddrphy_dq_i8)
 );
 
+//------------------------------------------------------------------------------
+// Instance TRELLIS_IO_11 of TRELLIS_IO Module.
+//------------------------------------------------------------------------------
 TRELLIS_IO #(
-	.DIR("BIDIR")
+	// Parameters.
+	.DIR ("BIDIR")
 ) TRELLIS_IO_11 (
-	.B(ddram_dq[9]),
-	.I(ddrphy_dq_o9),
-	.T((~(~ddrphy_dq_oe_n9))),
-	.O(ddrphy_dq_i9)
+	// Inputs.
+	.B (ddram_dq[9]),
+	.I (ddrphy_dq_o9),
+	.T ((~(~ddrphy_dq_oe_n9))),
+
+	// Outputs.
+	.O (ddrphy_dq_i9)
 );
 
+//------------------------------------------------------------------------------
+// Instance TRELLIS_IO_12 of TRELLIS_IO Module.
+//------------------------------------------------------------------------------
 TRELLIS_IO #(
-	.DIR("BIDIR")
+	// Parameters.
+	.DIR ("BIDIR")
 ) TRELLIS_IO_12 (
-	.B(ddram_dq[10]),
-	.I(ddrphy_dq_o10),
-	.T((~(~ddrphy_dq_oe_n10))),
-	.O(ddrphy_dq_i10)
+	// Inputs.
+	.B (ddram_dq[10]),
+	.I (ddrphy_dq_o10),
+	.T ((~(~ddrphy_dq_oe_n10))),
+
+	// Outputs.
+	.O (ddrphy_dq_i10)
 );
 
+//------------------------------------------------------------------------------
+// Instance TRELLIS_IO_13 of TRELLIS_IO Module.
+//------------------------------------------------------------------------------
 TRELLIS_IO #(
-	.DIR("BIDIR")
+	// Parameters.
+	.DIR ("BIDIR")
 ) TRELLIS_IO_13 (
-	.B(ddram_dq[11]),
-	.I(ddrphy_dq_o11),
-	.T((~(~ddrphy_dq_oe_n11))),
-	.O(ddrphy_dq_i11)
+	// Inputs.
+	.B (ddram_dq[11]),
+	.I (ddrphy_dq_o11),
+	.T ((~(~ddrphy_dq_oe_n11))),
+
+	// Outputs.
+	.O (ddrphy_dq_i11)
 );
 
+//------------------------------------------------------------------------------
+// Instance TRELLIS_IO_14 of TRELLIS_IO Module.
+//------------------------------------------------------------------------------
 TRELLIS_IO #(
-	.DIR("BIDIR")
+	// Parameters.
+	.DIR ("BIDIR")
 ) TRELLIS_IO_14 (
-	.B(ddram_dq[12]),
-	.I(ddrphy_dq_o12),
-	.T((~(~ddrphy_dq_oe_n12))),
-	.O(ddrphy_dq_i12)
+	// Inputs.
+	.B (ddram_dq[12]),
+	.I (ddrphy_dq_o12),
+	.T ((~(~ddrphy_dq_oe_n12))),
+
+	// Outputs.
+	.O (ddrphy_dq_i12)
 );
 
+//------------------------------------------------------------------------------
+// Instance TRELLIS_IO_15 of TRELLIS_IO Module.
+//------------------------------------------------------------------------------
 TRELLIS_IO #(
-	.DIR("BIDIR")
+	// Parameters.
+	.DIR ("BIDIR")
 ) TRELLIS_IO_15 (
-	.B(ddram_dq[13]),
-	.I(ddrphy_dq_o13),
-	.T((~(~ddrphy_dq_oe_n13))),
-	.O(ddrphy_dq_i13)
+	// Inputs.
+	.B (ddram_dq[13]),
+	.I (ddrphy_dq_o13),
+	.T ((~(~ddrphy_dq_oe_n13))),
+
+	// Outputs.
+	.O (ddrphy_dq_i13)
 );
 
+//------------------------------------------------------------------------------
+// Instance TRELLIS_IO_16 of TRELLIS_IO Module.
+//------------------------------------------------------------------------------
 TRELLIS_IO #(
-	.DIR("BIDIR")
+	// Parameters.
+	.DIR ("BIDIR")
 ) TRELLIS_IO_16 (
-	.B(ddram_dq[14]),
-	.I(ddrphy_dq_o14),
-	.T((~(~ddrphy_dq_oe_n14))),
-	.O(ddrphy_dq_i14)
+	// Inputs.
+	.B (ddram_dq[14]),
+	.I (ddrphy_dq_o14),
+	.T ((~(~ddrphy_dq_oe_n14))),
+
+	// Outputs.
+	.O (ddrphy_dq_i14)
 );
 
+//------------------------------------------------------------------------------
+// Instance TRELLIS_IO_17 of TRELLIS_IO Module.
+//------------------------------------------------------------------------------
 TRELLIS_IO #(
-	.DIR("BIDIR")
+	// Parameters.
+	.DIR ("BIDIR")
 ) TRELLIS_IO_17 (
-	.B(ddram_dq[15]),
-	.I(ddrphy_dq_o15),
-	.T((~(~ddrphy_dq_oe_n15))),
-	.O(ddrphy_dq_i15)
+	// Inputs.
+	.B (ddram_dq[15]),
+	.I (ddrphy_dq_o15),
+	.T ((~(~ddrphy_dq_oe_n15))),
+
+	// Outputs.
+	.O (ddrphy_dq_i15)
 );
 
 endmodule
 
 // -----------------------------------------------------------------------------
-//  Auto-Generated by LiteX on 2022-10-28 19:01:26.
+//  Auto-Generated by LiteX on 2024-04-01 10:12:11.
 //------------------------------------------------------------------------------
diff --git a/litedram/generated/sim/litedram_core.init b/litedram/generated/sim/litedram_core.init
index 71d4b3f..7cf9fda 100644
--- a/litedram/generated/sim/litedram_core.init
+++ b/litedram/generated/sim/litedram_core.init
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diff --git a/litedram/generated/sim/litedram_core.v b/litedram/generated/sim/litedram_core.v
index 71c1017..4b6cea9 100644
--- a/litedram/generated/sim/litedram_core.v
+++ b/litedram/generated/sim/litedram_core.v
@@ -8,2028 +8,2211 @@
 //
 // Filename   : litedram_core.v
 // Device     : 
-// LiteX sha1 : --------
-// Date       : 2022-10-28 19:01:27
+// LiteX sha1 : 87137c30
+// Date       : 2024-04-01 10:12:12
 //------------------------------------------------------------------------------
 
+`timescale 1ns / 1ps
 
 //------------------------------------------------------------------------------
 // Module
 //------------------------------------------------------------------------------
 
 module litedram_core (
-    input  wire          sim_trace,
     input  wire          clk,
     output wire          init_done,
     output wire          init_error,
-    input  wire   [29:0] wb_ctrl_adr,
-    input  wire   [31:0] wb_ctrl_dat_w,
-    output wire   [31:0] wb_ctrl_dat_r,
-    input  wire    [3:0] wb_ctrl_sel,
-    input  wire          wb_ctrl_cyc,
-    input  wire          wb_ctrl_stb,
-    output wire          wb_ctrl_ack,
-    input  wire          wb_ctrl_we,
-    input  wire    [2:0] wb_ctrl_cti,
-    input  wire    [1:0] wb_ctrl_bte,
-    output wire          wb_ctrl_err,
+    input  wire          sim_trace,
     output wire          user_clk,
-    output wire          user_rst,
-    input  wire          user_port_native_0_cmd_valid,
+    input  wire   [23:0] user_port_native_0_cmd_addr,
     output wire          user_port_native_0_cmd_ready,
+    input  wire          user_port_native_0_cmd_valid,
     input  wire          user_port_native_0_cmd_we,
-    input  wire   [23:0] user_port_native_0_cmd_addr,
-    input  wire          user_port_native_0_wdata_valid,
+    output wire  [127:0] user_port_native_0_rdata_data,
+    input  wire          user_port_native_0_rdata_ready,
+    output wire          user_port_native_0_rdata_valid,
+    input  wire  [127:0] user_port_native_0_wdata_data,
     output wire          user_port_native_0_wdata_ready,
+    input  wire          user_port_native_0_wdata_valid,
     input  wire   [15:0] user_port_native_0_wdata_we,
-    input  wire  [127:0] user_port_native_0_wdata_data,
-    output wire          user_port_native_0_rdata_valid,
-    input  wire          user_port_native_0_rdata_ready,
-    output wire  [127:0] user_port_native_0_rdata_data
+    output wire          user_rst,
+    output wire          wb_ctrl_ack,
+    input  wire   [29:0] wb_ctrl_adr,
+    input  wire    [1:0] wb_ctrl_bte,
+    input  wire    [2:0] wb_ctrl_cti,
+    input  wire          wb_ctrl_cyc,
+    output wire   [31:0] wb_ctrl_dat_r,
+    input  wire   [31:0] wb_ctrl_dat_w,
+    output wire          wb_ctrl_err,
+    input  wire    [3:0] wb_ctrl_sel,
+    input  wire          wb_ctrl_stb,
+    input  wire          wb_ctrl_we
 );
 
 
+//------------------------------------------------------------------------------
+// Hierarchy
+//------------------------------------------------------------------------------
+
+/*
+LiteDRAMCore
+└─── bus (SoCBusHandler)
+│    └─── _interconnect (InterconnectPointToPoint)
+└─── csr (SoCCSRHandler)
+└─── irq (SoCIRQHandler)
+└─── cpu (CPUNone)
+└─── crg (CRG)
+└─── ddrphy (SDRAMPHYModel)
+│    └─── dfiphasemodel_0* (DFIPhaseModel)
+│    └─── dfiphasemodel_1* (DFIPhaseModel)
+│    └─── dfiphasemodel_2* (DFIPhaseModel)
+│    └─── dfiphasemodel_3* (DFIPhaseModel)
+│    └─── bankmodel_0* (BankModel)
+│    └─── bankmodel_1* (BankModel)
+│    └─── bankmodel_2* (BankModel)
+│    └─── bankmodel_3* (BankModel)
+│    └─── bankmodel_4* (BankModel)
+│    └─── bankmodel_5* (BankModel)
+│    └─── bankmodel_6* (BankModel)
+│    └─── bankmodel_7* (BankModel)
+└─── sdram (LiteDRAMCore)
+│    └─── dfii (DFIInjector)
+│    │    └─── pi0 (PhaseInjector)
+│    │    └─── pi1 (PhaseInjector)
+│    │    └─── pi2 (PhaseInjector)
+│    │    └─── pi3 (PhaseInjector)
+│    └─── controller (LiteDRAMController)
+│    │    └─── refresher (Refresher)
+│    │    │    └─── timer (RefreshTimer)
+│    │    │    └─── postponer (RefreshPostponer)
+│    │    │    └─── sequencer (RefreshSequencer)
+│    │    │    │    └─── refreshexecuter_0* (RefreshExecuter)
+│    │    │    └─── zqcs_timer (RefreshTimer)
+│    │    │    └─── zqs_executer (ZQCSExecuter)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_0* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_1* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_2* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_3* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_4* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_5* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_6* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_7* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── multiplexer (Multiplexer)
+│    │    │    └─── choose_cmd (_CommandChooser)
+│    │    │    │    └─── roundrobin_0* (RoundRobin)
+│    │    │    └─── choose_req (_CommandChooser)
+│    │    │    │    └─── roundrobin_0* (RoundRobin)
+│    │    │    └─── _steerer_0* (_Steerer)
+│    │    │    └─── trrdcon (tXXDController)
+│    │    │    └─── tfawcon (tFAWController)
+│    │    │    └─── tccdcon (tXXDController)
+│    │    │    └─── twtrcon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    └─── crossbar (LiteDRAMCrossbar)
+│    │    └─── roundrobin_0* (RoundRobin)
+│    │    └─── roundrobin_1* (RoundRobin)
+│    │    └─── roundrobin_2* (RoundRobin)
+│    │    └─── roundrobin_3* (RoundRobin)
+│    │    └─── roundrobin_4* (RoundRobin)
+│    │    └─── roundrobin_5* (RoundRobin)
+│    │    └─── roundrobin_6* (RoundRobin)
+│    │    └─── roundrobin_7* (RoundRobin)
+└─── ddrctrl (LiteDRAMCoreControl)
+└─── csr_bridge (Wishbone2CSR)
+│    └─── fsm (FSM)
+└─── csr_bankarray (CSRBankArray)
+│    └─── csrbank_0* (CSRBank)
+│    │    └─── csrstorage_0* (CSRStorage)
+│    │    └─── csrstorage_1* (CSRStorage)
+│    └─── csrbank_1* (CSRBank)
+│    │    └─── csrstorage_0* (CSRStorage)
+│    │    └─── csrstorage_1* (CSRStorage)
+│    │    └─── csrstorage_2* (CSRStorage)
+│    │    └─── csrstorage_3* (CSRStorage)
+│    │    └─── csrstorage_4* (CSRStorage)
+│    │    └─── csrstatus_0* (CSRStatus)
+│    │    └─── csrstorage_5* (CSRStorage)
+│    │    └─── csrstorage_6* (CSRStorage)
+│    │    └─── csrstorage_7* (CSRStorage)
+│    │    └─── csrstorage_8* (CSRStorage)
+│    │    └─── csrstatus_1* (CSRStatus)
+│    │    └─── csrstorage_9* (CSRStorage)
+│    │    └─── csrstorage_10* (CSRStorage)
+│    │    └─── csrstorage_11* (CSRStorage)
+│    │    └─── csrstorage_12* (CSRStorage)
+│    │    └─── csrstatus_2* (CSRStatus)
+│    │    └─── csrstorage_13* (CSRStorage)
+│    │    └─── csrstorage_14* (CSRStorage)
+│    │    └─── csrstorage_15* (CSRStorage)
+│    │    └─── csrstorage_16* (CSRStorage)
+│    │    └─── csrstatus_3* (CSRStatus)
+└─── csr_interconnect (InterconnectShared)
+* : Generated name.
+[]: BlackBox.
+*/
+
 //------------------------------------------------------------------------------
 // Signals
 //------------------------------------------------------------------------------
 
-wire          sys_clk;
-wire          sys_rst;
+wire   [13:0] adr;
+reg     [3:0] bankmachine0_next_state = 4'd0;
+reg     [3:0] bankmachine0_state = 4'd0;
+reg     [3:0] bankmachine1_next_state = 4'd0;
+reg     [3:0] bankmachine1_state = 4'd0;
+reg     [3:0] bankmachine2_next_state = 4'd0;
+reg     [3:0] bankmachine2_state = 4'd0;
+reg     [3:0] bankmachine3_next_state = 4'd0;
+reg     [3:0] bankmachine3_state = 4'd0;
+reg     [3:0] bankmachine4_next_state = 4'd0;
+reg     [3:0] bankmachine4_state = 4'd0;
+reg     [3:0] bankmachine5_next_state = 4'd0;
+reg     [3:0] bankmachine5_state = 4'd0;
+reg     [3:0] bankmachine6_next_state = 4'd0;
+reg     [3:0] bankmachine6_state = 4'd0;
+reg     [3:0] bankmachine7_next_state = 4'd0;
+reg     [3:0] bankmachine7_state = 4'd0;
+wire          csrbank0_init_done0_r;
+reg           csrbank0_init_done0_re = 1'd0;
+wire          csrbank0_init_done0_w;
+reg           csrbank0_init_done0_we = 1'd0;
+wire          csrbank0_init_error0_r;
+reg           csrbank0_init_error0_re = 1'd0;
+wire          csrbank0_init_error0_w;
+reg           csrbank0_init_error0_we = 1'd0;
+wire          csrbank0_sel;
+wire    [3:0] csrbank1_dfii_control0_r;
+reg           csrbank1_dfii_control0_re = 1'd0;
+wire    [3:0] csrbank1_dfii_control0_w;
+reg           csrbank1_dfii_control0_we = 1'd0;
+wire   [13:0] csrbank1_dfii_pi0_address0_r;
+reg           csrbank1_dfii_pi0_address0_re = 1'd0;
+wire   [13:0] csrbank1_dfii_pi0_address0_w;
+reg           csrbank1_dfii_pi0_address0_we = 1'd0;
+wire    [2:0] csrbank1_dfii_pi0_baddress0_r;
+reg           csrbank1_dfii_pi0_baddress0_re = 1'd0;
+wire    [2:0] csrbank1_dfii_pi0_baddress0_w;
+reg           csrbank1_dfii_pi0_baddress0_we = 1'd0;
+wire    [7:0] csrbank1_dfii_pi0_command0_r;
+reg           csrbank1_dfii_pi0_command0_re = 1'd0;
+wire    [7:0] csrbank1_dfii_pi0_command0_w;
+reg           csrbank1_dfii_pi0_command0_we = 1'd0;
+wire   [31:0] csrbank1_dfii_pi0_rddata_r;
+reg           csrbank1_dfii_pi0_rddata_re = 1'd0;
+wire   [31:0] csrbank1_dfii_pi0_rddata_w;
+reg           csrbank1_dfii_pi0_rddata_we = 1'd0;
+wire   [31:0] csrbank1_dfii_pi0_wrdata0_r;
+reg           csrbank1_dfii_pi0_wrdata0_re = 1'd0;
+wire   [31:0] csrbank1_dfii_pi0_wrdata0_w;
+reg           csrbank1_dfii_pi0_wrdata0_we = 1'd0;
+wire   [13:0] csrbank1_dfii_pi1_address0_r;
+reg           csrbank1_dfii_pi1_address0_re = 1'd0;
+wire   [13:0] csrbank1_dfii_pi1_address0_w;
+reg           csrbank1_dfii_pi1_address0_we = 1'd0;
+wire    [2:0] csrbank1_dfii_pi1_baddress0_r;
+reg           csrbank1_dfii_pi1_baddress0_re = 1'd0;
+wire    [2:0] csrbank1_dfii_pi1_baddress0_w;
+reg           csrbank1_dfii_pi1_baddress0_we = 1'd0;
+wire    [7:0] csrbank1_dfii_pi1_command0_r;
+reg           csrbank1_dfii_pi1_command0_re = 1'd0;
+wire    [7:0] csrbank1_dfii_pi1_command0_w;
+reg           csrbank1_dfii_pi1_command0_we = 1'd0;
+wire   [31:0] csrbank1_dfii_pi1_rddata_r;
+reg           csrbank1_dfii_pi1_rddata_re = 1'd0;
+wire   [31:0] csrbank1_dfii_pi1_rddata_w;
+reg           csrbank1_dfii_pi1_rddata_we = 1'd0;
+wire   [31:0] csrbank1_dfii_pi1_wrdata0_r;
+reg           csrbank1_dfii_pi1_wrdata0_re = 1'd0;
+wire   [31:0] csrbank1_dfii_pi1_wrdata0_w;
+reg           csrbank1_dfii_pi1_wrdata0_we = 1'd0;
+wire   [13:0] csrbank1_dfii_pi2_address0_r;
+reg           csrbank1_dfii_pi2_address0_re = 1'd0;
+wire   [13:0] csrbank1_dfii_pi2_address0_w;
+reg           csrbank1_dfii_pi2_address0_we = 1'd0;
+wire    [2:0] csrbank1_dfii_pi2_baddress0_r;
+reg           csrbank1_dfii_pi2_baddress0_re = 1'd0;
+wire    [2:0] csrbank1_dfii_pi2_baddress0_w;
+reg           csrbank1_dfii_pi2_baddress0_we = 1'd0;
+wire    [7:0] csrbank1_dfii_pi2_command0_r;
+reg           csrbank1_dfii_pi2_command0_re = 1'd0;
+wire    [7:0] csrbank1_dfii_pi2_command0_w;
+reg           csrbank1_dfii_pi2_command0_we = 1'd0;
+wire   [31:0] csrbank1_dfii_pi2_rddata_r;
+reg           csrbank1_dfii_pi2_rddata_re = 1'd0;
+wire   [31:0] csrbank1_dfii_pi2_rddata_w;
+reg           csrbank1_dfii_pi2_rddata_we = 1'd0;
+wire   [31:0] csrbank1_dfii_pi2_wrdata0_r;
+reg           csrbank1_dfii_pi2_wrdata0_re = 1'd0;
+wire   [31:0] csrbank1_dfii_pi2_wrdata0_w;
+reg           csrbank1_dfii_pi2_wrdata0_we = 1'd0;
+wire   [13:0] csrbank1_dfii_pi3_address0_r;
+reg           csrbank1_dfii_pi3_address0_re = 1'd0;
+wire   [13:0] csrbank1_dfii_pi3_address0_w;
+reg           csrbank1_dfii_pi3_address0_we = 1'd0;
+wire    [2:0] csrbank1_dfii_pi3_baddress0_r;
+reg           csrbank1_dfii_pi3_baddress0_re = 1'd0;
+wire    [2:0] csrbank1_dfii_pi3_baddress0_w;
+reg           csrbank1_dfii_pi3_baddress0_we = 1'd0;
+wire    [7:0] csrbank1_dfii_pi3_command0_r;
+reg           csrbank1_dfii_pi3_command0_re = 1'd0;
+wire    [7:0] csrbank1_dfii_pi3_command0_w;
+reg           csrbank1_dfii_pi3_command0_we = 1'd0;
+wire   [31:0] csrbank1_dfii_pi3_rddata_r;
+reg           csrbank1_dfii_pi3_rddata_re = 1'd0;
+wire   [31:0] csrbank1_dfii_pi3_rddata_w;
+reg           csrbank1_dfii_pi3_rddata_we = 1'd0;
+wire   [31:0] csrbank1_dfii_pi3_wrdata0_r;
+reg           csrbank1_dfii_pi3_wrdata0_re = 1'd0;
+wire   [31:0] csrbank1_dfii_pi3_wrdata0_w;
+reg           csrbank1_dfii_pi3_wrdata0_we = 1'd0;
+wire          csrbank1_sel;
+wire   [31:0] dat_r;
+wire   [31:0] dat_w;
+reg           interface0_ack = 1'd0;
+wire   [29:0] interface0_adr;
+wire   [13:0] interface0_bank_bus_adr;
+reg    [31:0] interface0_bank_bus_dat_r = 32'd0;
+wire   [31:0] interface0_bank_bus_dat_w;
+wire          interface0_bank_bus_we;
+wire    [1:0] interface0_bte;
+wire    [2:0] interface0_cti;
+wire          interface0_cyc;
+reg    [31:0] interface0_dat_r = 32'd0;
+wire   [31:0] interface0_dat_w;
+reg           interface0_err = 1'd0;
+wire    [3:0] interface0_sel;
+wire          interface0_stb;
+wire          interface0_we;
+reg    [13:0] interface1_adr = 14'd0;
+reg    [13:0] interface1_adr_next_value1 = 14'd0;
+reg           interface1_adr_next_value_ce1 = 1'd0;
+wire   [13:0] interface1_bank_bus_adr;
+reg    [31:0] interface1_bank_bus_dat_r = 32'd0;
+wire   [31:0] interface1_bank_bus_dat_w;
+wire          interface1_bank_bus_we;
+wire   [31:0] interface1_dat_r;
+reg    [31:0] interface1_dat_w = 32'd0;
+reg    [31:0] interface1_dat_w_next_value0 = 32'd0;
+reg           interface1_dat_w_next_value_ce0 = 1'd0;
+reg           interface1_we = 1'd0;
+reg           interface1_we_next_value2 = 1'd0;
+reg           interface1_we_next_value_ce2 = 1'd0;
+reg           locked0 = 1'd0;
+reg           locked1 = 1'd0;
+reg           locked2 = 1'd0;
+reg           locked3 = 1'd0;
+reg           locked4 = 1'd0;
+reg           locked5 = 1'd0;
+reg           locked6 = 1'd0;
+reg           locked7 = 1'd0;
+reg     [3:0] multiplexer_next_state = 4'd0;
+reg     [3:0] multiplexer_state = 4'd0;
+reg           new_master_rdata_valid0 = 1'd0;
+reg           new_master_rdata_valid1 = 1'd0;
+reg           new_master_rdata_valid2 = 1'd0;
+reg           new_master_rdata_valid3 = 1'd0;
+reg           new_master_rdata_valid4 = 1'd0;
+reg           new_master_rdata_valid5 = 1'd0;
+reg           new_master_rdata_valid6 = 1'd0;
+reg           new_master_rdata_valid7 = 1'd0;
+reg           new_master_rdata_valid8 = 1'd0;
+reg           new_master_wdata_ready0 = 1'd0;
+reg           new_master_wdata_ready1 = 1'd0;
+reg     [1:0] next_state = 2'd0;
 wire          por_clk;
-reg           soc_int_rst = 1'd1;
-wire   [13:0] soc_ddrphy_dfi_p0_address;
-wire    [2:0] soc_ddrphy_dfi_p0_bank;
-wire          soc_ddrphy_dfi_p0_cas_n;
-wire          soc_ddrphy_dfi_p0_cs_n;
-wire          soc_ddrphy_dfi_p0_ras_n;
-wire          soc_ddrphy_dfi_p0_we_n;
-wire          soc_ddrphy_dfi_p0_cke;
-wire          soc_ddrphy_dfi_p0_odt;
-wire          soc_ddrphy_dfi_p0_reset_n;
-wire          soc_ddrphy_dfi_p0_act_n;
-wire   [31:0] soc_ddrphy_dfi_p0_wrdata;
-wire          soc_ddrphy_dfi_p0_wrdata_en;
-wire    [3:0] soc_ddrphy_dfi_p0_wrdata_mask;
-wire          soc_ddrphy_dfi_p0_rddata_en;
-wire   [31:0] soc_ddrphy_dfi_p0_rddata;
-wire          soc_ddrphy_dfi_p0_rddata_valid;
-wire   [13:0] soc_ddrphy_dfi_p1_address;
-wire    [2:0] soc_ddrphy_dfi_p1_bank;
-wire          soc_ddrphy_dfi_p1_cas_n;
-wire          soc_ddrphy_dfi_p1_cs_n;
-wire          soc_ddrphy_dfi_p1_ras_n;
-wire          soc_ddrphy_dfi_p1_we_n;
-wire          soc_ddrphy_dfi_p1_cke;
-wire          soc_ddrphy_dfi_p1_odt;
-wire          soc_ddrphy_dfi_p1_reset_n;
-wire          soc_ddrphy_dfi_p1_act_n;
-wire   [31:0] soc_ddrphy_dfi_p1_wrdata;
-wire          soc_ddrphy_dfi_p1_wrdata_en;
-wire    [3:0] soc_ddrphy_dfi_p1_wrdata_mask;
-wire          soc_ddrphy_dfi_p1_rddata_en;
-wire   [31:0] soc_ddrphy_dfi_p1_rddata;
-wire          soc_ddrphy_dfi_p1_rddata_valid;
-wire   [13:0] soc_ddrphy_dfi_p2_address;
-wire    [2:0] soc_ddrphy_dfi_p2_bank;
-wire          soc_ddrphy_dfi_p2_cas_n;
-wire          soc_ddrphy_dfi_p2_cs_n;
-wire          soc_ddrphy_dfi_p2_ras_n;
-wire          soc_ddrphy_dfi_p2_we_n;
-wire          soc_ddrphy_dfi_p2_cke;
-wire          soc_ddrphy_dfi_p2_odt;
-wire          soc_ddrphy_dfi_p2_reset_n;
-wire          soc_ddrphy_dfi_p2_act_n;
-wire   [31:0] soc_ddrphy_dfi_p2_wrdata;
-wire          soc_ddrphy_dfi_p2_wrdata_en;
-wire    [3:0] soc_ddrphy_dfi_p2_wrdata_mask;
-wire          soc_ddrphy_dfi_p2_rddata_en;
-wire   [31:0] soc_ddrphy_dfi_p2_rddata;
-wire          soc_ddrphy_dfi_p2_rddata_valid;
-wire   [13:0] soc_ddrphy_dfi_p3_address;
-wire    [2:0] soc_ddrphy_dfi_p3_bank;
-wire          soc_ddrphy_dfi_p3_cas_n;
-wire          soc_ddrphy_dfi_p3_cs_n;
-wire          soc_ddrphy_dfi_p3_ras_n;
-wire          soc_ddrphy_dfi_p3_we_n;
-wire          soc_ddrphy_dfi_p3_cke;
-wire          soc_ddrphy_dfi_p3_odt;
-wire          soc_ddrphy_dfi_p3_reset_n;
-wire          soc_ddrphy_dfi_p3_act_n;
-wire   [31:0] soc_ddrphy_dfi_p3_wrdata;
-wire          soc_ddrphy_dfi_p3_wrdata_en;
-wire    [3:0] soc_ddrphy_dfi_p3_wrdata_mask;
-wire          soc_ddrphy_dfi_p3_rddata_en;
-wire   [31:0] soc_ddrphy_dfi_p3_rddata;
-wire          soc_ddrphy_dfi_p3_rddata_valid;
-reg           soc_ddrphy_dfiphasemodel0_activate = 1'd0;
-reg           soc_ddrphy_dfiphasemodel0_precharge = 1'd0;
-reg           soc_ddrphy_dfiphasemodel0_write = 1'd0;
-reg           soc_ddrphy_dfiphasemodel0_read = 1'd0;
-reg           soc_ddrphy_dfiphasemodel1_activate = 1'd0;
-reg           soc_ddrphy_dfiphasemodel1_precharge = 1'd0;
-reg           soc_ddrphy_dfiphasemodel1_write = 1'd0;
-reg           soc_ddrphy_dfiphasemodel1_read = 1'd0;
-reg           soc_ddrphy_dfiphasemodel2_activate = 1'd0;
-reg           soc_ddrphy_dfiphasemodel2_precharge = 1'd0;
-reg           soc_ddrphy_dfiphasemodel2_write = 1'd0;
-reg           soc_ddrphy_dfiphasemodel2_read = 1'd0;
-reg           soc_ddrphy_dfiphasemodel3_activate = 1'd0;
-reg           soc_ddrphy_dfiphasemodel3_precharge = 1'd0;
-reg           soc_ddrphy_dfiphasemodel3_write = 1'd0;
-reg           soc_ddrphy_dfiphasemodel3_read = 1'd0;
-reg           soc_ddrphy_bankmodel0_activate = 1'd0;
-reg    [13:0] soc_ddrphy_bankmodel0_activate_row = 14'd0;
-reg           soc_ddrphy_bankmodel0_precharge = 1'd0;
-wire          soc_ddrphy_bankmodel0_write;
-wire    [9:0] soc_ddrphy_bankmodel0_write_col;
-wire  [127:0] soc_ddrphy_bankmodel0_write_data;
-wire   [15:0] soc_ddrphy_bankmodel0_write_mask;
-reg           soc_ddrphy_bankmodel0_read = 1'd0;
-reg     [9:0] soc_ddrphy_bankmodel0_read_col = 10'd0;
-reg   [127:0] soc_ddrphy_bankmodel0_read_data = 128'd0;
-reg           soc_ddrphy_bankmodel0_active = 1'd0;
-reg    [13:0] soc_ddrphy_bankmodel0_row = 14'd0;
-reg    [20:0] soc_ddrphy_bankmodel0_write_port_adr = 21'd0;
-wire  [127:0] soc_ddrphy_bankmodel0_write_port_dat_r;
-reg    [15:0] soc_ddrphy_bankmodel0_write_port_we = 16'd0;
-reg   [127:0] soc_ddrphy_bankmodel0_write_port_dat_w = 128'd0;
-reg    [20:0] soc_ddrphy_bankmodel0_read_port_adr = 21'd0;
-wire  [127:0] soc_ddrphy_bankmodel0_read_port_dat_r;
-wire   [20:0] soc_ddrphy_bankmodel0_wraddr;
-wire   [20:0] soc_ddrphy_bankmodel0_rdaddr;
-reg           soc_ddrphy_bankmodel1_activate = 1'd0;
-reg    [13:0] soc_ddrphy_bankmodel1_activate_row = 14'd0;
-reg           soc_ddrphy_bankmodel1_precharge = 1'd0;
-wire          soc_ddrphy_bankmodel1_write;
-wire    [9:0] soc_ddrphy_bankmodel1_write_col;
-wire  [127:0] soc_ddrphy_bankmodel1_write_data;
-wire   [15:0] soc_ddrphy_bankmodel1_write_mask;
-reg           soc_ddrphy_bankmodel1_read = 1'd0;
-reg     [9:0] soc_ddrphy_bankmodel1_read_col = 10'd0;
-reg   [127:0] soc_ddrphy_bankmodel1_read_data = 128'd0;
-reg           soc_ddrphy_bankmodel1_active = 1'd0;
-reg    [13:0] soc_ddrphy_bankmodel1_row = 14'd0;
-reg    [20:0] soc_ddrphy_bankmodel1_write_port_adr = 21'd0;
-wire  [127:0] soc_ddrphy_bankmodel1_write_port_dat_r;
-reg    [15:0] soc_ddrphy_bankmodel1_write_port_we = 16'd0;
-reg   [127:0] soc_ddrphy_bankmodel1_write_port_dat_w = 128'd0;
-reg    [20:0] soc_ddrphy_bankmodel1_read_port_adr = 21'd0;
-wire  [127:0] soc_ddrphy_bankmodel1_read_port_dat_r;
-wire   [20:0] soc_ddrphy_bankmodel1_wraddr;
+reg     [1:0] refresher_next_state = 2'd0;
+reg     [1:0] refresher_state = 2'd0;
+reg           rhs_self0 = 1'd0;
+reg    [13:0] rhs_self1 = 14'd0;
+reg           rhs_self10 = 1'd0;
+reg           rhs_self11 = 1'd0;
+reg    [20:0] rhs_self12 = 21'd0;
+reg           rhs_self13 = 1'd0;
+reg           rhs_self14 = 1'd0;
+reg    [20:0] rhs_self15 = 21'd0;
+reg           rhs_self16 = 1'd0;
+reg           rhs_self17 = 1'd0;
+reg    [20:0] rhs_self18 = 21'd0;
+reg           rhs_self19 = 1'd0;
+reg     [2:0] rhs_self2 = 3'd0;
+reg           rhs_self20 = 1'd0;
+reg    [20:0] rhs_self21 = 21'd0;
+reg           rhs_self22 = 1'd0;
+reg           rhs_self23 = 1'd0;
+reg    [20:0] rhs_self24 = 21'd0;
+reg           rhs_self25 = 1'd0;
+reg           rhs_self26 = 1'd0;
+reg    [20:0] rhs_self27 = 21'd0;
+reg           rhs_self28 = 1'd0;
+reg           rhs_self29 = 1'd0;
+reg           rhs_self3 = 1'd0;
+reg    [20:0] rhs_self30 = 21'd0;
+reg           rhs_self31 = 1'd0;
+reg           rhs_self32 = 1'd0;
+reg    [20:0] rhs_self33 = 21'd0;
+reg           rhs_self34 = 1'd0;
+reg           rhs_self35 = 1'd0;
+reg           rhs_self4 = 1'd0;
+reg           rhs_self5 = 1'd0;
+reg           rhs_self6 = 1'd0;
+reg    [13:0] rhs_self7 = 14'd0;
+reg     [2:0] rhs_self8 = 3'd0;
+reg           rhs_self9 = 1'd0;
+wire          roundrobin0_ce;
+wire          roundrobin0_grant;
+wire          roundrobin0_request;
+wire          roundrobin1_ce;
+wire          roundrobin1_grant;
+wire          roundrobin1_request;
+wire          roundrobin2_ce;
+wire          roundrobin2_grant;
+wire          roundrobin2_request;
+wire          roundrobin3_ce;
+wire          roundrobin3_grant;
+wire          roundrobin3_request;
+wire          roundrobin4_ce;
+wire          roundrobin4_grant;
+wire          roundrobin4_request;
+wire          roundrobin5_ce;
+wire          roundrobin5_grant;
+wire          roundrobin5_request;
+wire          roundrobin6_ce;
+wire          roundrobin6_grant;
+wire          roundrobin6_request;
+wire          roundrobin7_ce;
+wire          roundrobin7_grant;
+wire          roundrobin7_request;
+reg     [2:0] self0 = 3'd0;
+reg    [13:0] self1 = 14'd0;
+reg           self10 = 1'd0;
+reg           self11 = 1'd0;
+reg           self12 = 1'd0;
+reg           self13 = 1'd0;
+reg     [2:0] self14 = 3'd0;
+reg    [13:0] self15 = 14'd0;
+reg           self16 = 1'd0;
+reg           self17 = 1'd0;
+reg           self18 = 1'd0;
+reg           self19 = 1'd0;
+reg           self2 = 1'd0;
+reg           self20 = 1'd0;
+reg     [2:0] self21 = 3'd0;
+reg    [13:0] self22 = 14'd0;
+reg           self23 = 1'd0;
+reg           self24 = 1'd0;
+reg           self25 = 1'd0;
+reg           self26 = 1'd0;
+reg           self27 = 1'd0;
+reg           self3 = 1'd0;
+reg           self4 = 1'd0;
+reg           self5 = 1'd0;
+reg           self6 = 1'd0;
+reg     [2:0] self7 = 3'd0;
+reg    [13:0] self8 = 14'd0;
+reg           self9 = 1'd0;
+wire   [24:0] slice_proxy0;
+wire   [24:0] slice_proxy1;
+wire   [24:0] slice_proxy10;
+wire   [24:0] slice_proxy11;
+wire   [24:0] slice_proxy12;
+wire   [24:0] slice_proxy13;
+wire   [24:0] slice_proxy14;
+wire   [24:0] slice_proxy15;
+wire   [24:0] slice_proxy2;
+wire   [24:0] slice_proxy3;
+wire   [24:0] slice_proxy4;
+wire   [24:0] slice_proxy5;
+wire   [24:0] slice_proxy6;
+wire   [24:0] slice_proxy7;
+wire   [24:0] slice_proxy8;
+wire   [24:0] slice_proxy9;
+reg     [3:0] soc_ddrphy_activates0 = 4'd0;
+reg     [3:0] soc_ddrphy_activates1 = 4'd0;
+reg     [3:0] soc_ddrphy_activates2 = 4'd0;
+reg     [3:0] soc_ddrphy_activates3 = 4'd0;
+reg     [3:0] soc_ddrphy_activates4 = 4'd0;
+reg     [3:0] soc_ddrphy_activates5 = 4'd0;
+reg     [3:0] soc_ddrphy_activates6 = 4'd0;
+reg     [3:0] soc_ddrphy_activates7 = 4'd0;
+reg           soc_ddrphy_bank_write0 = 1'd0;
+reg           soc_ddrphy_bank_write1 = 1'd0;
+reg           soc_ddrphy_bank_write2 = 1'd0;
+reg           soc_ddrphy_bank_write3 = 1'd0;
+reg           soc_ddrphy_bank_write4 = 1'd0;
+reg           soc_ddrphy_bank_write5 = 1'd0;
+reg           soc_ddrphy_bank_write6 = 1'd0;
+reg           soc_ddrphy_bank_write7 = 1'd0;
+reg     [9:0] soc_ddrphy_bank_write_col0 = 10'd0;
+reg     [9:0] soc_ddrphy_bank_write_col1 = 10'd0;
+reg     [9:0] soc_ddrphy_bank_write_col2 = 10'd0;
+reg     [9:0] soc_ddrphy_bank_write_col3 = 10'd0;
+reg     [9:0] soc_ddrphy_bank_write_col4 = 10'd0;
+reg     [9:0] soc_ddrphy_bank_write_col5 = 10'd0;
+reg     [9:0] soc_ddrphy_bank_write_col6 = 10'd0;
+reg     [9:0] soc_ddrphy_bank_write_col7 = 10'd0;
+reg           soc_ddrphy_bankmodel0_activate = 1'd0;
+reg    [13:0] soc_ddrphy_bankmodel0_activate_row = 14'd0;
+reg           soc_ddrphy_bankmodel0_active = 1'd0;
+reg           soc_ddrphy_bankmodel0_precharge = 1'd0;
+wire   [20:0] soc_ddrphy_bankmodel0_rdaddr;
+reg           soc_ddrphy_bankmodel0_read = 1'd0;
+reg     [9:0] soc_ddrphy_bankmodel0_read_col = 10'd0;
+reg   [127:0] soc_ddrphy_bankmodel0_read_data = 128'd0;
+reg    [20:0] soc_ddrphy_bankmodel0_read_port_adr = 21'd0;
+wire  [127:0] soc_ddrphy_bankmodel0_read_port_dat_r;
+reg    [13:0] soc_ddrphy_bankmodel0_row = 14'd0;
+wire   [20:0] soc_ddrphy_bankmodel0_wraddr;
+wire          soc_ddrphy_bankmodel0_write;
+wire    [9:0] soc_ddrphy_bankmodel0_write_col;
+wire  [127:0] soc_ddrphy_bankmodel0_write_data;
+wire   [15:0] soc_ddrphy_bankmodel0_write_mask;
+reg    [20:0] soc_ddrphy_bankmodel0_write_port_adr = 21'd0;
+wire  [127:0] soc_ddrphy_bankmodel0_write_port_dat_r;
+reg   [127:0] soc_ddrphy_bankmodel0_write_port_dat_w = 128'd0;
+reg    [15:0] soc_ddrphy_bankmodel0_write_port_we = 16'd0;
+reg           soc_ddrphy_bankmodel1_activate = 1'd0;
+reg    [13:0] soc_ddrphy_bankmodel1_activate_row = 14'd0;
+reg           soc_ddrphy_bankmodel1_active = 1'd0;
+reg           soc_ddrphy_bankmodel1_precharge = 1'd0;
 wire   [20:0] soc_ddrphy_bankmodel1_rdaddr;
+reg           soc_ddrphy_bankmodel1_read = 1'd0;
+reg     [9:0] soc_ddrphy_bankmodel1_read_col = 10'd0;
+reg   [127:0] soc_ddrphy_bankmodel1_read_data = 128'd0;
+reg    [20:0] soc_ddrphy_bankmodel1_read_port_adr = 21'd0;
+wire  [127:0] soc_ddrphy_bankmodel1_read_port_dat_r;
+reg    [13:0] soc_ddrphy_bankmodel1_row = 14'd0;
+wire   [20:0] soc_ddrphy_bankmodel1_wraddr;
+wire          soc_ddrphy_bankmodel1_write;
+wire    [9:0] soc_ddrphy_bankmodel1_write_col;
+wire  [127:0] soc_ddrphy_bankmodel1_write_data;
+wire   [15:0] soc_ddrphy_bankmodel1_write_mask;
+reg    [20:0] soc_ddrphy_bankmodel1_write_port_adr = 21'd0;
+wire  [127:0] soc_ddrphy_bankmodel1_write_port_dat_r;
+reg   [127:0] soc_ddrphy_bankmodel1_write_port_dat_w = 128'd0;
+reg    [15:0] soc_ddrphy_bankmodel1_write_port_we = 16'd0;
 reg           soc_ddrphy_bankmodel2_activate = 1'd0;
 reg    [13:0] soc_ddrphy_bankmodel2_activate_row = 14'd0;
+reg           soc_ddrphy_bankmodel2_active = 1'd0;
 reg           soc_ddrphy_bankmodel2_precharge = 1'd0;
-wire          soc_ddrphy_bankmodel2_write;
-wire    [9:0] soc_ddrphy_bankmodel2_write_col;
-wire  [127:0] soc_ddrphy_bankmodel2_write_data;
-wire   [15:0] soc_ddrphy_bankmodel2_write_mask;
+wire   [20:0] soc_ddrphy_bankmodel2_rdaddr;
 reg           soc_ddrphy_bankmodel2_read = 1'd0;
 reg     [9:0] soc_ddrphy_bankmodel2_read_col = 10'd0;
 reg   [127:0] soc_ddrphy_bankmodel2_read_data = 128'd0;
-reg           soc_ddrphy_bankmodel2_active = 1'd0;
+reg    [20:0] soc_ddrphy_bankmodel2_read_port_adr = 21'd0;
+wire  [127:0] soc_ddrphy_bankmodel2_read_port_dat_r;
 reg    [13:0] soc_ddrphy_bankmodel2_row = 14'd0;
+wire   [20:0] soc_ddrphy_bankmodel2_wraddr;
+wire          soc_ddrphy_bankmodel2_write;
+wire    [9:0] soc_ddrphy_bankmodel2_write_col;
+wire  [127:0] soc_ddrphy_bankmodel2_write_data;
+wire   [15:0] soc_ddrphy_bankmodel2_write_mask;
 reg    [20:0] soc_ddrphy_bankmodel2_write_port_adr = 21'd0;
 wire  [127:0] soc_ddrphy_bankmodel2_write_port_dat_r;
-reg    [15:0] soc_ddrphy_bankmodel2_write_port_we = 16'd0;
 reg   [127:0] soc_ddrphy_bankmodel2_write_port_dat_w = 128'd0;
-reg    [20:0] soc_ddrphy_bankmodel2_read_port_adr = 21'd0;
-wire  [127:0] soc_ddrphy_bankmodel2_read_port_dat_r;
-wire   [20:0] soc_ddrphy_bankmodel2_wraddr;
-wire   [20:0] soc_ddrphy_bankmodel2_rdaddr;
+reg    [15:0] soc_ddrphy_bankmodel2_write_port_we = 16'd0;
 reg           soc_ddrphy_bankmodel3_activate = 1'd0;
 reg    [13:0] soc_ddrphy_bankmodel3_activate_row = 14'd0;
+reg           soc_ddrphy_bankmodel3_active = 1'd0;
 reg           soc_ddrphy_bankmodel3_precharge = 1'd0;
-wire          soc_ddrphy_bankmodel3_write;
-wire    [9:0] soc_ddrphy_bankmodel3_write_col;
-wire  [127:0] soc_ddrphy_bankmodel3_write_data;
-wire   [15:0] soc_ddrphy_bankmodel3_write_mask;
+wire   [20:0] soc_ddrphy_bankmodel3_rdaddr;
 reg           soc_ddrphy_bankmodel3_read = 1'd0;
 reg     [9:0] soc_ddrphy_bankmodel3_read_col = 10'd0;
 reg   [127:0] soc_ddrphy_bankmodel3_read_data = 128'd0;
-reg           soc_ddrphy_bankmodel3_active = 1'd0;
+reg    [20:0] soc_ddrphy_bankmodel3_read_port_adr = 21'd0;
+wire  [127:0] soc_ddrphy_bankmodel3_read_port_dat_r;
 reg    [13:0] soc_ddrphy_bankmodel3_row = 14'd0;
+wire   [20:0] soc_ddrphy_bankmodel3_wraddr;
+wire          soc_ddrphy_bankmodel3_write;
+wire    [9:0] soc_ddrphy_bankmodel3_write_col;
+wire  [127:0] soc_ddrphy_bankmodel3_write_data;
+wire   [15:0] soc_ddrphy_bankmodel3_write_mask;
 reg    [20:0] soc_ddrphy_bankmodel3_write_port_adr = 21'd0;
 wire  [127:0] soc_ddrphy_bankmodel3_write_port_dat_r;
-reg    [15:0] soc_ddrphy_bankmodel3_write_port_we = 16'd0;
 reg   [127:0] soc_ddrphy_bankmodel3_write_port_dat_w = 128'd0;
-reg    [20:0] soc_ddrphy_bankmodel3_read_port_adr = 21'd0;
-wire  [127:0] soc_ddrphy_bankmodel3_read_port_dat_r;
-wire   [20:0] soc_ddrphy_bankmodel3_wraddr;
-wire   [20:0] soc_ddrphy_bankmodel3_rdaddr;
+reg    [15:0] soc_ddrphy_bankmodel3_write_port_we = 16'd0;
 reg           soc_ddrphy_bankmodel4_activate = 1'd0;
 reg    [13:0] soc_ddrphy_bankmodel4_activate_row = 14'd0;
+reg           soc_ddrphy_bankmodel4_active = 1'd0;
 reg           soc_ddrphy_bankmodel4_precharge = 1'd0;
-wire          soc_ddrphy_bankmodel4_write;
-wire    [9:0] soc_ddrphy_bankmodel4_write_col;
-wire  [127:0] soc_ddrphy_bankmodel4_write_data;
-wire   [15:0] soc_ddrphy_bankmodel4_write_mask;
+wire   [20:0] soc_ddrphy_bankmodel4_rdaddr;
 reg           soc_ddrphy_bankmodel4_read = 1'd0;
 reg     [9:0] soc_ddrphy_bankmodel4_read_col = 10'd0;
 reg   [127:0] soc_ddrphy_bankmodel4_read_data = 128'd0;
-reg           soc_ddrphy_bankmodel4_active = 1'd0;
+reg    [20:0] soc_ddrphy_bankmodel4_read_port_adr = 21'd0;
+wire  [127:0] soc_ddrphy_bankmodel4_read_port_dat_r;
 reg    [13:0] soc_ddrphy_bankmodel4_row = 14'd0;
+wire   [20:0] soc_ddrphy_bankmodel4_wraddr;
+wire          soc_ddrphy_bankmodel4_write;
+wire    [9:0] soc_ddrphy_bankmodel4_write_col;
+wire  [127:0] soc_ddrphy_bankmodel4_write_data;
+wire   [15:0] soc_ddrphy_bankmodel4_write_mask;
 reg    [20:0] soc_ddrphy_bankmodel4_write_port_adr = 21'd0;
 wire  [127:0] soc_ddrphy_bankmodel4_write_port_dat_r;
-reg    [15:0] soc_ddrphy_bankmodel4_write_port_we = 16'd0;
 reg   [127:0] soc_ddrphy_bankmodel4_write_port_dat_w = 128'd0;
-reg    [20:0] soc_ddrphy_bankmodel4_read_port_adr = 21'd0;
-wire  [127:0] soc_ddrphy_bankmodel4_read_port_dat_r;
-wire   [20:0] soc_ddrphy_bankmodel4_wraddr;
-wire   [20:0] soc_ddrphy_bankmodel4_rdaddr;
+reg    [15:0] soc_ddrphy_bankmodel4_write_port_we = 16'd0;
 reg           soc_ddrphy_bankmodel5_activate = 1'd0;
 reg    [13:0] soc_ddrphy_bankmodel5_activate_row = 14'd0;
+reg           soc_ddrphy_bankmodel5_active = 1'd0;
 reg           soc_ddrphy_bankmodel5_precharge = 1'd0;
-wire          soc_ddrphy_bankmodel5_write;
-wire    [9:0] soc_ddrphy_bankmodel5_write_col;
-wire  [127:0] soc_ddrphy_bankmodel5_write_data;
-wire   [15:0] soc_ddrphy_bankmodel5_write_mask;
+wire   [20:0] soc_ddrphy_bankmodel5_rdaddr;
 reg           soc_ddrphy_bankmodel5_read = 1'd0;
 reg     [9:0] soc_ddrphy_bankmodel5_read_col = 10'd0;
 reg   [127:0] soc_ddrphy_bankmodel5_read_data = 128'd0;
-reg           soc_ddrphy_bankmodel5_active = 1'd0;
+reg    [20:0] soc_ddrphy_bankmodel5_read_port_adr = 21'd0;
+wire  [127:0] soc_ddrphy_bankmodel5_read_port_dat_r;
 reg    [13:0] soc_ddrphy_bankmodel5_row = 14'd0;
+wire   [20:0] soc_ddrphy_bankmodel5_wraddr;
+wire          soc_ddrphy_bankmodel5_write;
+wire    [9:0] soc_ddrphy_bankmodel5_write_col;
+wire  [127:0] soc_ddrphy_bankmodel5_write_data;
+wire   [15:0] soc_ddrphy_bankmodel5_write_mask;
 reg    [20:0] soc_ddrphy_bankmodel5_write_port_adr = 21'd0;
 wire  [127:0] soc_ddrphy_bankmodel5_write_port_dat_r;
-reg    [15:0] soc_ddrphy_bankmodel5_write_port_we = 16'd0;
 reg   [127:0] soc_ddrphy_bankmodel5_write_port_dat_w = 128'd0;
-reg    [20:0] soc_ddrphy_bankmodel5_read_port_adr = 21'd0;
-wire  [127:0] soc_ddrphy_bankmodel5_read_port_dat_r;
-wire   [20:0] soc_ddrphy_bankmodel5_wraddr;
-wire   [20:0] soc_ddrphy_bankmodel5_rdaddr;
+reg    [15:0] soc_ddrphy_bankmodel5_write_port_we = 16'd0;
 reg           soc_ddrphy_bankmodel6_activate = 1'd0;
 reg    [13:0] soc_ddrphy_bankmodel6_activate_row = 14'd0;
+reg           soc_ddrphy_bankmodel6_active = 1'd0;
 reg           soc_ddrphy_bankmodel6_precharge = 1'd0;
-wire          soc_ddrphy_bankmodel6_write;
-wire    [9:0] soc_ddrphy_bankmodel6_write_col;
-wire  [127:0] soc_ddrphy_bankmodel6_write_data;
-wire   [15:0] soc_ddrphy_bankmodel6_write_mask;
+wire   [20:0] soc_ddrphy_bankmodel6_rdaddr;
 reg           soc_ddrphy_bankmodel6_read = 1'd0;
 reg     [9:0] soc_ddrphy_bankmodel6_read_col = 10'd0;
 reg   [127:0] soc_ddrphy_bankmodel6_read_data = 128'd0;
-reg           soc_ddrphy_bankmodel6_active = 1'd0;
+reg    [20:0] soc_ddrphy_bankmodel6_read_port_adr = 21'd0;
+wire  [127:0] soc_ddrphy_bankmodel6_read_port_dat_r;
 reg    [13:0] soc_ddrphy_bankmodel6_row = 14'd0;
+wire   [20:0] soc_ddrphy_bankmodel6_wraddr;
+wire          soc_ddrphy_bankmodel6_write;
+wire    [9:0] soc_ddrphy_bankmodel6_write_col;
+wire  [127:0] soc_ddrphy_bankmodel6_write_data;
+wire   [15:0] soc_ddrphy_bankmodel6_write_mask;
 reg    [20:0] soc_ddrphy_bankmodel6_write_port_adr = 21'd0;
 wire  [127:0] soc_ddrphy_bankmodel6_write_port_dat_r;
-reg    [15:0] soc_ddrphy_bankmodel6_write_port_we = 16'd0;
 reg   [127:0] soc_ddrphy_bankmodel6_write_port_dat_w = 128'd0;
-reg    [20:0] soc_ddrphy_bankmodel6_read_port_adr = 21'd0;
-wire  [127:0] soc_ddrphy_bankmodel6_read_port_dat_r;
-wire   [20:0] soc_ddrphy_bankmodel6_wraddr;
-wire   [20:0] soc_ddrphy_bankmodel6_rdaddr;
+reg    [15:0] soc_ddrphy_bankmodel6_write_port_we = 16'd0;
 reg           soc_ddrphy_bankmodel7_activate = 1'd0;
 reg    [13:0] soc_ddrphy_bankmodel7_activate_row = 14'd0;
+reg           soc_ddrphy_bankmodel7_active = 1'd0;
 reg           soc_ddrphy_bankmodel7_precharge = 1'd0;
-wire          soc_ddrphy_bankmodel7_write;
-wire    [9:0] soc_ddrphy_bankmodel7_write_col;
-wire  [127:0] soc_ddrphy_bankmodel7_write_data;
-wire   [15:0] soc_ddrphy_bankmodel7_write_mask;
+wire   [20:0] soc_ddrphy_bankmodel7_rdaddr;
 reg           soc_ddrphy_bankmodel7_read = 1'd0;
 reg     [9:0] soc_ddrphy_bankmodel7_read_col = 10'd0;
 reg   [127:0] soc_ddrphy_bankmodel7_read_data = 128'd0;
-reg           soc_ddrphy_bankmodel7_active = 1'd0;
+reg    [20:0] soc_ddrphy_bankmodel7_read_port_adr = 21'd0;
+wire  [127:0] soc_ddrphy_bankmodel7_read_port_dat_r;
 reg    [13:0] soc_ddrphy_bankmodel7_row = 14'd0;
+wire   [20:0] soc_ddrphy_bankmodel7_wraddr;
+wire          soc_ddrphy_bankmodel7_write;
+wire    [9:0] soc_ddrphy_bankmodel7_write_col;
+wire  [127:0] soc_ddrphy_bankmodel7_write_data;
+wire   [15:0] soc_ddrphy_bankmodel7_write_mask;
 reg    [20:0] soc_ddrphy_bankmodel7_write_port_adr = 21'd0;
 wire  [127:0] soc_ddrphy_bankmodel7_write_port_dat_r;
-reg    [15:0] soc_ddrphy_bankmodel7_write_port_we = 16'd0;
 reg   [127:0] soc_ddrphy_bankmodel7_write_port_dat_w = 128'd0;
-reg    [20:0] soc_ddrphy_bankmodel7_read_port_adr = 21'd0;
-wire  [127:0] soc_ddrphy_bankmodel7_read_port_dat_r;
-wire   [20:0] soc_ddrphy_bankmodel7_wraddr;
-wire   [20:0] soc_ddrphy_bankmodel7_rdaddr;
-reg     [3:0] soc_ddrphy_activates0 = 4'd0;
-reg     [3:0] soc_ddrphy_precharges0 = 4'd0;
-reg           soc_ddrphy_bank_write0 = 1'd0;
-reg     [9:0] soc_ddrphy_bank_write_col0 = 10'd0;
-reg     [3:0] soc_ddrphy_writes0 = 4'd0;
-reg           soc_ddrphy_new_bank_write0 = 1'd0;
-reg     [9:0] soc_ddrphy_new_bank_write_col0 = 10'd0;
-reg     [3:0] soc_ddrphy_reads0 = 4'd0;
-reg     [3:0] soc_ddrphy_activates1 = 4'd0;
-reg     [3:0] soc_ddrphy_precharges1 = 4'd0;
-reg           soc_ddrphy_bank_write1 = 1'd0;
-reg     [9:0] soc_ddrphy_bank_write_col1 = 10'd0;
-reg     [3:0] soc_ddrphy_writes1 = 4'd0;
-reg           soc_ddrphy_new_bank_write1 = 1'd0;
-reg     [9:0] soc_ddrphy_new_bank_write_col1 = 10'd0;
-reg     [3:0] soc_ddrphy_reads1 = 4'd0;
-reg     [3:0] soc_ddrphy_activates2 = 4'd0;
-reg     [3:0] soc_ddrphy_precharges2 = 4'd0;
-reg           soc_ddrphy_bank_write2 = 1'd0;
-reg     [9:0] soc_ddrphy_bank_write_col2 = 10'd0;
-reg     [3:0] soc_ddrphy_writes2 = 4'd0;
-reg           soc_ddrphy_new_bank_write2 = 1'd0;
-reg     [9:0] soc_ddrphy_new_bank_write_col2 = 10'd0;
-reg     [3:0] soc_ddrphy_reads2 = 4'd0;
-reg     [3:0] soc_ddrphy_activates3 = 4'd0;
-reg     [3:0] soc_ddrphy_precharges3 = 4'd0;
-reg           soc_ddrphy_bank_write3 = 1'd0;
-reg     [9:0] soc_ddrphy_bank_write_col3 = 10'd0;
-reg     [3:0] soc_ddrphy_writes3 = 4'd0;
-reg           soc_ddrphy_new_bank_write3 = 1'd0;
-reg     [9:0] soc_ddrphy_new_bank_write_col3 = 10'd0;
-reg     [3:0] soc_ddrphy_reads3 = 4'd0;
-reg     [3:0] soc_ddrphy_activates4 = 4'd0;
-reg     [3:0] soc_ddrphy_precharges4 = 4'd0;
-reg           soc_ddrphy_bank_write4 = 1'd0;
-reg     [9:0] soc_ddrphy_bank_write_col4 = 10'd0;
-reg     [3:0] soc_ddrphy_writes4 = 4'd0;
-reg           soc_ddrphy_new_bank_write4 = 1'd0;
-reg     [9:0] soc_ddrphy_new_bank_write_col4 = 10'd0;
-reg     [3:0] soc_ddrphy_reads4 = 4'd0;
-reg     [3:0] soc_ddrphy_activates5 = 4'd0;
-reg     [3:0] soc_ddrphy_precharges5 = 4'd0;
-reg           soc_ddrphy_bank_write5 = 1'd0;
-reg     [9:0] soc_ddrphy_bank_write_col5 = 10'd0;
-reg     [3:0] soc_ddrphy_writes5 = 4'd0;
-reg           soc_ddrphy_new_bank_write5 = 1'd0;
-reg     [9:0] soc_ddrphy_new_bank_write_col5 = 10'd0;
-reg     [3:0] soc_ddrphy_reads5 = 4'd0;
-reg     [3:0] soc_ddrphy_activates6 = 4'd0;
-reg     [3:0] soc_ddrphy_precharges6 = 4'd0;
-reg           soc_ddrphy_bank_write6 = 1'd0;
-reg     [9:0] soc_ddrphy_bank_write_col6 = 10'd0;
-reg     [3:0] soc_ddrphy_writes6 = 4'd0;
-reg           soc_ddrphy_new_bank_write6 = 1'd0;
-reg     [9:0] soc_ddrphy_new_bank_write_col6 = 10'd0;
-reg     [3:0] soc_ddrphy_reads6 = 4'd0;
-reg     [3:0] soc_ddrphy_activates7 = 4'd0;
-reg     [3:0] soc_ddrphy_precharges7 = 4'd0;
-reg           soc_ddrphy_bank_write7 = 1'd0;
-reg     [9:0] soc_ddrphy_bank_write_col7 = 10'd0;
-reg     [3:0] soc_ddrphy_writes7 = 4'd0;
-reg           soc_ddrphy_new_bank_write7 = 1'd0;
-reg     [9:0] soc_ddrphy_new_bank_write_col7 = 10'd0;
-reg     [3:0] soc_ddrphy_reads7 = 4'd0;
+reg    [15:0] soc_ddrphy_bankmodel7_write_port_we = 16'd0;
 wire          soc_ddrphy_banks_read;
 wire  [127:0] soc_ddrphy_banks_read_data;
+wire          soc_ddrphy_dfi_p0_act_n;
+wire   [13:0] soc_ddrphy_dfi_p0_address;
+wire    [2:0] soc_ddrphy_dfi_p0_bank;
+wire          soc_ddrphy_dfi_p0_cas_n;
+wire          soc_ddrphy_dfi_p0_cke;
+wire          soc_ddrphy_dfi_p0_cs_n;
+wire          soc_ddrphy_dfi_p0_odt;
+wire          soc_ddrphy_dfi_p0_ras_n;
+wire   [31:0] soc_ddrphy_dfi_p0_rddata;
+wire          soc_ddrphy_dfi_p0_rddata_en;
+wire          soc_ddrphy_dfi_p0_rddata_valid;
+wire          soc_ddrphy_dfi_p0_reset_n;
+wire          soc_ddrphy_dfi_p0_we_n;
+wire   [31:0] soc_ddrphy_dfi_p0_wrdata;
+wire          soc_ddrphy_dfi_p0_wrdata_en;
+wire    [3:0] soc_ddrphy_dfi_p0_wrdata_mask;
+wire          soc_ddrphy_dfi_p1_act_n;
+wire   [13:0] soc_ddrphy_dfi_p1_address;
+wire    [2:0] soc_ddrphy_dfi_p1_bank;
+wire          soc_ddrphy_dfi_p1_cas_n;
+wire          soc_ddrphy_dfi_p1_cke;
+wire          soc_ddrphy_dfi_p1_cs_n;
+wire          soc_ddrphy_dfi_p1_odt;
+wire          soc_ddrphy_dfi_p1_ras_n;
+wire   [31:0] soc_ddrphy_dfi_p1_rddata;
+wire          soc_ddrphy_dfi_p1_rddata_en;
+wire          soc_ddrphy_dfi_p1_rddata_valid;
+wire          soc_ddrphy_dfi_p1_reset_n;
+wire          soc_ddrphy_dfi_p1_we_n;
+wire   [31:0] soc_ddrphy_dfi_p1_wrdata;
+wire          soc_ddrphy_dfi_p1_wrdata_en;
+wire    [3:0] soc_ddrphy_dfi_p1_wrdata_mask;
+wire          soc_ddrphy_dfi_p2_act_n;
+wire   [13:0] soc_ddrphy_dfi_p2_address;
+wire    [2:0] soc_ddrphy_dfi_p2_bank;
+wire          soc_ddrphy_dfi_p2_cas_n;
+wire          soc_ddrphy_dfi_p2_cke;
+wire          soc_ddrphy_dfi_p2_cs_n;
+wire          soc_ddrphy_dfi_p2_odt;
+wire          soc_ddrphy_dfi_p2_ras_n;
+wire   [31:0] soc_ddrphy_dfi_p2_rddata;
+wire          soc_ddrphy_dfi_p2_rddata_en;
+wire          soc_ddrphy_dfi_p2_rddata_valid;
+wire          soc_ddrphy_dfi_p2_reset_n;
+wire          soc_ddrphy_dfi_p2_we_n;
+wire   [31:0] soc_ddrphy_dfi_p2_wrdata;
+wire          soc_ddrphy_dfi_p2_wrdata_en;
+wire    [3:0] soc_ddrphy_dfi_p2_wrdata_mask;
+wire          soc_ddrphy_dfi_p3_act_n;
+wire   [13:0] soc_ddrphy_dfi_p3_address;
+wire    [2:0] soc_ddrphy_dfi_p3_bank;
+wire          soc_ddrphy_dfi_p3_cas_n;
+wire          soc_ddrphy_dfi_p3_cke;
+wire          soc_ddrphy_dfi_p3_cs_n;
+wire          soc_ddrphy_dfi_p3_odt;
+wire          soc_ddrphy_dfi_p3_ras_n;
+wire   [31:0] soc_ddrphy_dfi_p3_rddata;
+wire          soc_ddrphy_dfi_p3_rddata_en;
+wire          soc_ddrphy_dfi_p3_rddata_valid;
+wire          soc_ddrphy_dfi_p3_reset_n;
+wire          soc_ddrphy_dfi_p3_we_n;
+wire   [31:0] soc_ddrphy_dfi_p3_wrdata;
+wire          soc_ddrphy_dfi_p3_wrdata_en;
+wire    [3:0] soc_ddrphy_dfi_p3_wrdata_mask;
+reg           soc_ddrphy_dfiphasemodel0_activate = 1'd0;
+reg           soc_ddrphy_dfiphasemodel0_precharge = 1'd0;
+reg           soc_ddrphy_dfiphasemodel0_read = 1'd0;
+reg           soc_ddrphy_dfiphasemodel0_write = 1'd0;
+reg           soc_ddrphy_dfiphasemodel1_activate = 1'd0;
+reg           soc_ddrphy_dfiphasemodel1_precharge = 1'd0;
+reg           soc_ddrphy_dfiphasemodel1_read = 1'd0;
+reg           soc_ddrphy_dfiphasemodel1_write = 1'd0;
+reg           soc_ddrphy_dfiphasemodel2_activate = 1'd0;
+reg           soc_ddrphy_dfiphasemodel2_precharge = 1'd0;
+reg           soc_ddrphy_dfiphasemodel2_read = 1'd0;
+reg           soc_ddrphy_dfiphasemodel2_write = 1'd0;
+reg           soc_ddrphy_dfiphasemodel3_activate = 1'd0;
+reg           soc_ddrphy_dfiphasemodel3_precharge = 1'd0;
+reg           soc_ddrphy_dfiphasemodel3_read = 1'd0;
+reg           soc_ddrphy_dfiphasemodel3_write = 1'd0;
+reg           soc_ddrphy_new_bank_write0 = 1'd0;
+reg           soc_ddrphy_new_bank_write1 = 1'd0;
+reg           soc_ddrphy_new_bank_write2 = 1'd0;
+reg           soc_ddrphy_new_bank_write3 = 1'd0;
+reg           soc_ddrphy_new_bank_write4 = 1'd0;
+reg           soc_ddrphy_new_bank_write5 = 1'd0;
+reg           soc_ddrphy_new_bank_write6 = 1'd0;
+reg           soc_ddrphy_new_bank_write7 = 1'd0;
+reg     [9:0] soc_ddrphy_new_bank_write_col0 = 10'd0;
+reg     [9:0] soc_ddrphy_new_bank_write_col1 = 10'd0;
+reg     [9:0] soc_ddrphy_new_bank_write_col2 = 10'd0;
+reg     [9:0] soc_ddrphy_new_bank_write_col3 = 10'd0;
+reg     [9:0] soc_ddrphy_new_bank_write_col4 = 10'd0;
+reg     [9:0] soc_ddrphy_new_bank_write_col5 = 10'd0;
+reg     [9:0] soc_ddrphy_new_bank_write_col6 = 10'd0;
+reg     [9:0] soc_ddrphy_new_bank_write_col7 = 10'd0;
 reg           soc_ddrphy_new_banks_read0 = 1'd0;
-reg   [127:0] soc_ddrphy_new_banks_read_data0 = 128'd0;
 reg           soc_ddrphy_new_banks_read1 = 1'd0;
-reg   [127:0] soc_ddrphy_new_banks_read_data1 = 128'd0;
 reg           soc_ddrphy_new_banks_read2 = 1'd0;
-reg   [127:0] soc_ddrphy_new_banks_read_data2 = 128'd0;
 reg           soc_ddrphy_new_banks_read3 = 1'd0;
-reg   [127:0] soc_ddrphy_new_banks_read_data3 = 128'd0;
 reg           soc_ddrphy_new_banks_read4 = 1'd0;
-reg   [127:0] soc_ddrphy_new_banks_read_data4 = 128'd0;
 reg           soc_ddrphy_new_banks_read5 = 1'd0;
-reg   [127:0] soc_ddrphy_new_banks_read_data5 = 128'd0;
 reg           soc_ddrphy_new_banks_read6 = 1'd0;
-reg   [127:0] soc_ddrphy_new_banks_read_data6 = 128'd0;
 reg           soc_ddrphy_new_banks_read7 = 1'd0;
+reg   [127:0] soc_ddrphy_new_banks_read_data0 = 128'd0;
+reg   [127:0] soc_ddrphy_new_banks_read_data1 = 128'd0;
+reg   [127:0] soc_ddrphy_new_banks_read_data2 = 128'd0;
+reg   [127:0] soc_ddrphy_new_banks_read_data3 = 128'd0;
+reg   [127:0] soc_ddrphy_new_banks_read_data4 = 128'd0;
+reg   [127:0] soc_ddrphy_new_banks_read_data5 = 128'd0;
+reg   [127:0] soc_ddrphy_new_banks_read_data6 = 128'd0;
 reg   [127:0] soc_ddrphy_new_banks_read_data7 = 128'd0;
-wire   [13:0] soc_litedramcore_slave_p0_address;
-wire    [2:0] soc_litedramcore_slave_p0_bank;
-wire          soc_litedramcore_slave_p0_cas_n;
-wire          soc_litedramcore_slave_p0_cs_n;
-wire          soc_litedramcore_slave_p0_ras_n;
-wire          soc_litedramcore_slave_p0_we_n;
-wire          soc_litedramcore_slave_p0_cke;
-wire          soc_litedramcore_slave_p0_odt;
-wire          soc_litedramcore_slave_p0_reset_n;
-wire          soc_litedramcore_slave_p0_act_n;
-wire   [31:0] soc_litedramcore_slave_p0_wrdata;
-wire          soc_litedramcore_slave_p0_wrdata_en;
-wire    [3:0] soc_litedramcore_slave_p0_wrdata_mask;
-wire          soc_litedramcore_slave_p0_rddata_en;
-reg    [31:0] soc_litedramcore_slave_p0_rddata = 32'd0;
-reg           soc_litedramcore_slave_p0_rddata_valid = 1'd0;
-wire   [13:0] soc_litedramcore_slave_p1_address;
-wire    [2:0] soc_litedramcore_slave_p1_bank;
-wire          soc_litedramcore_slave_p1_cas_n;
-wire          soc_litedramcore_slave_p1_cs_n;
-wire          soc_litedramcore_slave_p1_ras_n;
-wire          soc_litedramcore_slave_p1_we_n;
-wire          soc_litedramcore_slave_p1_cke;
-wire          soc_litedramcore_slave_p1_odt;
-wire          soc_litedramcore_slave_p1_reset_n;
-wire          soc_litedramcore_slave_p1_act_n;
-wire   [31:0] soc_litedramcore_slave_p1_wrdata;
-wire          soc_litedramcore_slave_p1_wrdata_en;
-wire    [3:0] soc_litedramcore_slave_p1_wrdata_mask;
-wire          soc_litedramcore_slave_p1_rddata_en;
-reg    [31:0] soc_litedramcore_slave_p1_rddata = 32'd0;
-reg           soc_litedramcore_slave_p1_rddata_valid = 1'd0;
-wire   [13:0] soc_litedramcore_slave_p2_address;
-wire    [2:0] soc_litedramcore_slave_p2_bank;
-wire          soc_litedramcore_slave_p2_cas_n;
-wire          soc_litedramcore_slave_p2_cs_n;
-wire          soc_litedramcore_slave_p2_ras_n;
-wire          soc_litedramcore_slave_p2_we_n;
-wire          soc_litedramcore_slave_p2_cke;
-wire          soc_litedramcore_slave_p2_odt;
-wire          soc_litedramcore_slave_p2_reset_n;
-wire          soc_litedramcore_slave_p2_act_n;
-wire   [31:0] soc_litedramcore_slave_p2_wrdata;
-wire          soc_litedramcore_slave_p2_wrdata_en;
-wire    [3:0] soc_litedramcore_slave_p2_wrdata_mask;
-wire          soc_litedramcore_slave_p2_rddata_en;
-reg    [31:0] soc_litedramcore_slave_p2_rddata = 32'd0;
-reg           soc_litedramcore_slave_p2_rddata_valid = 1'd0;
-wire   [13:0] soc_litedramcore_slave_p3_address;
-wire    [2:0] soc_litedramcore_slave_p3_bank;
-wire          soc_litedramcore_slave_p3_cas_n;
-wire          soc_litedramcore_slave_p3_cs_n;
-wire          soc_litedramcore_slave_p3_ras_n;
-wire          soc_litedramcore_slave_p3_we_n;
-wire          soc_litedramcore_slave_p3_cke;
-wire          soc_litedramcore_slave_p3_odt;
-wire          soc_litedramcore_slave_p3_reset_n;
-wire          soc_litedramcore_slave_p3_act_n;
-wire   [31:0] soc_litedramcore_slave_p3_wrdata;
-wire          soc_litedramcore_slave_p3_wrdata_en;
-wire    [3:0] soc_litedramcore_slave_p3_wrdata_mask;
-wire          soc_litedramcore_slave_p3_rddata_en;
-reg    [31:0] soc_litedramcore_slave_p3_rddata = 32'd0;
-reg           soc_litedramcore_slave_p3_rddata_valid = 1'd0;
-reg    [13:0] soc_litedramcore_master_p0_address = 14'd0;
-reg     [2:0] soc_litedramcore_master_p0_bank = 3'd0;
-reg           soc_litedramcore_master_p0_cas_n = 1'd1;
-reg           soc_litedramcore_master_p0_cs_n = 1'd1;
-reg           soc_litedramcore_master_p0_ras_n = 1'd1;
-reg           soc_litedramcore_master_p0_we_n = 1'd1;
-reg           soc_litedramcore_master_p0_cke = 1'd0;
-reg           soc_litedramcore_master_p0_odt = 1'd0;
-reg           soc_litedramcore_master_p0_reset_n = 1'd0;
-reg           soc_litedramcore_master_p0_act_n = 1'd1;
-reg    [31:0] soc_litedramcore_master_p0_wrdata = 32'd0;
-reg           soc_litedramcore_master_p0_wrdata_en = 1'd0;
-reg     [3:0] soc_litedramcore_master_p0_wrdata_mask = 4'd0;
-reg           soc_litedramcore_master_p0_rddata_en = 1'd0;
-wire   [31:0] soc_litedramcore_master_p0_rddata;
-wire          soc_litedramcore_master_p0_rddata_valid;
-reg    [13:0] soc_litedramcore_master_p1_address = 14'd0;
-reg     [2:0] soc_litedramcore_master_p1_bank = 3'd0;
-reg           soc_litedramcore_master_p1_cas_n = 1'd1;
-reg           soc_litedramcore_master_p1_cs_n = 1'd1;
-reg           soc_litedramcore_master_p1_ras_n = 1'd1;
-reg           soc_litedramcore_master_p1_we_n = 1'd1;
-reg           soc_litedramcore_master_p1_cke = 1'd0;
-reg           soc_litedramcore_master_p1_odt = 1'd0;
-reg           soc_litedramcore_master_p1_reset_n = 1'd0;
-reg           soc_litedramcore_master_p1_act_n = 1'd1;
-reg    [31:0] soc_litedramcore_master_p1_wrdata = 32'd0;
-reg           soc_litedramcore_master_p1_wrdata_en = 1'd0;
-reg     [3:0] soc_litedramcore_master_p1_wrdata_mask = 4'd0;
-reg           soc_litedramcore_master_p1_rddata_en = 1'd0;
-wire   [31:0] soc_litedramcore_master_p1_rddata;
-wire          soc_litedramcore_master_p1_rddata_valid;
-reg    [13:0] soc_litedramcore_master_p2_address = 14'd0;
-reg     [2:0] soc_litedramcore_master_p2_bank = 3'd0;
-reg           soc_litedramcore_master_p2_cas_n = 1'd1;
-reg           soc_litedramcore_master_p2_cs_n = 1'd1;
-reg           soc_litedramcore_master_p2_ras_n = 1'd1;
-reg           soc_litedramcore_master_p2_we_n = 1'd1;
-reg           soc_litedramcore_master_p2_cke = 1'd0;
-reg           soc_litedramcore_master_p2_odt = 1'd0;
-reg           soc_litedramcore_master_p2_reset_n = 1'd0;
-reg           soc_litedramcore_master_p2_act_n = 1'd1;
-reg    [31:0] soc_litedramcore_master_p2_wrdata = 32'd0;
-reg           soc_litedramcore_master_p2_wrdata_en = 1'd0;
-reg     [3:0] soc_litedramcore_master_p2_wrdata_mask = 4'd0;
-reg           soc_litedramcore_master_p2_rddata_en = 1'd0;
-wire   [31:0] soc_litedramcore_master_p2_rddata;
-wire          soc_litedramcore_master_p2_rddata_valid;
-reg    [13:0] soc_litedramcore_master_p3_address = 14'd0;
-reg     [2:0] soc_litedramcore_master_p3_bank = 3'd0;
-reg           soc_litedramcore_master_p3_cas_n = 1'd1;
-reg           soc_litedramcore_master_p3_cs_n = 1'd1;
-reg           soc_litedramcore_master_p3_ras_n = 1'd1;
-reg           soc_litedramcore_master_p3_we_n = 1'd1;
-reg           soc_litedramcore_master_p3_cke = 1'd0;
-reg           soc_litedramcore_master_p3_odt = 1'd0;
-reg           soc_litedramcore_master_p3_reset_n = 1'd0;
-reg           soc_litedramcore_master_p3_act_n = 1'd1;
-reg    [31:0] soc_litedramcore_master_p3_wrdata = 32'd0;
-reg           soc_litedramcore_master_p3_wrdata_en = 1'd0;
-reg     [3:0] soc_litedramcore_master_p3_wrdata_mask = 4'd0;
-reg           soc_litedramcore_master_p3_rddata_en = 1'd0;
-wire   [31:0] soc_litedramcore_master_p3_rddata;
-wire          soc_litedramcore_master_p3_rddata_valid;
-wire   [13:0] soc_litedramcore_csr_dfi_p0_address;
-wire    [2:0] soc_litedramcore_csr_dfi_p0_bank;
-reg           soc_litedramcore_csr_dfi_p0_cas_n = 1'd1;
-reg           soc_litedramcore_csr_dfi_p0_cs_n = 1'd1;
-reg           soc_litedramcore_csr_dfi_p0_ras_n = 1'd1;
-reg           soc_litedramcore_csr_dfi_p0_we_n = 1'd1;
-wire          soc_litedramcore_csr_dfi_p0_cke;
-wire          soc_litedramcore_csr_dfi_p0_odt;
-wire          soc_litedramcore_csr_dfi_p0_reset_n;
-reg           soc_litedramcore_csr_dfi_p0_act_n = 1'd1;
-wire   [31:0] soc_litedramcore_csr_dfi_p0_wrdata;
-wire          soc_litedramcore_csr_dfi_p0_wrdata_en;
-wire    [3:0] soc_litedramcore_csr_dfi_p0_wrdata_mask;
-wire          soc_litedramcore_csr_dfi_p0_rddata_en;
-reg    [31:0] soc_litedramcore_csr_dfi_p0_rddata = 32'd0;
-reg           soc_litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
-wire   [13:0] soc_litedramcore_csr_dfi_p1_address;
-wire    [2:0] soc_litedramcore_csr_dfi_p1_bank;
-reg           soc_litedramcore_csr_dfi_p1_cas_n = 1'd1;
-reg           soc_litedramcore_csr_dfi_p1_cs_n = 1'd1;
-reg           soc_litedramcore_csr_dfi_p1_ras_n = 1'd1;
-reg           soc_litedramcore_csr_dfi_p1_we_n = 1'd1;
-wire          soc_litedramcore_csr_dfi_p1_cke;
-wire          soc_litedramcore_csr_dfi_p1_odt;
-wire          soc_litedramcore_csr_dfi_p1_reset_n;
-reg           soc_litedramcore_csr_dfi_p1_act_n = 1'd1;
-wire   [31:0] soc_litedramcore_csr_dfi_p1_wrdata;
-wire          soc_litedramcore_csr_dfi_p1_wrdata_en;
-wire    [3:0] soc_litedramcore_csr_dfi_p1_wrdata_mask;
-wire          soc_litedramcore_csr_dfi_p1_rddata_en;
-reg    [31:0] soc_litedramcore_csr_dfi_p1_rddata = 32'd0;
-reg           soc_litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
-wire   [13:0] soc_litedramcore_csr_dfi_p2_address;
-wire    [2:0] soc_litedramcore_csr_dfi_p2_bank;
-reg           soc_litedramcore_csr_dfi_p2_cas_n = 1'd1;
-reg           soc_litedramcore_csr_dfi_p2_cs_n = 1'd1;
-reg           soc_litedramcore_csr_dfi_p2_ras_n = 1'd1;
-reg           soc_litedramcore_csr_dfi_p2_we_n = 1'd1;
-wire          soc_litedramcore_csr_dfi_p2_cke;
-wire          soc_litedramcore_csr_dfi_p2_odt;
-wire          soc_litedramcore_csr_dfi_p2_reset_n;
-reg           soc_litedramcore_csr_dfi_p2_act_n = 1'd1;
-wire   [31:0] soc_litedramcore_csr_dfi_p2_wrdata;
-wire          soc_litedramcore_csr_dfi_p2_wrdata_en;
-wire    [3:0] soc_litedramcore_csr_dfi_p2_wrdata_mask;
-wire          soc_litedramcore_csr_dfi_p2_rddata_en;
-reg    [31:0] soc_litedramcore_csr_dfi_p2_rddata = 32'd0;
-reg           soc_litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
-wire   [13:0] soc_litedramcore_csr_dfi_p3_address;
-wire    [2:0] soc_litedramcore_csr_dfi_p3_bank;
-reg           soc_litedramcore_csr_dfi_p3_cas_n = 1'd1;
-reg           soc_litedramcore_csr_dfi_p3_cs_n = 1'd1;
-reg           soc_litedramcore_csr_dfi_p3_ras_n = 1'd1;
-reg           soc_litedramcore_csr_dfi_p3_we_n = 1'd1;
-wire          soc_litedramcore_csr_dfi_p3_cke;
-wire          soc_litedramcore_csr_dfi_p3_odt;
-wire          soc_litedramcore_csr_dfi_p3_reset_n;
-reg           soc_litedramcore_csr_dfi_p3_act_n = 1'd1;
-wire   [31:0] soc_litedramcore_csr_dfi_p3_wrdata;
-wire          soc_litedramcore_csr_dfi_p3_wrdata_en;
-wire    [3:0] soc_litedramcore_csr_dfi_p3_wrdata_mask;
-wire          soc_litedramcore_csr_dfi_p3_rddata_en;
-reg    [31:0] soc_litedramcore_csr_dfi_p3_rddata = 32'd0;
-reg           soc_litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
-reg    [13:0] soc_litedramcore_ext_dfi_p0_address = 14'd0;
-reg     [2:0] soc_litedramcore_ext_dfi_p0_bank = 3'd0;
-reg           soc_litedramcore_ext_dfi_p0_cas_n = 1'd1;
-reg           soc_litedramcore_ext_dfi_p0_cs_n = 1'd1;
-reg           soc_litedramcore_ext_dfi_p0_ras_n = 1'd1;
-reg           soc_litedramcore_ext_dfi_p0_we_n = 1'd1;
-reg           soc_litedramcore_ext_dfi_p0_cke = 1'd0;
-reg           soc_litedramcore_ext_dfi_p0_odt = 1'd0;
-reg           soc_litedramcore_ext_dfi_p0_reset_n = 1'd0;
-reg           soc_litedramcore_ext_dfi_p0_act_n = 1'd1;
-reg    [31:0] soc_litedramcore_ext_dfi_p0_wrdata = 32'd0;
-reg           soc_litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
-reg     [3:0] soc_litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
-reg           soc_litedramcore_ext_dfi_p0_rddata_en = 1'd0;
-reg    [31:0] soc_litedramcore_ext_dfi_p0_rddata = 32'd0;
-reg           soc_litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
-reg    [13:0] soc_litedramcore_ext_dfi_p1_address = 14'd0;
-reg     [2:0] soc_litedramcore_ext_dfi_p1_bank = 3'd0;
-reg           soc_litedramcore_ext_dfi_p1_cas_n = 1'd1;
-reg           soc_litedramcore_ext_dfi_p1_cs_n = 1'd1;
-reg           soc_litedramcore_ext_dfi_p1_ras_n = 1'd1;
-reg           soc_litedramcore_ext_dfi_p1_we_n = 1'd1;
-reg           soc_litedramcore_ext_dfi_p1_cke = 1'd0;
-reg           soc_litedramcore_ext_dfi_p1_odt = 1'd0;
-reg           soc_litedramcore_ext_dfi_p1_reset_n = 1'd0;
-reg           soc_litedramcore_ext_dfi_p1_act_n = 1'd1;
-reg    [31:0] soc_litedramcore_ext_dfi_p1_wrdata = 32'd0;
-reg           soc_litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
-reg     [3:0] soc_litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
-reg           soc_litedramcore_ext_dfi_p1_rddata_en = 1'd0;
-reg    [31:0] soc_litedramcore_ext_dfi_p1_rddata = 32'd0;
-reg           soc_litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
-reg    [13:0] soc_litedramcore_ext_dfi_p2_address = 14'd0;
-reg     [2:0] soc_litedramcore_ext_dfi_p2_bank = 3'd0;
-reg           soc_litedramcore_ext_dfi_p2_cas_n = 1'd1;
-reg           soc_litedramcore_ext_dfi_p2_cs_n = 1'd1;
-reg           soc_litedramcore_ext_dfi_p2_ras_n = 1'd1;
-reg           soc_litedramcore_ext_dfi_p2_we_n = 1'd1;
-reg           soc_litedramcore_ext_dfi_p2_cke = 1'd0;
-reg           soc_litedramcore_ext_dfi_p2_odt = 1'd0;
-reg           soc_litedramcore_ext_dfi_p2_reset_n = 1'd0;
-reg           soc_litedramcore_ext_dfi_p2_act_n = 1'd1;
-reg    [31:0] soc_litedramcore_ext_dfi_p2_wrdata = 32'd0;
-reg           soc_litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
-reg     [3:0] soc_litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
-reg           soc_litedramcore_ext_dfi_p2_rddata_en = 1'd0;
-reg    [31:0] soc_litedramcore_ext_dfi_p2_rddata = 32'd0;
-reg           soc_litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
-reg    [13:0] soc_litedramcore_ext_dfi_p3_address = 14'd0;
-reg     [2:0] soc_litedramcore_ext_dfi_p3_bank = 3'd0;
-reg           soc_litedramcore_ext_dfi_p3_cas_n = 1'd1;
-reg           soc_litedramcore_ext_dfi_p3_cs_n = 1'd1;
-reg           soc_litedramcore_ext_dfi_p3_ras_n = 1'd1;
-reg           soc_litedramcore_ext_dfi_p3_we_n = 1'd1;
-reg           soc_litedramcore_ext_dfi_p3_cke = 1'd0;
-reg           soc_litedramcore_ext_dfi_p3_odt = 1'd0;
-reg           soc_litedramcore_ext_dfi_p3_reset_n = 1'd0;
-reg           soc_litedramcore_ext_dfi_p3_act_n = 1'd1;
-reg    [31:0] soc_litedramcore_ext_dfi_p3_wrdata = 32'd0;
-reg           soc_litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
-reg     [3:0] soc_litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
-reg           soc_litedramcore_ext_dfi_p3_rddata_en = 1'd0;
-reg    [31:0] soc_litedramcore_ext_dfi_p3_rddata = 32'd0;
-reg           soc_litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
-reg           soc_litedramcore_ext_dfi_sel = 1'd0;
-wire          soc_litedramcore_sel;
-wire          soc_litedramcore_cke;
-wire          soc_litedramcore_odt;
-wire          soc_litedramcore_reset_n;
-reg     [3:0] soc_litedramcore_storage = 4'd1;
-reg           soc_litedramcore_re = 1'd0;
-wire          soc_litedramcore_phaseinjector0_csrfield_cs;
-wire          soc_litedramcore_phaseinjector0_csrfield_we;
-wire          soc_litedramcore_phaseinjector0_csrfield_cas;
-wire          soc_litedramcore_phaseinjector0_csrfield_ras;
-wire          soc_litedramcore_phaseinjector0_csrfield_wren;
-wire          soc_litedramcore_phaseinjector0_csrfield_rden;
-reg     [5:0] soc_litedramcore_phaseinjector0_command_storage = 6'd0;
-reg           soc_litedramcore_phaseinjector0_command_re = 1'd0;
-reg           soc_litedramcore_phaseinjector0_command_issue_re = 1'd0;
-wire          soc_litedramcore_phaseinjector0_command_issue_r;
-reg           soc_litedramcore_phaseinjector0_command_issue_we = 1'd0;
-reg           soc_litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg    [13:0] soc_litedramcore_phaseinjector0_address_storage = 14'd0;
-reg           soc_litedramcore_phaseinjector0_address_re = 1'd0;
-reg     [2:0] soc_litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg           soc_litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg    [31:0] soc_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
-reg           soc_litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg    [31:0] soc_litedramcore_phaseinjector0_rddata_status = 32'd0;
-wire          soc_litedramcore_phaseinjector0_rddata_we;
-reg           soc_litedramcore_phaseinjector0_rddata_re = 1'd0;
-wire          soc_litedramcore_phaseinjector1_csrfield_cs;
-wire          soc_litedramcore_phaseinjector1_csrfield_we;
-wire          soc_litedramcore_phaseinjector1_csrfield_cas;
-wire          soc_litedramcore_phaseinjector1_csrfield_ras;
-wire          soc_litedramcore_phaseinjector1_csrfield_wren;
-wire          soc_litedramcore_phaseinjector1_csrfield_rden;
-reg     [5:0] soc_litedramcore_phaseinjector1_command_storage = 6'd0;
-reg           soc_litedramcore_phaseinjector1_command_re = 1'd0;
-reg           soc_litedramcore_phaseinjector1_command_issue_re = 1'd0;
-wire          soc_litedramcore_phaseinjector1_command_issue_r;
-reg           soc_litedramcore_phaseinjector1_command_issue_we = 1'd0;
-reg           soc_litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg    [13:0] soc_litedramcore_phaseinjector1_address_storage = 14'd0;
-reg           soc_litedramcore_phaseinjector1_address_re = 1'd0;
-reg     [2:0] soc_litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg           soc_litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg    [31:0] soc_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
-reg           soc_litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg    [31:0] soc_litedramcore_phaseinjector1_rddata_status = 32'd0;
-wire          soc_litedramcore_phaseinjector1_rddata_we;
-reg           soc_litedramcore_phaseinjector1_rddata_re = 1'd0;
-wire          soc_litedramcore_phaseinjector2_csrfield_cs;
-wire          soc_litedramcore_phaseinjector2_csrfield_we;
-wire          soc_litedramcore_phaseinjector2_csrfield_cas;
-wire          soc_litedramcore_phaseinjector2_csrfield_ras;
-wire          soc_litedramcore_phaseinjector2_csrfield_wren;
-wire          soc_litedramcore_phaseinjector2_csrfield_rden;
-reg     [5:0] soc_litedramcore_phaseinjector2_command_storage = 6'd0;
-reg           soc_litedramcore_phaseinjector2_command_re = 1'd0;
-reg           soc_litedramcore_phaseinjector2_command_issue_re = 1'd0;
-wire          soc_litedramcore_phaseinjector2_command_issue_r;
-reg           soc_litedramcore_phaseinjector2_command_issue_we = 1'd0;
-reg           soc_litedramcore_phaseinjector2_command_issue_w = 1'd0;
-reg    [13:0] soc_litedramcore_phaseinjector2_address_storage = 14'd0;
-reg           soc_litedramcore_phaseinjector2_address_re = 1'd0;
-reg     [2:0] soc_litedramcore_phaseinjector2_baddress_storage = 3'd0;
-reg           soc_litedramcore_phaseinjector2_baddress_re = 1'd0;
-reg    [31:0] soc_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
-reg           soc_litedramcore_phaseinjector2_wrdata_re = 1'd0;
-reg    [31:0] soc_litedramcore_phaseinjector2_rddata_status = 32'd0;
-wire          soc_litedramcore_phaseinjector2_rddata_we;
-reg           soc_litedramcore_phaseinjector2_rddata_re = 1'd0;
-wire          soc_litedramcore_phaseinjector3_csrfield_cs;
-wire          soc_litedramcore_phaseinjector3_csrfield_we;
-wire          soc_litedramcore_phaseinjector3_csrfield_cas;
-wire          soc_litedramcore_phaseinjector3_csrfield_ras;
-wire          soc_litedramcore_phaseinjector3_csrfield_wren;
-wire          soc_litedramcore_phaseinjector3_csrfield_rden;
-reg     [5:0] soc_litedramcore_phaseinjector3_command_storage = 6'd0;
-reg           soc_litedramcore_phaseinjector3_command_re = 1'd0;
-reg           soc_litedramcore_phaseinjector3_command_issue_re = 1'd0;
-wire          soc_litedramcore_phaseinjector3_command_issue_r;
-reg           soc_litedramcore_phaseinjector3_command_issue_we = 1'd0;
-reg           soc_litedramcore_phaseinjector3_command_issue_w = 1'd0;
-reg    [13:0] soc_litedramcore_phaseinjector3_address_storage = 14'd0;
-reg           soc_litedramcore_phaseinjector3_address_re = 1'd0;
-reg     [2:0] soc_litedramcore_phaseinjector3_baddress_storage = 3'd0;
-reg           soc_litedramcore_phaseinjector3_baddress_re = 1'd0;
-reg    [31:0] soc_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
-reg           soc_litedramcore_phaseinjector3_wrdata_re = 1'd0;
-reg    [31:0] soc_litedramcore_phaseinjector3_rddata_status = 32'd0;
-wire          soc_litedramcore_phaseinjector3_rddata_we;
-reg           soc_litedramcore_phaseinjector3_rddata_re = 1'd0;
-wire          soc_litedramcore_interface_bank0_valid;
-wire          soc_litedramcore_interface_bank0_ready;
-wire          soc_litedramcore_interface_bank0_we;
-wire   [20:0] soc_litedramcore_interface_bank0_addr;
-wire          soc_litedramcore_interface_bank0_lock;
-wire          soc_litedramcore_interface_bank0_wdata_ready;
-wire          soc_litedramcore_interface_bank0_rdata_valid;
-wire          soc_litedramcore_interface_bank1_valid;
-wire          soc_litedramcore_interface_bank1_ready;
-wire          soc_litedramcore_interface_bank1_we;
-wire   [20:0] soc_litedramcore_interface_bank1_addr;
-wire          soc_litedramcore_interface_bank1_lock;
-wire          soc_litedramcore_interface_bank1_wdata_ready;
-wire          soc_litedramcore_interface_bank1_rdata_valid;
-wire          soc_litedramcore_interface_bank2_valid;
-wire          soc_litedramcore_interface_bank2_ready;
-wire          soc_litedramcore_interface_bank2_we;
-wire   [20:0] soc_litedramcore_interface_bank2_addr;
-wire          soc_litedramcore_interface_bank2_lock;
-wire          soc_litedramcore_interface_bank2_wdata_ready;
-wire          soc_litedramcore_interface_bank2_rdata_valid;
-wire          soc_litedramcore_interface_bank3_valid;
-wire          soc_litedramcore_interface_bank3_ready;
-wire          soc_litedramcore_interface_bank3_we;
-wire   [20:0] soc_litedramcore_interface_bank3_addr;
-wire          soc_litedramcore_interface_bank3_lock;
-wire          soc_litedramcore_interface_bank3_wdata_ready;
-wire          soc_litedramcore_interface_bank3_rdata_valid;
-wire          soc_litedramcore_interface_bank4_valid;
-wire          soc_litedramcore_interface_bank4_ready;
-wire          soc_litedramcore_interface_bank4_we;
-wire   [20:0] soc_litedramcore_interface_bank4_addr;
-wire          soc_litedramcore_interface_bank4_lock;
-wire          soc_litedramcore_interface_bank4_wdata_ready;
-wire          soc_litedramcore_interface_bank4_rdata_valid;
-wire          soc_litedramcore_interface_bank5_valid;
-wire          soc_litedramcore_interface_bank5_ready;
-wire          soc_litedramcore_interface_bank5_we;
-wire   [20:0] soc_litedramcore_interface_bank5_addr;
-wire          soc_litedramcore_interface_bank5_lock;
-wire          soc_litedramcore_interface_bank5_wdata_ready;
-wire          soc_litedramcore_interface_bank5_rdata_valid;
-wire          soc_litedramcore_interface_bank6_valid;
-wire          soc_litedramcore_interface_bank6_ready;
-wire          soc_litedramcore_interface_bank6_we;
-wire   [20:0] soc_litedramcore_interface_bank6_addr;
-wire          soc_litedramcore_interface_bank6_lock;
-wire          soc_litedramcore_interface_bank6_wdata_ready;
-wire          soc_litedramcore_interface_bank6_rdata_valid;
-wire          soc_litedramcore_interface_bank7_valid;
-wire          soc_litedramcore_interface_bank7_ready;
-wire          soc_litedramcore_interface_bank7_we;
-wire   [20:0] soc_litedramcore_interface_bank7_addr;
-wire          soc_litedramcore_interface_bank7_lock;
-wire          soc_litedramcore_interface_bank7_wdata_ready;
-wire          soc_litedramcore_interface_bank7_rdata_valid;
-reg   [127:0] soc_litedramcore_interface_wdata = 128'd0;
-reg    [15:0] soc_litedramcore_interface_wdata_we = 16'd0;
-wire  [127:0] soc_litedramcore_interface_rdata;
-reg    [13:0] soc_litedramcore_dfi_p0_address = 14'd0;
-reg     [2:0] soc_litedramcore_dfi_p0_bank = 3'd0;
-reg           soc_litedramcore_dfi_p0_cas_n = 1'd1;
-reg           soc_litedramcore_dfi_p0_cs_n = 1'd1;
-reg           soc_litedramcore_dfi_p0_ras_n = 1'd1;
-reg           soc_litedramcore_dfi_p0_we_n = 1'd1;
-wire          soc_litedramcore_dfi_p0_cke;
-wire          soc_litedramcore_dfi_p0_odt;
-wire          soc_litedramcore_dfi_p0_reset_n;
-reg           soc_litedramcore_dfi_p0_act_n = 1'd1;
-wire   [31:0] soc_litedramcore_dfi_p0_wrdata;
-reg           soc_litedramcore_dfi_p0_wrdata_en = 1'd0;
-wire    [3:0] soc_litedramcore_dfi_p0_wrdata_mask;
-reg           soc_litedramcore_dfi_p0_rddata_en = 1'd0;
-wire   [31:0] soc_litedramcore_dfi_p0_rddata;
-wire          soc_litedramcore_dfi_p0_rddata_valid;
-reg    [13:0] soc_litedramcore_dfi_p1_address = 14'd0;
-reg     [2:0] soc_litedramcore_dfi_p1_bank = 3'd0;
-reg           soc_litedramcore_dfi_p1_cas_n = 1'd1;
-reg           soc_litedramcore_dfi_p1_cs_n = 1'd1;
-reg           soc_litedramcore_dfi_p1_ras_n = 1'd1;
-reg           soc_litedramcore_dfi_p1_we_n = 1'd1;
-wire          soc_litedramcore_dfi_p1_cke;
-wire          soc_litedramcore_dfi_p1_odt;
-wire          soc_litedramcore_dfi_p1_reset_n;
-reg           soc_litedramcore_dfi_p1_act_n = 1'd1;
-wire   [31:0] soc_litedramcore_dfi_p1_wrdata;
-reg           soc_litedramcore_dfi_p1_wrdata_en = 1'd0;
-wire    [3:0] soc_litedramcore_dfi_p1_wrdata_mask;
-reg           soc_litedramcore_dfi_p1_rddata_en = 1'd0;
-wire   [31:0] soc_litedramcore_dfi_p1_rddata;
-wire          soc_litedramcore_dfi_p1_rddata_valid;
-reg    [13:0] soc_litedramcore_dfi_p2_address = 14'd0;
-reg     [2:0] soc_litedramcore_dfi_p2_bank = 3'd0;
-reg           soc_litedramcore_dfi_p2_cas_n = 1'd1;
-reg           soc_litedramcore_dfi_p2_cs_n = 1'd1;
-reg           soc_litedramcore_dfi_p2_ras_n = 1'd1;
-reg           soc_litedramcore_dfi_p2_we_n = 1'd1;
-wire          soc_litedramcore_dfi_p2_cke;
-wire          soc_litedramcore_dfi_p2_odt;
-wire          soc_litedramcore_dfi_p2_reset_n;
-reg           soc_litedramcore_dfi_p2_act_n = 1'd1;
-wire   [31:0] soc_litedramcore_dfi_p2_wrdata;
-reg           soc_litedramcore_dfi_p2_wrdata_en = 1'd0;
-wire    [3:0] soc_litedramcore_dfi_p2_wrdata_mask;
-reg           soc_litedramcore_dfi_p2_rddata_en = 1'd0;
-wire   [31:0] soc_litedramcore_dfi_p2_rddata;
-wire          soc_litedramcore_dfi_p2_rddata_valid;
-reg    [13:0] soc_litedramcore_dfi_p3_address = 14'd0;
-reg     [2:0] soc_litedramcore_dfi_p3_bank = 3'd0;
-reg           soc_litedramcore_dfi_p3_cas_n = 1'd1;
-reg           soc_litedramcore_dfi_p3_cs_n = 1'd1;
-reg           soc_litedramcore_dfi_p3_ras_n = 1'd1;
-reg           soc_litedramcore_dfi_p3_we_n = 1'd1;
-wire          soc_litedramcore_dfi_p3_cke;
-wire          soc_litedramcore_dfi_p3_odt;
-wire          soc_litedramcore_dfi_p3_reset_n;
-reg           soc_litedramcore_dfi_p3_act_n = 1'd1;
-wire   [31:0] soc_litedramcore_dfi_p3_wrdata;
-reg           soc_litedramcore_dfi_p3_wrdata_en = 1'd0;
-wire    [3:0] soc_litedramcore_dfi_p3_wrdata_mask;
-reg           soc_litedramcore_dfi_p3_rddata_en = 1'd0;
-wire   [31:0] soc_litedramcore_dfi_p3_rddata;
-wire          soc_litedramcore_dfi_p3_rddata_valid;
-reg           soc_litedramcore_cmd_valid = 1'd0;
-reg           soc_litedramcore_cmd_ready = 1'd0;
-reg           soc_litedramcore_cmd_last = 1'd0;
-reg    [13:0] soc_litedramcore_cmd_payload_a = 14'd0;
-reg     [2:0] soc_litedramcore_cmd_payload_ba = 3'd0;
-reg           soc_litedramcore_cmd_payload_cas = 1'd0;
-reg           soc_litedramcore_cmd_payload_ras = 1'd0;
-reg           soc_litedramcore_cmd_payload_we = 1'd0;
-reg           soc_litedramcore_cmd_payload_is_read = 1'd0;
-reg           soc_litedramcore_cmd_payload_is_write = 1'd0;
-wire          soc_litedramcore_wants_refresh;
-wire          soc_litedramcore_wants_zqcs;
-wire          soc_litedramcore_timer_wait;
-wire          soc_litedramcore_timer_done0;
-wire    [9:0] soc_litedramcore_timer_count0;
-wire          soc_litedramcore_timer_done1;
-reg     [9:0] soc_litedramcore_timer_count1 = 10'd781;
-wire          soc_litedramcore_postponer_req_i;
-reg           soc_litedramcore_postponer_req_o = 1'd0;
-reg           soc_litedramcore_postponer_count = 1'd0;
-reg           soc_litedramcore_sequencer_start0 = 1'd0;
-wire          soc_litedramcore_sequencer_done0;
-wire          soc_litedramcore_sequencer_start1;
-reg           soc_litedramcore_sequencer_done1 = 1'd0;
-reg     [5:0] soc_litedramcore_sequencer_counter = 6'd0;
-reg           soc_litedramcore_sequencer_count = 1'd0;
-wire          soc_litedramcore_zqcs_timer_wait;
-wire          soc_litedramcore_zqcs_timer_done0;
-wire   [26:0] soc_litedramcore_zqcs_timer_count0;
-wire          soc_litedramcore_zqcs_timer_done1;
-reg    [26:0] soc_litedramcore_zqcs_timer_count1 = 27'd99999999;
-reg           soc_litedramcore_zqcs_executer_start = 1'd0;
-reg           soc_litedramcore_zqcs_executer_done = 1'd0;
-reg     [4:0] soc_litedramcore_zqcs_executer_counter = 5'd0;
-wire          soc_litedramcore_bankmachine0_req_valid;
-wire          soc_litedramcore_bankmachine0_req_ready;
-wire          soc_litedramcore_bankmachine0_req_we;
-wire   [20:0] soc_litedramcore_bankmachine0_req_addr;
-wire          soc_litedramcore_bankmachine0_req_lock;
-reg           soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg           soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
-wire          soc_litedramcore_bankmachine0_refresh_req;
-reg           soc_litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg           soc_litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg           soc_litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg     [3:0] soc_ddrphy_precharges0 = 4'd0;
+reg     [3:0] soc_ddrphy_precharges1 = 4'd0;
+reg     [3:0] soc_ddrphy_precharges2 = 4'd0;
+reg     [3:0] soc_ddrphy_precharges3 = 4'd0;
+reg     [3:0] soc_ddrphy_precharges4 = 4'd0;
+reg     [3:0] soc_ddrphy_precharges5 = 4'd0;
+reg     [3:0] soc_ddrphy_precharges6 = 4'd0;
+reg     [3:0] soc_ddrphy_precharges7 = 4'd0;
+reg     [3:0] soc_ddrphy_reads0 = 4'd0;
+reg     [3:0] soc_ddrphy_reads1 = 4'd0;
+reg     [3:0] soc_ddrphy_reads2 = 4'd0;
+reg     [3:0] soc_ddrphy_reads3 = 4'd0;
+reg     [3:0] soc_ddrphy_reads4 = 4'd0;
+reg     [3:0] soc_ddrphy_reads5 = 4'd0;
+reg     [3:0] soc_ddrphy_reads6 = 4'd0;
+reg     [3:0] soc_ddrphy_reads7 = 4'd0;
+reg     [3:0] soc_ddrphy_writes0 = 4'd0;
+reg     [3:0] soc_ddrphy_writes1 = 4'd0;
+reg     [3:0] soc_ddrphy_writes2 = 4'd0;
+reg     [3:0] soc_ddrphy_writes3 = 4'd0;
+reg     [3:0] soc_ddrphy_writes4 = 4'd0;
+reg     [3:0] soc_ddrphy_writes5 = 4'd0;
+reg     [3:0] soc_ddrphy_writes6 = 4'd0;
+reg     [3:0] soc_ddrphy_writes7 = 4'd0;
+reg           soc_init_done_re = 1'd0;
+reg           soc_init_done_storage = 1'd0;
+reg           soc_init_error_re = 1'd0;
+reg           soc_init_error_storage = 1'd0;
+reg           soc_int_rst = 1'd1;
+reg           soc_litedramcore_bankmachine0_auto_precharge = 1'd0;
 reg    [13:0] soc_litedramcore_bankmachine0_cmd_payload_a = 14'd0;
 wire    [2:0] soc_litedramcore_bankmachine0_cmd_payload_ba;
 reg           soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg           soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg           soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
 reg           soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
 reg           soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
 reg           soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg           soc_litedramcore_bankmachine0_auto_precharge = 1'd0;
-wire          soc_litedramcore_bankmachine0_sink_valid;
-wire          soc_litedramcore_bankmachine0_sink_ready;
-reg           soc_litedramcore_bankmachine0_sink_first = 1'd0;
-reg           soc_litedramcore_bankmachine0_sink_last = 1'd0;
-wire          soc_litedramcore_bankmachine0_sink_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine0_sink_payload_addr;
-wire          soc_litedramcore_bankmachine0_source_valid;
-wire          soc_litedramcore_bankmachine0_source_ready;
-wire          soc_litedramcore_bankmachine0_source_first;
-wire          soc_litedramcore_bankmachine0_source_last;
-wire          soc_litedramcore_bankmachine0_source_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine0_source_payload_addr;
-wire          soc_litedramcore_bankmachine0_syncfifo0_we;
-wire          soc_litedramcore_bankmachine0_syncfifo0_writable;
-wire          soc_litedramcore_bankmachine0_syncfifo0_re;
-wire          soc_litedramcore_bankmachine0_syncfifo0_readable;
-wire   [23:0] soc_litedramcore_bankmachine0_syncfifo0_din;
-wire   [23:0] soc_litedramcore_bankmachine0_syncfifo0_dout;
-reg     [4:0] soc_litedramcore_bankmachine0_level = 5'd0;
-reg           soc_litedramcore_bankmachine0_replace = 1'd0;
-reg     [3:0] soc_litedramcore_bankmachine0_produce = 4'd0;
+reg           soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg           soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg           soc_litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg           soc_litedramcore_bankmachine0_cmd_valid = 1'd0;
 reg     [3:0] soc_litedramcore_bankmachine0_consume = 4'd0;
-reg     [3:0] soc_litedramcore_bankmachine0_wrport_adr = 4'd0;
-wire   [23:0] soc_litedramcore_bankmachine0_wrport_dat_r;
-wire          soc_litedramcore_bankmachine0_wrport_we;
-wire   [23:0] soc_litedramcore_bankmachine0_wrport_dat_w;
 wire          soc_litedramcore_bankmachine0_do_read;
-wire    [3:0] soc_litedramcore_bankmachine0_rdport_adr;
-wire   [23:0] soc_litedramcore_bankmachine0_rdport_dat_r;
-wire          soc_litedramcore_bankmachine0_fifo_in_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine0_fifo_in_payload_addr;
 wire          soc_litedramcore_bankmachine0_fifo_in_first;
 wire          soc_litedramcore_bankmachine0_fifo_in_last;
-wire          soc_litedramcore_bankmachine0_fifo_out_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine0_fifo_out_payload_addr;
+wire   [20:0] soc_litedramcore_bankmachine0_fifo_in_payload_addr;
+wire          soc_litedramcore_bankmachine0_fifo_in_payload_we;
 wire          soc_litedramcore_bankmachine0_fifo_out_first;
 wire          soc_litedramcore_bankmachine0_fifo_out_last;
-wire          soc_litedramcore_bankmachine0_sink_sink_valid;
-wire          soc_litedramcore_bankmachine0_sink_sink_ready;
-wire          soc_litedramcore_bankmachine0_sink_sink_first;
-wire          soc_litedramcore_bankmachine0_sink_sink_last;
-wire          soc_litedramcore_bankmachine0_sink_sink_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine0_sink_sink_payload_addr;
-wire          soc_litedramcore_bankmachine0_source_source_valid;
-wire          soc_litedramcore_bankmachine0_source_source_ready;
-wire          soc_litedramcore_bankmachine0_source_source_first;
-wire          soc_litedramcore_bankmachine0_source_source_last;
-wire          soc_litedramcore_bankmachine0_source_source_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine0_source_source_payload_addr;
-wire          soc_litedramcore_bankmachine0_pipe_valid_sink_valid;
-wire          soc_litedramcore_bankmachine0_pipe_valid_sink_ready;
+wire   [20:0] soc_litedramcore_bankmachine0_fifo_out_payload_addr;
+wire          soc_litedramcore_bankmachine0_fifo_out_payload_we;
+reg     [4:0] soc_litedramcore_bankmachine0_level = 5'd0;
 wire          soc_litedramcore_bankmachine0_pipe_valid_sink_first;
 wire          soc_litedramcore_bankmachine0_pipe_valid_sink_last;
-wire          soc_litedramcore_bankmachine0_pipe_valid_sink_payload_we;
 wire   [20:0] soc_litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
-reg           soc_litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0;
-wire          soc_litedramcore_bankmachine0_pipe_valid_source_ready;
+wire          soc_litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+wire          soc_litedramcore_bankmachine0_pipe_valid_sink_ready;
+wire          soc_litedramcore_bankmachine0_pipe_valid_sink_valid;
 reg           soc_litedramcore_bankmachine0_pipe_valid_source_first = 1'd0;
 reg           soc_litedramcore_bankmachine0_pipe_valid_source_last = 1'd0;
-reg           soc_litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0;
 reg    [20:0] soc_litedramcore_bankmachine0_pipe_valid_source_payload_addr = 21'd0;
+reg           soc_litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0;
+wire          soc_litedramcore_bankmachine0_pipe_valid_source_ready;
+reg           soc_litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0;
+reg     [3:0] soc_litedramcore_bankmachine0_produce = 4'd0;
+wire    [3:0] soc_litedramcore_bankmachine0_rdport_adr;
+wire   [23:0] soc_litedramcore_bankmachine0_rdport_dat_r;
+reg           soc_litedramcore_bankmachine0_refresh_gnt = 1'd0;
+wire          soc_litedramcore_bankmachine0_refresh_req;
+reg           soc_litedramcore_bankmachine0_replace = 1'd0;
+wire   [20:0] soc_litedramcore_bankmachine0_req_addr;
+wire          soc_litedramcore_bankmachine0_req_lock;
+reg           soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire          soc_litedramcore_bankmachine0_req_ready;
+wire          soc_litedramcore_bankmachine0_req_valid;
+reg           soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+wire          soc_litedramcore_bankmachine0_req_we;
 reg    [13:0] soc_litedramcore_bankmachine0_row = 14'd0;
-reg           soc_litedramcore_bankmachine0_row_opened = 1'd0;
-wire          soc_litedramcore_bankmachine0_row_hit;
-reg           soc_litedramcore_bankmachine0_row_open = 1'd0;
 reg           soc_litedramcore_bankmachine0_row_close = 1'd0;
 reg           soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
-wire          soc_litedramcore_bankmachine0_twtpcon_valid;
-reg           soc_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg     [2:0] soc_litedramcore_bankmachine0_twtpcon_count = 3'd0;
-wire          soc_litedramcore_bankmachine0_trccon_valid;
-reg           soc_litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg     [2:0] soc_litedramcore_bankmachine0_trccon_count = 3'd0;
-wire          soc_litedramcore_bankmachine0_trascon_valid;
-reg           soc_litedramcore_bankmachine0_trascon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine0_row_hit;
+reg           soc_litedramcore_bankmachine0_row_open = 1'd0;
+reg           soc_litedramcore_bankmachine0_row_opened = 1'd0;
+reg           soc_litedramcore_bankmachine0_sink_first = 1'd0;
+reg           soc_litedramcore_bankmachine0_sink_last = 1'd0;
+wire   [20:0] soc_litedramcore_bankmachine0_sink_payload_addr;
+wire          soc_litedramcore_bankmachine0_sink_payload_we;
+wire          soc_litedramcore_bankmachine0_sink_ready;
+wire          soc_litedramcore_bankmachine0_sink_sink_first;
+wire          soc_litedramcore_bankmachine0_sink_sink_last;
+wire   [20:0] soc_litedramcore_bankmachine0_sink_sink_payload_addr;
+wire          soc_litedramcore_bankmachine0_sink_sink_payload_we;
+wire          soc_litedramcore_bankmachine0_sink_sink_ready;
+wire          soc_litedramcore_bankmachine0_sink_sink_valid;
+wire          soc_litedramcore_bankmachine0_sink_valid;
+wire          soc_litedramcore_bankmachine0_source_first;
+wire          soc_litedramcore_bankmachine0_source_last;
+wire   [20:0] soc_litedramcore_bankmachine0_source_payload_addr;
+wire          soc_litedramcore_bankmachine0_source_payload_we;
+wire          soc_litedramcore_bankmachine0_source_ready;
+wire          soc_litedramcore_bankmachine0_source_source_first;
+wire          soc_litedramcore_bankmachine0_source_source_last;
+wire   [20:0] soc_litedramcore_bankmachine0_source_source_payload_addr;
+wire          soc_litedramcore_bankmachine0_source_source_payload_we;
+wire          soc_litedramcore_bankmachine0_source_source_ready;
+wire          soc_litedramcore_bankmachine0_source_source_valid;
+wire          soc_litedramcore_bankmachine0_source_valid;
+wire   [23:0] soc_litedramcore_bankmachine0_syncfifo0_din;
+wire   [23:0] soc_litedramcore_bankmachine0_syncfifo0_dout;
+wire          soc_litedramcore_bankmachine0_syncfifo0_re;
+wire          soc_litedramcore_bankmachine0_syncfifo0_readable;
+wire          soc_litedramcore_bankmachine0_syncfifo0_we;
+wire          soc_litedramcore_bankmachine0_syncfifo0_writable;
 reg     [2:0] soc_litedramcore_bankmachine0_trascon_count = 3'd0;
-wire          soc_litedramcore_bankmachine1_req_valid;
-wire          soc_litedramcore_bankmachine1_req_ready;
-wire          soc_litedramcore_bankmachine1_req_we;
-wire   [20:0] soc_litedramcore_bankmachine1_req_addr;
-wire          soc_litedramcore_bankmachine1_req_lock;
-reg           soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg           soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
-wire          soc_litedramcore_bankmachine1_refresh_req;
-reg           soc_litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg           soc_litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg           soc_litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg           soc_litedramcore_bankmachine0_trascon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine0_trascon_valid;
+reg     [2:0] soc_litedramcore_bankmachine0_trccon_count = 3'd0;
+reg           soc_litedramcore_bankmachine0_trccon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine0_trccon_valid;
+reg     [2:0] soc_litedramcore_bankmachine0_twtpcon_count = 3'd0;
+reg           soc_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine0_twtpcon_valid;
+reg     [3:0] soc_litedramcore_bankmachine0_wrport_adr = 4'd0;
+wire   [23:0] soc_litedramcore_bankmachine0_wrport_dat_r;
+wire   [23:0] soc_litedramcore_bankmachine0_wrport_dat_w;
+wire          soc_litedramcore_bankmachine0_wrport_we;
+reg           soc_litedramcore_bankmachine1_auto_precharge = 1'd0;
 reg    [13:0] soc_litedramcore_bankmachine1_cmd_payload_a = 14'd0;
 wire    [2:0] soc_litedramcore_bankmachine1_cmd_payload_ba;
 reg           soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg           soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg           soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
 reg           soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
 reg           soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
 reg           soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg           soc_litedramcore_bankmachine1_auto_precharge = 1'd0;
-wire          soc_litedramcore_bankmachine1_sink_valid;
-wire          soc_litedramcore_bankmachine1_sink_ready;
-reg           soc_litedramcore_bankmachine1_sink_first = 1'd0;
-reg           soc_litedramcore_bankmachine1_sink_last = 1'd0;
-wire          soc_litedramcore_bankmachine1_sink_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine1_sink_payload_addr;
-wire          soc_litedramcore_bankmachine1_source_valid;
-wire          soc_litedramcore_bankmachine1_source_ready;
-wire          soc_litedramcore_bankmachine1_source_first;
-wire          soc_litedramcore_bankmachine1_source_last;
-wire          soc_litedramcore_bankmachine1_source_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine1_source_payload_addr;
-wire          soc_litedramcore_bankmachine1_syncfifo1_we;
-wire          soc_litedramcore_bankmachine1_syncfifo1_writable;
-wire          soc_litedramcore_bankmachine1_syncfifo1_re;
-wire          soc_litedramcore_bankmachine1_syncfifo1_readable;
-wire   [23:0] soc_litedramcore_bankmachine1_syncfifo1_din;
-wire   [23:0] soc_litedramcore_bankmachine1_syncfifo1_dout;
-reg     [4:0] soc_litedramcore_bankmachine1_level = 5'd0;
-reg           soc_litedramcore_bankmachine1_replace = 1'd0;
-reg     [3:0] soc_litedramcore_bankmachine1_produce = 4'd0;
+reg           soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg           soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg           soc_litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg           soc_litedramcore_bankmachine1_cmd_valid = 1'd0;
 reg     [3:0] soc_litedramcore_bankmachine1_consume = 4'd0;
-reg     [3:0] soc_litedramcore_bankmachine1_wrport_adr = 4'd0;
-wire   [23:0] soc_litedramcore_bankmachine1_wrport_dat_r;
-wire          soc_litedramcore_bankmachine1_wrport_we;
-wire   [23:0] soc_litedramcore_bankmachine1_wrport_dat_w;
 wire          soc_litedramcore_bankmachine1_do_read;
-wire    [3:0] soc_litedramcore_bankmachine1_rdport_adr;
-wire   [23:0] soc_litedramcore_bankmachine1_rdport_dat_r;
-wire          soc_litedramcore_bankmachine1_fifo_in_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine1_fifo_in_payload_addr;
 wire          soc_litedramcore_bankmachine1_fifo_in_first;
 wire          soc_litedramcore_bankmachine1_fifo_in_last;
-wire          soc_litedramcore_bankmachine1_fifo_out_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine1_fifo_out_payload_addr;
+wire   [20:0] soc_litedramcore_bankmachine1_fifo_in_payload_addr;
+wire          soc_litedramcore_bankmachine1_fifo_in_payload_we;
 wire          soc_litedramcore_bankmachine1_fifo_out_first;
 wire          soc_litedramcore_bankmachine1_fifo_out_last;
-wire          soc_litedramcore_bankmachine1_sink_sink_valid;
-wire          soc_litedramcore_bankmachine1_sink_sink_ready;
-wire          soc_litedramcore_bankmachine1_sink_sink_first;
-wire          soc_litedramcore_bankmachine1_sink_sink_last;
-wire          soc_litedramcore_bankmachine1_sink_sink_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine1_sink_sink_payload_addr;
-wire          soc_litedramcore_bankmachine1_source_source_valid;
-wire          soc_litedramcore_bankmachine1_source_source_ready;
-wire          soc_litedramcore_bankmachine1_source_source_first;
-wire          soc_litedramcore_bankmachine1_source_source_last;
-wire          soc_litedramcore_bankmachine1_source_source_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine1_source_source_payload_addr;
-wire          soc_litedramcore_bankmachine1_pipe_valid_sink_valid;
-wire          soc_litedramcore_bankmachine1_pipe_valid_sink_ready;
+wire   [20:0] soc_litedramcore_bankmachine1_fifo_out_payload_addr;
+wire          soc_litedramcore_bankmachine1_fifo_out_payload_we;
+reg     [4:0] soc_litedramcore_bankmachine1_level = 5'd0;
 wire          soc_litedramcore_bankmachine1_pipe_valid_sink_first;
 wire          soc_litedramcore_bankmachine1_pipe_valid_sink_last;
-wire          soc_litedramcore_bankmachine1_pipe_valid_sink_payload_we;
 wire   [20:0] soc_litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
-reg           soc_litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0;
-wire          soc_litedramcore_bankmachine1_pipe_valid_source_ready;
+wire          soc_litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+wire          soc_litedramcore_bankmachine1_pipe_valid_sink_ready;
+wire          soc_litedramcore_bankmachine1_pipe_valid_sink_valid;
 reg           soc_litedramcore_bankmachine1_pipe_valid_source_first = 1'd0;
 reg           soc_litedramcore_bankmachine1_pipe_valid_source_last = 1'd0;
-reg           soc_litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0;
 reg    [20:0] soc_litedramcore_bankmachine1_pipe_valid_source_payload_addr = 21'd0;
+reg           soc_litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0;
+wire          soc_litedramcore_bankmachine1_pipe_valid_source_ready;
+reg           soc_litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0;
+reg     [3:0] soc_litedramcore_bankmachine1_produce = 4'd0;
+wire    [3:0] soc_litedramcore_bankmachine1_rdport_adr;
+wire   [23:0] soc_litedramcore_bankmachine1_rdport_dat_r;
+reg           soc_litedramcore_bankmachine1_refresh_gnt = 1'd0;
+wire          soc_litedramcore_bankmachine1_refresh_req;
+reg           soc_litedramcore_bankmachine1_replace = 1'd0;
+wire   [20:0] soc_litedramcore_bankmachine1_req_addr;
+wire          soc_litedramcore_bankmachine1_req_lock;
+reg           soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire          soc_litedramcore_bankmachine1_req_ready;
+wire          soc_litedramcore_bankmachine1_req_valid;
+reg           soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+wire          soc_litedramcore_bankmachine1_req_we;
 reg    [13:0] soc_litedramcore_bankmachine1_row = 14'd0;
-reg           soc_litedramcore_bankmachine1_row_opened = 1'd0;
-wire          soc_litedramcore_bankmachine1_row_hit;
-reg           soc_litedramcore_bankmachine1_row_open = 1'd0;
 reg           soc_litedramcore_bankmachine1_row_close = 1'd0;
 reg           soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
-wire          soc_litedramcore_bankmachine1_twtpcon_valid;
-reg           soc_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg     [2:0] soc_litedramcore_bankmachine1_twtpcon_count = 3'd0;
-wire          soc_litedramcore_bankmachine1_trccon_valid;
-reg           soc_litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg     [2:0] soc_litedramcore_bankmachine1_trccon_count = 3'd0;
-wire          soc_litedramcore_bankmachine1_trascon_valid;
-reg           soc_litedramcore_bankmachine1_trascon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine1_row_hit;
+reg           soc_litedramcore_bankmachine1_row_open = 1'd0;
+reg           soc_litedramcore_bankmachine1_row_opened = 1'd0;
+reg           soc_litedramcore_bankmachine1_sink_first = 1'd0;
+reg           soc_litedramcore_bankmachine1_sink_last = 1'd0;
+wire   [20:0] soc_litedramcore_bankmachine1_sink_payload_addr;
+wire          soc_litedramcore_bankmachine1_sink_payload_we;
+wire          soc_litedramcore_bankmachine1_sink_ready;
+wire          soc_litedramcore_bankmachine1_sink_sink_first;
+wire          soc_litedramcore_bankmachine1_sink_sink_last;
+wire   [20:0] soc_litedramcore_bankmachine1_sink_sink_payload_addr;
+wire          soc_litedramcore_bankmachine1_sink_sink_payload_we;
+wire          soc_litedramcore_bankmachine1_sink_sink_ready;
+wire          soc_litedramcore_bankmachine1_sink_sink_valid;
+wire          soc_litedramcore_bankmachine1_sink_valid;
+wire          soc_litedramcore_bankmachine1_source_first;
+wire          soc_litedramcore_bankmachine1_source_last;
+wire   [20:0] soc_litedramcore_bankmachine1_source_payload_addr;
+wire          soc_litedramcore_bankmachine1_source_payload_we;
+wire          soc_litedramcore_bankmachine1_source_ready;
+wire          soc_litedramcore_bankmachine1_source_source_first;
+wire          soc_litedramcore_bankmachine1_source_source_last;
+wire   [20:0] soc_litedramcore_bankmachine1_source_source_payload_addr;
+wire          soc_litedramcore_bankmachine1_source_source_payload_we;
+wire          soc_litedramcore_bankmachine1_source_source_ready;
+wire          soc_litedramcore_bankmachine1_source_source_valid;
+wire          soc_litedramcore_bankmachine1_source_valid;
+wire   [23:0] soc_litedramcore_bankmachine1_syncfifo1_din;
+wire   [23:0] soc_litedramcore_bankmachine1_syncfifo1_dout;
+wire          soc_litedramcore_bankmachine1_syncfifo1_re;
+wire          soc_litedramcore_bankmachine1_syncfifo1_readable;
+wire          soc_litedramcore_bankmachine1_syncfifo1_we;
+wire          soc_litedramcore_bankmachine1_syncfifo1_writable;
 reg     [2:0] soc_litedramcore_bankmachine1_trascon_count = 3'd0;
-wire          soc_litedramcore_bankmachine2_req_valid;
-wire          soc_litedramcore_bankmachine2_req_ready;
-wire          soc_litedramcore_bankmachine2_req_we;
-wire   [20:0] soc_litedramcore_bankmachine2_req_addr;
-wire          soc_litedramcore_bankmachine2_req_lock;
-reg           soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg           soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
-wire          soc_litedramcore_bankmachine2_refresh_req;
-reg           soc_litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg           soc_litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg           soc_litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg           soc_litedramcore_bankmachine1_trascon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine1_trascon_valid;
+reg     [2:0] soc_litedramcore_bankmachine1_trccon_count = 3'd0;
+reg           soc_litedramcore_bankmachine1_trccon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine1_trccon_valid;
+reg     [2:0] soc_litedramcore_bankmachine1_twtpcon_count = 3'd0;
+reg           soc_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine1_twtpcon_valid;
+reg     [3:0] soc_litedramcore_bankmachine1_wrport_adr = 4'd0;
+wire   [23:0] soc_litedramcore_bankmachine1_wrport_dat_r;
+wire   [23:0] soc_litedramcore_bankmachine1_wrport_dat_w;
+wire          soc_litedramcore_bankmachine1_wrport_we;
+reg           soc_litedramcore_bankmachine2_auto_precharge = 1'd0;
 reg    [13:0] soc_litedramcore_bankmachine2_cmd_payload_a = 14'd0;
 wire    [2:0] soc_litedramcore_bankmachine2_cmd_payload_ba;
 reg           soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg           soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg           soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
 reg           soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
 reg           soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
 reg           soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg           soc_litedramcore_bankmachine2_auto_precharge = 1'd0;
-wire          soc_litedramcore_bankmachine2_sink_valid;
-wire          soc_litedramcore_bankmachine2_sink_ready;
-reg           soc_litedramcore_bankmachine2_sink_first = 1'd0;
-reg           soc_litedramcore_bankmachine2_sink_last = 1'd0;
-wire          soc_litedramcore_bankmachine2_sink_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine2_sink_payload_addr;
-wire          soc_litedramcore_bankmachine2_source_valid;
-wire          soc_litedramcore_bankmachine2_source_ready;
-wire          soc_litedramcore_bankmachine2_source_first;
-wire          soc_litedramcore_bankmachine2_source_last;
-wire          soc_litedramcore_bankmachine2_source_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine2_source_payload_addr;
-wire          soc_litedramcore_bankmachine2_syncfifo2_we;
-wire          soc_litedramcore_bankmachine2_syncfifo2_writable;
-wire          soc_litedramcore_bankmachine2_syncfifo2_re;
-wire          soc_litedramcore_bankmachine2_syncfifo2_readable;
-wire   [23:0] soc_litedramcore_bankmachine2_syncfifo2_din;
-wire   [23:0] soc_litedramcore_bankmachine2_syncfifo2_dout;
-reg     [4:0] soc_litedramcore_bankmachine2_level = 5'd0;
-reg           soc_litedramcore_bankmachine2_replace = 1'd0;
-reg     [3:0] soc_litedramcore_bankmachine2_produce = 4'd0;
+reg           soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg           soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg           soc_litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg           soc_litedramcore_bankmachine2_cmd_valid = 1'd0;
 reg     [3:0] soc_litedramcore_bankmachine2_consume = 4'd0;
-reg     [3:0] soc_litedramcore_bankmachine2_wrport_adr = 4'd0;
-wire   [23:0] soc_litedramcore_bankmachine2_wrport_dat_r;
-wire          soc_litedramcore_bankmachine2_wrport_we;
-wire   [23:0] soc_litedramcore_bankmachine2_wrport_dat_w;
 wire          soc_litedramcore_bankmachine2_do_read;
-wire    [3:0] soc_litedramcore_bankmachine2_rdport_adr;
-wire   [23:0] soc_litedramcore_bankmachine2_rdport_dat_r;
-wire          soc_litedramcore_bankmachine2_fifo_in_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine2_fifo_in_payload_addr;
 wire          soc_litedramcore_bankmachine2_fifo_in_first;
 wire          soc_litedramcore_bankmachine2_fifo_in_last;
-wire          soc_litedramcore_bankmachine2_fifo_out_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine2_fifo_out_payload_addr;
+wire   [20:0] soc_litedramcore_bankmachine2_fifo_in_payload_addr;
+wire          soc_litedramcore_bankmachine2_fifo_in_payload_we;
 wire          soc_litedramcore_bankmachine2_fifo_out_first;
 wire          soc_litedramcore_bankmachine2_fifo_out_last;
-wire          soc_litedramcore_bankmachine2_sink_sink_valid;
-wire          soc_litedramcore_bankmachine2_sink_sink_ready;
-wire          soc_litedramcore_bankmachine2_sink_sink_first;
-wire          soc_litedramcore_bankmachine2_sink_sink_last;
-wire          soc_litedramcore_bankmachine2_sink_sink_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine2_sink_sink_payload_addr;
-wire          soc_litedramcore_bankmachine2_source_source_valid;
-wire          soc_litedramcore_bankmachine2_source_source_ready;
-wire          soc_litedramcore_bankmachine2_source_source_first;
-wire          soc_litedramcore_bankmachine2_source_source_last;
-wire          soc_litedramcore_bankmachine2_source_source_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine2_source_source_payload_addr;
-wire          soc_litedramcore_bankmachine2_pipe_valid_sink_valid;
-wire          soc_litedramcore_bankmachine2_pipe_valid_sink_ready;
+wire   [20:0] soc_litedramcore_bankmachine2_fifo_out_payload_addr;
+wire          soc_litedramcore_bankmachine2_fifo_out_payload_we;
+reg     [4:0] soc_litedramcore_bankmachine2_level = 5'd0;
 wire          soc_litedramcore_bankmachine2_pipe_valid_sink_first;
 wire          soc_litedramcore_bankmachine2_pipe_valid_sink_last;
-wire          soc_litedramcore_bankmachine2_pipe_valid_sink_payload_we;
 wire   [20:0] soc_litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
-reg           soc_litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0;
-wire          soc_litedramcore_bankmachine2_pipe_valid_source_ready;
+wire          soc_litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+wire          soc_litedramcore_bankmachine2_pipe_valid_sink_ready;
+wire          soc_litedramcore_bankmachine2_pipe_valid_sink_valid;
 reg           soc_litedramcore_bankmachine2_pipe_valid_source_first = 1'd0;
 reg           soc_litedramcore_bankmachine2_pipe_valid_source_last = 1'd0;
-reg           soc_litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0;
 reg    [20:0] soc_litedramcore_bankmachine2_pipe_valid_source_payload_addr = 21'd0;
+reg           soc_litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0;
+wire          soc_litedramcore_bankmachine2_pipe_valid_source_ready;
+reg           soc_litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0;
+reg     [3:0] soc_litedramcore_bankmachine2_produce = 4'd0;
+wire    [3:0] soc_litedramcore_bankmachine2_rdport_adr;
+wire   [23:0] soc_litedramcore_bankmachine2_rdport_dat_r;
+reg           soc_litedramcore_bankmachine2_refresh_gnt = 1'd0;
+wire          soc_litedramcore_bankmachine2_refresh_req;
+reg           soc_litedramcore_bankmachine2_replace = 1'd0;
+wire   [20:0] soc_litedramcore_bankmachine2_req_addr;
+wire          soc_litedramcore_bankmachine2_req_lock;
+reg           soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire          soc_litedramcore_bankmachine2_req_ready;
+wire          soc_litedramcore_bankmachine2_req_valid;
+reg           soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+wire          soc_litedramcore_bankmachine2_req_we;
 reg    [13:0] soc_litedramcore_bankmachine2_row = 14'd0;
-reg           soc_litedramcore_bankmachine2_row_opened = 1'd0;
-wire          soc_litedramcore_bankmachine2_row_hit;
-reg           soc_litedramcore_bankmachine2_row_open = 1'd0;
 reg           soc_litedramcore_bankmachine2_row_close = 1'd0;
 reg           soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
-wire          soc_litedramcore_bankmachine2_twtpcon_valid;
-reg           soc_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg     [2:0] soc_litedramcore_bankmachine2_twtpcon_count = 3'd0;
-wire          soc_litedramcore_bankmachine2_trccon_valid;
-reg           soc_litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg     [2:0] soc_litedramcore_bankmachine2_trccon_count = 3'd0;
-wire          soc_litedramcore_bankmachine2_trascon_valid;
-reg           soc_litedramcore_bankmachine2_trascon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine2_row_hit;
+reg           soc_litedramcore_bankmachine2_row_open = 1'd0;
+reg           soc_litedramcore_bankmachine2_row_opened = 1'd0;
+reg           soc_litedramcore_bankmachine2_sink_first = 1'd0;
+reg           soc_litedramcore_bankmachine2_sink_last = 1'd0;
+wire   [20:0] soc_litedramcore_bankmachine2_sink_payload_addr;
+wire          soc_litedramcore_bankmachine2_sink_payload_we;
+wire          soc_litedramcore_bankmachine2_sink_ready;
+wire          soc_litedramcore_bankmachine2_sink_sink_first;
+wire          soc_litedramcore_bankmachine2_sink_sink_last;
+wire   [20:0] soc_litedramcore_bankmachine2_sink_sink_payload_addr;
+wire          soc_litedramcore_bankmachine2_sink_sink_payload_we;
+wire          soc_litedramcore_bankmachine2_sink_sink_ready;
+wire          soc_litedramcore_bankmachine2_sink_sink_valid;
+wire          soc_litedramcore_bankmachine2_sink_valid;
+wire          soc_litedramcore_bankmachine2_source_first;
+wire          soc_litedramcore_bankmachine2_source_last;
+wire   [20:0] soc_litedramcore_bankmachine2_source_payload_addr;
+wire          soc_litedramcore_bankmachine2_source_payload_we;
+wire          soc_litedramcore_bankmachine2_source_ready;
+wire          soc_litedramcore_bankmachine2_source_source_first;
+wire          soc_litedramcore_bankmachine2_source_source_last;
+wire   [20:0] soc_litedramcore_bankmachine2_source_source_payload_addr;
+wire          soc_litedramcore_bankmachine2_source_source_payload_we;
+wire          soc_litedramcore_bankmachine2_source_source_ready;
+wire          soc_litedramcore_bankmachine2_source_source_valid;
+wire          soc_litedramcore_bankmachine2_source_valid;
+wire   [23:0] soc_litedramcore_bankmachine2_syncfifo2_din;
+wire   [23:0] soc_litedramcore_bankmachine2_syncfifo2_dout;
+wire          soc_litedramcore_bankmachine2_syncfifo2_re;
+wire          soc_litedramcore_bankmachine2_syncfifo2_readable;
+wire          soc_litedramcore_bankmachine2_syncfifo2_we;
+wire          soc_litedramcore_bankmachine2_syncfifo2_writable;
 reg     [2:0] soc_litedramcore_bankmachine2_trascon_count = 3'd0;
-wire          soc_litedramcore_bankmachine3_req_valid;
-wire          soc_litedramcore_bankmachine3_req_ready;
-wire          soc_litedramcore_bankmachine3_req_we;
-wire   [20:0] soc_litedramcore_bankmachine3_req_addr;
-wire          soc_litedramcore_bankmachine3_req_lock;
-reg           soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg           soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
-wire          soc_litedramcore_bankmachine3_refresh_req;
-reg           soc_litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg           soc_litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg           soc_litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg           soc_litedramcore_bankmachine2_trascon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine2_trascon_valid;
+reg     [2:0] soc_litedramcore_bankmachine2_trccon_count = 3'd0;
+reg           soc_litedramcore_bankmachine2_trccon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine2_trccon_valid;
+reg     [2:0] soc_litedramcore_bankmachine2_twtpcon_count = 3'd0;
+reg           soc_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine2_twtpcon_valid;
+reg     [3:0] soc_litedramcore_bankmachine2_wrport_adr = 4'd0;
+wire   [23:0] soc_litedramcore_bankmachine2_wrport_dat_r;
+wire   [23:0] soc_litedramcore_bankmachine2_wrport_dat_w;
+wire          soc_litedramcore_bankmachine2_wrport_we;
+reg           soc_litedramcore_bankmachine3_auto_precharge = 1'd0;
 reg    [13:0] soc_litedramcore_bankmachine3_cmd_payload_a = 14'd0;
 wire    [2:0] soc_litedramcore_bankmachine3_cmd_payload_ba;
 reg           soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg           soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg           soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
 reg           soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
 reg           soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
 reg           soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg           soc_litedramcore_bankmachine3_auto_precharge = 1'd0;
-wire          soc_litedramcore_bankmachine3_sink_valid;
-wire          soc_litedramcore_bankmachine3_sink_ready;
-reg           soc_litedramcore_bankmachine3_sink_first = 1'd0;
-reg           soc_litedramcore_bankmachine3_sink_last = 1'd0;
-wire          soc_litedramcore_bankmachine3_sink_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine3_sink_payload_addr;
-wire          soc_litedramcore_bankmachine3_source_valid;
-wire          soc_litedramcore_bankmachine3_source_ready;
-wire          soc_litedramcore_bankmachine3_source_first;
-wire          soc_litedramcore_bankmachine3_source_last;
-wire          soc_litedramcore_bankmachine3_source_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine3_source_payload_addr;
-wire          soc_litedramcore_bankmachine3_syncfifo3_we;
-wire          soc_litedramcore_bankmachine3_syncfifo3_writable;
-wire          soc_litedramcore_bankmachine3_syncfifo3_re;
-wire          soc_litedramcore_bankmachine3_syncfifo3_readable;
-wire   [23:0] soc_litedramcore_bankmachine3_syncfifo3_din;
-wire   [23:0] soc_litedramcore_bankmachine3_syncfifo3_dout;
-reg     [4:0] soc_litedramcore_bankmachine3_level = 5'd0;
-reg           soc_litedramcore_bankmachine3_replace = 1'd0;
-reg     [3:0] soc_litedramcore_bankmachine3_produce = 4'd0;
+reg           soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg           soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg           soc_litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg           soc_litedramcore_bankmachine3_cmd_valid = 1'd0;
 reg     [3:0] soc_litedramcore_bankmachine3_consume = 4'd0;
-reg     [3:0] soc_litedramcore_bankmachine3_wrport_adr = 4'd0;
-wire   [23:0] soc_litedramcore_bankmachine3_wrport_dat_r;
-wire          soc_litedramcore_bankmachine3_wrport_we;
-wire   [23:0] soc_litedramcore_bankmachine3_wrport_dat_w;
 wire          soc_litedramcore_bankmachine3_do_read;
-wire    [3:0] soc_litedramcore_bankmachine3_rdport_adr;
-wire   [23:0] soc_litedramcore_bankmachine3_rdport_dat_r;
-wire          soc_litedramcore_bankmachine3_fifo_in_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine3_fifo_in_payload_addr;
 wire          soc_litedramcore_bankmachine3_fifo_in_first;
 wire          soc_litedramcore_bankmachine3_fifo_in_last;
-wire          soc_litedramcore_bankmachine3_fifo_out_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine3_fifo_out_payload_addr;
+wire   [20:0] soc_litedramcore_bankmachine3_fifo_in_payload_addr;
+wire          soc_litedramcore_bankmachine3_fifo_in_payload_we;
 wire          soc_litedramcore_bankmachine3_fifo_out_first;
 wire          soc_litedramcore_bankmachine3_fifo_out_last;
-wire          soc_litedramcore_bankmachine3_sink_sink_valid;
-wire          soc_litedramcore_bankmachine3_sink_sink_ready;
-wire          soc_litedramcore_bankmachine3_sink_sink_first;
-wire          soc_litedramcore_bankmachine3_sink_sink_last;
-wire          soc_litedramcore_bankmachine3_sink_sink_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine3_sink_sink_payload_addr;
-wire          soc_litedramcore_bankmachine3_source_source_valid;
-wire          soc_litedramcore_bankmachine3_source_source_ready;
-wire          soc_litedramcore_bankmachine3_source_source_first;
-wire          soc_litedramcore_bankmachine3_source_source_last;
-wire          soc_litedramcore_bankmachine3_source_source_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine3_source_source_payload_addr;
-wire          soc_litedramcore_bankmachine3_pipe_valid_sink_valid;
-wire          soc_litedramcore_bankmachine3_pipe_valid_sink_ready;
+wire   [20:0] soc_litedramcore_bankmachine3_fifo_out_payload_addr;
+wire          soc_litedramcore_bankmachine3_fifo_out_payload_we;
+reg     [4:0] soc_litedramcore_bankmachine3_level = 5'd0;
 wire          soc_litedramcore_bankmachine3_pipe_valid_sink_first;
 wire          soc_litedramcore_bankmachine3_pipe_valid_sink_last;
-wire          soc_litedramcore_bankmachine3_pipe_valid_sink_payload_we;
 wire   [20:0] soc_litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
-reg           soc_litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0;
-wire          soc_litedramcore_bankmachine3_pipe_valid_source_ready;
+wire          soc_litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+wire          soc_litedramcore_bankmachine3_pipe_valid_sink_ready;
+wire          soc_litedramcore_bankmachine3_pipe_valid_sink_valid;
 reg           soc_litedramcore_bankmachine3_pipe_valid_source_first = 1'd0;
 reg           soc_litedramcore_bankmachine3_pipe_valid_source_last = 1'd0;
-reg           soc_litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0;
 reg    [20:0] soc_litedramcore_bankmachine3_pipe_valid_source_payload_addr = 21'd0;
+reg           soc_litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0;
+wire          soc_litedramcore_bankmachine3_pipe_valid_source_ready;
+reg           soc_litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0;
+reg     [3:0] soc_litedramcore_bankmachine3_produce = 4'd0;
+wire    [3:0] soc_litedramcore_bankmachine3_rdport_adr;
+wire   [23:0] soc_litedramcore_bankmachine3_rdport_dat_r;
+reg           soc_litedramcore_bankmachine3_refresh_gnt = 1'd0;
+wire          soc_litedramcore_bankmachine3_refresh_req;
+reg           soc_litedramcore_bankmachine3_replace = 1'd0;
+wire   [20:0] soc_litedramcore_bankmachine3_req_addr;
+wire          soc_litedramcore_bankmachine3_req_lock;
+reg           soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire          soc_litedramcore_bankmachine3_req_ready;
+wire          soc_litedramcore_bankmachine3_req_valid;
+reg           soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+wire          soc_litedramcore_bankmachine3_req_we;
 reg    [13:0] soc_litedramcore_bankmachine3_row = 14'd0;
-reg           soc_litedramcore_bankmachine3_row_opened = 1'd0;
-wire          soc_litedramcore_bankmachine3_row_hit;
-reg           soc_litedramcore_bankmachine3_row_open = 1'd0;
 reg           soc_litedramcore_bankmachine3_row_close = 1'd0;
 reg           soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
-wire          soc_litedramcore_bankmachine3_twtpcon_valid;
-reg           soc_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg     [2:0] soc_litedramcore_bankmachine3_twtpcon_count = 3'd0;
-wire          soc_litedramcore_bankmachine3_trccon_valid;
-reg           soc_litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg     [2:0] soc_litedramcore_bankmachine3_trccon_count = 3'd0;
-wire          soc_litedramcore_bankmachine3_trascon_valid;
-reg           soc_litedramcore_bankmachine3_trascon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine3_row_hit;
+reg           soc_litedramcore_bankmachine3_row_open = 1'd0;
+reg           soc_litedramcore_bankmachine3_row_opened = 1'd0;
+reg           soc_litedramcore_bankmachine3_sink_first = 1'd0;
+reg           soc_litedramcore_bankmachine3_sink_last = 1'd0;
+wire   [20:0] soc_litedramcore_bankmachine3_sink_payload_addr;
+wire          soc_litedramcore_bankmachine3_sink_payload_we;
+wire          soc_litedramcore_bankmachine3_sink_ready;
+wire          soc_litedramcore_bankmachine3_sink_sink_first;
+wire          soc_litedramcore_bankmachine3_sink_sink_last;
+wire   [20:0] soc_litedramcore_bankmachine3_sink_sink_payload_addr;
+wire          soc_litedramcore_bankmachine3_sink_sink_payload_we;
+wire          soc_litedramcore_bankmachine3_sink_sink_ready;
+wire          soc_litedramcore_bankmachine3_sink_sink_valid;
+wire          soc_litedramcore_bankmachine3_sink_valid;
+wire          soc_litedramcore_bankmachine3_source_first;
+wire          soc_litedramcore_bankmachine3_source_last;
+wire   [20:0] soc_litedramcore_bankmachine3_source_payload_addr;
+wire          soc_litedramcore_bankmachine3_source_payload_we;
+wire          soc_litedramcore_bankmachine3_source_ready;
+wire          soc_litedramcore_bankmachine3_source_source_first;
+wire          soc_litedramcore_bankmachine3_source_source_last;
+wire   [20:0] soc_litedramcore_bankmachine3_source_source_payload_addr;
+wire          soc_litedramcore_bankmachine3_source_source_payload_we;
+wire          soc_litedramcore_bankmachine3_source_source_ready;
+wire          soc_litedramcore_bankmachine3_source_source_valid;
+wire          soc_litedramcore_bankmachine3_source_valid;
+wire   [23:0] soc_litedramcore_bankmachine3_syncfifo3_din;
+wire   [23:0] soc_litedramcore_bankmachine3_syncfifo3_dout;
+wire          soc_litedramcore_bankmachine3_syncfifo3_re;
+wire          soc_litedramcore_bankmachine3_syncfifo3_readable;
+wire          soc_litedramcore_bankmachine3_syncfifo3_we;
+wire          soc_litedramcore_bankmachine3_syncfifo3_writable;
 reg     [2:0] soc_litedramcore_bankmachine3_trascon_count = 3'd0;
-wire          soc_litedramcore_bankmachine4_req_valid;
-wire          soc_litedramcore_bankmachine4_req_ready;
-wire          soc_litedramcore_bankmachine4_req_we;
-wire   [20:0] soc_litedramcore_bankmachine4_req_addr;
-wire          soc_litedramcore_bankmachine4_req_lock;
-reg           soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg           soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
-wire          soc_litedramcore_bankmachine4_refresh_req;
-reg           soc_litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg           soc_litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg           soc_litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg           soc_litedramcore_bankmachine3_trascon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine3_trascon_valid;
+reg     [2:0] soc_litedramcore_bankmachine3_trccon_count = 3'd0;
+reg           soc_litedramcore_bankmachine3_trccon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine3_trccon_valid;
+reg     [2:0] soc_litedramcore_bankmachine3_twtpcon_count = 3'd0;
+reg           soc_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine3_twtpcon_valid;
+reg     [3:0] soc_litedramcore_bankmachine3_wrport_adr = 4'd0;
+wire   [23:0] soc_litedramcore_bankmachine3_wrport_dat_r;
+wire   [23:0] soc_litedramcore_bankmachine3_wrport_dat_w;
+wire          soc_litedramcore_bankmachine3_wrport_we;
+reg           soc_litedramcore_bankmachine4_auto_precharge = 1'd0;
 reg    [13:0] soc_litedramcore_bankmachine4_cmd_payload_a = 14'd0;
 wire    [2:0] soc_litedramcore_bankmachine4_cmd_payload_ba;
 reg           soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg           soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg           soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
 reg           soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
 reg           soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
 reg           soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg           soc_litedramcore_bankmachine4_auto_precharge = 1'd0;
-wire          soc_litedramcore_bankmachine4_sink_valid;
-wire          soc_litedramcore_bankmachine4_sink_ready;
-reg           soc_litedramcore_bankmachine4_sink_first = 1'd0;
-reg           soc_litedramcore_bankmachine4_sink_last = 1'd0;
-wire          soc_litedramcore_bankmachine4_sink_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine4_sink_payload_addr;
-wire          soc_litedramcore_bankmachine4_source_valid;
-wire          soc_litedramcore_bankmachine4_source_ready;
-wire          soc_litedramcore_bankmachine4_source_first;
-wire          soc_litedramcore_bankmachine4_source_last;
-wire          soc_litedramcore_bankmachine4_source_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine4_source_payload_addr;
-wire          soc_litedramcore_bankmachine4_syncfifo4_we;
-wire          soc_litedramcore_bankmachine4_syncfifo4_writable;
-wire          soc_litedramcore_bankmachine4_syncfifo4_re;
-wire          soc_litedramcore_bankmachine4_syncfifo4_readable;
-wire   [23:0] soc_litedramcore_bankmachine4_syncfifo4_din;
-wire   [23:0] soc_litedramcore_bankmachine4_syncfifo4_dout;
-reg     [4:0] soc_litedramcore_bankmachine4_level = 5'd0;
-reg           soc_litedramcore_bankmachine4_replace = 1'd0;
-reg     [3:0] soc_litedramcore_bankmachine4_produce = 4'd0;
+reg           soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg           soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg           soc_litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg           soc_litedramcore_bankmachine4_cmd_valid = 1'd0;
 reg     [3:0] soc_litedramcore_bankmachine4_consume = 4'd0;
-reg     [3:0] soc_litedramcore_bankmachine4_wrport_adr = 4'd0;
-wire   [23:0] soc_litedramcore_bankmachine4_wrport_dat_r;
-wire          soc_litedramcore_bankmachine4_wrport_we;
-wire   [23:0] soc_litedramcore_bankmachine4_wrport_dat_w;
 wire          soc_litedramcore_bankmachine4_do_read;
-wire    [3:0] soc_litedramcore_bankmachine4_rdport_adr;
-wire   [23:0] soc_litedramcore_bankmachine4_rdport_dat_r;
-wire          soc_litedramcore_bankmachine4_fifo_in_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine4_fifo_in_payload_addr;
 wire          soc_litedramcore_bankmachine4_fifo_in_first;
 wire          soc_litedramcore_bankmachine4_fifo_in_last;
-wire          soc_litedramcore_bankmachine4_fifo_out_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine4_fifo_out_payload_addr;
+wire   [20:0] soc_litedramcore_bankmachine4_fifo_in_payload_addr;
+wire          soc_litedramcore_bankmachine4_fifo_in_payload_we;
 wire          soc_litedramcore_bankmachine4_fifo_out_first;
 wire          soc_litedramcore_bankmachine4_fifo_out_last;
-wire          soc_litedramcore_bankmachine4_sink_sink_valid;
-wire          soc_litedramcore_bankmachine4_sink_sink_ready;
-wire          soc_litedramcore_bankmachine4_sink_sink_first;
-wire          soc_litedramcore_bankmachine4_sink_sink_last;
-wire          soc_litedramcore_bankmachine4_sink_sink_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine4_sink_sink_payload_addr;
-wire          soc_litedramcore_bankmachine4_source_source_valid;
-wire          soc_litedramcore_bankmachine4_source_source_ready;
-wire          soc_litedramcore_bankmachine4_source_source_first;
-wire          soc_litedramcore_bankmachine4_source_source_last;
-wire          soc_litedramcore_bankmachine4_source_source_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine4_source_source_payload_addr;
-wire          soc_litedramcore_bankmachine4_pipe_valid_sink_valid;
-wire          soc_litedramcore_bankmachine4_pipe_valid_sink_ready;
+wire   [20:0] soc_litedramcore_bankmachine4_fifo_out_payload_addr;
+wire          soc_litedramcore_bankmachine4_fifo_out_payload_we;
+reg     [4:0] soc_litedramcore_bankmachine4_level = 5'd0;
 wire          soc_litedramcore_bankmachine4_pipe_valid_sink_first;
 wire          soc_litedramcore_bankmachine4_pipe_valid_sink_last;
-wire          soc_litedramcore_bankmachine4_pipe_valid_sink_payload_we;
 wire   [20:0] soc_litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
-reg           soc_litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0;
-wire          soc_litedramcore_bankmachine4_pipe_valid_source_ready;
+wire          soc_litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+wire          soc_litedramcore_bankmachine4_pipe_valid_sink_ready;
+wire          soc_litedramcore_bankmachine4_pipe_valid_sink_valid;
 reg           soc_litedramcore_bankmachine4_pipe_valid_source_first = 1'd0;
 reg           soc_litedramcore_bankmachine4_pipe_valid_source_last = 1'd0;
-reg           soc_litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0;
 reg    [20:0] soc_litedramcore_bankmachine4_pipe_valid_source_payload_addr = 21'd0;
+reg           soc_litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0;
+wire          soc_litedramcore_bankmachine4_pipe_valid_source_ready;
+reg           soc_litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0;
+reg     [3:0] soc_litedramcore_bankmachine4_produce = 4'd0;
+wire    [3:0] soc_litedramcore_bankmachine4_rdport_adr;
+wire   [23:0] soc_litedramcore_bankmachine4_rdport_dat_r;
+reg           soc_litedramcore_bankmachine4_refresh_gnt = 1'd0;
+wire          soc_litedramcore_bankmachine4_refresh_req;
+reg           soc_litedramcore_bankmachine4_replace = 1'd0;
+wire   [20:0] soc_litedramcore_bankmachine4_req_addr;
+wire          soc_litedramcore_bankmachine4_req_lock;
+reg           soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire          soc_litedramcore_bankmachine4_req_ready;
+wire          soc_litedramcore_bankmachine4_req_valid;
+reg           soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+wire          soc_litedramcore_bankmachine4_req_we;
 reg    [13:0] soc_litedramcore_bankmachine4_row = 14'd0;
-reg           soc_litedramcore_bankmachine4_row_opened = 1'd0;
-wire          soc_litedramcore_bankmachine4_row_hit;
-reg           soc_litedramcore_bankmachine4_row_open = 1'd0;
 reg           soc_litedramcore_bankmachine4_row_close = 1'd0;
 reg           soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
-wire          soc_litedramcore_bankmachine4_twtpcon_valid;
-reg           soc_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg     [2:0] soc_litedramcore_bankmachine4_twtpcon_count = 3'd0;
-wire          soc_litedramcore_bankmachine4_trccon_valid;
-reg           soc_litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg     [2:0] soc_litedramcore_bankmachine4_trccon_count = 3'd0;
-wire          soc_litedramcore_bankmachine4_trascon_valid;
-reg           soc_litedramcore_bankmachine4_trascon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine4_row_hit;
+reg           soc_litedramcore_bankmachine4_row_open = 1'd0;
+reg           soc_litedramcore_bankmachine4_row_opened = 1'd0;
+reg           soc_litedramcore_bankmachine4_sink_first = 1'd0;
+reg           soc_litedramcore_bankmachine4_sink_last = 1'd0;
+wire   [20:0] soc_litedramcore_bankmachine4_sink_payload_addr;
+wire          soc_litedramcore_bankmachine4_sink_payload_we;
+wire          soc_litedramcore_bankmachine4_sink_ready;
+wire          soc_litedramcore_bankmachine4_sink_sink_first;
+wire          soc_litedramcore_bankmachine4_sink_sink_last;
+wire   [20:0] soc_litedramcore_bankmachine4_sink_sink_payload_addr;
+wire          soc_litedramcore_bankmachine4_sink_sink_payload_we;
+wire          soc_litedramcore_bankmachine4_sink_sink_ready;
+wire          soc_litedramcore_bankmachine4_sink_sink_valid;
+wire          soc_litedramcore_bankmachine4_sink_valid;
+wire          soc_litedramcore_bankmachine4_source_first;
+wire          soc_litedramcore_bankmachine4_source_last;
+wire   [20:0] soc_litedramcore_bankmachine4_source_payload_addr;
+wire          soc_litedramcore_bankmachine4_source_payload_we;
+wire          soc_litedramcore_bankmachine4_source_ready;
+wire          soc_litedramcore_bankmachine4_source_source_first;
+wire          soc_litedramcore_bankmachine4_source_source_last;
+wire   [20:0] soc_litedramcore_bankmachine4_source_source_payload_addr;
+wire          soc_litedramcore_bankmachine4_source_source_payload_we;
+wire          soc_litedramcore_bankmachine4_source_source_ready;
+wire          soc_litedramcore_bankmachine4_source_source_valid;
+wire          soc_litedramcore_bankmachine4_source_valid;
+wire   [23:0] soc_litedramcore_bankmachine4_syncfifo4_din;
+wire   [23:0] soc_litedramcore_bankmachine4_syncfifo4_dout;
+wire          soc_litedramcore_bankmachine4_syncfifo4_re;
+wire          soc_litedramcore_bankmachine4_syncfifo4_readable;
+wire          soc_litedramcore_bankmachine4_syncfifo4_we;
+wire          soc_litedramcore_bankmachine4_syncfifo4_writable;
 reg     [2:0] soc_litedramcore_bankmachine4_trascon_count = 3'd0;
-wire          soc_litedramcore_bankmachine5_req_valid;
-wire          soc_litedramcore_bankmachine5_req_ready;
-wire          soc_litedramcore_bankmachine5_req_we;
-wire   [20:0] soc_litedramcore_bankmachine5_req_addr;
-wire          soc_litedramcore_bankmachine5_req_lock;
-reg           soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg           soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
-wire          soc_litedramcore_bankmachine5_refresh_req;
-reg           soc_litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg           soc_litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg           soc_litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg           soc_litedramcore_bankmachine4_trascon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine4_trascon_valid;
+reg     [2:0] soc_litedramcore_bankmachine4_trccon_count = 3'd0;
+reg           soc_litedramcore_bankmachine4_trccon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine4_trccon_valid;
+reg     [2:0] soc_litedramcore_bankmachine4_twtpcon_count = 3'd0;
+reg           soc_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine4_twtpcon_valid;
+reg     [3:0] soc_litedramcore_bankmachine4_wrport_adr = 4'd0;
+wire   [23:0] soc_litedramcore_bankmachine4_wrport_dat_r;
+wire   [23:0] soc_litedramcore_bankmachine4_wrport_dat_w;
+wire          soc_litedramcore_bankmachine4_wrport_we;
+reg           soc_litedramcore_bankmachine5_auto_precharge = 1'd0;
 reg    [13:0] soc_litedramcore_bankmachine5_cmd_payload_a = 14'd0;
 wire    [2:0] soc_litedramcore_bankmachine5_cmd_payload_ba;
 reg           soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg           soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg           soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
 reg           soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
 reg           soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
 reg           soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg           soc_litedramcore_bankmachine5_auto_precharge = 1'd0;
-wire          soc_litedramcore_bankmachine5_sink_valid;
-wire          soc_litedramcore_bankmachine5_sink_ready;
-reg           soc_litedramcore_bankmachine5_sink_first = 1'd0;
-reg           soc_litedramcore_bankmachine5_sink_last = 1'd0;
-wire          soc_litedramcore_bankmachine5_sink_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine5_sink_payload_addr;
-wire          soc_litedramcore_bankmachine5_source_valid;
-wire          soc_litedramcore_bankmachine5_source_ready;
-wire          soc_litedramcore_bankmachine5_source_first;
-wire          soc_litedramcore_bankmachine5_source_last;
-wire          soc_litedramcore_bankmachine5_source_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine5_source_payload_addr;
-wire          soc_litedramcore_bankmachine5_syncfifo5_we;
-wire          soc_litedramcore_bankmachine5_syncfifo5_writable;
-wire          soc_litedramcore_bankmachine5_syncfifo5_re;
-wire          soc_litedramcore_bankmachine5_syncfifo5_readable;
-wire   [23:0] soc_litedramcore_bankmachine5_syncfifo5_din;
-wire   [23:0] soc_litedramcore_bankmachine5_syncfifo5_dout;
-reg     [4:0] soc_litedramcore_bankmachine5_level = 5'd0;
-reg           soc_litedramcore_bankmachine5_replace = 1'd0;
-reg     [3:0] soc_litedramcore_bankmachine5_produce = 4'd0;
+reg           soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg           soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg           soc_litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg           soc_litedramcore_bankmachine5_cmd_valid = 1'd0;
 reg     [3:0] soc_litedramcore_bankmachine5_consume = 4'd0;
-reg     [3:0] soc_litedramcore_bankmachine5_wrport_adr = 4'd0;
-wire   [23:0] soc_litedramcore_bankmachine5_wrport_dat_r;
-wire          soc_litedramcore_bankmachine5_wrport_we;
-wire   [23:0] soc_litedramcore_bankmachine5_wrport_dat_w;
 wire          soc_litedramcore_bankmachine5_do_read;
-wire    [3:0] soc_litedramcore_bankmachine5_rdport_adr;
-wire   [23:0] soc_litedramcore_bankmachine5_rdport_dat_r;
-wire          soc_litedramcore_bankmachine5_fifo_in_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine5_fifo_in_payload_addr;
 wire          soc_litedramcore_bankmachine5_fifo_in_first;
 wire          soc_litedramcore_bankmachine5_fifo_in_last;
-wire          soc_litedramcore_bankmachine5_fifo_out_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine5_fifo_out_payload_addr;
+wire   [20:0] soc_litedramcore_bankmachine5_fifo_in_payload_addr;
+wire          soc_litedramcore_bankmachine5_fifo_in_payload_we;
 wire          soc_litedramcore_bankmachine5_fifo_out_first;
 wire          soc_litedramcore_bankmachine5_fifo_out_last;
-wire          soc_litedramcore_bankmachine5_sink_sink_valid;
-wire          soc_litedramcore_bankmachine5_sink_sink_ready;
-wire          soc_litedramcore_bankmachine5_sink_sink_first;
-wire          soc_litedramcore_bankmachine5_sink_sink_last;
-wire          soc_litedramcore_bankmachine5_sink_sink_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine5_sink_sink_payload_addr;
-wire          soc_litedramcore_bankmachine5_source_source_valid;
-wire          soc_litedramcore_bankmachine5_source_source_ready;
-wire          soc_litedramcore_bankmachine5_source_source_first;
-wire          soc_litedramcore_bankmachine5_source_source_last;
-wire          soc_litedramcore_bankmachine5_source_source_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine5_source_source_payload_addr;
-wire          soc_litedramcore_bankmachine5_pipe_valid_sink_valid;
-wire          soc_litedramcore_bankmachine5_pipe_valid_sink_ready;
+wire   [20:0] soc_litedramcore_bankmachine5_fifo_out_payload_addr;
+wire          soc_litedramcore_bankmachine5_fifo_out_payload_we;
+reg     [4:0] soc_litedramcore_bankmachine5_level = 5'd0;
 wire          soc_litedramcore_bankmachine5_pipe_valid_sink_first;
 wire          soc_litedramcore_bankmachine5_pipe_valid_sink_last;
-wire          soc_litedramcore_bankmachine5_pipe_valid_sink_payload_we;
 wire   [20:0] soc_litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
-reg           soc_litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0;
-wire          soc_litedramcore_bankmachine5_pipe_valid_source_ready;
+wire          soc_litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+wire          soc_litedramcore_bankmachine5_pipe_valid_sink_ready;
+wire          soc_litedramcore_bankmachine5_pipe_valid_sink_valid;
 reg           soc_litedramcore_bankmachine5_pipe_valid_source_first = 1'd0;
 reg           soc_litedramcore_bankmachine5_pipe_valid_source_last = 1'd0;
-reg           soc_litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0;
 reg    [20:0] soc_litedramcore_bankmachine5_pipe_valid_source_payload_addr = 21'd0;
+reg           soc_litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0;
+wire          soc_litedramcore_bankmachine5_pipe_valid_source_ready;
+reg           soc_litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0;
+reg     [3:0] soc_litedramcore_bankmachine5_produce = 4'd0;
+wire    [3:0] soc_litedramcore_bankmachine5_rdport_adr;
+wire   [23:0] soc_litedramcore_bankmachine5_rdport_dat_r;
+reg           soc_litedramcore_bankmachine5_refresh_gnt = 1'd0;
+wire          soc_litedramcore_bankmachine5_refresh_req;
+reg           soc_litedramcore_bankmachine5_replace = 1'd0;
+wire   [20:0] soc_litedramcore_bankmachine5_req_addr;
+wire          soc_litedramcore_bankmachine5_req_lock;
+reg           soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire          soc_litedramcore_bankmachine5_req_ready;
+wire          soc_litedramcore_bankmachine5_req_valid;
+reg           soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+wire          soc_litedramcore_bankmachine5_req_we;
 reg    [13:0] soc_litedramcore_bankmachine5_row = 14'd0;
-reg           soc_litedramcore_bankmachine5_row_opened = 1'd0;
-wire          soc_litedramcore_bankmachine5_row_hit;
-reg           soc_litedramcore_bankmachine5_row_open = 1'd0;
 reg           soc_litedramcore_bankmachine5_row_close = 1'd0;
 reg           soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
-wire          soc_litedramcore_bankmachine5_twtpcon_valid;
-reg           soc_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg     [2:0] soc_litedramcore_bankmachine5_twtpcon_count = 3'd0;
-wire          soc_litedramcore_bankmachine5_trccon_valid;
-reg           soc_litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg     [2:0] soc_litedramcore_bankmachine5_trccon_count = 3'd0;
-wire          soc_litedramcore_bankmachine5_trascon_valid;
-reg           soc_litedramcore_bankmachine5_trascon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine5_row_hit;
+reg           soc_litedramcore_bankmachine5_row_open = 1'd0;
+reg           soc_litedramcore_bankmachine5_row_opened = 1'd0;
+reg           soc_litedramcore_bankmachine5_sink_first = 1'd0;
+reg           soc_litedramcore_bankmachine5_sink_last = 1'd0;
+wire   [20:0] soc_litedramcore_bankmachine5_sink_payload_addr;
+wire          soc_litedramcore_bankmachine5_sink_payload_we;
+wire          soc_litedramcore_bankmachine5_sink_ready;
+wire          soc_litedramcore_bankmachine5_sink_sink_first;
+wire          soc_litedramcore_bankmachine5_sink_sink_last;
+wire   [20:0] soc_litedramcore_bankmachine5_sink_sink_payload_addr;
+wire          soc_litedramcore_bankmachine5_sink_sink_payload_we;
+wire          soc_litedramcore_bankmachine5_sink_sink_ready;
+wire          soc_litedramcore_bankmachine5_sink_sink_valid;
+wire          soc_litedramcore_bankmachine5_sink_valid;
+wire          soc_litedramcore_bankmachine5_source_first;
+wire          soc_litedramcore_bankmachine5_source_last;
+wire   [20:0] soc_litedramcore_bankmachine5_source_payload_addr;
+wire          soc_litedramcore_bankmachine5_source_payload_we;
+wire          soc_litedramcore_bankmachine5_source_ready;
+wire          soc_litedramcore_bankmachine5_source_source_first;
+wire          soc_litedramcore_bankmachine5_source_source_last;
+wire   [20:0] soc_litedramcore_bankmachine5_source_source_payload_addr;
+wire          soc_litedramcore_bankmachine5_source_source_payload_we;
+wire          soc_litedramcore_bankmachine5_source_source_ready;
+wire          soc_litedramcore_bankmachine5_source_source_valid;
+wire          soc_litedramcore_bankmachine5_source_valid;
+wire   [23:0] soc_litedramcore_bankmachine5_syncfifo5_din;
+wire   [23:0] soc_litedramcore_bankmachine5_syncfifo5_dout;
+wire          soc_litedramcore_bankmachine5_syncfifo5_re;
+wire          soc_litedramcore_bankmachine5_syncfifo5_readable;
+wire          soc_litedramcore_bankmachine5_syncfifo5_we;
+wire          soc_litedramcore_bankmachine5_syncfifo5_writable;
 reg     [2:0] soc_litedramcore_bankmachine5_trascon_count = 3'd0;
-wire          soc_litedramcore_bankmachine6_req_valid;
-wire          soc_litedramcore_bankmachine6_req_ready;
-wire          soc_litedramcore_bankmachine6_req_we;
-wire   [20:0] soc_litedramcore_bankmachine6_req_addr;
-wire          soc_litedramcore_bankmachine6_req_lock;
-reg           soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg           soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
-wire          soc_litedramcore_bankmachine6_refresh_req;
-reg           soc_litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg           soc_litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg           soc_litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg           soc_litedramcore_bankmachine5_trascon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine5_trascon_valid;
+reg     [2:0] soc_litedramcore_bankmachine5_trccon_count = 3'd0;
+reg           soc_litedramcore_bankmachine5_trccon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine5_trccon_valid;
+reg     [2:0] soc_litedramcore_bankmachine5_twtpcon_count = 3'd0;
+reg           soc_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine5_twtpcon_valid;
+reg     [3:0] soc_litedramcore_bankmachine5_wrport_adr = 4'd0;
+wire   [23:0] soc_litedramcore_bankmachine5_wrport_dat_r;
+wire   [23:0] soc_litedramcore_bankmachine5_wrport_dat_w;
+wire          soc_litedramcore_bankmachine5_wrport_we;
+reg           soc_litedramcore_bankmachine6_auto_precharge = 1'd0;
 reg    [13:0] soc_litedramcore_bankmachine6_cmd_payload_a = 14'd0;
 wire    [2:0] soc_litedramcore_bankmachine6_cmd_payload_ba;
 reg           soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg           soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg           soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
 reg           soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
 reg           soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
 reg           soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg           soc_litedramcore_bankmachine6_auto_precharge = 1'd0;
-wire          soc_litedramcore_bankmachine6_sink_valid;
-wire          soc_litedramcore_bankmachine6_sink_ready;
-reg           soc_litedramcore_bankmachine6_sink_first = 1'd0;
-reg           soc_litedramcore_bankmachine6_sink_last = 1'd0;
-wire          soc_litedramcore_bankmachine6_sink_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine6_sink_payload_addr;
-wire          soc_litedramcore_bankmachine6_source_valid;
-wire          soc_litedramcore_bankmachine6_source_ready;
-wire          soc_litedramcore_bankmachine6_source_first;
-wire          soc_litedramcore_bankmachine6_source_last;
-wire          soc_litedramcore_bankmachine6_source_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine6_source_payload_addr;
-wire          soc_litedramcore_bankmachine6_syncfifo6_we;
-wire          soc_litedramcore_bankmachine6_syncfifo6_writable;
-wire          soc_litedramcore_bankmachine6_syncfifo6_re;
-wire          soc_litedramcore_bankmachine6_syncfifo6_readable;
-wire   [23:0] soc_litedramcore_bankmachine6_syncfifo6_din;
-wire   [23:0] soc_litedramcore_bankmachine6_syncfifo6_dout;
-reg     [4:0] soc_litedramcore_bankmachine6_level = 5'd0;
-reg           soc_litedramcore_bankmachine6_replace = 1'd0;
-reg     [3:0] soc_litedramcore_bankmachine6_produce = 4'd0;
+reg           soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg           soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg           soc_litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg           soc_litedramcore_bankmachine6_cmd_valid = 1'd0;
 reg     [3:0] soc_litedramcore_bankmachine6_consume = 4'd0;
-reg     [3:0] soc_litedramcore_bankmachine6_wrport_adr = 4'd0;
-wire   [23:0] soc_litedramcore_bankmachine6_wrport_dat_r;
-wire          soc_litedramcore_bankmachine6_wrport_we;
-wire   [23:0] soc_litedramcore_bankmachine6_wrport_dat_w;
 wire          soc_litedramcore_bankmachine6_do_read;
-wire    [3:0] soc_litedramcore_bankmachine6_rdport_adr;
-wire   [23:0] soc_litedramcore_bankmachine6_rdport_dat_r;
-wire          soc_litedramcore_bankmachine6_fifo_in_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine6_fifo_in_payload_addr;
 wire          soc_litedramcore_bankmachine6_fifo_in_first;
 wire          soc_litedramcore_bankmachine6_fifo_in_last;
-wire          soc_litedramcore_bankmachine6_fifo_out_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine6_fifo_out_payload_addr;
+wire   [20:0] soc_litedramcore_bankmachine6_fifo_in_payload_addr;
+wire          soc_litedramcore_bankmachine6_fifo_in_payload_we;
 wire          soc_litedramcore_bankmachine6_fifo_out_first;
 wire          soc_litedramcore_bankmachine6_fifo_out_last;
-wire          soc_litedramcore_bankmachine6_sink_sink_valid;
-wire          soc_litedramcore_bankmachine6_sink_sink_ready;
-wire          soc_litedramcore_bankmachine6_sink_sink_first;
-wire          soc_litedramcore_bankmachine6_sink_sink_last;
-wire          soc_litedramcore_bankmachine6_sink_sink_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine6_sink_sink_payload_addr;
-wire          soc_litedramcore_bankmachine6_source_source_valid;
-wire          soc_litedramcore_bankmachine6_source_source_ready;
-wire          soc_litedramcore_bankmachine6_source_source_first;
-wire          soc_litedramcore_bankmachine6_source_source_last;
-wire          soc_litedramcore_bankmachine6_source_source_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine6_source_source_payload_addr;
-wire          soc_litedramcore_bankmachine6_pipe_valid_sink_valid;
-wire          soc_litedramcore_bankmachine6_pipe_valid_sink_ready;
+wire   [20:0] soc_litedramcore_bankmachine6_fifo_out_payload_addr;
+wire          soc_litedramcore_bankmachine6_fifo_out_payload_we;
+reg     [4:0] soc_litedramcore_bankmachine6_level = 5'd0;
 wire          soc_litedramcore_bankmachine6_pipe_valid_sink_first;
 wire          soc_litedramcore_bankmachine6_pipe_valid_sink_last;
-wire          soc_litedramcore_bankmachine6_pipe_valid_sink_payload_we;
 wire   [20:0] soc_litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
-reg           soc_litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0;
-wire          soc_litedramcore_bankmachine6_pipe_valid_source_ready;
+wire          soc_litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+wire          soc_litedramcore_bankmachine6_pipe_valid_sink_ready;
+wire          soc_litedramcore_bankmachine6_pipe_valid_sink_valid;
 reg           soc_litedramcore_bankmachine6_pipe_valid_source_first = 1'd0;
 reg           soc_litedramcore_bankmachine6_pipe_valid_source_last = 1'd0;
-reg           soc_litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0;
 reg    [20:0] soc_litedramcore_bankmachine6_pipe_valid_source_payload_addr = 21'd0;
+reg           soc_litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0;
+wire          soc_litedramcore_bankmachine6_pipe_valid_source_ready;
+reg           soc_litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0;
+reg     [3:0] soc_litedramcore_bankmachine6_produce = 4'd0;
+wire    [3:0] soc_litedramcore_bankmachine6_rdport_adr;
+wire   [23:0] soc_litedramcore_bankmachine6_rdport_dat_r;
+reg           soc_litedramcore_bankmachine6_refresh_gnt = 1'd0;
+wire          soc_litedramcore_bankmachine6_refresh_req;
+reg           soc_litedramcore_bankmachine6_replace = 1'd0;
+wire   [20:0] soc_litedramcore_bankmachine6_req_addr;
+wire          soc_litedramcore_bankmachine6_req_lock;
+reg           soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire          soc_litedramcore_bankmachine6_req_ready;
+wire          soc_litedramcore_bankmachine6_req_valid;
+reg           soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+wire          soc_litedramcore_bankmachine6_req_we;
 reg    [13:0] soc_litedramcore_bankmachine6_row = 14'd0;
-reg           soc_litedramcore_bankmachine6_row_opened = 1'd0;
-wire          soc_litedramcore_bankmachine6_row_hit;
-reg           soc_litedramcore_bankmachine6_row_open = 1'd0;
 reg           soc_litedramcore_bankmachine6_row_close = 1'd0;
 reg           soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
-wire          soc_litedramcore_bankmachine6_twtpcon_valid;
-reg           soc_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg     [2:0] soc_litedramcore_bankmachine6_twtpcon_count = 3'd0;
-wire          soc_litedramcore_bankmachine6_trccon_valid;
-reg           soc_litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg     [2:0] soc_litedramcore_bankmachine6_trccon_count = 3'd0;
-wire          soc_litedramcore_bankmachine6_trascon_valid;
-reg           soc_litedramcore_bankmachine6_trascon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine6_row_hit;
+reg           soc_litedramcore_bankmachine6_row_open = 1'd0;
+reg           soc_litedramcore_bankmachine6_row_opened = 1'd0;
+reg           soc_litedramcore_bankmachine6_sink_first = 1'd0;
+reg           soc_litedramcore_bankmachine6_sink_last = 1'd0;
+wire   [20:0] soc_litedramcore_bankmachine6_sink_payload_addr;
+wire          soc_litedramcore_bankmachine6_sink_payload_we;
+wire          soc_litedramcore_bankmachine6_sink_ready;
+wire          soc_litedramcore_bankmachine6_sink_sink_first;
+wire          soc_litedramcore_bankmachine6_sink_sink_last;
+wire   [20:0] soc_litedramcore_bankmachine6_sink_sink_payload_addr;
+wire          soc_litedramcore_bankmachine6_sink_sink_payload_we;
+wire          soc_litedramcore_bankmachine6_sink_sink_ready;
+wire          soc_litedramcore_bankmachine6_sink_sink_valid;
+wire          soc_litedramcore_bankmachine6_sink_valid;
+wire          soc_litedramcore_bankmachine6_source_first;
+wire          soc_litedramcore_bankmachine6_source_last;
+wire   [20:0] soc_litedramcore_bankmachine6_source_payload_addr;
+wire          soc_litedramcore_bankmachine6_source_payload_we;
+wire          soc_litedramcore_bankmachine6_source_ready;
+wire          soc_litedramcore_bankmachine6_source_source_first;
+wire          soc_litedramcore_bankmachine6_source_source_last;
+wire   [20:0] soc_litedramcore_bankmachine6_source_source_payload_addr;
+wire          soc_litedramcore_bankmachine6_source_source_payload_we;
+wire          soc_litedramcore_bankmachine6_source_source_ready;
+wire          soc_litedramcore_bankmachine6_source_source_valid;
+wire          soc_litedramcore_bankmachine6_source_valid;
+wire   [23:0] soc_litedramcore_bankmachine6_syncfifo6_din;
+wire   [23:0] soc_litedramcore_bankmachine6_syncfifo6_dout;
+wire          soc_litedramcore_bankmachine6_syncfifo6_re;
+wire          soc_litedramcore_bankmachine6_syncfifo6_readable;
+wire          soc_litedramcore_bankmachine6_syncfifo6_we;
+wire          soc_litedramcore_bankmachine6_syncfifo6_writable;
 reg     [2:0] soc_litedramcore_bankmachine6_trascon_count = 3'd0;
-wire          soc_litedramcore_bankmachine7_req_valid;
-wire          soc_litedramcore_bankmachine7_req_ready;
-wire          soc_litedramcore_bankmachine7_req_we;
-wire   [20:0] soc_litedramcore_bankmachine7_req_addr;
-wire          soc_litedramcore_bankmachine7_req_lock;
-reg           soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg           soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
-wire          soc_litedramcore_bankmachine7_refresh_req;
-reg           soc_litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg           soc_litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg           soc_litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg           soc_litedramcore_bankmachine6_trascon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine6_trascon_valid;
+reg     [2:0] soc_litedramcore_bankmachine6_trccon_count = 3'd0;
+reg           soc_litedramcore_bankmachine6_trccon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine6_trccon_valid;
+reg     [2:0] soc_litedramcore_bankmachine6_twtpcon_count = 3'd0;
+reg           soc_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine6_twtpcon_valid;
+reg     [3:0] soc_litedramcore_bankmachine6_wrport_adr = 4'd0;
+wire   [23:0] soc_litedramcore_bankmachine6_wrport_dat_r;
+wire   [23:0] soc_litedramcore_bankmachine6_wrport_dat_w;
+wire          soc_litedramcore_bankmachine6_wrport_we;
+reg           soc_litedramcore_bankmachine7_auto_precharge = 1'd0;
 reg    [13:0] soc_litedramcore_bankmachine7_cmd_payload_a = 14'd0;
 wire    [2:0] soc_litedramcore_bankmachine7_cmd_payload_ba;
 reg           soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg           soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg           soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
 reg           soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
 reg           soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
 reg           soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg           soc_litedramcore_bankmachine7_auto_precharge = 1'd0;
-wire          soc_litedramcore_bankmachine7_sink_valid;
-wire          soc_litedramcore_bankmachine7_sink_ready;
-reg           soc_litedramcore_bankmachine7_sink_first = 1'd0;
-reg           soc_litedramcore_bankmachine7_sink_last = 1'd0;
-wire          soc_litedramcore_bankmachine7_sink_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine7_sink_payload_addr;
-wire          soc_litedramcore_bankmachine7_source_valid;
-wire          soc_litedramcore_bankmachine7_source_ready;
-wire          soc_litedramcore_bankmachine7_source_first;
-wire          soc_litedramcore_bankmachine7_source_last;
-wire          soc_litedramcore_bankmachine7_source_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine7_source_payload_addr;
-wire          soc_litedramcore_bankmachine7_syncfifo7_we;
-wire          soc_litedramcore_bankmachine7_syncfifo7_writable;
-wire          soc_litedramcore_bankmachine7_syncfifo7_re;
-wire          soc_litedramcore_bankmachine7_syncfifo7_readable;
-wire   [23:0] soc_litedramcore_bankmachine7_syncfifo7_din;
-wire   [23:0] soc_litedramcore_bankmachine7_syncfifo7_dout;
-reg     [4:0] soc_litedramcore_bankmachine7_level = 5'd0;
-reg           soc_litedramcore_bankmachine7_replace = 1'd0;
-reg     [3:0] soc_litedramcore_bankmachine7_produce = 4'd0;
+reg           soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg           soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg           soc_litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg           soc_litedramcore_bankmachine7_cmd_valid = 1'd0;
 reg     [3:0] soc_litedramcore_bankmachine7_consume = 4'd0;
-reg     [3:0] soc_litedramcore_bankmachine7_wrport_adr = 4'd0;
-wire   [23:0] soc_litedramcore_bankmachine7_wrport_dat_r;
-wire          soc_litedramcore_bankmachine7_wrport_we;
-wire   [23:0] soc_litedramcore_bankmachine7_wrport_dat_w;
 wire          soc_litedramcore_bankmachine7_do_read;
-wire    [3:0] soc_litedramcore_bankmachine7_rdport_adr;
-wire   [23:0] soc_litedramcore_bankmachine7_rdport_dat_r;
-wire          soc_litedramcore_bankmachine7_fifo_in_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine7_fifo_in_payload_addr;
 wire          soc_litedramcore_bankmachine7_fifo_in_first;
 wire          soc_litedramcore_bankmachine7_fifo_in_last;
-wire          soc_litedramcore_bankmachine7_fifo_out_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine7_fifo_out_payload_addr;
+wire   [20:0] soc_litedramcore_bankmachine7_fifo_in_payload_addr;
+wire          soc_litedramcore_bankmachine7_fifo_in_payload_we;
 wire          soc_litedramcore_bankmachine7_fifo_out_first;
 wire          soc_litedramcore_bankmachine7_fifo_out_last;
-wire          soc_litedramcore_bankmachine7_sink_sink_valid;
-wire          soc_litedramcore_bankmachine7_sink_sink_ready;
-wire          soc_litedramcore_bankmachine7_sink_sink_first;
-wire          soc_litedramcore_bankmachine7_sink_sink_last;
-wire          soc_litedramcore_bankmachine7_sink_sink_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine7_sink_sink_payload_addr;
-wire          soc_litedramcore_bankmachine7_source_source_valid;
-wire          soc_litedramcore_bankmachine7_source_source_ready;
-wire          soc_litedramcore_bankmachine7_source_source_first;
-wire          soc_litedramcore_bankmachine7_source_source_last;
-wire          soc_litedramcore_bankmachine7_source_source_payload_we;
-wire   [20:0] soc_litedramcore_bankmachine7_source_source_payload_addr;
-wire          soc_litedramcore_bankmachine7_pipe_valid_sink_valid;
-wire          soc_litedramcore_bankmachine7_pipe_valid_sink_ready;
+wire   [20:0] soc_litedramcore_bankmachine7_fifo_out_payload_addr;
+wire          soc_litedramcore_bankmachine7_fifo_out_payload_we;
+reg     [4:0] soc_litedramcore_bankmachine7_level = 5'd0;
 wire          soc_litedramcore_bankmachine7_pipe_valid_sink_first;
 wire          soc_litedramcore_bankmachine7_pipe_valid_sink_last;
-wire          soc_litedramcore_bankmachine7_pipe_valid_sink_payload_we;
 wire   [20:0] soc_litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
-reg           soc_litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0;
-wire          soc_litedramcore_bankmachine7_pipe_valid_source_ready;
+wire          soc_litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+wire          soc_litedramcore_bankmachine7_pipe_valid_sink_ready;
+wire          soc_litedramcore_bankmachine7_pipe_valid_sink_valid;
 reg           soc_litedramcore_bankmachine7_pipe_valid_source_first = 1'd0;
 reg           soc_litedramcore_bankmachine7_pipe_valid_source_last = 1'd0;
-reg           soc_litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0;
 reg    [20:0] soc_litedramcore_bankmachine7_pipe_valid_source_payload_addr = 21'd0;
+reg           soc_litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0;
+wire          soc_litedramcore_bankmachine7_pipe_valid_source_ready;
+reg           soc_litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0;
+reg     [3:0] soc_litedramcore_bankmachine7_produce = 4'd0;
+wire    [3:0] soc_litedramcore_bankmachine7_rdport_adr;
+wire   [23:0] soc_litedramcore_bankmachine7_rdport_dat_r;
+reg           soc_litedramcore_bankmachine7_refresh_gnt = 1'd0;
+wire          soc_litedramcore_bankmachine7_refresh_req;
+reg           soc_litedramcore_bankmachine7_replace = 1'd0;
+wire   [20:0] soc_litedramcore_bankmachine7_req_addr;
+wire          soc_litedramcore_bankmachine7_req_lock;
+reg           soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire          soc_litedramcore_bankmachine7_req_ready;
+wire          soc_litedramcore_bankmachine7_req_valid;
+reg           soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+wire          soc_litedramcore_bankmachine7_req_we;
 reg    [13:0] soc_litedramcore_bankmachine7_row = 14'd0;
-reg           soc_litedramcore_bankmachine7_row_opened = 1'd0;
-wire          soc_litedramcore_bankmachine7_row_hit;
-reg           soc_litedramcore_bankmachine7_row_open = 1'd0;
 reg           soc_litedramcore_bankmachine7_row_close = 1'd0;
 reg           soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
-wire          soc_litedramcore_bankmachine7_twtpcon_valid;
-reg           soc_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg     [2:0] soc_litedramcore_bankmachine7_twtpcon_count = 3'd0;
-wire          soc_litedramcore_bankmachine7_trccon_valid;
-reg           soc_litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg     [2:0] soc_litedramcore_bankmachine7_trccon_count = 3'd0;
-wire          soc_litedramcore_bankmachine7_trascon_valid;
-reg           soc_litedramcore_bankmachine7_trascon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine7_row_hit;
+reg           soc_litedramcore_bankmachine7_row_open = 1'd0;
+reg           soc_litedramcore_bankmachine7_row_opened = 1'd0;
+reg           soc_litedramcore_bankmachine7_sink_first = 1'd0;
+reg           soc_litedramcore_bankmachine7_sink_last = 1'd0;
+wire   [20:0] soc_litedramcore_bankmachine7_sink_payload_addr;
+wire          soc_litedramcore_bankmachine7_sink_payload_we;
+wire          soc_litedramcore_bankmachine7_sink_ready;
+wire          soc_litedramcore_bankmachine7_sink_sink_first;
+wire          soc_litedramcore_bankmachine7_sink_sink_last;
+wire   [20:0] soc_litedramcore_bankmachine7_sink_sink_payload_addr;
+wire          soc_litedramcore_bankmachine7_sink_sink_payload_we;
+wire          soc_litedramcore_bankmachine7_sink_sink_ready;
+wire          soc_litedramcore_bankmachine7_sink_sink_valid;
+wire          soc_litedramcore_bankmachine7_sink_valid;
+wire          soc_litedramcore_bankmachine7_source_first;
+wire          soc_litedramcore_bankmachine7_source_last;
+wire   [20:0] soc_litedramcore_bankmachine7_source_payload_addr;
+wire          soc_litedramcore_bankmachine7_source_payload_we;
+wire          soc_litedramcore_bankmachine7_source_ready;
+wire          soc_litedramcore_bankmachine7_source_source_first;
+wire          soc_litedramcore_bankmachine7_source_source_last;
+wire   [20:0] soc_litedramcore_bankmachine7_source_source_payload_addr;
+wire          soc_litedramcore_bankmachine7_source_source_payload_we;
+wire          soc_litedramcore_bankmachine7_source_source_ready;
+wire          soc_litedramcore_bankmachine7_source_source_valid;
+wire          soc_litedramcore_bankmachine7_source_valid;
+wire   [23:0] soc_litedramcore_bankmachine7_syncfifo7_din;
+wire   [23:0] soc_litedramcore_bankmachine7_syncfifo7_dout;
+wire          soc_litedramcore_bankmachine7_syncfifo7_re;
+wire          soc_litedramcore_bankmachine7_syncfifo7_readable;
+wire          soc_litedramcore_bankmachine7_syncfifo7_we;
+wire          soc_litedramcore_bankmachine7_syncfifo7_writable;
 reg     [2:0] soc_litedramcore_bankmachine7_trascon_count = 3'd0;
-wire          soc_litedramcore_ras_allowed;
+reg           soc_litedramcore_bankmachine7_trascon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine7_trascon_valid;
+reg     [2:0] soc_litedramcore_bankmachine7_trccon_count = 3'd0;
+reg           soc_litedramcore_bankmachine7_trccon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine7_trccon_valid;
+reg     [2:0] soc_litedramcore_bankmachine7_twtpcon_count = 3'd0;
+reg           soc_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+wire          soc_litedramcore_bankmachine7_twtpcon_valid;
+reg     [3:0] soc_litedramcore_bankmachine7_wrport_adr = 4'd0;
+wire   [23:0] soc_litedramcore_bankmachine7_wrport_dat_r;
+wire   [23:0] soc_litedramcore_bankmachine7_wrport_dat_w;
+wire          soc_litedramcore_bankmachine7_wrport_we;
 wire          soc_litedramcore_cas_allowed;
-reg           soc_litedramcore_choose_cmd_want_reads = 1'd0;
-reg           soc_litedramcore_choose_cmd_want_writes = 1'd0;
-reg           soc_litedramcore_choose_cmd_want_cmds = 1'd0;
-reg           soc_litedramcore_choose_cmd_want_activates = 1'd0;
-wire          soc_litedramcore_choose_cmd_cmd_valid;
-reg           soc_litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire          soc_litedramcore_choose_cmd_ce;
 wire   [13:0] soc_litedramcore_choose_cmd_cmd_payload_a;
 wire    [2:0] soc_litedramcore_choose_cmd_cmd_payload_ba;
 reg           soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg           soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg           soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
 wire          soc_litedramcore_choose_cmd_cmd_payload_is_cmd;
 wire          soc_litedramcore_choose_cmd_cmd_payload_is_read;
 wire          soc_litedramcore_choose_cmd_cmd_payload_is_write;
-reg     [7:0] soc_litedramcore_choose_cmd_valids = 8'd0;
-wire    [7:0] soc_litedramcore_choose_cmd_request;
+reg           soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg           soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+reg           soc_litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire          soc_litedramcore_choose_cmd_cmd_valid;
 reg     [2:0] soc_litedramcore_choose_cmd_grant = 3'd0;
-wire          soc_litedramcore_choose_cmd_ce;
-reg           soc_litedramcore_choose_req_want_reads = 1'd0;
-reg           soc_litedramcore_choose_req_want_writes = 1'd0;
-reg           soc_litedramcore_choose_req_want_cmds = 1'd0;
-reg           soc_litedramcore_choose_req_want_activates = 1'd0;
-wire          soc_litedramcore_choose_req_cmd_valid;
-reg           soc_litedramcore_choose_req_cmd_ready = 1'd0;
+wire    [7:0] soc_litedramcore_choose_cmd_request;
+reg     [7:0] soc_litedramcore_choose_cmd_valids = 8'd0;
+reg           soc_litedramcore_choose_cmd_want_activates = 1'd0;
+reg           soc_litedramcore_choose_cmd_want_cmds = 1'd0;
+reg           soc_litedramcore_choose_cmd_want_reads = 1'd0;
+reg           soc_litedramcore_choose_cmd_want_writes = 1'd0;
+wire          soc_litedramcore_choose_req_ce;
 wire   [13:0] soc_litedramcore_choose_req_cmd_payload_a;
 wire    [2:0] soc_litedramcore_choose_req_cmd_payload_ba;
 reg           soc_litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg           soc_litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg           soc_litedramcore_choose_req_cmd_payload_we = 1'd0;
 wire          soc_litedramcore_choose_req_cmd_payload_is_cmd;
 wire          soc_litedramcore_choose_req_cmd_payload_is_read;
 wire          soc_litedramcore_choose_req_cmd_payload_is_write;
-reg     [7:0] soc_litedramcore_choose_req_valids = 8'd0;
-wire    [7:0] soc_litedramcore_choose_req_request;
+reg           soc_litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg           soc_litedramcore_choose_req_cmd_payload_we = 1'd0;
+reg           soc_litedramcore_choose_req_cmd_ready = 1'd0;
+wire          soc_litedramcore_choose_req_cmd_valid;
 reg     [2:0] soc_litedramcore_choose_req_grant = 3'd0;
-wire          soc_litedramcore_choose_req_ce;
+wire    [7:0] soc_litedramcore_choose_req_request;
+reg     [7:0] soc_litedramcore_choose_req_valids = 8'd0;
+reg           soc_litedramcore_choose_req_want_activates = 1'd0;
+reg           soc_litedramcore_choose_req_want_cmds = 1'd0;
+reg           soc_litedramcore_choose_req_want_reads = 1'd0;
+reg           soc_litedramcore_choose_req_want_writes = 1'd0;
+wire          soc_litedramcore_cke;
+reg           soc_litedramcore_cmd_last = 1'd0;
+reg    [13:0] soc_litedramcore_cmd_payload_a = 14'd0;
+reg     [2:0] soc_litedramcore_cmd_payload_ba = 3'd0;
+reg           soc_litedramcore_cmd_payload_cas = 1'd0;
+reg           soc_litedramcore_cmd_payload_is_read = 1'd0;
+reg           soc_litedramcore_cmd_payload_is_write = 1'd0;
+reg           soc_litedramcore_cmd_payload_ras = 1'd0;
+reg           soc_litedramcore_cmd_payload_we = 1'd0;
+reg           soc_litedramcore_cmd_ready = 1'd0;
+reg           soc_litedramcore_cmd_valid = 1'd0;
+reg           soc_litedramcore_csr_dfi_p0_act_n = 1'd1;
+wire   [13:0] soc_litedramcore_csr_dfi_p0_address;
+wire    [2:0] soc_litedramcore_csr_dfi_p0_bank;
+reg           soc_litedramcore_csr_dfi_p0_cas_n = 1'd1;
+reg           soc_litedramcore_csr_dfi_p0_cke = 1'd0;
+reg           soc_litedramcore_csr_dfi_p0_cs_n = 1'd1;
+reg           soc_litedramcore_csr_dfi_p0_odt = 1'd0;
+reg           soc_litedramcore_csr_dfi_p0_ras_n = 1'd1;
+reg    [31:0] soc_litedramcore_csr_dfi_p0_rddata = 32'd0;
+wire          soc_litedramcore_csr_dfi_p0_rddata_en;
+reg           soc_litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
+wire          soc_litedramcore_csr_dfi_p0_reset_n;
+reg           soc_litedramcore_csr_dfi_p0_we_n = 1'd1;
+wire   [31:0] soc_litedramcore_csr_dfi_p0_wrdata;
+wire          soc_litedramcore_csr_dfi_p0_wrdata_en;
+wire    [3:0] soc_litedramcore_csr_dfi_p0_wrdata_mask;
+reg           soc_litedramcore_csr_dfi_p1_act_n = 1'd1;
+wire   [13:0] soc_litedramcore_csr_dfi_p1_address;
+wire    [2:0] soc_litedramcore_csr_dfi_p1_bank;
+reg           soc_litedramcore_csr_dfi_p1_cas_n = 1'd1;
+reg           soc_litedramcore_csr_dfi_p1_cke = 1'd0;
+reg           soc_litedramcore_csr_dfi_p1_cs_n = 1'd1;
+reg           soc_litedramcore_csr_dfi_p1_odt = 1'd0;
+reg           soc_litedramcore_csr_dfi_p1_ras_n = 1'd1;
+reg    [31:0] soc_litedramcore_csr_dfi_p1_rddata = 32'd0;
+wire          soc_litedramcore_csr_dfi_p1_rddata_en;
+reg           soc_litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
+wire          soc_litedramcore_csr_dfi_p1_reset_n;
+reg           soc_litedramcore_csr_dfi_p1_we_n = 1'd1;
+wire   [31:0] soc_litedramcore_csr_dfi_p1_wrdata;
+wire          soc_litedramcore_csr_dfi_p1_wrdata_en;
+wire    [3:0] soc_litedramcore_csr_dfi_p1_wrdata_mask;
+reg           soc_litedramcore_csr_dfi_p2_act_n = 1'd1;
+wire   [13:0] soc_litedramcore_csr_dfi_p2_address;
+wire    [2:0] soc_litedramcore_csr_dfi_p2_bank;
+reg           soc_litedramcore_csr_dfi_p2_cas_n = 1'd1;
+reg           soc_litedramcore_csr_dfi_p2_cke = 1'd0;
+reg           soc_litedramcore_csr_dfi_p2_cs_n = 1'd1;
+reg           soc_litedramcore_csr_dfi_p2_odt = 1'd0;
+reg           soc_litedramcore_csr_dfi_p2_ras_n = 1'd1;
+reg    [31:0] soc_litedramcore_csr_dfi_p2_rddata = 32'd0;
+wire          soc_litedramcore_csr_dfi_p2_rddata_en;
+reg           soc_litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
+wire          soc_litedramcore_csr_dfi_p2_reset_n;
+reg           soc_litedramcore_csr_dfi_p2_we_n = 1'd1;
+wire   [31:0] soc_litedramcore_csr_dfi_p2_wrdata;
+wire          soc_litedramcore_csr_dfi_p2_wrdata_en;
+wire    [3:0] soc_litedramcore_csr_dfi_p2_wrdata_mask;
+reg           soc_litedramcore_csr_dfi_p3_act_n = 1'd1;
+wire   [13:0] soc_litedramcore_csr_dfi_p3_address;
+wire    [2:0] soc_litedramcore_csr_dfi_p3_bank;
+reg           soc_litedramcore_csr_dfi_p3_cas_n = 1'd1;
+reg           soc_litedramcore_csr_dfi_p3_cke = 1'd0;
+reg           soc_litedramcore_csr_dfi_p3_cs_n = 1'd1;
+reg           soc_litedramcore_csr_dfi_p3_odt = 1'd0;
+reg           soc_litedramcore_csr_dfi_p3_ras_n = 1'd1;
+reg    [31:0] soc_litedramcore_csr_dfi_p3_rddata = 32'd0;
+wire          soc_litedramcore_csr_dfi_p3_rddata_en;
+reg           soc_litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
+wire          soc_litedramcore_csr_dfi_p3_reset_n;
+reg           soc_litedramcore_csr_dfi_p3_we_n = 1'd1;
+wire   [31:0] soc_litedramcore_csr_dfi_p3_wrdata;
+wire          soc_litedramcore_csr_dfi_p3_wrdata_en;
+wire    [3:0] soc_litedramcore_csr_dfi_p3_wrdata_mask;
+reg           soc_litedramcore_dfi_p0_act_n = 1'd1;
+reg    [13:0] soc_litedramcore_dfi_p0_address = 14'd0;
+reg     [2:0] soc_litedramcore_dfi_p0_bank = 3'd0;
+reg           soc_litedramcore_dfi_p0_cas_n = 1'd1;
+wire          soc_litedramcore_dfi_p0_cke;
+reg           soc_litedramcore_dfi_p0_cs_n = 1'd1;
+wire          soc_litedramcore_dfi_p0_odt;
+reg           soc_litedramcore_dfi_p0_ras_n = 1'd1;
+wire   [31:0] soc_litedramcore_dfi_p0_rddata;
+reg           soc_litedramcore_dfi_p0_rddata_en = 1'd0;
+wire          soc_litedramcore_dfi_p0_rddata_valid;
+wire          soc_litedramcore_dfi_p0_reset_n;
+reg           soc_litedramcore_dfi_p0_we_n = 1'd1;
+wire   [31:0] soc_litedramcore_dfi_p0_wrdata;
+reg           soc_litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire    [3:0] soc_litedramcore_dfi_p0_wrdata_mask;
+reg           soc_litedramcore_dfi_p1_act_n = 1'd1;
+reg    [13:0] soc_litedramcore_dfi_p1_address = 14'd0;
+reg     [2:0] soc_litedramcore_dfi_p1_bank = 3'd0;
+reg           soc_litedramcore_dfi_p1_cas_n = 1'd1;
+wire          soc_litedramcore_dfi_p1_cke;
+reg           soc_litedramcore_dfi_p1_cs_n = 1'd1;
+wire          soc_litedramcore_dfi_p1_odt;
+reg           soc_litedramcore_dfi_p1_ras_n = 1'd1;
+wire   [31:0] soc_litedramcore_dfi_p1_rddata;
+reg           soc_litedramcore_dfi_p1_rddata_en = 1'd0;
+wire          soc_litedramcore_dfi_p1_rddata_valid;
+wire          soc_litedramcore_dfi_p1_reset_n;
+reg           soc_litedramcore_dfi_p1_we_n = 1'd1;
+wire   [31:0] soc_litedramcore_dfi_p1_wrdata;
+reg           soc_litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire    [3:0] soc_litedramcore_dfi_p1_wrdata_mask;
+reg           soc_litedramcore_dfi_p2_act_n = 1'd1;
+reg    [13:0] soc_litedramcore_dfi_p2_address = 14'd0;
+reg     [2:0] soc_litedramcore_dfi_p2_bank = 3'd0;
+reg           soc_litedramcore_dfi_p2_cas_n = 1'd1;
+wire          soc_litedramcore_dfi_p2_cke;
+reg           soc_litedramcore_dfi_p2_cs_n = 1'd1;
+wire          soc_litedramcore_dfi_p2_odt;
+reg           soc_litedramcore_dfi_p2_ras_n = 1'd1;
+wire   [31:0] soc_litedramcore_dfi_p2_rddata;
+reg           soc_litedramcore_dfi_p2_rddata_en = 1'd0;
+wire          soc_litedramcore_dfi_p2_rddata_valid;
+wire          soc_litedramcore_dfi_p2_reset_n;
+reg           soc_litedramcore_dfi_p2_we_n = 1'd1;
+wire   [31:0] soc_litedramcore_dfi_p2_wrdata;
+reg           soc_litedramcore_dfi_p2_wrdata_en = 1'd0;
+wire    [3:0] soc_litedramcore_dfi_p2_wrdata_mask;
+reg           soc_litedramcore_dfi_p3_act_n = 1'd1;
+reg    [13:0] soc_litedramcore_dfi_p3_address = 14'd0;
+reg     [2:0] soc_litedramcore_dfi_p3_bank = 3'd0;
+reg           soc_litedramcore_dfi_p3_cas_n = 1'd1;
+wire          soc_litedramcore_dfi_p3_cke;
+reg           soc_litedramcore_dfi_p3_cs_n = 1'd1;
+wire          soc_litedramcore_dfi_p3_odt;
+reg           soc_litedramcore_dfi_p3_ras_n = 1'd1;
+wire   [31:0] soc_litedramcore_dfi_p3_rddata;
+reg           soc_litedramcore_dfi_p3_rddata_en = 1'd0;
+wire          soc_litedramcore_dfi_p3_rddata_valid;
+wire          soc_litedramcore_dfi_p3_reset_n;
+reg           soc_litedramcore_dfi_p3_we_n = 1'd1;
+wire   [31:0] soc_litedramcore_dfi_p3_wrdata;
+reg           soc_litedramcore_dfi_p3_wrdata_en = 1'd0;
+wire    [3:0] soc_litedramcore_dfi_p3_wrdata_mask;
+reg           soc_litedramcore_en0 = 1'd0;
+reg           soc_litedramcore_en1 = 1'd0;
+reg           soc_litedramcore_ext_dfi_p0_act_n = 1'd1;
+reg    [13:0] soc_litedramcore_ext_dfi_p0_address = 14'd0;
+reg     [2:0] soc_litedramcore_ext_dfi_p0_bank = 3'd0;
+reg           soc_litedramcore_ext_dfi_p0_cas_n = 1'd1;
+reg           soc_litedramcore_ext_dfi_p0_cke = 1'd0;
+reg           soc_litedramcore_ext_dfi_p0_cs_n = 1'd1;
+reg           soc_litedramcore_ext_dfi_p0_odt = 1'd0;
+reg           soc_litedramcore_ext_dfi_p0_ras_n = 1'd1;
+reg    [31:0] soc_litedramcore_ext_dfi_p0_rddata = 32'd0;
+reg           soc_litedramcore_ext_dfi_p0_rddata_en = 1'd0;
+reg           soc_litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
+reg           soc_litedramcore_ext_dfi_p0_reset_n = 1'd0;
+reg           soc_litedramcore_ext_dfi_p0_we_n = 1'd1;
+reg    [31:0] soc_litedramcore_ext_dfi_p0_wrdata = 32'd0;
+reg           soc_litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
+reg     [3:0] soc_litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
+reg           soc_litedramcore_ext_dfi_p1_act_n = 1'd1;
+reg    [13:0] soc_litedramcore_ext_dfi_p1_address = 14'd0;
+reg     [2:0] soc_litedramcore_ext_dfi_p1_bank = 3'd0;
+reg           soc_litedramcore_ext_dfi_p1_cas_n = 1'd1;
+reg           soc_litedramcore_ext_dfi_p1_cke = 1'd0;
+reg           soc_litedramcore_ext_dfi_p1_cs_n = 1'd1;
+reg           soc_litedramcore_ext_dfi_p1_odt = 1'd0;
+reg           soc_litedramcore_ext_dfi_p1_ras_n = 1'd1;
+reg    [31:0] soc_litedramcore_ext_dfi_p1_rddata = 32'd0;
+reg           soc_litedramcore_ext_dfi_p1_rddata_en = 1'd0;
+reg           soc_litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
+reg           soc_litedramcore_ext_dfi_p1_reset_n = 1'd0;
+reg           soc_litedramcore_ext_dfi_p1_we_n = 1'd1;
+reg    [31:0] soc_litedramcore_ext_dfi_p1_wrdata = 32'd0;
+reg           soc_litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
+reg     [3:0] soc_litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
+reg           soc_litedramcore_ext_dfi_p2_act_n = 1'd1;
+reg    [13:0] soc_litedramcore_ext_dfi_p2_address = 14'd0;
+reg     [2:0] soc_litedramcore_ext_dfi_p2_bank = 3'd0;
+reg           soc_litedramcore_ext_dfi_p2_cas_n = 1'd1;
+reg           soc_litedramcore_ext_dfi_p2_cke = 1'd0;
+reg           soc_litedramcore_ext_dfi_p2_cs_n = 1'd1;
+reg           soc_litedramcore_ext_dfi_p2_odt = 1'd0;
+reg           soc_litedramcore_ext_dfi_p2_ras_n = 1'd1;
+reg    [31:0] soc_litedramcore_ext_dfi_p2_rddata = 32'd0;
+reg           soc_litedramcore_ext_dfi_p2_rddata_en = 1'd0;
+reg           soc_litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
+reg           soc_litedramcore_ext_dfi_p2_reset_n = 1'd0;
+reg           soc_litedramcore_ext_dfi_p2_we_n = 1'd1;
+reg    [31:0] soc_litedramcore_ext_dfi_p2_wrdata = 32'd0;
+reg           soc_litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
+reg     [3:0] soc_litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
+reg           soc_litedramcore_ext_dfi_p3_act_n = 1'd1;
+reg    [13:0] soc_litedramcore_ext_dfi_p3_address = 14'd0;
+reg     [2:0] soc_litedramcore_ext_dfi_p3_bank = 3'd0;
+reg           soc_litedramcore_ext_dfi_p3_cas_n = 1'd1;
+reg           soc_litedramcore_ext_dfi_p3_cke = 1'd0;
+reg           soc_litedramcore_ext_dfi_p3_cs_n = 1'd1;
+reg           soc_litedramcore_ext_dfi_p3_odt = 1'd0;
+reg           soc_litedramcore_ext_dfi_p3_ras_n = 1'd1;
+reg    [31:0] soc_litedramcore_ext_dfi_p3_rddata = 32'd0;
+reg           soc_litedramcore_ext_dfi_p3_rddata_en = 1'd0;
+reg           soc_litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
+reg           soc_litedramcore_ext_dfi_p3_reset_n = 1'd0;
+reg           soc_litedramcore_ext_dfi_p3_we_n = 1'd1;
+reg    [31:0] soc_litedramcore_ext_dfi_p3_wrdata = 32'd0;
+reg           soc_litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
+reg     [3:0] soc_litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
+reg           soc_litedramcore_ext_dfi_sel = 1'd0;
+wire          soc_litedramcore_go_to_refresh;
+wire   [20:0] soc_litedramcore_interface_bank0_addr;
+wire          soc_litedramcore_interface_bank0_lock;
+wire          soc_litedramcore_interface_bank0_rdata_valid;
+wire          soc_litedramcore_interface_bank0_ready;
+wire          soc_litedramcore_interface_bank0_valid;
+wire          soc_litedramcore_interface_bank0_wdata_ready;
+wire          soc_litedramcore_interface_bank0_we;
+wire   [20:0] soc_litedramcore_interface_bank1_addr;
+wire          soc_litedramcore_interface_bank1_lock;
+wire          soc_litedramcore_interface_bank1_rdata_valid;
+wire          soc_litedramcore_interface_bank1_ready;
+wire          soc_litedramcore_interface_bank1_valid;
+wire          soc_litedramcore_interface_bank1_wdata_ready;
+wire          soc_litedramcore_interface_bank1_we;
+wire   [20:0] soc_litedramcore_interface_bank2_addr;
+wire          soc_litedramcore_interface_bank2_lock;
+wire          soc_litedramcore_interface_bank2_rdata_valid;
+wire          soc_litedramcore_interface_bank2_ready;
+wire          soc_litedramcore_interface_bank2_valid;
+wire          soc_litedramcore_interface_bank2_wdata_ready;
+wire          soc_litedramcore_interface_bank2_we;
+wire   [20:0] soc_litedramcore_interface_bank3_addr;
+wire          soc_litedramcore_interface_bank3_lock;
+wire          soc_litedramcore_interface_bank3_rdata_valid;
+wire          soc_litedramcore_interface_bank3_ready;
+wire          soc_litedramcore_interface_bank3_valid;
+wire          soc_litedramcore_interface_bank3_wdata_ready;
+wire          soc_litedramcore_interface_bank3_we;
+wire   [20:0] soc_litedramcore_interface_bank4_addr;
+wire          soc_litedramcore_interface_bank4_lock;
+wire          soc_litedramcore_interface_bank4_rdata_valid;
+wire          soc_litedramcore_interface_bank4_ready;
+wire          soc_litedramcore_interface_bank4_valid;
+wire          soc_litedramcore_interface_bank4_wdata_ready;
+wire          soc_litedramcore_interface_bank4_we;
+wire   [20:0] soc_litedramcore_interface_bank5_addr;
+wire          soc_litedramcore_interface_bank5_lock;
+wire          soc_litedramcore_interface_bank5_rdata_valid;
+wire          soc_litedramcore_interface_bank5_ready;
+wire          soc_litedramcore_interface_bank5_valid;
+wire          soc_litedramcore_interface_bank5_wdata_ready;
+wire          soc_litedramcore_interface_bank5_we;
+wire   [20:0] soc_litedramcore_interface_bank6_addr;
+wire          soc_litedramcore_interface_bank6_lock;
+wire          soc_litedramcore_interface_bank6_rdata_valid;
+wire          soc_litedramcore_interface_bank6_ready;
+wire          soc_litedramcore_interface_bank6_valid;
+wire          soc_litedramcore_interface_bank6_wdata_ready;
+wire          soc_litedramcore_interface_bank6_we;
+wire   [20:0] soc_litedramcore_interface_bank7_addr;
+wire          soc_litedramcore_interface_bank7_lock;
+wire          soc_litedramcore_interface_bank7_rdata_valid;
+wire          soc_litedramcore_interface_bank7_ready;
+wire          soc_litedramcore_interface_bank7_valid;
+wire          soc_litedramcore_interface_bank7_wdata_ready;
+wire          soc_litedramcore_interface_bank7_we;
+wire  [127:0] soc_litedramcore_interface_rdata;
+reg   [127:0] soc_litedramcore_interface_wdata = 128'd0;
+reg    [15:0] soc_litedramcore_interface_wdata_we = 16'd0;
+reg           soc_litedramcore_master_p0_act_n = 1'd1;
+reg    [13:0] soc_litedramcore_master_p0_address = 14'd0;
+reg     [2:0] soc_litedramcore_master_p0_bank = 3'd0;
+reg           soc_litedramcore_master_p0_cas_n = 1'd1;
+reg           soc_litedramcore_master_p0_cke = 1'd0;
+reg           soc_litedramcore_master_p0_cs_n = 1'd1;
+reg           soc_litedramcore_master_p0_odt = 1'd0;
+reg           soc_litedramcore_master_p0_ras_n = 1'd1;
+wire   [31:0] soc_litedramcore_master_p0_rddata;
+reg           soc_litedramcore_master_p0_rddata_en = 1'd0;
+wire          soc_litedramcore_master_p0_rddata_valid;
+reg           soc_litedramcore_master_p0_reset_n = 1'd0;
+reg           soc_litedramcore_master_p0_we_n = 1'd1;
+reg    [31:0] soc_litedramcore_master_p0_wrdata = 32'd0;
+reg           soc_litedramcore_master_p0_wrdata_en = 1'd0;
+reg     [3:0] soc_litedramcore_master_p0_wrdata_mask = 4'd0;
+reg           soc_litedramcore_master_p1_act_n = 1'd1;
+reg    [13:0] soc_litedramcore_master_p1_address = 14'd0;
+reg     [2:0] soc_litedramcore_master_p1_bank = 3'd0;
+reg           soc_litedramcore_master_p1_cas_n = 1'd1;
+reg           soc_litedramcore_master_p1_cke = 1'd0;
+reg           soc_litedramcore_master_p1_cs_n = 1'd1;
+reg           soc_litedramcore_master_p1_odt = 1'd0;
+reg           soc_litedramcore_master_p1_ras_n = 1'd1;
+wire   [31:0] soc_litedramcore_master_p1_rddata;
+reg           soc_litedramcore_master_p1_rddata_en = 1'd0;
+wire          soc_litedramcore_master_p1_rddata_valid;
+reg           soc_litedramcore_master_p1_reset_n = 1'd0;
+reg           soc_litedramcore_master_p1_we_n = 1'd1;
+reg    [31:0] soc_litedramcore_master_p1_wrdata = 32'd0;
+reg           soc_litedramcore_master_p1_wrdata_en = 1'd0;
+reg     [3:0] soc_litedramcore_master_p1_wrdata_mask = 4'd0;
+reg           soc_litedramcore_master_p2_act_n = 1'd1;
+reg    [13:0] soc_litedramcore_master_p2_address = 14'd0;
+reg     [2:0] soc_litedramcore_master_p2_bank = 3'd0;
+reg           soc_litedramcore_master_p2_cas_n = 1'd1;
+reg           soc_litedramcore_master_p2_cke = 1'd0;
+reg           soc_litedramcore_master_p2_cs_n = 1'd1;
+reg           soc_litedramcore_master_p2_odt = 1'd0;
+reg           soc_litedramcore_master_p2_ras_n = 1'd1;
+wire   [31:0] soc_litedramcore_master_p2_rddata;
+reg           soc_litedramcore_master_p2_rddata_en = 1'd0;
+wire          soc_litedramcore_master_p2_rddata_valid;
+reg           soc_litedramcore_master_p2_reset_n = 1'd0;
+reg           soc_litedramcore_master_p2_we_n = 1'd1;
+reg    [31:0] soc_litedramcore_master_p2_wrdata = 32'd0;
+reg           soc_litedramcore_master_p2_wrdata_en = 1'd0;
+reg     [3:0] soc_litedramcore_master_p2_wrdata_mask = 4'd0;
+reg           soc_litedramcore_master_p3_act_n = 1'd1;
+reg    [13:0] soc_litedramcore_master_p3_address = 14'd0;
+reg     [2:0] soc_litedramcore_master_p3_bank = 3'd0;
+reg           soc_litedramcore_master_p3_cas_n = 1'd1;
+reg           soc_litedramcore_master_p3_cke = 1'd0;
+reg           soc_litedramcore_master_p3_cs_n = 1'd1;
+reg           soc_litedramcore_master_p3_odt = 1'd0;
+reg           soc_litedramcore_master_p3_ras_n = 1'd1;
+wire   [31:0] soc_litedramcore_master_p3_rddata;
+reg           soc_litedramcore_master_p3_rddata_en = 1'd0;
+wire          soc_litedramcore_master_p3_rddata_valid;
+reg           soc_litedramcore_master_p3_reset_n = 1'd0;
+reg           soc_litedramcore_master_p3_we_n = 1'd1;
+reg    [31:0] soc_litedramcore_master_p3_wrdata = 32'd0;
+reg           soc_litedramcore_master_p3_wrdata_en = 1'd0;
+reg     [3:0] soc_litedramcore_master_p3_wrdata_mask = 4'd0;
+wire          soc_litedramcore_max_time0;
+wire          soc_litedramcore_max_time1;
 reg    [13:0] soc_litedramcore_nop_a = 14'd0;
 reg     [2:0] soc_litedramcore_nop_ba = 3'd0;
-reg     [1:0] soc_litedramcore_steerer_sel0 = 2'd0;
-reg     [1:0] soc_litedramcore_steerer_sel1 = 2'd0;
-reg     [1:0] soc_litedramcore_steerer_sel2 = 2'd0;
-reg     [1:0] soc_litedramcore_steerer_sel3 = 2'd0;
-reg           soc_litedramcore_steerer0 = 1'd1;
-reg           soc_litedramcore_steerer1 = 1'd1;
-reg           soc_litedramcore_steerer2 = 1'd1;
-reg           soc_litedramcore_steerer3 = 1'd1;
+wire          soc_litedramcore_odt;
+reg           soc_litedramcore_phaseinjector0_address_re = 1'd0;
+reg    [13:0] soc_litedramcore_phaseinjector0_address_storage = 14'd0;
+reg           soc_litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg     [2:0] soc_litedramcore_phaseinjector0_baddress_storage = 3'd0;
+wire          soc_litedramcore_phaseinjector0_command_issue_r;
+reg           soc_litedramcore_phaseinjector0_command_issue_re = 1'd0;
+reg           soc_litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg           soc_litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg           soc_litedramcore_phaseinjector0_command_re = 1'd0;
+reg     [7:0] soc_litedramcore_phaseinjector0_command_storage = 8'd0;
+wire          soc_litedramcore_phaseinjector0_csrfield_cas;
+wire          soc_litedramcore_phaseinjector0_csrfield_cs;
+wire          soc_litedramcore_phaseinjector0_csrfield_cs_bottom;
+wire          soc_litedramcore_phaseinjector0_csrfield_cs_top;
+wire          soc_litedramcore_phaseinjector0_csrfield_ras;
+wire          soc_litedramcore_phaseinjector0_csrfield_rden;
+wire          soc_litedramcore_phaseinjector0_csrfield_we;
+wire          soc_litedramcore_phaseinjector0_csrfield_wren;
+reg           soc_litedramcore_phaseinjector0_rddata_re = 1'd0;
+reg    [31:0] soc_litedramcore_phaseinjector0_rddata_status = 32'd0;
+wire          soc_litedramcore_phaseinjector0_rddata_we;
+reg           soc_litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg    [31:0] soc_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
+reg           soc_litedramcore_phaseinjector1_address_re = 1'd0;
+reg    [13:0] soc_litedramcore_phaseinjector1_address_storage = 14'd0;
+reg           soc_litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg     [2:0] soc_litedramcore_phaseinjector1_baddress_storage = 3'd0;
+wire          soc_litedramcore_phaseinjector1_command_issue_r;
+reg           soc_litedramcore_phaseinjector1_command_issue_re = 1'd0;
+reg           soc_litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg           soc_litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg           soc_litedramcore_phaseinjector1_command_re = 1'd0;
+reg     [7:0] soc_litedramcore_phaseinjector1_command_storage = 8'd0;
+wire          soc_litedramcore_phaseinjector1_csrfield_cas;
+wire          soc_litedramcore_phaseinjector1_csrfield_cs;
+wire          soc_litedramcore_phaseinjector1_csrfield_cs_bottom;
+wire          soc_litedramcore_phaseinjector1_csrfield_cs_top;
+wire          soc_litedramcore_phaseinjector1_csrfield_ras;
+wire          soc_litedramcore_phaseinjector1_csrfield_rden;
+wire          soc_litedramcore_phaseinjector1_csrfield_we;
+wire          soc_litedramcore_phaseinjector1_csrfield_wren;
+reg           soc_litedramcore_phaseinjector1_rddata_re = 1'd0;
+reg    [31:0] soc_litedramcore_phaseinjector1_rddata_status = 32'd0;
+wire          soc_litedramcore_phaseinjector1_rddata_we;
+reg           soc_litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg    [31:0] soc_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
+reg           soc_litedramcore_phaseinjector2_address_re = 1'd0;
+reg    [13:0] soc_litedramcore_phaseinjector2_address_storage = 14'd0;
+reg           soc_litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg     [2:0] soc_litedramcore_phaseinjector2_baddress_storage = 3'd0;
+wire          soc_litedramcore_phaseinjector2_command_issue_r;
+reg           soc_litedramcore_phaseinjector2_command_issue_re = 1'd0;
+reg           soc_litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg           soc_litedramcore_phaseinjector2_command_issue_we = 1'd0;
+reg           soc_litedramcore_phaseinjector2_command_re = 1'd0;
+reg     [7:0] soc_litedramcore_phaseinjector2_command_storage = 8'd0;
+wire          soc_litedramcore_phaseinjector2_csrfield_cas;
+wire          soc_litedramcore_phaseinjector2_csrfield_cs;
+wire          soc_litedramcore_phaseinjector2_csrfield_cs_bottom;
+wire          soc_litedramcore_phaseinjector2_csrfield_cs_top;
+wire          soc_litedramcore_phaseinjector2_csrfield_ras;
+wire          soc_litedramcore_phaseinjector2_csrfield_rden;
+wire          soc_litedramcore_phaseinjector2_csrfield_we;
+wire          soc_litedramcore_phaseinjector2_csrfield_wren;
+reg           soc_litedramcore_phaseinjector2_rddata_re = 1'd0;
+reg    [31:0] soc_litedramcore_phaseinjector2_rddata_status = 32'd0;
+wire          soc_litedramcore_phaseinjector2_rddata_we;
+reg           soc_litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg    [31:0] soc_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
+reg           soc_litedramcore_phaseinjector3_address_re = 1'd0;
+reg    [13:0] soc_litedramcore_phaseinjector3_address_storage = 14'd0;
+reg           soc_litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg     [2:0] soc_litedramcore_phaseinjector3_baddress_storage = 3'd0;
+wire          soc_litedramcore_phaseinjector3_command_issue_r;
+reg           soc_litedramcore_phaseinjector3_command_issue_re = 1'd0;
+reg           soc_litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg           soc_litedramcore_phaseinjector3_command_issue_we = 1'd0;
+reg           soc_litedramcore_phaseinjector3_command_re = 1'd0;
+reg     [7:0] soc_litedramcore_phaseinjector3_command_storage = 8'd0;
+wire          soc_litedramcore_phaseinjector3_csrfield_cas;
+wire          soc_litedramcore_phaseinjector3_csrfield_cs;
+wire          soc_litedramcore_phaseinjector3_csrfield_cs_bottom;
+wire          soc_litedramcore_phaseinjector3_csrfield_cs_top;
+wire          soc_litedramcore_phaseinjector3_csrfield_ras;
+wire          soc_litedramcore_phaseinjector3_csrfield_rden;
+wire          soc_litedramcore_phaseinjector3_csrfield_we;
+wire          soc_litedramcore_phaseinjector3_csrfield_wren;
+reg           soc_litedramcore_phaseinjector3_rddata_re = 1'd0;
+reg    [31:0] soc_litedramcore_phaseinjector3_rddata_status = 32'd0;
+wire          soc_litedramcore_phaseinjector3_rddata_we;
+reg           soc_litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg    [31:0] soc_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
+reg           soc_litedramcore_postponer_count = 1'd0;
+wire          soc_litedramcore_postponer_req_i;
+reg           soc_litedramcore_postponer_req_o = 1'd0;
+wire          soc_litedramcore_ras_allowed;
+reg           soc_litedramcore_re = 1'd0;
+wire          soc_litedramcore_read_available;
+wire          soc_litedramcore_reset_n;
+wire          soc_litedramcore_sel;
+reg           soc_litedramcore_sequencer_count = 1'd0;
+wire          soc_litedramcore_sequencer_done0;
+reg           soc_litedramcore_sequencer_done1 = 1'd0;
+reg           soc_litedramcore_sequencer_start0 = 1'd0;
+wire          soc_litedramcore_sequencer_start1;
+reg     [5:0] soc_litedramcore_sequencer_trigger = 6'd0;
+wire          soc_litedramcore_slave_p0_act_n;
+wire   [13:0] soc_litedramcore_slave_p0_address;
+wire    [2:0] soc_litedramcore_slave_p0_bank;
+wire          soc_litedramcore_slave_p0_cas_n;
+wire          soc_litedramcore_slave_p0_cke;
+wire          soc_litedramcore_slave_p0_cs_n;
+wire          soc_litedramcore_slave_p0_odt;
+wire          soc_litedramcore_slave_p0_ras_n;
+reg    [31:0] soc_litedramcore_slave_p0_rddata = 32'd0;
+wire          soc_litedramcore_slave_p0_rddata_en;
+reg           soc_litedramcore_slave_p0_rddata_valid = 1'd0;
+wire          soc_litedramcore_slave_p0_reset_n;
+wire          soc_litedramcore_slave_p0_we_n;
+wire   [31:0] soc_litedramcore_slave_p0_wrdata;
+wire          soc_litedramcore_slave_p0_wrdata_en;
+wire    [3:0] soc_litedramcore_slave_p0_wrdata_mask;
+wire          soc_litedramcore_slave_p1_act_n;
+wire   [13:0] soc_litedramcore_slave_p1_address;
+wire    [2:0] soc_litedramcore_slave_p1_bank;
+wire          soc_litedramcore_slave_p1_cas_n;
+wire          soc_litedramcore_slave_p1_cke;
+wire          soc_litedramcore_slave_p1_cs_n;
+wire          soc_litedramcore_slave_p1_odt;
+wire          soc_litedramcore_slave_p1_ras_n;
+reg    [31:0] soc_litedramcore_slave_p1_rddata = 32'd0;
+wire          soc_litedramcore_slave_p1_rddata_en;
+reg           soc_litedramcore_slave_p1_rddata_valid = 1'd0;
+wire          soc_litedramcore_slave_p1_reset_n;
+wire          soc_litedramcore_slave_p1_we_n;
+wire   [31:0] soc_litedramcore_slave_p1_wrdata;
+wire          soc_litedramcore_slave_p1_wrdata_en;
+wire    [3:0] soc_litedramcore_slave_p1_wrdata_mask;
+wire          soc_litedramcore_slave_p2_act_n;
+wire   [13:0] soc_litedramcore_slave_p2_address;
+wire    [2:0] soc_litedramcore_slave_p2_bank;
+wire          soc_litedramcore_slave_p2_cas_n;
+wire          soc_litedramcore_slave_p2_cke;
+wire          soc_litedramcore_slave_p2_cs_n;
+wire          soc_litedramcore_slave_p2_odt;
+wire          soc_litedramcore_slave_p2_ras_n;
+reg    [31:0] soc_litedramcore_slave_p2_rddata = 32'd0;
+wire          soc_litedramcore_slave_p2_rddata_en;
+reg           soc_litedramcore_slave_p2_rddata_valid = 1'd0;
+wire          soc_litedramcore_slave_p2_reset_n;
+wire          soc_litedramcore_slave_p2_we_n;
+wire   [31:0] soc_litedramcore_slave_p2_wrdata;
+wire          soc_litedramcore_slave_p2_wrdata_en;
+wire    [3:0] soc_litedramcore_slave_p2_wrdata_mask;
+wire          soc_litedramcore_slave_p3_act_n;
+wire   [13:0] soc_litedramcore_slave_p3_address;
+wire    [2:0] soc_litedramcore_slave_p3_bank;
+wire          soc_litedramcore_slave_p3_cas_n;
+wire          soc_litedramcore_slave_p3_cke;
+wire          soc_litedramcore_slave_p3_cs_n;
+wire          soc_litedramcore_slave_p3_odt;
+wire          soc_litedramcore_slave_p3_ras_n;
+reg    [31:0] soc_litedramcore_slave_p3_rddata = 32'd0;
+wire          soc_litedramcore_slave_p3_rddata_en;
+reg           soc_litedramcore_slave_p3_rddata_valid = 1'd0;
+wire          soc_litedramcore_slave_p3_reset_n;
+wire          soc_litedramcore_slave_p3_we_n;
+wire   [31:0] soc_litedramcore_slave_p3_wrdata;
+wire          soc_litedramcore_slave_p3_wrdata_en;
+wire    [3:0] soc_litedramcore_slave_p3_wrdata_mask;
+reg     [1:0] soc_litedramcore_steerer0 = 2'd0;
+reg     [1:0] soc_litedramcore_steerer1 = 2'd0;
+reg           soc_litedramcore_steerer10 = 1'd1;
+reg           soc_litedramcore_steerer11 = 1'd1;
+reg     [1:0] soc_litedramcore_steerer2 = 2'd0;
+reg     [1:0] soc_litedramcore_steerer3 = 2'd0;
 reg           soc_litedramcore_steerer4 = 1'd1;
 reg           soc_litedramcore_steerer5 = 1'd1;
 reg           soc_litedramcore_steerer6 = 1'd1;
 reg           soc_litedramcore_steerer7 = 1'd1;
-wire          soc_litedramcore_trrdcon_valid;
-reg           soc_litedramcore_trrdcon_ready = 1'd0;
-reg           soc_litedramcore_trrdcon_count = 1'd0;
-wire          soc_litedramcore_tfawcon_valid;
-reg           soc_litedramcore_tfawcon_ready = 1'd1;
+reg           soc_litedramcore_steerer8 = 1'd1;
+reg           soc_litedramcore_steerer9 = 1'd1;
+reg     [3:0] soc_litedramcore_storage = 4'd1;
+reg           soc_litedramcore_tccdcon_count = 1'd0;
+reg           soc_litedramcore_tccdcon_ready = 1'd0;
+wire          soc_litedramcore_tccdcon_valid;
 wire    [2:0] soc_litedramcore_tfawcon_count;
+reg           soc_litedramcore_tfawcon_ready = 1'd1;
+wire          soc_litedramcore_tfawcon_valid;
 reg     [4:0] soc_litedramcore_tfawcon_window = 5'd0;
-wire          soc_litedramcore_tccdcon_valid;
-reg           soc_litedramcore_tccdcon_ready = 1'd0;
-reg           soc_litedramcore_tccdcon_count = 1'd0;
-wire          soc_litedramcore_twtrcon_valid;
-reg           soc_litedramcore_twtrcon_ready = 1'd0;
-reg     [2:0] soc_litedramcore_twtrcon_count = 3'd0;
-wire          soc_litedramcore_read_available;
-wire          soc_litedramcore_write_available;
-reg           soc_litedramcore_en0 = 1'd0;
-wire          soc_litedramcore_max_time0;
 reg     [4:0] soc_litedramcore_time0 = 5'd0;
-reg           soc_litedramcore_en1 = 1'd0;
-wire          soc_litedramcore_max_time1;
 reg     [3:0] soc_litedramcore_time1 = 4'd0;
-wire          soc_litedramcore_go_to_refresh;
-reg           soc_init_done_storage = 1'd0;
-reg           soc_init_done_re = 1'd0;
-reg           soc_init_error_storage = 1'd0;
-reg           soc_init_error_re = 1'd0;
+wire    [9:0] soc_litedramcore_timer_count0;
+reg     [9:0] soc_litedramcore_timer_count1 = 10'd781;
+wire          soc_litedramcore_timer_done0;
+wire          soc_litedramcore_timer_done1;
+wire          soc_litedramcore_timer_wait;
+reg           soc_litedramcore_trrdcon_count = 1'd0;
+reg           soc_litedramcore_trrdcon_ready = 1'd0;
+wire          soc_litedramcore_trrdcon_valid;
+reg     [2:0] soc_litedramcore_twtrcon_count = 3'd0;
+reg           soc_litedramcore_twtrcon_ready = 1'd0;
+wire          soc_litedramcore_twtrcon_valid;
+wire          soc_litedramcore_wants_refresh;
+wire          soc_litedramcore_wants_zqcs;
+wire          soc_litedramcore_write_available;
+reg           soc_litedramcore_zqcs_executer_done = 1'd0;
+reg           soc_litedramcore_zqcs_executer_start = 1'd0;
+reg     [4:0] soc_litedramcore_zqcs_executer_trigger = 5'd0;
+wire   [26:0] soc_litedramcore_zqcs_timer_count0;
+reg    [26:0] soc_litedramcore_zqcs_timer_count1 = 27'd99999999;
+wire          soc_litedramcore_zqcs_timer_done0;
+wire          soc_litedramcore_zqcs_timer_done1;
+wire          soc_litedramcore_zqcs_timer_wait;
+wire          soc_user_enable;
+wire   [23:0] soc_user_port_cmd_payload_addr;
+wire          soc_user_port_cmd_payload_we;
+wire          soc_user_port_cmd_ready;
+wire          soc_user_port_cmd_valid;
+wire  [127:0] soc_user_port_rdata_payload_data;
+wire          soc_user_port_rdata_ready;
+wire          soc_user_port_rdata_valid;
+wire  [127:0] soc_user_port_wdata_payload_data;
+wire   [15:0] soc_user_port_wdata_payload_we;
+wire          soc_user_port_wdata_ready;
+wire          soc_user_port_wdata_valid;
+wire          soc_wb_bus_ack;
 wire   [29:0] soc_wb_bus_adr;
-wire   [31:0] soc_wb_bus_dat_w;
+wire    [1:0] soc_wb_bus_bte;
+wire    [2:0] soc_wb_bus_cti;
+wire          soc_wb_bus_cyc;
 wire   [31:0] soc_wb_bus_dat_r;
+wire   [31:0] soc_wb_bus_dat_w;
+wire          soc_wb_bus_err;
 wire    [3:0] soc_wb_bus_sel;
-wire          soc_wb_bus_cyc;
 wire          soc_wb_bus_stb;
-wire          soc_wb_bus_ack;
 wire          soc_wb_bus_we;
-wire    [2:0] soc_wb_bus_cti;
-wire    [1:0] soc_wb_bus_bte;
-wire          soc_wb_bus_err;
-wire          soc_user_enable;
-wire          soc_user_port_cmd_valid;
-wire          soc_user_port_cmd_ready;
-wire          soc_user_port_cmd_payload_we;
-wire   [23:0] soc_user_port_cmd_payload_addr;
-wire          soc_user_port_wdata_valid;
-wire          soc_user_port_wdata_ready;
-wire  [127:0] soc_user_port_wdata_payload_data;
-wire   [15:0] soc_user_port_wdata_payload_we;
-wire          soc_user_port_rdata_valid;
-wire          soc_user_port_rdata_ready;
-wire  [127:0] soc_user_port_rdata_payload_data;
-reg    [13:0] litedramcore_adr = 14'd0;
-reg           litedramcore_we = 1'd0;
-reg    [31:0] litedramcore_dat_w = 32'd0;
-wire   [31:0] litedramcore_dat_r;
-wire   [29:0] litedramcore_wishbone_adr;
-wire   [31:0] litedramcore_wishbone_dat_w;
-reg    [31:0] litedramcore_wishbone_dat_r = 32'd0;
-wire    [3:0] litedramcore_wishbone_sel;
-wire          litedramcore_wishbone_cyc;
-wire          litedramcore_wishbone_stb;
-reg           litedramcore_wishbone_ack = 1'd0;
-wire          litedramcore_wishbone_we;
-wire    [2:0] litedramcore_wishbone_cti;
-wire    [1:0] litedramcore_wishbone_bte;
-reg           litedramcore_wishbone_err = 1'd0;
-wire   [13:0] interface0_bank_bus_adr;
-wire          interface0_bank_bus_we;
-wire   [31:0] interface0_bank_bus_dat_w;
-reg    [31:0] interface0_bank_bus_dat_r = 32'd0;
-reg           csrbank0_init_done0_re = 1'd0;
-wire          csrbank0_init_done0_r;
-reg           csrbank0_init_done0_we = 1'd0;
-wire          csrbank0_init_done0_w;
-reg           csrbank0_init_error0_re = 1'd0;
-wire          csrbank0_init_error0_r;
-reg           csrbank0_init_error0_we = 1'd0;
-wire          csrbank0_init_error0_w;
-wire          csrbank0_sel;
-wire   [13:0] interface1_bank_bus_adr;
-wire          interface1_bank_bus_we;
-wire   [31:0] interface1_bank_bus_dat_w;
-reg    [31:0] interface1_bank_bus_dat_r = 32'd0;
-reg           csrbank1_dfii_control0_re = 1'd0;
-wire    [3:0] csrbank1_dfii_control0_r;
-reg           csrbank1_dfii_control0_we = 1'd0;
-wire    [3:0] csrbank1_dfii_control0_w;
-reg           csrbank1_dfii_pi0_command0_re = 1'd0;
-wire    [5:0] csrbank1_dfii_pi0_command0_r;
-reg           csrbank1_dfii_pi0_command0_we = 1'd0;
-wire    [5:0] csrbank1_dfii_pi0_command0_w;
-reg           csrbank1_dfii_pi0_address0_re = 1'd0;
-wire   [13:0] csrbank1_dfii_pi0_address0_r;
-reg           csrbank1_dfii_pi0_address0_we = 1'd0;
-wire   [13:0] csrbank1_dfii_pi0_address0_w;
-reg           csrbank1_dfii_pi0_baddress0_re = 1'd0;
-wire    [2:0] csrbank1_dfii_pi0_baddress0_r;
-reg           csrbank1_dfii_pi0_baddress0_we = 1'd0;
-wire    [2:0] csrbank1_dfii_pi0_baddress0_w;
-reg           csrbank1_dfii_pi0_wrdata0_re = 1'd0;
-wire   [31:0] csrbank1_dfii_pi0_wrdata0_r;
-reg           csrbank1_dfii_pi0_wrdata0_we = 1'd0;
-wire   [31:0] csrbank1_dfii_pi0_wrdata0_w;
-reg           csrbank1_dfii_pi0_rddata_re = 1'd0;
-wire   [31:0] csrbank1_dfii_pi0_rddata_r;
-reg           csrbank1_dfii_pi0_rddata_we = 1'd0;
-wire   [31:0] csrbank1_dfii_pi0_rddata_w;
-reg           csrbank1_dfii_pi1_command0_re = 1'd0;
-wire    [5:0] csrbank1_dfii_pi1_command0_r;
-reg           csrbank1_dfii_pi1_command0_we = 1'd0;
-wire    [5:0] csrbank1_dfii_pi1_command0_w;
-reg           csrbank1_dfii_pi1_address0_re = 1'd0;
-wire   [13:0] csrbank1_dfii_pi1_address0_r;
-reg           csrbank1_dfii_pi1_address0_we = 1'd0;
-wire   [13:0] csrbank1_dfii_pi1_address0_w;
-reg           csrbank1_dfii_pi1_baddress0_re = 1'd0;
-wire    [2:0] csrbank1_dfii_pi1_baddress0_r;
-reg           csrbank1_dfii_pi1_baddress0_we = 1'd0;
-wire    [2:0] csrbank1_dfii_pi1_baddress0_w;
-reg           csrbank1_dfii_pi1_wrdata0_re = 1'd0;
-wire   [31:0] csrbank1_dfii_pi1_wrdata0_r;
-reg           csrbank1_dfii_pi1_wrdata0_we = 1'd0;
-wire   [31:0] csrbank1_dfii_pi1_wrdata0_w;
-reg           csrbank1_dfii_pi1_rddata_re = 1'd0;
-wire   [31:0] csrbank1_dfii_pi1_rddata_r;
-reg           csrbank1_dfii_pi1_rddata_we = 1'd0;
-wire   [31:0] csrbank1_dfii_pi1_rddata_w;
-reg           csrbank1_dfii_pi2_command0_re = 1'd0;
-wire    [5:0] csrbank1_dfii_pi2_command0_r;
-reg           csrbank1_dfii_pi2_command0_we = 1'd0;
-wire    [5:0] csrbank1_dfii_pi2_command0_w;
-reg           csrbank1_dfii_pi2_address0_re = 1'd0;
-wire   [13:0] csrbank1_dfii_pi2_address0_r;
-reg           csrbank1_dfii_pi2_address0_we = 1'd0;
-wire   [13:0] csrbank1_dfii_pi2_address0_w;
-reg           csrbank1_dfii_pi2_baddress0_re = 1'd0;
-wire    [2:0] csrbank1_dfii_pi2_baddress0_r;
-reg           csrbank1_dfii_pi2_baddress0_we = 1'd0;
-wire    [2:0] csrbank1_dfii_pi2_baddress0_w;
-reg           csrbank1_dfii_pi2_wrdata0_re = 1'd0;
-wire   [31:0] csrbank1_dfii_pi2_wrdata0_r;
-reg           csrbank1_dfii_pi2_wrdata0_we = 1'd0;
-wire   [31:0] csrbank1_dfii_pi2_wrdata0_w;
-reg           csrbank1_dfii_pi2_rddata_re = 1'd0;
-wire   [31:0] csrbank1_dfii_pi2_rddata_r;
-reg           csrbank1_dfii_pi2_rddata_we = 1'd0;
-wire   [31:0] csrbank1_dfii_pi2_rddata_w;
-reg           csrbank1_dfii_pi3_command0_re = 1'd0;
-wire    [5:0] csrbank1_dfii_pi3_command0_r;
-reg           csrbank1_dfii_pi3_command0_we = 1'd0;
-wire    [5:0] csrbank1_dfii_pi3_command0_w;
-reg           csrbank1_dfii_pi3_address0_re = 1'd0;
-wire   [13:0] csrbank1_dfii_pi3_address0_r;
-reg           csrbank1_dfii_pi3_address0_we = 1'd0;
-wire   [13:0] csrbank1_dfii_pi3_address0_w;
-reg           csrbank1_dfii_pi3_baddress0_re = 1'd0;
-wire    [2:0] csrbank1_dfii_pi3_baddress0_r;
-reg           csrbank1_dfii_pi3_baddress0_we = 1'd0;
-wire    [2:0] csrbank1_dfii_pi3_baddress0_w;
-reg           csrbank1_dfii_pi3_wrdata0_re = 1'd0;
-wire   [31:0] csrbank1_dfii_pi3_wrdata0_r;
-reg           csrbank1_dfii_pi3_wrdata0_we = 1'd0;
-wire   [31:0] csrbank1_dfii_pi3_wrdata0_w;
-reg           csrbank1_dfii_pi3_rddata_re = 1'd0;
-wire   [31:0] csrbank1_dfii_pi3_rddata_r;
-reg           csrbank1_dfii_pi3_rddata_we = 1'd0;
-wire   [31:0] csrbank1_dfii_pi3_rddata_w;
-wire          csrbank1_sel;
-wire   [13:0] csr_interconnect_adr;
-wire          csr_interconnect_we;
-wire   [31:0] csr_interconnect_dat_w;
-wire   [31:0] csr_interconnect_dat_r;
-reg     [1:0] litedramcore_refresher_state = 2'd0;
-reg     [1:0] litedramcore_refresher_next_state = 2'd0;
-reg     [3:0] litedramcore_bankmachine0_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine0_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine1_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine1_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine2_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine2_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine3_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine3_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine4_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine4_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine5_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine5_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine6_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine6_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine7_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine7_next_state = 4'd0;
-reg     [3:0] litedramcore_multiplexer_state = 4'd0;
-reg     [3:0] litedramcore_multiplexer_next_state = 4'd0;
-wire          litedramcore_roundrobin0_request;
-wire          litedramcore_roundrobin0_grant;
-wire          litedramcore_roundrobin0_ce;
-wire          litedramcore_roundrobin1_request;
-wire          litedramcore_roundrobin1_grant;
-wire          litedramcore_roundrobin1_ce;
-wire          litedramcore_roundrobin2_request;
-wire          litedramcore_roundrobin2_grant;
-wire          litedramcore_roundrobin2_ce;
-wire          litedramcore_roundrobin3_request;
-wire          litedramcore_roundrobin3_grant;
-wire          litedramcore_roundrobin3_ce;
-wire          litedramcore_roundrobin4_request;
-wire          litedramcore_roundrobin4_grant;
-wire          litedramcore_roundrobin4_ce;
-wire          litedramcore_roundrobin5_request;
-wire          litedramcore_roundrobin5_grant;
-wire          litedramcore_roundrobin5_ce;
-wire          litedramcore_roundrobin6_request;
-wire          litedramcore_roundrobin6_grant;
-wire          litedramcore_roundrobin6_ce;
-wire          litedramcore_roundrobin7_request;
-wire          litedramcore_roundrobin7_grant;
-wire          litedramcore_roundrobin7_ce;
-reg           litedramcore_locked0 = 1'd0;
-reg           litedramcore_locked1 = 1'd0;
-reg           litedramcore_locked2 = 1'd0;
-reg           litedramcore_locked3 = 1'd0;
-reg           litedramcore_locked4 = 1'd0;
-reg           litedramcore_locked5 = 1'd0;
-reg           litedramcore_locked6 = 1'd0;
-reg           litedramcore_locked7 = 1'd0;
-reg           litedramcore_new_master_wdata_ready0 = 1'd0;
-reg           litedramcore_new_master_wdata_ready1 = 1'd0;
-reg           litedramcore_new_master_rdata_valid0 = 1'd0;
-reg           litedramcore_new_master_rdata_valid1 = 1'd0;
-reg           litedramcore_new_master_rdata_valid2 = 1'd0;
-reg           litedramcore_new_master_rdata_valid3 = 1'd0;
-reg           litedramcore_new_master_rdata_valid4 = 1'd0;
-reg           litedramcore_new_master_rdata_valid5 = 1'd0;
-reg           litedramcore_new_master_rdata_valid6 = 1'd0;
-reg           litedramcore_new_master_rdata_valid7 = 1'd0;
-reg           litedramcore_new_master_rdata_valid8 = 1'd0;
-reg     [1:0] litedramcore_state = 2'd0;
-reg     [1:0] litedramcore_next_state = 2'd0;
-reg    [31:0] litedramcore_dat_w_next_value0 = 32'd0;
-reg           litedramcore_dat_w_next_value_ce0 = 1'd0;
-reg    [13:0] litedramcore_adr_next_value1 = 14'd0;
-reg           litedramcore_adr_next_value_ce1 = 1'd0;
-reg           litedramcore_we_next_value2 = 1'd0;
-reg           litedramcore_we_next_value_ce2 = 1'd0;
-wire   [24:0] slice_proxy0;
-wire   [24:0] slice_proxy1;
-wire   [24:0] slice_proxy2;
-wire   [24:0] slice_proxy3;
-wire   [24:0] slice_proxy4;
-wire   [24:0] slice_proxy5;
-wire   [24:0] slice_proxy6;
-wire   [24:0] slice_proxy7;
-wire   [24:0] slice_proxy8;
-wire   [24:0] slice_proxy9;
-wire   [24:0] slice_proxy10;
-wire   [24:0] slice_proxy11;
-wire   [24:0] slice_proxy12;
-wire   [24:0] slice_proxy13;
-wire   [24:0] slice_proxy14;
-wire   [24:0] slice_proxy15;
-reg           rhs_array_muxed0 = 1'd0;
-reg    [13:0] rhs_array_muxed1 = 14'd0;
-reg     [2:0] rhs_array_muxed2 = 3'd0;
-reg           rhs_array_muxed3 = 1'd0;
-reg           rhs_array_muxed4 = 1'd0;
-reg           rhs_array_muxed5 = 1'd0;
-reg           t_array_muxed0 = 1'd0;
-reg           t_array_muxed1 = 1'd0;
-reg           t_array_muxed2 = 1'd0;
-reg           rhs_array_muxed6 = 1'd0;
-reg    [13:0] rhs_array_muxed7 = 14'd0;
-reg     [2:0] rhs_array_muxed8 = 3'd0;
-reg           rhs_array_muxed9 = 1'd0;
-reg           rhs_array_muxed10 = 1'd0;
-reg           rhs_array_muxed11 = 1'd0;
-reg           t_array_muxed3 = 1'd0;
-reg           t_array_muxed4 = 1'd0;
-reg           t_array_muxed5 = 1'd0;
-reg    [20:0] rhs_array_muxed12 = 21'd0;
-reg           rhs_array_muxed13 = 1'd0;
-reg           rhs_array_muxed14 = 1'd0;
-reg    [20:0] rhs_array_muxed15 = 21'd0;
-reg           rhs_array_muxed16 = 1'd0;
-reg           rhs_array_muxed17 = 1'd0;
-reg    [20:0] rhs_array_muxed18 = 21'd0;
-reg           rhs_array_muxed19 = 1'd0;
-reg           rhs_array_muxed20 = 1'd0;
-reg    [20:0] rhs_array_muxed21 = 21'd0;
-reg           rhs_array_muxed22 = 1'd0;
-reg           rhs_array_muxed23 = 1'd0;
-reg    [20:0] rhs_array_muxed24 = 21'd0;
-reg           rhs_array_muxed25 = 1'd0;
-reg           rhs_array_muxed26 = 1'd0;
-reg    [20:0] rhs_array_muxed27 = 21'd0;
-reg           rhs_array_muxed28 = 1'd0;
-reg           rhs_array_muxed29 = 1'd0;
-reg    [20:0] rhs_array_muxed30 = 21'd0;
-reg           rhs_array_muxed31 = 1'd0;
-reg           rhs_array_muxed32 = 1'd0;
-reg    [20:0] rhs_array_muxed33 = 21'd0;
-reg           rhs_array_muxed34 = 1'd0;
-reg           rhs_array_muxed35 = 1'd0;
-reg     [2:0] array_muxed0 = 3'd0;
-reg    [13:0] array_muxed1 = 14'd0;
-reg           array_muxed2 = 1'd0;
-reg           array_muxed3 = 1'd0;
-reg           array_muxed4 = 1'd0;
-reg           array_muxed5 = 1'd0;
-reg           array_muxed6 = 1'd0;
-reg     [2:0] array_muxed7 = 3'd0;
-reg    [13:0] array_muxed8 = 14'd0;
-reg           array_muxed9 = 1'd0;
-reg           array_muxed10 = 1'd0;
-reg           array_muxed11 = 1'd0;
-reg           array_muxed12 = 1'd0;
-reg           array_muxed13 = 1'd0;
-reg     [2:0] array_muxed14 = 3'd0;
-reg    [13:0] array_muxed15 = 14'd0;
-reg           array_muxed16 = 1'd0;
-reg           array_muxed17 = 1'd0;
-reg           array_muxed18 = 1'd0;
-reg           array_muxed19 = 1'd0;
-reg           array_muxed20 = 1'd0;
-reg     [2:0] array_muxed21 = 3'd0;
-reg    [13:0] array_muxed22 = 14'd0;
-reg           array_muxed23 = 1'd0;
-reg           array_muxed24 = 1'd0;
-reg           array_muxed25 = 1'd0;
-reg           array_muxed26 = 1'd0;
-reg           array_muxed27 = 1'd0;
+reg     [1:0] state = 2'd0;
+wire          sys_clk;
+wire          sys_rst;
+reg           t_self0 = 1'd0;
+reg           t_self1 = 1'd0;
+reg           t_self2 = 1'd0;
+reg           t_self3 = 1'd0;
+reg           t_self4 = 1'd0;
+reg           t_self5 = 1'd0;
+wire          we;
 
 //------------------------------------------------------------------------------
 // Combinatorial Logic
@@ -2062,6 +2245,17 @@ assign soc_user_port_wdata_payload_data = user_port_native_0_wdata_data;
 assign user_port_native_0_rdata_valid = (soc_user_port_rdata_valid & soc_user_enable);
 assign soc_user_port_rdata_ready = (user_port_native_0_rdata_ready & soc_user_enable);
 assign user_port_native_0_rdata_data = soc_user_port_rdata_payload_data;
+assign interface0_adr = soc_wb_bus_adr;
+assign interface0_dat_w = soc_wb_bus_dat_w;
+assign soc_wb_bus_dat_r = interface0_dat_r;
+assign interface0_sel = soc_wb_bus_sel;
+assign interface0_cyc = soc_wb_bus_cyc;
+assign interface0_stb = soc_wb_bus_stb;
+assign soc_wb_bus_ack = interface0_ack;
+assign interface0_we = soc_wb_bus_we;
+assign interface0_cti = soc_wb_bus_cti;
+assign interface0_bte = soc_wb_bus_bte;
+assign soc_wb_bus_err = interface0_err;
 assign sys_clk = clk;
 assign por_clk = clk;
 assign sys_rst = soc_int_rst;
@@ -3950,6 +4144,9 @@ always @(*) begin
             soc_litedramcore_master_p0_cs_n <= soc_litedramcore_ext_dfi_p0_cs_n;
         end else begin
             soc_litedramcore_master_p0_cs_n <= soc_litedramcore_slave_p0_cs_n;
+            if (1'd0) begin
+                soc_litedramcore_master_p0_cs_n <= {2{soc_litedramcore_slave_p0_cs_n}};
+            end
         end
     end else begin
         soc_litedramcore_master_p0_cs_n <= soc_litedramcore_csr_dfi_p0_cs_n;
@@ -4118,6 +4315,9 @@ always @(*) begin
             soc_litedramcore_master_p1_cs_n <= soc_litedramcore_ext_dfi_p1_cs_n;
         end else begin
             soc_litedramcore_master_p1_cs_n <= soc_litedramcore_slave_p1_cs_n;
+            if (1'd0) begin
+                soc_litedramcore_master_p1_cs_n <= {2{soc_litedramcore_slave_p1_cs_n}};
+            end
         end
     end else begin
         soc_litedramcore_master_p1_cs_n <= soc_litedramcore_csr_dfi_p1_cs_n;
@@ -4286,6 +4486,9 @@ always @(*) begin
             soc_litedramcore_master_p2_cs_n <= soc_litedramcore_ext_dfi_p2_cs_n;
         end else begin
             soc_litedramcore_master_p2_cs_n <= soc_litedramcore_slave_p2_cs_n;
+            if (1'd0) begin
+                soc_litedramcore_master_p2_cs_n <= {2{soc_litedramcore_slave_p2_cs_n}};
+            end
         end
     end else begin
         soc_litedramcore_master_p2_cs_n <= soc_litedramcore_csr_dfi_p2_cs_n;
@@ -4454,6 +4657,9 @@ always @(*) begin
             soc_litedramcore_master_p3_cs_n <= soc_litedramcore_ext_dfi_p3_cs_n;
         end else begin
             soc_litedramcore_master_p3_cs_n <= soc_litedramcore_slave_p3_cs_n;
+            if (1'd0) begin
+                soc_litedramcore_master_p3_cs_n <= {2{soc_litedramcore_slave_p3_cs_n}};
+            end
         end
     end else begin
         soc_litedramcore_master_p3_cs_n <= soc_litedramcore_csr_dfi_p3_cs_n;
@@ -4715,14 +4921,38 @@ always @(*) begin
     end else begin
     end
 end
-assign soc_litedramcore_csr_dfi_p0_cke = soc_litedramcore_cke;
-assign soc_litedramcore_csr_dfi_p1_cke = soc_litedramcore_cke;
-assign soc_litedramcore_csr_dfi_p2_cke = soc_litedramcore_cke;
-assign soc_litedramcore_csr_dfi_p3_cke = soc_litedramcore_cke;
-assign soc_litedramcore_csr_dfi_p0_odt = soc_litedramcore_odt;
-assign soc_litedramcore_csr_dfi_p1_odt = soc_litedramcore_odt;
-assign soc_litedramcore_csr_dfi_p2_odt = soc_litedramcore_odt;
-assign soc_litedramcore_csr_dfi_p3_odt = soc_litedramcore_odt;
+always @(*) begin
+    soc_litedramcore_csr_dfi_p0_cke <= 1'd0;
+    soc_litedramcore_csr_dfi_p0_cke <= soc_litedramcore_cke;
+end
+always @(*) begin
+    soc_litedramcore_csr_dfi_p1_cke <= 1'd0;
+    soc_litedramcore_csr_dfi_p1_cke <= soc_litedramcore_cke;
+end
+always @(*) begin
+    soc_litedramcore_csr_dfi_p2_cke <= 1'd0;
+    soc_litedramcore_csr_dfi_p2_cke <= soc_litedramcore_cke;
+end
+always @(*) begin
+    soc_litedramcore_csr_dfi_p3_cke <= 1'd0;
+    soc_litedramcore_csr_dfi_p3_cke <= soc_litedramcore_cke;
+end
+always @(*) begin
+    soc_litedramcore_csr_dfi_p0_odt <= 1'd0;
+    soc_litedramcore_csr_dfi_p0_odt <= soc_litedramcore_odt;
+end
+always @(*) begin
+    soc_litedramcore_csr_dfi_p1_odt <= 1'd0;
+    soc_litedramcore_csr_dfi_p1_odt <= soc_litedramcore_odt;
+end
+always @(*) begin
+    soc_litedramcore_csr_dfi_p2_odt <= 1'd0;
+    soc_litedramcore_csr_dfi_p2_odt <= soc_litedramcore_odt;
+end
+always @(*) begin
+    soc_litedramcore_csr_dfi_p3_odt <= 1'd0;
+    soc_litedramcore_csr_dfi_p3_odt <= soc_litedramcore_odt;
+end
 assign soc_litedramcore_csr_dfi_p0_reset_n = soc_litedramcore_reset_n;
 assign soc_litedramcore_csr_dfi_p1_reset_n = soc_litedramcore_reset_n;
 assign soc_litedramcore_csr_dfi_p2_reset_n = soc_litedramcore_reset_n;
@@ -4730,7 +4960,15 @@ assign soc_litedramcore_csr_dfi_p3_reset_n = soc_litedramcore_reset_n;
 always @(*) begin
     soc_litedramcore_csr_dfi_p0_cs_n <= 1'd1;
     if (soc_litedramcore_phaseinjector0_command_issue_re) begin
-        soc_litedramcore_csr_dfi_p0_cs_n <= {1{(~soc_litedramcore_phaseinjector0_csrfield_cs)}};
+        if (soc_litedramcore_phaseinjector0_csrfield_cs_top) begin
+            soc_litedramcore_csr_dfi_p0_cs_n <= 2'd2;
+        end else begin
+            if (soc_litedramcore_phaseinjector0_csrfield_cs_bottom) begin
+                soc_litedramcore_csr_dfi_p0_cs_n <= 1'd1;
+            end else begin
+                soc_litedramcore_csr_dfi_p0_cs_n <= {1{(~soc_litedramcore_phaseinjector0_csrfield_cs)}};
+            end
+        end
     end else begin
         soc_litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
     end
@@ -4768,7 +5006,15 @@ assign soc_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
 always @(*) begin
     soc_litedramcore_csr_dfi_p1_cs_n <= 1'd1;
     if (soc_litedramcore_phaseinjector1_command_issue_re) begin
-        soc_litedramcore_csr_dfi_p1_cs_n <= {1{(~soc_litedramcore_phaseinjector1_csrfield_cs)}};
+        if (soc_litedramcore_phaseinjector1_csrfield_cs_top) begin
+            soc_litedramcore_csr_dfi_p1_cs_n <= 2'd2;
+        end else begin
+            if (soc_litedramcore_phaseinjector1_csrfield_cs_bottom) begin
+                soc_litedramcore_csr_dfi_p1_cs_n <= 1'd1;
+            end else begin
+                soc_litedramcore_csr_dfi_p1_cs_n <= {1{(~soc_litedramcore_phaseinjector1_csrfield_cs)}};
+            end
+        end
     end else begin
         soc_litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
     end
@@ -4806,7 +5052,15 @@ assign soc_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
 always @(*) begin
     soc_litedramcore_csr_dfi_p2_cs_n <= 1'd1;
     if (soc_litedramcore_phaseinjector2_command_issue_re) begin
-        soc_litedramcore_csr_dfi_p2_cs_n <= {1{(~soc_litedramcore_phaseinjector2_csrfield_cs)}};
+        if (soc_litedramcore_phaseinjector2_csrfield_cs_top) begin
+            soc_litedramcore_csr_dfi_p2_cs_n <= 2'd2;
+        end else begin
+            if (soc_litedramcore_phaseinjector2_csrfield_cs_bottom) begin
+                soc_litedramcore_csr_dfi_p2_cs_n <= 1'd1;
+            end else begin
+                soc_litedramcore_csr_dfi_p2_cs_n <= {1{(~soc_litedramcore_phaseinjector2_csrfield_cs)}};
+            end
+        end
     end else begin
         soc_litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
     end
@@ -4844,7 +5098,15 @@ assign soc_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
 always @(*) begin
     soc_litedramcore_csr_dfi_p3_cs_n <= 1'd1;
     if (soc_litedramcore_phaseinjector3_command_issue_re) begin
-        soc_litedramcore_csr_dfi_p3_cs_n <= {1{(~soc_litedramcore_phaseinjector3_csrfield_cs)}};
+        if (soc_litedramcore_phaseinjector3_csrfield_cs_top) begin
+            soc_litedramcore_csr_dfi_p3_cs_n <= 2'd2;
+        end else begin
+            if (soc_litedramcore_phaseinjector3_csrfield_cs_bottom) begin
+                soc_litedramcore_csr_dfi_p3_cs_n <= 1'd1;
+            end else begin
+                soc_litedramcore_csr_dfi_p3_cs_n <= {1{(~soc_litedramcore_phaseinjector3_csrfield_cs)}};
+            end
+        end
     end else begin
         soc_litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
     end
@@ -4949,32 +5211,32 @@ assign soc_litedramcore_zqcs_timer_done1 = (soc_litedramcore_zqcs_timer_count1 =
 assign soc_litedramcore_zqcs_timer_done0 = soc_litedramcore_zqcs_timer_done1;
 assign soc_litedramcore_zqcs_timer_count0 = soc_litedramcore_zqcs_timer_count1;
 always @(*) begin
-    litedramcore_refresher_next_state <= 2'd0;
-    litedramcore_refresher_next_state <= litedramcore_refresher_state;
-    case (litedramcore_refresher_state)
+    refresher_next_state <= 2'd0;
+    refresher_next_state <= refresher_state;
+    case (refresher_state)
         1'd1: begin
             if (soc_litedramcore_cmd_ready) begin
-                litedramcore_refresher_next_state <= 2'd2;
+                refresher_next_state <= 2'd2;
             end
         end
         2'd2: begin
             if (soc_litedramcore_sequencer_done0) begin
                 if (soc_litedramcore_wants_zqcs) begin
-                    litedramcore_refresher_next_state <= 2'd3;
+                    refresher_next_state <= 2'd3;
                 end else begin
-                    litedramcore_refresher_next_state <= 1'd0;
+                    refresher_next_state <= 1'd0;
                 end
             end
         end
         2'd3: begin
             if (soc_litedramcore_zqcs_executer_done) begin
-                litedramcore_refresher_next_state <= 1'd0;
+                refresher_next_state <= 1'd0;
             end
         end
         default: begin
             if (1'd1) begin
                 if (soc_litedramcore_wants_refresh) begin
-                    litedramcore_refresher_next_state <= 1'd1;
+                    refresher_next_state <= 1'd1;
                 end
             end
         end
@@ -4982,7 +5244,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_sequencer_start0 <= 1'd0;
-    case (litedramcore_refresher_state)
+    case (refresher_state)
         1'd1: begin
             if (soc_litedramcore_cmd_ready) begin
                 soc_litedramcore_sequencer_start0 <= 1'd1;
@@ -4998,7 +5260,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_cmd_valid <= 1'd0;
-    case (litedramcore_refresher_state)
+    case (refresher_state)
         1'd1: begin
             soc_litedramcore_cmd_valid <= 1'd1;
         end
@@ -5023,7 +5285,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_zqcs_executer_start <= 1'd0;
-    case (litedramcore_refresher_state)
+    case (refresher_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5042,7 +5304,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_cmd_last <= 1'd0;
-    case (litedramcore_refresher_state)
+    case (refresher_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5141,69 +5403,95 @@ assign soc_litedramcore_bankmachine0_source_source_last = soc_litedramcore_bankm
 assign soc_litedramcore_bankmachine0_source_source_payload_we = soc_litedramcore_bankmachine0_pipe_valid_source_payload_we;
 assign soc_litedramcore_bankmachine0_source_source_payload_addr = soc_litedramcore_bankmachine0_pipe_valid_source_payload_addr;
 always @(*) begin
-    litedramcore_bankmachine0_next_state <= 4'd0;
-    litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
-    case (litedramcore_bankmachine0_state)
+    bankmachine0_next_state <= 4'd0;
+    bankmachine0_next_state <= bankmachine0_state;
+    case (bankmachine0_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
                 if (soc_litedramcore_bankmachine0_cmd_ready) begin
-                    litedramcore_bankmachine0_next_state <= 3'd5;
+                    bankmachine0_next_state <= 3'd5;
                 end
             end
         end
         2'd2: begin
             if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_next_state <= 3'd5;
+                bankmachine0_next_state <= 3'd5;
             end
         end
         2'd3: begin
             if (soc_litedramcore_bankmachine0_trccon_ready) begin
                 if (soc_litedramcore_bankmachine0_cmd_ready) begin
-                    litedramcore_bankmachine0_next_state <= 3'd7;
+                    bankmachine0_next_state <= 3'd7;
                 end
             end
         end
         3'd4: begin
             if ((~soc_litedramcore_bankmachine0_refresh_req)) begin
-                litedramcore_bankmachine0_next_state <= 1'd0;
+                bankmachine0_next_state <= 1'd0;
             end
         end
         3'd5: begin
-            litedramcore_bankmachine0_next_state <= 3'd6;
+            bankmachine0_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine0_next_state <= 2'd3;
+            bankmachine0_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine0_next_state <= 4'd8;
+            bankmachine0_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine0_next_state <= 1'd0;
+            bankmachine0_next_state <= 1'd0;
         end
         default: begin
             if (soc_litedramcore_bankmachine0_refresh_req) begin
-                litedramcore_bankmachine0_next_state <= 3'd4;
+                bankmachine0_next_state <= 3'd4;
             end else begin
                 if (soc_litedramcore_bankmachine0_source_source_valid) begin
                     if (soc_litedramcore_bankmachine0_row_opened) begin
                         if (soc_litedramcore_bankmachine0_row_hit) begin
                             if ((soc_litedramcore_bankmachine0_cmd_ready & soc_litedramcore_bankmachine0_auto_precharge)) begin
-                                litedramcore_bankmachine0_next_state <= 2'd2;
+                                bankmachine0_next_state <= 2'd2;
                             end
                         end else begin
-                            litedramcore_bankmachine0_next_state <= 1'd1;
+                            bankmachine0_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine0_next_state <= 2'd3;
+                        bankmachine0_next_state <= 2'd3;
                     end
                 end
             end
         end
     endcase
 end
+always @(*) begin
+    soc_litedramcore_bankmachine0_row_close <= 1'd0;
+    case (bankmachine0_state)
+        1'd1: begin
+            soc_litedramcore_bankmachine0_row_close <= 1'd1;
+        end
+        2'd2: begin
+            soc_litedramcore_bankmachine0_row_close <= 1'd1;
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            soc_litedramcore_bankmachine0_row_close <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
 always @(*) begin
     soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    case (bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5229,7 +5517,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    case (bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5264,7 +5552,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    case (bankmachine0_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
                 soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
@@ -5293,7 +5581,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    case (bankmachine0_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
                 soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
@@ -5334,7 +5622,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    case (bankmachine0_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
                 soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
@@ -5364,7 +5652,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    case (bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5402,7 +5690,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    case (bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5440,7 +5728,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    case (bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5478,7 +5766,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    case (bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5516,7 +5804,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    case (bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5542,7 +5830,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine0_row_open <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    case (bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5568,7 +5856,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine0_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    case (bankmachine0_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
                 soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
@@ -5607,32 +5895,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    soc_litedramcore_bankmachine0_row_close <= 1'd0;
-    case (litedramcore_bankmachine0_state)
-        1'd1: begin
-            soc_litedramcore_bankmachine0_row_close <= 1'd1;
-        end
-        2'd2: begin
-            soc_litedramcore_bankmachine0_row_close <= 1'd1;
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            soc_litedramcore_bankmachine0_row_close <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
 assign soc_litedramcore_bankmachine1_sink_valid = soc_litedramcore_bankmachine1_req_valid;
 assign soc_litedramcore_bankmachine1_req_ready = soc_litedramcore_bankmachine1_sink_ready;
 assign soc_litedramcore_bankmachine1_sink_payload_we = soc_litedramcore_bankmachine1_req_we;
@@ -5712,60 +5974,95 @@ assign soc_litedramcore_bankmachine1_source_source_last = soc_litedramcore_bankm
 assign soc_litedramcore_bankmachine1_source_source_payload_we = soc_litedramcore_bankmachine1_pipe_valid_source_payload_we;
 assign soc_litedramcore_bankmachine1_source_source_payload_addr = soc_litedramcore_bankmachine1_pipe_valid_source_payload_addr;
 always @(*) begin
-    litedramcore_bankmachine1_next_state <= 4'd0;
-    litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
-    case (litedramcore_bankmachine1_state)
+    bankmachine1_next_state <= 4'd0;
+    bankmachine1_next_state <= bankmachine1_state;
+    case (bankmachine1_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
                 if (soc_litedramcore_bankmachine1_cmd_ready) begin
-                    litedramcore_bankmachine1_next_state <= 3'd5;
+                    bankmachine1_next_state <= 3'd5;
                 end
             end
         end
         2'd2: begin
             if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_next_state <= 3'd5;
+                bankmachine1_next_state <= 3'd5;
             end
         end
         2'd3: begin
             if (soc_litedramcore_bankmachine1_trccon_ready) begin
                 if (soc_litedramcore_bankmachine1_cmd_ready) begin
-                    litedramcore_bankmachine1_next_state <= 3'd7;
+                    bankmachine1_next_state <= 3'd7;
                 end
             end
         end
         3'd4: begin
             if ((~soc_litedramcore_bankmachine1_refresh_req)) begin
-                litedramcore_bankmachine1_next_state <= 1'd0;
+                bankmachine1_next_state <= 1'd0;
             end
         end
         3'd5: begin
-            litedramcore_bankmachine1_next_state <= 3'd6;
+            bankmachine1_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine1_next_state <= 2'd3;
+            bankmachine1_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine1_next_state <= 4'd8;
+            bankmachine1_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine1_next_state <= 1'd0;
+            bankmachine1_next_state <= 1'd0;
         end
         default: begin
             if (soc_litedramcore_bankmachine1_refresh_req) begin
-                litedramcore_bankmachine1_next_state <= 3'd4;
+                bankmachine1_next_state <= 3'd4;
             end else begin
                 if (soc_litedramcore_bankmachine1_source_source_valid) begin
                     if (soc_litedramcore_bankmachine1_row_opened) begin
                         if (soc_litedramcore_bankmachine1_row_hit) begin
                             if ((soc_litedramcore_bankmachine1_cmd_ready & soc_litedramcore_bankmachine1_auto_precharge)) begin
-                                litedramcore_bankmachine1_next_state <= 2'd2;
+                                bankmachine1_next_state <= 2'd2;
                             end
                         end else begin
-                            litedramcore_bankmachine1_next_state <= 1'd1;
+                            bankmachine1_next_state <= 1'd1;
+                        end
+                    end else begin
+                        bankmachine1_next_state <= 2'd3;
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+    case (bankmachine1_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (soc_litedramcore_bankmachine1_refresh_req) begin
+            end else begin
+                if (soc_litedramcore_bankmachine1_source_source_valid) begin
+                    if (soc_litedramcore_bankmachine1_row_opened) begin
+                        if (soc_litedramcore_bankmachine1_row_hit) begin
+                            soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+                        end else begin
                         end
                     end else begin
-                        litedramcore_bankmachine1_next_state <= 2'd3;
                     end
                 end
             end
@@ -5774,7 +6071,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    case (bankmachine1_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
                 soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
@@ -5803,7 +6100,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    case (bankmachine1_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
                 soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
@@ -5844,7 +6141,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    case (bankmachine1_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
                 soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
@@ -5874,7 +6171,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    case (bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5912,7 +6209,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    case (bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5950,7 +6247,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    case (bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5988,7 +6285,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    case (bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6026,7 +6323,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    case (bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6052,7 +6349,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine1_row_open <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    case (bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6078,7 +6375,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine1_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    case (bankmachine1_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
                 soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
@@ -6119,7 +6416,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine1_row_close <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    case (bankmachine1_state)
         1'd1: begin
             soc_litedramcore_bankmachine1_row_close <= 1'd1;
         end
@@ -6145,7 +6442,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    case (bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6169,41 +6466,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine1_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (soc_litedramcore_bankmachine1_refresh_req) begin
-            end else begin
-                if (soc_litedramcore_bankmachine1_source_source_valid) begin
-                    if (soc_litedramcore_bankmachine1_row_opened) begin
-                        if (soc_litedramcore_bankmachine1_row_hit) begin
-                            soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 assign soc_litedramcore_bankmachine2_sink_valid = soc_litedramcore_bankmachine2_req_valid;
 assign soc_litedramcore_bankmachine2_req_ready = soc_litedramcore_bankmachine2_sink_ready;
 assign soc_litedramcore_bankmachine2_sink_payload_we = soc_litedramcore_bankmachine2_req_we;
@@ -6283,60 +6545,128 @@ assign soc_litedramcore_bankmachine2_source_source_last = soc_litedramcore_bankm
 assign soc_litedramcore_bankmachine2_source_source_payload_we = soc_litedramcore_bankmachine2_pipe_valid_source_payload_we;
 assign soc_litedramcore_bankmachine2_source_source_payload_addr = soc_litedramcore_bankmachine2_pipe_valid_source_payload_addr;
 always @(*) begin
-    litedramcore_bankmachine2_next_state <= 4'd0;
-    litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
-    case (litedramcore_bankmachine2_state)
+    bankmachine2_next_state <= 4'd0;
+    bankmachine2_next_state <= bankmachine2_state;
+    case (bankmachine2_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
                 if (soc_litedramcore_bankmachine2_cmd_ready) begin
-                    litedramcore_bankmachine2_next_state <= 3'd5;
+                    bankmachine2_next_state <= 3'd5;
                 end
             end
         end
         2'd2: begin
             if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_next_state <= 3'd5;
+                bankmachine2_next_state <= 3'd5;
             end
         end
         2'd3: begin
             if (soc_litedramcore_bankmachine2_trccon_ready) begin
                 if (soc_litedramcore_bankmachine2_cmd_ready) begin
-                    litedramcore_bankmachine2_next_state <= 3'd7;
+                    bankmachine2_next_state <= 3'd7;
                 end
             end
         end
         3'd4: begin
             if ((~soc_litedramcore_bankmachine2_refresh_req)) begin
-                litedramcore_bankmachine2_next_state <= 1'd0;
+                bankmachine2_next_state <= 1'd0;
             end
         end
         3'd5: begin
-            litedramcore_bankmachine2_next_state <= 3'd6;
+            bankmachine2_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine2_next_state <= 2'd3;
+            bankmachine2_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine2_next_state <= 4'd8;
+            bankmachine2_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine2_next_state <= 1'd0;
+            bankmachine2_next_state <= 1'd0;
         end
         default: begin
             if (soc_litedramcore_bankmachine2_refresh_req) begin
-                litedramcore_bankmachine2_next_state <= 3'd4;
+                bankmachine2_next_state <= 3'd4;
             end else begin
                 if (soc_litedramcore_bankmachine2_source_source_valid) begin
                     if (soc_litedramcore_bankmachine2_row_opened) begin
                         if (soc_litedramcore_bankmachine2_row_hit) begin
                             if ((soc_litedramcore_bankmachine2_cmd_ready & soc_litedramcore_bankmachine2_auto_precharge)) begin
-                                litedramcore_bankmachine2_next_state <= 2'd2;
+                                bankmachine2_next_state <= 2'd2;
+                            end
+                        end else begin
+                            bankmachine2_next_state <= 1'd1;
+                        end
+                    end else begin
+                        bankmachine2_next_state <= 2'd3;
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+    case (bankmachine2_state)
+        1'd1: begin
+            if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+                soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (soc_litedramcore_bankmachine2_trccon_ready) begin
+                soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+            end
+        end
+        3'd4: begin
+            soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+    case (bankmachine2_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (soc_litedramcore_bankmachine2_refresh_req) begin
+            end else begin
+                if (soc_litedramcore_bankmachine2_source_source_valid) begin
+                    if (soc_litedramcore_bankmachine2_row_opened) begin
+                        if (soc_litedramcore_bankmachine2_row_hit) begin
+                            if (soc_litedramcore_bankmachine2_source_source_payload_we) begin
+                            end else begin
+                                soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
-                            litedramcore_bankmachine2_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine2_next_state <= 2'd3;
                     end
                 end
             end
@@ -6345,7 +6675,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    case (bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6383,7 +6713,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    case (bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6421,7 +6751,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    case (bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6459,7 +6789,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    case (bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6485,7 +6815,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine2_row_open <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    case (bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6511,7 +6841,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine2_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    case (bankmachine2_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
                 soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
@@ -6552,7 +6882,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine2_row_close <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    case (bankmachine2_state)
         1'd1: begin
             soc_litedramcore_bankmachine2_row_close <= 1'd1;
         end
@@ -6578,7 +6908,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    case (bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6604,7 +6934,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    case (bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6639,7 +6969,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    case (bankmachine2_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
                 soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
@@ -6668,7 +6998,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    case (bankmachine2_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
                 soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
@@ -6707,74 +7037,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine2_state)
-        1'd1: begin
-            if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
-                soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (soc_litedramcore_bankmachine2_trccon_ready) begin
-                soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
-            end
-        end
-        3'd4: begin
-            soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine2_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (soc_litedramcore_bankmachine2_refresh_req) begin
-            end else begin
-                if (soc_litedramcore_bankmachine2_source_source_valid) begin
-                    if (soc_litedramcore_bankmachine2_row_opened) begin
-                        if (soc_litedramcore_bankmachine2_row_hit) begin
-                            if (soc_litedramcore_bankmachine2_source_source_payload_we) begin
-                            end else begin
-                                soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 assign soc_litedramcore_bankmachine3_sink_valid = soc_litedramcore_bankmachine3_req_valid;
 assign soc_litedramcore_bankmachine3_req_ready = soc_litedramcore_bankmachine3_sink_ready;
 assign soc_litedramcore_bankmachine3_sink_payload_we = soc_litedramcore_bankmachine3_req_we;
@@ -6854,60 +7116,60 @@ assign soc_litedramcore_bankmachine3_source_source_last = soc_litedramcore_bankm
 assign soc_litedramcore_bankmachine3_source_source_payload_we = soc_litedramcore_bankmachine3_pipe_valid_source_payload_we;
 assign soc_litedramcore_bankmachine3_source_source_payload_addr = soc_litedramcore_bankmachine3_pipe_valid_source_payload_addr;
 always @(*) begin
-    litedramcore_bankmachine3_next_state <= 4'd0;
-    litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
-    case (litedramcore_bankmachine3_state)
+    bankmachine3_next_state <= 4'd0;
+    bankmachine3_next_state <= bankmachine3_state;
+    case (bankmachine3_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
                 if (soc_litedramcore_bankmachine3_cmd_ready) begin
-                    litedramcore_bankmachine3_next_state <= 3'd5;
+                    bankmachine3_next_state <= 3'd5;
                 end
             end
         end
         2'd2: begin
             if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_next_state <= 3'd5;
+                bankmachine3_next_state <= 3'd5;
             end
         end
         2'd3: begin
             if (soc_litedramcore_bankmachine3_trccon_ready) begin
                 if (soc_litedramcore_bankmachine3_cmd_ready) begin
-                    litedramcore_bankmachine3_next_state <= 3'd7;
+                    bankmachine3_next_state <= 3'd7;
                 end
             end
         end
         3'd4: begin
             if ((~soc_litedramcore_bankmachine3_refresh_req)) begin
-                litedramcore_bankmachine3_next_state <= 1'd0;
+                bankmachine3_next_state <= 1'd0;
             end
         end
         3'd5: begin
-            litedramcore_bankmachine3_next_state <= 3'd6;
+            bankmachine3_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine3_next_state <= 2'd3;
+            bankmachine3_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine3_next_state <= 4'd8;
+            bankmachine3_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine3_next_state <= 1'd0;
+            bankmachine3_next_state <= 1'd0;
         end
         default: begin
             if (soc_litedramcore_bankmachine3_refresh_req) begin
-                litedramcore_bankmachine3_next_state <= 3'd4;
+                bankmachine3_next_state <= 3'd4;
             end else begin
                 if (soc_litedramcore_bankmachine3_source_source_valid) begin
                     if (soc_litedramcore_bankmachine3_row_opened) begin
                         if (soc_litedramcore_bankmachine3_row_hit) begin
                             if ((soc_litedramcore_bankmachine3_cmd_ready & soc_litedramcore_bankmachine3_auto_precharge)) begin
-                                litedramcore_bankmachine3_next_state <= 2'd2;
+                                bankmachine3_next_state <= 2'd2;
                             end
                         end else begin
-                            litedramcore_bankmachine3_next_state <= 1'd1;
+                            bankmachine3_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine3_next_state <= 2'd3;
+                        bankmachine3_next_state <= 2'd3;
                     end
                 end
             end
@@ -6915,18 +7177,56 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    soc_litedramcore_bankmachine3_row_open <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+    case (bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (soc_litedramcore_bankmachine3_trccon_ready) begin
-                soc_litedramcore_bankmachine3_row_open <= 1'd1;
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (soc_litedramcore_bankmachine3_refresh_req) begin
+            end else begin
+                if (soc_litedramcore_bankmachine3_source_source_valid) begin
+                    if (soc_litedramcore_bankmachine3_row_opened) begin
+                        if (soc_litedramcore_bankmachine3_row_hit) begin
+                            if (soc_litedramcore_bankmachine3_source_source_payload_we) begin
+                            end else begin
+                                soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
             end
         end
+    endcase
+end
+always @(*) begin
+    soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+    case (bankmachine3_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
         3'd4: begin
+            if (soc_litedramcore_bankmachine3_twtpcon_ready) begin
+                soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -6942,7 +7242,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine3_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    case (bankmachine3_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
                 soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
@@ -6983,7 +7283,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine3_row_close <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    case (bankmachine3_state)
         1'd1: begin
             soc_litedramcore_bankmachine3_row_close <= 1'd1;
         end
@@ -7008,18 +7308,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    soc_litedramcore_bankmachine3_row_open <= 1'd0;
+    case (bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (soc_litedramcore_bankmachine3_trccon_ready) begin
+                soc_litedramcore_bankmachine3_row_open <= 1'd1;
+            end
         end
         3'd4: begin
-            if (soc_litedramcore_bankmachine3_twtpcon_ready) begin
-                soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
-            end
         end
         3'd5: begin
         end
@@ -7035,7 +7335,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    case (bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7061,7 +7361,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    case (bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7096,7 +7396,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    case (bankmachine3_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
                 soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
@@ -7125,7 +7425,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    case (bankmachine3_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
                 soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
@@ -7166,7 +7466,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    case (bankmachine3_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
                 soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
@@ -7196,7 +7496,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    case (bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7234,7 +7534,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    case (bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7271,46 +7571,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    soc_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine3_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (soc_litedramcore_bankmachine3_refresh_req) begin
-            end else begin
-                if (soc_litedramcore_bankmachine3_source_source_valid) begin
-                    if (soc_litedramcore_bankmachine3_row_opened) begin
-                        if (soc_litedramcore_bankmachine3_row_hit) begin
-                            if (soc_litedramcore_bankmachine3_source_source_payload_we) begin
-                                soc_litedramcore_bankmachine3_req_wdata_ready <= soc_litedramcore_bankmachine3_cmd_ready;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
-always @(*) begin
-    soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    soc_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+    case (bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7334,8 +7596,8 @@ always @(*) begin
                     if (soc_litedramcore_bankmachine3_row_opened) begin
                         if (soc_litedramcore_bankmachine3_row_hit) begin
                             if (soc_litedramcore_bankmachine3_source_source_payload_we) begin
+                                soc_litedramcore_bankmachine3_req_wdata_ready <= soc_litedramcore_bankmachine3_cmd_ready;
                             end else begin
-                                soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready;
                             end
                         end else begin
                         end
@@ -7425,69 +7687,95 @@ assign soc_litedramcore_bankmachine4_source_source_last = soc_litedramcore_bankm
 assign soc_litedramcore_bankmachine4_source_source_payload_we = soc_litedramcore_bankmachine4_pipe_valid_source_payload_we;
 assign soc_litedramcore_bankmachine4_source_source_payload_addr = soc_litedramcore_bankmachine4_pipe_valid_source_payload_addr;
 always @(*) begin
-    litedramcore_bankmachine4_next_state <= 4'd0;
-    litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
-    case (litedramcore_bankmachine4_state)
+    bankmachine4_next_state <= 4'd0;
+    bankmachine4_next_state <= bankmachine4_state;
+    case (bankmachine4_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
                 if (soc_litedramcore_bankmachine4_cmd_ready) begin
-                    litedramcore_bankmachine4_next_state <= 3'd5;
+                    bankmachine4_next_state <= 3'd5;
                 end
             end
         end
         2'd2: begin
             if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_next_state <= 3'd5;
+                bankmachine4_next_state <= 3'd5;
             end
         end
         2'd3: begin
             if (soc_litedramcore_bankmachine4_trccon_ready) begin
                 if (soc_litedramcore_bankmachine4_cmd_ready) begin
-                    litedramcore_bankmachine4_next_state <= 3'd7;
+                    bankmachine4_next_state <= 3'd7;
                 end
             end
         end
         3'd4: begin
             if ((~soc_litedramcore_bankmachine4_refresh_req)) begin
-                litedramcore_bankmachine4_next_state <= 1'd0;
+                bankmachine4_next_state <= 1'd0;
             end
         end
         3'd5: begin
-            litedramcore_bankmachine4_next_state <= 3'd6;
+            bankmachine4_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine4_next_state <= 2'd3;
+            bankmachine4_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine4_next_state <= 4'd8;
+            bankmachine4_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine4_next_state <= 1'd0;
+            bankmachine4_next_state <= 1'd0;
         end
         default: begin
             if (soc_litedramcore_bankmachine4_refresh_req) begin
-                litedramcore_bankmachine4_next_state <= 3'd4;
+                bankmachine4_next_state <= 3'd4;
             end else begin
                 if (soc_litedramcore_bankmachine4_source_source_valid) begin
                     if (soc_litedramcore_bankmachine4_row_opened) begin
                         if (soc_litedramcore_bankmachine4_row_hit) begin
                             if ((soc_litedramcore_bankmachine4_cmd_ready & soc_litedramcore_bankmachine4_auto_precharge)) begin
-                                litedramcore_bankmachine4_next_state <= 2'd2;
+                                bankmachine4_next_state <= 2'd2;
                             end
                         end else begin
-                            litedramcore_bankmachine4_next_state <= 1'd1;
+                            bankmachine4_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine4_next_state <= 2'd3;
+                        bankmachine4_next_state <= 2'd3;
                     end
                 end
             end
         end
     endcase
 end
+always @(*) begin
+    soc_litedramcore_bankmachine4_row_close <= 1'd0;
+    case (bankmachine4_state)
+        1'd1: begin
+            soc_litedramcore_bankmachine4_row_close <= 1'd1;
+        end
+        2'd2: begin
+            soc_litedramcore_bankmachine4_row_close <= 1'd1;
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            soc_litedramcore_bankmachine4_row_close <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
 always @(*) begin
     soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    case (bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7513,7 +7801,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    case (bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7548,7 +7836,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    case (bankmachine4_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
                 soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
@@ -7577,7 +7865,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    case (bankmachine4_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
                 soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
@@ -7618,7 +7906,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    case (bankmachine4_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
                 soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
@@ -7648,7 +7936,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    case (bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7686,7 +7974,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    case (bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7724,7 +8012,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    case (bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7762,7 +8050,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    case (bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7800,7 +8088,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    case (bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7826,7 +8114,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine4_row_open <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    case (bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7852,7 +8140,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine4_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    case (bankmachine4_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
                 soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
@@ -7891,32 +8179,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    soc_litedramcore_bankmachine4_row_close <= 1'd0;
-    case (litedramcore_bankmachine4_state)
-        1'd1: begin
-            soc_litedramcore_bankmachine4_row_close <= 1'd1;
-        end
-        2'd2: begin
-            soc_litedramcore_bankmachine4_row_close <= 1'd1;
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            soc_litedramcore_bankmachine4_row_close <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
 assign soc_litedramcore_bankmachine5_sink_valid = soc_litedramcore_bankmachine5_req_valid;
 assign soc_litedramcore_bankmachine5_req_ready = soc_litedramcore_bankmachine5_sink_ready;
 assign soc_litedramcore_bankmachine5_sink_payload_we = soc_litedramcore_bankmachine5_req_we;
@@ -7996,60 +8258,95 @@ assign soc_litedramcore_bankmachine5_source_source_last = soc_litedramcore_bankm
 assign soc_litedramcore_bankmachine5_source_source_payload_we = soc_litedramcore_bankmachine5_pipe_valid_source_payload_we;
 assign soc_litedramcore_bankmachine5_source_source_payload_addr = soc_litedramcore_bankmachine5_pipe_valid_source_payload_addr;
 always @(*) begin
-    litedramcore_bankmachine5_next_state <= 4'd0;
-    litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
-    case (litedramcore_bankmachine5_state)
+    bankmachine5_next_state <= 4'd0;
+    bankmachine5_next_state <= bankmachine5_state;
+    case (bankmachine5_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
                 if (soc_litedramcore_bankmachine5_cmd_ready) begin
-                    litedramcore_bankmachine5_next_state <= 3'd5;
+                    bankmachine5_next_state <= 3'd5;
                 end
             end
         end
         2'd2: begin
             if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_next_state <= 3'd5;
+                bankmachine5_next_state <= 3'd5;
             end
         end
         2'd3: begin
             if (soc_litedramcore_bankmachine5_trccon_ready) begin
                 if (soc_litedramcore_bankmachine5_cmd_ready) begin
-                    litedramcore_bankmachine5_next_state <= 3'd7;
+                    bankmachine5_next_state <= 3'd7;
                 end
             end
         end
         3'd4: begin
             if ((~soc_litedramcore_bankmachine5_refresh_req)) begin
-                litedramcore_bankmachine5_next_state <= 1'd0;
+                bankmachine5_next_state <= 1'd0;
             end
         end
         3'd5: begin
-            litedramcore_bankmachine5_next_state <= 3'd6;
+            bankmachine5_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine5_next_state <= 2'd3;
+            bankmachine5_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine5_next_state <= 4'd8;
+            bankmachine5_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine5_next_state <= 1'd0;
+            bankmachine5_next_state <= 1'd0;
         end
         default: begin
             if (soc_litedramcore_bankmachine5_refresh_req) begin
-                litedramcore_bankmachine5_next_state <= 3'd4;
+                bankmachine5_next_state <= 3'd4;
             end else begin
                 if (soc_litedramcore_bankmachine5_source_source_valid) begin
                     if (soc_litedramcore_bankmachine5_row_opened) begin
                         if (soc_litedramcore_bankmachine5_row_hit) begin
                             if ((soc_litedramcore_bankmachine5_cmd_ready & soc_litedramcore_bankmachine5_auto_precharge)) begin
-                                litedramcore_bankmachine5_next_state <= 2'd2;
+                                bankmachine5_next_state <= 2'd2;
                             end
                         end else begin
-                            litedramcore_bankmachine5_next_state <= 1'd1;
+                            bankmachine5_next_state <= 1'd1;
+                        end
+                    end else begin
+                        bankmachine5_next_state <= 2'd3;
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+    case (bankmachine5_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (soc_litedramcore_bankmachine5_refresh_req) begin
+            end else begin
+                if (soc_litedramcore_bankmachine5_source_source_valid) begin
+                    if (soc_litedramcore_bankmachine5_row_opened) begin
+                        if (soc_litedramcore_bankmachine5_row_hit) begin
+                            soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+                        end else begin
                         end
                     end else begin
-                        litedramcore_bankmachine5_next_state <= 2'd3;
                     end
                 end
             end
@@ -8058,7 +8355,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    case (bankmachine5_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
                 soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
@@ -8087,7 +8384,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    case (bankmachine5_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
                 soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
@@ -8128,7 +8425,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    case (bankmachine5_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
                 soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
@@ -8158,7 +8455,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    case (bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8196,7 +8493,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    case (bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8234,7 +8531,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    case (bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8272,7 +8569,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    case (bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8310,7 +8607,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    case (bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8336,7 +8633,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine5_row_open <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    case (bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8362,7 +8659,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine5_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    case (bankmachine5_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
                 soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
@@ -8403,7 +8700,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine5_row_close <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    case (bankmachine5_state)
         1'd1: begin
             soc_litedramcore_bankmachine5_row_close <= 1'd1;
         end
@@ -8429,7 +8726,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    case (bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8453,41 +8750,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine5_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (soc_litedramcore_bankmachine5_refresh_req) begin
-            end else begin
-                if (soc_litedramcore_bankmachine5_source_source_valid) begin
-                    if (soc_litedramcore_bankmachine5_row_opened) begin
-                        if (soc_litedramcore_bankmachine5_row_hit) begin
-                            soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 assign soc_litedramcore_bankmachine6_sink_valid = soc_litedramcore_bankmachine6_req_valid;
 assign soc_litedramcore_bankmachine6_req_ready = soc_litedramcore_bankmachine6_sink_ready;
 assign soc_litedramcore_bankmachine6_sink_payload_we = soc_litedramcore_bankmachine6_req_we;
@@ -8567,60 +8829,128 @@ assign soc_litedramcore_bankmachine6_source_source_last = soc_litedramcore_bankm
 assign soc_litedramcore_bankmachine6_source_source_payload_we = soc_litedramcore_bankmachine6_pipe_valid_source_payload_we;
 assign soc_litedramcore_bankmachine6_source_source_payload_addr = soc_litedramcore_bankmachine6_pipe_valid_source_payload_addr;
 always @(*) begin
-    litedramcore_bankmachine6_next_state <= 4'd0;
-    litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
-    case (litedramcore_bankmachine6_state)
+    bankmachine6_next_state <= 4'd0;
+    bankmachine6_next_state <= bankmachine6_state;
+    case (bankmachine6_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
                 if (soc_litedramcore_bankmachine6_cmd_ready) begin
-                    litedramcore_bankmachine6_next_state <= 3'd5;
+                    bankmachine6_next_state <= 3'd5;
                 end
             end
         end
         2'd2: begin
             if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_next_state <= 3'd5;
+                bankmachine6_next_state <= 3'd5;
             end
         end
         2'd3: begin
             if (soc_litedramcore_bankmachine6_trccon_ready) begin
                 if (soc_litedramcore_bankmachine6_cmd_ready) begin
-                    litedramcore_bankmachine6_next_state <= 3'd7;
+                    bankmachine6_next_state <= 3'd7;
                 end
             end
         end
         3'd4: begin
             if ((~soc_litedramcore_bankmachine6_refresh_req)) begin
-                litedramcore_bankmachine6_next_state <= 1'd0;
+                bankmachine6_next_state <= 1'd0;
             end
         end
         3'd5: begin
-            litedramcore_bankmachine6_next_state <= 3'd6;
+            bankmachine6_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine6_next_state <= 2'd3;
+            bankmachine6_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine6_next_state <= 4'd8;
+            bankmachine6_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine6_next_state <= 1'd0;
+            bankmachine6_next_state <= 1'd0;
         end
         default: begin
             if (soc_litedramcore_bankmachine6_refresh_req) begin
-                litedramcore_bankmachine6_next_state <= 3'd4;
+                bankmachine6_next_state <= 3'd4;
             end else begin
                 if (soc_litedramcore_bankmachine6_source_source_valid) begin
                     if (soc_litedramcore_bankmachine6_row_opened) begin
                         if (soc_litedramcore_bankmachine6_row_hit) begin
                             if ((soc_litedramcore_bankmachine6_cmd_ready & soc_litedramcore_bankmachine6_auto_precharge)) begin
-                                litedramcore_bankmachine6_next_state <= 2'd2;
+                                bankmachine6_next_state <= 2'd2;
+                            end
+                        end else begin
+                            bankmachine6_next_state <= 1'd1;
+                        end
+                    end else begin
+                        bankmachine6_next_state <= 2'd3;
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+    case (bankmachine6_state)
+        1'd1: begin
+            if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+                soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (soc_litedramcore_bankmachine6_trccon_ready) begin
+                soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+            end
+        end
+        3'd4: begin
+            soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+    case (bankmachine6_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (soc_litedramcore_bankmachine6_refresh_req) begin
+            end else begin
+                if (soc_litedramcore_bankmachine6_source_source_valid) begin
+                    if (soc_litedramcore_bankmachine6_row_opened) begin
+                        if (soc_litedramcore_bankmachine6_row_hit) begin
+                            if (soc_litedramcore_bankmachine6_source_source_payload_we) begin
+                            end else begin
+                                soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
-                            litedramcore_bankmachine6_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine6_next_state <= 2'd3;
                     end
                 end
             end
@@ -8629,7 +8959,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    case (bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8667,7 +8997,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    case (bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8705,7 +9035,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    case (bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8743,7 +9073,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    case (bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8769,7 +9099,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine6_row_open <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    case (bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8795,7 +9125,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine6_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    case (bankmachine6_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
                 soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
@@ -8836,7 +9166,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine6_row_close <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    case (bankmachine6_state)
         1'd1: begin
             soc_litedramcore_bankmachine6_row_close <= 1'd1;
         end
@@ -8862,7 +9192,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    case (bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8888,7 +9218,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    case (bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8922,92 +9252,21 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine6_state)
-        1'd1: begin
-            if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
-                soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (soc_litedramcore_bankmachine6_trccon_ready) begin
-                soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine6_state)
-        1'd1: begin
-            if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
-                soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (soc_litedramcore_bankmachine6_refresh_req) begin
-            end else begin
-                if (soc_litedramcore_bankmachine6_source_source_valid) begin
-                    if (soc_litedramcore_bankmachine6_row_opened) begin
-                        if (soc_litedramcore_bankmachine6_row_hit) begin
-                            if (soc_litedramcore_bankmachine6_source_source_payload_we) begin
-                                soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
-always @(*) begin
-    soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+    case (bankmachine6_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
-                soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+                soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
             if (soc_litedramcore_bankmachine6_trccon_ready) begin
-                soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+                soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
-            soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -9022,9 +9281,12 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+    case (bankmachine6_state)
         1'd1: begin
+            if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+                soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+            end
         end
         2'd2: begin
         end
@@ -9047,8 +9309,8 @@ always @(*) begin
                     if (soc_litedramcore_bankmachine6_row_opened) begin
                         if (soc_litedramcore_bankmachine6_row_hit) begin
                             if (soc_litedramcore_bankmachine6_source_source_payload_we) begin
+                                soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
                             end else begin
-                                soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -9138,60 +9400,60 @@ assign soc_litedramcore_bankmachine7_source_source_last = soc_litedramcore_bankm
 assign soc_litedramcore_bankmachine7_source_source_payload_we = soc_litedramcore_bankmachine7_pipe_valid_source_payload_we;
 assign soc_litedramcore_bankmachine7_source_source_payload_addr = soc_litedramcore_bankmachine7_pipe_valid_source_payload_addr;
 always @(*) begin
-    litedramcore_bankmachine7_next_state <= 4'd0;
-    litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
-    case (litedramcore_bankmachine7_state)
+    bankmachine7_next_state <= 4'd0;
+    bankmachine7_next_state <= bankmachine7_state;
+    case (bankmachine7_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
                 if (soc_litedramcore_bankmachine7_cmd_ready) begin
-                    litedramcore_bankmachine7_next_state <= 3'd5;
+                    bankmachine7_next_state <= 3'd5;
                 end
             end
         end
         2'd2: begin
             if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_next_state <= 3'd5;
+                bankmachine7_next_state <= 3'd5;
             end
         end
         2'd3: begin
             if (soc_litedramcore_bankmachine7_trccon_ready) begin
                 if (soc_litedramcore_bankmachine7_cmd_ready) begin
-                    litedramcore_bankmachine7_next_state <= 3'd7;
+                    bankmachine7_next_state <= 3'd7;
                 end
             end
         end
         3'd4: begin
             if ((~soc_litedramcore_bankmachine7_refresh_req)) begin
-                litedramcore_bankmachine7_next_state <= 1'd0;
+                bankmachine7_next_state <= 1'd0;
             end
         end
         3'd5: begin
-            litedramcore_bankmachine7_next_state <= 3'd6;
+            bankmachine7_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine7_next_state <= 2'd3;
+            bankmachine7_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine7_next_state <= 4'd8;
+            bankmachine7_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine7_next_state <= 1'd0;
+            bankmachine7_next_state <= 1'd0;
         end
         default: begin
             if (soc_litedramcore_bankmachine7_refresh_req) begin
-                litedramcore_bankmachine7_next_state <= 3'd4;
+                bankmachine7_next_state <= 3'd4;
             end else begin
                 if (soc_litedramcore_bankmachine7_source_source_valid) begin
                     if (soc_litedramcore_bankmachine7_row_opened) begin
                         if (soc_litedramcore_bankmachine7_row_hit) begin
                             if ((soc_litedramcore_bankmachine7_cmd_ready & soc_litedramcore_bankmachine7_auto_precharge)) begin
-                                litedramcore_bankmachine7_next_state <= 2'd2;
+                                bankmachine7_next_state <= 2'd2;
                             end
                         end else begin
-                            litedramcore_bankmachine7_next_state <= 1'd1;
+                            bankmachine7_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine7_next_state <= 2'd3;
+                        bankmachine7_next_state <= 2'd3;
                     end
                 end
             end
@@ -9199,18 +9461,56 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    soc_litedramcore_bankmachine7_row_open <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+    case (bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (soc_litedramcore_bankmachine7_trccon_ready) begin
-                soc_litedramcore_bankmachine7_row_open <= 1'd1;
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (soc_litedramcore_bankmachine7_refresh_req) begin
+            end else begin
+                if (soc_litedramcore_bankmachine7_source_source_valid) begin
+                    if (soc_litedramcore_bankmachine7_row_opened) begin
+                        if (soc_litedramcore_bankmachine7_row_hit) begin
+                            if (soc_litedramcore_bankmachine7_source_source_payload_we) begin
+                            end else begin
+                                soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
             end
         end
+    endcase
+end
+always @(*) begin
+    soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+    case (bankmachine7_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
         3'd4: begin
+            if (soc_litedramcore_bankmachine7_twtpcon_ready) begin
+                soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -9226,7 +9526,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine7_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    case (bankmachine7_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
                 soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
@@ -9267,7 +9567,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine7_row_close <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    case (bankmachine7_state)
         1'd1: begin
             soc_litedramcore_bankmachine7_row_close <= 1'd1;
         end
@@ -9292,18 +9592,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    soc_litedramcore_bankmachine7_row_open <= 1'd0;
+    case (bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (soc_litedramcore_bankmachine7_trccon_ready) begin
+                soc_litedramcore_bankmachine7_row_open <= 1'd1;
+            end
         end
         3'd4: begin
-            if (soc_litedramcore_bankmachine7_twtpcon_ready) begin
-                soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
-            end
         end
         3'd5: begin
         end
@@ -9319,7 +9619,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    case (bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9345,7 +9645,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    case (bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9380,7 +9680,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    case (bankmachine7_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
                 soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
@@ -9409,7 +9709,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    case (bankmachine7_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
                 soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
@@ -9450,7 +9750,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    case (bankmachine7_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
                 soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
@@ -9480,7 +9780,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    case (bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9518,7 +9818,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    case (bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9556,7 +9856,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    case (bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9592,44 +9892,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine7_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (soc_litedramcore_bankmachine7_refresh_req) begin
-            end else begin
-                if (soc_litedramcore_bankmachine7_source_source_valid) begin
-                    if (soc_litedramcore_bankmachine7_row_opened) begin
-                        if (soc_litedramcore_bankmachine7_row_hit) begin
-                            if (soc_litedramcore_bankmachine7_source_source_payload_we) begin
-                            end else begin
-                                soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 assign soc_litedramcore_trrdcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we)));
 assign soc_litedramcore_tfawcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we)));
 assign soc_litedramcore_ras_allowed = (soc_litedramcore_trrdcon_ready & soc_litedramcore_tfawcon_ready);
@@ -9670,28 +9932,28 @@ always @(*) begin
     soc_litedramcore_choose_cmd_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
 end
 assign soc_litedramcore_choose_cmd_request = soc_litedramcore_choose_cmd_valids;
-assign soc_litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
-assign soc_litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1;
-assign soc_litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
-assign soc_litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
-assign soc_litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
-assign soc_litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
+assign soc_litedramcore_choose_cmd_cmd_valid = rhs_self0;
+assign soc_litedramcore_choose_cmd_cmd_payload_a = rhs_self1;
+assign soc_litedramcore_choose_cmd_cmd_payload_ba = rhs_self2;
+assign soc_litedramcore_choose_cmd_cmd_payload_is_read = rhs_self3;
+assign soc_litedramcore_choose_cmd_cmd_payload_is_write = rhs_self4;
+assign soc_litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_self5;
 always @(*) begin
     soc_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
     if (soc_litedramcore_choose_cmd_cmd_valid) begin
-        soc_litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
+        soc_litedramcore_choose_cmd_cmd_payload_cas <= t_self0;
     end
 end
 always @(*) begin
     soc_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
     if (soc_litedramcore_choose_cmd_cmd_valid) begin
-        soc_litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
+        soc_litedramcore_choose_cmd_cmd_payload_ras <= t_self1;
     end
 end
 always @(*) begin
     soc_litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
     if (soc_litedramcore_choose_cmd_cmd_valid) begin
-        soc_litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
+        soc_litedramcore_choose_cmd_cmd_payload_we <= t_self2;
     end
 end
 always @(*) begin
@@ -9779,104 +10041,104 @@ always @(*) begin
     soc_litedramcore_choose_req_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
 end
 assign soc_litedramcore_choose_req_request = soc_litedramcore_choose_req_valids;
-assign soc_litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
-assign soc_litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7;
-assign soc_litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8;
-assign soc_litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9;
-assign soc_litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
-assign soc_litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
+assign soc_litedramcore_choose_req_cmd_valid = rhs_self6;
+assign soc_litedramcore_choose_req_cmd_payload_a = rhs_self7;
+assign soc_litedramcore_choose_req_cmd_payload_ba = rhs_self8;
+assign soc_litedramcore_choose_req_cmd_payload_is_read = rhs_self9;
+assign soc_litedramcore_choose_req_cmd_payload_is_write = rhs_self10;
+assign soc_litedramcore_choose_req_cmd_payload_is_cmd = rhs_self11;
 always @(*) begin
     soc_litedramcore_choose_req_cmd_payload_cas <= 1'd0;
     if (soc_litedramcore_choose_req_cmd_valid) begin
-        soc_litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
+        soc_litedramcore_choose_req_cmd_payload_cas <= t_self3;
     end
 end
 always @(*) begin
     soc_litedramcore_choose_req_cmd_payload_ras <= 1'd0;
     if (soc_litedramcore_choose_req_cmd_valid) begin
-        soc_litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
+        soc_litedramcore_choose_req_cmd_payload_ras <= t_self4;
     end
 end
 always @(*) begin
     soc_litedramcore_choose_req_cmd_payload_we <= 1'd0;
     if (soc_litedramcore_choose_req_cmd_valid) begin
-        soc_litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
+        soc_litedramcore_choose_req_cmd_payload_we <= t_self5;
     end
 end
 assign soc_litedramcore_choose_req_ce = (soc_litedramcore_choose_req_cmd_ready | (~soc_litedramcore_choose_req_cmd_valid));
 assign soc_litedramcore_dfi_p0_reset_n = 1'd1;
-assign soc_litedramcore_dfi_p0_cke = {1{soc_litedramcore_steerer0}};
-assign soc_litedramcore_dfi_p0_odt = {1{soc_litedramcore_steerer1}};
+assign soc_litedramcore_dfi_p0_cke = {1{soc_litedramcore_steerer4}};
+assign soc_litedramcore_dfi_p0_odt = {1{soc_litedramcore_steerer5}};
 assign soc_litedramcore_dfi_p1_reset_n = 1'd1;
-assign soc_litedramcore_dfi_p1_cke = {1{soc_litedramcore_steerer2}};
-assign soc_litedramcore_dfi_p1_odt = {1{soc_litedramcore_steerer3}};
+assign soc_litedramcore_dfi_p1_cke = {1{soc_litedramcore_steerer6}};
+assign soc_litedramcore_dfi_p1_odt = {1{soc_litedramcore_steerer7}};
 assign soc_litedramcore_dfi_p2_reset_n = 1'd1;
-assign soc_litedramcore_dfi_p2_cke = {1{soc_litedramcore_steerer4}};
-assign soc_litedramcore_dfi_p2_odt = {1{soc_litedramcore_steerer5}};
+assign soc_litedramcore_dfi_p2_cke = {1{soc_litedramcore_steerer8}};
+assign soc_litedramcore_dfi_p2_odt = {1{soc_litedramcore_steerer9}};
 assign soc_litedramcore_dfi_p3_reset_n = 1'd1;
-assign soc_litedramcore_dfi_p3_cke = {1{soc_litedramcore_steerer6}};
-assign soc_litedramcore_dfi_p3_odt = {1{soc_litedramcore_steerer7}};
+assign soc_litedramcore_dfi_p3_cke = {1{soc_litedramcore_steerer10}};
+assign soc_litedramcore_dfi_p3_odt = {1{soc_litedramcore_steerer11}};
 assign soc_litedramcore_tfawcon_count = ((((soc_litedramcore_tfawcon_window[0] + soc_litedramcore_tfawcon_window[1]) + soc_litedramcore_tfawcon_window[2]) + soc_litedramcore_tfawcon_window[3]) + soc_litedramcore_tfawcon_window[4]);
 always @(*) begin
-    litedramcore_multiplexer_next_state <= 4'd0;
-    litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
-    case (litedramcore_multiplexer_state)
+    multiplexer_next_state <= 4'd0;
+    multiplexer_next_state <= multiplexer_state;
+    case (multiplexer_state)
         1'd1: begin
             if (soc_litedramcore_read_available) begin
                 if (((~soc_litedramcore_write_available) | soc_litedramcore_max_time1)) begin
-                    litedramcore_multiplexer_next_state <= 2'd3;
+                    multiplexer_next_state <= 2'd3;
                 end
             end
             if (soc_litedramcore_go_to_refresh) begin
-                litedramcore_multiplexer_next_state <= 2'd2;
+                multiplexer_next_state <= 2'd2;
             end
         end
         2'd2: begin
             if (soc_litedramcore_cmd_last) begin
-                litedramcore_multiplexer_next_state <= 1'd0;
+                multiplexer_next_state <= 1'd0;
             end
         end
         2'd3: begin
             if (soc_litedramcore_twtrcon_ready) begin
-                litedramcore_multiplexer_next_state <= 1'd0;
+                multiplexer_next_state <= 1'd0;
             end
         end
         3'd4: begin
-            litedramcore_multiplexer_next_state <= 3'd5;
+            multiplexer_next_state <= 3'd5;
         end
         3'd5: begin
-            litedramcore_multiplexer_next_state <= 3'd6;
+            multiplexer_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_multiplexer_next_state <= 3'd7;
+            multiplexer_next_state <= 3'd7;
         end
         3'd7: begin
-            litedramcore_multiplexer_next_state <= 4'd8;
+            multiplexer_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_multiplexer_next_state <= 4'd9;
+            multiplexer_next_state <= 4'd9;
         end
         4'd9: begin
-            litedramcore_multiplexer_next_state <= 4'd10;
+            multiplexer_next_state <= 4'd10;
         end
         4'd10: begin
-            litedramcore_multiplexer_next_state <= 1'd1;
+            multiplexer_next_state <= 1'd1;
         end
         default: begin
             if (soc_litedramcore_write_available) begin
                 if (((~soc_litedramcore_read_available) | soc_litedramcore_max_time0)) begin
-                    litedramcore_multiplexer_next_state <= 3'd4;
+                    multiplexer_next_state <= 3'd4;
                 end
             end
             if (soc_litedramcore_go_to_refresh) begin
-                litedramcore_multiplexer_next_state <= 2'd2;
+                multiplexer_next_state <= 2'd2;
             end
         end
     endcase
 end
 always @(*) begin
     soc_litedramcore_choose_req_cmd_ready <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    case (multiplexer_state)
         1'd1: begin
             if (1'd0) begin
                 soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
@@ -9913,7 +10175,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_en1 <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    case (multiplexer_state)
         1'd1: begin
             soc_litedramcore_en1 <= 1'd1;
         end
@@ -9940,19 +10202,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    soc_litedramcore_steerer_sel0 <= 2'd0;
-    case (litedramcore_multiplexer_state)
+    soc_litedramcore_steerer3 <= 2'd0;
+    case (multiplexer_state)
         1'd1: begin
-            soc_litedramcore_steerer_sel0 <= 1'd0;
-            if (1'd0) begin
-                soc_litedramcore_steerer_sel0 <= 2'd2;
+            soc_litedramcore_steerer3 <= 1'd0;
+            if (1'd1) begin
+                soc_litedramcore_steerer3 <= 2'd2;
             end
             if (1'd0) begin
-                soc_litedramcore_steerer_sel0 <= 1'd1;
+                soc_litedramcore_steerer3 <= 1'd1;
             end
         end
         2'd2: begin
-            soc_litedramcore_steerer_sel0 <= 2'd3;
         end
         2'd3: begin
         end
@@ -9971,29 +10232,30 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            soc_litedramcore_steerer_sel0 <= 1'd0;
+            soc_litedramcore_steerer3 <= 1'd0;
             if (1'd0) begin
-                soc_litedramcore_steerer_sel0 <= 2'd2;
+                soc_litedramcore_steerer3 <= 2'd2;
             end
             if (1'd0) begin
-                soc_litedramcore_steerer_sel0 <= 1'd1;
+                soc_litedramcore_steerer3 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    soc_litedramcore_steerer_sel1 <= 2'd0;
-    case (litedramcore_multiplexer_state)
+    soc_litedramcore_steerer0 <= 2'd0;
+    case (multiplexer_state)
         1'd1: begin
-            soc_litedramcore_steerer_sel1 <= 1'd0;
+            soc_litedramcore_steerer0 <= 1'd0;
             if (1'd0) begin
-                soc_litedramcore_steerer_sel1 <= 2'd2;
+                soc_litedramcore_steerer0 <= 2'd2;
             end
             if (1'd0) begin
-                soc_litedramcore_steerer_sel1 <= 1'd1;
+                soc_litedramcore_steerer0 <= 1'd1;
             end
         end
         2'd2: begin
+            soc_litedramcore_steerer0 <= 2'd3;
         end
         2'd3: begin
         end
@@ -10012,26 +10274,26 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            soc_litedramcore_steerer_sel1 <= 1'd0;
+            soc_litedramcore_steerer0 <= 1'd0;
             if (1'd0) begin
-                soc_litedramcore_steerer_sel1 <= 2'd2;
+                soc_litedramcore_steerer0 <= 2'd2;
             end
-            if (1'd1) begin
-                soc_litedramcore_steerer_sel1 <= 1'd1;
+            if (1'd0) begin
+                soc_litedramcore_steerer0 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    soc_litedramcore_steerer_sel2 <= 2'd0;
-    case (litedramcore_multiplexer_state)
+    soc_litedramcore_steerer1 <= 2'd0;
+    case (multiplexer_state)
         1'd1: begin
-            soc_litedramcore_steerer_sel2 <= 1'd0;
+            soc_litedramcore_steerer1 <= 1'd0;
             if (1'd0) begin
-                soc_litedramcore_steerer_sel2 <= 2'd2;
+                soc_litedramcore_steerer1 <= 2'd2;
             end
-            if (1'd1) begin
-                soc_litedramcore_steerer_sel2 <= 1'd1;
+            if (1'd0) begin
+                soc_litedramcore_steerer1 <= 1'd1;
             end
         end
         2'd2: begin
@@ -10053,23 +10315,26 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            soc_litedramcore_steerer_sel2 <= 1'd0;
-            if (1'd1) begin
-                soc_litedramcore_steerer_sel2 <= 2'd2;
-            end
+            soc_litedramcore_steerer1 <= 1'd0;
             if (1'd0) begin
-                soc_litedramcore_steerer_sel2 <= 1'd1;
+                soc_litedramcore_steerer1 <= 2'd2;
+            end
+            if (1'd1) begin
+                soc_litedramcore_steerer1 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    soc_litedramcore_choose_cmd_want_activates <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    soc_litedramcore_steerer2 <= 2'd0;
+    case (multiplexer_state)
         1'd1: begin
+            soc_litedramcore_steerer2 <= 1'd0;
             if (1'd0) begin
-            end else begin
-                soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed;
+                soc_litedramcore_steerer2 <= 2'd2;
+            end
+            if (1'd1) begin
+                soc_litedramcore_steerer2 <= 1'd1;
             end
         end
         2'd2: begin
@@ -10091,23 +10356,23 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
+            soc_litedramcore_steerer2 <= 1'd0;
+            if (1'd1) begin
+                soc_litedramcore_steerer2 <= 2'd2;
+            end
             if (1'd0) begin
-            end else begin
-                soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed;
+                soc_litedramcore_steerer2 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    soc_litedramcore_steerer_sel3 <= 2'd0;
-    case (litedramcore_multiplexer_state)
+    soc_litedramcore_choose_cmd_want_activates <= 1'd0;
+    case (multiplexer_state)
         1'd1: begin
-            soc_litedramcore_steerer_sel3 <= 1'd0;
-            if (1'd1) begin
-                soc_litedramcore_steerer_sel3 <= 2'd2;
-            end
             if (1'd0) begin
-                soc_litedramcore_steerer_sel3 <= 1'd1;
+            end else begin
+                soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed;
             end
         end
         2'd2: begin
@@ -10129,19 +10394,16 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            soc_litedramcore_steerer_sel3 <= 1'd0;
-            if (1'd0) begin
-                soc_litedramcore_steerer_sel3 <= 2'd2;
-            end
             if (1'd0) begin
-                soc_litedramcore_steerer_sel3 <= 1'd1;
+            end else begin
+                soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed;
             end
         end
     endcase
 end
 always @(*) begin
     soc_litedramcore_en0 <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    case (multiplexer_state)
         1'd1: begin
         end
         2'd2: begin
@@ -10169,7 +10431,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_cmd_ready <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    case (multiplexer_state)
         1'd1: begin
         end
         2'd2: begin
@@ -10197,7 +10459,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_choose_cmd_cmd_ready <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    case (multiplexer_state)
         1'd1: begin
             if (1'd0) begin
             end else begin
@@ -10232,7 +10494,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_choose_req_want_reads <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    case (multiplexer_state)
         1'd1: begin
         end
         2'd2: begin
@@ -10260,7 +10522,7 @@ always @(*) begin
 end
 always @(*) begin
     soc_litedramcore_choose_req_want_writes <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    case (multiplexer_state)
         1'd1: begin
             soc_litedramcore_choose_req_want_writes <= 1'd1;
         end
@@ -10286,216 +10548,205 @@ always @(*) begin
         end
     endcase
 end
-assign litedramcore_roundrobin0_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
-assign litedramcore_roundrobin0_ce = ((~soc_litedramcore_interface_bank0_valid) & (~soc_litedramcore_interface_bank0_lock));
-assign soc_litedramcore_interface_bank0_addr = rhs_array_muxed12;
-assign soc_litedramcore_interface_bank0_we = rhs_array_muxed13;
-assign soc_litedramcore_interface_bank0_valid = rhs_array_muxed14;
-assign litedramcore_roundrobin1_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
-assign litedramcore_roundrobin1_ce = ((~soc_litedramcore_interface_bank1_valid) & (~soc_litedramcore_interface_bank1_lock));
-assign soc_litedramcore_interface_bank1_addr = rhs_array_muxed15;
-assign soc_litedramcore_interface_bank1_we = rhs_array_muxed16;
-assign soc_litedramcore_interface_bank1_valid = rhs_array_muxed17;
-assign litedramcore_roundrobin2_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
-assign litedramcore_roundrobin2_ce = ((~soc_litedramcore_interface_bank2_valid) & (~soc_litedramcore_interface_bank2_lock));
-assign soc_litedramcore_interface_bank2_addr = rhs_array_muxed18;
-assign soc_litedramcore_interface_bank2_we = rhs_array_muxed19;
-assign soc_litedramcore_interface_bank2_valid = rhs_array_muxed20;
-assign litedramcore_roundrobin3_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
-assign litedramcore_roundrobin3_ce = ((~soc_litedramcore_interface_bank3_valid) & (~soc_litedramcore_interface_bank3_lock));
-assign soc_litedramcore_interface_bank3_addr = rhs_array_muxed21;
-assign soc_litedramcore_interface_bank3_we = rhs_array_muxed22;
-assign soc_litedramcore_interface_bank3_valid = rhs_array_muxed23;
-assign litedramcore_roundrobin4_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
-assign litedramcore_roundrobin4_ce = ((~soc_litedramcore_interface_bank4_valid) & (~soc_litedramcore_interface_bank4_lock));
-assign soc_litedramcore_interface_bank4_addr = rhs_array_muxed24;
-assign soc_litedramcore_interface_bank4_we = rhs_array_muxed25;
-assign soc_litedramcore_interface_bank4_valid = rhs_array_muxed26;
-assign litedramcore_roundrobin5_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
-assign litedramcore_roundrobin5_ce = ((~soc_litedramcore_interface_bank5_valid) & (~soc_litedramcore_interface_bank5_lock));
-assign soc_litedramcore_interface_bank5_addr = rhs_array_muxed27;
-assign soc_litedramcore_interface_bank5_we = rhs_array_muxed28;
-assign soc_litedramcore_interface_bank5_valid = rhs_array_muxed29;
-assign litedramcore_roundrobin6_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
-assign litedramcore_roundrobin6_ce = ((~soc_litedramcore_interface_bank6_valid) & (~soc_litedramcore_interface_bank6_lock));
-assign soc_litedramcore_interface_bank6_addr = rhs_array_muxed30;
-assign soc_litedramcore_interface_bank6_we = rhs_array_muxed31;
-assign soc_litedramcore_interface_bank6_valid = rhs_array_muxed32;
-assign litedramcore_roundrobin7_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid)};
-assign litedramcore_roundrobin7_ce = ((~soc_litedramcore_interface_bank7_valid) & (~soc_litedramcore_interface_bank7_lock));
-assign soc_litedramcore_interface_bank7_addr = rhs_array_muxed33;
-assign soc_litedramcore_interface_bank7_we = rhs_array_muxed34;
-assign soc_litedramcore_interface_bank7_valid = rhs_array_muxed35;
-assign soc_user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & soc_litedramcore_interface_bank7_ready));
-assign soc_user_port_wdata_ready = litedramcore_new_master_wdata_ready1;
-assign soc_user_port_rdata_valid = litedramcore_new_master_rdata_valid8;
+assign roundrobin0_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign roundrobin0_ce = ((~soc_litedramcore_interface_bank0_valid) & (~soc_litedramcore_interface_bank0_lock));
+assign soc_litedramcore_interface_bank0_addr = rhs_self12;
+assign soc_litedramcore_interface_bank0_we = rhs_self13;
+assign soc_litedramcore_interface_bank0_valid = rhs_self14;
+assign roundrobin1_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign roundrobin1_ce = ((~soc_litedramcore_interface_bank1_valid) & (~soc_litedramcore_interface_bank1_lock));
+assign soc_litedramcore_interface_bank1_addr = rhs_self15;
+assign soc_litedramcore_interface_bank1_we = rhs_self16;
+assign soc_litedramcore_interface_bank1_valid = rhs_self17;
+assign roundrobin2_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign roundrobin2_ce = ((~soc_litedramcore_interface_bank2_valid) & (~soc_litedramcore_interface_bank2_lock));
+assign soc_litedramcore_interface_bank2_addr = rhs_self18;
+assign soc_litedramcore_interface_bank2_we = rhs_self19;
+assign soc_litedramcore_interface_bank2_valid = rhs_self20;
+assign roundrobin3_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign roundrobin3_ce = ((~soc_litedramcore_interface_bank3_valid) & (~soc_litedramcore_interface_bank3_lock));
+assign soc_litedramcore_interface_bank3_addr = rhs_self21;
+assign soc_litedramcore_interface_bank3_we = rhs_self22;
+assign soc_litedramcore_interface_bank3_valid = rhs_self23;
+assign roundrobin4_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign roundrobin4_ce = ((~soc_litedramcore_interface_bank4_valid) & (~soc_litedramcore_interface_bank4_lock));
+assign soc_litedramcore_interface_bank4_addr = rhs_self24;
+assign soc_litedramcore_interface_bank4_we = rhs_self25;
+assign soc_litedramcore_interface_bank4_valid = rhs_self26;
+assign roundrobin5_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign roundrobin5_ce = ((~soc_litedramcore_interface_bank5_valid) & (~soc_litedramcore_interface_bank5_lock));
+assign soc_litedramcore_interface_bank5_addr = rhs_self27;
+assign soc_litedramcore_interface_bank5_we = rhs_self28;
+assign soc_litedramcore_interface_bank5_valid = rhs_self29;
+assign roundrobin6_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign roundrobin6_ce = ((~soc_litedramcore_interface_bank6_valid) & (~soc_litedramcore_interface_bank6_lock));
+assign soc_litedramcore_interface_bank6_addr = rhs_self30;
+assign soc_litedramcore_interface_bank6_we = rhs_self31;
+assign soc_litedramcore_interface_bank6_valid = rhs_self32;
+assign roundrobin7_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign roundrobin7_ce = ((~soc_litedramcore_interface_bank7_valid) & (~soc_litedramcore_interface_bank7_lock));
+assign soc_litedramcore_interface_bank7_addr = rhs_self33;
+assign soc_litedramcore_interface_bank7_we = rhs_self34;
+assign soc_litedramcore_interface_bank7_valid = rhs_self35;
+assign soc_user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank0_ready)) | (((roundrobin1_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank1_ready)) | (((roundrobin2_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank2_ready)) | (((roundrobin3_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank3_ready)) | (((roundrobin4_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank4_ready)) | (((roundrobin5_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank5_ready)) | (((roundrobin6_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank6_ready)) | (((roundrobin7_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0)))))) & soc_litedramcore_interface_bank7_ready));
+assign soc_user_port_wdata_ready = new_master_wdata_ready1;
+assign soc_user_port_rdata_valid = new_master_rdata_valid8;
 always @(*) begin
-    soc_litedramcore_interface_wdata <= 128'd0;
-    case ({litedramcore_new_master_wdata_ready1})
+    soc_litedramcore_interface_wdata_we <= 16'd0;
+    case ({new_master_wdata_ready1})
         1'd1: begin
-            soc_litedramcore_interface_wdata <= soc_user_port_wdata_payload_data;
+            soc_litedramcore_interface_wdata_we <= soc_user_port_wdata_payload_we;
         end
         default: begin
-            soc_litedramcore_interface_wdata <= 1'd0;
+            soc_litedramcore_interface_wdata_we <= 1'd0;
         end
     endcase
 end
 always @(*) begin
-    soc_litedramcore_interface_wdata_we <= 16'd0;
-    case ({litedramcore_new_master_wdata_ready1})
+    soc_litedramcore_interface_wdata <= 128'd0;
+    case ({new_master_wdata_ready1})
         1'd1: begin
-            soc_litedramcore_interface_wdata_we <= soc_user_port_wdata_payload_we;
+            soc_litedramcore_interface_wdata <= soc_user_port_wdata_payload_data;
         end
         default: begin
-            soc_litedramcore_interface_wdata_we <= 1'd0;
+            soc_litedramcore_interface_wdata <= 1'd0;
         end
     endcase
 end
 assign soc_user_port_rdata_payload_data = soc_litedramcore_interface_rdata;
-assign litedramcore_roundrobin0_grant = 1'd0;
-assign litedramcore_roundrobin1_grant = 1'd0;
-assign litedramcore_roundrobin2_grant = 1'd0;
-assign litedramcore_roundrobin3_grant = 1'd0;
-assign litedramcore_roundrobin4_grant = 1'd0;
-assign litedramcore_roundrobin5_grant = 1'd0;
-assign litedramcore_roundrobin6_grant = 1'd0;
-assign litedramcore_roundrobin7_grant = 1'd0;
+assign roundrobin0_grant = 1'd0;
+assign roundrobin1_grant = 1'd0;
+assign roundrobin2_grant = 1'd0;
+assign roundrobin3_grant = 1'd0;
+assign roundrobin4_grant = 1'd0;
+assign roundrobin5_grant = 1'd0;
+assign roundrobin6_grant = 1'd0;
+assign roundrobin7_grant = 1'd0;
 always @(*) begin
-    litedramcore_next_state <= 2'd0;
-    litedramcore_next_state <= litedramcore_state;
-    case (litedramcore_state)
+    next_state <= 2'd0;
+    next_state <= state;
+    case (state)
         1'd1: begin
-            litedramcore_next_state <= 2'd2;
+            next_state <= 2'd2;
         end
         2'd2: begin
-            litedramcore_next_state <= 1'd0;
+            next_state <= 1'd0;
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_next_state <= 1'd1;
+            if ((interface0_cyc & interface0_stb)) begin
+                next_state <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_dat_w_next_value0 <= 32'd0;
-    case (litedramcore_state)
+    interface1_dat_w_next_value0 <= 32'd0;
+    case (state)
         1'd1: begin
         end
         2'd2: begin
         end
         default: begin
-            litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
+            interface1_dat_w_next_value0 <= interface0_dat_w;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_dat_w_next_value_ce0 <= 1'd0;
-    case (litedramcore_state)
+    interface1_dat_w_next_value_ce0 <= 1'd0;
+    case (state)
         1'd1: begin
         end
         2'd2: begin
         end
         default: begin
-            litedramcore_dat_w_next_value_ce0 <= 1'd1;
+            interface1_dat_w_next_value_ce0 <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_wishbone_ack <= 1'd0;
-    case (litedramcore_state)
+    interface1_adr_next_value1 <= 14'd0;
+    case (state)
         1'd1: begin
+            interface1_adr_next_value1 <= 1'd0;
         end
         2'd2: begin
-            litedramcore_wishbone_ack <= 1'd1;
         end
         default: begin
+            if ((interface0_cyc & interface0_stb)) begin
+                interface1_adr_next_value1 <= interface0_adr[29:0];
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_adr_next_value1 <= 14'd0;
-    case (litedramcore_state)
+    interface1_adr_next_value_ce1 <= 1'd0;
+    case (state)
         1'd1: begin
-            litedramcore_adr_next_value1 <= 1'd0;
+            interface1_adr_next_value_ce1 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
+            if ((interface0_cyc & interface0_stb)) begin
+                interface1_adr_next_value_ce1 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_adr_next_value_ce1 <= 1'd0;
-    case (litedramcore_state)
+    interface1_we_next_value2 <= 1'd0;
+    case (state)
         1'd1: begin
-            litedramcore_adr_next_value_ce1 <= 1'd1;
+            interface1_we_next_value2 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_adr_next_value_ce1 <= 1'd1;
+            if ((interface0_cyc & interface0_stb)) begin
+                interface1_we_next_value2 <= (interface0_we & (interface0_sel != 1'd0));
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_we_next_value2 <= 1'd0;
-    case (litedramcore_state)
+    interface1_we_next_value_ce2 <= 1'd0;
+    case (state)
         1'd1: begin
-            litedramcore_we_next_value2 <= 1'd0;
+            interface1_we_next_value_ce2 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+            if ((interface0_cyc & interface0_stb)) begin
+                interface1_we_next_value_ce2 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_we_next_value_ce2 <= 1'd0;
-    case (litedramcore_state)
+    interface0_dat_r <= 32'd0;
+    case (state)
         1'd1: begin
-            litedramcore_we_next_value_ce2 <= 1'd1;
         end
         2'd2: begin
+            interface0_dat_r <= interface1_dat_r;
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_we_next_value_ce2 <= 1'd1;
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_wishbone_dat_r <= 32'd0;
-    case (litedramcore_state)
+    interface0_ack <= 1'd0;
+    case (state)
         1'd1: begin
         end
         2'd2: begin
-            litedramcore_wishbone_dat_r <= litedramcore_dat_r;
+            interface0_ack <= 1'd1;
         end
         default: begin
         end
     endcase
 end
-assign litedramcore_wishbone_adr = soc_wb_bus_adr;
-assign litedramcore_wishbone_dat_w = soc_wb_bus_dat_w;
-assign soc_wb_bus_dat_r = litedramcore_wishbone_dat_r;
-assign litedramcore_wishbone_sel = soc_wb_bus_sel;
-assign litedramcore_wishbone_cyc = soc_wb_bus_cyc;
-assign litedramcore_wishbone_stb = soc_wb_bus_stb;
-assign soc_wb_bus_ack = litedramcore_wishbone_ack;
-assign litedramcore_wishbone_we = soc_wb_bus_we;
-assign litedramcore_wishbone_cti = soc_wb_bus_cti;
-assign litedramcore_wishbone_bte = soc_wb_bus_bte;
-assign soc_wb_bus_err = litedramcore_wishbone_err;
 assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
 assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
@@ -10512,15 +10763,15 @@ always @(*) begin
 end
 assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank0_init_error0_we <= 1'd0;
+    csrbank0_init_error0_re <= 1'd0;
     if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank0_init_error0_we <= (~interface0_bank_bus_we);
+        csrbank0_init_error0_re <= interface0_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank0_init_error0_re <= 1'd0;
+    csrbank0_init_error0_we <= 1'd0;
     if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank0_init_error0_re <= interface0_bank_bus_we;
+        csrbank0_init_error0_we <= (~interface0_bank_bus_we);
     end
 end
 assign csrbank0_init_done0_w = soc_init_done_storage;
@@ -10528,41 +10779,41 @@ assign csrbank0_init_error0_w = soc_init_error_storage;
 assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
 assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0];
 always @(*) begin
-    csrbank1_dfii_control0_we <= 1'd0;
+    csrbank1_dfii_control0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank1_dfii_control0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_control0_re <= interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_dfii_control0_re <= 1'd0;
+    csrbank1_dfii_control0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank1_dfii_control0_re <= interface1_bank_bus_we;
+        csrbank1_dfii_control0_we <= (~interface1_bank_bus_we);
     end
 end
-assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[5:0];
+assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank1_dfii_pi0_command0_re <= 1'd0;
+    csrbank1_dfii_pi0_command0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank1_dfii_pi0_command0_re <= interface1_bank_bus_we;
+        csrbank1_dfii_pi0_command0_we <= (~interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank1_dfii_pi0_command0_we <= 1'd0;
+    csrbank1_dfii_pi0_command0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank1_dfii_pi0_command0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi0_command0_re <= interface1_bank_bus_we;
     end
 end
 assign soc_litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-    soc_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+    soc_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        soc_litedramcore_phaseinjector0_command_issue_we <= (~interface1_bank_bus_we);
+        soc_litedramcore_phaseinjector0_command_issue_re <= interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    soc_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+    soc_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        soc_litedramcore_phaseinjector0_command_issue_re <= interface1_bank_bus_we;
+        soc_litedramcore_phaseinjector0_command_issue_we <= (~interface1_bank_bus_we);
     end
 end
 assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[13:0];
@@ -10593,31 +10844,31 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank1_dfii_pi0_wrdata0_re <= 1'd0;
+    csrbank1_dfii_pi0_wrdata0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        csrbank1_dfii_pi0_wrdata0_re <= interface1_bank_bus_we;
+        csrbank1_dfii_pi0_wrdata0_we <= (~interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank1_dfii_pi0_wrdata0_we <= 1'd0;
+    csrbank1_dfii_pi0_wrdata0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        csrbank1_dfii_pi0_wrdata0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi0_wrdata0_re <= interface1_bank_bus_we;
     end
 end
 assign csrbank1_dfii_pi0_rddata_r = interface1_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank1_dfii_pi0_rddata_we <= 1'd0;
+    csrbank1_dfii_pi0_rddata_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        csrbank1_dfii_pi0_rddata_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi0_rddata_re <= interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_dfii_pi0_rddata_re <= 1'd0;
+    csrbank1_dfii_pi0_rddata_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        csrbank1_dfii_pi0_rddata_re <= interface1_bank_bus_we;
+        csrbank1_dfii_pi0_rddata_we <= (~interface1_bank_bus_we);
     end
 end
-assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[5:0];
+assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
     csrbank1_dfii_pi1_command0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
@@ -10632,41 +10883,41 @@ always @(*) begin
 end
 assign soc_litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-    soc_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+    soc_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
-        soc_litedramcore_phaseinjector1_command_issue_re <= interface1_bank_bus_we;
+        soc_litedramcore_phaseinjector1_command_issue_we <= (~interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    soc_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+    soc_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
-        soc_litedramcore_phaseinjector1_command_issue_we <= (~interface1_bank_bus_we);
+        soc_litedramcore_phaseinjector1_command_issue_re <= interface1_bank_bus_we;
     end
 end
 assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[13:0];
 always @(*) begin
-    csrbank1_dfii_pi1_address0_re <= 1'd0;
+    csrbank1_dfii_pi1_address0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
-        csrbank1_dfii_pi1_address0_re <= interface1_bank_bus_we;
+        csrbank1_dfii_pi1_address0_we <= (~interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank1_dfii_pi1_address0_we <= 1'd0;
+    csrbank1_dfii_pi1_address0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
-        csrbank1_dfii_pi1_address0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi1_address0_re <= interface1_bank_bus_we;
     end
 end
 assign csrbank1_dfii_pi1_baddress0_r = interface1_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank1_dfii_pi1_baddress0_we <= 1'd0;
+    csrbank1_dfii_pi1_baddress0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
-        csrbank1_dfii_pi1_baddress0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi1_baddress0_re <= interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_dfii_pi1_baddress0_re <= 1'd0;
+    csrbank1_dfii_pi1_baddress0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
-        csrbank1_dfii_pi1_baddress0_re <= interface1_bank_bus_we;
+        csrbank1_dfii_pi1_baddress0_we <= (~interface1_bank_bus_we);
     end
 end
 assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[31:0];
@@ -10695,17 +10946,17 @@ always @(*) begin
         csrbank1_dfii_pi1_rddata_we <= (~interface1_bank_bus_we);
     end
 end
-assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[5:0];
+assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank1_dfii_pi2_command0_we <= 1'd0;
+    csrbank1_dfii_pi2_command0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin
-        csrbank1_dfii_pi2_command0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi2_command0_re <= interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_dfii_pi2_command0_re <= 1'd0;
+    csrbank1_dfii_pi2_command0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin
-        csrbank1_dfii_pi2_command0_re <= interface1_bank_bus_we;
+        csrbank1_dfii_pi2_command0_we <= (~interface1_bank_bus_we);
     end
 end
 assign soc_litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0];
@@ -10749,31 +11000,31 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank1_dfii_pi2_wrdata0_we <= 1'd0;
+    csrbank1_dfii_pi2_wrdata0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin
-        csrbank1_dfii_pi2_wrdata0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi2_wrdata0_re <= interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_dfii_pi2_wrdata0_re <= 1'd0;
+    csrbank1_dfii_pi2_wrdata0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin
-        csrbank1_dfii_pi2_wrdata0_re <= interface1_bank_bus_we;
+        csrbank1_dfii_pi2_wrdata0_we <= (~interface1_bank_bus_we);
     end
 end
 assign csrbank1_dfii_pi2_rddata_r = interface1_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank1_dfii_pi2_rddata_re <= 1'd0;
+    csrbank1_dfii_pi2_rddata_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin
-        csrbank1_dfii_pi2_rddata_re <= interface1_bank_bus_we;
+        csrbank1_dfii_pi2_rddata_we <= (~interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank1_dfii_pi2_rddata_we <= 1'd0;
+    csrbank1_dfii_pi2_rddata_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin
-        csrbank1_dfii_pi2_rddata_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi2_rddata_re <= interface1_bank_bus_we;
     end
 end
-assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[5:0];
+assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
     csrbank1_dfii_pi3_command0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin
@@ -10801,28 +11052,28 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[13:0];
 always @(*) begin
-    csrbank1_dfii_pi3_address0_we <= 1'd0;
+    csrbank1_dfii_pi3_address0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin
-        csrbank1_dfii_pi3_address0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi3_address0_re <= interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_dfii_pi3_address0_re <= 1'd0;
+    csrbank1_dfii_pi3_address0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin
-        csrbank1_dfii_pi3_address0_re <= interface1_bank_bus_we;
+        csrbank1_dfii_pi3_address0_we <= (~interface1_bank_bus_we);
     end
 end
 assign csrbank1_dfii_pi3_baddress0_r = interface1_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank1_dfii_pi3_baddress0_re <= 1'd0;
+    csrbank1_dfii_pi3_baddress0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin
-        csrbank1_dfii_pi3_baddress0_re <= interface1_bank_bus_we;
+        csrbank1_dfii_pi3_baddress0_we <= (~interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank1_dfii_pi3_baddress0_we <= 1'd0;
+    csrbank1_dfii_pi3_baddress0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin
-        csrbank1_dfii_pi3_baddress0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi3_baddress0_re <= interface1_bank_bus_we;
     end
 end
 assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[31:0];
@@ -10862,7 +11113,9 @@ assign soc_litedramcore_phaseinjector0_csrfield_cas = soc_litedramcore_phaseinje
 assign soc_litedramcore_phaseinjector0_csrfield_ras = soc_litedramcore_phaseinjector0_command_storage[3];
 assign soc_litedramcore_phaseinjector0_csrfield_wren = soc_litedramcore_phaseinjector0_command_storage[4];
 assign soc_litedramcore_phaseinjector0_csrfield_rden = soc_litedramcore_phaseinjector0_command_storage[5];
-assign csrbank1_dfii_pi0_command0_w = soc_litedramcore_phaseinjector0_command_storage[5:0];
+assign soc_litedramcore_phaseinjector0_csrfield_cs_top = soc_litedramcore_phaseinjector0_command_storage[6];
+assign soc_litedramcore_phaseinjector0_csrfield_cs_bottom = soc_litedramcore_phaseinjector0_command_storage[7];
+assign csrbank1_dfii_pi0_command0_w = soc_litedramcore_phaseinjector0_command_storage[7:0];
 assign csrbank1_dfii_pi0_address0_w = soc_litedramcore_phaseinjector0_address_storage[13:0];
 assign csrbank1_dfii_pi0_baddress0_w = soc_litedramcore_phaseinjector0_baddress_storage[2:0];
 assign csrbank1_dfii_pi0_wrdata0_w = soc_litedramcore_phaseinjector0_wrdata_storage[31:0];
@@ -10874,7 +11127,9 @@ assign soc_litedramcore_phaseinjector1_csrfield_cas = soc_litedramcore_phaseinje
 assign soc_litedramcore_phaseinjector1_csrfield_ras = soc_litedramcore_phaseinjector1_command_storage[3];
 assign soc_litedramcore_phaseinjector1_csrfield_wren = soc_litedramcore_phaseinjector1_command_storage[4];
 assign soc_litedramcore_phaseinjector1_csrfield_rden = soc_litedramcore_phaseinjector1_command_storage[5];
-assign csrbank1_dfii_pi1_command0_w = soc_litedramcore_phaseinjector1_command_storage[5:0];
+assign soc_litedramcore_phaseinjector1_csrfield_cs_top = soc_litedramcore_phaseinjector1_command_storage[6];
+assign soc_litedramcore_phaseinjector1_csrfield_cs_bottom = soc_litedramcore_phaseinjector1_command_storage[7];
+assign csrbank1_dfii_pi1_command0_w = soc_litedramcore_phaseinjector1_command_storage[7:0];
 assign csrbank1_dfii_pi1_address0_w = soc_litedramcore_phaseinjector1_address_storage[13:0];
 assign csrbank1_dfii_pi1_baddress0_w = soc_litedramcore_phaseinjector1_baddress_storage[2:0];
 assign csrbank1_dfii_pi1_wrdata0_w = soc_litedramcore_phaseinjector1_wrdata_storage[31:0];
@@ -10886,7 +11141,9 @@ assign soc_litedramcore_phaseinjector2_csrfield_cas = soc_litedramcore_phaseinje
 assign soc_litedramcore_phaseinjector2_csrfield_ras = soc_litedramcore_phaseinjector2_command_storage[3];
 assign soc_litedramcore_phaseinjector2_csrfield_wren = soc_litedramcore_phaseinjector2_command_storage[4];
 assign soc_litedramcore_phaseinjector2_csrfield_rden = soc_litedramcore_phaseinjector2_command_storage[5];
-assign csrbank1_dfii_pi2_command0_w = soc_litedramcore_phaseinjector2_command_storage[5:0];
+assign soc_litedramcore_phaseinjector2_csrfield_cs_top = soc_litedramcore_phaseinjector2_command_storage[6];
+assign soc_litedramcore_phaseinjector2_csrfield_cs_bottom = soc_litedramcore_phaseinjector2_command_storage[7];
+assign csrbank1_dfii_pi2_command0_w = soc_litedramcore_phaseinjector2_command_storage[7:0];
 assign csrbank1_dfii_pi2_address0_w = soc_litedramcore_phaseinjector2_address_storage[13:0];
 assign csrbank1_dfii_pi2_baddress0_w = soc_litedramcore_phaseinjector2_baddress_storage[2:0];
 assign csrbank1_dfii_pi2_wrdata0_w = soc_litedramcore_phaseinjector2_wrdata_storage[31:0];
@@ -10898,23 +11155,25 @@ assign soc_litedramcore_phaseinjector3_csrfield_cas = soc_litedramcore_phaseinje
 assign soc_litedramcore_phaseinjector3_csrfield_ras = soc_litedramcore_phaseinjector3_command_storage[3];
 assign soc_litedramcore_phaseinjector3_csrfield_wren = soc_litedramcore_phaseinjector3_command_storage[4];
 assign soc_litedramcore_phaseinjector3_csrfield_rden = soc_litedramcore_phaseinjector3_command_storage[5];
-assign csrbank1_dfii_pi3_command0_w = soc_litedramcore_phaseinjector3_command_storage[5:0];
+assign soc_litedramcore_phaseinjector3_csrfield_cs_top = soc_litedramcore_phaseinjector3_command_storage[6];
+assign soc_litedramcore_phaseinjector3_csrfield_cs_bottom = soc_litedramcore_phaseinjector3_command_storage[7];
+assign csrbank1_dfii_pi3_command0_w = soc_litedramcore_phaseinjector3_command_storage[7:0];
 assign csrbank1_dfii_pi3_address0_w = soc_litedramcore_phaseinjector3_address_storage[13:0];
 assign csrbank1_dfii_pi3_baddress0_w = soc_litedramcore_phaseinjector3_baddress_storage[2:0];
 assign csrbank1_dfii_pi3_wrdata0_w = soc_litedramcore_phaseinjector3_wrdata_storage[31:0];
 assign csrbank1_dfii_pi3_rddata_w = soc_litedramcore_phaseinjector3_rddata_status[31:0];
 assign soc_litedramcore_phaseinjector3_rddata_we = csrbank1_dfii_pi3_rddata_we;
-assign csr_interconnect_adr = litedramcore_adr;
-assign csr_interconnect_we = litedramcore_we;
-assign csr_interconnect_dat_w = litedramcore_dat_w;
-assign litedramcore_dat_r = csr_interconnect_dat_r;
-assign interface0_bank_bus_adr = csr_interconnect_adr;
-assign interface1_bank_bus_adr = csr_interconnect_adr;
-assign interface0_bank_bus_we = csr_interconnect_we;
-assign interface1_bank_bus_we = csr_interconnect_we;
-assign interface0_bank_bus_dat_w = csr_interconnect_dat_w;
-assign interface1_bank_bus_dat_w = csr_interconnect_dat_w;
-assign csr_interconnect_dat_r = (interface0_bank_bus_dat_r | interface1_bank_bus_dat_r);
+assign adr = interface1_adr;
+assign we = interface1_we;
+assign dat_w = interface1_dat_w;
+assign interface1_dat_r = dat_r;
+assign interface0_bank_bus_adr = adr;
+assign interface1_bank_bus_adr = adr;
+assign interface0_bank_bus_we = we;
+assign interface1_bank_bus_we = we;
+assign interface0_bank_bus_dat_w = dat_w;
+assign interface1_bank_bus_dat_w = dat_w;
+assign dat_r = (interface0_bank_bus_dat_r | interface1_bank_bus_dat_r);
 assign slice_proxy0 = ((soc_ddrphy_bankmodel0_row * 11'd1024) | soc_ddrphy_bankmodel0_write_col);
 assign slice_proxy1 = ((soc_ddrphy_bankmodel0_row * 11'd1024) | soc_ddrphy_bankmodel0_read_col);
 assign slice_proxy2 = ((soc_ddrphy_bankmodel1_row * 11'd1024) | soc_ddrphy_bankmodel1_write_col);
@@ -10932,1192 +11191,1192 @@ assign slice_proxy13 = ((soc_ddrphy_bankmodel6_row * 11'd1024) | soc_ddrphy_bank
 assign slice_proxy14 = ((soc_ddrphy_bankmodel7_row * 11'd1024) | soc_ddrphy_bankmodel7_write_col);
 assign slice_proxy15 = ((soc_ddrphy_bankmodel7_row * 11'd1024) | soc_ddrphy_bankmodel7_read_col);
 always @(*) begin
-    rhs_array_muxed0 <= 1'd0;
+    rhs_self0 <= 1'd0;
     case (soc_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[0];
+            rhs_self0 <= soc_litedramcore_choose_cmd_valids[0];
         end
         1'd1: begin
-            rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[1];
+            rhs_self0 <= soc_litedramcore_choose_cmd_valids[1];
         end
         2'd2: begin
-            rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[2];
+            rhs_self0 <= soc_litedramcore_choose_cmd_valids[2];
         end
         2'd3: begin
-            rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[3];
+            rhs_self0 <= soc_litedramcore_choose_cmd_valids[3];
         end
         3'd4: begin
-            rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[4];
+            rhs_self0 <= soc_litedramcore_choose_cmd_valids[4];
         end
         3'd5: begin
-            rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[5];
+            rhs_self0 <= soc_litedramcore_choose_cmd_valids[5];
         end
         3'd6: begin
-            rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[6];
+            rhs_self0 <= soc_litedramcore_choose_cmd_valids[6];
         end
         default: begin
-            rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[7];
+            rhs_self0 <= soc_litedramcore_choose_cmd_valids[7];
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed1 <= 14'd0;
+    rhs_self1 <= 14'd0;
     case (soc_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_a;
+            rhs_self1 <= soc_litedramcore_bankmachine0_cmd_payload_a;
         end
         1'd1: begin
-            rhs_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_a;
+            rhs_self1 <= soc_litedramcore_bankmachine1_cmd_payload_a;
         end
         2'd2: begin
-            rhs_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_a;
+            rhs_self1 <= soc_litedramcore_bankmachine2_cmd_payload_a;
         end
         2'd3: begin
-            rhs_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_a;
+            rhs_self1 <= soc_litedramcore_bankmachine3_cmd_payload_a;
         end
         3'd4: begin
-            rhs_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_a;
+            rhs_self1 <= soc_litedramcore_bankmachine4_cmd_payload_a;
         end
         3'd5: begin
-            rhs_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_a;
+            rhs_self1 <= soc_litedramcore_bankmachine5_cmd_payload_a;
         end
         3'd6: begin
-            rhs_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_a;
+            rhs_self1 <= soc_litedramcore_bankmachine6_cmd_payload_a;
         end
         default: begin
-            rhs_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_a;
+            rhs_self1 <= soc_litedramcore_bankmachine7_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed2 <= 3'd0;
+    rhs_self2 <= 3'd0;
     case (soc_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_ba;
+            rhs_self2 <= soc_litedramcore_bankmachine0_cmd_payload_ba;
         end
         1'd1: begin
-            rhs_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_ba;
+            rhs_self2 <= soc_litedramcore_bankmachine1_cmd_payload_ba;
         end
         2'd2: begin
-            rhs_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_ba;
+            rhs_self2 <= soc_litedramcore_bankmachine2_cmd_payload_ba;
         end
         2'd3: begin
-            rhs_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_ba;
+            rhs_self2 <= soc_litedramcore_bankmachine3_cmd_payload_ba;
         end
         3'd4: begin
-            rhs_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_ba;
+            rhs_self2 <= soc_litedramcore_bankmachine4_cmd_payload_ba;
         end
         3'd5: begin
-            rhs_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_ba;
+            rhs_self2 <= soc_litedramcore_bankmachine5_cmd_payload_ba;
         end
         3'd6: begin
-            rhs_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_ba;
+            rhs_self2 <= soc_litedramcore_bankmachine6_cmd_payload_ba;
         end
         default: begin
-            rhs_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_ba;
+            rhs_self2 <= soc_litedramcore_bankmachine7_cmd_payload_ba;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed3 <= 1'd0;
+    rhs_self3 <= 1'd0;
     case (soc_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_is_read;
+            rhs_self3 <= soc_litedramcore_bankmachine0_cmd_payload_is_read;
         end
         1'd1: begin
-            rhs_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_is_read;
+            rhs_self3 <= soc_litedramcore_bankmachine1_cmd_payload_is_read;
         end
         2'd2: begin
-            rhs_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_is_read;
+            rhs_self3 <= soc_litedramcore_bankmachine2_cmd_payload_is_read;
         end
         2'd3: begin
-            rhs_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_is_read;
+            rhs_self3 <= soc_litedramcore_bankmachine3_cmd_payload_is_read;
         end
         3'd4: begin
-            rhs_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_is_read;
+            rhs_self3 <= soc_litedramcore_bankmachine4_cmd_payload_is_read;
         end
         3'd5: begin
-            rhs_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_is_read;
+            rhs_self3 <= soc_litedramcore_bankmachine5_cmd_payload_is_read;
         end
         3'd6: begin
-            rhs_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_is_read;
+            rhs_self3 <= soc_litedramcore_bankmachine6_cmd_payload_is_read;
         end
         default: begin
-            rhs_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_is_read;
+            rhs_self3 <= soc_litedramcore_bankmachine7_cmd_payload_is_read;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed4 <= 1'd0;
+    rhs_self4 <= 1'd0;
     case (soc_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_is_write;
+            rhs_self4 <= soc_litedramcore_bankmachine0_cmd_payload_is_write;
         end
         1'd1: begin
-            rhs_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_is_write;
+            rhs_self4 <= soc_litedramcore_bankmachine1_cmd_payload_is_write;
         end
         2'd2: begin
-            rhs_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_is_write;
+            rhs_self4 <= soc_litedramcore_bankmachine2_cmd_payload_is_write;
         end
         2'd3: begin
-            rhs_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_is_write;
+            rhs_self4 <= soc_litedramcore_bankmachine3_cmd_payload_is_write;
         end
         3'd4: begin
-            rhs_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_is_write;
+            rhs_self4 <= soc_litedramcore_bankmachine4_cmd_payload_is_write;
         end
         3'd5: begin
-            rhs_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_is_write;
+            rhs_self4 <= soc_litedramcore_bankmachine5_cmd_payload_is_write;
         end
         3'd6: begin
-            rhs_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_is_write;
+            rhs_self4 <= soc_litedramcore_bankmachine6_cmd_payload_is_write;
         end
         default: begin
-            rhs_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_is_write;
+            rhs_self4 <= soc_litedramcore_bankmachine7_cmd_payload_is_write;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed5 <= 1'd0;
+    rhs_self5 <= 1'd0;
     case (soc_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd;
+            rhs_self5 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd;
         end
         1'd1: begin
-            rhs_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd;
+            rhs_self5 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd;
         end
         2'd2: begin
-            rhs_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd;
+            rhs_self5 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd;
         end
         2'd3: begin
-            rhs_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd;
+            rhs_self5 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd;
         end
         3'd4: begin
-            rhs_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd;
+            rhs_self5 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd;
         end
         3'd5: begin
-            rhs_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd;
+            rhs_self5 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd;
         end
         3'd6: begin
-            rhs_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd;
+            rhs_self5 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd;
         end
         default: begin
-            rhs_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd;
+            rhs_self5 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed0 <= 1'd0;
+    t_self0 <= 1'd0;
     case (soc_litedramcore_choose_cmd_grant)
         1'd0: begin
-            t_array_muxed0 <= soc_litedramcore_bankmachine0_cmd_payload_cas;
+            t_self0 <= soc_litedramcore_bankmachine0_cmd_payload_cas;
         end
         1'd1: begin
-            t_array_muxed0 <= soc_litedramcore_bankmachine1_cmd_payload_cas;
+            t_self0 <= soc_litedramcore_bankmachine1_cmd_payload_cas;
         end
         2'd2: begin
-            t_array_muxed0 <= soc_litedramcore_bankmachine2_cmd_payload_cas;
+            t_self0 <= soc_litedramcore_bankmachine2_cmd_payload_cas;
         end
         2'd3: begin
-            t_array_muxed0 <= soc_litedramcore_bankmachine3_cmd_payload_cas;
+            t_self0 <= soc_litedramcore_bankmachine3_cmd_payload_cas;
         end
         3'd4: begin
-            t_array_muxed0 <= soc_litedramcore_bankmachine4_cmd_payload_cas;
+            t_self0 <= soc_litedramcore_bankmachine4_cmd_payload_cas;
         end
         3'd5: begin
-            t_array_muxed0 <= soc_litedramcore_bankmachine5_cmd_payload_cas;
+            t_self0 <= soc_litedramcore_bankmachine5_cmd_payload_cas;
         end
         3'd6: begin
-            t_array_muxed0 <= soc_litedramcore_bankmachine6_cmd_payload_cas;
+            t_self0 <= soc_litedramcore_bankmachine6_cmd_payload_cas;
         end
         default: begin
-            t_array_muxed0 <= soc_litedramcore_bankmachine7_cmd_payload_cas;
+            t_self0 <= soc_litedramcore_bankmachine7_cmd_payload_cas;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed1 <= 1'd0;
+    t_self1 <= 1'd0;
     case (soc_litedramcore_choose_cmd_grant)
         1'd0: begin
-            t_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_ras;
+            t_self1 <= soc_litedramcore_bankmachine0_cmd_payload_ras;
         end
         1'd1: begin
-            t_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_ras;
+            t_self1 <= soc_litedramcore_bankmachine1_cmd_payload_ras;
         end
         2'd2: begin
-            t_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_ras;
+            t_self1 <= soc_litedramcore_bankmachine2_cmd_payload_ras;
         end
         2'd3: begin
-            t_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_ras;
+            t_self1 <= soc_litedramcore_bankmachine3_cmd_payload_ras;
         end
         3'd4: begin
-            t_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_ras;
+            t_self1 <= soc_litedramcore_bankmachine4_cmd_payload_ras;
         end
         3'd5: begin
-            t_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_ras;
+            t_self1 <= soc_litedramcore_bankmachine5_cmd_payload_ras;
         end
         3'd6: begin
-            t_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_ras;
+            t_self1 <= soc_litedramcore_bankmachine6_cmd_payload_ras;
         end
         default: begin
-            t_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_ras;
+            t_self1 <= soc_litedramcore_bankmachine7_cmd_payload_ras;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed2 <= 1'd0;
+    t_self2 <= 1'd0;
     case (soc_litedramcore_choose_cmd_grant)
         1'd0: begin
-            t_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_we;
+            t_self2 <= soc_litedramcore_bankmachine0_cmd_payload_we;
         end
         1'd1: begin
-            t_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_we;
+            t_self2 <= soc_litedramcore_bankmachine1_cmd_payload_we;
         end
         2'd2: begin
-            t_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_we;
+            t_self2 <= soc_litedramcore_bankmachine2_cmd_payload_we;
         end
         2'd3: begin
-            t_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_we;
+            t_self2 <= soc_litedramcore_bankmachine3_cmd_payload_we;
         end
         3'd4: begin
-            t_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_we;
+            t_self2 <= soc_litedramcore_bankmachine4_cmd_payload_we;
         end
         3'd5: begin
-            t_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_we;
+            t_self2 <= soc_litedramcore_bankmachine5_cmd_payload_we;
         end
         3'd6: begin
-            t_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_we;
+            t_self2 <= soc_litedramcore_bankmachine6_cmd_payload_we;
         end
         default: begin
-            t_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_we;
+            t_self2 <= soc_litedramcore_bankmachine7_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed6 <= 1'd0;
+    rhs_self6 <= 1'd0;
     case (soc_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[0];
+            rhs_self6 <= soc_litedramcore_choose_req_valids[0];
         end
         1'd1: begin
-            rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[1];
+            rhs_self6 <= soc_litedramcore_choose_req_valids[1];
         end
         2'd2: begin
-            rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[2];
+            rhs_self6 <= soc_litedramcore_choose_req_valids[2];
         end
         2'd3: begin
-            rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[3];
+            rhs_self6 <= soc_litedramcore_choose_req_valids[3];
         end
         3'd4: begin
-            rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[4];
+            rhs_self6 <= soc_litedramcore_choose_req_valids[4];
         end
         3'd5: begin
-            rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[5];
+            rhs_self6 <= soc_litedramcore_choose_req_valids[5];
         end
         3'd6: begin
-            rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[6];
+            rhs_self6 <= soc_litedramcore_choose_req_valids[6];
         end
         default: begin
-            rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[7];
+            rhs_self6 <= soc_litedramcore_choose_req_valids[7];
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed7 <= 14'd0;
+    rhs_self7 <= 14'd0;
     case (soc_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed7 <= soc_litedramcore_bankmachine0_cmd_payload_a;
+            rhs_self7 <= soc_litedramcore_bankmachine0_cmd_payload_a;
         end
         1'd1: begin
-            rhs_array_muxed7 <= soc_litedramcore_bankmachine1_cmd_payload_a;
+            rhs_self7 <= soc_litedramcore_bankmachine1_cmd_payload_a;
         end
         2'd2: begin
-            rhs_array_muxed7 <= soc_litedramcore_bankmachine2_cmd_payload_a;
+            rhs_self7 <= soc_litedramcore_bankmachine2_cmd_payload_a;
         end
         2'd3: begin
-            rhs_array_muxed7 <= soc_litedramcore_bankmachine3_cmd_payload_a;
+            rhs_self7 <= soc_litedramcore_bankmachine3_cmd_payload_a;
         end
         3'd4: begin
-            rhs_array_muxed7 <= soc_litedramcore_bankmachine4_cmd_payload_a;
+            rhs_self7 <= soc_litedramcore_bankmachine4_cmd_payload_a;
         end
         3'd5: begin
-            rhs_array_muxed7 <= soc_litedramcore_bankmachine5_cmd_payload_a;
+            rhs_self7 <= soc_litedramcore_bankmachine5_cmd_payload_a;
         end
         3'd6: begin
-            rhs_array_muxed7 <= soc_litedramcore_bankmachine6_cmd_payload_a;
+            rhs_self7 <= soc_litedramcore_bankmachine6_cmd_payload_a;
         end
         default: begin
-            rhs_array_muxed7 <= soc_litedramcore_bankmachine7_cmd_payload_a;
+            rhs_self7 <= soc_litedramcore_bankmachine7_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed8 <= 3'd0;
+    rhs_self8 <= 3'd0;
     case (soc_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed8 <= soc_litedramcore_bankmachine0_cmd_payload_ba;
+            rhs_self8 <= soc_litedramcore_bankmachine0_cmd_payload_ba;
         end
         1'd1: begin
-            rhs_array_muxed8 <= soc_litedramcore_bankmachine1_cmd_payload_ba;
+            rhs_self8 <= soc_litedramcore_bankmachine1_cmd_payload_ba;
         end
         2'd2: begin
-            rhs_array_muxed8 <= soc_litedramcore_bankmachine2_cmd_payload_ba;
+            rhs_self8 <= soc_litedramcore_bankmachine2_cmd_payload_ba;
         end
         2'd3: begin
-            rhs_array_muxed8 <= soc_litedramcore_bankmachine3_cmd_payload_ba;
+            rhs_self8 <= soc_litedramcore_bankmachine3_cmd_payload_ba;
         end
         3'd4: begin
-            rhs_array_muxed8 <= soc_litedramcore_bankmachine4_cmd_payload_ba;
+            rhs_self8 <= soc_litedramcore_bankmachine4_cmd_payload_ba;
         end
         3'd5: begin
-            rhs_array_muxed8 <= soc_litedramcore_bankmachine5_cmd_payload_ba;
+            rhs_self8 <= soc_litedramcore_bankmachine5_cmd_payload_ba;
         end
         3'd6: begin
-            rhs_array_muxed8 <= soc_litedramcore_bankmachine6_cmd_payload_ba;
+            rhs_self8 <= soc_litedramcore_bankmachine6_cmd_payload_ba;
         end
         default: begin
-            rhs_array_muxed8 <= soc_litedramcore_bankmachine7_cmd_payload_ba;
+            rhs_self8 <= soc_litedramcore_bankmachine7_cmd_payload_ba;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed9 <= 1'd0;
+    rhs_self9 <= 1'd0;
     case (soc_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed9 <= soc_litedramcore_bankmachine0_cmd_payload_is_read;
+            rhs_self9 <= soc_litedramcore_bankmachine0_cmd_payload_is_read;
         end
         1'd1: begin
-            rhs_array_muxed9 <= soc_litedramcore_bankmachine1_cmd_payload_is_read;
+            rhs_self9 <= soc_litedramcore_bankmachine1_cmd_payload_is_read;
         end
         2'd2: begin
-            rhs_array_muxed9 <= soc_litedramcore_bankmachine2_cmd_payload_is_read;
+            rhs_self9 <= soc_litedramcore_bankmachine2_cmd_payload_is_read;
         end
         2'd3: begin
-            rhs_array_muxed9 <= soc_litedramcore_bankmachine3_cmd_payload_is_read;
+            rhs_self9 <= soc_litedramcore_bankmachine3_cmd_payload_is_read;
         end
         3'd4: begin
-            rhs_array_muxed9 <= soc_litedramcore_bankmachine4_cmd_payload_is_read;
+            rhs_self9 <= soc_litedramcore_bankmachine4_cmd_payload_is_read;
         end
         3'd5: begin
-            rhs_array_muxed9 <= soc_litedramcore_bankmachine5_cmd_payload_is_read;
+            rhs_self9 <= soc_litedramcore_bankmachine5_cmd_payload_is_read;
         end
         3'd6: begin
-            rhs_array_muxed9 <= soc_litedramcore_bankmachine6_cmd_payload_is_read;
+            rhs_self9 <= soc_litedramcore_bankmachine6_cmd_payload_is_read;
         end
         default: begin
-            rhs_array_muxed9 <= soc_litedramcore_bankmachine7_cmd_payload_is_read;
+            rhs_self9 <= soc_litedramcore_bankmachine7_cmd_payload_is_read;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed10 <= 1'd0;
+    rhs_self10 <= 1'd0;
     case (soc_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed10 <= soc_litedramcore_bankmachine0_cmd_payload_is_write;
+            rhs_self10 <= soc_litedramcore_bankmachine0_cmd_payload_is_write;
         end
         1'd1: begin
-            rhs_array_muxed10 <= soc_litedramcore_bankmachine1_cmd_payload_is_write;
+            rhs_self10 <= soc_litedramcore_bankmachine1_cmd_payload_is_write;
         end
         2'd2: begin
-            rhs_array_muxed10 <= soc_litedramcore_bankmachine2_cmd_payload_is_write;
+            rhs_self10 <= soc_litedramcore_bankmachine2_cmd_payload_is_write;
         end
         2'd3: begin
-            rhs_array_muxed10 <= soc_litedramcore_bankmachine3_cmd_payload_is_write;
+            rhs_self10 <= soc_litedramcore_bankmachine3_cmd_payload_is_write;
         end
         3'd4: begin
-            rhs_array_muxed10 <= soc_litedramcore_bankmachine4_cmd_payload_is_write;
+            rhs_self10 <= soc_litedramcore_bankmachine4_cmd_payload_is_write;
         end
         3'd5: begin
-            rhs_array_muxed10 <= soc_litedramcore_bankmachine5_cmd_payload_is_write;
+            rhs_self10 <= soc_litedramcore_bankmachine5_cmd_payload_is_write;
         end
         3'd6: begin
-            rhs_array_muxed10 <= soc_litedramcore_bankmachine6_cmd_payload_is_write;
+            rhs_self10 <= soc_litedramcore_bankmachine6_cmd_payload_is_write;
         end
         default: begin
-            rhs_array_muxed10 <= soc_litedramcore_bankmachine7_cmd_payload_is_write;
+            rhs_self10 <= soc_litedramcore_bankmachine7_cmd_payload_is_write;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed11 <= 1'd0;
+    rhs_self11 <= 1'd0;
     case (soc_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed11 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd;
+            rhs_self11 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd;
         end
         1'd1: begin
-            rhs_array_muxed11 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd;
+            rhs_self11 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd;
         end
         2'd2: begin
-            rhs_array_muxed11 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd;
+            rhs_self11 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd;
         end
         2'd3: begin
-            rhs_array_muxed11 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd;
+            rhs_self11 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd;
         end
         3'd4: begin
-            rhs_array_muxed11 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd;
+            rhs_self11 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd;
         end
         3'd5: begin
-            rhs_array_muxed11 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd;
+            rhs_self11 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd;
         end
         3'd6: begin
-            rhs_array_muxed11 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd;
+            rhs_self11 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd;
         end
         default: begin
-            rhs_array_muxed11 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd;
+            rhs_self11 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed3 <= 1'd0;
+    t_self3 <= 1'd0;
     case (soc_litedramcore_choose_req_grant)
         1'd0: begin
-            t_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_cas;
+            t_self3 <= soc_litedramcore_bankmachine0_cmd_payload_cas;
         end
         1'd1: begin
-            t_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_cas;
+            t_self3 <= soc_litedramcore_bankmachine1_cmd_payload_cas;
         end
         2'd2: begin
-            t_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_cas;
+            t_self3 <= soc_litedramcore_bankmachine2_cmd_payload_cas;
         end
         2'd3: begin
-            t_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_cas;
+            t_self3 <= soc_litedramcore_bankmachine3_cmd_payload_cas;
         end
         3'd4: begin
-            t_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_cas;
+            t_self3 <= soc_litedramcore_bankmachine4_cmd_payload_cas;
         end
         3'd5: begin
-            t_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_cas;
+            t_self3 <= soc_litedramcore_bankmachine5_cmd_payload_cas;
         end
         3'd6: begin
-            t_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_cas;
+            t_self3 <= soc_litedramcore_bankmachine6_cmd_payload_cas;
         end
         default: begin
-            t_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_cas;
+            t_self3 <= soc_litedramcore_bankmachine7_cmd_payload_cas;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed4 <= 1'd0;
+    t_self4 <= 1'd0;
     case (soc_litedramcore_choose_req_grant)
         1'd0: begin
-            t_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_ras;
+            t_self4 <= soc_litedramcore_bankmachine0_cmd_payload_ras;
         end
         1'd1: begin
-            t_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_ras;
+            t_self4 <= soc_litedramcore_bankmachine1_cmd_payload_ras;
         end
         2'd2: begin
-            t_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_ras;
+            t_self4 <= soc_litedramcore_bankmachine2_cmd_payload_ras;
         end
         2'd3: begin
-            t_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_ras;
+            t_self4 <= soc_litedramcore_bankmachine3_cmd_payload_ras;
         end
         3'd4: begin
-            t_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_ras;
+            t_self4 <= soc_litedramcore_bankmachine4_cmd_payload_ras;
         end
         3'd5: begin
-            t_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_ras;
+            t_self4 <= soc_litedramcore_bankmachine5_cmd_payload_ras;
         end
         3'd6: begin
-            t_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_ras;
+            t_self4 <= soc_litedramcore_bankmachine6_cmd_payload_ras;
         end
         default: begin
-            t_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_ras;
+            t_self4 <= soc_litedramcore_bankmachine7_cmd_payload_ras;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed5 <= 1'd0;
+    t_self5 <= 1'd0;
     case (soc_litedramcore_choose_req_grant)
         1'd0: begin
-            t_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_we;
+            t_self5 <= soc_litedramcore_bankmachine0_cmd_payload_we;
         end
         1'd1: begin
-            t_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_we;
+            t_self5 <= soc_litedramcore_bankmachine1_cmd_payload_we;
         end
         2'd2: begin
-            t_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_we;
+            t_self5 <= soc_litedramcore_bankmachine2_cmd_payload_we;
         end
         2'd3: begin
-            t_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_we;
+            t_self5 <= soc_litedramcore_bankmachine3_cmd_payload_we;
         end
         3'd4: begin
-            t_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_we;
+            t_self5 <= soc_litedramcore_bankmachine4_cmd_payload_we;
         end
         3'd5: begin
-            t_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_we;
+            t_self5 <= soc_litedramcore_bankmachine5_cmd_payload_we;
         end
         3'd6: begin
-            t_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_we;
+            t_self5 <= soc_litedramcore_bankmachine6_cmd_payload_we;
         end
         default: begin
-            t_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_we;
+            t_self5 <= soc_litedramcore_bankmachine7_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed12 <= 21'd0;
-    case (litedramcore_roundrobin0_grant)
+    rhs_self12 <= 21'd0;
+    case (roundrobin0_grant)
         default: begin
-            rhs_array_muxed12 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
+            rhs_self12 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed13 <= 1'd0;
-    case (litedramcore_roundrobin0_grant)
+    rhs_self13 <= 1'd0;
+    case (roundrobin0_grant)
         default: begin
-            rhs_array_muxed13 <= soc_user_port_cmd_payload_we;
+            rhs_self13 <= soc_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed14 <= 1'd0;
-    case (litedramcore_roundrobin0_grant)
+    rhs_self14 <= 1'd0;
+    case (roundrobin0_grant)
         default: begin
-            rhs_array_muxed14 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+            rhs_self14 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed15 <= 21'd0;
-    case (litedramcore_roundrobin1_grant)
+    rhs_self15 <= 21'd0;
+    case (roundrobin1_grant)
         default: begin
-            rhs_array_muxed15 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
+            rhs_self15 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed16 <= 1'd0;
-    case (litedramcore_roundrobin1_grant)
+    rhs_self16 <= 1'd0;
+    case (roundrobin1_grant)
         default: begin
-            rhs_array_muxed16 <= soc_user_port_cmd_payload_we;
+            rhs_self16 <= soc_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed17 <= 1'd0;
-    case (litedramcore_roundrobin1_grant)
+    rhs_self17 <= 1'd0;
+    case (roundrobin1_grant)
         default: begin
-            rhs_array_muxed17 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+            rhs_self17 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed18 <= 21'd0;
-    case (litedramcore_roundrobin2_grant)
+    rhs_self18 <= 21'd0;
+    case (roundrobin2_grant)
         default: begin
-            rhs_array_muxed18 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
+            rhs_self18 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed19 <= 1'd0;
-    case (litedramcore_roundrobin2_grant)
+    rhs_self19 <= 1'd0;
+    case (roundrobin2_grant)
         default: begin
-            rhs_array_muxed19 <= soc_user_port_cmd_payload_we;
+            rhs_self19 <= soc_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed20 <= 1'd0;
-    case (litedramcore_roundrobin2_grant)
+    rhs_self20 <= 1'd0;
+    case (roundrobin2_grant)
         default: begin
-            rhs_array_muxed20 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+            rhs_self20 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed21 <= 21'd0;
-    case (litedramcore_roundrobin3_grant)
+    rhs_self21 <= 21'd0;
+    case (roundrobin3_grant)
         default: begin
-            rhs_array_muxed21 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
+            rhs_self21 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed22 <= 1'd0;
-    case (litedramcore_roundrobin3_grant)
+    rhs_self22 <= 1'd0;
+    case (roundrobin3_grant)
         default: begin
-            rhs_array_muxed22 <= soc_user_port_cmd_payload_we;
+            rhs_self22 <= soc_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed23 <= 1'd0;
-    case (litedramcore_roundrobin3_grant)
+    rhs_self23 <= 1'd0;
+    case (roundrobin3_grant)
         default: begin
-            rhs_array_muxed23 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+            rhs_self23 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed24 <= 21'd0;
-    case (litedramcore_roundrobin4_grant)
+    rhs_self24 <= 21'd0;
+    case (roundrobin4_grant)
         default: begin
-            rhs_array_muxed24 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
+            rhs_self24 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed25 <= 1'd0;
-    case (litedramcore_roundrobin4_grant)
+    rhs_self25 <= 1'd0;
+    case (roundrobin4_grant)
         default: begin
-            rhs_array_muxed25 <= soc_user_port_cmd_payload_we;
+            rhs_self25 <= soc_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed26 <= 1'd0;
-    case (litedramcore_roundrobin4_grant)
+    rhs_self26 <= 1'd0;
+    case (roundrobin4_grant)
         default: begin
-            rhs_array_muxed26 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+            rhs_self26 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed27 <= 21'd0;
-    case (litedramcore_roundrobin5_grant)
+    rhs_self27 <= 21'd0;
+    case (roundrobin5_grant)
         default: begin
-            rhs_array_muxed27 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
+            rhs_self27 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed28 <= 1'd0;
-    case (litedramcore_roundrobin5_grant)
+    rhs_self28 <= 1'd0;
+    case (roundrobin5_grant)
         default: begin
-            rhs_array_muxed28 <= soc_user_port_cmd_payload_we;
+            rhs_self28 <= soc_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed29 <= 1'd0;
-    case (litedramcore_roundrobin5_grant)
+    rhs_self29 <= 1'd0;
+    case (roundrobin5_grant)
         default: begin
-            rhs_array_muxed29 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+            rhs_self29 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed30 <= 21'd0;
-    case (litedramcore_roundrobin6_grant)
+    rhs_self30 <= 21'd0;
+    case (roundrobin6_grant)
         default: begin
-            rhs_array_muxed30 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
+            rhs_self30 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed31 <= 1'd0;
-    case (litedramcore_roundrobin6_grant)
+    rhs_self31 <= 1'd0;
+    case (roundrobin6_grant)
         default: begin
-            rhs_array_muxed31 <= soc_user_port_cmd_payload_we;
+            rhs_self31 <= soc_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed32 <= 1'd0;
-    case (litedramcore_roundrobin6_grant)
+    rhs_self32 <= 1'd0;
+    case (roundrobin6_grant)
         default: begin
-            rhs_array_muxed32 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+            rhs_self32 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed33 <= 21'd0;
-    case (litedramcore_roundrobin7_grant)
+    rhs_self33 <= 21'd0;
+    case (roundrobin7_grant)
         default: begin
-            rhs_array_muxed33 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
+            rhs_self33 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed34 <= 1'd0;
-    case (litedramcore_roundrobin7_grant)
+    rhs_self34 <= 1'd0;
+    case (roundrobin7_grant)
         default: begin
-            rhs_array_muxed34 <= soc_user_port_cmd_payload_we;
+            rhs_self34 <= soc_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed35 <= 1'd0;
-    case (litedramcore_roundrobin7_grant)
+    rhs_self35 <= 1'd0;
+    case (roundrobin7_grant)
         default: begin
-            rhs_array_muxed35 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid);
+            rhs_self35 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    array_muxed0 <= 3'd0;
-    case (soc_litedramcore_steerer_sel0)
+    self0 <= 3'd0;
+    case (soc_litedramcore_steerer0)
         1'd0: begin
-            array_muxed0 <= soc_litedramcore_nop_ba[2:0];
+            self0 <= soc_litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed0 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            self0 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed0 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
+            self0 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed0 <= soc_litedramcore_cmd_payload_ba[2:0];
+            self0 <= soc_litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed1 <= 14'd0;
-    case (soc_litedramcore_steerer_sel0)
+    self1 <= 14'd0;
+    case (soc_litedramcore_steerer0)
         1'd0: begin
-            array_muxed1 <= soc_litedramcore_nop_a;
+            self1 <= soc_litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed1 <= soc_litedramcore_choose_cmd_cmd_payload_a;
+            self1 <= soc_litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed1 <= soc_litedramcore_choose_req_cmd_payload_a;
+            self1 <= soc_litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed1 <= soc_litedramcore_cmd_payload_a;
+            self1 <= soc_litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed2 <= 1'd0;
-    case (soc_litedramcore_steerer_sel0)
+    self2 <= 1'd0;
+    case (soc_litedramcore_steerer0)
         1'd0: begin
-            array_muxed2 <= 1'd0;
+            self2 <= 1'd0;
         end
         1'd1: begin
-            array_muxed2 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
+            self2 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed2 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
+            self2 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed2 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
+            self2 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed3 <= 1'd0;
-    case (soc_litedramcore_steerer_sel0)
+    self3 <= 1'd0;
+    case (soc_litedramcore_steerer0)
         1'd0: begin
-            array_muxed3 <= 1'd0;
+            self3 <= 1'd0;
         end
         1'd1: begin
-            array_muxed3 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
+            self3 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed3 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
+            self3 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed3 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
+            self3 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed4 <= 1'd0;
-    case (soc_litedramcore_steerer_sel0)
+    self4 <= 1'd0;
+    case (soc_litedramcore_steerer0)
         1'd0: begin
-            array_muxed4 <= 1'd0;
+            self4 <= 1'd0;
         end
         1'd1: begin
-            array_muxed4 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
+            self4 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed4 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
+            self4 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed4 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
+            self4 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed5 <= 1'd0;
-    case (soc_litedramcore_steerer_sel0)
+    self5 <= 1'd0;
+    case (soc_litedramcore_steerer0)
         1'd0: begin
-            array_muxed5 <= 1'd0;
+            self5 <= 1'd0;
         end
         1'd1: begin
-            array_muxed5 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
+            self5 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed5 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
+            self5 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed5 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
+            self5 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed6 <= 1'd0;
-    case (soc_litedramcore_steerer_sel0)
+    self6 <= 1'd0;
+    case (soc_litedramcore_steerer0)
         1'd0: begin
-            array_muxed6 <= 1'd0;
+            self6 <= 1'd0;
         end
         1'd1: begin
-            array_muxed6 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
+            self6 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed6 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
+            self6 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed6 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
+            self6 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
         end
     endcase
 end
 always @(*) begin
-    array_muxed7 <= 3'd0;
-    case (soc_litedramcore_steerer_sel1)
+    self7 <= 3'd0;
+    case (soc_litedramcore_steerer1)
         1'd0: begin
-            array_muxed7 <= soc_litedramcore_nop_ba[2:0];
+            self7 <= soc_litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed7 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            self7 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed7 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
+            self7 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed7 <= soc_litedramcore_cmd_payload_ba[2:0];
+            self7 <= soc_litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed8 <= 14'd0;
-    case (soc_litedramcore_steerer_sel1)
+    self8 <= 14'd0;
+    case (soc_litedramcore_steerer1)
         1'd0: begin
-            array_muxed8 <= soc_litedramcore_nop_a;
+            self8 <= soc_litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed8 <= soc_litedramcore_choose_cmd_cmd_payload_a;
+            self8 <= soc_litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed8 <= soc_litedramcore_choose_req_cmd_payload_a;
+            self8 <= soc_litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed8 <= soc_litedramcore_cmd_payload_a;
+            self8 <= soc_litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed9 <= 1'd0;
-    case (soc_litedramcore_steerer_sel1)
+    self9 <= 1'd0;
+    case (soc_litedramcore_steerer1)
         1'd0: begin
-            array_muxed9 <= 1'd0;
+            self9 <= 1'd0;
         end
         1'd1: begin
-            array_muxed9 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
+            self9 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed9 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
+            self9 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed9 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
+            self9 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed10 <= 1'd0;
-    case (soc_litedramcore_steerer_sel1)
+    self10 <= 1'd0;
+    case (soc_litedramcore_steerer1)
         1'd0: begin
-            array_muxed10 <= 1'd0;
+            self10 <= 1'd0;
         end
         1'd1: begin
-            array_muxed10 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
+            self10 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed10 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
+            self10 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed10 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
+            self10 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed11 <= 1'd0;
-    case (soc_litedramcore_steerer_sel1)
+    self11 <= 1'd0;
+    case (soc_litedramcore_steerer1)
         1'd0: begin
-            array_muxed11 <= 1'd0;
+            self11 <= 1'd0;
         end
         1'd1: begin
-            array_muxed11 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
+            self11 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed11 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
+            self11 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed11 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
+            self11 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed12 <= 1'd0;
-    case (soc_litedramcore_steerer_sel1)
+    self12 <= 1'd0;
+    case (soc_litedramcore_steerer1)
         1'd0: begin
-            array_muxed12 <= 1'd0;
+            self12 <= 1'd0;
         end
         1'd1: begin
-            array_muxed12 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
+            self12 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed12 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
+            self12 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed12 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
+            self12 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed13 <= 1'd0;
-    case (soc_litedramcore_steerer_sel1)
+    self13 <= 1'd0;
+    case (soc_litedramcore_steerer1)
         1'd0: begin
-            array_muxed13 <= 1'd0;
+            self13 <= 1'd0;
         end
         1'd1: begin
-            array_muxed13 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
+            self13 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed13 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
+            self13 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed13 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
+            self13 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
         end
     endcase
 end
 always @(*) begin
-    array_muxed14 <= 3'd0;
-    case (soc_litedramcore_steerer_sel2)
+    self14 <= 3'd0;
+    case (soc_litedramcore_steerer2)
         1'd0: begin
-            array_muxed14 <= soc_litedramcore_nop_ba[2:0];
+            self14 <= soc_litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed14 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            self14 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed14 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
+            self14 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed14 <= soc_litedramcore_cmd_payload_ba[2:0];
+            self14 <= soc_litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed15 <= 14'd0;
-    case (soc_litedramcore_steerer_sel2)
+    self15 <= 14'd0;
+    case (soc_litedramcore_steerer2)
         1'd0: begin
-            array_muxed15 <= soc_litedramcore_nop_a;
+            self15 <= soc_litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed15 <= soc_litedramcore_choose_cmd_cmd_payload_a;
+            self15 <= soc_litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed15 <= soc_litedramcore_choose_req_cmd_payload_a;
+            self15 <= soc_litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed15 <= soc_litedramcore_cmd_payload_a;
+            self15 <= soc_litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed16 <= 1'd0;
-    case (soc_litedramcore_steerer_sel2)
+    self16 <= 1'd0;
+    case (soc_litedramcore_steerer2)
         1'd0: begin
-            array_muxed16 <= 1'd0;
+            self16 <= 1'd0;
         end
         1'd1: begin
-            array_muxed16 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
+            self16 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed16 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
+            self16 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed16 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
+            self16 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed17 <= 1'd0;
-    case (soc_litedramcore_steerer_sel2)
+    self17 <= 1'd0;
+    case (soc_litedramcore_steerer2)
         1'd0: begin
-            array_muxed17 <= 1'd0;
+            self17 <= 1'd0;
         end
         1'd1: begin
-            array_muxed17 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
+            self17 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed17 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
+            self17 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed17 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
+            self17 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed18 <= 1'd0;
-    case (soc_litedramcore_steerer_sel2)
+    self18 <= 1'd0;
+    case (soc_litedramcore_steerer2)
         1'd0: begin
-            array_muxed18 <= 1'd0;
+            self18 <= 1'd0;
         end
         1'd1: begin
-            array_muxed18 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
+            self18 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed18 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
+            self18 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed18 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
+            self18 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed19 <= 1'd0;
-    case (soc_litedramcore_steerer_sel2)
+    self19 <= 1'd0;
+    case (soc_litedramcore_steerer2)
         1'd0: begin
-            array_muxed19 <= 1'd0;
+            self19 <= 1'd0;
         end
         1'd1: begin
-            array_muxed19 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
+            self19 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed19 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
+            self19 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed19 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
+            self19 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed20 <= 1'd0;
-    case (soc_litedramcore_steerer_sel2)
+    self20 <= 1'd0;
+    case (soc_litedramcore_steerer2)
         1'd0: begin
-            array_muxed20 <= 1'd0;
+            self20 <= 1'd0;
         end
         1'd1: begin
-            array_muxed20 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
+            self20 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed20 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
+            self20 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed20 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
+            self20 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
         end
     endcase
 end
 always @(*) begin
-    array_muxed21 <= 3'd0;
-    case (soc_litedramcore_steerer_sel3)
+    self21 <= 3'd0;
+    case (soc_litedramcore_steerer3)
         1'd0: begin
-            array_muxed21 <= soc_litedramcore_nop_ba[2:0];
+            self21 <= soc_litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed21 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            self21 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed21 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
+            self21 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed21 <= soc_litedramcore_cmd_payload_ba[2:0];
+            self21 <= soc_litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed22 <= 14'd0;
-    case (soc_litedramcore_steerer_sel3)
+    self22 <= 14'd0;
+    case (soc_litedramcore_steerer3)
         1'd0: begin
-            array_muxed22 <= soc_litedramcore_nop_a;
+            self22 <= soc_litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed22 <= soc_litedramcore_choose_cmd_cmd_payload_a;
+            self22 <= soc_litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed22 <= soc_litedramcore_choose_req_cmd_payload_a;
+            self22 <= soc_litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed22 <= soc_litedramcore_cmd_payload_a;
+            self22 <= soc_litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed23 <= 1'd0;
-    case (soc_litedramcore_steerer_sel3)
+    self23 <= 1'd0;
+    case (soc_litedramcore_steerer3)
         1'd0: begin
-            array_muxed23 <= 1'd0;
+            self23 <= 1'd0;
         end
         1'd1: begin
-            array_muxed23 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
+            self23 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed23 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
+            self23 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed23 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
+            self23 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed24 <= 1'd0;
-    case (soc_litedramcore_steerer_sel3)
+    self24 <= 1'd0;
+    case (soc_litedramcore_steerer3)
         1'd0: begin
-            array_muxed24 <= 1'd0;
+            self24 <= 1'd0;
         end
         1'd1: begin
-            array_muxed24 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
+            self24 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed24 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
+            self24 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed24 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
+            self24 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed25 <= 1'd0;
-    case (soc_litedramcore_steerer_sel3)
+    self25 <= 1'd0;
+    case (soc_litedramcore_steerer3)
         1'd0: begin
-            array_muxed25 <= 1'd0;
+            self25 <= 1'd0;
         end
         1'd1: begin
-            array_muxed25 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
+            self25 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed25 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
+            self25 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed25 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
+            self25 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed26 <= 1'd0;
-    case (soc_litedramcore_steerer_sel3)
+    self26 <= 1'd0;
+    case (soc_litedramcore_steerer3)
         1'd0: begin
-            array_muxed26 <= 1'd0;
+            self26 <= 1'd0;
         end
         1'd1: begin
-            array_muxed26 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
+            self26 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed26 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
+            self26 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed26 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
+            self26 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed27 <= 1'd0;
-    case (soc_litedramcore_steerer_sel3)
+    self27 <= 1'd0;
+    case (soc_litedramcore_steerer3)
         1'd0: begin
-            array_muxed27 <= 1'd0;
+            self27 <= 1'd0;
         end
         1'd1: begin
-            array_muxed27 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
+            self27 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed27 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
+            self27 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed27 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
+            self27 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
         end
     endcase
 end
@@ -12268,21 +12527,21 @@ always @(posedge sys_clk) begin
     soc_litedramcore_cmd_payload_ras <= 1'd0;
     soc_litedramcore_cmd_payload_we <= 1'd0;
     soc_litedramcore_sequencer_done1 <= 1'd0;
-    if ((soc_litedramcore_sequencer_start1 & (soc_litedramcore_sequencer_counter == 1'd0))) begin
+    if ((soc_litedramcore_sequencer_start1 & (soc_litedramcore_sequencer_trigger == 1'd0))) begin
         soc_litedramcore_cmd_payload_a <= 11'd1024;
         soc_litedramcore_cmd_payload_ba <= 1'd0;
         soc_litedramcore_cmd_payload_cas <= 1'd0;
         soc_litedramcore_cmd_payload_ras <= 1'd1;
         soc_litedramcore_cmd_payload_we <= 1'd1;
     end
-    if ((soc_litedramcore_sequencer_counter == 2'd3)) begin
+    if ((soc_litedramcore_sequencer_trigger == 2'd3)) begin
         soc_litedramcore_cmd_payload_a <= 11'd1024;
         soc_litedramcore_cmd_payload_ba <= 1'd0;
         soc_litedramcore_cmd_payload_cas <= 1'd1;
         soc_litedramcore_cmd_payload_ras <= 1'd1;
         soc_litedramcore_cmd_payload_we <= 1'd0;
     end
-    if ((soc_litedramcore_sequencer_counter == 6'd35)) begin
+    if ((soc_litedramcore_sequencer_trigger == 6'd35)) begin
         soc_litedramcore_cmd_payload_a <= 1'd0;
         soc_litedramcore_cmd_payload_ba <= 1'd0;
         soc_litedramcore_cmd_payload_cas <= 1'd0;
@@ -12290,14 +12549,14 @@ always @(posedge sys_clk) begin
         soc_litedramcore_cmd_payload_we <= 1'd0;
         soc_litedramcore_sequencer_done1 <= 1'd1;
     end
-    if ((soc_litedramcore_sequencer_counter == 6'd35)) begin
-        soc_litedramcore_sequencer_counter <= 1'd0;
+    if ((soc_litedramcore_sequencer_trigger == 6'd35)) begin
+        soc_litedramcore_sequencer_trigger <= 1'd0;
     end else begin
-        if ((soc_litedramcore_sequencer_counter != 1'd0)) begin
-            soc_litedramcore_sequencer_counter <= (soc_litedramcore_sequencer_counter + 1'd1);
+        if ((soc_litedramcore_sequencer_trigger != 1'd0)) begin
+            soc_litedramcore_sequencer_trigger <= (soc_litedramcore_sequencer_trigger + 1'd1);
         end else begin
             if (soc_litedramcore_sequencer_start1) begin
-                soc_litedramcore_sequencer_counter <= 1'd1;
+                soc_litedramcore_sequencer_trigger <= 1'd1;
             end
         end
     end
@@ -12307,21 +12566,21 @@ always @(posedge sys_clk) begin
         soc_litedramcore_zqcs_timer_count1 <= 27'd99999999;
     end
     soc_litedramcore_zqcs_executer_done <= 1'd0;
-    if ((soc_litedramcore_zqcs_executer_start & (soc_litedramcore_zqcs_executer_counter == 1'd0))) begin
+    if ((soc_litedramcore_zqcs_executer_start & (soc_litedramcore_zqcs_executer_trigger == 1'd0))) begin
         soc_litedramcore_cmd_payload_a <= 11'd1024;
         soc_litedramcore_cmd_payload_ba <= 1'd0;
         soc_litedramcore_cmd_payload_cas <= 1'd0;
         soc_litedramcore_cmd_payload_ras <= 1'd1;
         soc_litedramcore_cmd_payload_we <= 1'd1;
     end
-    if ((soc_litedramcore_zqcs_executer_counter == 2'd3)) begin
+    if ((soc_litedramcore_zqcs_executer_trigger == 2'd3)) begin
         soc_litedramcore_cmd_payload_a <= 1'd0;
         soc_litedramcore_cmd_payload_ba <= 1'd0;
         soc_litedramcore_cmd_payload_cas <= 1'd0;
         soc_litedramcore_cmd_payload_ras <= 1'd0;
         soc_litedramcore_cmd_payload_we <= 1'd1;
     end
-    if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin
+    if ((soc_litedramcore_zqcs_executer_trigger == 5'd19)) begin
         soc_litedramcore_cmd_payload_a <= 1'd0;
         soc_litedramcore_cmd_payload_ba <= 1'd0;
         soc_litedramcore_cmd_payload_cas <= 1'd0;
@@ -12329,18 +12588,18 @@ always @(posedge sys_clk) begin
         soc_litedramcore_cmd_payload_we <= 1'd0;
         soc_litedramcore_zqcs_executer_done <= 1'd1;
     end
-    if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin
-        soc_litedramcore_zqcs_executer_counter <= 1'd0;
+    if ((soc_litedramcore_zqcs_executer_trigger == 5'd19)) begin
+        soc_litedramcore_zqcs_executer_trigger <= 1'd0;
     end else begin
-        if ((soc_litedramcore_zqcs_executer_counter != 1'd0)) begin
-            soc_litedramcore_zqcs_executer_counter <= (soc_litedramcore_zqcs_executer_counter + 1'd1);
+        if ((soc_litedramcore_zqcs_executer_trigger != 1'd0)) begin
+            soc_litedramcore_zqcs_executer_trigger <= (soc_litedramcore_zqcs_executer_trigger + 1'd1);
         end else begin
             if (soc_litedramcore_zqcs_executer_start) begin
-                soc_litedramcore_zqcs_executer_counter <= 1'd1;
+                soc_litedramcore_zqcs_executer_trigger <= 1'd1;
             end
         end
     end
-    litedramcore_refresher_state <= litedramcore_refresher_next_state;
+    refresher_state <= refresher_next_state;
     if (soc_litedramcore_bankmachine0_row_close) begin
         soc_litedramcore_bankmachine0_row_opened <= 1'd0;
     end else begin
@@ -12416,7 +12675,7 @@ always @(posedge sys_clk) begin
             end
         end
     end
-    litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
+    bankmachine0_state <= bankmachine0_next_state;
     if (soc_litedramcore_bankmachine1_row_close) begin
         soc_litedramcore_bankmachine1_row_opened <= 1'd0;
     end else begin
@@ -12492,7 +12751,7 @@ always @(posedge sys_clk) begin
             end
         end
     end
-    litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
+    bankmachine1_state <= bankmachine1_next_state;
     if (soc_litedramcore_bankmachine2_row_close) begin
         soc_litedramcore_bankmachine2_row_opened <= 1'd0;
     end else begin
@@ -12568,7 +12827,7 @@ always @(posedge sys_clk) begin
             end
         end
     end
-    litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
+    bankmachine2_state <= bankmachine2_next_state;
     if (soc_litedramcore_bankmachine3_row_close) begin
         soc_litedramcore_bankmachine3_row_opened <= 1'd0;
     end else begin
@@ -12644,7 +12903,7 @@ always @(posedge sys_clk) begin
             end
         end
     end
-    litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
+    bankmachine3_state <= bankmachine3_next_state;
     if (soc_litedramcore_bankmachine4_row_close) begin
         soc_litedramcore_bankmachine4_row_opened <= 1'd0;
     end else begin
@@ -12720,7 +12979,7 @@ always @(posedge sys_clk) begin
             end
         end
     end
-    litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
+    bankmachine4_state <= bankmachine4_next_state;
     if (soc_litedramcore_bankmachine5_row_close) begin
         soc_litedramcore_bankmachine5_row_opened <= 1'd0;
     end else begin
@@ -12796,7 +13055,7 @@ always @(posedge sys_clk) begin
             end
         end
     end
-    litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
+    bankmachine5_state <= bankmachine5_next_state;
     if (soc_litedramcore_bankmachine6_row_close) begin
         soc_litedramcore_bankmachine6_row_opened <= 1'd0;
     end else begin
@@ -12872,7 +13131,7 @@ always @(posedge sys_clk) begin
             end
         end
     end
-    litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
+    bankmachine6_state <= bankmachine6_next_state;
     if (soc_litedramcore_bankmachine7_row_close) begin
         soc_litedramcore_bankmachine7_row_opened <= 1'd0;
     end else begin
@@ -12948,7 +13207,7 @@ always @(posedge sys_clk) begin
             end
         end
     end
-    litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
+    bankmachine7_state <= bankmachine7_next_state;
     if ((~soc_litedramcore_en0)) begin
         soc_litedramcore_time0 <= 5'd31;
     end else begin
@@ -13436,37 +13695,37 @@ always @(posedge sys_clk) begin
         endcase
     end
     soc_litedramcore_dfi_p0_cs_n <= 1'd0;
-    soc_litedramcore_dfi_p0_bank <= array_muxed0;
-    soc_litedramcore_dfi_p0_address <= array_muxed1;
-    soc_litedramcore_dfi_p0_cas_n <= (~array_muxed2);
-    soc_litedramcore_dfi_p0_ras_n <= (~array_muxed3);
-    soc_litedramcore_dfi_p0_we_n <= (~array_muxed4);
-    soc_litedramcore_dfi_p0_rddata_en <= array_muxed5;
-    soc_litedramcore_dfi_p0_wrdata_en <= array_muxed6;
+    soc_litedramcore_dfi_p0_bank <= self0;
+    soc_litedramcore_dfi_p0_address <= self1;
+    soc_litedramcore_dfi_p0_cas_n <= (~self2);
+    soc_litedramcore_dfi_p0_ras_n <= (~self3);
+    soc_litedramcore_dfi_p0_we_n <= (~self4);
+    soc_litedramcore_dfi_p0_rddata_en <= self5;
+    soc_litedramcore_dfi_p0_wrdata_en <= self6;
     soc_litedramcore_dfi_p1_cs_n <= 1'd0;
-    soc_litedramcore_dfi_p1_bank <= array_muxed7;
-    soc_litedramcore_dfi_p1_address <= array_muxed8;
-    soc_litedramcore_dfi_p1_cas_n <= (~array_muxed9);
-    soc_litedramcore_dfi_p1_ras_n <= (~array_muxed10);
-    soc_litedramcore_dfi_p1_we_n <= (~array_muxed11);
-    soc_litedramcore_dfi_p1_rddata_en <= array_muxed12;
-    soc_litedramcore_dfi_p1_wrdata_en <= array_muxed13;
+    soc_litedramcore_dfi_p1_bank <= self7;
+    soc_litedramcore_dfi_p1_address <= self8;
+    soc_litedramcore_dfi_p1_cas_n <= (~self9);
+    soc_litedramcore_dfi_p1_ras_n <= (~self10);
+    soc_litedramcore_dfi_p1_we_n <= (~self11);
+    soc_litedramcore_dfi_p1_rddata_en <= self12;
+    soc_litedramcore_dfi_p1_wrdata_en <= self13;
     soc_litedramcore_dfi_p2_cs_n <= 1'd0;
-    soc_litedramcore_dfi_p2_bank <= array_muxed14;
-    soc_litedramcore_dfi_p2_address <= array_muxed15;
-    soc_litedramcore_dfi_p2_cas_n <= (~array_muxed16);
-    soc_litedramcore_dfi_p2_ras_n <= (~array_muxed17);
-    soc_litedramcore_dfi_p2_we_n <= (~array_muxed18);
-    soc_litedramcore_dfi_p2_rddata_en <= array_muxed19;
-    soc_litedramcore_dfi_p2_wrdata_en <= array_muxed20;
+    soc_litedramcore_dfi_p2_bank <= self14;
+    soc_litedramcore_dfi_p2_address <= self15;
+    soc_litedramcore_dfi_p2_cas_n <= (~self16);
+    soc_litedramcore_dfi_p2_ras_n <= (~self17);
+    soc_litedramcore_dfi_p2_we_n <= (~self18);
+    soc_litedramcore_dfi_p2_rddata_en <= self19;
+    soc_litedramcore_dfi_p2_wrdata_en <= self20;
     soc_litedramcore_dfi_p3_cs_n <= 1'd0;
-    soc_litedramcore_dfi_p3_bank <= array_muxed21;
-    soc_litedramcore_dfi_p3_address <= array_muxed22;
-    soc_litedramcore_dfi_p3_cas_n <= (~array_muxed23);
-    soc_litedramcore_dfi_p3_ras_n <= (~array_muxed24);
-    soc_litedramcore_dfi_p3_we_n <= (~array_muxed25);
-    soc_litedramcore_dfi_p3_rddata_en <= array_muxed26;
-    soc_litedramcore_dfi_p3_wrdata_en <= array_muxed27;
+    soc_litedramcore_dfi_p3_bank <= self21;
+    soc_litedramcore_dfi_p3_address <= self22;
+    soc_litedramcore_dfi_p3_cas_n <= (~self23);
+    soc_litedramcore_dfi_p3_ras_n <= (~self24);
+    soc_litedramcore_dfi_p3_we_n <= (~self25);
+    soc_litedramcore_dfi_p3_rddata_en <= self26;
+    soc_litedramcore_dfi_p3_wrdata_en <= self27;
     if (soc_litedramcore_trrdcon_valid) begin
         soc_litedramcore_trrdcon_count <= 1'd1;
         if (1'd0) begin
@@ -13520,27 +13779,27 @@ always @(posedge sys_clk) begin
             end
         end
     end
-    litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
-    litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_wdata_ready));
-    litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
-    litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_rdata_valid));
-    litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
-    litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
-    litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
-    litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
-    litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
-    litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
-    litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
-    litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
-    litedramcore_state <= litedramcore_next_state;
-    if (litedramcore_dat_w_next_value_ce0) begin
-        litedramcore_dat_w <= litedramcore_dat_w_next_value0;
+    multiplexer_state <= multiplexer_next_state;
+    new_master_wdata_ready0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_wdata_ready)) | ((roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_wdata_ready)) | ((roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_wdata_ready)) | ((roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_wdata_ready)) | ((roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_wdata_ready)) | ((roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_wdata_ready)) | ((roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_wdata_ready)) | ((roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_wdata_ready));
+    new_master_wdata_ready1 <= new_master_wdata_ready0;
+    new_master_rdata_valid0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_rdata_valid)) | ((roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_rdata_valid)) | ((roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_rdata_valid)) | ((roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_rdata_valid)) | ((roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_rdata_valid)) | ((roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_rdata_valid)) | ((roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_rdata_valid)) | ((roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_rdata_valid));
+    new_master_rdata_valid1 <= new_master_rdata_valid0;
+    new_master_rdata_valid2 <= new_master_rdata_valid1;
+    new_master_rdata_valid3 <= new_master_rdata_valid2;
+    new_master_rdata_valid4 <= new_master_rdata_valid3;
+    new_master_rdata_valid5 <= new_master_rdata_valid4;
+    new_master_rdata_valid6 <= new_master_rdata_valid5;
+    new_master_rdata_valid7 <= new_master_rdata_valid6;
+    new_master_rdata_valid8 <= new_master_rdata_valid7;
+    state <= next_state;
+    if (interface1_dat_w_next_value_ce0) begin
+        interface1_dat_w <= interface1_dat_w_next_value0;
     end
-    if (litedramcore_adr_next_value_ce1) begin
-        litedramcore_adr <= litedramcore_adr_next_value1;
+    if (interface1_adr_next_value_ce1) begin
+        interface1_adr <= interface1_adr_next_value1;
     end
-    if (litedramcore_we_next_value_ce2) begin
-        litedramcore_we <= litedramcore_we_next_value2;
+    if (interface1_we_next_value_ce2) begin
+        interface1_we <= interface1_we_next_value2;
     end
     interface0_bank_bus_dat_r <= 1'd0;
     if (csrbank0_sel) begin
@@ -13646,7 +13905,7 @@ always @(posedge sys_clk) begin
     end
     soc_litedramcore_re <= csrbank1_dfii_control0_re;
     if (csrbank1_dfii_pi0_command0_re) begin
-        soc_litedramcore_phaseinjector0_command_storage[5:0] <= csrbank1_dfii_pi0_command0_r;
+        soc_litedramcore_phaseinjector0_command_storage[7:0] <= csrbank1_dfii_pi0_command0_r;
     end
     soc_litedramcore_phaseinjector0_command_re <= csrbank1_dfii_pi0_command0_re;
     if (csrbank1_dfii_pi0_address0_re) begin
@@ -13663,7 +13922,7 @@ always @(posedge sys_clk) begin
     soc_litedramcore_phaseinjector0_wrdata_re <= csrbank1_dfii_pi0_wrdata0_re;
     soc_litedramcore_phaseinjector0_rddata_re <= csrbank1_dfii_pi0_rddata_re;
     if (csrbank1_dfii_pi1_command0_re) begin
-        soc_litedramcore_phaseinjector1_command_storage[5:0] <= csrbank1_dfii_pi1_command0_r;
+        soc_litedramcore_phaseinjector1_command_storage[7:0] <= csrbank1_dfii_pi1_command0_r;
     end
     soc_litedramcore_phaseinjector1_command_re <= csrbank1_dfii_pi1_command0_re;
     if (csrbank1_dfii_pi1_address0_re) begin
@@ -13680,7 +13939,7 @@ always @(posedge sys_clk) begin
     soc_litedramcore_phaseinjector1_wrdata_re <= csrbank1_dfii_pi1_wrdata0_re;
     soc_litedramcore_phaseinjector1_rddata_re <= csrbank1_dfii_pi1_rddata_re;
     if (csrbank1_dfii_pi2_command0_re) begin
-        soc_litedramcore_phaseinjector2_command_storage[5:0] <= csrbank1_dfii_pi2_command0_r;
+        soc_litedramcore_phaseinjector2_command_storage[7:0] <= csrbank1_dfii_pi2_command0_r;
     end
     soc_litedramcore_phaseinjector2_command_re <= csrbank1_dfii_pi2_command0_re;
     if (csrbank1_dfii_pi2_address0_re) begin
@@ -13697,7 +13956,7 @@ always @(posedge sys_clk) begin
     soc_litedramcore_phaseinjector2_wrdata_re <= csrbank1_dfii_pi2_wrdata0_re;
     soc_litedramcore_phaseinjector2_rddata_re <= csrbank1_dfii_pi2_rddata_re;
     if (csrbank1_dfii_pi3_command0_re) begin
-        soc_litedramcore_phaseinjector3_command_storage[5:0] <= csrbank1_dfii_pi3_command0_r;
+        soc_litedramcore_phaseinjector3_command_storage[7:0] <= csrbank1_dfii_pi3_command0_r;
     end
     soc_litedramcore_phaseinjector3_command_re <= csrbank1_dfii_pi3_command0_re;
     if (csrbank1_dfii_pi3_address0_re) begin
@@ -13764,28 +14023,28 @@ always @(posedge sys_clk) begin
         soc_ddrphy_new_banks_read_data7 <= 128'd0;
         soc_litedramcore_storage <= 4'd1;
         soc_litedramcore_re <= 1'd0;
-        soc_litedramcore_phaseinjector0_command_storage <= 6'd0;
+        soc_litedramcore_phaseinjector0_command_storage <= 8'd0;
         soc_litedramcore_phaseinjector0_command_re <= 1'd0;
         soc_litedramcore_phaseinjector0_address_re <= 1'd0;
         soc_litedramcore_phaseinjector0_baddress_re <= 1'd0;
         soc_litedramcore_phaseinjector0_wrdata_re <= 1'd0;
         soc_litedramcore_phaseinjector0_rddata_status <= 32'd0;
         soc_litedramcore_phaseinjector0_rddata_re <= 1'd0;
-        soc_litedramcore_phaseinjector1_command_storage <= 6'd0;
+        soc_litedramcore_phaseinjector1_command_storage <= 8'd0;
         soc_litedramcore_phaseinjector1_command_re <= 1'd0;
         soc_litedramcore_phaseinjector1_address_re <= 1'd0;
         soc_litedramcore_phaseinjector1_baddress_re <= 1'd0;
         soc_litedramcore_phaseinjector1_wrdata_re <= 1'd0;
         soc_litedramcore_phaseinjector1_rddata_status <= 32'd0;
         soc_litedramcore_phaseinjector1_rddata_re <= 1'd0;
-        soc_litedramcore_phaseinjector2_command_storage <= 6'd0;
+        soc_litedramcore_phaseinjector2_command_storage <= 8'd0;
         soc_litedramcore_phaseinjector2_command_re <= 1'd0;
         soc_litedramcore_phaseinjector2_address_re <= 1'd0;
         soc_litedramcore_phaseinjector2_baddress_re <= 1'd0;
         soc_litedramcore_phaseinjector2_wrdata_re <= 1'd0;
         soc_litedramcore_phaseinjector2_rddata_status <= 32'd0;
         soc_litedramcore_phaseinjector2_rddata_re <= 1'd0;
-        soc_litedramcore_phaseinjector3_command_storage <= 6'd0;
+        soc_litedramcore_phaseinjector3_command_storage <= 8'd0;
         soc_litedramcore_phaseinjector3_command_re <= 1'd0;
         soc_litedramcore_phaseinjector3_address_re <= 1'd0;
         soc_litedramcore_phaseinjector3_baddress_re <= 1'd0;
@@ -13833,11 +14092,11 @@ always @(posedge sys_clk) begin
         soc_litedramcore_postponer_req_o <= 1'd0;
         soc_litedramcore_postponer_count <= 1'd0;
         soc_litedramcore_sequencer_done1 <= 1'd0;
-        soc_litedramcore_sequencer_counter <= 6'd0;
+        soc_litedramcore_sequencer_trigger <= 6'd0;
         soc_litedramcore_sequencer_count <= 1'd0;
         soc_litedramcore_zqcs_timer_count1 <= 27'd99999999;
         soc_litedramcore_zqcs_executer_done <= 1'd0;
-        soc_litedramcore_zqcs_executer_counter <= 5'd0;
+        soc_litedramcore_zqcs_executer_trigger <= 5'd0;
         soc_litedramcore_bankmachine0_level <= 5'd0;
         soc_litedramcore_bankmachine0_produce <= 4'd0;
         soc_litedramcore_bankmachine0_consume <= 4'd0;
@@ -13966,29 +14225,29 @@ always @(posedge sys_clk) begin
         soc_init_done_re <= 1'd0;
         soc_init_error_storage <= 1'd0;
         soc_init_error_re <= 1'd0;
-        litedramcore_we <= 1'd0;
-        litedramcore_refresher_state <= 2'd0;
-        litedramcore_bankmachine0_state <= 4'd0;
-        litedramcore_bankmachine1_state <= 4'd0;
-        litedramcore_bankmachine2_state <= 4'd0;
-        litedramcore_bankmachine3_state <= 4'd0;
-        litedramcore_bankmachine4_state <= 4'd0;
-        litedramcore_bankmachine5_state <= 4'd0;
-        litedramcore_bankmachine6_state <= 4'd0;
-        litedramcore_bankmachine7_state <= 4'd0;
-        litedramcore_multiplexer_state <= 4'd0;
-        litedramcore_new_master_wdata_ready0 <= 1'd0;
-        litedramcore_new_master_wdata_ready1 <= 1'd0;
-        litedramcore_new_master_rdata_valid0 <= 1'd0;
-        litedramcore_new_master_rdata_valid1 <= 1'd0;
-        litedramcore_new_master_rdata_valid2 <= 1'd0;
-        litedramcore_new_master_rdata_valid3 <= 1'd0;
-        litedramcore_new_master_rdata_valid4 <= 1'd0;
-        litedramcore_new_master_rdata_valid5 <= 1'd0;
-        litedramcore_new_master_rdata_valid6 <= 1'd0;
-        litedramcore_new_master_rdata_valid7 <= 1'd0;
-        litedramcore_new_master_rdata_valid8 <= 1'd0;
-        litedramcore_state <= 2'd0;
+        interface1_we <= 1'd0;
+        refresher_state <= 2'd0;
+        bankmachine0_state <= 4'd0;
+        bankmachine1_state <= 4'd0;
+        bankmachine2_state <= 4'd0;
+        bankmachine3_state <= 4'd0;
+        bankmachine4_state <= 4'd0;
+        bankmachine5_state <= 4'd0;
+        bankmachine6_state <= 4'd0;
+        bankmachine7_state <= 4'd0;
+        multiplexer_state <= 4'd0;
+        new_master_wdata_ready0 <= 1'd0;
+        new_master_wdata_ready1 <= 1'd0;
+        new_master_rdata_valid0 <= 1'd0;
+        new_master_rdata_valid1 <= 1'd0;
+        new_master_rdata_valid2 <= 1'd0;
+        new_master_rdata_valid3 <= 1'd0;
+        new_master_rdata_valid4 <= 1'd0;
+        new_master_rdata_valid5 <= 1'd0;
+        new_master_rdata_valid6 <= 1'd0;
+        new_master_rdata_valid7 <= 1'd0;
+        new_master_rdata_valid8 <= 1'd0;
+        state <= 2'd0;
     end
 end
 
@@ -14528,5 +14787,5 @@ assign soc_litedramcore_bankmachine7_rdport_dat_r = storage_7[soc_litedramcore_b
 endmodule
 
 // -----------------------------------------------------------------------------
-//  Auto-Generated by LiteX on 2022-10-28 19:01:27.
+//  Auto-Generated by LiteX on 2024-04-01 10:12:12.
 //------------------------------------------------------------------------------
diff --git a/litedram/generated/wukong-v2/litedram_core.init b/litedram/generated/wukong-v2/litedram_core.init
index 61e54f3..0573632 100644
--- a/litedram/generated/wukong-v2/litedram_core.init
+++ b/litedram/generated/wukong-v2/litedram_core.init
@@ -7,7 +7,7 @@ a64b5a7d14004a39
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 798c07c6618c0000
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 4e8004207c6903a6
 0000000000000000
@@ -510,677 +510,687 @@ a64b5a7d14004a39
 0000000000000000
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 0000000000004269
diff --git a/litedram/generated/wukong-v2/litedram_core.v b/litedram/generated/wukong-v2/litedram_core.v
index 4196f91..d66961b 100644
--- a/litedram/generated/wukong-v2/litedram_core.v
+++ b/litedram/generated/wukong-v2/litedram_core.v
@@ -8,10 +8,11 @@
 //
 // Filename   : litedram_core.v
 // Device     : 
-// LiteX sha1 : --------
-// Date       : 2022-10-28 19:01:24
+// LiteX sha1 : 87137c30
+// Date       : 2024-04-01 10:12:10
 //------------------------------------------------------------------------------
 
+`timescale 1ns / 1ps
 
 //------------------------------------------------------------------------------
 // Module
@@ -19,4868 +20,5285 @@
 
 module litedram_core (
     input  wire          clk,
-    input  wire          rst,
-    output wire          pll_locked,
     output wire   [13:0] ddram_a,
     output wire    [2:0] ddram_ba,
-    output wire          ddram_ras_n,
     output wire          ddram_cas_n,
-    output wire          ddram_we_n,
+    output wire          ddram_cke,
+    output wire          ddram_clk_n,
+    output wire          ddram_clk_p,
     output wire          ddram_cs_n,
     output wire    [1:0] ddram_dm,
     inout  wire   [15:0] ddram_dq,
-    inout  wire    [1:0] ddram_dqs_p,
     inout  wire    [1:0] ddram_dqs_n,
-    output wire          ddram_clk_p,
-    output wire          ddram_clk_n,
-    output wire          ddram_cke,
+    inout  wire    [1:0] ddram_dqs_p,
     output wire          ddram_odt,
+    output wire          ddram_ras_n,
     output wire          ddram_reset_n,
+    output wire          ddram_we_n,
     output wire          init_done,
     output wire          init_error,
-    input  wire   [29:0] wb_ctrl_adr,
-    input  wire   [31:0] wb_ctrl_dat_w,
-    output wire   [31:0] wb_ctrl_dat_r,
-    input  wire    [3:0] wb_ctrl_sel,
-    input  wire          wb_ctrl_cyc,
-    input  wire          wb_ctrl_stb,
-    output wire          wb_ctrl_ack,
-    input  wire          wb_ctrl_we,
-    input  wire    [2:0] wb_ctrl_cti,
-    input  wire    [1:0] wb_ctrl_bte,
-    output wire          wb_ctrl_err,
+    output wire          pll_locked,
+    input  wire          rst,
     output wire          user_clk,
-    output wire          user_rst,
-    input  wire          user_port_native_0_cmd_valid,
+    input  wire   [23:0] user_port_native_0_cmd_addr,
     output wire          user_port_native_0_cmd_ready,
+    input  wire          user_port_native_0_cmd_valid,
     input  wire          user_port_native_0_cmd_we,
-    input  wire   [23:0] user_port_native_0_cmd_addr,
-    input  wire          user_port_native_0_wdata_valid,
+    output wire  [127:0] user_port_native_0_rdata_data,
+    input  wire          user_port_native_0_rdata_ready,
+    output wire          user_port_native_0_rdata_valid,
+    input  wire  [127:0] user_port_native_0_wdata_data,
     output wire          user_port_native_0_wdata_ready,
+    input  wire          user_port_native_0_wdata_valid,
     input  wire   [15:0] user_port_native_0_wdata_we,
-    input  wire  [127:0] user_port_native_0_wdata_data,
-    output wire          user_port_native_0_rdata_valid,
-    input  wire          user_port_native_0_rdata_ready,
-    output wire  [127:0] user_port_native_0_rdata_data
+    output wire          user_rst,
+    output wire          wb_ctrl_ack,
+    input  wire   [29:0] wb_ctrl_adr,
+    input  wire    [1:0] wb_ctrl_bte,
+    input  wire    [2:0] wb_ctrl_cti,
+    input  wire          wb_ctrl_cyc,
+    output wire   [31:0] wb_ctrl_dat_r,
+    input  wire   [31:0] wb_ctrl_dat_w,
+    output wire          wb_ctrl_err,
+    input  wire    [3:0] wb_ctrl_sel,
+    input  wire          wb_ctrl_stb,
+    input  wire          wb_ctrl_we
 );
 
 
+//------------------------------------------------------------------------------
+// Hierarchy
+//------------------------------------------------------------------------------
+
+/*
+LiteDRAMCore
+└─── bus (SoCBusHandler)
+│    └─── _interconnect (InterconnectPointToPoint)
+└─── csr (SoCCSRHandler)
+└─── irq (SoCIRQHandler)
+└─── cpu (CPUNone)
+└─── crg (LiteDRAMS7DDRPHYCRG)
+│    └─── pll (S7PLL)
+│    │    └─── [FDCE]
+│    │    └─── [BUFG]
+│    │    └─── [FDCE]
+│    │    └─── [BUFG]
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [BUFG]
+│    │    └─── [BUFG]
+│    │    └─── [PLLE2_ADV]
+│    └─── idelayctrl (S7IDELAYCTRL)
+│    │    └─── [IDELAYCTRL]
+└─── ddrphy (A7DDRPHY)
+│    └─── tappeddelayline_0* (TappedDelayLine)
+│    └─── dqspattern_0* (DQSPattern)
+│    └─── bitslip_0* (BitSlip)
+│    └─── bitslip_1* (BitSlip)
+│    └─── bitslip_2* (BitSlip)
+│    └─── bitslip_3* (BitSlip)
+│    └─── tappeddelayline_1* (TappedDelayLine)
+│    └─── bitslip_4* (BitSlip)
+│    └─── bitslip_5* (BitSlip)
+│    └─── bitslip_6* (BitSlip)
+│    └─── bitslip_7* (BitSlip)
+│    └─── bitslip_8* (BitSlip)
+│    └─── bitslip_9* (BitSlip)
+│    └─── bitslip_10* (BitSlip)
+│    └─── bitslip_11* (BitSlip)
+│    └─── bitslip_12* (BitSlip)
+│    └─── bitslip_13* (BitSlip)
+│    └─── bitslip_14* (BitSlip)
+│    └─── bitslip_15* (BitSlip)
+│    └─── bitslip_16* (BitSlip)
+│    └─── bitslip_17* (BitSlip)
+│    └─── bitslip_18* (BitSlip)
+│    └─── bitslip_19* (BitSlip)
+│    └─── bitslip_20* (BitSlip)
+│    └─── bitslip_21* (BitSlip)
+│    └─── bitslip_22* (BitSlip)
+│    └─── bitslip_23* (BitSlip)
+│    └─── bitslip_24* (BitSlip)
+│    └─── bitslip_25* (BitSlip)
+│    └─── bitslip_26* (BitSlip)
+│    └─── bitslip_27* (BitSlip)
+│    └─── bitslip_28* (BitSlip)
+│    └─── bitslip_29* (BitSlip)
+│    └─── bitslip_30* (BitSlip)
+│    └─── bitslip_31* (BitSlip)
+│    └─── bitslip_32* (BitSlip)
+│    └─── bitslip_33* (BitSlip)
+│    └─── bitslip_34* (BitSlip)
+│    └─── bitslip_35* (BitSlip)
+│    └─── tappeddelayline_2* (TappedDelayLine)
+│    └─── tappeddelayline_3* (TappedDelayLine)
+│    └─── [IOBUF]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [OBUFDS]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUFDS]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IOBUFDS]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [IOBUF]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [IDELAYE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [IOBUF]
+│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+└─── sdram (LiteDRAMCore)
+│    └─── dfii (DFIInjector)
+│    │    └─── pi0 (PhaseInjector)
+│    │    └─── pi1 (PhaseInjector)
+│    │    └─── pi2 (PhaseInjector)
+│    │    └─── pi3 (PhaseInjector)
+│    └─── controller (LiteDRAMController)
+│    │    └─── refresher (Refresher)
+│    │    │    └─── timer (RefreshTimer)
+│    │    │    └─── postponer (RefreshPostponer)
+│    │    │    └─── sequencer (RefreshSequencer)
+│    │    │    │    └─── refreshexecuter_0* (RefreshExecuter)
+│    │    │    └─── zqcs_timer (RefreshTimer)
+│    │    │    └─── zqs_executer (ZQCSExecuter)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_0* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_1* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_2* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_3* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_4* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_5* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_6* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── bankmachine_7* (BankMachine)
+│    │    │    └─── syncfifo_0* (SyncFIFO)
+│    │    │    │    └─── fifo (SyncFIFO)
+│    │    │    └─── buffer_0* (Buffer)
+│    │    │    │    └─── pipe_valid (PipeValid)
+│    │    │    │    └─── pipeline (Pipeline)
+│    │    │    └─── twtpcon (tXXDController)
+│    │    │    └─── trccon (tXXDController)
+│    │    │    └─── trascon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    │    └─── multiplexer (Multiplexer)
+│    │    │    └─── choose_cmd (_CommandChooser)
+│    │    │    │    └─── roundrobin_0* (RoundRobin)
+│    │    │    └─── choose_req (_CommandChooser)
+│    │    │    │    └─── roundrobin_0* (RoundRobin)
+│    │    │    └─── _steerer_0* (_Steerer)
+│    │    │    └─── trrdcon (tXXDController)
+│    │    │    └─── tfawcon (tFAWController)
+│    │    │    └─── tccdcon (tXXDController)
+│    │    │    └─── twtrcon (tXXDController)
+│    │    │    └─── fsm (FSM)
+│    └─── crossbar (LiteDRAMCrossbar)
+│    │    └─── roundrobin_0* (RoundRobin)
+│    │    └─── roundrobin_1* (RoundRobin)
+│    │    └─── roundrobin_2* (RoundRobin)
+│    │    └─── roundrobin_3* (RoundRobin)
+│    │    └─── roundrobin_4* (RoundRobin)
+│    │    └─── roundrobin_5* (RoundRobin)
+│    │    └─── roundrobin_6* (RoundRobin)
+│    │    └─── roundrobin_7* (RoundRobin)
+└─── ddrctrl (LiteDRAMCoreControl)
+└─── csr_bridge (Wishbone2CSR)
+│    └─── fsm (FSM)
+└─── csr_bankarray (CSRBankArray)
+│    └─── csrbank_0* (CSRBank)
+│    │    └─── csrstorage_0* (CSRStorage)
+│    │    └─── csrstorage_1* (CSRStorage)
+│    └─── csrbank_1* (CSRBank)
+│    │    └─── csrstorage_0* (CSRStorage)
+│    │    └─── csrstorage_1* (CSRStorage)
+│    │    └─── csrstorage_2* (CSRStorage)
+│    │    └─── csrstorage_3* (CSRStorage)
+│    │    └─── csrstorage_4* (CSRStorage)
+│    │    └─── csrstorage_5* (CSRStorage)
+│    └─── csrbank_2* (CSRBank)
+│    │    └─── csrstorage_0* (CSRStorage)
+│    │    └─── csrstorage_1* (CSRStorage)
+│    │    └─── csrstorage_2* (CSRStorage)
+│    │    └─── csrstorage_3* (CSRStorage)
+│    │    └─── csrstorage_4* (CSRStorage)
+│    │    └─── csrstatus_0* (CSRStatus)
+│    │    └─── csrstorage_5* (CSRStorage)
+│    │    └─── csrstorage_6* (CSRStorage)
+│    │    └─── csrstorage_7* (CSRStorage)
+│    │    └─── csrstorage_8* (CSRStorage)
+│    │    └─── csrstatus_1* (CSRStatus)
+│    │    └─── csrstorage_9* (CSRStorage)
+│    │    └─── csrstorage_10* (CSRStorage)
+│    │    └─── csrstorage_11* (CSRStorage)
+│    │    └─── csrstorage_12* (CSRStorage)
+│    │    └─── csrstatus_2* (CSRStatus)
+│    │    └─── csrstorage_13* (CSRStorage)
+│    │    └─── csrstorage_14* (CSRStorage)
+│    │    └─── csrstorage_15* (CSRStorage)
+│    │    └─── csrstorage_16* (CSRStorage)
+│    │    └─── csrstatus_3* (CSRStatus)
+└─── csr_interconnect (InterconnectShared)
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+└─── [FDPE]
+* : Generated name.
+[]: BlackBox.
+*/
+
 //------------------------------------------------------------------------------
 // Signals
 //------------------------------------------------------------------------------
 
-reg           rst_1 = 1'd0;
-wire          sys_clk;
-wire          sys_rst;
-wire          sys4x_clk;
-wire          sys4x_dqs_clk;
+wire   [13:0] builder_adr;
+reg     [3:0] builder_bankmachine0_next_state = 4'd0;
+reg     [3:0] builder_bankmachine0_state = 4'd0;
+reg     [3:0] builder_bankmachine1_next_state = 4'd0;
+reg     [3:0] builder_bankmachine1_state = 4'd0;
+reg     [3:0] builder_bankmachine2_next_state = 4'd0;
+reg     [3:0] builder_bankmachine2_state = 4'd0;
+reg     [3:0] builder_bankmachine3_next_state = 4'd0;
+reg     [3:0] builder_bankmachine3_state = 4'd0;
+reg     [3:0] builder_bankmachine4_next_state = 4'd0;
+reg     [3:0] builder_bankmachine4_state = 4'd0;
+reg     [3:0] builder_bankmachine5_next_state = 4'd0;
+reg     [3:0] builder_bankmachine5_state = 4'd0;
+reg     [3:0] builder_bankmachine6_next_state = 4'd0;
+reg     [3:0] builder_bankmachine6_state = 4'd0;
+reg     [3:0] builder_bankmachine7_next_state = 4'd0;
+reg     [3:0] builder_bankmachine7_state = 4'd0;
+wire          builder_csrbank0_init_done0_r;
+reg           builder_csrbank0_init_done0_re = 1'd0;
+wire          builder_csrbank0_init_done0_w;
+reg           builder_csrbank0_init_done0_we = 1'd0;
+wire          builder_csrbank0_init_error0_r;
+reg           builder_csrbank0_init_error0_re = 1'd0;
+wire          builder_csrbank0_init_error0_w;
+reg           builder_csrbank0_init_error0_we = 1'd0;
+wire          builder_csrbank0_sel;
+wire    [1:0] builder_csrbank1_dly_sel0_r;
+reg           builder_csrbank1_dly_sel0_re = 1'd0;
+wire    [1:0] builder_csrbank1_dly_sel0_w;
+reg           builder_csrbank1_dly_sel0_we = 1'd0;
+wire    [4:0] builder_csrbank1_half_sys8x_taps0_r;
+reg           builder_csrbank1_half_sys8x_taps0_re = 1'd0;
+wire    [4:0] builder_csrbank1_half_sys8x_taps0_w;
+reg           builder_csrbank1_half_sys8x_taps0_we = 1'd0;
+wire    [1:0] builder_csrbank1_rdphase0_r;
+reg           builder_csrbank1_rdphase0_re = 1'd0;
+wire    [1:0] builder_csrbank1_rdphase0_w;
+reg           builder_csrbank1_rdphase0_we = 1'd0;
+wire          builder_csrbank1_rst0_r;
+reg           builder_csrbank1_rst0_re = 1'd0;
+wire          builder_csrbank1_rst0_w;
+reg           builder_csrbank1_rst0_we = 1'd0;
+wire          builder_csrbank1_sel;
+wire          builder_csrbank1_wlevel_en0_r;
+reg           builder_csrbank1_wlevel_en0_re = 1'd0;
+wire          builder_csrbank1_wlevel_en0_w;
+reg           builder_csrbank1_wlevel_en0_we = 1'd0;
+wire    [1:0] builder_csrbank1_wrphase0_r;
+reg           builder_csrbank1_wrphase0_re = 1'd0;
+wire    [1:0] builder_csrbank1_wrphase0_w;
+reg           builder_csrbank1_wrphase0_we = 1'd0;
+wire    [3:0] builder_csrbank2_dfii_control0_r;
+reg           builder_csrbank2_dfii_control0_re = 1'd0;
+wire    [3:0] builder_csrbank2_dfii_control0_w;
+reg           builder_csrbank2_dfii_control0_we = 1'd0;
+wire   [13:0] builder_csrbank2_dfii_pi0_address0_r;
+reg           builder_csrbank2_dfii_pi0_address0_re = 1'd0;
+wire   [13:0] builder_csrbank2_dfii_pi0_address0_w;
+reg           builder_csrbank2_dfii_pi0_address0_we = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi0_baddress0_r;
+reg           builder_csrbank2_dfii_pi0_baddress0_re = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi0_baddress0_w;
+reg           builder_csrbank2_dfii_pi0_baddress0_we = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi0_command0_r;
+reg           builder_csrbank2_dfii_pi0_command0_re = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi0_command0_w;
+reg           builder_csrbank2_dfii_pi0_command0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi0_rddata_r;
+reg           builder_csrbank2_dfii_pi0_rddata_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi0_rddata_w;
+reg           builder_csrbank2_dfii_pi0_rddata_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi0_wrdata0_r;
+reg           builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi0_wrdata0_w;
+reg           builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0;
+wire   [13:0] builder_csrbank2_dfii_pi1_address0_r;
+reg           builder_csrbank2_dfii_pi1_address0_re = 1'd0;
+wire   [13:0] builder_csrbank2_dfii_pi1_address0_w;
+reg           builder_csrbank2_dfii_pi1_address0_we = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi1_baddress0_r;
+reg           builder_csrbank2_dfii_pi1_baddress0_re = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi1_baddress0_w;
+reg           builder_csrbank2_dfii_pi1_baddress0_we = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi1_command0_r;
+reg           builder_csrbank2_dfii_pi1_command0_re = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi1_command0_w;
+reg           builder_csrbank2_dfii_pi1_command0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi1_rddata_r;
+reg           builder_csrbank2_dfii_pi1_rddata_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi1_rddata_w;
+reg           builder_csrbank2_dfii_pi1_rddata_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi1_wrdata0_r;
+reg           builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi1_wrdata0_w;
+reg           builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0;
+wire   [13:0] builder_csrbank2_dfii_pi2_address0_r;
+reg           builder_csrbank2_dfii_pi2_address0_re = 1'd0;
+wire   [13:0] builder_csrbank2_dfii_pi2_address0_w;
+reg           builder_csrbank2_dfii_pi2_address0_we = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi2_baddress0_r;
+reg           builder_csrbank2_dfii_pi2_baddress0_re = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi2_baddress0_w;
+reg           builder_csrbank2_dfii_pi2_baddress0_we = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi2_command0_r;
+reg           builder_csrbank2_dfii_pi2_command0_re = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi2_command0_w;
+reg           builder_csrbank2_dfii_pi2_command0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi2_rddata_r;
+reg           builder_csrbank2_dfii_pi2_rddata_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi2_rddata_w;
+reg           builder_csrbank2_dfii_pi2_rddata_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi2_wrdata0_r;
+reg           builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi2_wrdata0_w;
+reg           builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0;
+wire   [13:0] builder_csrbank2_dfii_pi3_address0_r;
+reg           builder_csrbank2_dfii_pi3_address0_re = 1'd0;
+wire   [13:0] builder_csrbank2_dfii_pi3_address0_w;
+reg           builder_csrbank2_dfii_pi3_address0_we = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi3_baddress0_r;
+reg           builder_csrbank2_dfii_pi3_baddress0_re = 1'd0;
+wire    [2:0] builder_csrbank2_dfii_pi3_baddress0_w;
+reg           builder_csrbank2_dfii_pi3_baddress0_we = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi3_command0_r;
+reg           builder_csrbank2_dfii_pi3_command0_re = 1'd0;
+wire    [7:0] builder_csrbank2_dfii_pi3_command0_w;
+reg           builder_csrbank2_dfii_pi3_command0_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi3_rddata_r;
+reg           builder_csrbank2_dfii_pi3_rddata_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi3_rddata_w;
+reg           builder_csrbank2_dfii_pi3_rddata_we = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi3_wrdata0_r;
+reg           builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0;
+wire   [31:0] builder_csrbank2_dfii_pi3_wrdata0_w;
+reg           builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0;
+wire          builder_csrbank2_sel;
+wire   [31:0] builder_dat_r;
+wire   [31:0] builder_dat_w;
+reg           builder_interface0_ack = 1'd0;
+wire   [29:0] builder_interface0_adr;
+wire   [13:0] builder_interface0_bank_bus_adr;
+reg    [31:0] builder_interface0_bank_bus_dat_r = 32'd0;
+wire   [31:0] builder_interface0_bank_bus_dat_w;
+wire          builder_interface0_bank_bus_we;
+wire    [1:0] builder_interface0_bte;
+wire    [2:0] builder_interface0_cti;
+wire          builder_interface0_cyc;
+reg    [31:0] builder_interface0_dat_r = 32'd0;
+wire   [31:0] builder_interface0_dat_w;
+reg           builder_interface0_err = 1'd0;
+wire    [3:0] builder_interface0_sel;
+wire          builder_interface0_stb;
+wire          builder_interface0_we;
+reg    [13:0] builder_interface1_adr = 14'd0;
+reg    [13:0] builder_interface1_adr_next_value1 = 14'd0;
+reg           builder_interface1_adr_next_value_ce1 = 1'd0;
+wire   [13:0] builder_interface1_bank_bus_adr;
+reg    [31:0] builder_interface1_bank_bus_dat_r = 32'd0;
+wire   [31:0] builder_interface1_bank_bus_dat_w;
+wire          builder_interface1_bank_bus_we;
+wire   [31:0] builder_interface1_dat_r;
+reg    [31:0] builder_interface1_dat_w = 32'd0;
+reg    [31:0] builder_interface1_dat_w_next_value0 = 32'd0;
+reg           builder_interface1_dat_w_next_value_ce0 = 1'd0;
+reg           builder_interface1_we = 1'd0;
+reg           builder_interface1_we_next_value2 = 1'd0;
+reg           builder_interface1_we_next_value_ce2 = 1'd0;
+wire   [13:0] builder_interface2_bank_bus_adr;
+reg    [31:0] builder_interface2_bank_bus_dat_r = 32'd0;
+wire   [31:0] builder_interface2_bank_bus_dat_w;
+wire          builder_interface2_bank_bus_we;
+reg           builder_locked0 = 1'd0;
+reg           builder_locked1 = 1'd0;
+reg           builder_locked2 = 1'd0;
+reg           builder_locked3 = 1'd0;
+reg           builder_locked4 = 1'd0;
+reg           builder_locked5 = 1'd0;
+reg           builder_locked6 = 1'd0;
+reg           builder_locked7 = 1'd0;
+reg     [3:0] builder_multiplexer_next_state = 4'd0;
+reg     [3:0] builder_multiplexer_state = 4'd0;
+reg           builder_new_master_rdata_valid0 = 1'd0;
+reg           builder_new_master_rdata_valid1 = 1'd0;
+reg           builder_new_master_rdata_valid2 = 1'd0;
+reg           builder_new_master_rdata_valid3 = 1'd0;
+reg           builder_new_master_rdata_valid4 = 1'd0;
+reg           builder_new_master_rdata_valid5 = 1'd0;
+reg           builder_new_master_rdata_valid6 = 1'd0;
+reg           builder_new_master_rdata_valid7 = 1'd0;
+reg           builder_new_master_rdata_valid8 = 1'd0;
+reg           builder_new_master_wdata_ready0 = 1'd0;
+reg           builder_new_master_wdata_ready1 = 1'd0;
+reg     [1:0] builder_next_state = 2'd0;
+wire          builder_pll_fb;
+reg     [1:0] builder_refresher_next_state = 2'd0;
+reg     [1:0] builder_refresher_state = 2'd0;
+wire          builder_reset0;
+wire          builder_reset1;
+wire          builder_reset2;
+wire          builder_reset3;
+wire          builder_reset4;
+wire          builder_reset5;
+wire          builder_reset6;
+wire          builder_reset7;
+reg           builder_rhs_self0 = 1'd0;
+reg    [13:0] builder_rhs_self1 = 14'd0;
+reg           builder_rhs_self10 = 1'd0;
+reg           builder_rhs_self11 = 1'd0;
+reg    [20:0] builder_rhs_self12 = 21'd0;
+reg           builder_rhs_self13 = 1'd0;
+reg           builder_rhs_self14 = 1'd0;
+reg    [20:0] builder_rhs_self15 = 21'd0;
+reg           builder_rhs_self16 = 1'd0;
+reg           builder_rhs_self17 = 1'd0;
+reg    [20:0] builder_rhs_self18 = 21'd0;
+reg           builder_rhs_self19 = 1'd0;
+reg     [2:0] builder_rhs_self2 = 3'd0;
+reg           builder_rhs_self20 = 1'd0;
+reg    [20:0] builder_rhs_self21 = 21'd0;
+reg           builder_rhs_self22 = 1'd0;
+reg           builder_rhs_self23 = 1'd0;
+reg    [20:0] builder_rhs_self24 = 21'd0;
+reg           builder_rhs_self25 = 1'd0;
+reg           builder_rhs_self26 = 1'd0;
+reg    [20:0] builder_rhs_self27 = 21'd0;
+reg           builder_rhs_self28 = 1'd0;
+reg           builder_rhs_self29 = 1'd0;
+reg           builder_rhs_self3 = 1'd0;
+reg    [20:0] builder_rhs_self30 = 21'd0;
+reg           builder_rhs_self31 = 1'd0;
+reg           builder_rhs_self32 = 1'd0;
+reg    [20:0] builder_rhs_self33 = 21'd0;
+reg           builder_rhs_self34 = 1'd0;
+reg           builder_rhs_self35 = 1'd0;
+reg           builder_rhs_self4 = 1'd0;
+reg           builder_rhs_self5 = 1'd0;
+reg           builder_rhs_self6 = 1'd0;
+reg    [13:0] builder_rhs_self7 = 14'd0;
+reg     [2:0] builder_rhs_self8 = 3'd0;
+reg           builder_rhs_self9 = 1'd0;
+wire          builder_roundrobin0_ce;
+wire          builder_roundrobin0_grant;
+wire          builder_roundrobin0_request;
+wire          builder_roundrobin1_ce;
+wire          builder_roundrobin1_grant;
+wire          builder_roundrobin1_request;
+wire          builder_roundrobin2_ce;
+wire          builder_roundrobin2_grant;
+wire          builder_roundrobin2_request;
+wire          builder_roundrobin3_ce;
+wire          builder_roundrobin3_grant;
+wire          builder_roundrobin3_request;
+wire          builder_roundrobin4_ce;
+wire          builder_roundrobin4_grant;
+wire          builder_roundrobin4_request;
+wire          builder_roundrobin5_ce;
+wire          builder_roundrobin5_grant;
+wire          builder_roundrobin5_request;
+wire          builder_roundrobin6_ce;
+wire          builder_roundrobin6_grant;
+wire          builder_roundrobin6_request;
+wire          builder_roundrobin7_ce;
+wire          builder_roundrobin7_grant;
+wire          builder_roundrobin7_request;
+reg     [2:0] builder_self0 = 3'd0;
+reg    [13:0] builder_self1 = 14'd0;
+reg           builder_self10 = 1'd0;
+reg           builder_self11 = 1'd0;
+reg           builder_self12 = 1'd0;
+reg           builder_self13 = 1'd0;
+reg     [2:0] builder_self14 = 3'd0;
+reg    [13:0] builder_self15 = 14'd0;
+reg           builder_self16 = 1'd0;
+reg           builder_self17 = 1'd0;
+reg           builder_self18 = 1'd0;
+reg           builder_self19 = 1'd0;
+reg           builder_self2 = 1'd0;
+reg           builder_self20 = 1'd0;
+reg     [2:0] builder_self21 = 3'd0;
+reg    [13:0] builder_self22 = 14'd0;
+reg           builder_self23 = 1'd0;
+reg           builder_self24 = 1'd0;
+reg           builder_self25 = 1'd0;
+reg           builder_self26 = 1'd0;
+reg           builder_self27 = 1'd0;
+reg           builder_self3 = 1'd0;
+reg           builder_self4 = 1'd0;
+reg           builder_self5 = 1'd0;
+reg           builder_self6 = 1'd0;
+reg     [2:0] builder_self7 = 3'd0;
+reg    [13:0] builder_self8 = 14'd0;
+reg           builder_self9 = 1'd0;
+reg     [1:0] builder_state = 2'd0;
+reg           builder_t_self0 = 1'd0;
+reg           builder_t_self1 = 1'd0;
+reg           builder_t_self2 = 1'd0;
+reg           builder_t_self3 = 1'd0;
+reg           builder_t_self4 = 1'd0;
+reg           builder_t_self5 = 1'd0;
+wire          builder_we;
+wire          builder_xilinxasyncresetsynchronizerimpl0_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl0_rst_meta;
+wire          builder_xilinxasyncresetsynchronizerimpl1_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl1_rst_meta;
+wire          builder_xilinxasyncresetsynchronizerimpl2_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl2_expr;
+wire          builder_xilinxasyncresetsynchronizerimpl2_rst_meta;
+wire          builder_xilinxasyncresetsynchronizerimpl3_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl3_expr;
+wire          builder_xilinxasyncresetsynchronizerimpl3_rst_meta;
 wire          iodelay_clk;
 wire          iodelay_rst;
-wire          reset;
-reg           power_down = 1'd0;
-wire          locked;
-wire          clkin;
-wire          clkout0;
-wire          clkout_buf0;
-wire          clkout1;
-wire          clkout_buf1;
-wire          clkout2;
-wire          clkout_buf2;
-wire          clkout3;
-wire          clkout_buf3;
-reg     [3:0] reset_counter = 4'd15;
-reg           ic_reset = 1'd1;
-reg           a7ddrphy_rst_storage = 1'd0;
-reg           a7ddrphy_rst_re = 1'd0;
-reg     [1:0] a7ddrphy_dly_sel_storage = 2'd0;
-reg           a7ddrphy_dly_sel_re = 1'd0;
-reg     [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8;
-reg           a7ddrphy_half_sys8x_taps_re = 1'd0;
-reg           a7ddrphy_wlevel_en_storage = 1'd0;
-reg           a7ddrphy_wlevel_en_re = 1'd0;
-reg           a7ddrphy_wlevel_strobe_re = 1'd0;
-wire          a7ddrphy_wlevel_strobe_r;
-reg           a7ddrphy_wlevel_strobe_we = 1'd0;
-reg           a7ddrphy_wlevel_strobe_w = 1'd0;
-reg           a7ddrphy_rdly_dq_rst_re = 1'd0;
-wire          a7ddrphy_rdly_dq_rst_r;
-reg           a7ddrphy_rdly_dq_rst_we = 1'd0;
-reg           a7ddrphy_rdly_dq_rst_w = 1'd0;
-reg           a7ddrphy_rdly_dq_inc_re = 1'd0;
-wire          a7ddrphy_rdly_dq_inc_r;
-reg           a7ddrphy_rdly_dq_inc_we = 1'd0;
-reg           a7ddrphy_rdly_dq_inc_w = 1'd0;
-reg           a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
-wire          a7ddrphy_rdly_dq_bitslip_rst_r;
-reg           a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
-reg           a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-reg           a7ddrphy_rdly_dq_bitslip_re = 1'd0;
-wire          a7ddrphy_rdly_dq_bitslip_r;
-reg           a7ddrphy_rdly_dq_bitslip_we = 1'd0;
-reg           a7ddrphy_rdly_dq_bitslip_w = 1'd0;
-reg           a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
-wire          a7ddrphy_wdly_dq_bitslip_rst_r;
-reg           a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
-reg           a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
-reg           a7ddrphy_wdly_dq_bitslip_re = 1'd0;
-wire          a7ddrphy_wdly_dq_bitslip_r;
-reg           a7ddrphy_wdly_dq_bitslip_we = 1'd0;
-reg           a7ddrphy_wdly_dq_bitslip_w = 1'd0;
-reg     [1:0] a7ddrphy_rdphase_storage = 2'd2;
-reg           a7ddrphy_rdphase_re = 1'd0;
-reg     [1:0] a7ddrphy_wrphase_storage = 2'd3;
-reg           a7ddrphy_wrphase_re = 1'd0;
-wire   [13:0] a7ddrphy_dfi_p0_address;
-wire    [2:0] a7ddrphy_dfi_p0_bank;
-wire          a7ddrphy_dfi_p0_cas_n;
-wire          a7ddrphy_dfi_p0_cs_n;
-wire          a7ddrphy_dfi_p0_ras_n;
-wire          a7ddrphy_dfi_p0_we_n;
-wire          a7ddrphy_dfi_p0_cke;
-wire          a7ddrphy_dfi_p0_odt;
-wire          a7ddrphy_dfi_p0_reset_n;
-wire          a7ddrphy_dfi_p0_act_n;
-wire   [31:0] a7ddrphy_dfi_p0_wrdata;
-wire          a7ddrphy_dfi_p0_wrdata_en;
-wire    [3:0] a7ddrphy_dfi_p0_wrdata_mask;
-wire          a7ddrphy_dfi_p0_rddata_en;
-reg    [31:0] a7ddrphy_dfi_p0_rddata = 32'd0;
-wire          a7ddrphy_dfi_p0_rddata_valid;
-wire   [13:0] a7ddrphy_dfi_p1_address;
-wire    [2:0] a7ddrphy_dfi_p1_bank;
-wire          a7ddrphy_dfi_p1_cas_n;
-wire          a7ddrphy_dfi_p1_cs_n;
-wire          a7ddrphy_dfi_p1_ras_n;
-wire          a7ddrphy_dfi_p1_we_n;
-wire          a7ddrphy_dfi_p1_cke;
-wire          a7ddrphy_dfi_p1_odt;
-wire          a7ddrphy_dfi_p1_reset_n;
-wire          a7ddrphy_dfi_p1_act_n;
-wire   [31:0] a7ddrphy_dfi_p1_wrdata;
-wire          a7ddrphy_dfi_p1_wrdata_en;
-wire    [3:0] a7ddrphy_dfi_p1_wrdata_mask;
-wire          a7ddrphy_dfi_p1_rddata_en;
-reg    [31:0] a7ddrphy_dfi_p1_rddata = 32'd0;
-wire          a7ddrphy_dfi_p1_rddata_valid;
-wire   [13:0] a7ddrphy_dfi_p2_address;
-wire    [2:0] a7ddrphy_dfi_p2_bank;
-wire          a7ddrphy_dfi_p2_cas_n;
-wire          a7ddrphy_dfi_p2_cs_n;
-wire          a7ddrphy_dfi_p2_ras_n;
-wire          a7ddrphy_dfi_p2_we_n;
-wire          a7ddrphy_dfi_p2_cke;
-wire          a7ddrphy_dfi_p2_odt;
-wire          a7ddrphy_dfi_p2_reset_n;
-wire          a7ddrphy_dfi_p2_act_n;
-wire   [31:0] a7ddrphy_dfi_p2_wrdata;
-wire          a7ddrphy_dfi_p2_wrdata_en;
-wire    [3:0] a7ddrphy_dfi_p2_wrdata_mask;
-wire          a7ddrphy_dfi_p2_rddata_en;
-reg    [31:0] a7ddrphy_dfi_p2_rddata = 32'd0;
-wire          a7ddrphy_dfi_p2_rddata_valid;
-wire   [13:0] a7ddrphy_dfi_p3_address;
-wire    [2:0] a7ddrphy_dfi_p3_bank;
-wire          a7ddrphy_dfi_p3_cas_n;
-wire          a7ddrphy_dfi_p3_cs_n;
-wire          a7ddrphy_dfi_p3_ras_n;
-wire          a7ddrphy_dfi_p3_we_n;
-wire          a7ddrphy_dfi_p3_cke;
-wire          a7ddrphy_dfi_p3_odt;
-wire          a7ddrphy_dfi_p3_reset_n;
-wire          a7ddrphy_dfi_p3_act_n;
-wire   [31:0] a7ddrphy_dfi_p3_wrdata;
-wire          a7ddrphy_dfi_p3_wrdata_en;
-wire    [3:0] a7ddrphy_dfi_p3_wrdata_mask;
-wire          a7ddrphy_dfi_p3_rddata_en;
-reg    [31:0] a7ddrphy_dfi_p3_rddata = 32'd0;
-wire          a7ddrphy_dfi_p3_rddata_valid;
-wire          a7ddrphy_sd_clk_se_nodelay;
-wire    [2:0] a7ddrphy_pads_ba;
-reg           a7ddrphy_dqs_oe = 1'd0;
-wire          a7ddrphy_dqs_preamble;
-wire          a7ddrphy_dqs_postamble;
-wire          a7ddrphy_dqs_oe_delay_tappeddelayline;
-reg           a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg           a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-reg           a7ddrphy_dqspattern0 = 1'd0;
-reg           a7ddrphy_dqspattern1 = 1'd0;
-reg     [7:0] a7ddrphy_dqspattern_o0 = 8'd0;
-reg     [7:0] a7ddrphy_dqspattern_o1 = 8'd0;
-wire          a7ddrphy_dqs_o_no_delay0;
-wire          a7ddrphy_dqs_t0;
-reg     [7:0] a7ddrphy_bitslip00 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip0_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip0_r0 = 16'd0;
-wire          a7ddrphy0;
-wire          a7ddrphy_dqs_o_no_delay1;
-wire          a7ddrphy_dqs_t1;
-reg     [7:0] a7ddrphy_bitslip10 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip1_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip1_r0 = 16'd0;
-wire          a7ddrphy1;
-reg     [7:0] a7ddrphy_bitslip01 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip0_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip0_r1 = 16'd0;
-reg     [7:0] a7ddrphy_bitslip11 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip1_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip1_r1 = 16'd0;
-wire          a7ddrphy_dq_oe;
-wire          a7ddrphy_dq_oe_delay_tappeddelayline;
-reg           a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg           a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-wire          a7ddrphy_dq_o_nodelay0;
-wire          a7ddrphy_dq_i_nodelay0;
-wire          a7ddrphy_dq_i_delayed0;
-wire          a7ddrphy_dq_t0;
-reg     [7:0] a7ddrphy_bitslip02 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip0_value2 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip0_r2 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip03;
-reg     [7:0] a7ddrphy_bitslip04 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip0_value3 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip0_r3 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay1;
-wire          a7ddrphy_dq_i_nodelay1;
-wire          a7ddrphy_dq_i_delayed1;
-wire          a7ddrphy_dq_t1;
-reg     [7:0] a7ddrphy_bitslip12 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip1_value2 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip1_r2 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip13;
-reg     [7:0] a7ddrphy_bitslip14 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip1_value3 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip1_r3 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay2;
-wire          a7ddrphy_dq_i_nodelay2;
-wire          a7ddrphy_dq_i_delayed2;
-wire          a7ddrphy_dq_t2;
-reg     [7:0] a7ddrphy_bitslip20 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip2_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip2_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip21;
-reg     [7:0] a7ddrphy_bitslip22 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip2_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip2_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay3;
-wire          a7ddrphy_dq_i_nodelay3;
-wire          a7ddrphy_dq_i_delayed3;
-wire          a7ddrphy_dq_t3;
-reg     [7:0] a7ddrphy_bitslip30 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip3_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip3_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip31;
-reg     [7:0] a7ddrphy_bitslip32 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip3_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip3_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay4;
-wire          a7ddrphy_dq_i_nodelay4;
-wire          a7ddrphy_dq_i_delayed4;
-wire          a7ddrphy_dq_t4;
-reg     [7:0] a7ddrphy_bitslip40 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip4_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip4_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip41;
-reg     [7:0] a7ddrphy_bitslip42 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip4_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip4_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay5;
-wire          a7ddrphy_dq_i_nodelay5;
-wire          a7ddrphy_dq_i_delayed5;
-wire          a7ddrphy_dq_t5;
-reg     [7:0] a7ddrphy_bitslip50 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip5_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip5_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip51;
-reg     [7:0] a7ddrphy_bitslip52 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip5_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip5_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay6;
-wire          a7ddrphy_dq_i_nodelay6;
-wire          a7ddrphy_dq_i_delayed6;
-wire          a7ddrphy_dq_t6;
-reg     [7:0] a7ddrphy_bitslip60 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip6_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip6_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip61;
-reg     [7:0] a7ddrphy_bitslip62 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip6_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip6_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay7;
-wire          a7ddrphy_dq_i_nodelay7;
-wire          a7ddrphy_dq_i_delayed7;
-wire          a7ddrphy_dq_t7;
-reg     [7:0] a7ddrphy_bitslip70 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip7_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip7_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip71;
-reg     [7:0] a7ddrphy_bitslip72 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip7_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip7_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay8;
-wire          a7ddrphy_dq_i_nodelay8;
-wire          a7ddrphy_dq_i_delayed8;
-wire          a7ddrphy_dq_t8;
-reg     [7:0] a7ddrphy_bitslip80 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip8_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip8_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip81;
-reg     [7:0] a7ddrphy_bitslip82 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip8_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip8_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay9;
-wire          a7ddrphy_dq_i_nodelay9;
-wire          a7ddrphy_dq_i_delayed9;
-wire          a7ddrphy_dq_t9;
-reg     [7:0] a7ddrphy_bitslip90 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip9_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip9_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip91;
-reg     [7:0] a7ddrphy_bitslip92 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip9_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip9_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay10;
-wire          a7ddrphy_dq_i_nodelay10;
-wire          a7ddrphy_dq_i_delayed10;
-wire          a7ddrphy_dq_t10;
-reg     [7:0] a7ddrphy_bitslip100 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip10_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip10_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip101;
-reg     [7:0] a7ddrphy_bitslip102 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip10_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip10_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay11;
-wire          a7ddrphy_dq_i_nodelay11;
-wire          a7ddrphy_dq_i_delayed11;
-wire          a7ddrphy_dq_t11;
-reg     [7:0] a7ddrphy_bitslip110 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip11_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip11_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip111;
-reg     [7:0] a7ddrphy_bitslip112 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip11_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip11_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay12;
-wire          a7ddrphy_dq_i_nodelay12;
-wire          a7ddrphy_dq_i_delayed12;
-wire          a7ddrphy_dq_t12;
-reg     [7:0] a7ddrphy_bitslip120 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip12_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip12_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip121;
-reg     [7:0] a7ddrphy_bitslip122 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip12_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip12_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay13;
-wire          a7ddrphy_dq_i_nodelay13;
-wire          a7ddrphy_dq_i_delayed13;
-wire          a7ddrphy_dq_t13;
-reg     [7:0] a7ddrphy_bitslip130 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip13_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip13_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip131;
-reg     [7:0] a7ddrphy_bitslip132 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip13_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip13_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay14;
-wire          a7ddrphy_dq_i_nodelay14;
-wire          a7ddrphy_dq_i_delayed14;
-wire          a7ddrphy_dq_t14;
-reg     [7:0] a7ddrphy_bitslip140 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip14_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip14_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip141;
-reg     [7:0] a7ddrphy_bitslip142 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip14_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip14_r1 = 16'd0;
-wire          a7ddrphy_dq_o_nodelay15;
-wire          a7ddrphy_dq_i_nodelay15;
-wire          a7ddrphy_dq_i_delayed15;
-wire          a7ddrphy_dq_t15;
-reg     [7:0] a7ddrphy_bitslip150 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip15_value0 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip15_r0 = 16'd0;
-wire    [7:0] a7ddrphy_bitslip151;
-reg     [7:0] a7ddrphy_bitslip152 = 8'd0;
-reg     [2:0] a7ddrphy_bitslip15_value1 = 3'd7;
-reg    [15:0] a7ddrphy_bitslip15_r1 = 16'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
-reg           a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
-reg           a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
-reg           a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
-reg           a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
-wire   [13:0] litedramcore_slave_p0_address;
-wire    [2:0] litedramcore_slave_p0_bank;
-wire          litedramcore_slave_p0_cas_n;
-wire          litedramcore_slave_p0_cs_n;
-wire          litedramcore_slave_p0_ras_n;
-wire          litedramcore_slave_p0_we_n;
-wire          litedramcore_slave_p0_cke;
-wire          litedramcore_slave_p0_odt;
-wire          litedramcore_slave_p0_reset_n;
-wire          litedramcore_slave_p0_act_n;
-wire   [31:0] litedramcore_slave_p0_wrdata;
-wire          litedramcore_slave_p0_wrdata_en;
-wire    [3:0] litedramcore_slave_p0_wrdata_mask;
-wire          litedramcore_slave_p0_rddata_en;
-reg    [31:0] litedramcore_slave_p0_rddata = 32'd0;
-reg           litedramcore_slave_p0_rddata_valid = 1'd0;
-wire   [13:0] litedramcore_slave_p1_address;
-wire    [2:0] litedramcore_slave_p1_bank;
-wire          litedramcore_slave_p1_cas_n;
-wire          litedramcore_slave_p1_cs_n;
-wire          litedramcore_slave_p1_ras_n;
-wire          litedramcore_slave_p1_we_n;
-wire          litedramcore_slave_p1_cke;
-wire          litedramcore_slave_p1_odt;
-wire          litedramcore_slave_p1_reset_n;
-wire          litedramcore_slave_p1_act_n;
-wire   [31:0] litedramcore_slave_p1_wrdata;
-wire          litedramcore_slave_p1_wrdata_en;
-wire    [3:0] litedramcore_slave_p1_wrdata_mask;
-wire          litedramcore_slave_p1_rddata_en;
-reg    [31:0] litedramcore_slave_p1_rddata = 32'd0;
-reg           litedramcore_slave_p1_rddata_valid = 1'd0;
-wire   [13:0] litedramcore_slave_p2_address;
-wire    [2:0] litedramcore_slave_p2_bank;
-wire          litedramcore_slave_p2_cas_n;
-wire          litedramcore_slave_p2_cs_n;
-wire          litedramcore_slave_p2_ras_n;
-wire          litedramcore_slave_p2_we_n;
-wire          litedramcore_slave_p2_cke;
-wire          litedramcore_slave_p2_odt;
-wire          litedramcore_slave_p2_reset_n;
-wire          litedramcore_slave_p2_act_n;
-wire   [31:0] litedramcore_slave_p2_wrdata;
-wire          litedramcore_slave_p2_wrdata_en;
-wire    [3:0] litedramcore_slave_p2_wrdata_mask;
-wire          litedramcore_slave_p2_rddata_en;
-reg    [31:0] litedramcore_slave_p2_rddata = 32'd0;
-reg           litedramcore_slave_p2_rddata_valid = 1'd0;
-wire   [13:0] litedramcore_slave_p3_address;
-wire    [2:0] litedramcore_slave_p3_bank;
-wire          litedramcore_slave_p3_cas_n;
-wire          litedramcore_slave_p3_cs_n;
-wire          litedramcore_slave_p3_ras_n;
-wire          litedramcore_slave_p3_we_n;
-wire          litedramcore_slave_p3_cke;
-wire          litedramcore_slave_p3_odt;
-wire          litedramcore_slave_p3_reset_n;
-wire          litedramcore_slave_p3_act_n;
-wire   [31:0] litedramcore_slave_p3_wrdata;
-wire          litedramcore_slave_p3_wrdata_en;
-wire    [3:0] litedramcore_slave_p3_wrdata_mask;
-wire          litedramcore_slave_p3_rddata_en;
-reg    [31:0] litedramcore_slave_p3_rddata = 32'd0;
-reg           litedramcore_slave_p3_rddata_valid = 1'd0;
-reg    [13:0] litedramcore_master_p0_address = 14'd0;
-reg     [2:0] litedramcore_master_p0_bank = 3'd0;
-reg           litedramcore_master_p0_cas_n = 1'd1;
-reg           litedramcore_master_p0_cs_n = 1'd1;
-reg           litedramcore_master_p0_ras_n = 1'd1;
-reg           litedramcore_master_p0_we_n = 1'd1;
-reg           litedramcore_master_p0_cke = 1'd0;
-reg           litedramcore_master_p0_odt = 1'd0;
-reg           litedramcore_master_p0_reset_n = 1'd0;
-reg           litedramcore_master_p0_act_n = 1'd1;
-reg    [31:0] litedramcore_master_p0_wrdata = 32'd0;
-reg           litedramcore_master_p0_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_master_p0_wrdata_mask = 4'd0;
-reg           litedramcore_master_p0_rddata_en = 1'd0;
-wire   [31:0] litedramcore_master_p0_rddata;
-wire          litedramcore_master_p0_rddata_valid;
-reg    [13:0] litedramcore_master_p1_address = 14'd0;
-reg     [2:0] litedramcore_master_p1_bank = 3'd0;
-reg           litedramcore_master_p1_cas_n = 1'd1;
-reg           litedramcore_master_p1_cs_n = 1'd1;
-reg           litedramcore_master_p1_ras_n = 1'd1;
-reg           litedramcore_master_p1_we_n = 1'd1;
-reg           litedramcore_master_p1_cke = 1'd0;
-reg           litedramcore_master_p1_odt = 1'd0;
-reg           litedramcore_master_p1_reset_n = 1'd0;
-reg           litedramcore_master_p1_act_n = 1'd1;
-reg    [31:0] litedramcore_master_p1_wrdata = 32'd0;
-reg           litedramcore_master_p1_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_master_p1_wrdata_mask = 4'd0;
-reg           litedramcore_master_p1_rddata_en = 1'd0;
-wire   [31:0] litedramcore_master_p1_rddata;
-wire          litedramcore_master_p1_rddata_valid;
-reg    [13:0] litedramcore_master_p2_address = 14'd0;
-reg     [2:0] litedramcore_master_p2_bank = 3'd0;
-reg           litedramcore_master_p2_cas_n = 1'd1;
-reg           litedramcore_master_p2_cs_n = 1'd1;
-reg           litedramcore_master_p2_ras_n = 1'd1;
-reg           litedramcore_master_p2_we_n = 1'd1;
-reg           litedramcore_master_p2_cke = 1'd0;
-reg           litedramcore_master_p2_odt = 1'd0;
-reg           litedramcore_master_p2_reset_n = 1'd0;
-reg           litedramcore_master_p2_act_n = 1'd1;
-reg    [31:0] litedramcore_master_p2_wrdata = 32'd0;
-reg           litedramcore_master_p2_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_master_p2_wrdata_mask = 4'd0;
-reg           litedramcore_master_p2_rddata_en = 1'd0;
-wire   [31:0] litedramcore_master_p2_rddata;
-wire          litedramcore_master_p2_rddata_valid;
-reg    [13:0] litedramcore_master_p3_address = 14'd0;
-reg     [2:0] litedramcore_master_p3_bank = 3'd0;
-reg           litedramcore_master_p3_cas_n = 1'd1;
-reg           litedramcore_master_p3_cs_n = 1'd1;
-reg           litedramcore_master_p3_ras_n = 1'd1;
-reg           litedramcore_master_p3_we_n = 1'd1;
-reg           litedramcore_master_p3_cke = 1'd0;
-reg           litedramcore_master_p3_odt = 1'd0;
-reg           litedramcore_master_p3_reset_n = 1'd0;
-reg           litedramcore_master_p3_act_n = 1'd1;
-reg    [31:0] litedramcore_master_p3_wrdata = 32'd0;
-reg           litedramcore_master_p3_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_master_p3_wrdata_mask = 4'd0;
-reg           litedramcore_master_p3_rddata_en = 1'd0;
-wire   [31:0] litedramcore_master_p3_rddata;
-wire          litedramcore_master_p3_rddata_valid;
-wire   [13:0] litedramcore_csr_dfi_p0_address;
-wire    [2:0] litedramcore_csr_dfi_p0_bank;
-reg           litedramcore_csr_dfi_p0_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p0_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p0_ras_n = 1'd1;
-reg           litedramcore_csr_dfi_p0_we_n = 1'd1;
-wire          litedramcore_csr_dfi_p0_cke;
-wire          litedramcore_csr_dfi_p0_odt;
-wire          litedramcore_csr_dfi_p0_reset_n;
-reg           litedramcore_csr_dfi_p0_act_n = 1'd1;
-wire   [31:0] litedramcore_csr_dfi_p0_wrdata;
-wire          litedramcore_csr_dfi_p0_wrdata_en;
-wire    [3:0] litedramcore_csr_dfi_p0_wrdata_mask;
-wire          litedramcore_csr_dfi_p0_rddata_en;
-reg    [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0;
-reg           litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
-wire   [13:0] litedramcore_csr_dfi_p1_address;
-wire    [2:0] litedramcore_csr_dfi_p1_bank;
-reg           litedramcore_csr_dfi_p1_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p1_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p1_ras_n = 1'd1;
-reg           litedramcore_csr_dfi_p1_we_n = 1'd1;
-wire          litedramcore_csr_dfi_p1_cke;
-wire          litedramcore_csr_dfi_p1_odt;
-wire          litedramcore_csr_dfi_p1_reset_n;
-reg           litedramcore_csr_dfi_p1_act_n = 1'd1;
-wire   [31:0] litedramcore_csr_dfi_p1_wrdata;
-wire          litedramcore_csr_dfi_p1_wrdata_en;
-wire    [3:0] litedramcore_csr_dfi_p1_wrdata_mask;
-wire          litedramcore_csr_dfi_p1_rddata_en;
-reg    [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0;
-reg           litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
-wire   [13:0] litedramcore_csr_dfi_p2_address;
-wire    [2:0] litedramcore_csr_dfi_p2_bank;
-reg           litedramcore_csr_dfi_p2_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p2_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p2_ras_n = 1'd1;
-reg           litedramcore_csr_dfi_p2_we_n = 1'd1;
-wire          litedramcore_csr_dfi_p2_cke;
-wire          litedramcore_csr_dfi_p2_odt;
-wire          litedramcore_csr_dfi_p2_reset_n;
-reg           litedramcore_csr_dfi_p2_act_n = 1'd1;
-wire   [31:0] litedramcore_csr_dfi_p2_wrdata;
-wire          litedramcore_csr_dfi_p2_wrdata_en;
-wire    [3:0] litedramcore_csr_dfi_p2_wrdata_mask;
-wire          litedramcore_csr_dfi_p2_rddata_en;
-reg    [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0;
-reg           litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
-wire   [13:0] litedramcore_csr_dfi_p3_address;
-wire    [2:0] litedramcore_csr_dfi_p3_bank;
-reg           litedramcore_csr_dfi_p3_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p3_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p3_ras_n = 1'd1;
-reg           litedramcore_csr_dfi_p3_we_n = 1'd1;
-wire          litedramcore_csr_dfi_p3_cke;
-wire          litedramcore_csr_dfi_p3_odt;
-wire          litedramcore_csr_dfi_p3_reset_n;
-reg           litedramcore_csr_dfi_p3_act_n = 1'd1;
-wire   [31:0] litedramcore_csr_dfi_p3_wrdata;
-wire          litedramcore_csr_dfi_p3_wrdata_en;
-wire    [3:0] litedramcore_csr_dfi_p3_wrdata_mask;
-wire          litedramcore_csr_dfi_p3_rddata_en;
-reg    [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0;
-reg           litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
-reg    [13:0] litedramcore_ext_dfi_p0_address = 14'd0;
-reg     [2:0] litedramcore_ext_dfi_p0_bank = 3'd0;
-reg           litedramcore_ext_dfi_p0_cas_n = 1'd1;
-reg           litedramcore_ext_dfi_p0_cs_n = 1'd1;
-reg           litedramcore_ext_dfi_p0_ras_n = 1'd1;
-reg           litedramcore_ext_dfi_p0_we_n = 1'd1;
-reg           litedramcore_ext_dfi_p0_cke = 1'd0;
-reg           litedramcore_ext_dfi_p0_odt = 1'd0;
-reg           litedramcore_ext_dfi_p0_reset_n = 1'd0;
-reg           litedramcore_ext_dfi_p0_act_n = 1'd1;
-reg    [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0;
-reg           litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
-reg           litedramcore_ext_dfi_p0_rddata_en = 1'd0;
-reg    [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0;
-reg           litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
-reg    [13:0] litedramcore_ext_dfi_p1_address = 14'd0;
-reg     [2:0] litedramcore_ext_dfi_p1_bank = 3'd0;
-reg           litedramcore_ext_dfi_p1_cas_n = 1'd1;
-reg           litedramcore_ext_dfi_p1_cs_n = 1'd1;
-reg           litedramcore_ext_dfi_p1_ras_n = 1'd1;
-reg           litedramcore_ext_dfi_p1_we_n = 1'd1;
-reg           litedramcore_ext_dfi_p1_cke = 1'd0;
-reg           litedramcore_ext_dfi_p1_odt = 1'd0;
-reg           litedramcore_ext_dfi_p1_reset_n = 1'd0;
-reg           litedramcore_ext_dfi_p1_act_n = 1'd1;
-reg    [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0;
-reg           litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
-reg           litedramcore_ext_dfi_p1_rddata_en = 1'd0;
-reg    [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0;
-reg           litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
-reg    [13:0] litedramcore_ext_dfi_p2_address = 14'd0;
-reg     [2:0] litedramcore_ext_dfi_p2_bank = 3'd0;
-reg           litedramcore_ext_dfi_p2_cas_n = 1'd1;
-reg           litedramcore_ext_dfi_p2_cs_n = 1'd1;
-reg           litedramcore_ext_dfi_p2_ras_n = 1'd1;
-reg           litedramcore_ext_dfi_p2_we_n = 1'd1;
-reg           litedramcore_ext_dfi_p2_cke = 1'd0;
-reg           litedramcore_ext_dfi_p2_odt = 1'd0;
-reg           litedramcore_ext_dfi_p2_reset_n = 1'd0;
-reg           litedramcore_ext_dfi_p2_act_n = 1'd1;
-reg    [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0;
-reg           litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
-reg           litedramcore_ext_dfi_p2_rddata_en = 1'd0;
-reg    [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0;
-reg           litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
-reg    [13:0] litedramcore_ext_dfi_p3_address = 14'd0;
-reg     [2:0] litedramcore_ext_dfi_p3_bank = 3'd0;
-reg           litedramcore_ext_dfi_p3_cas_n = 1'd1;
-reg           litedramcore_ext_dfi_p3_cs_n = 1'd1;
-reg           litedramcore_ext_dfi_p3_ras_n = 1'd1;
-reg           litedramcore_ext_dfi_p3_we_n = 1'd1;
-reg           litedramcore_ext_dfi_p3_cke = 1'd0;
-reg           litedramcore_ext_dfi_p3_odt = 1'd0;
-reg           litedramcore_ext_dfi_p3_reset_n = 1'd0;
-reg           litedramcore_ext_dfi_p3_act_n = 1'd1;
-reg    [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0;
-reg           litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
-reg     [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
-reg           litedramcore_ext_dfi_p3_rddata_en = 1'd0;
-reg    [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0;
-reg           litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
-reg           litedramcore_ext_dfi_sel = 1'd0;
-wire          litedramcore_sel;
-wire          litedramcore_cke;
-wire          litedramcore_odt;
-wire          litedramcore_reset_n;
-reg     [3:0] litedramcore_storage = 4'd1;
-reg           litedramcore_re = 1'd0;
-wire          litedramcore_phaseinjector0_csrfield_cs;
-wire          litedramcore_phaseinjector0_csrfield_we;
-wire          litedramcore_phaseinjector0_csrfield_cas;
-wire          litedramcore_phaseinjector0_csrfield_ras;
-wire          litedramcore_phaseinjector0_csrfield_wren;
-wire          litedramcore_phaseinjector0_csrfield_rden;
-reg     [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
-reg           litedramcore_phaseinjector0_command_re = 1'd0;
-reg           litedramcore_phaseinjector0_command_issue_re = 1'd0;
-wire          litedramcore_phaseinjector0_command_issue_r;
-reg           litedramcore_phaseinjector0_command_issue_we = 1'd0;
-reg           litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg    [13:0] litedramcore_phaseinjector0_address_storage = 14'd0;
-reg           litedramcore_phaseinjector0_address_re = 1'd0;
-reg     [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg           litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0;
-reg           litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0;
-wire          litedramcore_phaseinjector0_rddata_we;
-reg           litedramcore_phaseinjector0_rddata_re = 1'd0;
-wire          litedramcore_phaseinjector1_csrfield_cs;
-wire          litedramcore_phaseinjector1_csrfield_we;
-wire          litedramcore_phaseinjector1_csrfield_cas;
-wire          litedramcore_phaseinjector1_csrfield_ras;
-wire          litedramcore_phaseinjector1_csrfield_wren;
-wire          litedramcore_phaseinjector1_csrfield_rden;
-reg     [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
-reg           litedramcore_phaseinjector1_command_re = 1'd0;
-reg           litedramcore_phaseinjector1_command_issue_re = 1'd0;
-wire          litedramcore_phaseinjector1_command_issue_r;
-reg           litedramcore_phaseinjector1_command_issue_we = 1'd0;
-reg           litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg    [13:0] litedramcore_phaseinjector1_address_storage = 14'd0;
-reg           litedramcore_phaseinjector1_address_re = 1'd0;
-reg     [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg           litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0;
-reg           litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0;
-wire          litedramcore_phaseinjector1_rddata_we;
-reg           litedramcore_phaseinjector1_rddata_re = 1'd0;
-wire          litedramcore_phaseinjector2_csrfield_cs;
-wire          litedramcore_phaseinjector2_csrfield_we;
-wire          litedramcore_phaseinjector2_csrfield_cas;
-wire          litedramcore_phaseinjector2_csrfield_ras;
-wire          litedramcore_phaseinjector2_csrfield_wren;
-wire          litedramcore_phaseinjector2_csrfield_rden;
-reg     [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
-reg           litedramcore_phaseinjector2_command_re = 1'd0;
-reg           litedramcore_phaseinjector2_command_issue_re = 1'd0;
-wire          litedramcore_phaseinjector2_command_issue_r;
-reg           litedramcore_phaseinjector2_command_issue_we = 1'd0;
-reg           litedramcore_phaseinjector2_command_issue_w = 1'd0;
-reg    [13:0] litedramcore_phaseinjector2_address_storage = 14'd0;
-reg           litedramcore_phaseinjector2_address_re = 1'd0;
-reg     [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
-reg           litedramcore_phaseinjector2_baddress_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0;
-reg           litedramcore_phaseinjector2_wrdata_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0;
-wire          litedramcore_phaseinjector2_rddata_we;
-reg           litedramcore_phaseinjector2_rddata_re = 1'd0;
-wire          litedramcore_phaseinjector3_csrfield_cs;
-wire          litedramcore_phaseinjector3_csrfield_we;
-wire          litedramcore_phaseinjector3_csrfield_cas;
-wire          litedramcore_phaseinjector3_csrfield_ras;
-wire          litedramcore_phaseinjector3_csrfield_wren;
-wire          litedramcore_phaseinjector3_csrfield_rden;
-reg     [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
-reg           litedramcore_phaseinjector3_command_re = 1'd0;
-reg           litedramcore_phaseinjector3_command_issue_re = 1'd0;
-wire          litedramcore_phaseinjector3_command_issue_r;
-reg           litedramcore_phaseinjector3_command_issue_we = 1'd0;
-reg           litedramcore_phaseinjector3_command_issue_w = 1'd0;
-reg    [13:0] litedramcore_phaseinjector3_address_storage = 14'd0;
-reg           litedramcore_phaseinjector3_address_re = 1'd0;
-reg     [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
-reg           litedramcore_phaseinjector3_baddress_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0;
-reg           litedramcore_phaseinjector3_wrdata_re = 1'd0;
-reg    [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0;
-wire          litedramcore_phaseinjector3_rddata_we;
-reg           litedramcore_phaseinjector3_rddata_re = 1'd0;
-wire          litedramcore_interface_bank0_valid;
-wire          litedramcore_interface_bank0_ready;
-wire          litedramcore_interface_bank0_we;
-wire   [20:0] litedramcore_interface_bank0_addr;
-wire          litedramcore_interface_bank0_lock;
-wire          litedramcore_interface_bank0_wdata_ready;
-wire          litedramcore_interface_bank0_rdata_valid;
-wire          litedramcore_interface_bank1_valid;
-wire          litedramcore_interface_bank1_ready;
-wire          litedramcore_interface_bank1_we;
-wire   [20:0] litedramcore_interface_bank1_addr;
-wire          litedramcore_interface_bank1_lock;
-wire          litedramcore_interface_bank1_wdata_ready;
-wire          litedramcore_interface_bank1_rdata_valid;
-wire          litedramcore_interface_bank2_valid;
-wire          litedramcore_interface_bank2_ready;
-wire          litedramcore_interface_bank2_we;
-wire   [20:0] litedramcore_interface_bank2_addr;
-wire          litedramcore_interface_bank2_lock;
-wire          litedramcore_interface_bank2_wdata_ready;
-wire          litedramcore_interface_bank2_rdata_valid;
-wire          litedramcore_interface_bank3_valid;
-wire          litedramcore_interface_bank3_ready;
-wire          litedramcore_interface_bank3_we;
-wire   [20:0] litedramcore_interface_bank3_addr;
-wire          litedramcore_interface_bank3_lock;
-wire          litedramcore_interface_bank3_wdata_ready;
-wire          litedramcore_interface_bank3_rdata_valid;
-wire          litedramcore_interface_bank4_valid;
-wire          litedramcore_interface_bank4_ready;
-wire          litedramcore_interface_bank4_we;
-wire   [20:0] litedramcore_interface_bank4_addr;
-wire          litedramcore_interface_bank4_lock;
-wire          litedramcore_interface_bank4_wdata_ready;
-wire          litedramcore_interface_bank4_rdata_valid;
-wire          litedramcore_interface_bank5_valid;
-wire          litedramcore_interface_bank5_ready;
-wire          litedramcore_interface_bank5_we;
-wire   [20:0] litedramcore_interface_bank5_addr;
-wire          litedramcore_interface_bank5_lock;
-wire          litedramcore_interface_bank5_wdata_ready;
-wire          litedramcore_interface_bank5_rdata_valid;
-wire          litedramcore_interface_bank6_valid;
-wire          litedramcore_interface_bank6_ready;
-wire          litedramcore_interface_bank6_we;
-wire   [20:0] litedramcore_interface_bank6_addr;
-wire          litedramcore_interface_bank6_lock;
-wire          litedramcore_interface_bank6_wdata_ready;
-wire          litedramcore_interface_bank6_rdata_valid;
-wire          litedramcore_interface_bank7_valid;
-wire          litedramcore_interface_bank7_ready;
-wire          litedramcore_interface_bank7_we;
-wire   [20:0] litedramcore_interface_bank7_addr;
-wire          litedramcore_interface_bank7_lock;
-wire          litedramcore_interface_bank7_wdata_ready;
-wire          litedramcore_interface_bank7_rdata_valid;
-reg   [127:0] litedramcore_interface_wdata = 128'd0;
-reg    [15:0] litedramcore_interface_wdata_we = 16'd0;
-wire  [127:0] litedramcore_interface_rdata;
-reg    [13:0] litedramcore_dfi_p0_address = 14'd0;
-reg     [2:0] litedramcore_dfi_p0_bank = 3'd0;
-reg           litedramcore_dfi_p0_cas_n = 1'd1;
-reg           litedramcore_dfi_p0_cs_n = 1'd1;
-reg           litedramcore_dfi_p0_ras_n = 1'd1;
-reg           litedramcore_dfi_p0_we_n = 1'd1;
-wire          litedramcore_dfi_p0_cke;
-wire          litedramcore_dfi_p0_odt;
-wire          litedramcore_dfi_p0_reset_n;
-reg           litedramcore_dfi_p0_act_n = 1'd1;
-wire   [31:0] litedramcore_dfi_p0_wrdata;
-reg           litedramcore_dfi_p0_wrdata_en = 1'd0;
-wire    [3:0] litedramcore_dfi_p0_wrdata_mask;
-reg           litedramcore_dfi_p0_rddata_en = 1'd0;
-wire   [31:0] litedramcore_dfi_p0_rddata;
-wire          litedramcore_dfi_p0_rddata_valid;
-reg    [13:0] litedramcore_dfi_p1_address = 14'd0;
-reg     [2:0] litedramcore_dfi_p1_bank = 3'd0;
-reg           litedramcore_dfi_p1_cas_n = 1'd1;
-reg           litedramcore_dfi_p1_cs_n = 1'd1;
-reg           litedramcore_dfi_p1_ras_n = 1'd1;
-reg           litedramcore_dfi_p1_we_n = 1'd1;
-wire          litedramcore_dfi_p1_cke;
-wire          litedramcore_dfi_p1_odt;
-wire          litedramcore_dfi_p1_reset_n;
-reg           litedramcore_dfi_p1_act_n = 1'd1;
-wire   [31:0] litedramcore_dfi_p1_wrdata;
-reg           litedramcore_dfi_p1_wrdata_en = 1'd0;
-wire    [3:0] litedramcore_dfi_p1_wrdata_mask;
-reg           litedramcore_dfi_p1_rddata_en = 1'd0;
-wire   [31:0] litedramcore_dfi_p1_rddata;
-wire          litedramcore_dfi_p1_rddata_valid;
-reg    [13:0] litedramcore_dfi_p2_address = 14'd0;
-reg     [2:0] litedramcore_dfi_p2_bank = 3'd0;
-reg           litedramcore_dfi_p2_cas_n = 1'd1;
-reg           litedramcore_dfi_p2_cs_n = 1'd1;
-reg           litedramcore_dfi_p2_ras_n = 1'd1;
-reg           litedramcore_dfi_p2_we_n = 1'd1;
-wire          litedramcore_dfi_p2_cke;
-wire          litedramcore_dfi_p2_odt;
-wire          litedramcore_dfi_p2_reset_n;
-reg           litedramcore_dfi_p2_act_n = 1'd1;
-wire   [31:0] litedramcore_dfi_p2_wrdata;
-reg           litedramcore_dfi_p2_wrdata_en = 1'd0;
-wire    [3:0] litedramcore_dfi_p2_wrdata_mask;
-reg           litedramcore_dfi_p2_rddata_en = 1'd0;
-wire   [31:0] litedramcore_dfi_p2_rddata;
-wire          litedramcore_dfi_p2_rddata_valid;
-reg    [13:0] litedramcore_dfi_p3_address = 14'd0;
-reg     [2:0] litedramcore_dfi_p3_bank = 3'd0;
-reg           litedramcore_dfi_p3_cas_n = 1'd1;
-reg           litedramcore_dfi_p3_cs_n = 1'd1;
-reg           litedramcore_dfi_p3_ras_n = 1'd1;
-reg           litedramcore_dfi_p3_we_n = 1'd1;
-wire          litedramcore_dfi_p3_cke;
-wire          litedramcore_dfi_p3_odt;
-wire          litedramcore_dfi_p3_reset_n;
-reg           litedramcore_dfi_p3_act_n = 1'd1;
-wire   [31:0] litedramcore_dfi_p3_wrdata;
-reg           litedramcore_dfi_p3_wrdata_en = 1'd0;
-wire    [3:0] litedramcore_dfi_p3_wrdata_mask;
-reg           litedramcore_dfi_p3_rddata_en = 1'd0;
-wire   [31:0] litedramcore_dfi_p3_rddata;
-wire          litedramcore_dfi_p3_rddata_valid;
-reg           litedramcore_cmd_valid = 1'd0;
-reg           litedramcore_cmd_ready = 1'd0;
-reg           litedramcore_cmd_last = 1'd0;
-reg    [13:0] litedramcore_cmd_payload_a = 14'd0;
-reg     [2:0] litedramcore_cmd_payload_ba = 3'd0;
-reg           litedramcore_cmd_payload_cas = 1'd0;
-reg           litedramcore_cmd_payload_ras = 1'd0;
-reg           litedramcore_cmd_payload_we = 1'd0;
-reg           litedramcore_cmd_payload_is_read = 1'd0;
-reg           litedramcore_cmd_payload_is_write = 1'd0;
-wire          litedramcore_wants_refresh;
-wire          litedramcore_wants_zqcs;
-wire          litedramcore_timer_wait;
-wire          litedramcore_timer_done0;
-wire    [9:0] litedramcore_timer_count0;
-wire          litedramcore_timer_done1;
-reg     [9:0] litedramcore_timer_count1 = 10'd781;
-wire          litedramcore_postponer_req_i;
-reg           litedramcore_postponer_req_o = 1'd0;
-reg           litedramcore_postponer_count = 1'd0;
-reg           litedramcore_sequencer_start0 = 1'd0;
-wire          litedramcore_sequencer_done0;
-wire          litedramcore_sequencer_start1;
-reg           litedramcore_sequencer_done1 = 1'd0;
-reg     [5:0] litedramcore_sequencer_counter = 6'd0;
-reg           litedramcore_sequencer_count = 1'd0;
-wire          litedramcore_zqcs_timer_wait;
-wire          litedramcore_zqcs_timer_done0;
-wire   [26:0] litedramcore_zqcs_timer_count0;
-wire          litedramcore_zqcs_timer_done1;
-reg    [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
-reg           litedramcore_zqcs_executer_start = 1'd0;
-reg           litedramcore_zqcs_executer_done = 1'd0;
-reg     [4:0] litedramcore_zqcs_executer_counter = 5'd0;
-wire          litedramcore_bankmachine0_req_valid;
-wire          litedramcore_bankmachine0_req_ready;
-wire          litedramcore_bankmachine0_req_we;
-wire   [20:0] litedramcore_bankmachine0_req_addr;
-wire          litedramcore_bankmachine0_req_lock;
-reg           litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine0_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine0_refresh_req;
-reg           litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg    [13:0] litedramcore_bankmachine0_cmd_payload_a = 14'd0;
-wire    [2:0] litedramcore_bankmachine0_cmd_payload_ba;
-reg           litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine0_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine0_sink_valid;
-wire          litedramcore_bankmachine0_sink_ready;
-reg           litedramcore_bankmachine0_sink_first = 1'd0;
-reg           litedramcore_bankmachine0_sink_last = 1'd0;
-wire          litedramcore_bankmachine0_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine0_sink_payload_addr;
-wire          litedramcore_bankmachine0_source_valid;
-wire          litedramcore_bankmachine0_source_ready;
-wire          litedramcore_bankmachine0_source_first;
-wire          litedramcore_bankmachine0_source_last;
-wire          litedramcore_bankmachine0_source_payload_we;
-wire   [20:0] litedramcore_bankmachine0_source_payload_addr;
-wire          litedramcore_bankmachine0_syncfifo0_we;
-wire          litedramcore_bankmachine0_syncfifo0_writable;
-wire          litedramcore_bankmachine0_syncfifo0_re;
-wire          litedramcore_bankmachine0_syncfifo0_readable;
-wire   [23:0] litedramcore_bankmachine0_syncfifo0_din;
-wire   [23:0] litedramcore_bankmachine0_syncfifo0_dout;
-reg     [4:0] litedramcore_bankmachine0_level = 5'd0;
-reg           litedramcore_bankmachine0_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine0_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine0_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0;
-wire   [23:0] litedramcore_bankmachine0_wrport_dat_r;
-wire          litedramcore_bankmachine0_wrport_we;
-wire   [23:0] litedramcore_bankmachine0_wrport_dat_w;
-wire          litedramcore_bankmachine0_do_read;
-wire    [3:0] litedramcore_bankmachine0_rdport_adr;
-wire   [23:0] litedramcore_bankmachine0_rdport_dat_r;
-wire          litedramcore_bankmachine0_fifo_in_payload_we;
-wire   [20:0] litedramcore_bankmachine0_fifo_in_payload_addr;
-wire          litedramcore_bankmachine0_fifo_in_first;
-wire          litedramcore_bankmachine0_fifo_in_last;
-wire          litedramcore_bankmachine0_fifo_out_payload_we;
-wire   [20:0] litedramcore_bankmachine0_fifo_out_payload_addr;
-wire          litedramcore_bankmachine0_fifo_out_first;
-wire          litedramcore_bankmachine0_fifo_out_last;
-wire          litedramcore_bankmachine0_sink_sink_valid;
-wire          litedramcore_bankmachine0_sink_sink_ready;
-wire          litedramcore_bankmachine0_sink_sink_first;
-wire          litedramcore_bankmachine0_sink_sink_last;
-wire          litedramcore_bankmachine0_sink_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine0_sink_sink_payload_addr;
-wire          litedramcore_bankmachine0_source_source_valid;
-wire          litedramcore_bankmachine0_source_source_ready;
-wire          litedramcore_bankmachine0_source_source_first;
-wire          litedramcore_bankmachine0_source_source_last;
-wire          litedramcore_bankmachine0_source_source_payload_we;
-wire   [20:0] litedramcore_bankmachine0_source_source_payload_addr;
-wire          litedramcore_bankmachine0_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine0_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine0_pipe_valid_sink_first;
-wire          litedramcore_bankmachine0_pipe_valid_sink_last;
-wire          litedramcore_bankmachine0_pipe_valid_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine0_pipe_valid_source_ready;
-reg           litedramcore_bankmachine0_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine0_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0;
-reg    [20:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 21'd0;
-reg    [13:0] litedramcore_bankmachine0_row = 14'd0;
-reg           litedramcore_bankmachine0_row_opened = 1'd0;
-wire          litedramcore_bankmachine0_row_hit;
-reg           litedramcore_bankmachine0_row_open = 1'd0;
-reg           litedramcore_bankmachine0_row_close = 1'd0;
-reg           litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine0_twtpcon_valid;
+wire          main_a7ddrphy0;
+wire          main_a7ddrphy1;
+reg     [7:0] main_a7ddrphy_bitslip00 = 8'd0;
+reg     [7:0] main_a7ddrphy_bitslip01 = 8'd0;
+reg     [7:0] main_a7ddrphy_bitslip02 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip03;
+reg     [7:0] main_a7ddrphy_bitslip04 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip10 = 8'd0;
+reg     [7:0] main_a7ddrphy_bitslip100 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip101;
+reg     [7:0] main_a7ddrphy_bitslip102 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip11 = 8'd0;
+reg     [7:0] main_a7ddrphy_bitslip110 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip111;
+reg     [7:0] main_a7ddrphy_bitslip112 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip12 = 8'd0;
+reg     [7:0] main_a7ddrphy_bitslip120 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip121;
+reg     [7:0] main_a7ddrphy_bitslip122 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7;
+wire    [7:0] main_a7ddrphy_bitslip13;
+reg     [7:0] main_a7ddrphy_bitslip130 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip131;
+reg     [7:0] main_a7ddrphy_bitslip132 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip14 = 8'd0;
+reg     [7:0] main_a7ddrphy_bitslip140 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip141;
+reg     [7:0] main_a7ddrphy_bitslip142 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip150 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip151;
+reg     [7:0] main_a7ddrphy_bitslip152 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7;
+reg    [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip20 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip21;
+reg     [7:0] main_a7ddrphy_bitslip22 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip30 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip31;
+reg     [7:0] main_a7ddrphy_bitslip32 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip40 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip41;
+reg     [7:0] main_a7ddrphy_bitslip42 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip50 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip51;
+reg     [7:0] main_a7ddrphy_bitslip52 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip60 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip61;
+reg     [7:0] main_a7ddrphy_bitslip62 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip70 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip71;
+reg     [7:0] main_a7ddrphy_bitslip72 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip80 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip81;
+reg     [7:0] main_a7ddrphy_bitslip82 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7;
+reg     [7:0] main_a7ddrphy_bitslip90 = 8'd0;
+wire    [7:0] main_a7ddrphy_bitslip91;
+reg     [7:0] main_a7ddrphy_bitslip92 = 8'd0;
+reg    [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0;
+reg    [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0;
+reg     [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7;
+reg     [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7;
+wire          main_a7ddrphy_dfi_p0_act_n;
+wire   [13:0] main_a7ddrphy_dfi_p0_address;
+wire    [2:0] main_a7ddrphy_dfi_p0_bank;
+wire          main_a7ddrphy_dfi_p0_cas_n;
+wire          main_a7ddrphy_dfi_p0_cke;
+wire          main_a7ddrphy_dfi_p0_cs_n;
+wire          main_a7ddrphy_dfi_p0_odt;
+wire          main_a7ddrphy_dfi_p0_ras_n;
+reg    [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0;
+wire          main_a7ddrphy_dfi_p0_rddata_en;
+wire          main_a7ddrphy_dfi_p0_rddata_valid;
+wire          main_a7ddrphy_dfi_p0_reset_n;
+wire          main_a7ddrphy_dfi_p0_we_n;
+wire   [31:0] main_a7ddrphy_dfi_p0_wrdata;
+wire          main_a7ddrphy_dfi_p0_wrdata_en;
+wire    [3:0] main_a7ddrphy_dfi_p0_wrdata_mask;
+wire          main_a7ddrphy_dfi_p1_act_n;
+wire   [13:0] main_a7ddrphy_dfi_p1_address;
+wire    [2:0] main_a7ddrphy_dfi_p1_bank;
+wire          main_a7ddrphy_dfi_p1_cas_n;
+wire          main_a7ddrphy_dfi_p1_cke;
+wire          main_a7ddrphy_dfi_p1_cs_n;
+wire          main_a7ddrphy_dfi_p1_odt;
+wire          main_a7ddrphy_dfi_p1_ras_n;
+reg    [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0;
+wire          main_a7ddrphy_dfi_p1_rddata_en;
+wire          main_a7ddrphy_dfi_p1_rddata_valid;
+wire          main_a7ddrphy_dfi_p1_reset_n;
+wire          main_a7ddrphy_dfi_p1_we_n;
+wire   [31:0] main_a7ddrphy_dfi_p1_wrdata;
+wire          main_a7ddrphy_dfi_p1_wrdata_en;
+wire    [3:0] main_a7ddrphy_dfi_p1_wrdata_mask;
+wire          main_a7ddrphy_dfi_p2_act_n;
+wire   [13:0] main_a7ddrphy_dfi_p2_address;
+wire    [2:0] main_a7ddrphy_dfi_p2_bank;
+wire          main_a7ddrphy_dfi_p2_cas_n;
+wire          main_a7ddrphy_dfi_p2_cke;
+wire          main_a7ddrphy_dfi_p2_cs_n;
+wire          main_a7ddrphy_dfi_p2_odt;
+wire          main_a7ddrphy_dfi_p2_ras_n;
+reg    [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0;
+wire          main_a7ddrphy_dfi_p2_rddata_en;
+wire          main_a7ddrphy_dfi_p2_rddata_valid;
+wire          main_a7ddrphy_dfi_p2_reset_n;
+wire          main_a7ddrphy_dfi_p2_we_n;
+wire   [31:0] main_a7ddrphy_dfi_p2_wrdata;
+wire          main_a7ddrphy_dfi_p2_wrdata_en;
+wire    [3:0] main_a7ddrphy_dfi_p2_wrdata_mask;
+wire          main_a7ddrphy_dfi_p3_act_n;
+wire   [13:0] main_a7ddrphy_dfi_p3_address;
+wire    [2:0] main_a7ddrphy_dfi_p3_bank;
+wire          main_a7ddrphy_dfi_p3_cas_n;
+wire          main_a7ddrphy_dfi_p3_cke;
+wire          main_a7ddrphy_dfi_p3_cs_n;
+wire          main_a7ddrphy_dfi_p3_odt;
+wire          main_a7ddrphy_dfi_p3_ras_n;
+reg    [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0;
+wire          main_a7ddrphy_dfi_p3_rddata_en;
+wire          main_a7ddrphy_dfi_p3_rddata_valid;
+wire          main_a7ddrphy_dfi_p3_reset_n;
+wire          main_a7ddrphy_dfi_p3_we_n;
+wire   [31:0] main_a7ddrphy_dfi_p3_wrdata;
+wire          main_a7ddrphy_dfi_p3_wrdata_en;
+wire    [3:0] main_a7ddrphy_dfi_p3_wrdata_mask;
+reg           main_a7ddrphy_dly_sel_re = 1'd0;
+reg     [1:0] main_a7ddrphy_dly_sel_storage = 2'd0;
+wire          main_a7ddrphy_dq_i_delayed0;
+wire          main_a7ddrphy_dq_i_delayed1;
+wire          main_a7ddrphy_dq_i_delayed10;
+wire          main_a7ddrphy_dq_i_delayed11;
+wire          main_a7ddrphy_dq_i_delayed12;
+wire          main_a7ddrphy_dq_i_delayed13;
+wire          main_a7ddrphy_dq_i_delayed14;
+wire          main_a7ddrphy_dq_i_delayed15;
+wire          main_a7ddrphy_dq_i_delayed2;
+wire          main_a7ddrphy_dq_i_delayed3;
+wire          main_a7ddrphy_dq_i_delayed4;
+wire          main_a7ddrphy_dq_i_delayed5;
+wire          main_a7ddrphy_dq_i_delayed6;
+wire          main_a7ddrphy_dq_i_delayed7;
+wire          main_a7ddrphy_dq_i_delayed8;
+wire          main_a7ddrphy_dq_i_delayed9;
+wire          main_a7ddrphy_dq_i_nodelay0;
+wire          main_a7ddrphy_dq_i_nodelay1;
+wire          main_a7ddrphy_dq_i_nodelay10;
+wire          main_a7ddrphy_dq_i_nodelay11;
+wire          main_a7ddrphy_dq_i_nodelay12;
+wire          main_a7ddrphy_dq_i_nodelay13;
+wire          main_a7ddrphy_dq_i_nodelay14;
+wire          main_a7ddrphy_dq_i_nodelay15;
+wire          main_a7ddrphy_dq_i_nodelay2;
+wire          main_a7ddrphy_dq_i_nodelay3;
+wire          main_a7ddrphy_dq_i_nodelay4;
+wire          main_a7ddrphy_dq_i_nodelay5;
+wire          main_a7ddrphy_dq_i_nodelay6;
+wire          main_a7ddrphy_dq_i_nodelay7;
+wire          main_a7ddrphy_dq_i_nodelay8;
+wire          main_a7ddrphy_dq_i_nodelay9;
+wire          main_a7ddrphy_dq_o_nodelay0;
+wire          main_a7ddrphy_dq_o_nodelay1;
+wire          main_a7ddrphy_dq_o_nodelay10;
+wire          main_a7ddrphy_dq_o_nodelay11;
+wire          main_a7ddrphy_dq_o_nodelay12;
+wire          main_a7ddrphy_dq_o_nodelay13;
+wire          main_a7ddrphy_dq_o_nodelay14;
+wire          main_a7ddrphy_dq_o_nodelay15;
+wire          main_a7ddrphy_dq_o_nodelay2;
+wire          main_a7ddrphy_dq_o_nodelay3;
+wire          main_a7ddrphy_dq_o_nodelay4;
+wire          main_a7ddrphy_dq_o_nodelay5;
+wire          main_a7ddrphy_dq_o_nodelay6;
+wire          main_a7ddrphy_dq_o_nodelay7;
+wire          main_a7ddrphy_dq_o_nodelay8;
+wire          main_a7ddrphy_dq_o_nodelay9;
+wire          main_a7ddrphy_dq_oe;
+wire          main_a7ddrphy_dq_oe_delay_tappeddelayline;
+reg           main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg           main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+wire          main_a7ddrphy_dq_t0;
+wire          main_a7ddrphy_dq_t1;
+wire          main_a7ddrphy_dq_t10;
+wire          main_a7ddrphy_dq_t11;
+wire          main_a7ddrphy_dq_t12;
+wire          main_a7ddrphy_dq_t13;
+wire          main_a7ddrphy_dq_t14;
+wire          main_a7ddrphy_dq_t15;
+wire          main_a7ddrphy_dq_t2;
+wire          main_a7ddrphy_dq_t3;
+wire          main_a7ddrphy_dq_t4;
+wire          main_a7ddrphy_dq_t5;
+wire          main_a7ddrphy_dq_t6;
+wire          main_a7ddrphy_dq_t7;
+wire          main_a7ddrphy_dq_t8;
+wire          main_a7ddrphy_dq_t9;
+wire          main_a7ddrphy_dqs_o_no_delay0;
+wire          main_a7ddrphy_dqs_o_no_delay1;
+reg           main_a7ddrphy_dqs_oe = 1'd0;
+wire          main_a7ddrphy_dqs_oe_delay_tappeddelayline;
+reg           main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg           main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+wire          main_a7ddrphy_dqs_postamble;
+wire          main_a7ddrphy_dqs_preamble;
+wire          main_a7ddrphy_dqs_t0;
+wire          main_a7ddrphy_dqs_t1;
+reg           main_a7ddrphy_dqspattern0 = 1'd0;
+reg           main_a7ddrphy_dqspattern1 = 1'd0;
+reg     [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0;
+reg     [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0;
+reg           main_a7ddrphy_half_sys8x_taps_re = 1'd0;
+reg     [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8;
+wire    [2:0] main_a7ddrphy_pads_ba;
+reg           main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
+reg           main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
+wire          main_a7ddrphy_rdly_dq_bitslip_r;
+reg           main_a7ddrphy_rdly_dq_bitslip_re = 1'd0;
+wire          main_a7ddrphy_rdly_dq_bitslip_rst_r;
+reg           main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
+reg           main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+reg           main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
+reg           main_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
+reg           main_a7ddrphy_rdly_dq_bitslip_we = 1'd0;
+wire          main_a7ddrphy_rdly_dq_inc_r;
+reg           main_a7ddrphy_rdly_dq_inc_re = 1'd0;
+reg           main_a7ddrphy_rdly_dq_inc_w = 1'd0;
+reg           main_a7ddrphy_rdly_dq_inc_we = 1'd0;
+wire          main_a7ddrphy_rdly_dq_rst_r;
+reg           main_a7ddrphy_rdly_dq_rst_re = 1'd0;
+reg           main_a7ddrphy_rdly_dq_rst_w = 1'd0;
+reg           main_a7ddrphy_rdly_dq_rst_we = 1'd0;
+reg           main_a7ddrphy_rdphase_re = 1'd0;
+reg     [1:0] main_a7ddrphy_rdphase_storage = 2'd2;
+reg           main_a7ddrphy_rst_re = 1'd0;
+reg           main_a7ddrphy_rst_storage = 1'd0;
+wire          main_a7ddrphy_sd_clk_se_nodelay;
+wire          main_a7ddrphy_wdly_dq_bitslip_r;
+reg           main_a7ddrphy_wdly_dq_bitslip_re = 1'd0;
+wire          main_a7ddrphy_wdly_dq_bitslip_rst_r;
+reg           main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
+reg           main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
+reg           main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
+reg           main_a7ddrphy_wdly_dq_bitslip_w = 1'd0;
+reg           main_a7ddrphy_wdly_dq_bitslip_we = 1'd0;
+reg           main_a7ddrphy_wlevel_en_re = 1'd0;
+reg           main_a7ddrphy_wlevel_en_storage = 1'd0;
+wire          main_a7ddrphy_wlevel_strobe_r;
+reg           main_a7ddrphy_wlevel_strobe_re = 1'd0;
+reg           main_a7ddrphy_wlevel_strobe_w = 1'd0;
+reg           main_a7ddrphy_wlevel_strobe_we = 1'd0;
+reg           main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
+reg           main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
+reg           main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
+reg           main_a7ddrphy_wrphase_re = 1'd0;
+reg     [1:0] main_a7ddrphy_wrphase_storage = 2'd3;
+wire          main_clkin;
+wire          main_clkout0;
+wire          main_clkout1;
+wire          main_clkout2;
+wire          main_clkout3;
+wire          main_clkout_buf0;
+wire          main_clkout_buf1;
+wire          main_clkout_buf2;
+wire          main_clkout_buf3;
+reg           main_ic_reset = 1'd1;
+reg           main_init_done_re = 1'd0;
+reg           main_init_done_storage = 1'd0;
+reg           main_init_error_re = 1'd0;
+reg           main_init_error_storage = 1'd0;
+reg           main_litedramcore_bankmachine0_auto_precharge = 1'd0;
+reg    [13:0] main_litedramcore_bankmachine0_cmd_payload_a = 14'd0;
+wire    [2:0] main_litedramcore_bankmachine0_cmd_payload_ba;
+reg           main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine0_consume = 4'd0;
+wire          main_litedramcore_bankmachine0_do_read;
+wire          main_litedramcore_bankmachine0_fifo_in_first;
+wire          main_litedramcore_bankmachine0_fifo_in_last;
+wire   [20:0] main_litedramcore_bankmachine0_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine0_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine0_fifo_out_first;
+wire          main_litedramcore_bankmachine0_fifo_out_last;
+wire   [20:0] main_litedramcore_bankmachine0_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine0_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine0_level = 5'd0;
+wire          main_litedramcore_bankmachine0_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine0_pipe_valid_sink_last;
+wire   [20:0] main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine0_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine0_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine0_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine0_pipe_valid_source_last = 1'd0;
+reg    [20:0] main_litedramcore_bankmachine0_pipe_valid_source_payload_addr = 21'd0;
+reg           main_litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine0_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine0_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine0_rdport_adr;
+wire   [23:0] main_litedramcore_bankmachine0_rdport_dat_r;
+reg           main_litedramcore_bankmachine0_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine0_refresh_req;
+reg           main_litedramcore_bankmachine0_replace = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine0_req_addr;
+wire          main_litedramcore_bankmachine0_req_lock;
+reg           main_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine0_req_ready;
+wire          main_litedramcore_bankmachine0_req_valid;
+reg           main_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine0_req_we;
+reg    [13:0] main_litedramcore_bankmachine0_row = 14'd0;
+reg           main_litedramcore_bankmachine0_row_close = 1'd0;
+reg           main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine0_row_hit;
+reg           main_litedramcore_bankmachine0_row_open = 1'd0;
+reg           main_litedramcore_bankmachine0_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine0_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine0_sink_last = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine0_sink_payload_addr;
+wire          main_litedramcore_bankmachine0_sink_payload_we;
+wire          main_litedramcore_bankmachine0_sink_ready;
+wire          main_litedramcore_bankmachine0_sink_sink_first;
+wire          main_litedramcore_bankmachine0_sink_sink_last;
+wire   [20:0] main_litedramcore_bankmachine0_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine0_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine0_sink_sink_ready;
+wire          main_litedramcore_bankmachine0_sink_sink_valid;
+wire          main_litedramcore_bankmachine0_sink_valid;
+wire          main_litedramcore_bankmachine0_source_first;
+wire          main_litedramcore_bankmachine0_source_last;
+wire   [20:0] main_litedramcore_bankmachine0_source_payload_addr;
+wire          main_litedramcore_bankmachine0_source_payload_we;
+wire          main_litedramcore_bankmachine0_source_ready;
+wire          main_litedramcore_bankmachine0_source_source_first;
+wire          main_litedramcore_bankmachine0_source_source_last;
+wire   [20:0] main_litedramcore_bankmachine0_source_source_payload_addr;
+wire          main_litedramcore_bankmachine0_source_source_payload_we;
+wire          main_litedramcore_bankmachine0_source_source_ready;
+wire          main_litedramcore_bankmachine0_source_source_valid;
+wire          main_litedramcore_bankmachine0_source_valid;
+wire   [23:0] main_litedramcore_bankmachine0_syncfifo0_din;
+wire   [23:0] main_litedramcore_bankmachine0_syncfifo0_dout;
+wire          main_litedramcore_bankmachine0_syncfifo0_re;
+wire          main_litedramcore_bankmachine0_syncfifo0_readable;
+wire          main_litedramcore_bankmachine0_syncfifo0_we;
+wire          main_litedramcore_bankmachine0_syncfifo0_writable;
+reg     [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine0_trccon_valid;
+reg           main_litedramcore_bankmachine0_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine0_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
-wire          litedramcore_bankmachine0_trascon_valid;
+reg           main_litedramcore_bankmachine0_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine0_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine0_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
-wire          litedramcore_bankmachine1_req_valid;
-wire          litedramcore_bankmachine1_req_ready;
-wire          litedramcore_bankmachine1_req_we;
-wire   [20:0] litedramcore_bankmachine1_req_addr;
-wire          litedramcore_bankmachine1_req_lock;
-reg           litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine1_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine1_refresh_req;
-reg           litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine1_cmd_ready = 1'd0;
-reg    [13:0] litedramcore_bankmachine1_cmd_payload_a = 14'd0;
-wire    [2:0] litedramcore_bankmachine1_cmd_payload_ba;
-reg           litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine1_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine1_sink_valid;
-wire          litedramcore_bankmachine1_sink_ready;
-reg           litedramcore_bankmachine1_sink_first = 1'd0;
-reg           litedramcore_bankmachine1_sink_last = 1'd0;
-wire          litedramcore_bankmachine1_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine1_sink_payload_addr;
-wire          litedramcore_bankmachine1_source_valid;
-wire          litedramcore_bankmachine1_source_ready;
-wire          litedramcore_bankmachine1_source_first;
-wire          litedramcore_bankmachine1_source_last;
-wire          litedramcore_bankmachine1_source_payload_we;
-wire   [20:0] litedramcore_bankmachine1_source_payload_addr;
-wire          litedramcore_bankmachine1_syncfifo1_we;
-wire          litedramcore_bankmachine1_syncfifo1_writable;
-wire          litedramcore_bankmachine1_syncfifo1_re;
-wire          litedramcore_bankmachine1_syncfifo1_readable;
-wire   [23:0] litedramcore_bankmachine1_syncfifo1_din;
-wire   [23:0] litedramcore_bankmachine1_syncfifo1_dout;
-reg     [4:0] litedramcore_bankmachine1_level = 5'd0;
-reg           litedramcore_bankmachine1_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine1_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine1_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0;
-wire   [23:0] litedramcore_bankmachine1_wrport_dat_r;
-wire          litedramcore_bankmachine1_wrport_we;
-wire   [23:0] litedramcore_bankmachine1_wrport_dat_w;
-wire          litedramcore_bankmachine1_do_read;
-wire    [3:0] litedramcore_bankmachine1_rdport_adr;
-wire   [23:0] litedramcore_bankmachine1_rdport_dat_r;
-wire          litedramcore_bankmachine1_fifo_in_payload_we;
-wire   [20:0] litedramcore_bankmachine1_fifo_in_payload_addr;
-wire          litedramcore_bankmachine1_fifo_in_first;
-wire          litedramcore_bankmachine1_fifo_in_last;
-wire          litedramcore_bankmachine1_fifo_out_payload_we;
-wire   [20:0] litedramcore_bankmachine1_fifo_out_payload_addr;
-wire          litedramcore_bankmachine1_fifo_out_first;
-wire          litedramcore_bankmachine1_fifo_out_last;
-wire          litedramcore_bankmachine1_sink_sink_valid;
-wire          litedramcore_bankmachine1_sink_sink_ready;
-wire          litedramcore_bankmachine1_sink_sink_first;
-wire          litedramcore_bankmachine1_sink_sink_last;
-wire          litedramcore_bankmachine1_sink_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine1_sink_sink_payload_addr;
-wire          litedramcore_bankmachine1_source_source_valid;
-wire          litedramcore_bankmachine1_source_source_ready;
-wire          litedramcore_bankmachine1_source_source_first;
-wire          litedramcore_bankmachine1_source_source_last;
-wire          litedramcore_bankmachine1_source_source_payload_we;
-wire   [20:0] litedramcore_bankmachine1_source_source_payload_addr;
-wire          litedramcore_bankmachine1_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine1_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine1_pipe_valid_sink_first;
-wire          litedramcore_bankmachine1_pipe_valid_sink_last;
-wire          litedramcore_bankmachine1_pipe_valid_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine1_pipe_valid_source_ready;
-reg           litedramcore_bankmachine1_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine1_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0;
-reg    [20:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 21'd0;
-reg    [13:0] litedramcore_bankmachine1_row = 14'd0;
-reg           litedramcore_bankmachine1_row_opened = 1'd0;
-wire          litedramcore_bankmachine1_row_hit;
-reg           litedramcore_bankmachine1_row_open = 1'd0;
-reg           litedramcore_bankmachine1_row_close = 1'd0;
-reg           litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine1_twtpcon_valid;
+reg           main_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine0_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine0_wrport_adr = 4'd0;
+wire   [23:0] main_litedramcore_bankmachine0_wrport_dat_r;
+wire   [23:0] main_litedramcore_bankmachine0_wrport_dat_w;
+wire          main_litedramcore_bankmachine0_wrport_we;
+reg           main_litedramcore_bankmachine1_auto_precharge = 1'd0;
+reg    [13:0] main_litedramcore_bankmachine1_cmd_payload_a = 14'd0;
+wire    [2:0] main_litedramcore_bankmachine1_cmd_payload_ba;
+reg           main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine1_consume = 4'd0;
+wire          main_litedramcore_bankmachine1_do_read;
+wire          main_litedramcore_bankmachine1_fifo_in_first;
+wire          main_litedramcore_bankmachine1_fifo_in_last;
+wire   [20:0] main_litedramcore_bankmachine1_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine1_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine1_fifo_out_first;
+wire          main_litedramcore_bankmachine1_fifo_out_last;
+wire   [20:0] main_litedramcore_bankmachine1_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine1_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine1_level = 5'd0;
+wire          main_litedramcore_bankmachine1_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine1_pipe_valid_sink_last;
+wire   [20:0] main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine1_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine1_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine1_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine1_pipe_valid_source_last = 1'd0;
+reg    [20:0] main_litedramcore_bankmachine1_pipe_valid_source_payload_addr = 21'd0;
+reg           main_litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine1_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine1_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine1_rdport_adr;
+wire   [23:0] main_litedramcore_bankmachine1_rdport_dat_r;
+reg           main_litedramcore_bankmachine1_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine1_refresh_req;
+reg           main_litedramcore_bankmachine1_replace = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine1_req_addr;
+wire          main_litedramcore_bankmachine1_req_lock;
+reg           main_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine1_req_ready;
+wire          main_litedramcore_bankmachine1_req_valid;
+reg           main_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine1_req_we;
+reg    [13:0] main_litedramcore_bankmachine1_row = 14'd0;
+reg           main_litedramcore_bankmachine1_row_close = 1'd0;
+reg           main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine1_row_hit;
+reg           main_litedramcore_bankmachine1_row_open = 1'd0;
+reg           main_litedramcore_bankmachine1_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine1_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine1_sink_last = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine1_sink_payload_addr;
+wire          main_litedramcore_bankmachine1_sink_payload_we;
+wire          main_litedramcore_bankmachine1_sink_ready;
+wire          main_litedramcore_bankmachine1_sink_sink_first;
+wire          main_litedramcore_bankmachine1_sink_sink_last;
+wire   [20:0] main_litedramcore_bankmachine1_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine1_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine1_sink_sink_ready;
+wire          main_litedramcore_bankmachine1_sink_sink_valid;
+wire          main_litedramcore_bankmachine1_sink_valid;
+wire          main_litedramcore_bankmachine1_source_first;
+wire          main_litedramcore_bankmachine1_source_last;
+wire   [20:0] main_litedramcore_bankmachine1_source_payload_addr;
+wire          main_litedramcore_bankmachine1_source_payload_we;
+wire          main_litedramcore_bankmachine1_source_ready;
+wire          main_litedramcore_bankmachine1_source_source_first;
+wire          main_litedramcore_bankmachine1_source_source_last;
+wire   [20:0] main_litedramcore_bankmachine1_source_source_payload_addr;
+wire          main_litedramcore_bankmachine1_source_source_payload_we;
+wire          main_litedramcore_bankmachine1_source_source_ready;
+wire          main_litedramcore_bankmachine1_source_source_valid;
+wire          main_litedramcore_bankmachine1_source_valid;
+wire   [23:0] main_litedramcore_bankmachine1_syncfifo1_din;
+wire   [23:0] main_litedramcore_bankmachine1_syncfifo1_dout;
+wire          main_litedramcore_bankmachine1_syncfifo1_re;
+wire          main_litedramcore_bankmachine1_syncfifo1_readable;
+wire          main_litedramcore_bankmachine1_syncfifo1_we;
+wire          main_litedramcore_bankmachine1_syncfifo1_writable;
+reg     [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine1_trccon_valid;
+reg           main_litedramcore_bankmachine1_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine1_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
-wire          litedramcore_bankmachine1_trascon_valid;
+reg           main_litedramcore_bankmachine1_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine1_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine1_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
-wire          litedramcore_bankmachine2_req_valid;
-wire          litedramcore_bankmachine2_req_ready;
-wire          litedramcore_bankmachine2_req_we;
-wire   [20:0] litedramcore_bankmachine2_req_addr;
-wire          litedramcore_bankmachine2_req_lock;
-reg           litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine2_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine2_refresh_req;
-reg           litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine2_cmd_ready = 1'd0;
-reg    [13:0] litedramcore_bankmachine2_cmd_payload_a = 14'd0;
-wire    [2:0] litedramcore_bankmachine2_cmd_payload_ba;
-reg           litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine2_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine2_sink_valid;
-wire          litedramcore_bankmachine2_sink_ready;
-reg           litedramcore_bankmachine2_sink_first = 1'd0;
-reg           litedramcore_bankmachine2_sink_last = 1'd0;
-wire          litedramcore_bankmachine2_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine2_sink_payload_addr;
-wire          litedramcore_bankmachine2_source_valid;
-wire          litedramcore_bankmachine2_source_ready;
-wire          litedramcore_bankmachine2_source_first;
-wire          litedramcore_bankmachine2_source_last;
-wire          litedramcore_bankmachine2_source_payload_we;
-wire   [20:0] litedramcore_bankmachine2_source_payload_addr;
-wire          litedramcore_bankmachine2_syncfifo2_we;
-wire          litedramcore_bankmachine2_syncfifo2_writable;
-wire          litedramcore_bankmachine2_syncfifo2_re;
-wire          litedramcore_bankmachine2_syncfifo2_readable;
-wire   [23:0] litedramcore_bankmachine2_syncfifo2_din;
-wire   [23:0] litedramcore_bankmachine2_syncfifo2_dout;
-reg     [4:0] litedramcore_bankmachine2_level = 5'd0;
-reg           litedramcore_bankmachine2_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine2_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine2_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0;
-wire   [23:0] litedramcore_bankmachine2_wrport_dat_r;
-wire          litedramcore_bankmachine2_wrport_we;
-wire   [23:0] litedramcore_bankmachine2_wrport_dat_w;
-wire          litedramcore_bankmachine2_do_read;
-wire    [3:0] litedramcore_bankmachine2_rdport_adr;
-wire   [23:0] litedramcore_bankmachine2_rdport_dat_r;
-wire          litedramcore_bankmachine2_fifo_in_payload_we;
-wire   [20:0] litedramcore_bankmachine2_fifo_in_payload_addr;
-wire          litedramcore_bankmachine2_fifo_in_first;
-wire          litedramcore_bankmachine2_fifo_in_last;
-wire          litedramcore_bankmachine2_fifo_out_payload_we;
-wire   [20:0] litedramcore_bankmachine2_fifo_out_payload_addr;
-wire          litedramcore_bankmachine2_fifo_out_first;
-wire          litedramcore_bankmachine2_fifo_out_last;
-wire          litedramcore_bankmachine2_sink_sink_valid;
-wire          litedramcore_bankmachine2_sink_sink_ready;
-wire          litedramcore_bankmachine2_sink_sink_first;
-wire          litedramcore_bankmachine2_sink_sink_last;
-wire          litedramcore_bankmachine2_sink_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine2_sink_sink_payload_addr;
-wire          litedramcore_bankmachine2_source_source_valid;
-wire          litedramcore_bankmachine2_source_source_ready;
-wire          litedramcore_bankmachine2_source_source_first;
-wire          litedramcore_bankmachine2_source_source_last;
-wire          litedramcore_bankmachine2_source_source_payload_we;
-wire   [20:0] litedramcore_bankmachine2_source_source_payload_addr;
-wire          litedramcore_bankmachine2_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine2_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine2_pipe_valid_sink_first;
-wire          litedramcore_bankmachine2_pipe_valid_sink_last;
-wire          litedramcore_bankmachine2_pipe_valid_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine2_pipe_valid_source_ready;
-reg           litedramcore_bankmachine2_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine2_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0;
-reg    [20:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 21'd0;
-reg    [13:0] litedramcore_bankmachine2_row = 14'd0;
-reg           litedramcore_bankmachine2_row_opened = 1'd0;
-wire          litedramcore_bankmachine2_row_hit;
-reg           litedramcore_bankmachine2_row_open = 1'd0;
-reg           litedramcore_bankmachine2_row_close = 1'd0;
-reg           litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine2_twtpcon_valid;
+reg           main_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine1_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine1_wrport_adr = 4'd0;
+wire   [23:0] main_litedramcore_bankmachine1_wrport_dat_r;
+wire   [23:0] main_litedramcore_bankmachine1_wrport_dat_w;
+wire          main_litedramcore_bankmachine1_wrport_we;
+reg           main_litedramcore_bankmachine2_auto_precharge = 1'd0;
+reg    [13:0] main_litedramcore_bankmachine2_cmd_payload_a = 14'd0;
+wire    [2:0] main_litedramcore_bankmachine2_cmd_payload_ba;
+reg           main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine2_consume = 4'd0;
+wire          main_litedramcore_bankmachine2_do_read;
+wire          main_litedramcore_bankmachine2_fifo_in_first;
+wire          main_litedramcore_bankmachine2_fifo_in_last;
+wire   [20:0] main_litedramcore_bankmachine2_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine2_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine2_fifo_out_first;
+wire          main_litedramcore_bankmachine2_fifo_out_last;
+wire   [20:0] main_litedramcore_bankmachine2_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine2_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine2_level = 5'd0;
+wire          main_litedramcore_bankmachine2_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine2_pipe_valid_sink_last;
+wire   [20:0] main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine2_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine2_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine2_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine2_pipe_valid_source_last = 1'd0;
+reg    [20:0] main_litedramcore_bankmachine2_pipe_valid_source_payload_addr = 21'd0;
+reg           main_litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine2_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine2_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine2_rdport_adr;
+wire   [23:0] main_litedramcore_bankmachine2_rdport_dat_r;
+reg           main_litedramcore_bankmachine2_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine2_refresh_req;
+reg           main_litedramcore_bankmachine2_replace = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine2_req_addr;
+wire          main_litedramcore_bankmachine2_req_lock;
+reg           main_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine2_req_ready;
+wire          main_litedramcore_bankmachine2_req_valid;
+reg           main_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine2_req_we;
+reg    [13:0] main_litedramcore_bankmachine2_row = 14'd0;
+reg           main_litedramcore_bankmachine2_row_close = 1'd0;
+reg           main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine2_row_hit;
+reg           main_litedramcore_bankmachine2_row_open = 1'd0;
+reg           main_litedramcore_bankmachine2_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine2_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine2_sink_last = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine2_sink_payload_addr;
+wire          main_litedramcore_bankmachine2_sink_payload_we;
+wire          main_litedramcore_bankmachine2_sink_ready;
+wire          main_litedramcore_bankmachine2_sink_sink_first;
+wire          main_litedramcore_bankmachine2_sink_sink_last;
+wire   [20:0] main_litedramcore_bankmachine2_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine2_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine2_sink_sink_ready;
+wire          main_litedramcore_bankmachine2_sink_sink_valid;
+wire          main_litedramcore_bankmachine2_sink_valid;
+wire          main_litedramcore_bankmachine2_source_first;
+wire          main_litedramcore_bankmachine2_source_last;
+wire   [20:0] main_litedramcore_bankmachine2_source_payload_addr;
+wire          main_litedramcore_bankmachine2_source_payload_we;
+wire          main_litedramcore_bankmachine2_source_ready;
+wire          main_litedramcore_bankmachine2_source_source_first;
+wire          main_litedramcore_bankmachine2_source_source_last;
+wire   [20:0] main_litedramcore_bankmachine2_source_source_payload_addr;
+wire          main_litedramcore_bankmachine2_source_source_payload_we;
+wire          main_litedramcore_bankmachine2_source_source_ready;
+wire          main_litedramcore_bankmachine2_source_source_valid;
+wire          main_litedramcore_bankmachine2_source_valid;
+wire   [23:0] main_litedramcore_bankmachine2_syncfifo2_din;
+wire   [23:0] main_litedramcore_bankmachine2_syncfifo2_dout;
+wire          main_litedramcore_bankmachine2_syncfifo2_re;
+wire          main_litedramcore_bankmachine2_syncfifo2_readable;
+wire          main_litedramcore_bankmachine2_syncfifo2_we;
+wire          main_litedramcore_bankmachine2_syncfifo2_writable;
+reg     [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine2_trccon_valid;
+reg           main_litedramcore_bankmachine2_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine2_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
-wire          litedramcore_bankmachine2_trascon_valid;
+reg           main_litedramcore_bankmachine2_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine2_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine2_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
-wire          litedramcore_bankmachine3_req_valid;
-wire          litedramcore_bankmachine3_req_ready;
-wire          litedramcore_bankmachine3_req_we;
-wire   [20:0] litedramcore_bankmachine3_req_addr;
-wire          litedramcore_bankmachine3_req_lock;
-reg           litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine3_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine3_refresh_req;
-reg           litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine3_cmd_ready = 1'd0;
-reg    [13:0] litedramcore_bankmachine3_cmd_payload_a = 14'd0;
-wire    [2:0] litedramcore_bankmachine3_cmd_payload_ba;
-reg           litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine3_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine3_sink_valid;
-wire          litedramcore_bankmachine3_sink_ready;
-reg           litedramcore_bankmachine3_sink_first = 1'd0;
-reg           litedramcore_bankmachine3_sink_last = 1'd0;
-wire          litedramcore_bankmachine3_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine3_sink_payload_addr;
-wire          litedramcore_bankmachine3_source_valid;
-wire          litedramcore_bankmachine3_source_ready;
-wire          litedramcore_bankmachine3_source_first;
-wire          litedramcore_bankmachine3_source_last;
-wire          litedramcore_bankmachine3_source_payload_we;
-wire   [20:0] litedramcore_bankmachine3_source_payload_addr;
-wire          litedramcore_bankmachine3_syncfifo3_we;
-wire          litedramcore_bankmachine3_syncfifo3_writable;
-wire          litedramcore_bankmachine3_syncfifo3_re;
-wire          litedramcore_bankmachine3_syncfifo3_readable;
-wire   [23:0] litedramcore_bankmachine3_syncfifo3_din;
-wire   [23:0] litedramcore_bankmachine3_syncfifo3_dout;
-reg     [4:0] litedramcore_bankmachine3_level = 5'd0;
-reg           litedramcore_bankmachine3_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine3_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine3_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0;
-wire   [23:0] litedramcore_bankmachine3_wrport_dat_r;
-wire          litedramcore_bankmachine3_wrport_we;
-wire   [23:0] litedramcore_bankmachine3_wrport_dat_w;
-wire          litedramcore_bankmachine3_do_read;
-wire    [3:0] litedramcore_bankmachine3_rdport_adr;
-wire   [23:0] litedramcore_bankmachine3_rdport_dat_r;
-wire          litedramcore_bankmachine3_fifo_in_payload_we;
-wire   [20:0] litedramcore_bankmachine3_fifo_in_payload_addr;
-wire          litedramcore_bankmachine3_fifo_in_first;
-wire          litedramcore_bankmachine3_fifo_in_last;
-wire          litedramcore_bankmachine3_fifo_out_payload_we;
-wire   [20:0] litedramcore_bankmachine3_fifo_out_payload_addr;
-wire          litedramcore_bankmachine3_fifo_out_first;
-wire          litedramcore_bankmachine3_fifo_out_last;
-wire          litedramcore_bankmachine3_sink_sink_valid;
-wire          litedramcore_bankmachine3_sink_sink_ready;
-wire          litedramcore_bankmachine3_sink_sink_first;
-wire          litedramcore_bankmachine3_sink_sink_last;
-wire          litedramcore_bankmachine3_sink_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine3_sink_sink_payload_addr;
-wire          litedramcore_bankmachine3_source_source_valid;
-wire          litedramcore_bankmachine3_source_source_ready;
-wire          litedramcore_bankmachine3_source_source_first;
-wire          litedramcore_bankmachine3_source_source_last;
-wire          litedramcore_bankmachine3_source_source_payload_we;
-wire   [20:0] litedramcore_bankmachine3_source_source_payload_addr;
-wire          litedramcore_bankmachine3_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine3_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine3_pipe_valid_sink_first;
-wire          litedramcore_bankmachine3_pipe_valid_sink_last;
-wire          litedramcore_bankmachine3_pipe_valid_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine3_pipe_valid_source_ready;
-reg           litedramcore_bankmachine3_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine3_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0;
-reg    [20:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 21'd0;
-reg    [13:0] litedramcore_bankmachine3_row = 14'd0;
-reg           litedramcore_bankmachine3_row_opened = 1'd0;
-wire          litedramcore_bankmachine3_row_hit;
-reg           litedramcore_bankmachine3_row_open = 1'd0;
-reg           litedramcore_bankmachine3_row_close = 1'd0;
-reg           litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine3_twtpcon_valid;
+reg           main_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine2_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine2_wrport_adr = 4'd0;
+wire   [23:0] main_litedramcore_bankmachine2_wrport_dat_r;
+wire   [23:0] main_litedramcore_bankmachine2_wrport_dat_w;
+wire          main_litedramcore_bankmachine2_wrport_we;
+reg           main_litedramcore_bankmachine3_auto_precharge = 1'd0;
+reg    [13:0] main_litedramcore_bankmachine3_cmd_payload_a = 14'd0;
+wire    [2:0] main_litedramcore_bankmachine3_cmd_payload_ba;
+reg           main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine3_consume = 4'd0;
+wire          main_litedramcore_bankmachine3_do_read;
+wire          main_litedramcore_bankmachine3_fifo_in_first;
+wire          main_litedramcore_bankmachine3_fifo_in_last;
+wire   [20:0] main_litedramcore_bankmachine3_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine3_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine3_fifo_out_first;
+wire          main_litedramcore_bankmachine3_fifo_out_last;
+wire   [20:0] main_litedramcore_bankmachine3_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine3_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine3_level = 5'd0;
+wire          main_litedramcore_bankmachine3_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine3_pipe_valid_sink_last;
+wire   [20:0] main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine3_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine3_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine3_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine3_pipe_valid_source_last = 1'd0;
+reg    [20:0] main_litedramcore_bankmachine3_pipe_valid_source_payload_addr = 21'd0;
+reg           main_litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine3_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine3_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine3_rdport_adr;
+wire   [23:0] main_litedramcore_bankmachine3_rdport_dat_r;
+reg           main_litedramcore_bankmachine3_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine3_refresh_req;
+reg           main_litedramcore_bankmachine3_replace = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine3_req_addr;
+wire          main_litedramcore_bankmachine3_req_lock;
+reg           main_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine3_req_ready;
+wire          main_litedramcore_bankmachine3_req_valid;
+reg           main_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine3_req_we;
+reg    [13:0] main_litedramcore_bankmachine3_row = 14'd0;
+reg           main_litedramcore_bankmachine3_row_close = 1'd0;
+reg           main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine3_row_hit;
+reg           main_litedramcore_bankmachine3_row_open = 1'd0;
+reg           main_litedramcore_bankmachine3_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine3_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine3_sink_last = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine3_sink_payload_addr;
+wire          main_litedramcore_bankmachine3_sink_payload_we;
+wire          main_litedramcore_bankmachine3_sink_ready;
+wire          main_litedramcore_bankmachine3_sink_sink_first;
+wire          main_litedramcore_bankmachine3_sink_sink_last;
+wire   [20:0] main_litedramcore_bankmachine3_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine3_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine3_sink_sink_ready;
+wire          main_litedramcore_bankmachine3_sink_sink_valid;
+wire          main_litedramcore_bankmachine3_sink_valid;
+wire          main_litedramcore_bankmachine3_source_first;
+wire          main_litedramcore_bankmachine3_source_last;
+wire   [20:0] main_litedramcore_bankmachine3_source_payload_addr;
+wire          main_litedramcore_bankmachine3_source_payload_we;
+wire          main_litedramcore_bankmachine3_source_ready;
+wire          main_litedramcore_bankmachine3_source_source_first;
+wire          main_litedramcore_bankmachine3_source_source_last;
+wire   [20:0] main_litedramcore_bankmachine3_source_source_payload_addr;
+wire          main_litedramcore_bankmachine3_source_source_payload_we;
+wire          main_litedramcore_bankmachine3_source_source_ready;
+wire          main_litedramcore_bankmachine3_source_source_valid;
+wire          main_litedramcore_bankmachine3_source_valid;
+wire   [23:0] main_litedramcore_bankmachine3_syncfifo3_din;
+wire   [23:0] main_litedramcore_bankmachine3_syncfifo3_dout;
+wire          main_litedramcore_bankmachine3_syncfifo3_re;
+wire          main_litedramcore_bankmachine3_syncfifo3_readable;
+wire          main_litedramcore_bankmachine3_syncfifo3_we;
+wire          main_litedramcore_bankmachine3_syncfifo3_writable;
+reg     [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine3_trccon_valid;
+reg           main_litedramcore_bankmachine3_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine3_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
-wire          litedramcore_bankmachine3_trascon_valid;
+reg           main_litedramcore_bankmachine3_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine3_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine3_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
-wire          litedramcore_bankmachine4_req_valid;
-wire          litedramcore_bankmachine4_req_ready;
-wire          litedramcore_bankmachine4_req_we;
-wire   [20:0] litedramcore_bankmachine4_req_addr;
-wire          litedramcore_bankmachine4_req_lock;
-reg           litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine4_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine4_refresh_req;
-reg           litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine4_cmd_ready = 1'd0;
-reg    [13:0] litedramcore_bankmachine4_cmd_payload_a = 14'd0;
-wire    [2:0] litedramcore_bankmachine4_cmd_payload_ba;
-reg           litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine4_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine4_sink_valid;
-wire          litedramcore_bankmachine4_sink_ready;
-reg           litedramcore_bankmachine4_sink_first = 1'd0;
-reg           litedramcore_bankmachine4_sink_last = 1'd0;
-wire          litedramcore_bankmachine4_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine4_sink_payload_addr;
-wire          litedramcore_bankmachine4_source_valid;
-wire          litedramcore_bankmachine4_source_ready;
-wire          litedramcore_bankmachine4_source_first;
-wire          litedramcore_bankmachine4_source_last;
-wire          litedramcore_bankmachine4_source_payload_we;
-wire   [20:0] litedramcore_bankmachine4_source_payload_addr;
-wire          litedramcore_bankmachine4_syncfifo4_we;
-wire          litedramcore_bankmachine4_syncfifo4_writable;
-wire          litedramcore_bankmachine4_syncfifo4_re;
-wire          litedramcore_bankmachine4_syncfifo4_readable;
-wire   [23:0] litedramcore_bankmachine4_syncfifo4_din;
-wire   [23:0] litedramcore_bankmachine4_syncfifo4_dout;
-reg     [4:0] litedramcore_bankmachine4_level = 5'd0;
-reg           litedramcore_bankmachine4_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine4_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine4_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0;
-wire   [23:0] litedramcore_bankmachine4_wrport_dat_r;
-wire          litedramcore_bankmachine4_wrport_we;
-wire   [23:0] litedramcore_bankmachine4_wrport_dat_w;
-wire          litedramcore_bankmachine4_do_read;
-wire    [3:0] litedramcore_bankmachine4_rdport_adr;
-wire   [23:0] litedramcore_bankmachine4_rdport_dat_r;
-wire          litedramcore_bankmachine4_fifo_in_payload_we;
-wire   [20:0] litedramcore_bankmachine4_fifo_in_payload_addr;
-wire          litedramcore_bankmachine4_fifo_in_first;
-wire          litedramcore_bankmachine4_fifo_in_last;
-wire          litedramcore_bankmachine4_fifo_out_payload_we;
-wire   [20:0] litedramcore_bankmachine4_fifo_out_payload_addr;
-wire          litedramcore_bankmachine4_fifo_out_first;
-wire          litedramcore_bankmachine4_fifo_out_last;
-wire          litedramcore_bankmachine4_sink_sink_valid;
-wire          litedramcore_bankmachine4_sink_sink_ready;
-wire          litedramcore_bankmachine4_sink_sink_first;
-wire          litedramcore_bankmachine4_sink_sink_last;
-wire          litedramcore_bankmachine4_sink_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine4_sink_sink_payload_addr;
-wire          litedramcore_bankmachine4_source_source_valid;
-wire          litedramcore_bankmachine4_source_source_ready;
-wire          litedramcore_bankmachine4_source_source_first;
-wire          litedramcore_bankmachine4_source_source_last;
-wire          litedramcore_bankmachine4_source_source_payload_we;
-wire   [20:0] litedramcore_bankmachine4_source_source_payload_addr;
-wire          litedramcore_bankmachine4_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine4_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine4_pipe_valid_sink_first;
-wire          litedramcore_bankmachine4_pipe_valid_sink_last;
-wire          litedramcore_bankmachine4_pipe_valid_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine4_pipe_valid_source_ready;
-reg           litedramcore_bankmachine4_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine4_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0;
-reg    [20:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 21'd0;
-reg    [13:0] litedramcore_bankmachine4_row = 14'd0;
-reg           litedramcore_bankmachine4_row_opened = 1'd0;
-wire          litedramcore_bankmachine4_row_hit;
-reg           litedramcore_bankmachine4_row_open = 1'd0;
-reg           litedramcore_bankmachine4_row_close = 1'd0;
-reg           litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine4_twtpcon_valid;
+reg           main_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine3_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine3_wrport_adr = 4'd0;
+wire   [23:0] main_litedramcore_bankmachine3_wrport_dat_r;
+wire   [23:0] main_litedramcore_bankmachine3_wrport_dat_w;
+wire          main_litedramcore_bankmachine3_wrport_we;
+reg           main_litedramcore_bankmachine4_auto_precharge = 1'd0;
+reg    [13:0] main_litedramcore_bankmachine4_cmd_payload_a = 14'd0;
+wire    [2:0] main_litedramcore_bankmachine4_cmd_payload_ba;
+reg           main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine4_consume = 4'd0;
+wire          main_litedramcore_bankmachine4_do_read;
+wire          main_litedramcore_bankmachine4_fifo_in_first;
+wire          main_litedramcore_bankmachine4_fifo_in_last;
+wire   [20:0] main_litedramcore_bankmachine4_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine4_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine4_fifo_out_first;
+wire          main_litedramcore_bankmachine4_fifo_out_last;
+wire   [20:0] main_litedramcore_bankmachine4_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine4_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine4_level = 5'd0;
+wire          main_litedramcore_bankmachine4_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine4_pipe_valid_sink_last;
+wire   [20:0] main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine4_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine4_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine4_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine4_pipe_valid_source_last = 1'd0;
+reg    [20:0] main_litedramcore_bankmachine4_pipe_valid_source_payload_addr = 21'd0;
+reg           main_litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine4_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine4_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine4_rdport_adr;
+wire   [23:0] main_litedramcore_bankmachine4_rdport_dat_r;
+reg           main_litedramcore_bankmachine4_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine4_refresh_req;
+reg           main_litedramcore_bankmachine4_replace = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine4_req_addr;
+wire          main_litedramcore_bankmachine4_req_lock;
+reg           main_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine4_req_ready;
+wire          main_litedramcore_bankmachine4_req_valid;
+reg           main_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine4_req_we;
+reg    [13:0] main_litedramcore_bankmachine4_row = 14'd0;
+reg           main_litedramcore_bankmachine4_row_close = 1'd0;
+reg           main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine4_row_hit;
+reg           main_litedramcore_bankmachine4_row_open = 1'd0;
+reg           main_litedramcore_bankmachine4_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine4_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine4_sink_last = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine4_sink_payload_addr;
+wire          main_litedramcore_bankmachine4_sink_payload_we;
+wire          main_litedramcore_bankmachine4_sink_ready;
+wire          main_litedramcore_bankmachine4_sink_sink_first;
+wire          main_litedramcore_bankmachine4_sink_sink_last;
+wire   [20:0] main_litedramcore_bankmachine4_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine4_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine4_sink_sink_ready;
+wire          main_litedramcore_bankmachine4_sink_sink_valid;
+wire          main_litedramcore_bankmachine4_sink_valid;
+wire          main_litedramcore_bankmachine4_source_first;
+wire          main_litedramcore_bankmachine4_source_last;
+wire   [20:0] main_litedramcore_bankmachine4_source_payload_addr;
+wire          main_litedramcore_bankmachine4_source_payload_we;
+wire          main_litedramcore_bankmachine4_source_ready;
+wire          main_litedramcore_bankmachine4_source_source_first;
+wire          main_litedramcore_bankmachine4_source_source_last;
+wire   [20:0] main_litedramcore_bankmachine4_source_source_payload_addr;
+wire          main_litedramcore_bankmachine4_source_source_payload_we;
+wire          main_litedramcore_bankmachine4_source_source_ready;
+wire          main_litedramcore_bankmachine4_source_source_valid;
+wire          main_litedramcore_bankmachine4_source_valid;
+wire   [23:0] main_litedramcore_bankmachine4_syncfifo4_din;
+wire   [23:0] main_litedramcore_bankmachine4_syncfifo4_dout;
+wire          main_litedramcore_bankmachine4_syncfifo4_re;
+wire          main_litedramcore_bankmachine4_syncfifo4_readable;
+wire          main_litedramcore_bankmachine4_syncfifo4_we;
+wire          main_litedramcore_bankmachine4_syncfifo4_writable;
+reg     [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine4_trccon_valid;
+reg           main_litedramcore_bankmachine4_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine4_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
-wire          litedramcore_bankmachine4_trascon_valid;
+reg           main_litedramcore_bankmachine4_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine4_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine4_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
-wire          litedramcore_bankmachine5_req_valid;
-wire          litedramcore_bankmachine5_req_ready;
-wire          litedramcore_bankmachine5_req_we;
-wire   [20:0] litedramcore_bankmachine5_req_addr;
-wire          litedramcore_bankmachine5_req_lock;
-reg           litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine5_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine5_refresh_req;
-reg           litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine5_cmd_ready = 1'd0;
-reg    [13:0] litedramcore_bankmachine5_cmd_payload_a = 14'd0;
-wire    [2:0] litedramcore_bankmachine5_cmd_payload_ba;
-reg           litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine5_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine5_sink_valid;
-wire          litedramcore_bankmachine5_sink_ready;
-reg           litedramcore_bankmachine5_sink_first = 1'd0;
-reg           litedramcore_bankmachine5_sink_last = 1'd0;
-wire          litedramcore_bankmachine5_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine5_sink_payload_addr;
-wire          litedramcore_bankmachine5_source_valid;
-wire          litedramcore_bankmachine5_source_ready;
-wire          litedramcore_bankmachine5_source_first;
-wire          litedramcore_bankmachine5_source_last;
-wire          litedramcore_bankmachine5_source_payload_we;
-wire   [20:0] litedramcore_bankmachine5_source_payload_addr;
-wire          litedramcore_bankmachine5_syncfifo5_we;
-wire          litedramcore_bankmachine5_syncfifo5_writable;
-wire          litedramcore_bankmachine5_syncfifo5_re;
-wire          litedramcore_bankmachine5_syncfifo5_readable;
-wire   [23:0] litedramcore_bankmachine5_syncfifo5_din;
-wire   [23:0] litedramcore_bankmachine5_syncfifo5_dout;
-reg     [4:0] litedramcore_bankmachine5_level = 5'd0;
-reg           litedramcore_bankmachine5_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine5_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine5_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0;
-wire   [23:0] litedramcore_bankmachine5_wrport_dat_r;
-wire          litedramcore_bankmachine5_wrport_we;
-wire   [23:0] litedramcore_bankmachine5_wrport_dat_w;
-wire          litedramcore_bankmachine5_do_read;
-wire    [3:0] litedramcore_bankmachine5_rdport_adr;
-wire   [23:0] litedramcore_bankmachine5_rdport_dat_r;
-wire          litedramcore_bankmachine5_fifo_in_payload_we;
-wire   [20:0] litedramcore_bankmachine5_fifo_in_payload_addr;
-wire          litedramcore_bankmachine5_fifo_in_first;
-wire          litedramcore_bankmachine5_fifo_in_last;
-wire          litedramcore_bankmachine5_fifo_out_payload_we;
-wire   [20:0] litedramcore_bankmachine5_fifo_out_payload_addr;
-wire          litedramcore_bankmachine5_fifo_out_first;
-wire          litedramcore_bankmachine5_fifo_out_last;
-wire          litedramcore_bankmachine5_sink_sink_valid;
-wire          litedramcore_bankmachine5_sink_sink_ready;
-wire          litedramcore_bankmachine5_sink_sink_first;
-wire          litedramcore_bankmachine5_sink_sink_last;
-wire          litedramcore_bankmachine5_sink_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine5_sink_sink_payload_addr;
-wire          litedramcore_bankmachine5_source_source_valid;
-wire          litedramcore_bankmachine5_source_source_ready;
-wire          litedramcore_bankmachine5_source_source_first;
-wire          litedramcore_bankmachine5_source_source_last;
-wire          litedramcore_bankmachine5_source_source_payload_we;
-wire   [20:0] litedramcore_bankmachine5_source_source_payload_addr;
-wire          litedramcore_bankmachine5_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine5_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine5_pipe_valid_sink_first;
-wire          litedramcore_bankmachine5_pipe_valid_sink_last;
-wire          litedramcore_bankmachine5_pipe_valid_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine5_pipe_valid_source_ready;
-reg           litedramcore_bankmachine5_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine5_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0;
-reg    [20:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 21'd0;
-reg    [13:0] litedramcore_bankmachine5_row = 14'd0;
-reg           litedramcore_bankmachine5_row_opened = 1'd0;
-wire          litedramcore_bankmachine5_row_hit;
-reg           litedramcore_bankmachine5_row_open = 1'd0;
-reg           litedramcore_bankmachine5_row_close = 1'd0;
-reg           litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine5_twtpcon_valid;
+reg           main_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine4_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine4_wrport_adr = 4'd0;
+wire   [23:0] main_litedramcore_bankmachine4_wrport_dat_r;
+wire   [23:0] main_litedramcore_bankmachine4_wrport_dat_w;
+wire          main_litedramcore_bankmachine4_wrport_we;
+reg           main_litedramcore_bankmachine5_auto_precharge = 1'd0;
+reg    [13:0] main_litedramcore_bankmachine5_cmd_payload_a = 14'd0;
+wire    [2:0] main_litedramcore_bankmachine5_cmd_payload_ba;
+reg           main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine5_consume = 4'd0;
+wire          main_litedramcore_bankmachine5_do_read;
+wire          main_litedramcore_bankmachine5_fifo_in_first;
+wire          main_litedramcore_bankmachine5_fifo_in_last;
+wire   [20:0] main_litedramcore_bankmachine5_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine5_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine5_fifo_out_first;
+wire          main_litedramcore_bankmachine5_fifo_out_last;
+wire   [20:0] main_litedramcore_bankmachine5_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine5_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine5_level = 5'd0;
+wire          main_litedramcore_bankmachine5_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine5_pipe_valid_sink_last;
+wire   [20:0] main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine5_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine5_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine5_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine5_pipe_valid_source_last = 1'd0;
+reg    [20:0] main_litedramcore_bankmachine5_pipe_valid_source_payload_addr = 21'd0;
+reg           main_litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine5_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine5_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine5_rdport_adr;
+wire   [23:0] main_litedramcore_bankmachine5_rdport_dat_r;
+reg           main_litedramcore_bankmachine5_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine5_refresh_req;
+reg           main_litedramcore_bankmachine5_replace = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine5_req_addr;
+wire          main_litedramcore_bankmachine5_req_lock;
+reg           main_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine5_req_ready;
+wire          main_litedramcore_bankmachine5_req_valid;
+reg           main_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine5_req_we;
+reg    [13:0] main_litedramcore_bankmachine5_row = 14'd0;
+reg           main_litedramcore_bankmachine5_row_close = 1'd0;
+reg           main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine5_row_hit;
+reg           main_litedramcore_bankmachine5_row_open = 1'd0;
+reg           main_litedramcore_bankmachine5_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine5_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine5_sink_last = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine5_sink_payload_addr;
+wire          main_litedramcore_bankmachine5_sink_payload_we;
+wire          main_litedramcore_bankmachine5_sink_ready;
+wire          main_litedramcore_bankmachine5_sink_sink_first;
+wire          main_litedramcore_bankmachine5_sink_sink_last;
+wire   [20:0] main_litedramcore_bankmachine5_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine5_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine5_sink_sink_ready;
+wire          main_litedramcore_bankmachine5_sink_sink_valid;
+wire          main_litedramcore_bankmachine5_sink_valid;
+wire          main_litedramcore_bankmachine5_source_first;
+wire          main_litedramcore_bankmachine5_source_last;
+wire   [20:0] main_litedramcore_bankmachine5_source_payload_addr;
+wire          main_litedramcore_bankmachine5_source_payload_we;
+wire          main_litedramcore_bankmachine5_source_ready;
+wire          main_litedramcore_bankmachine5_source_source_first;
+wire          main_litedramcore_bankmachine5_source_source_last;
+wire   [20:0] main_litedramcore_bankmachine5_source_source_payload_addr;
+wire          main_litedramcore_bankmachine5_source_source_payload_we;
+wire          main_litedramcore_bankmachine5_source_source_ready;
+wire          main_litedramcore_bankmachine5_source_source_valid;
+wire          main_litedramcore_bankmachine5_source_valid;
+wire   [23:0] main_litedramcore_bankmachine5_syncfifo5_din;
+wire   [23:0] main_litedramcore_bankmachine5_syncfifo5_dout;
+wire          main_litedramcore_bankmachine5_syncfifo5_re;
+wire          main_litedramcore_bankmachine5_syncfifo5_readable;
+wire          main_litedramcore_bankmachine5_syncfifo5_we;
+wire          main_litedramcore_bankmachine5_syncfifo5_writable;
+reg     [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine5_trccon_valid;
+reg           main_litedramcore_bankmachine5_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine5_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
-wire          litedramcore_bankmachine5_trascon_valid;
+reg           main_litedramcore_bankmachine5_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine5_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine5_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
-wire          litedramcore_bankmachine6_req_valid;
-wire          litedramcore_bankmachine6_req_ready;
-wire          litedramcore_bankmachine6_req_we;
-wire   [20:0] litedramcore_bankmachine6_req_addr;
-wire          litedramcore_bankmachine6_req_lock;
-reg           litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine6_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine6_refresh_req;
-reg           litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine6_cmd_ready = 1'd0;
-reg    [13:0] litedramcore_bankmachine6_cmd_payload_a = 14'd0;
-wire    [2:0] litedramcore_bankmachine6_cmd_payload_ba;
-reg           litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine6_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine6_sink_valid;
-wire          litedramcore_bankmachine6_sink_ready;
-reg           litedramcore_bankmachine6_sink_first = 1'd0;
-reg           litedramcore_bankmachine6_sink_last = 1'd0;
-wire          litedramcore_bankmachine6_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine6_sink_payload_addr;
-wire          litedramcore_bankmachine6_source_valid;
-wire          litedramcore_bankmachine6_source_ready;
-wire          litedramcore_bankmachine6_source_first;
-wire          litedramcore_bankmachine6_source_last;
-wire          litedramcore_bankmachine6_source_payload_we;
-wire   [20:0] litedramcore_bankmachine6_source_payload_addr;
-wire          litedramcore_bankmachine6_syncfifo6_we;
-wire          litedramcore_bankmachine6_syncfifo6_writable;
-wire          litedramcore_bankmachine6_syncfifo6_re;
-wire          litedramcore_bankmachine6_syncfifo6_readable;
-wire   [23:0] litedramcore_bankmachine6_syncfifo6_din;
-wire   [23:0] litedramcore_bankmachine6_syncfifo6_dout;
-reg     [4:0] litedramcore_bankmachine6_level = 5'd0;
-reg           litedramcore_bankmachine6_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine6_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine6_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0;
-wire   [23:0] litedramcore_bankmachine6_wrport_dat_r;
-wire          litedramcore_bankmachine6_wrport_we;
-wire   [23:0] litedramcore_bankmachine6_wrport_dat_w;
-wire          litedramcore_bankmachine6_do_read;
-wire    [3:0] litedramcore_bankmachine6_rdport_adr;
-wire   [23:0] litedramcore_bankmachine6_rdport_dat_r;
-wire          litedramcore_bankmachine6_fifo_in_payload_we;
-wire   [20:0] litedramcore_bankmachine6_fifo_in_payload_addr;
-wire          litedramcore_bankmachine6_fifo_in_first;
-wire          litedramcore_bankmachine6_fifo_in_last;
-wire          litedramcore_bankmachine6_fifo_out_payload_we;
-wire   [20:0] litedramcore_bankmachine6_fifo_out_payload_addr;
-wire          litedramcore_bankmachine6_fifo_out_first;
-wire          litedramcore_bankmachine6_fifo_out_last;
-wire          litedramcore_bankmachine6_sink_sink_valid;
-wire          litedramcore_bankmachine6_sink_sink_ready;
-wire          litedramcore_bankmachine6_sink_sink_first;
-wire          litedramcore_bankmachine6_sink_sink_last;
-wire          litedramcore_bankmachine6_sink_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine6_sink_sink_payload_addr;
-wire          litedramcore_bankmachine6_source_source_valid;
-wire          litedramcore_bankmachine6_source_source_ready;
-wire          litedramcore_bankmachine6_source_source_first;
-wire          litedramcore_bankmachine6_source_source_last;
-wire          litedramcore_bankmachine6_source_source_payload_we;
-wire   [20:0] litedramcore_bankmachine6_source_source_payload_addr;
-wire          litedramcore_bankmachine6_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine6_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine6_pipe_valid_sink_first;
-wire          litedramcore_bankmachine6_pipe_valid_sink_last;
-wire          litedramcore_bankmachine6_pipe_valid_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine6_pipe_valid_source_ready;
-reg           litedramcore_bankmachine6_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine6_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0;
-reg    [20:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 21'd0;
-reg    [13:0] litedramcore_bankmachine6_row = 14'd0;
-reg           litedramcore_bankmachine6_row_opened = 1'd0;
-wire          litedramcore_bankmachine6_row_hit;
-reg           litedramcore_bankmachine6_row_open = 1'd0;
-reg           litedramcore_bankmachine6_row_close = 1'd0;
-reg           litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine6_twtpcon_valid;
+reg           main_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine5_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine5_wrport_adr = 4'd0;
+wire   [23:0] main_litedramcore_bankmachine5_wrport_dat_r;
+wire   [23:0] main_litedramcore_bankmachine5_wrport_dat_w;
+wire          main_litedramcore_bankmachine5_wrport_we;
+reg           main_litedramcore_bankmachine6_auto_precharge = 1'd0;
+reg    [13:0] main_litedramcore_bankmachine6_cmd_payload_a = 14'd0;
+wire    [2:0] main_litedramcore_bankmachine6_cmd_payload_ba;
+reg           main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine6_consume = 4'd0;
+wire          main_litedramcore_bankmachine6_do_read;
+wire          main_litedramcore_bankmachine6_fifo_in_first;
+wire          main_litedramcore_bankmachine6_fifo_in_last;
+wire   [20:0] main_litedramcore_bankmachine6_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine6_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine6_fifo_out_first;
+wire          main_litedramcore_bankmachine6_fifo_out_last;
+wire   [20:0] main_litedramcore_bankmachine6_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine6_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine6_level = 5'd0;
+wire          main_litedramcore_bankmachine6_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine6_pipe_valid_sink_last;
+wire   [20:0] main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine6_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine6_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine6_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine6_pipe_valid_source_last = 1'd0;
+reg    [20:0] main_litedramcore_bankmachine6_pipe_valid_source_payload_addr = 21'd0;
+reg           main_litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine6_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine6_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine6_rdport_adr;
+wire   [23:0] main_litedramcore_bankmachine6_rdport_dat_r;
+reg           main_litedramcore_bankmachine6_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine6_refresh_req;
+reg           main_litedramcore_bankmachine6_replace = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine6_req_addr;
+wire          main_litedramcore_bankmachine6_req_lock;
+reg           main_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine6_req_ready;
+wire          main_litedramcore_bankmachine6_req_valid;
+reg           main_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine6_req_we;
+reg    [13:0] main_litedramcore_bankmachine6_row = 14'd0;
+reg           main_litedramcore_bankmachine6_row_close = 1'd0;
+reg           main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine6_row_hit;
+reg           main_litedramcore_bankmachine6_row_open = 1'd0;
+reg           main_litedramcore_bankmachine6_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine6_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine6_sink_last = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine6_sink_payload_addr;
+wire          main_litedramcore_bankmachine6_sink_payload_we;
+wire          main_litedramcore_bankmachine6_sink_ready;
+wire          main_litedramcore_bankmachine6_sink_sink_first;
+wire          main_litedramcore_bankmachine6_sink_sink_last;
+wire   [20:0] main_litedramcore_bankmachine6_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine6_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine6_sink_sink_ready;
+wire          main_litedramcore_bankmachine6_sink_sink_valid;
+wire          main_litedramcore_bankmachine6_sink_valid;
+wire          main_litedramcore_bankmachine6_source_first;
+wire          main_litedramcore_bankmachine6_source_last;
+wire   [20:0] main_litedramcore_bankmachine6_source_payload_addr;
+wire          main_litedramcore_bankmachine6_source_payload_we;
+wire          main_litedramcore_bankmachine6_source_ready;
+wire          main_litedramcore_bankmachine6_source_source_first;
+wire          main_litedramcore_bankmachine6_source_source_last;
+wire   [20:0] main_litedramcore_bankmachine6_source_source_payload_addr;
+wire          main_litedramcore_bankmachine6_source_source_payload_we;
+wire          main_litedramcore_bankmachine6_source_source_ready;
+wire          main_litedramcore_bankmachine6_source_source_valid;
+wire          main_litedramcore_bankmachine6_source_valid;
+wire   [23:0] main_litedramcore_bankmachine6_syncfifo6_din;
+wire   [23:0] main_litedramcore_bankmachine6_syncfifo6_dout;
+wire          main_litedramcore_bankmachine6_syncfifo6_re;
+wire          main_litedramcore_bankmachine6_syncfifo6_readable;
+wire          main_litedramcore_bankmachine6_syncfifo6_we;
+wire          main_litedramcore_bankmachine6_syncfifo6_writable;
+reg     [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine6_trccon_valid;
+reg           main_litedramcore_bankmachine6_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine6_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
-wire          litedramcore_bankmachine6_trascon_valid;
+reg           main_litedramcore_bankmachine6_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine6_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine6_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
-wire          litedramcore_bankmachine7_req_valid;
-wire          litedramcore_bankmachine7_req_ready;
-wire          litedramcore_bankmachine7_req_we;
-wire   [20:0] litedramcore_bankmachine7_req_addr;
-wire          litedramcore_bankmachine7_req_lock;
-reg           litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg           litedramcore_bankmachine7_req_rdata_valid = 1'd0;
-wire          litedramcore_bankmachine7_refresh_req;
-reg           litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg           litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg           litedramcore_bankmachine7_cmd_ready = 1'd0;
-reg    [13:0] litedramcore_bankmachine7_cmd_payload_a = 14'd0;
-wire    [2:0] litedramcore_bankmachine7_cmd_payload_ba;
-reg           litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_we = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
-reg           litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg           litedramcore_bankmachine7_auto_precharge = 1'd0;
-wire          litedramcore_bankmachine7_sink_valid;
-wire          litedramcore_bankmachine7_sink_ready;
-reg           litedramcore_bankmachine7_sink_first = 1'd0;
-reg           litedramcore_bankmachine7_sink_last = 1'd0;
-wire          litedramcore_bankmachine7_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine7_sink_payload_addr;
-wire          litedramcore_bankmachine7_source_valid;
-wire          litedramcore_bankmachine7_source_ready;
-wire          litedramcore_bankmachine7_source_first;
-wire          litedramcore_bankmachine7_source_last;
-wire          litedramcore_bankmachine7_source_payload_we;
-wire   [20:0] litedramcore_bankmachine7_source_payload_addr;
-wire          litedramcore_bankmachine7_syncfifo7_we;
-wire          litedramcore_bankmachine7_syncfifo7_writable;
-wire          litedramcore_bankmachine7_syncfifo7_re;
-wire          litedramcore_bankmachine7_syncfifo7_readable;
-wire   [23:0] litedramcore_bankmachine7_syncfifo7_din;
-wire   [23:0] litedramcore_bankmachine7_syncfifo7_dout;
-reg     [4:0] litedramcore_bankmachine7_level = 5'd0;
-reg           litedramcore_bankmachine7_replace = 1'd0;
-reg     [3:0] litedramcore_bankmachine7_produce = 4'd0;
-reg     [3:0] litedramcore_bankmachine7_consume = 4'd0;
-reg     [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0;
-wire   [23:0] litedramcore_bankmachine7_wrport_dat_r;
-wire          litedramcore_bankmachine7_wrport_we;
-wire   [23:0] litedramcore_bankmachine7_wrport_dat_w;
-wire          litedramcore_bankmachine7_do_read;
-wire    [3:0] litedramcore_bankmachine7_rdport_adr;
-wire   [23:0] litedramcore_bankmachine7_rdport_dat_r;
-wire          litedramcore_bankmachine7_fifo_in_payload_we;
-wire   [20:0] litedramcore_bankmachine7_fifo_in_payload_addr;
-wire          litedramcore_bankmachine7_fifo_in_first;
-wire          litedramcore_bankmachine7_fifo_in_last;
-wire          litedramcore_bankmachine7_fifo_out_payload_we;
-wire   [20:0] litedramcore_bankmachine7_fifo_out_payload_addr;
-wire          litedramcore_bankmachine7_fifo_out_first;
-wire          litedramcore_bankmachine7_fifo_out_last;
-wire          litedramcore_bankmachine7_sink_sink_valid;
-wire          litedramcore_bankmachine7_sink_sink_ready;
-wire          litedramcore_bankmachine7_sink_sink_first;
-wire          litedramcore_bankmachine7_sink_sink_last;
-wire          litedramcore_bankmachine7_sink_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine7_sink_sink_payload_addr;
-wire          litedramcore_bankmachine7_source_source_valid;
-wire          litedramcore_bankmachine7_source_source_ready;
-wire          litedramcore_bankmachine7_source_source_first;
-wire          litedramcore_bankmachine7_source_source_last;
-wire          litedramcore_bankmachine7_source_source_payload_we;
-wire   [20:0] litedramcore_bankmachine7_source_source_payload_addr;
-wire          litedramcore_bankmachine7_pipe_valid_sink_valid;
-wire          litedramcore_bankmachine7_pipe_valid_sink_ready;
-wire          litedramcore_bankmachine7_pipe_valid_sink_first;
-wire          litedramcore_bankmachine7_pipe_valid_sink_last;
-wire          litedramcore_bankmachine7_pipe_valid_sink_payload_we;
-wire   [20:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
-reg           litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0;
-wire          litedramcore_bankmachine7_pipe_valid_source_ready;
-reg           litedramcore_bankmachine7_pipe_valid_source_first = 1'd0;
-reg           litedramcore_bankmachine7_pipe_valid_source_last = 1'd0;
-reg           litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0;
-reg    [20:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 21'd0;
-reg    [13:0] litedramcore_bankmachine7_row = 14'd0;
-reg           litedramcore_bankmachine7_row_opened = 1'd0;
-wire          litedramcore_bankmachine7_row_hit;
-reg           litedramcore_bankmachine7_row_open = 1'd0;
-reg           litedramcore_bankmachine7_row_close = 1'd0;
-reg           litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
-wire          litedramcore_bankmachine7_twtpcon_valid;
+reg           main_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine6_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine6_wrport_adr = 4'd0;
+wire   [23:0] main_litedramcore_bankmachine6_wrport_dat_r;
+wire   [23:0] main_litedramcore_bankmachine6_wrport_dat_w;
+wire          main_litedramcore_bankmachine6_wrport_we;
+reg           main_litedramcore_bankmachine7_auto_precharge = 1'd0;
+reg    [13:0] main_litedramcore_bankmachine7_cmd_payload_a = 14'd0;
+wire    [2:0] main_litedramcore_bankmachine7_cmd_payload_ba;
+reg           main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg           main_litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine7_consume = 4'd0;
+wire          main_litedramcore_bankmachine7_do_read;
+wire          main_litedramcore_bankmachine7_fifo_in_first;
+wire          main_litedramcore_bankmachine7_fifo_in_last;
+wire   [20:0] main_litedramcore_bankmachine7_fifo_in_payload_addr;
+wire          main_litedramcore_bankmachine7_fifo_in_payload_we;
+wire          main_litedramcore_bankmachine7_fifo_out_first;
+wire          main_litedramcore_bankmachine7_fifo_out_last;
+wire   [20:0] main_litedramcore_bankmachine7_fifo_out_payload_addr;
+wire          main_litedramcore_bankmachine7_fifo_out_payload_we;
+reg     [4:0] main_litedramcore_bankmachine7_level = 5'd0;
+wire          main_litedramcore_bankmachine7_pipe_valid_sink_first;
+wire          main_litedramcore_bankmachine7_pipe_valid_sink_last;
+wire   [20:0] main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
+wire          main_litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+wire          main_litedramcore_bankmachine7_pipe_valid_sink_ready;
+wire          main_litedramcore_bankmachine7_pipe_valid_sink_valid;
+reg           main_litedramcore_bankmachine7_pipe_valid_source_first = 1'd0;
+reg           main_litedramcore_bankmachine7_pipe_valid_source_last = 1'd0;
+reg    [20:0] main_litedramcore_bankmachine7_pipe_valid_source_payload_addr = 21'd0;
+reg           main_litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0;
+wire          main_litedramcore_bankmachine7_pipe_valid_source_ready;
+reg           main_litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0;
+reg     [3:0] main_litedramcore_bankmachine7_produce = 4'd0;
+wire    [3:0] main_litedramcore_bankmachine7_rdport_adr;
+wire   [23:0] main_litedramcore_bankmachine7_rdport_dat_r;
+reg           main_litedramcore_bankmachine7_refresh_gnt = 1'd0;
+wire          main_litedramcore_bankmachine7_refresh_req;
+reg           main_litedramcore_bankmachine7_replace = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine7_req_addr;
+wire          main_litedramcore_bankmachine7_req_lock;
+reg           main_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire          main_litedramcore_bankmachine7_req_ready;
+wire          main_litedramcore_bankmachine7_req_valid;
+reg           main_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+wire          main_litedramcore_bankmachine7_req_we;
+reg    [13:0] main_litedramcore_bankmachine7_row = 14'd0;
+reg           main_litedramcore_bankmachine7_row_close = 1'd0;
+reg           main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire          main_litedramcore_bankmachine7_row_hit;
+reg           main_litedramcore_bankmachine7_row_open = 1'd0;
+reg           main_litedramcore_bankmachine7_row_opened = 1'd0;
+reg           main_litedramcore_bankmachine7_sink_first = 1'd0;
+reg           main_litedramcore_bankmachine7_sink_last = 1'd0;
+wire   [20:0] main_litedramcore_bankmachine7_sink_payload_addr;
+wire          main_litedramcore_bankmachine7_sink_payload_we;
+wire          main_litedramcore_bankmachine7_sink_ready;
+wire          main_litedramcore_bankmachine7_sink_sink_first;
+wire          main_litedramcore_bankmachine7_sink_sink_last;
+wire   [20:0] main_litedramcore_bankmachine7_sink_sink_payload_addr;
+wire          main_litedramcore_bankmachine7_sink_sink_payload_we;
+wire          main_litedramcore_bankmachine7_sink_sink_ready;
+wire          main_litedramcore_bankmachine7_sink_sink_valid;
+wire          main_litedramcore_bankmachine7_sink_valid;
+wire          main_litedramcore_bankmachine7_source_first;
+wire          main_litedramcore_bankmachine7_source_last;
+wire   [20:0] main_litedramcore_bankmachine7_source_payload_addr;
+wire          main_litedramcore_bankmachine7_source_payload_we;
+wire          main_litedramcore_bankmachine7_source_ready;
+wire          main_litedramcore_bankmachine7_source_source_first;
+wire          main_litedramcore_bankmachine7_source_source_last;
+wire   [20:0] main_litedramcore_bankmachine7_source_source_payload_addr;
+wire          main_litedramcore_bankmachine7_source_source_payload_we;
+wire          main_litedramcore_bankmachine7_source_source_ready;
+wire          main_litedramcore_bankmachine7_source_source_valid;
+wire          main_litedramcore_bankmachine7_source_valid;
+wire   [23:0] main_litedramcore_bankmachine7_syncfifo7_din;
+wire   [23:0] main_litedramcore_bankmachine7_syncfifo7_dout;
+wire          main_litedramcore_bankmachine7_syncfifo7_re;
+wire          main_litedramcore_bankmachine7_syncfifo7_readable;
+wire          main_litedramcore_bankmachine7_syncfifo7_we;
+wire          main_litedramcore_bankmachine7_syncfifo7_writable;
+reg     [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
-wire          litedramcore_bankmachine7_trccon_valid;
+reg           main_litedramcore_bankmachine7_trascon_ready = 1'd0;
+wire          main_litedramcore_bankmachine7_trascon_valid;
+reg     [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
-wire          litedramcore_bankmachine7_trascon_valid;
+reg           main_litedramcore_bankmachine7_trccon_ready = 1'd0;
+wire          main_litedramcore_bankmachine7_trccon_valid;
+reg     [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_bankmachine7_trascon_ready = 1'd0;
-reg     [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
-wire          litedramcore_ras_allowed;
-wire          litedramcore_cas_allowed;
-wire    [1:0] litedramcore_rdcmdphase;
-wire    [1:0] litedramcore_wrcmdphase;
-reg           litedramcore_choose_cmd_want_reads = 1'd0;
-reg           litedramcore_choose_cmd_want_writes = 1'd0;
-reg           litedramcore_choose_cmd_want_cmds = 1'd0;
-reg           litedramcore_choose_cmd_want_activates = 1'd0;
-wire          litedramcore_choose_cmd_cmd_valid;
-reg           litedramcore_choose_cmd_cmd_ready = 1'd0;
-wire   [13:0] litedramcore_choose_cmd_cmd_payload_a;
-wire    [2:0] litedramcore_choose_cmd_cmd_payload_ba;
-reg           litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg           litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg           litedramcore_choose_cmd_cmd_payload_we = 1'd0;
-wire          litedramcore_choose_cmd_cmd_payload_is_cmd;
-wire          litedramcore_choose_cmd_cmd_payload_is_read;
-wire          litedramcore_choose_cmd_cmd_payload_is_write;
-reg     [7:0] litedramcore_choose_cmd_valids = 8'd0;
-wire    [7:0] litedramcore_choose_cmd_request;
-reg     [2:0] litedramcore_choose_cmd_grant = 3'd0;
-wire          litedramcore_choose_cmd_ce;
-reg           litedramcore_choose_req_want_reads = 1'd0;
-reg           litedramcore_choose_req_want_writes = 1'd0;
-reg           litedramcore_choose_req_want_cmds = 1'd0;
-reg           litedramcore_choose_req_want_activates = 1'd0;
-wire          litedramcore_choose_req_cmd_valid;
-reg           litedramcore_choose_req_cmd_ready = 1'd0;
-wire   [13:0] litedramcore_choose_req_cmd_payload_a;
-wire    [2:0] litedramcore_choose_req_cmd_payload_ba;
-reg           litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg           litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg           litedramcore_choose_req_cmd_payload_we = 1'd0;
-wire          litedramcore_choose_req_cmd_payload_is_cmd;
-wire          litedramcore_choose_req_cmd_payload_is_read;
-wire          litedramcore_choose_req_cmd_payload_is_write;
-reg     [7:0] litedramcore_choose_req_valids = 8'd0;
-wire    [7:0] litedramcore_choose_req_request;
-reg     [2:0] litedramcore_choose_req_grant = 3'd0;
-wire          litedramcore_choose_req_ce;
-reg    [13:0] litedramcore_nop_a = 14'd0;
-reg     [2:0] litedramcore_nop_ba = 3'd0;
-reg     [1:0] litedramcore_steerer_sel0 = 2'd0;
-reg     [1:0] litedramcore_steerer_sel1 = 2'd0;
-reg     [1:0] litedramcore_steerer_sel2 = 2'd0;
-reg     [1:0] litedramcore_steerer_sel3 = 2'd0;
-reg           litedramcore_steerer0 = 1'd1;
-reg           litedramcore_steerer1 = 1'd1;
-reg           litedramcore_steerer2 = 1'd1;
-reg           litedramcore_steerer3 = 1'd1;
-reg           litedramcore_steerer4 = 1'd1;
-reg           litedramcore_steerer5 = 1'd1;
-reg           litedramcore_steerer6 = 1'd1;
-reg           litedramcore_steerer7 = 1'd1;
-wire          litedramcore_trrdcon_valid;
+reg           main_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+wire          main_litedramcore_bankmachine7_twtpcon_valid;
+reg     [3:0] main_litedramcore_bankmachine7_wrport_adr = 4'd0;
+wire   [23:0] main_litedramcore_bankmachine7_wrport_dat_r;
+wire   [23:0] main_litedramcore_bankmachine7_wrport_dat_w;
+wire          main_litedramcore_bankmachine7_wrport_we;
+wire          main_litedramcore_cas_allowed;
+wire          main_litedramcore_choose_cmd_ce;
+wire   [13:0] main_litedramcore_choose_cmd_cmd_payload_a;
+wire    [2:0] main_litedramcore_choose_cmd_cmd_payload_ba;
+reg           main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+wire          main_litedramcore_choose_cmd_cmd_payload_is_cmd;
+wire          main_litedramcore_choose_cmd_cmd_payload_is_read;
+wire          main_litedramcore_choose_cmd_cmd_payload_is_write;
+reg           main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+reg           main_litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire          main_litedramcore_choose_cmd_cmd_valid;
+reg     [2:0] main_litedramcore_choose_cmd_grant = 3'd0;
+wire    [7:0] main_litedramcore_choose_cmd_request;
+reg     [7:0] main_litedramcore_choose_cmd_valids = 8'd0;
+reg           main_litedramcore_choose_cmd_want_activates = 1'd0;
+reg           main_litedramcore_choose_cmd_want_cmds = 1'd0;
+reg           main_litedramcore_choose_cmd_want_reads = 1'd0;
+reg           main_litedramcore_choose_cmd_want_writes = 1'd0;
+wire          main_litedramcore_choose_req_ce;
+wire   [13:0] main_litedramcore_choose_req_cmd_payload_a;
+wire    [2:0] main_litedramcore_choose_req_cmd_payload_ba;
+reg           main_litedramcore_choose_req_cmd_payload_cas = 1'd0;
+wire          main_litedramcore_choose_req_cmd_payload_is_cmd;
+wire          main_litedramcore_choose_req_cmd_payload_is_read;
+wire          main_litedramcore_choose_req_cmd_payload_is_write;
+reg           main_litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_choose_req_cmd_payload_we = 1'd0;
+reg           main_litedramcore_choose_req_cmd_ready = 1'd0;
+wire          main_litedramcore_choose_req_cmd_valid;
+reg     [2:0] main_litedramcore_choose_req_grant = 3'd0;
+wire    [7:0] main_litedramcore_choose_req_request;
+reg     [7:0] main_litedramcore_choose_req_valids = 8'd0;
+reg           main_litedramcore_choose_req_want_activates = 1'd0;
+reg           main_litedramcore_choose_req_want_cmds = 1'd0;
+reg           main_litedramcore_choose_req_want_reads = 1'd0;
+reg           main_litedramcore_choose_req_want_writes = 1'd0;
+wire          main_litedramcore_cke;
+reg           main_litedramcore_cmd_last = 1'd0;
+reg    [13:0] main_litedramcore_cmd_payload_a = 14'd0;
+reg     [2:0] main_litedramcore_cmd_payload_ba = 3'd0;
+reg           main_litedramcore_cmd_payload_cas = 1'd0;
+reg           main_litedramcore_cmd_payload_is_read = 1'd0;
+reg           main_litedramcore_cmd_payload_is_write = 1'd0;
+reg           main_litedramcore_cmd_payload_ras = 1'd0;
+reg           main_litedramcore_cmd_payload_we = 1'd0;
+reg           main_litedramcore_cmd_ready = 1'd0;
+reg           main_litedramcore_cmd_valid = 1'd0;
+reg           main_litedramcore_csr_dfi_p0_act_n = 1'd1;
+wire   [13:0] main_litedramcore_csr_dfi_p0_address;
+wire    [2:0] main_litedramcore_csr_dfi_p0_bank;
+reg           main_litedramcore_csr_dfi_p0_cas_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p0_cke = 1'd0;
+reg           main_litedramcore_csr_dfi_p0_cs_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p0_odt = 1'd0;
+reg           main_litedramcore_csr_dfi_p0_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_csr_dfi_p0_rddata = 32'd0;
+wire          main_litedramcore_csr_dfi_p0_rddata_en;
+reg           main_litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
+wire          main_litedramcore_csr_dfi_p0_reset_n;
+reg           main_litedramcore_csr_dfi_p0_we_n = 1'd1;
+wire   [31:0] main_litedramcore_csr_dfi_p0_wrdata;
+wire          main_litedramcore_csr_dfi_p0_wrdata_en;
+wire    [3:0] main_litedramcore_csr_dfi_p0_wrdata_mask;
+reg           main_litedramcore_csr_dfi_p1_act_n = 1'd1;
+wire   [13:0] main_litedramcore_csr_dfi_p1_address;
+wire    [2:0] main_litedramcore_csr_dfi_p1_bank;
+reg           main_litedramcore_csr_dfi_p1_cas_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p1_cke = 1'd0;
+reg           main_litedramcore_csr_dfi_p1_cs_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p1_odt = 1'd0;
+reg           main_litedramcore_csr_dfi_p1_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_csr_dfi_p1_rddata = 32'd0;
+wire          main_litedramcore_csr_dfi_p1_rddata_en;
+reg           main_litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
+wire          main_litedramcore_csr_dfi_p1_reset_n;
+reg           main_litedramcore_csr_dfi_p1_we_n = 1'd1;
+wire   [31:0] main_litedramcore_csr_dfi_p1_wrdata;
+wire          main_litedramcore_csr_dfi_p1_wrdata_en;
+wire    [3:0] main_litedramcore_csr_dfi_p1_wrdata_mask;
+reg           main_litedramcore_csr_dfi_p2_act_n = 1'd1;
+wire   [13:0] main_litedramcore_csr_dfi_p2_address;
+wire    [2:0] main_litedramcore_csr_dfi_p2_bank;
+reg           main_litedramcore_csr_dfi_p2_cas_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p2_cke = 1'd0;
+reg           main_litedramcore_csr_dfi_p2_cs_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p2_odt = 1'd0;
+reg           main_litedramcore_csr_dfi_p2_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_csr_dfi_p2_rddata = 32'd0;
+wire          main_litedramcore_csr_dfi_p2_rddata_en;
+reg           main_litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
+wire          main_litedramcore_csr_dfi_p2_reset_n;
+reg           main_litedramcore_csr_dfi_p2_we_n = 1'd1;
+wire   [31:0] main_litedramcore_csr_dfi_p2_wrdata;
+wire          main_litedramcore_csr_dfi_p2_wrdata_en;
+wire    [3:0] main_litedramcore_csr_dfi_p2_wrdata_mask;
+reg           main_litedramcore_csr_dfi_p3_act_n = 1'd1;
+wire   [13:0] main_litedramcore_csr_dfi_p3_address;
+wire    [2:0] main_litedramcore_csr_dfi_p3_bank;
+reg           main_litedramcore_csr_dfi_p3_cas_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p3_cke = 1'd0;
+reg           main_litedramcore_csr_dfi_p3_cs_n = 1'd1;
+reg           main_litedramcore_csr_dfi_p3_odt = 1'd0;
+reg           main_litedramcore_csr_dfi_p3_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_csr_dfi_p3_rddata = 32'd0;
+wire          main_litedramcore_csr_dfi_p3_rddata_en;
+reg           main_litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
+wire          main_litedramcore_csr_dfi_p3_reset_n;
+reg           main_litedramcore_csr_dfi_p3_we_n = 1'd1;
+wire   [31:0] main_litedramcore_csr_dfi_p3_wrdata;
+wire          main_litedramcore_csr_dfi_p3_wrdata_en;
+wire    [3:0] main_litedramcore_csr_dfi_p3_wrdata_mask;
+reg           main_litedramcore_dfi_p0_act_n = 1'd1;
+reg    [13:0] main_litedramcore_dfi_p0_address = 14'd0;
+reg     [2:0] main_litedramcore_dfi_p0_bank = 3'd0;
+reg           main_litedramcore_dfi_p0_cas_n = 1'd1;
+wire          main_litedramcore_dfi_p0_cke;
+reg           main_litedramcore_dfi_p0_cs_n = 1'd1;
+wire          main_litedramcore_dfi_p0_odt;
+reg           main_litedramcore_dfi_p0_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p0_rddata;
+reg           main_litedramcore_dfi_p0_rddata_en = 1'd0;
+wire          main_litedramcore_dfi_p0_rddata_valid;
+wire          main_litedramcore_dfi_p0_reset_n;
+reg           main_litedramcore_dfi_p0_we_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p0_wrdata;
+reg           main_litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire    [3:0] main_litedramcore_dfi_p0_wrdata_mask;
+reg           main_litedramcore_dfi_p1_act_n = 1'd1;
+reg    [13:0] main_litedramcore_dfi_p1_address = 14'd0;
+reg     [2:0] main_litedramcore_dfi_p1_bank = 3'd0;
+reg           main_litedramcore_dfi_p1_cas_n = 1'd1;
+wire          main_litedramcore_dfi_p1_cke;
+reg           main_litedramcore_dfi_p1_cs_n = 1'd1;
+wire          main_litedramcore_dfi_p1_odt;
+reg           main_litedramcore_dfi_p1_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p1_rddata;
+reg           main_litedramcore_dfi_p1_rddata_en = 1'd0;
+wire          main_litedramcore_dfi_p1_rddata_valid;
+wire          main_litedramcore_dfi_p1_reset_n;
+reg           main_litedramcore_dfi_p1_we_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p1_wrdata;
+reg           main_litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire    [3:0] main_litedramcore_dfi_p1_wrdata_mask;
+reg           main_litedramcore_dfi_p2_act_n = 1'd1;
+reg    [13:0] main_litedramcore_dfi_p2_address = 14'd0;
+reg     [2:0] main_litedramcore_dfi_p2_bank = 3'd0;
+reg           main_litedramcore_dfi_p2_cas_n = 1'd1;
+wire          main_litedramcore_dfi_p2_cke;
+reg           main_litedramcore_dfi_p2_cs_n = 1'd1;
+wire          main_litedramcore_dfi_p2_odt;
+reg           main_litedramcore_dfi_p2_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p2_rddata;
+reg           main_litedramcore_dfi_p2_rddata_en = 1'd0;
+wire          main_litedramcore_dfi_p2_rddata_valid;
+wire          main_litedramcore_dfi_p2_reset_n;
+reg           main_litedramcore_dfi_p2_we_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p2_wrdata;
+reg           main_litedramcore_dfi_p2_wrdata_en = 1'd0;
+wire    [3:0] main_litedramcore_dfi_p2_wrdata_mask;
+reg           main_litedramcore_dfi_p3_act_n = 1'd1;
+reg    [13:0] main_litedramcore_dfi_p3_address = 14'd0;
+reg     [2:0] main_litedramcore_dfi_p3_bank = 3'd0;
+reg           main_litedramcore_dfi_p3_cas_n = 1'd1;
+wire          main_litedramcore_dfi_p3_cke;
+reg           main_litedramcore_dfi_p3_cs_n = 1'd1;
+wire          main_litedramcore_dfi_p3_odt;
+reg           main_litedramcore_dfi_p3_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p3_rddata;
+reg           main_litedramcore_dfi_p3_rddata_en = 1'd0;
+wire          main_litedramcore_dfi_p3_rddata_valid;
+wire          main_litedramcore_dfi_p3_reset_n;
+reg           main_litedramcore_dfi_p3_we_n = 1'd1;
+wire   [31:0] main_litedramcore_dfi_p3_wrdata;
+reg           main_litedramcore_dfi_p3_wrdata_en = 1'd0;
+wire    [3:0] main_litedramcore_dfi_p3_wrdata_mask;
+reg           main_litedramcore_en0 = 1'd0;
+reg           main_litedramcore_en1 = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_act_n = 1'd1;
+reg    [13:0] main_litedramcore_ext_dfi_p0_address = 14'd0;
+reg     [2:0] main_litedramcore_ext_dfi_p0_bank = 3'd0;
+reg           main_litedramcore_ext_dfi_p0_cas_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p0_cke = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_cs_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p0_odt = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p0_rddata = 32'd0;
+reg           main_litedramcore_ext_dfi_p0_rddata_en = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_reset_n = 1'd0;
+reg           main_litedramcore_ext_dfi_p0_we_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p0_wrdata = 32'd0;
+reg           main_litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
+reg           main_litedramcore_ext_dfi_p1_act_n = 1'd1;
+reg    [13:0] main_litedramcore_ext_dfi_p1_address = 14'd0;
+reg     [2:0] main_litedramcore_ext_dfi_p1_bank = 3'd0;
+reg           main_litedramcore_ext_dfi_p1_cas_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p1_cke = 1'd0;
+reg           main_litedramcore_ext_dfi_p1_cs_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p1_odt = 1'd0;
+reg           main_litedramcore_ext_dfi_p1_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p1_rddata = 32'd0;
+reg           main_litedramcore_ext_dfi_p1_rddata_en = 1'd0;
+reg           main_litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
+reg           main_litedramcore_ext_dfi_p1_reset_n = 1'd0;
+reg           main_litedramcore_ext_dfi_p1_we_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p1_wrdata = 32'd0;
+reg           main_litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
+reg           main_litedramcore_ext_dfi_p2_act_n = 1'd1;
+reg    [13:0] main_litedramcore_ext_dfi_p2_address = 14'd0;
+reg     [2:0] main_litedramcore_ext_dfi_p2_bank = 3'd0;
+reg           main_litedramcore_ext_dfi_p2_cas_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p2_cke = 1'd0;
+reg           main_litedramcore_ext_dfi_p2_cs_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p2_odt = 1'd0;
+reg           main_litedramcore_ext_dfi_p2_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p2_rddata = 32'd0;
+reg           main_litedramcore_ext_dfi_p2_rddata_en = 1'd0;
+reg           main_litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
+reg           main_litedramcore_ext_dfi_p2_reset_n = 1'd0;
+reg           main_litedramcore_ext_dfi_p2_we_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p2_wrdata = 32'd0;
+reg           main_litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
+reg           main_litedramcore_ext_dfi_p3_act_n = 1'd1;
+reg    [13:0] main_litedramcore_ext_dfi_p3_address = 14'd0;
+reg     [2:0] main_litedramcore_ext_dfi_p3_bank = 3'd0;
+reg           main_litedramcore_ext_dfi_p3_cas_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p3_cke = 1'd0;
+reg           main_litedramcore_ext_dfi_p3_cs_n = 1'd1;
+reg           main_litedramcore_ext_dfi_p3_odt = 1'd0;
+reg           main_litedramcore_ext_dfi_p3_ras_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p3_rddata = 32'd0;
+reg           main_litedramcore_ext_dfi_p3_rddata_en = 1'd0;
+reg           main_litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
+reg           main_litedramcore_ext_dfi_p3_reset_n = 1'd0;
+reg           main_litedramcore_ext_dfi_p3_we_n = 1'd1;
+reg    [31:0] main_litedramcore_ext_dfi_p3_wrdata = 32'd0;
+reg           main_litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
+reg           main_litedramcore_ext_dfi_sel = 1'd0;
+wire          main_litedramcore_go_to_refresh;
+wire   [20:0] main_litedramcore_interface_bank0_addr;
+wire          main_litedramcore_interface_bank0_lock;
+wire          main_litedramcore_interface_bank0_rdata_valid;
+wire          main_litedramcore_interface_bank0_ready;
+wire          main_litedramcore_interface_bank0_valid;
+wire          main_litedramcore_interface_bank0_wdata_ready;
+wire          main_litedramcore_interface_bank0_we;
+wire   [20:0] main_litedramcore_interface_bank1_addr;
+wire          main_litedramcore_interface_bank1_lock;
+wire          main_litedramcore_interface_bank1_rdata_valid;
+wire          main_litedramcore_interface_bank1_ready;
+wire          main_litedramcore_interface_bank1_valid;
+wire          main_litedramcore_interface_bank1_wdata_ready;
+wire          main_litedramcore_interface_bank1_we;
+wire   [20:0] main_litedramcore_interface_bank2_addr;
+wire          main_litedramcore_interface_bank2_lock;
+wire          main_litedramcore_interface_bank2_rdata_valid;
+wire          main_litedramcore_interface_bank2_ready;
+wire          main_litedramcore_interface_bank2_valid;
+wire          main_litedramcore_interface_bank2_wdata_ready;
+wire          main_litedramcore_interface_bank2_we;
+wire   [20:0] main_litedramcore_interface_bank3_addr;
+wire          main_litedramcore_interface_bank3_lock;
+wire          main_litedramcore_interface_bank3_rdata_valid;
+wire          main_litedramcore_interface_bank3_ready;
+wire          main_litedramcore_interface_bank3_valid;
+wire          main_litedramcore_interface_bank3_wdata_ready;
+wire          main_litedramcore_interface_bank3_we;
+wire   [20:0] main_litedramcore_interface_bank4_addr;
+wire          main_litedramcore_interface_bank4_lock;
+wire          main_litedramcore_interface_bank4_rdata_valid;
+wire          main_litedramcore_interface_bank4_ready;
+wire          main_litedramcore_interface_bank4_valid;
+wire          main_litedramcore_interface_bank4_wdata_ready;
+wire          main_litedramcore_interface_bank4_we;
+wire   [20:0] main_litedramcore_interface_bank5_addr;
+wire          main_litedramcore_interface_bank5_lock;
+wire          main_litedramcore_interface_bank5_rdata_valid;
+wire          main_litedramcore_interface_bank5_ready;
+wire          main_litedramcore_interface_bank5_valid;
+wire          main_litedramcore_interface_bank5_wdata_ready;
+wire          main_litedramcore_interface_bank5_we;
+wire   [20:0] main_litedramcore_interface_bank6_addr;
+wire          main_litedramcore_interface_bank6_lock;
+wire          main_litedramcore_interface_bank6_rdata_valid;
+wire          main_litedramcore_interface_bank6_ready;
+wire          main_litedramcore_interface_bank6_valid;
+wire          main_litedramcore_interface_bank6_wdata_ready;
+wire          main_litedramcore_interface_bank6_we;
+wire   [20:0] main_litedramcore_interface_bank7_addr;
+wire          main_litedramcore_interface_bank7_lock;
+wire          main_litedramcore_interface_bank7_rdata_valid;
+wire          main_litedramcore_interface_bank7_ready;
+wire          main_litedramcore_interface_bank7_valid;
+wire          main_litedramcore_interface_bank7_wdata_ready;
+wire          main_litedramcore_interface_bank7_we;
+wire  [127:0] main_litedramcore_interface_rdata;
+reg   [127:0] main_litedramcore_interface_wdata = 128'd0;
+reg    [15:0] main_litedramcore_interface_wdata_we = 16'd0;
+reg           main_litedramcore_master_p0_act_n = 1'd1;
+reg    [13:0] main_litedramcore_master_p0_address = 14'd0;
+reg     [2:0] main_litedramcore_master_p0_bank = 3'd0;
+reg           main_litedramcore_master_p0_cas_n = 1'd1;
+reg           main_litedramcore_master_p0_cke = 1'd0;
+reg           main_litedramcore_master_p0_cs_n = 1'd1;
+reg           main_litedramcore_master_p0_odt = 1'd0;
+reg           main_litedramcore_master_p0_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_master_p0_rddata;
+reg           main_litedramcore_master_p0_rddata_en = 1'd0;
+wire          main_litedramcore_master_p0_rddata_valid;
+reg           main_litedramcore_master_p0_reset_n = 1'd0;
+reg           main_litedramcore_master_p0_we_n = 1'd1;
+reg    [31:0] main_litedramcore_master_p0_wrdata = 32'd0;
+reg           main_litedramcore_master_p0_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0;
+reg           main_litedramcore_master_p1_act_n = 1'd1;
+reg    [13:0] main_litedramcore_master_p1_address = 14'd0;
+reg     [2:0] main_litedramcore_master_p1_bank = 3'd0;
+reg           main_litedramcore_master_p1_cas_n = 1'd1;
+reg           main_litedramcore_master_p1_cke = 1'd0;
+reg           main_litedramcore_master_p1_cs_n = 1'd1;
+reg           main_litedramcore_master_p1_odt = 1'd0;
+reg           main_litedramcore_master_p1_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_master_p1_rddata;
+reg           main_litedramcore_master_p1_rddata_en = 1'd0;
+wire          main_litedramcore_master_p1_rddata_valid;
+reg           main_litedramcore_master_p1_reset_n = 1'd0;
+reg           main_litedramcore_master_p1_we_n = 1'd1;
+reg    [31:0] main_litedramcore_master_p1_wrdata = 32'd0;
+reg           main_litedramcore_master_p1_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0;
+reg           main_litedramcore_master_p2_act_n = 1'd1;
+reg    [13:0] main_litedramcore_master_p2_address = 14'd0;
+reg     [2:0] main_litedramcore_master_p2_bank = 3'd0;
+reg           main_litedramcore_master_p2_cas_n = 1'd1;
+reg           main_litedramcore_master_p2_cke = 1'd0;
+reg           main_litedramcore_master_p2_cs_n = 1'd1;
+reg           main_litedramcore_master_p2_odt = 1'd0;
+reg           main_litedramcore_master_p2_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_master_p2_rddata;
+reg           main_litedramcore_master_p2_rddata_en = 1'd0;
+wire          main_litedramcore_master_p2_rddata_valid;
+reg           main_litedramcore_master_p2_reset_n = 1'd0;
+reg           main_litedramcore_master_p2_we_n = 1'd1;
+reg    [31:0] main_litedramcore_master_p2_wrdata = 32'd0;
+reg           main_litedramcore_master_p2_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0;
+reg           main_litedramcore_master_p3_act_n = 1'd1;
+reg    [13:0] main_litedramcore_master_p3_address = 14'd0;
+reg     [2:0] main_litedramcore_master_p3_bank = 3'd0;
+reg           main_litedramcore_master_p3_cas_n = 1'd1;
+reg           main_litedramcore_master_p3_cke = 1'd0;
+reg           main_litedramcore_master_p3_cs_n = 1'd1;
+reg           main_litedramcore_master_p3_odt = 1'd0;
+reg           main_litedramcore_master_p3_ras_n = 1'd1;
+wire   [31:0] main_litedramcore_master_p3_rddata;
+reg           main_litedramcore_master_p3_rddata_en = 1'd0;
+wire          main_litedramcore_master_p3_rddata_valid;
+reg           main_litedramcore_master_p3_reset_n = 1'd0;
+reg           main_litedramcore_master_p3_we_n = 1'd1;
+reg    [31:0] main_litedramcore_master_p3_wrdata = 32'd0;
+reg           main_litedramcore_master_p3_wrdata_en = 1'd0;
+reg     [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0;
+wire          main_litedramcore_max_time0;
+wire          main_litedramcore_max_time1;
+reg    [13:0] main_litedramcore_nop_a = 14'd0;
+reg     [2:0] main_litedramcore_nop_ba = 3'd0;
+wire    [1:0] main_litedramcore_nphases;
+wire          main_litedramcore_odt;
+reg           main_litedramcore_phaseinjector0_address_re = 1'd0;
+reg    [13:0] main_litedramcore_phaseinjector0_address_storage = 14'd0;
+reg           main_litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg     [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0;
+wire          main_litedramcore_phaseinjector0_command_issue_r;
+reg           main_litedramcore_phaseinjector0_command_issue_re = 1'd0;
+reg           main_litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg           main_litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg           main_litedramcore_phaseinjector0_command_re = 1'd0;
+reg     [7:0] main_litedramcore_phaseinjector0_command_storage = 8'd0;
+wire          main_litedramcore_phaseinjector0_csrfield_cas;
+wire          main_litedramcore_phaseinjector0_csrfield_cs;
+wire          main_litedramcore_phaseinjector0_csrfield_cs_bottom;
+wire          main_litedramcore_phaseinjector0_csrfield_cs_top;
+wire          main_litedramcore_phaseinjector0_csrfield_ras;
+wire          main_litedramcore_phaseinjector0_csrfield_rden;
+wire          main_litedramcore_phaseinjector0_csrfield_we;
+wire          main_litedramcore_phaseinjector0_csrfield_wren;
+reg           main_litedramcore_phaseinjector0_rddata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0;
+wire          main_litedramcore_phaseinjector0_rddata_we;
+reg           main_litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
+reg           main_litedramcore_phaseinjector1_address_re = 1'd0;
+reg    [13:0] main_litedramcore_phaseinjector1_address_storage = 14'd0;
+reg           main_litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg     [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0;
+wire          main_litedramcore_phaseinjector1_command_issue_r;
+reg           main_litedramcore_phaseinjector1_command_issue_re = 1'd0;
+reg           main_litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg           main_litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg           main_litedramcore_phaseinjector1_command_re = 1'd0;
+reg     [7:0] main_litedramcore_phaseinjector1_command_storage = 8'd0;
+wire          main_litedramcore_phaseinjector1_csrfield_cas;
+wire          main_litedramcore_phaseinjector1_csrfield_cs;
+wire          main_litedramcore_phaseinjector1_csrfield_cs_bottom;
+wire          main_litedramcore_phaseinjector1_csrfield_cs_top;
+wire          main_litedramcore_phaseinjector1_csrfield_ras;
+wire          main_litedramcore_phaseinjector1_csrfield_rden;
+wire          main_litedramcore_phaseinjector1_csrfield_we;
+wire          main_litedramcore_phaseinjector1_csrfield_wren;
+reg           main_litedramcore_phaseinjector1_rddata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0;
+wire          main_litedramcore_phaseinjector1_rddata_we;
+reg           main_litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
+reg           main_litedramcore_phaseinjector2_address_re = 1'd0;
+reg    [13:0] main_litedramcore_phaseinjector2_address_storage = 14'd0;
+reg           main_litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg     [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0;
+wire          main_litedramcore_phaseinjector2_command_issue_r;
+reg           main_litedramcore_phaseinjector2_command_issue_re = 1'd0;
+reg           main_litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg           main_litedramcore_phaseinjector2_command_issue_we = 1'd0;
+reg           main_litedramcore_phaseinjector2_command_re = 1'd0;
+reg     [7:0] main_litedramcore_phaseinjector2_command_storage = 8'd0;
+wire          main_litedramcore_phaseinjector2_csrfield_cas;
+wire          main_litedramcore_phaseinjector2_csrfield_cs;
+wire          main_litedramcore_phaseinjector2_csrfield_cs_bottom;
+wire          main_litedramcore_phaseinjector2_csrfield_cs_top;
+wire          main_litedramcore_phaseinjector2_csrfield_ras;
+wire          main_litedramcore_phaseinjector2_csrfield_rden;
+wire          main_litedramcore_phaseinjector2_csrfield_we;
+wire          main_litedramcore_phaseinjector2_csrfield_wren;
+reg           main_litedramcore_phaseinjector2_rddata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0;
+wire          main_litedramcore_phaseinjector2_rddata_we;
+reg           main_litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
+reg           main_litedramcore_phaseinjector3_address_re = 1'd0;
+reg    [13:0] main_litedramcore_phaseinjector3_address_storage = 14'd0;
+reg           main_litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg     [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0;
+wire          main_litedramcore_phaseinjector3_command_issue_r;
+reg           main_litedramcore_phaseinjector3_command_issue_re = 1'd0;
+reg           main_litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg           main_litedramcore_phaseinjector3_command_issue_we = 1'd0;
+reg           main_litedramcore_phaseinjector3_command_re = 1'd0;
+reg     [7:0] main_litedramcore_phaseinjector3_command_storage = 8'd0;
+wire          main_litedramcore_phaseinjector3_csrfield_cas;
+wire          main_litedramcore_phaseinjector3_csrfield_cs;
+wire          main_litedramcore_phaseinjector3_csrfield_cs_bottom;
+wire          main_litedramcore_phaseinjector3_csrfield_cs_top;
+wire          main_litedramcore_phaseinjector3_csrfield_ras;
+wire          main_litedramcore_phaseinjector3_csrfield_rden;
+wire          main_litedramcore_phaseinjector3_csrfield_we;
+wire          main_litedramcore_phaseinjector3_csrfield_wren;
+reg           main_litedramcore_phaseinjector3_rddata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0;
+wire          main_litedramcore_phaseinjector3_rddata_we;
+reg           main_litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg    [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
+reg           main_litedramcore_postponer_count = 1'd0;
+wire          main_litedramcore_postponer_req_i;
+reg           main_litedramcore_postponer_req_o = 1'd0;
+wire          main_litedramcore_ras_allowed;
+wire    [1:0] main_litedramcore_rdphase;
+reg           main_litedramcore_re = 1'd0;
+wire          main_litedramcore_read_available;
+wire          main_litedramcore_reset_n;
+wire          main_litedramcore_sel;
+reg           main_litedramcore_sequencer_count = 1'd0;
+wire          main_litedramcore_sequencer_done0;
+reg           main_litedramcore_sequencer_done1 = 1'd0;
+reg           main_litedramcore_sequencer_start0 = 1'd0;
+wire          main_litedramcore_sequencer_start1;
+reg     [5:0] main_litedramcore_sequencer_trigger = 6'd0;
+wire          main_litedramcore_slave_p0_act_n;
+wire   [13:0] main_litedramcore_slave_p0_address;
+wire    [2:0] main_litedramcore_slave_p0_bank;
+wire          main_litedramcore_slave_p0_cas_n;
+wire          main_litedramcore_slave_p0_cke;
+wire          main_litedramcore_slave_p0_cs_n;
+wire          main_litedramcore_slave_p0_odt;
+wire          main_litedramcore_slave_p0_ras_n;
+reg    [31:0] main_litedramcore_slave_p0_rddata = 32'd0;
+wire          main_litedramcore_slave_p0_rddata_en;
+reg           main_litedramcore_slave_p0_rddata_valid = 1'd0;
+wire          main_litedramcore_slave_p0_reset_n;
+wire          main_litedramcore_slave_p0_we_n;
+wire   [31:0] main_litedramcore_slave_p0_wrdata;
+wire          main_litedramcore_slave_p0_wrdata_en;
+wire    [3:0] main_litedramcore_slave_p0_wrdata_mask;
+wire          main_litedramcore_slave_p1_act_n;
+wire   [13:0] main_litedramcore_slave_p1_address;
+wire    [2:0] main_litedramcore_slave_p1_bank;
+wire          main_litedramcore_slave_p1_cas_n;
+wire          main_litedramcore_slave_p1_cke;
+wire          main_litedramcore_slave_p1_cs_n;
+wire          main_litedramcore_slave_p1_odt;
+wire          main_litedramcore_slave_p1_ras_n;
+reg    [31:0] main_litedramcore_slave_p1_rddata = 32'd0;
+wire          main_litedramcore_slave_p1_rddata_en;
+reg           main_litedramcore_slave_p1_rddata_valid = 1'd0;
+wire          main_litedramcore_slave_p1_reset_n;
+wire          main_litedramcore_slave_p1_we_n;
+wire   [31:0] main_litedramcore_slave_p1_wrdata;
+wire          main_litedramcore_slave_p1_wrdata_en;
+wire    [3:0] main_litedramcore_slave_p1_wrdata_mask;
+wire          main_litedramcore_slave_p2_act_n;
+wire   [13:0] main_litedramcore_slave_p2_address;
+wire    [2:0] main_litedramcore_slave_p2_bank;
+wire          main_litedramcore_slave_p2_cas_n;
+wire          main_litedramcore_slave_p2_cke;
+wire          main_litedramcore_slave_p2_cs_n;
+wire          main_litedramcore_slave_p2_odt;
+wire          main_litedramcore_slave_p2_ras_n;
+reg    [31:0] main_litedramcore_slave_p2_rddata = 32'd0;
+wire          main_litedramcore_slave_p2_rddata_en;
+reg           main_litedramcore_slave_p2_rddata_valid = 1'd0;
+wire          main_litedramcore_slave_p2_reset_n;
+wire          main_litedramcore_slave_p2_we_n;
+wire   [31:0] main_litedramcore_slave_p2_wrdata;
+wire          main_litedramcore_slave_p2_wrdata_en;
+wire    [3:0] main_litedramcore_slave_p2_wrdata_mask;
+wire          main_litedramcore_slave_p3_act_n;
+wire   [13:0] main_litedramcore_slave_p3_address;
+wire    [2:0] main_litedramcore_slave_p3_bank;
+wire          main_litedramcore_slave_p3_cas_n;
+wire          main_litedramcore_slave_p3_cke;
+wire          main_litedramcore_slave_p3_cs_n;
+wire          main_litedramcore_slave_p3_odt;
+wire          main_litedramcore_slave_p3_ras_n;
+reg    [31:0] main_litedramcore_slave_p3_rddata = 32'd0;
+wire          main_litedramcore_slave_p3_rddata_en;
+reg           main_litedramcore_slave_p3_rddata_valid = 1'd0;
+wire          main_litedramcore_slave_p3_reset_n;
+wire          main_litedramcore_slave_p3_we_n;
+wire   [31:0] main_litedramcore_slave_p3_wrdata;
+wire          main_litedramcore_slave_p3_wrdata_en;
+wire    [3:0] main_litedramcore_slave_p3_wrdata_mask;
+reg     [1:0] main_litedramcore_steerer0 = 2'd0;
+reg     [1:0] main_litedramcore_steerer1 = 2'd0;
+reg           main_litedramcore_steerer10 = 1'd1;
+reg           main_litedramcore_steerer11 = 1'd1;
+reg     [1:0] main_litedramcore_steerer2 = 2'd0;
+reg     [1:0] main_litedramcore_steerer3 = 2'd0;
+reg           main_litedramcore_steerer4 = 1'd1;
+reg           main_litedramcore_steerer5 = 1'd1;
+reg           main_litedramcore_steerer6 = 1'd1;
+reg           main_litedramcore_steerer7 = 1'd1;
+reg           main_litedramcore_steerer8 = 1'd1;
+reg           main_litedramcore_steerer9 = 1'd1;
+reg     [3:0] main_litedramcore_storage = 4'd1;
+reg           main_litedramcore_tccdcon_count = 1'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_trrdcon_ready = 1'd0;
-reg           litedramcore_trrdcon_count = 1'd0;
-wire          litedramcore_tfawcon_valid;
+reg           main_litedramcore_tccdcon_ready = 1'd0;
+wire          main_litedramcore_tccdcon_valid;
+wire    [2:0] main_litedramcore_tfawcon_count;
 (* dont_touch = "true" *)
-reg           litedramcore_tfawcon_ready = 1'd1;
-wire    [2:0] litedramcore_tfawcon_count;
-reg     [4:0] litedramcore_tfawcon_window = 5'd0;
-wire          litedramcore_tccdcon_valid;
+reg           main_litedramcore_tfawcon_ready = 1'd1;
+wire          main_litedramcore_tfawcon_valid;
+reg     [4:0] main_litedramcore_tfawcon_window = 5'd0;
+reg     [4:0] main_litedramcore_time0 = 5'd0;
+reg     [3:0] main_litedramcore_time1 = 4'd0;
+wire    [9:0] main_litedramcore_timer_count0;
+reg     [9:0] main_litedramcore_timer_count1 = 10'd781;
+wire          main_litedramcore_timer_done0;
+wire          main_litedramcore_timer_done1;
+wire          main_litedramcore_timer_wait;
+reg           main_litedramcore_trrdcon_count = 1'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_tccdcon_ready = 1'd0;
-reg           litedramcore_tccdcon_count = 1'd0;
-wire          litedramcore_twtrcon_valid;
+reg           main_litedramcore_trrdcon_ready = 1'd0;
+wire          main_litedramcore_trrdcon_valid;
+reg     [2:0] main_litedramcore_twtrcon_count = 3'd0;
 (* dont_touch = "true" *)
-reg           litedramcore_twtrcon_ready = 1'd0;
-reg     [2:0] litedramcore_twtrcon_count = 3'd0;
-wire          litedramcore_read_available;
-wire          litedramcore_write_available;
-reg           litedramcore_en0 = 1'd0;
-wire          litedramcore_max_time0;
-reg     [4:0] litedramcore_time0 = 5'd0;
-reg           litedramcore_en1 = 1'd0;
-wire          litedramcore_max_time1;
-reg     [3:0] litedramcore_time1 = 4'd0;
-wire          litedramcore_go_to_refresh;
-reg           init_done_storage = 1'd0;
-reg           init_done_re = 1'd0;
-reg           init_error_storage = 1'd0;
-reg           init_error_re = 1'd0;
-wire   [29:0] wb_bus_adr;
-wire   [31:0] wb_bus_dat_w;
-wire   [31:0] wb_bus_dat_r;
-wire    [3:0] wb_bus_sel;
-wire          wb_bus_cyc;
-wire          wb_bus_stb;
-wire          wb_bus_ack;
-wire          wb_bus_we;
-wire    [2:0] wb_bus_cti;
-wire    [1:0] wb_bus_bte;
-wire          wb_bus_err;
-wire          user_enable;
-wire          user_port_cmd_valid;
-wire          user_port_cmd_ready;
-wire          user_port_cmd_payload_we;
-wire   [23:0] user_port_cmd_payload_addr;
-wire          user_port_wdata_valid;
-wire          user_port_wdata_ready;
-wire  [127:0] user_port_wdata_payload_data;
-wire   [15:0] user_port_wdata_payload_we;
-wire          user_port_rdata_valid;
-wire          user_port_rdata_ready;
-wire  [127:0] user_port_rdata_payload_data;
-reg    [13:0] litedramcore_adr = 14'd0;
-reg           litedramcore_we = 1'd0;
-reg    [31:0] litedramcore_dat_w = 32'd0;
-wire   [31:0] litedramcore_dat_r;
-wire   [29:0] litedramcore_wishbone_adr;
-wire   [31:0] litedramcore_wishbone_dat_w;
-reg    [31:0] litedramcore_wishbone_dat_r = 32'd0;
-wire    [3:0] litedramcore_wishbone_sel;
-wire          litedramcore_wishbone_cyc;
-wire          litedramcore_wishbone_stb;
-reg           litedramcore_wishbone_ack = 1'd0;
-wire          litedramcore_wishbone_we;
-wire    [2:0] litedramcore_wishbone_cti;
-wire    [1:0] litedramcore_wishbone_bte;
-reg           litedramcore_wishbone_err = 1'd0;
-wire   [13:0] interface0_bank_bus_adr;
-wire          interface0_bank_bus_we;
-wire   [31:0] interface0_bank_bus_dat_w;
-reg    [31:0] interface0_bank_bus_dat_r = 32'd0;
-reg           csrbank0_init_done0_re = 1'd0;
-wire          csrbank0_init_done0_r;
-reg           csrbank0_init_done0_we = 1'd0;
-wire          csrbank0_init_done0_w;
-reg           csrbank0_init_error0_re = 1'd0;
-wire          csrbank0_init_error0_r;
-reg           csrbank0_init_error0_we = 1'd0;
-wire          csrbank0_init_error0_w;
-wire          csrbank0_sel;
-wire   [13:0] interface1_bank_bus_adr;
-wire          interface1_bank_bus_we;
-wire   [31:0] interface1_bank_bus_dat_w;
-reg    [31:0] interface1_bank_bus_dat_r = 32'd0;
-reg           csrbank1_rst0_re = 1'd0;
-wire          csrbank1_rst0_r;
-reg           csrbank1_rst0_we = 1'd0;
-wire          csrbank1_rst0_w;
-reg           csrbank1_dly_sel0_re = 1'd0;
-wire    [1:0] csrbank1_dly_sel0_r;
-reg           csrbank1_dly_sel0_we = 1'd0;
-wire    [1:0] csrbank1_dly_sel0_w;
-reg           csrbank1_half_sys8x_taps0_re = 1'd0;
-wire    [4:0] csrbank1_half_sys8x_taps0_r;
-reg           csrbank1_half_sys8x_taps0_we = 1'd0;
-wire    [4:0] csrbank1_half_sys8x_taps0_w;
-reg           csrbank1_wlevel_en0_re = 1'd0;
-wire          csrbank1_wlevel_en0_r;
-reg           csrbank1_wlevel_en0_we = 1'd0;
-wire          csrbank1_wlevel_en0_w;
-reg           csrbank1_rdphase0_re = 1'd0;
-wire    [1:0] csrbank1_rdphase0_r;
-reg           csrbank1_rdphase0_we = 1'd0;
-wire    [1:0] csrbank1_rdphase0_w;
-reg           csrbank1_wrphase0_re = 1'd0;
-wire    [1:0] csrbank1_wrphase0_r;
-reg           csrbank1_wrphase0_we = 1'd0;
-wire    [1:0] csrbank1_wrphase0_w;
-wire          csrbank1_sel;
-wire   [13:0] interface2_bank_bus_adr;
-wire          interface2_bank_bus_we;
-wire   [31:0] interface2_bank_bus_dat_w;
-reg    [31:0] interface2_bank_bus_dat_r = 32'd0;
-reg           csrbank2_dfii_control0_re = 1'd0;
-wire    [3:0] csrbank2_dfii_control0_r;
-reg           csrbank2_dfii_control0_we = 1'd0;
-wire    [3:0] csrbank2_dfii_control0_w;
-reg           csrbank2_dfii_pi0_command0_re = 1'd0;
-wire    [5:0] csrbank2_dfii_pi0_command0_r;
-reg           csrbank2_dfii_pi0_command0_we = 1'd0;
-wire    [5:0] csrbank2_dfii_pi0_command0_w;
-reg           csrbank2_dfii_pi0_address0_re = 1'd0;
-wire   [13:0] csrbank2_dfii_pi0_address0_r;
-reg           csrbank2_dfii_pi0_address0_we = 1'd0;
-wire   [13:0] csrbank2_dfii_pi0_address0_w;
-reg           csrbank2_dfii_pi0_baddress0_re = 1'd0;
-wire    [2:0] csrbank2_dfii_pi0_baddress0_r;
-reg           csrbank2_dfii_pi0_baddress0_we = 1'd0;
-wire    [2:0] csrbank2_dfii_pi0_baddress0_w;
-reg           csrbank2_dfii_pi0_wrdata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_wrdata0_r;
-reg           csrbank2_dfii_pi0_wrdata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_wrdata0_w;
-reg           csrbank2_dfii_pi0_rddata_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_rddata_r;
-reg           csrbank2_dfii_pi0_rddata_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi0_rddata_w;
-reg           csrbank2_dfii_pi1_command0_re = 1'd0;
-wire    [5:0] csrbank2_dfii_pi1_command0_r;
-reg           csrbank2_dfii_pi1_command0_we = 1'd0;
-wire    [5:0] csrbank2_dfii_pi1_command0_w;
-reg           csrbank2_dfii_pi1_address0_re = 1'd0;
-wire   [13:0] csrbank2_dfii_pi1_address0_r;
-reg           csrbank2_dfii_pi1_address0_we = 1'd0;
-wire   [13:0] csrbank2_dfii_pi1_address0_w;
-reg           csrbank2_dfii_pi1_baddress0_re = 1'd0;
-wire    [2:0] csrbank2_dfii_pi1_baddress0_r;
-reg           csrbank2_dfii_pi1_baddress0_we = 1'd0;
-wire    [2:0] csrbank2_dfii_pi1_baddress0_w;
-reg           csrbank2_dfii_pi1_wrdata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_wrdata0_r;
-reg           csrbank2_dfii_pi1_wrdata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_wrdata0_w;
-reg           csrbank2_dfii_pi1_rddata_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_rddata_r;
-reg           csrbank2_dfii_pi1_rddata_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi1_rddata_w;
-reg           csrbank2_dfii_pi2_command0_re = 1'd0;
-wire    [5:0] csrbank2_dfii_pi2_command0_r;
-reg           csrbank2_dfii_pi2_command0_we = 1'd0;
-wire    [5:0] csrbank2_dfii_pi2_command0_w;
-reg           csrbank2_dfii_pi2_address0_re = 1'd0;
-wire   [13:0] csrbank2_dfii_pi2_address0_r;
-reg           csrbank2_dfii_pi2_address0_we = 1'd0;
-wire   [13:0] csrbank2_dfii_pi2_address0_w;
-reg           csrbank2_dfii_pi2_baddress0_re = 1'd0;
-wire    [2:0] csrbank2_dfii_pi2_baddress0_r;
-reg           csrbank2_dfii_pi2_baddress0_we = 1'd0;
-wire    [2:0] csrbank2_dfii_pi2_baddress0_w;
-reg           csrbank2_dfii_pi2_wrdata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi2_wrdata0_r;
-reg           csrbank2_dfii_pi2_wrdata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi2_wrdata0_w;
-reg           csrbank2_dfii_pi2_rddata_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi2_rddata_r;
-reg           csrbank2_dfii_pi2_rddata_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi2_rddata_w;
-reg           csrbank2_dfii_pi3_command0_re = 1'd0;
-wire    [5:0] csrbank2_dfii_pi3_command0_r;
-reg           csrbank2_dfii_pi3_command0_we = 1'd0;
-wire    [5:0] csrbank2_dfii_pi3_command0_w;
-reg           csrbank2_dfii_pi3_address0_re = 1'd0;
-wire   [13:0] csrbank2_dfii_pi3_address0_r;
-reg           csrbank2_dfii_pi3_address0_we = 1'd0;
-wire   [13:0] csrbank2_dfii_pi3_address0_w;
-reg           csrbank2_dfii_pi3_baddress0_re = 1'd0;
-wire    [2:0] csrbank2_dfii_pi3_baddress0_r;
-reg           csrbank2_dfii_pi3_baddress0_we = 1'd0;
-wire    [2:0] csrbank2_dfii_pi3_baddress0_w;
-reg           csrbank2_dfii_pi3_wrdata0_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi3_wrdata0_r;
-reg           csrbank2_dfii_pi3_wrdata0_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi3_wrdata0_w;
-reg           csrbank2_dfii_pi3_rddata_re = 1'd0;
-wire   [31:0] csrbank2_dfii_pi3_rddata_r;
-reg           csrbank2_dfii_pi3_rddata_we = 1'd0;
-wire   [31:0] csrbank2_dfii_pi3_rddata_w;
-wire          csrbank2_sel;
-wire   [13:0] csr_interconnect_adr;
-wire          csr_interconnect_we;
-wire   [31:0] csr_interconnect_dat_w;
-wire   [31:0] csr_interconnect_dat_r;
-wire          litedramcore_reset0;
-wire          litedramcore_reset1;
-wire          litedramcore_reset2;
-wire          litedramcore_reset3;
-wire          litedramcore_reset4;
-wire          litedramcore_reset5;
-wire          litedramcore_reset6;
-wire          litedramcore_reset7;
-wire          litedramcore_pll_fb;
-reg     [1:0] litedramcore_refresher_state = 2'd0;
-reg     [1:0] litedramcore_refresher_next_state = 2'd0;
-reg     [3:0] litedramcore_bankmachine0_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine0_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine1_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine1_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine2_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine2_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine3_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine3_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine4_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine4_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine5_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine5_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine6_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine6_next_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine7_state = 4'd0;
-reg     [3:0] litedramcore_bankmachine7_next_state = 4'd0;
-reg     [3:0] litedramcore_multiplexer_state = 4'd0;
-reg     [3:0] litedramcore_multiplexer_next_state = 4'd0;
-wire          litedramcore_roundrobin0_request;
-wire          litedramcore_roundrobin0_grant;
-wire          litedramcore_roundrobin0_ce;
-wire          litedramcore_roundrobin1_request;
-wire          litedramcore_roundrobin1_grant;
-wire          litedramcore_roundrobin1_ce;
-wire          litedramcore_roundrobin2_request;
-wire          litedramcore_roundrobin2_grant;
-wire          litedramcore_roundrobin2_ce;
-wire          litedramcore_roundrobin3_request;
-wire          litedramcore_roundrobin3_grant;
-wire          litedramcore_roundrobin3_ce;
-wire          litedramcore_roundrobin4_request;
-wire          litedramcore_roundrobin4_grant;
-wire          litedramcore_roundrobin4_ce;
-wire          litedramcore_roundrobin5_request;
-wire          litedramcore_roundrobin5_grant;
-wire          litedramcore_roundrobin5_ce;
-wire          litedramcore_roundrobin6_request;
-wire          litedramcore_roundrobin6_grant;
-wire          litedramcore_roundrobin6_ce;
-wire          litedramcore_roundrobin7_request;
-wire          litedramcore_roundrobin7_grant;
-wire          litedramcore_roundrobin7_ce;
-reg           litedramcore_locked0 = 1'd0;
-reg           litedramcore_locked1 = 1'd0;
-reg           litedramcore_locked2 = 1'd0;
-reg           litedramcore_locked3 = 1'd0;
-reg           litedramcore_locked4 = 1'd0;
-reg           litedramcore_locked5 = 1'd0;
-reg           litedramcore_locked6 = 1'd0;
-reg           litedramcore_locked7 = 1'd0;
-reg           litedramcore_new_master_wdata_ready0 = 1'd0;
-reg           litedramcore_new_master_wdata_ready1 = 1'd0;
-reg           litedramcore_new_master_rdata_valid0 = 1'd0;
-reg           litedramcore_new_master_rdata_valid1 = 1'd0;
-reg           litedramcore_new_master_rdata_valid2 = 1'd0;
-reg           litedramcore_new_master_rdata_valid3 = 1'd0;
-reg           litedramcore_new_master_rdata_valid4 = 1'd0;
-reg           litedramcore_new_master_rdata_valid5 = 1'd0;
-reg           litedramcore_new_master_rdata_valid6 = 1'd0;
-reg           litedramcore_new_master_rdata_valid7 = 1'd0;
-reg           litedramcore_new_master_rdata_valid8 = 1'd0;
-reg     [1:0] litedramcore_state = 2'd0;
-reg     [1:0] litedramcore_next_state = 2'd0;
-reg    [31:0] litedramcore_dat_w_next_value0 = 32'd0;
-reg           litedramcore_dat_w_next_value_ce0 = 1'd0;
-reg    [13:0] litedramcore_adr_next_value1 = 14'd0;
-reg           litedramcore_adr_next_value_ce1 = 1'd0;
-reg           litedramcore_we_next_value2 = 1'd0;
-reg           litedramcore_we_next_value_ce2 = 1'd0;
-reg           rhs_array_muxed0 = 1'd0;
-reg    [13:0] rhs_array_muxed1 = 14'd0;
-reg     [2:0] rhs_array_muxed2 = 3'd0;
-reg           rhs_array_muxed3 = 1'd0;
-reg           rhs_array_muxed4 = 1'd0;
-reg           rhs_array_muxed5 = 1'd0;
-reg           t_array_muxed0 = 1'd0;
-reg           t_array_muxed1 = 1'd0;
-reg           t_array_muxed2 = 1'd0;
-reg           rhs_array_muxed6 = 1'd0;
-reg    [13:0] rhs_array_muxed7 = 14'd0;
-reg     [2:0] rhs_array_muxed8 = 3'd0;
-reg           rhs_array_muxed9 = 1'd0;
-reg           rhs_array_muxed10 = 1'd0;
-reg           rhs_array_muxed11 = 1'd0;
-reg           t_array_muxed3 = 1'd0;
-reg           t_array_muxed4 = 1'd0;
-reg           t_array_muxed5 = 1'd0;
-reg    [20:0] rhs_array_muxed12 = 21'd0;
-reg           rhs_array_muxed13 = 1'd0;
-reg           rhs_array_muxed14 = 1'd0;
-reg    [20:0] rhs_array_muxed15 = 21'd0;
-reg           rhs_array_muxed16 = 1'd0;
-reg           rhs_array_muxed17 = 1'd0;
-reg    [20:0] rhs_array_muxed18 = 21'd0;
-reg           rhs_array_muxed19 = 1'd0;
-reg           rhs_array_muxed20 = 1'd0;
-reg    [20:0] rhs_array_muxed21 = 21'd0;
-reg           rhs_array_muxed22 = 1'd0;
-reg           rhs_array_muxed23 = 1'd0;
-reg    [20:0] rhs_array_muxed24 = 21'd0;
-reg           rhs_array_muxed25 = 1'd0;
-reg           rhs_array_muxed26 = 1'd0;
-reg    [20:0] rhs_array_muxed27 = 21'd0;
-reg           rhs_array_muxed28 = 1'd0;
-reg           rhs_array_muxed29 = 1'd0;
-reg    [20:0] rhs_array_muxed30 = 21'd0;
-reg           rhs_array_muxed31 = 1'd0;
-reg           rhs_array_muxed32 = 1'd0;
-reg    [20:0] rhs_array_muxed33 = 21'd0;
-reg           rhs_array_muxed34 = 1'd0;
-reg           rhs_array_muxed35 = 1'd0;
-reg     [2:0] array_muxed0 = 3'd0;
-reg    [13:0] array_muxed1 = 14'd0;
-reg           array_muxed2 = 1'd0;
-reg           array_muxed3 = 1'd0;
-reg           array_muxed4 = 1'd0;
-reg           array_muxed5 = 1'd0;
-reg           array_muxed6 = 1'd0;
-reg     [2:0] array_muxed7 = 3'd0;
-reg    [13:0] array_muxed8 = 14'd0;
-reg           array_muxed9 = 1'd0;
-reg           array_muxed10 = 1'd0;
-reg           array_muxed11 = 1'd0;
-reg           array_muxed12 = 1'd0;
-reg           array_muxed13 = 1'd0;
-reg     [2:0] array_muxed14 = 3'd0;
-reg    [13:0] array_muxed15 = 14'd0;
-reg           array_muxed16 = 1'd0;
-reg           array_muxed17 = 1'd0;
-reg           array_muxed18 = 1'd0;
-reg           array_muxed19 = 1'd0;
-reg           array_muxed20 = 1'd0;
-reg     [2:0] array_muxed21 = 3'd0;
-reg    [13:0] array_muxed22 = 14'd0;
-reg           array_muxed23 = 1'd0;
-reg           array_muxed24 = 1'd0;
-reg           array_muxed25 = 1'd0;
-reg           array_muxed26 = 1'd0;
-reg           array_muxed27 = 1'd0;
-wire          xilinxasyncresetsynchronizerimpl0;
-wire          xilinxasyncresetsynchronizerimpl0_rst_meta;
-wire          xilinxasyncresetsynchronizerimpl1;
-wire          xilinxasyncresetsynchronizerimpl1_rst_meta;
-wire          xilinxasyncresetsynchronizerimpl2;
-wire          xilinxasyncresetsynchronizerimpl2_rst_meta;
-wire          xilinxasyncresetsynchronizerimpl2_expr;
-wire          xilinxasyncresetsynchronizerimpl3;
-wire          xilinxasyncresetsynchronizerimpl3_rst_meta;
-wire          xilinxasyncresetsynchronizerimpl3_expr;
+reg           main_litedramcore_twtrcon_ready = 1'd0;
+wire          main_litedramcore_twtrcon_valid;
+wire          main_litedramcore_wants_refresh;
+wire          main_litedramcore_wants_zqcs;
+wire          main_litedramcore_write_available;
+reg           main_litedramcore_zqcs_executer_done = 1'd0;
+reg           main_litedramcore_zqcs_executer_start = 1'd0;
+reg     [4:0] main_litedramcore_zqcs_executer_trigger = 5'd0;
+wire   [26:0] main_litedramcore_zqcs_timer_count0;
+reg    [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999;
+wire          main_litedramcore_zqcs_timer_done0;
+wire          main_litedramcore_zqcs_timer_done1;
+wire          main_litedramcore_zqcs_timer_wait;
+wire          main_locked;
+reg           main_power_down = 1'd0;
+wire          main_reset;
+reg     [3:0] main_reset_counter = 4'd15;
+reg           main_rst = 1'd0;
+wire          main_user_enable;
+wire   [23:0] main_user_port_cmd_payload_addr;
+wire          main_user_port_cmd_payload_we;
+wire          main_user_port_cmd_ready;
+wire          main_user_port_cmd_valid;
+wire  [127:0] main_user_port_rdata_payload_data;
+wire          main_user_port_rdata_ready;
+wire          main_user_port_rdata_valid;
+wire  [127:0] main_user_port_wdata_payload_data;
+wire   [15:0] main_user_port_wdata_payload_we;
+wire          main_user_port_wdata_ready;
+wire          main_user_port_wdata_valid;
+wire          main_wb_bus_ack;
+wire   [29:0] main_wb_bus_adr;
+wire    [1:0] main_wb_bus_bte;
+wire    [2:0] main_wb_bus_cti;
+wire          main_wb_bus_cyc;
+wire   [31:0] main_wb_bus_dat_r;
+wire   [31:0] main_wb_bus_dat_w;
+wire          main_wb_bus_err;
+wire    [3:0] main_wb_bus_sel;
+wire          main_wb_bus_stb;
+wire          main_wb_bus_we;
+wire          sys4x_clk;
+wire          sys4x_dqs_clk;
+wire          sys_clk;
+wire          sys_rst;
 
 //------------------------------------------------------------------------------
 // Combinatorial Logic
 //------------------------------------------------------------------------------
 
-assign init_done = init_done_storage;
-assign init_error = init_error_storage;
-assign wb_bus_adr = wb_ctrl_adr;
-assign wb_bus_dat_w = wb_ctrl_dat_w;
-assign wb_ctrl_dat_r = wb_bus_dat_r;
-assign wb_bus_sel = wb_ctrl_sel;
-assign wb_bus_cyc = wb_ctrl_cyc;
-assign wb_bus_stb = wb_ctrl_stb;
-assign wb_ctrl_ack = wb_bus_ack;
-assign wb_bus_we = wb_ctrl_we;
-assign wb_bus_cti = wb_ctrl_cti;
-assign wb_bus_bte = wb_ctrl_bte;
-assign wb_ctrl_err = wb_bus_err;
+assign init_done = main_init_done_storage;
+assign init_error = main_init_error_storage;
+assign main_wb_bus_adr = wb_ctrl_adr;
+assign main_wb_bus_dat_w = wb_ctrl_dat_w;
+assign wb_ctrl_dat_r = main_wb_bus_dat_r;
+assign main_wb_bus_sel = wb_ctrl_sel;
+assign main_wb_bus_cyc = wb_ctrl_cyc;
+assign main_wb_bus_stb = wb_ctrl_stb;
+assign wb_ctrl_ack = main_wb_bus_ack;
+assign main_wb_bus_we = wb_ctrl_we;
+assign main_wb_bus_cti = wb_ctrl_cti;
+assign main_wb_bus_bte = wb_ctrl_bte;
+assign wb_ctrl_err = main_wb_bus_err;
 assign user_clk = sys_clk;
 assign user_rst = sys_rst;
-assign user_enable = 1'd1;
-assign user_port_cmd_valid = (user_port_native_0_cmd_valid & user_enable);
-assign user_port_native_0_cmd_ready = (user_port_cmd_ready & user_enable);
-assign user_port_cmd_payload_we = user_port_native_0_cmd_we;
-assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
-assign user_port_wdata_valid = (user_port_native_0_wdata_valid & user_enable);
-assign user_port_native_0_wdata_ready = (user_port_wdata_ready & user_enable);
-assign user_port_wdata_payload_we = user_port_native_0_wdata_we;
-assign user_port_wdata_payload_data = user_port_native_0_wdata_data;
-assign user_port_native_0_rdata_valid = (user_port_rdata_valid & user_enable);
-assign user_port_rdata_ready = (user_port_native_0_rdata_ready & user_enable);
-assign user_port_native_0_rdata_data = user_port_rdata_payload_data;
-assign reset = (rst | rst_1);
-assign pll_locked = locked;
-assign clkin = clk;
-assign iodelay_clk = clkout_buf0;
-assign sys_clk = clkout_buf1;
-assign sys4x_clk = clkout_buf2;
-assign sys4x_dqs_clk = clkout_buf3;
-assign ddram_ba = a7ddrphy_pads_ba;
-assign a7ddrphy_dqs_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dqs_oe) | a7ddrphy_dqs_postamble);
-assign a7ddrphy_dq_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dq_oe) | a7ddrphy_dqs_postamble);
-always @(*) begin
-    a7ddrphy_dfi_p0_rddata <= 32'd0;
-    a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0];
-    a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1];
-    a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0];
-    a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1];
-    a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0];
-    a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1];
-    a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0];
-    a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1];
-    a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0];
-    a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1];
-    a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0];
-    a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1];
-    a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0];
-    a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1];
-    a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0];
-    a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1];
-    a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0];
-    a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1];
-    a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0];
-    a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1];
-    a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0];
-    a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1];
-    a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0];
-    a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1];
-    a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0];
-    a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1];
-    a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0];
-    a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1];
-    a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0];
-    a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1];
-    a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0];
-    a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1];
-end
-always @(*) begin
-    a7ddrphy_dfi_p1_rddata <= 32'd0;
-    a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2];
-    a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3];
-    a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2];
-    a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3];
-    a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2];
-    a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3];
-    a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2];
-    a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3];
-    a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2];
-    a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3];
-    a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2];
-    a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3];
-    a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2];
-    a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3];
-    a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2];
-    a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3];
-    a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2];
-    a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3];
-    a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2];
-    a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3];
-    a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2];
-    a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3];
-    a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2];
-    a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3];
-    a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2];
-    a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3];
-    a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2];
-    a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3];
-    a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2];
-    a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3];
-    a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2];
-    a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3];
-end
-always @(*) begin
-    a7ddrphy_dfi_p2_rddata <= 32'd0;
-    a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4];
-    a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5];
-    a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4];
-    a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5];
-    a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4];
-    a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5];
-    a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4];
-    a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5];
-    a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4];
-    a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5];
-    a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4];
-    a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5];
-    a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4];
-    a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5];
-    a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4];
-    a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5];
-    a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4];
-    a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5];
-    a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4];
-    a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5];
-    a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4];
-    a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5];
-    a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4];
-    a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5];
-    a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4];
-    a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5];
-    a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4];
-    a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5];
-    a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4];
-    a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5];
-    a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4];
-    a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5];
-end
-always @(*) begin
-    a7ddrphy_dfi_p3_rddata <= 32'd0;
-    a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6];
-    a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7];
-    a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6];
-    a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7];
-    a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6];
-    a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7];
-    a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6];
-    a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7];
-    a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6];
-    a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7];
-    a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6];
-    a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7];
-    a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6];
-    a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7];
-    a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6];
-    a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7];
-    a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6];
-    a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7];
-    a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6];
-    a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7];
-    a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6];
-    a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7];
-    a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6];
-    a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7];
-    a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6];
-    a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7];
-    a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6];
-    a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7];
-    a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6];
-    a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7];
-    a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6];
-    a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7];
-end
-assign a7ddrphy_dfi_p0_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
-assign a7ddrphy_dfi_p1_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
-assign a7ddrphy_dfi_p2_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
-assign a7ddrphy_dfi_p3_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
-assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en_tappeddelayline1;
-always @(*) begin
-    a7ddrphy_dqs_oe <= 1'd0;
-    if (a7ddrphy_wlevel_en_storage) begin
-        a7ddrphy_dqs_oe <= 1'd1;
-    end else begin
-        a7ddrphy_dqs_oe <= a7ddrphy_dq_oe;
-    end
-end
-assign a7ddrphy_dqs_preamble = (a7ddrphy_wrdata_en_tappeddelayline0 & (~a7ddrphy_wrdata_en_tappeddelayline1));
-assign a7ddrphy_dqs_postamble = (a7ddrphy_wrdata_en_tappeddelayline2 & (~a7ddrphy_wrdata_en_tappeddelayline1));
-always @(*) begin
-    a7ddrphy_dqspattern_o0 <= 8'd0;
-    a7ddrphy_dqspattern_o0 <= 7'd85;
-    if (a7ddrphy_dqspattern0) begin
-        a7ddrphy_dqspattern_o0 <= 5'd21;
-    end
-    if (a7ddrphy_dqspattern1) begin
-        a7ddrphy_dqspattern_o0 <= 7'd84;
-    end
-    if (a7ddrphy_wlevel_en_storage) begin
-        a7ddrphy_dqspattern_o0 <= 1'd0;
-        if (a7ddrphy_wlevel_strobe_re) begin
-            a7ddrphy_dqspattern_o0 <= 1'd1;
-        end
-    end
-end
-always @(*) begin
-    a7ddrphy_bitslip00 <= 8'd0;
-    case (a7ddrphy_bitslip0_value0)
+assign main_user_enable = 1'd1;
+assign main_user_port_cmd_valid = (user_port_native_0_cmd_valid & main_user_enable);
+assign user_port_native_0_cmd_ready = (main_user_port_cmd_ready & main_user_enable);
+assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we;
+assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
+assign main_user_port_wdata_valid = (user_port_native_0_wdata_valid & main_user_enable);
+assign user_port_native_0_wdata_ready = (main_user_port_wdata_ready & main_user_enable);
+assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we;
+assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data;
+assign user_port_native_0_rdata_valid = (main_user_port_rdata_valid & main_user_enable);
+assign main_user_port_rdata_ready = (user_port_native_0_rdata_ready & main_user_enable);
+assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data;
+assign builder_interface0_adr = main_wb_bus_adr;
+assign builder_interface0_dat_w = main_wb_bus_dat_w;
+assign main_wb_bus_dat_r = builder_interface0_dat_r;
+assign builder_interface0_sel = main_wb_bus_sel;
+assign builder_interface0_cyc = main_wb_bus_cyc;
+assign builder_interface0_stb = main_wb_bus_stb;
+assign main_wb_bus_ack = builder_interface0_ack;
+assign builder_interface0_we = main_wb_bus_we;
+assign builder_interface0_cti = main_wb_bus_cti;
+assign builder_interface0_bte = main_wb_bus_bte;
+assign main_wb_bus_err = builder_interface0_err;
+assign main_reset = (rst | main_rst);
+assign pll_locked = main_locked;
+assign main_clkin = clk;
+assign iodelay_clk = main_clkout_buf0;
+assign sys_clk = main_clkout_buf1;
+assign sys4x_clk = main_clkout_buf2;
+assign sys4x_dqs_clk = main_clkout_buf3;
+assign ddram_ba = main_a7ddrphy_pads_ba;
+assign main_a7ddrphy_dqs_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_oe) | main_a7ddrphy_dqs_postamble);
+assign main_a7ddrphy_dq_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dq_oe) | main_a7ddrphy_dqs_postamble);
+always @(*) begin
+    main_a7ddrphy_dfi_p0_rddata <= 32'd0;
+    main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip04[0];
+    main_a7ddrphy_dfi_p0_rddata[16] <= main_a7ddrphy_bitslip04[1];
+    main_a7ddrphy_dfi_p0_rddata[1] <= main_a7ddrphy_bitslip14[0];
+    main_a7ddrphy_dfi_p0_rddata[17] <= main_a7ddrphy_bitslip14[1];
+    main_a7ddrphy_dfi_p0_rddata[2] <= main_a7ddrphy_bitslip22[0];
+    main_a7ddrphy_dfi_p0_rddata[18] <= main_a7ddrphy_bitslip22[1];
+    main_a7ddrphy_dfi_p0_rddata[3] <= main_a7ddrphy_bitslip32[0];
+    main_a7ddrphy_dfi_p0_rddata[19] <= main_a7ddrphy_bitslip32[1];
+    main_a7ddrphy_dfi_p0_rddata[4] <= main_a7ddrphy_bitslip42[0];
+    main_a7ddrphy_dfi_p0_rddata[20] <= main_a7ddrphy_bitslip42[1];
+    main_a7ddrphy_dfi_p0_rddata[5] <= main_a7ddrphy_bitslip52[0];
+    main_a7ddrphy_dfi_p0_rddata[21] <= main_a7ddrphy_bitslip52[1];
+    main_a7ddrphy_dfi_p0_rddata[6] <= main_a7ddrphy_bitslip62[0];
+    main_a7ddrphy_dfi_p0_rddata[22] <= main_a7ddrphy_bitslip62[1];
+    main_a7ddrphy_dfi_p0_rddata[7] <= main_a7ddrphy_bitslip72[0];
+    main_a7ddrphy_dfi_p0_rddata[23] <= main_a7ddrphy_bitslip72[1];
+    main_a7ddrphy_dfi_p0_rddata[8] <= main_a7ddrphy_bitslip82[0];
+    main_a7ddrphy_dfi_p0_rddata[24] <= main_a7ddrphy_bitslip82[1];
+    main_a7ddrphy_dfi_p0_rddata[9] <= main_a7ddrphy_bitslip92[0];
+    main_a7ddrphy_dfi_p0_rddata[25] <= main_a7ddrphy_bitslip92[1];
+    main_a7ddrphy_dfi_p0_rddata[10] <= main_a7ddrphy_bitslip102[0];
+    main_a7ddrphy_dfi_p0_rddata[26] <= main_a7ddrphy_bitslip102[1];
+    main_a7ddrphy_dfi_p0_rddata[11] <= main_a7ddrphy_bitslip112[0];
+    main_a7ddrphy_dfi_p0_rddata[27] <= main_a7ddrphy_bitslip112[1];
+    main_a7ddrphy_dfi_p0_rddata[12] <= main_a7ddrphy_bitslip122[0];
+    main_a7ddrphy_dfi_p0_rddata[28] <= main_a7ddrphy_bitslip122[1];
+    main_a7ddrphy_dfi_p0_rddata[13] <= main_a7ddrphy_bitslip132[0];
+    main_a7ddrphy_dfi_p0_rddata[29] <= main_a7ddrphy_bitslip132[1];
+    main_a7ddrphy_dfi_p0_rddata[14] <= main_a7ddrphy_bitslip142[0];
+    main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip142[1];
+    main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip152[0];
+    main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip152[1];
+end
+always @(*) begin
+    main_a7ddrphy_dfi_p1_rddata <= 32'd0;
+    main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip04[2];
+    main_a7ddrphy_dfi_p1_rddata[16] <= main_a7ddrphy_bitslip04[3];
+    main_a7ddrphy_dfi_p1_rddata[1] <= main_a7ddrphy_bitslip14[2];
+    main_a7ddrphy_dfi_p1_rddata[17] <= main_a7ddrphy_bitslip14[3];
+    main_a7ddrphy_dfi_p1_rddata[2] <= main_a7ddrphy_bitslip22[2];
+    main_a7ddrphy_dfi_p1_rddata[18] <= main_a7ddrphy_bitslip22[3];
+    main_a7ddrphy_dfi_p1_rddata[3] <= main_a7ddrphy_bitslip32[2];
+    main_a7ddrphy_dfi_p1_rddata[19] <= main_a7ddrphy_bitslip32[3];
+    main_a7ddrphy_dfi_p1_rddata[4] <= main_a7ddrphy_bitslip42[2];
+    main_a7ddrphy_dfi_p1_rddata[20] <= main_a7ddrphy_bitslip42[3];
+    main_a7ddrphy_dfi_p1_rddata[5] <= main_a7ddrphy_bitslip52[2];
+    main_a7ddrphy_dfi_p1_rddata[21] <= main_a7ddrphy_bitslip52[3];
+    main_a7ddrphy_dfi_p1_rddata[6] <= main_a7ddrphy_bitslip62[2];
+    main_a7ddrphy_dfi_p1_rddata[22] <= main_a7ddrphy_bitslip62[3];
+    main_a7ddrphy_dfi_p1_rddata[7] <= main_a7ddrphy_bitslip72[2];
+    main_a7ddrphy_dfi_p1_rddata[23] <= main_a7ddrphy_bitslip72[3];
+    main_a7ddrphy_dfi_p1_rddata[8] <= main_a7ddrphy_bitslip82[2];
+    main_a7ddrphy_dfi_p1_rddata[24] <= main_a7ddrphy_bitslip82[3];
+    main_a7ddrphy_dfi_p1_rddata[9] <= main_a7ddrphy_bitslip92[2];
+    main_a7ddrphy_dfi_p1_rddata[25] <= main_a7ddrphy_bitslip92[3];
+    main_a7ddrphy_dfi_p1_rddata[10] <= main_a7ddrphy_bitslip102[2];
+    main_a7ddrphy_dfi_p1_rddata[26] <= main_a7ddrphy_bitslip102[3];
+    main_a7ddrphy_dfi_p1_rddata[11] <= main_a7ddrphy_bitslip112[2];
+    main_a7ddrphy_dfi_p1_rddata[27] <= main_a7ddrphy_bitslip112[3];
+    main_a7ddrphy_dfi_p1_rddata[12] <= main_a7ddrphy_bitslip122[2];
+    main_a7ddrphy_dfi_p1_rddata[28] <= main_a7ddrphy_bitslip122[3];
+    main_a7ddrphy_dfi_p1_rddata[13] <= main_a7ddrphy_bitslip132[2];
+    main_a7ddrphy_dfi_p1_rddata[29] <= main_a7ddrphy_bitslip132[3];
+    main_a7ddrphy_dfi_p1_rddata[14] <= main_a7ddrphy_bitslip142[2];
+    main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip142[3];
+    main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip152[2];
+    main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip152[3];
+end
+always @(*) begin
+    main_a7ddrphy_dfi_p2_rddata <= 32'd0;
+    main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip04[4];
+    main_a7ddrphy_dfi_p2_rddata[16] <= main_a7ddrphy_bitslip04[5];
+    main_a7ddrphy_dfi_p2_rddata[1] <= main_a7ddrphy_bitslip14[4];
+    main_a7ddrphy_dfi_p2_rddata[17] <= main_a7ddrphy_bitslip14[5];
+    main_a7ddrphy_dfi_p2_rddata[2] <= main_a7ddrphy_bitslip22[4];
+    main_a7ddrphy_dfi_p2_rddata[18] <= main_a7ddrphy_bitslip22[5];
+    main_a7ddrphy_dfi_p2_rddata[3] <= main_a7ddrphy_bitslip32[4];
+    main_a7ddrphy_dfi_p2_rddata[19] <= main_a7ddrphy_bitslip32[5];
+    main_a7ddrphy_dfi_p2_rddata[4] <= main_a7ddrphy_bitslip42[4];
+    main_a7ddrphy_dfi_p2_rddata[20] <= main_a7ddrphy_bitslip42[5];
+    main_a7ddrphy_dfi_p2_rddata[5] <= main_a7ddrphy_bitslip52[4];
+    main_a7ddrphy_dfi_p2_rddata[21] <= main_a7ddrphy_bitslip52[5];
+    main_a7ddrphy_dfi_p2_rddata[6] <= main_a7ddrphy_bitslip62[4];
+    main_a7ddrphy_dfi_p2_rddata[22] <= main_a7ddrphy_bitslip62[5];
+    main_a7ddrphy_dfi_p2_rddata[7] <= main_a7ddrphy_bitslip72[4];
+    main_a7ddrphy_dfi_p2_rddata[23] <= main_a7ddrphy_bitslip72[5];
+    main_a7ddrphy_dfi_p2_rddata[8] <= main_a7ddrphy_bitslip82[4];
+    main_a7ddrphy_dfi_p2_rddata[24] <= main_a7ddrphy_bitslip82[5];
+    main_a7ddrphy_dfi_p2_rddata[9] <= main_a7ddrphy_bitslip92[4];
+    main_a7ddrphy_dfi_p2_rddata[25] <= main_a7ddrphy_bitslip92[5];
+    main_a7ddrphy_dfi_p2_rddata[10] <= main_a7ddrphy_bitslip102[4];
+    main_a7ddrphy_dfi_p2_rddata[26] <= main_a7ddrphy_bitslip102[5];
+    main_a7ddrphy_dfi_p2_rddata[11] <= main_a7ddrphy_bitslip112[4];
+    main_a7ddrphy_dfi_p2_rddata[27] <= main_a7ddrphy_bitslip112[5];
+    main_a7ddrphy_dfi_p2_rddata[12] <= main_a7ddrphy_bitslip122[4];
+    main_a7ddrphy_dfi_p2_rddata[28] <= main_a7ddrphy_bitslip122[5];
+    main_a7ddrphy_dfi_p2_rddata[13] <= main_a7ddrphy_bitslip132[4];
+    main_a7ddrphy_dfi_p2_rddata[29] <= main_a7ddrphy_bitslip132[5];
+    main_a7ddrphy_dfi_p2_rddata[14] <= main_a7ddrphy_bitslip142[4];
+    main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip142[5];
+    main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip152[4];
+    main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip152[5];
+end
+always @(*) begin
+    main_a7ddrphy_dfi_p3_rddata <= 32'd0;
+    main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip04[6];
+    main_a7ddrphy_dfi_p3_rddata[16] <= main_a7ddrphy_bitslip04[7];
+    main_a7ddrphy_dfi_p3_rddata[1] <= main_a7ddrphy_bitslip14[6];
+    main_a7ddrphy_dfi_p3_rddata[17] <= main_a7ddrphy_bitslip14[7];
+    main_a7ddrphy_dfi_p3_rddata[2] <= main_a7ddrphy_bitslip22[6];
+    main_a7ddrphy_dfi_p3_rddata[18] <= main_a7ddrphy_bitslip22[7];
+    main_a7ddrphy_dfi_p3_rddata[3] <= main_a7ddrphy_bitslip32[6];
+    main_a7ddrphy_dfi_p3_rddata[19] <= main_a7ddrphy_bitslip32[7];
+    main_a7ddrphy_dfi_p3_rddata[4] <= main_a7ddrphy_bitslip42[6];
+    main_a7ddrphy_dfi_p3_rddata[20] <= main_a7ddrphy_bitslip42[7];
+    main_a7ddrphy_dfi_p3_rddata[5] <= main_a7ddrphy_bitslip52[6];
+    main_a7ddrphy_dfi_p3_rddata[21] <= main_a7ddrphy_bitslip52[7];
+    main_a7ddrphy_dfi_p3_rddata[6] <= main_a7ddrphy_bitslip62[6];
+    main_a7ddrphy_dfi_p3_rddata[22] <= main_a7ddrphy_bitslip62[7];
+    main_a7ddrphy_dfi_p3_rddata[7] <= main_a7ddrphy_bitslip72[6];
+    main_a7ddrphy_dfi_p3_rddata[23] <= main_a7ddrphy_bitslip72[7];
+    main_a7ddrphy_dfi_p3_rddata[8] <= main_a7ddrphy_bitslip82[6];
+    main_a7ddrphy_dfi_p3_rddata[24] <= main_a7ddrphy_bitslip82[7];
+    main_a7ddrphy_dfi_p3_rddata[9] <= main_a7ddrphy_bitslip92[6];
+    main_a7ddrphy_dfi_p3_rddata[25] <= main_a7ddrphy_bitslip92[7];
+    main_a7ddrphy_dfi_p3_rddata[10] <= main_a7ddrphy_bitslip102[6];
+    main_a7ddrphy_dfi_p3_rddata[26] <= main_a7ddrphy_bitslip102[7];
+    main_a7ddrphy_dfi_p3_rddata[11] <= main_a7ddrphy_bitslip112[6];
+    main_a7ddrphy_dfi_p3_rddata[27] <= main_a7ddrphy_bitslip112[7];
+    main_a7ddrphy_dfi_p3_rddata[12] <= main_a7ddrphy_bitslip122[6];
+    main_a7ddrphy_dfi_p3_rddata[28] <= main_a7ddrphy_bitslip122[7];
+    main_a7ddrphy_dfi_p3_rddata[13] <= main_a7ddrphy_bitslip132[6];
+    main_a7ddrphy_dfi_p3_rddata[29] <= main_a7ddrphy_bitslip132[7];
+    main_a7ddrphy_dfi_p3_rddata[14] <= main_a7ddrphy_bitslip142[6];
+    main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip142[7];
+    main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip152[6];
+    main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip152[7];
+end
+assign main_a7ddrphy_dfi_p0_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
+assign main_a7ddrphy_dfi_p1_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
+assign main_a7ddrphy_dfi_p2_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
+assign main_a7ddrphy_dfi_p3_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
+assign main_a7ddrphy_dq_oe = main_a7ddrphy_wrdata_en_tappeddelayline1;
+always @(*) begin
+    main_a7ddrphy_dqs_oe <= 1'd0;
+    if (main_a7ddrphy_wlevel_en_storage) begin
+        main_a7ddrphy_dqs_oe <= 1'd1;
+    end else begin
+        main_a7ddrphy_dqs_oe <= main_a7ddrphy_dq_oe;
+    end
+end
+assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_wrdata_en_tappeddelayline0 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
+assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_wrdata_en_tappeddelayline2 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
+always @(*) begin
+    main_a7ddrphy_dqspattern_o0 <= 8'd0;
+    main_a7ddrphy_dqspattern_o0 <= 7'd85;
+    if (main_a7ddrphy_dqspattern0) begin
+        main_a7ddrphy_dqspattern_o0 <= 5'd21;
+    end
+    if (main_a7ddrphy_dqspattern1) begin
+        main_a7ddrphy_dqspattern_o0 <= 7'd84;
+    end
+    if (main_a7ddrphy_wlevel_en_storage) begin
+        main_a7ddrphy_dqspattern_o0 <= 1'd0;
+        if (main_a7ddrphy_wlevel_strobe_re) begin
+            main_a7ddrphy_dqspattern_o0 <= 1'd1;
+        end
+    end
+end
+always @(*) begin
+    main_a7ddrphy_bitslip00 <= 8'd0;
+    case (main_a7ddrphy_bitslip0_value0)
         1'd0: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8];
+            main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip10 <= 8'd0;
-    case (a7ddrphy_bitslip1_value0)
+    main_a7ddrphy_bitslip10 <= 8'd0;
+    case (main_a7ddrphy_bitslip1_value0)
         1'd0: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8];
+            main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip01 <= 8'd0;
-    case (a7ddrphy_bitslip0_value1)
+    main_a7ddrphy_bitslip01 <= 8'd0;
+    case (main_a7ddrphy_bitslip0_value1)
         1'd0: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8];
+            main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip11 <= 8'd0;
-    case (a7ddrphy_bitslip1_value1)
+    main_a7ddrphy_bitslip11 <= 8'd0;
+    case (main_a7ddrphy_bitslip1_value1)
         1'd0: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8];
+            main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip02 <= 8'd0;
-    case (a7ddrphy_bitslip0_value2)
+    main_a7ddrphy_bitslip02 <= 8'd0;
+    case (main_a7ddrphy_bitslip0_value2)
         1'd0: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8];
+            main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip04 <= 8'd0;
-    case (a7ddrphy_bitslip0_value3)
+    main_a7ddrphy_bitslip04 <= 8'd0;
+    case (main_a7ddrphy_bitslip0_value3)
         1'd0: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8];
+            main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip12 <= 8'd0;
-    case (a7ddrphy_bitslip1_value2)
+    main_a7ddrphy_bitslip12 <= 8'd0;
+    case (main_a7ddrphy_bitslip1_value2)
         1'd0: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8];
+            main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip14 <= 8'd0;
-    case (a7ddrphy_bitslip1_value3)
+    main_a7ddrphy_bitslip14 <= 8'd0;
+    case (main_a7ddrphy_bitslip1_value3)
         1'd0: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8];
+            main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip20 <= 8'd0;
-    case (a7ddrphy_bitslip2_value0)
+    main_a7ddrphy_bitslip20 <= 8'd0;
+    case (main_a7ddrphy_bitslip2_value0)
         1'd0: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8];
+            main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip22 <= 8'd0;
-    case (a7ddrphy_bitslip2_value1)
+    main_a7ddrphy_bitslip22 <= 8'd0;
+    case (main_a7ddrphy_bitslip2_value1)
         1'd0: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8];
+            main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip30 <= 8'd0;
-    case (a7ddrphy_bitslip3_value0)
+    main_a7ddrphy_bitslip30 <= 8'd0;
+    case (main_a7ddrphy_bitslip3_value0)
         1'd0: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8];
+            main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip32 <= 8'd0;
-    case (a7ddrphy_bitslip3_value1)
+    main_a7ddrphy_bitslip32 <= 8'd0;
+    case (main_a7ddrphy_bitslip3_value1)
         1'd0: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8];
+            main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip40 <= 8'd0;
-    case (a7ddrphy_bitslip4_value0)
+    main_a7ddrphy_bitslip40 <= 8'd0;
+    case (main_a7ddrphy_bitslip4_value0)
         1'd0: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8];
+            main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip42 <= 8'd0;
-    case (a7ddrphy_bitslip4_value1)
+    main_a7ddrphy_bitslip42 <= 8'd0;
+    case (main_a7ddrphy_bitslip4_value1)
         1'd0: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8];
+            main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip50 <= 8'd0;
-    case (a7ddrphy_bitslip5_value0)
+    main_a7ddrphy_bitslip50 <= 8'd0;
+    case (main_a7ddrphy_bitslip5_value0)
         1'd0: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8];
+            main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip52 <= 8'd0;
-    case (a7ddrphy_bitslip5_value1)
+    main_a7ddrphy_bitslip52 <= 8'd0;
+    case (main_a7ddrphy_bitslip5_value1)
         1'd0: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8];
+            main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip60 <= 8'd0;
-    case (a7ddrphy_bitslip6_value0)
+    main_a7ddrphy_bitslip60 <= 8'd0;
+    case (main_a7ddrphy_bitslip6_value0)
         1'd0: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8];
+            main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip62 <= 8'd0;
-    case (a7ddrphy_bitslip6_value1)
+    main_a7ddrphy_bitslip62 <= 8'd0;
+    case (main_a7ddrphy_bitslip6_value1)
         1'd0: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8];
+            main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip70 <= 8'd0;
-    case (a7ddrphy_bitslip7_value0)
+    main_a7ddrphy_bitslip70 <= 8'd0;
+    case (main_a7ddrphy_bitslip7_value0)
         1'd0: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8];
+            main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip72 <= 8'd0;
-    case (a7ddrphy_bitslip7_value1)
+    main_a7ddrphy_bitslip72 <= 8'd0;
+    case (main_a7ddrphy_bitslip7_value1)
         1'd0: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8];
+            main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip80 <= 8'd0;
-    case (a7ddrphy_bitslip8_value0)
+    main_a7ddrphy_bitslip80 <= 8'd0;
+    case (main_a7ddrphy_bitslip8_value0)
         1'd0: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8];
+            main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip82 <= 8'd0;
-    case (a7ddrphy_bitslip8_value1)
+    main_a7ddrphy_bitslip82 <= 8'd0;
+    case (main_a7ddrphy_bitslip8_value1)
         1'd0: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8];
+            main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip90 <= 8'd0;
-    case (a7ddrphy_bitslip9_value0)
+    main_a7ddrphy_bitslip90 <= 8'd0;
+    case (main_a7ddrphy_bitslip9_value0)
         1'd0: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8];
+            main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip92 <= 8'd0;
-    case (a7ddrphy_bitslip9_value1)
+    main_a7ddrphy_bitslip92 <= 8'd0;
+    case (main_a7ddrphy_bitslip9_value1)
         1'd0: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8];
+            main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip100 <= 8'd0;
-    case (a7ddrphy_bitslip10_value0)
+    main_a7ddrphy_bitslip100 <= 8'd0;
+    case (main_a7ddrphy_bitslip10_value0)
         1'd0: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8];
+            main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip102 <= 8'd0;
-    case (a7ddrphy_bitslip10_value1)
+    main_a7ddrphy_bitslip102 <= 8'd0;
+    case (main_a7ddrphy_bitslip10_value1)
         1'd0: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8];
+            main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip110 <= 8'd0;
-    case (a7ddrphy_bitslip11_value0)
+    main_a7ddrphy_bitslip110 <= 8'd0;
+    case (main_a7ddrphy_bitslip11_value0)
         1'd0: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8];
+            main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip112 <= 8'd0;
-    case (a7ddrphy_bitslip11_value1)
+    main_a7ddrphy_bitslip112 <= 8'd0;
+    case (main_a7ddrphy_bitslip11_value1)
         1'd0: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8];
+            main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip120 <= 8'd0;
-    case (a7ddrphy_bitslip12_value0)
+    main_a7ddrphy_bitslip120 <= 8'd0;
+    case (main_a7ddrphy_bitslip12_value0)
         1'd0: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8];
+            main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip122 <= 8'd0;
-    case (a7ddrphy_bitslip12_value1)
+    main_a7ddrphy_bitslip122 <= 8'd0;
+    case (main_a7ddrphy_bitslip12_value1)
         1'd0: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8];
+            main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip130 <= 8'd0;
-    case (a7ddrphy_bitslip13_value0)
+    main_a7ddrphy_bitslip130 <= 8'd0;
+    case (main_a7ddrphy_bitslip13_value0)
         1'd0: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8];
+            main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip132 <= 8'd0;
-    case (a7ddrphy_bitslip13_value1)
+    main_a7ddrphy_bitslip132 <= 8'd0;
+    case (main_a7ddrphy_bitslip13_value1)
         1'd0: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8];
+            main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip140 <= 8'd0;
-    case (a7ddrphy_bitslip14_value0)
+    main_a7ddrphy_bitslip140 <= 8'd0;
+    case (main_a7ddrphy_bitslip14_value0)
         1'd0: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8];
+            main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip142 <= 8'd0;
-    case (a7ddrphy_bitslip14_value1)
+    main_a7ddrphy_bitslip142 <= 8'd0;
+    case (main_a7ddrphy_bitslip14_value1)
         1'd0: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8];
+            main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip150 <= 8'd0;
-    case (a7ddrphy_bitslip15_value0)
+    main_a7ddrphy_bitslip150 <= 8'd0;
+    case (main_a7ddrphy_bitslip15_value0)
         1'd0: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[8:1];
         end
         1'd1: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[9:2];
         end
         2'd2: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[10:3];
         end
         2'd3: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[11:4];
         end
         3'd4: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[12:5];
         end
         3'd5: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[13:6];
         end
         3'd6: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[14:7];
         end
         3'd7: begin
-            a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8];
+            main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[15:8];
         end
     endcase
 end
 always @(*) begin
-    a7ddrphy_bitslip152 <= 8'd0;
-    case (a7ddrphy_bitslip15_value1)
+    main_a7ddrphy_bitslip152 <= 8'd0;
+    case (main_a7ddrphy_bitslip15_value1)
         1'd0: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1];
-        end
-        1'd1: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2];
-        end
-        2'd2: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3];
-        end
-        2'd3: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4];
-        end
-        3'd4: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5];
-        end
-        3'd5: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6];
-        end
-        3'd6: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7];
-        end
-        3'd7: begin
-            a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8];
-        end
-    endcase
-end
-assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address;
-assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
-assign a7ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n;
-assign a7ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n;
-assign a7ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n;
-assign a7ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n;
-assign a7ddrphy_dfi_p0_cke = litedramcore_master_p0_cke;
-assign a7ddrphy_dfi_p0_odt = litedramcore_master_p0_odt;
-assign a7ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n;
-assign a7ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n;
-assign a7ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata;
-assign a7ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en;
-assign a7ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask;
-assign a7ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en;
-assign litedramcore_master_p0_rddata = a7ddrphy_dfi_p0_rddata;
-assign litedramcore_master_p0_rddata_valid = a7ddrphy_dfi_p0_rddata_valid;
-assign a7ddrphy_dfi_p1_address = litedramcore_master_p1_address;
-assign a7ddrphy_dfi_p1_bank = litedramcore_master_p1_bank;
-assign a7ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n;
-assign a7ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n;
-assign a7ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n;
-assign a7ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n;
-assign a7ddrphy_dfi_p1_cke = litedramcore_master_p1_cke;
-assign a7ddrphy_dfi_p1_odt = litedramcore_master_p1_odt;
-assign a7ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n;
-assign a7ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n;
-assign a7ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata;
-assign a7ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en;
-assign a7ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask;
-assign a7ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en;
-assign litedramcore_master_p1_rddata = a7ddrphy_dfi_p1_rddata;
-assign litedramcore_master_p1_rddata_valid = a7ddrphy_dfi_p1_rddata_valid;
-assign a7ddrphy_dfi_p2_address = litedramcore_master_p2_address;
-assign a7ddrphy_dfi_p2_bank = litedramcore_master_p2_bank;
-assign a7ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n;
-assign a7ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n;
-assign a7ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n;
-assign a7ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n;
-assign a7ddrphy_dfi_p2_cke = litedramcore_master_p2_cke;
-assign a7ddrphy_dfi_p2_odt = litedramcore_master_p2_odt;
-assign a7ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n;
-assign a7ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n;
-assign a7ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata;
-assign a7ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en;
-assign a7ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask;
-assign a7ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en;
-assign litedramcore_master_p2_rddata = a7ddrphy_dfi_p2_rddata;
-assign litedramcore_master_p2_rddata_valid = a7ddrphy_dfi_p2_rddata_valid;
-assign a7ddrphy_dfi_p3_address = litedramcore_master_p3_address;
-assign a7ddrphy_dfi_p3_bank = litedramcore_master_p3_bank;
-assign a7ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n;
-assign a7ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n;
-assign a7ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n;
-assign a7ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n;
-assign a7ddrphy_dfi_p3_cke = litedramcore_master_p3_cke;
-assign a7ddrphy_dfi_p3_odt = litedramcore_master_p3_odt;
-assign a7ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n;
-assign a7ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n;
-assign a7ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata;
-assign a7ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en;
-assign a7ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask;
-assign a7ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en;
-assign litedramcore_master_p3_rddata = a7ddrphy_dfi_p3_rddata;
-assign litedramcore_master_p3_rddata_valid = a7ddrphy_dfi_p3_rddata_valid;
-assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address;
-assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank;
-assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n;
-assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n;
-assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n;
-assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n;
-assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke;
-assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt;
-assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n;
-assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n;
-assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata;
-assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en;
-assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask;
-assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en;
-assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata;
-assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid;
-assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address;
-assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank;
-assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n;
-assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n;
-assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n;
-assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n;
-assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke;
-assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt;
-assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n;
-assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n;
-assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata;
-assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en;
-assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask;
-assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en;
-assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata;
-assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid;
-assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address;
-assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank;
-assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n;
-assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n;
-assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n;
-assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n;
-assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke;
-assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt;
-assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n;
-assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n;
-assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata;
-assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en;
-assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask;
-assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en;
-assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata;
-assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid;
-assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address;
-assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank;
-assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n;
-assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n;
-assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n;
-assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n;
-assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke;
-assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt;
-assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n;
-assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n;
-assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata;
-assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en;
-assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask;
-assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en;
-assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
-assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;
-always @(*) begin
-    litedramcore_csr_dfi_p0_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-    end else begin
-        litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata;
-    end
-end
-always @(*) begin
-    litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-    end else begin
-        litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
-    end
-end
-always @(*) begin
-    litedramcore_csr_dfi_p1_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-    end else begin
-        litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
-    end
-end
-always @(*) begin
-    litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-    end else begin
-        litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[8:1];
+        end
+        1'd1: begin
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[9:2];
+        end
+        2'd2: begin
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[10:3];
+        end
+        2'd3: begin
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[11:4];
+        end
+        3'd4: begin
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[12:5];
+        end
+        3'd5: begin
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[13:6];
+        end
+        3'd6: begin
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[14:7];
+        end
+        3'd7: begin
+            main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[15:8];
+        end
+    endcase
+end
+assign main_a7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address;
+assign main_a7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank;
+assign main_a7ddrphy_dfi_p0_cas_n = main_litedramcore_master_p0_cas_n;
+assign main_a7ddrphy_dfi_p0_cs_n = main_litedramcore_master_p0_cs_n;
+assign main_a7ddrphy_dfi_p0_ras_n = main_litedramcore_master_p0_ras_n;
+assign main_a7ddrphy_dfi_p0_we_n = main_litedramcore_master_p0_we_n;
+assign main_a7ddrphy_dfi_p0_cke = main_litedramcore_master_p0_cke;
+assign main_a7ddrphy_dfi_p0_odt = main_litedramcore_master_p0_odt;
+assign main_a7ddrphy_dfi_p0_reset_n = main_litedramcore_master_p0_reset_n;
+assign main_a7ddrphy_dfi_p0_act_n = main_litedramcore_master_p0_act_n;
+assign main_a7ddrphy_dfi_p0_wrdata = main_litedramcore_master_p0_wrdata;
+assign main_a7ddrphy_dfi_p0_wrdata_en = main_litedramcore_master_p0_wrdata_en;
+assign main_a7ddrphy_dfi_p0_wrdata_mask = main_litedramcore_master_p0_wrdata_mask;
+assign main_a7ddrphy_dfi_p0_rddata_en = main_litedramcore_master_p0_rddata_en;
+assign main_litedramcore_master_p0_rddata = main_a7ddrphy_dfi_p0_rddata;
+assign main_litedramcore_master_p0_rddata_valid = main_a7ddrphy_dfi_p0_rddata_valid;
+assign main_a7ddrphy_dfi_p1_address = main_litedramcore_master_p1_address;
+assign main_a7ddrphy_dfi_p1_bank = main_litedramcore_master_p1_bank;
+assign main_a7ddrphy_dfi_p1_cas_n = main_litedramcore_master_p1_cas_n;
+assign main_a7ddrphy_dfi_p1_cs_n = main_litedramcore_master_p1_cs_n;
+assign main_a7ddrphy_dfi_p1_ras_n = main_litedramcore_master_p1_ras_n;
+assign main_a7ddrphy_dfi_p1_we_n = main_litedramcore_master_p1_we_n;
+assign main_a7ddrphy_dfi_p1_cke = main_litedramcore_master_p1_cke;
+assign main_a7ddrphy_dfi_p1_odt = main_litedramcore_master_p1_odt;
+assign main_a7ddrphy_dfi_p1_reset_n = main_litedramcore_master_p1_reset_n;
+assign main_a7ddrphy_dfi_p1_act_n = main_litedramcore_master_p1_act_n;
+assign main_a7ddrphy_dfi_p1_wrdata = main_litedramcore_master_p1_wrdata;
+assign main_a7ddrphy_dfi_p1_wrdata_en = main_litedramcore_master_p1_wrdata_en;
+assign main_a7ddrphy_dfi_p1_wrdata_mask = main_litedramcore_master_p1_wrdata_mask;
+assign main_a7ddrphy_dfi_p1_rddata_en = main_litedramcore_master_p1_rddata_en;
+assign main_litedramcore_master_p1_rddata = main_a7ddrphy_dfi_p1_rddata;
+assign main_litedramcore_master_p1_rddata_valid = main_a7ddrphy_dfi_p1_rddata_valid;
+assign main_a7ddrphy_dfi_p2_address = main_litedramcore_master_p2_address;
+assign main_a7ddrphy_dfi_p2_bank = main_litedramcore_master_p2_bank;
+assign main_a7ddrphy_dfi_p2_cas_n = main_litedramcore_master_p2_cas_n;
+assign main_a7ddrphy_dfi_p2_cs_n = main_litedramcore_master_p2_cs_n;
+assign main_a7ddrphy_dfi_p2_ras_n = main_litedramcore_master_p2_ras_n;
+assign main_a7ddrphy_dfi_p2_we_n = main_litedramcore_master_p2_we_n;
+assign main_a7ddrphy_dfi_p2_cke = main_litedramcore_master_p2_cke;
+assign main_a7ddrphy_dfi_p2_odt = main_litedramcore_master_p2_odt;
+assign main_a7ddrphy_dfi_p2_reset_n = main_litedramcore_master_p2_reset_n;
+assign main_a7ddrphy_dfi_p2_act_n = main_litedramcore_master_p2_act_n;
+assign main_a7ddrphy_dfi_p2_wrdata = main_litedramcore_master_p2_wrdata;
+assign main_a7ddrphy_dfi_p2_wrdata_en = main_litedramcore_master_p2_wrdata_en;
+assign main_a7ddrphy_dfi_p2_wrdata_mask = main_litedramcore_master_p2_wrdata_mask;
+assign main_a7ddrphy_dfi_p2_rddata_en = main_litedramcore_master_p2_rddata_en;
+assign main_litedramcore_master_p2_rddata = main_a7ddrphy_dfi_p2_rddata;
+assign main_litedramcore_master_p2_rddata_valid = main_a7ddrphy_dfi_p2_rddata_valid;
+assign main_a7ddrphy_dfi_p3_address = main_litedramcore_master_p3_address;
+assign main_a7ddrphy_dfi_p3_bank = main_litedramcore_master_p3_bank;
+assign main_a7ddrphy_dfi_p3_cas_n = main_litedramcore_master_p3_cas_n;
+assign main_a7ddrphy_dfi_p3_cs_n = main_litedramcore_master_p3_cs_n;
+assign main_a7ddrphy_dfi_p3_ras_n = main_litedramcore_master_p3_ras_n;
+assign main_a7ddrphy_dfi_p3_we_n = main_litedramcore_master_p3_we_n;
+assign main_a7ddrphy_dfi_p3_cke = main_litedramcore_master_p3_cke;
+assign main_a7ddrphy_dfi_p3_odt = main_litedramcore_master_p3_odt;
+assign main_a7ddrphy_dfi_p3_reset_n = main_litedramcore_master_p3_reset_n;
+assign main_a7ddrphy_dfi_p3_act_n = main_litedramcore_master_p3_act_n;
+assign main_a7ddrphy_dfi_p3_wrdata = main_litedramcore_master_p3_wrdata;
+assign main_a7ddrphy_dfi_p3_wrdata_en = main_litedramcore_master_p3_wrdata_en;
+assign main_a7ddrphy_dfi_p3_wrdata_mask = main_litedramcore_master_p3_wrdata_mask;
+assign main_a7ddrphy_dfi_p3_rddata_en = main_litedramcore_master_p3_rddata_en;
+assign main_litedramcore_master_p3_rddata = main_a7ddrphy_dfi_p3_rddata;
+assign main_litedramcore_master_p3_rddata_valid = main_a7ddrphy_dfi_p3_rddata_valid;
+assign main_litedramcore_slave_p0_address = main_litedramcore_dfi_p0_address;
+assign main_litedramcore_slave_p0_bank = main_litedramcore_dfi_p0_bank;
+assign main_litedramcore_slave_p0_cas_n = main_litedramcore_dfi_p0_cas_n;
+assign main_litedramcore_slave_p0_cs_n = main_litedramcore_dfi_p0_cs_n;
+assign main_litedramcore_slave_p0_ras_n = main_litedramcore_dfi_p0_ras_n;
+assign main_litedramcore_slave_p0_we_n = main_litedramcore_dfi_p0_we_n;
+assign main_litedramcore_slave_p0_cke = main_litedramcore_dfi_p0_cke;
+assign main_litedramcore_slave_p0_odt = main_litedramcore_dfi_p0_odt;
+assign main_litedramcore_slave_p0_reset_n = main_litedramcore_dfi_p0_reset_n;
+assign main_litedramcore_slave_p0_act_n = main_litedramcore_dfi_p0_act_n;
+assign main_litedramcore_slave_p0_wrdata = main_litedramcore_dfi_p0_wrdata;
+assign main_litedramcore_slave_p0_wrdata_en = main_litedramcore_dfi_p0_wrdata_en;
+assign main_litedramcore_slave_p0_wrdata_mask = main_litedramcore_dfi_p0_wrdata_mask;
+assign main_litedramcore_slave_p0_rddata_en = main_litedramcore_dfi_p0_rddata_en;
+assign main_litedramcore_dfi_p0_rddata = main_litedramcore_slave_p0_rddata;
+assign main_litedramcore_dfi_p0_rddata_valid = main_litedramcore_slave_p0_rddata_valid;
+assign main_litedramcore_slave_p1_address = main_litedramcore_dfi_p1_address;
+assign main_litedramcore_slave_p1_bank = main_litedramcore_dfi_p1_bank;
+assign main_litedramcore_slave_p1_cas_n = main_litedramcore_dfi_p1_cas_n;
+assign main_litedramcore_slave_p1_cs_n = main_litedramcore_dfi_p1_cs_n;
+assign main_litedramcore_slave_p1_ras_n = main_litedramcore_dfi_p1_ras_n;
+assign main_litedramcore_slave_p1_we_n = main_litedramcore_dfi_p1_we_n;
+assign main_litedramcore_slave_p1_cke = main_litedramcore_dfi_p1_cke;
+assign main_litedramcore_slave_p1_odt = main_litedramcore_dfi_p1_odt;
+assign main_litedramcore_slave_p1_reset_n = main_litedramcore_dfi_p1_reset_n;
+assign main_litedramcore_slave_p1_act_n = main_litedramcore_dfi_p1_act_n;
+assign main_litedramcore_slave_p1_wrdata = main_litedramcore_dfi_p1_wrdata;
+assign main_litedramcore_slave_p1_wrdata_en = main_litedramcore_dfi_p1_wrdata_en;
+assign main_litedramcore_slave_p1_wrdata_mask = main_litedramcore_dfi_p1_wrdata_mask;
+assign main_litedramcore_slave_p1_rddata_en = main_litedramcore_dfi_p1_rddata_en;
+assign main_litedramcore_dfi_p1_rddata = main_litedramcore_slave_p1_rddata;
+assign main_litedramcore_dfi_p1_rddata_valid = main_litedramcore_slave_p1_rddata_valid;
+assign main_litedramcore_slave_p2_address = main_litedramcore_dfi_p2_address;
+assign main_litedramcore_slave_p2_bank = main_litedramcore_dfi_p2_bank;
+assign main_litedramcore_slave_p2_cas_n = main_litedramcore_dfi_p2_cas_n;
+assign main_litedramcore_slave_p2_cs_n = main_litedramcore_dfi_p2_cs_n;
+assign main_litedramcore_slave_p2_ras_n = main_litedramcore_dfi_p2_ras_n;
+assign main_litedramcore_slave_p2_we_n = main_litedramcore_dfi_p2_we_n;
+assign main_litedramcore_slave_p2_cke = main_litedramcore_dfi_p2_cke;
+assign main_litedramcore_slave_p2_odt = main_litedramcore_dfi_p2_odt;
+assign main_litedramcore_slave_p2_reset_n = main_litedramcore_dfi_p2_reset_n;
+assign main_litedramcore_slave_p2_act_n = main_litedramcore_dfi_p2_act_n;
+assign main_litedramcore_slave_p2_wrdata = main_litedramcore_dfi_p2_wrdata;
+assign main_litedramcore_slave_p2_wrdata_en = main_litedramcore_dfi_p2_wrdata_en;
+assign main_litedramcore_slave_p2_wrdata_mask = main_litedramcore_dfi_p2_wrdata_mask;
+assign main_litedramcore_slave_p2_rddata_en = main_litedramcore_dfi_p2_rddata_en;
+assign main_litedramcore_dfi_p2_rddata = main_litedramcore_slave_p2_rddata;
+assign main_litedramcore_dfi_p2_rddata_valid = main_litedramcore_slave_p2_rddata_valid;
+assign main_litedramcore_slave_p3_address = main_litedramcore_dfi_p3_address;
+assign main_litedramcore_slave_p3_bank = main_litedramcore_dfi_p3_bank;
+assign main_litedramcore_slave_p3_cas_n = main_litedramcore_dfi_p3_cas_n;
+assign main_litedramcore_slave_p3_cs_n = main_litedramcore_dfi_p3_cs_n;
+assign main_litedramcore_slave_p3_ras_n = main_litedramcore_dfi_p3_ras_n;
+assign main_litedramcore_slave_p3_we_n = main_litedramcore_dfi_p3_we_n;
+assign main_litedramcore_slave_p3_cke = main_litedramcore_dfi_p3_cke;
+assign main_litedramcore_slave_p3_odt = main_litedramcore_dfi_p3_odt;
+assign main_litedramcore_slave_p3_reset_n = main_litedramcore_dfi_p3_reset_n;
+assign main_litedramcore_slave_p3_act_n = main_litedramcore_dfi_p3_act_n;
+assign main_litedramcore_slave_p3_wrdata = main_litedramcore_dfi_p3_wrdata;
+assign main_litedramcore_slave_p3_wrdata_en = main_litedramcore_dfi_p3_wrdata_en;
+assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_mask;
+assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en;
+assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata;
+assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid;
+always @(*) begin
+    main_litedramcore_csr_dfi_p0_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+    end else begin
+        main_litedramcore_csr_dfi_p0_rddata <= main_litedramcore_master_p0_rddata;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p2_rddata <= 32'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata;
+        main_litedramcore_csr_dfi_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p1_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+        main_litedramcore_csr_dfi_p1_rddata <= main_litedramcore_master_p1_rddata;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p3_rddata <= 32'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata;
+        main_litedramcore_csr_dfi_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
+    main_litedramcore_csr_dfi_p2_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
     end else begin
-        litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+        main_litedramcore_csr_dfi_p2_rddata <= main_litedramcore_master_p2_rddata;
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p0_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata;
-        end else begin
-        end
+    main_litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+    end else begin
+        main_litedramcore_csr_dfi_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
+    end
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p3_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
     end else begin
+        main_litedramcore_csr_dfi_p3_rddata <= main_litedramcore_master_p3_rddata;
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+    main_litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+    end else begin
+        main_litedramcore_csr_dfi_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
+    end
+end
+always @(*) begin
+    main_litedramcore_ext_dfi_p0_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p0_rddata <= main_litedramcore_master_p0_rddata;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p1_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+    main_litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+    main_litedramcore_ext_dfi_p1_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p1_rddata <= main_litedramcore_master_p1_rddata;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p2_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata;
+    main_litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+    main_litedramcore_ext_dfi_p2_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p2_rddata <= main_litedramcore_master_p2_rddata;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p0_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
         end else begin
-            litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p0_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p0_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+            main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p3_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata;
+    main_litedramcore_slave_p0_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
+            main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+    main_litedramcore_ext_dfi_p3_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p3_rddata <= main_litedramcore_master_p3_rddata;
         end else begin
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p1_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_ext_dfi_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
         end else begin
-            litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p1_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p1_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+            main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p2_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p1_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
+            main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p2_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p2_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+            main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p3_rddata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p2_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
+            main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_slave_p3_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
+    main_litedramcore_slave_p3_rddata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+            main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata;
         end
     end else begin
     end
 end
 always @(*) begin
-    litedramcore_master_p0_address <= 14'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address;
+    main_litedramcore_slave_p3_rddata_valid <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
         end else begin
-            litedramcore_master_p0_address <= litedramcore_slave_p0_address;
+            main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
         end
     end else begin
-        litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_bank <= 3'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank;
+    main_litedramcore_master_p0_address <= 14'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_address <= main_litedramcore_ext_dfi_p0_address;
         end else begin
-            litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
+            main_litedramcore_master_p0_address <= main_litedramcore_slave_p0_address;
         end
     end else begin
-        litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank;
+        main_litedramcore_master_p0_address <= main_litedramcore_csr_dfi_p0_address;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_cas_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n;
+    main_litedramcore_master_p0_bank <= 3'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_bank <= main_litedramcore_ext_dfi_p0_bank;
         end else begin
-            litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
+            main_litedramcore_master_p0_bank <= main_litedramcore_slave_p0_bank;
         end
     end else begin
-        litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n;
+        main_litedramcore_master_p0_bank <= main_litedramcore_csr_dfi_p0_bank;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_cs_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
+    main_litedramcore_master_p0_cas_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_cas_n <= main_litedramcore_ext_dfi_p0_cas_n;
         end else begin
-            litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+            main_litedramcore_master_p0_cas_n <= main_litedramcore_slave_p0_cas_n;
         end
     end else begin
-        litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
+        main_litedramcore_master_p0_cas_n <= main_litedramcore_csr_dfi_p0_cas_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_ras_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
+    main_litedramcore_master_p0_cs_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_cs_n <= main_litedramcore_ext_dfi_p0_cs_n;
         end else begin
-            litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+            main_litedramcore_master_p0_cs_n <= main_litedramcore_slave_p0_cs_n;
+            if (1'd0) begin
+                main_litedramcore_master_p0_cs_n <= {2{main_litedramcore_slave_p0_cs_n}};
+            end
         end
     end else begin
-        litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
+        main_litedramcore_master_p0_cs_n <= main_litedramcore_csr_dfi_p0_cs_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_we_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
+    main_litedramcore_master_p0_ras_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_ras_n <= main_litedramcore_ext_dfi_p0_ras_n;
         end else begin
-            litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+            main_litedramcore_master_p0_ras_n <= main_litedramcore_slave_p0_ras_n;
         end
     end else begin
-        litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
+        main_litedramcore_master_p0_ras_n <= main_litedramcore_csr_dfi_p0_ras_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_cke <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke;
+    main_litedramcore_master_p0_we_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_we_n <= main_litedramcore_ext_dfi_p0_we_n;
         end else begin
-            litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
+            main_litedramcore_master_p0_we_n <= main_litedramcore_slave_p0_we_n;
         end
     end else begin
-        litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke;
+        main_litedramcore_master_p0_we_n <= main_litedramcore_csr_dfi_p0_we_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_odt <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt;
+    main_litedramcore_master_p0_cke <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_cke <= main_litedramcore_ext_dfi_p0_cke;
         end else begin
-            litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
+            main_litedramcore_master_p0_cke <= main_litedramcore_slave_p0_cke;
         end
     end else begin
-        litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt;
+        main_litedramcore_master_p0_cke <= main_litedramcore_csr_dfi_p0_cke;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_reset_n <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n;
+    main_litedramcore_master_p0_odt <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_odt <= main_litedramcore_ext_dfi_p0_odt;
         end else begin
-            litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
+            main_litedramcore_master_p0_odt <= main_litedramcore_slave_p0_odt;
         end
     end else begin
-        litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n;
+        main_litedramcore_master_p0_odt <= main_litedramcore_csr_dfi_p0_odt;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_act_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n;
+    main_litedramcore_master_p0_reset_n <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_reset_n <= main_litedramcore_ext_dfi_p0_reset_n;
         end else begin
-            litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
+            main_litedramcore_master_p0_reset_n <= main_litedramcore_slave_p0_reset_n;
         end
     end else begin
-        litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n;
+        main_litedramcore_master_p0_reset_n <= main_litedramcore_csr_dfi_p0_reset_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_wrdata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata;
+    main_litedramcore_master_p0_act_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_act_n <= main_litedramcore_ext_dfi_p0_act_n;
         end else begin
-            litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
+            main_litedramcore_master_p0_act_n <= main_litedramcore_slave_p0_act_n;
         end
     end else begin
-        litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata;
+        main_litedramcore_master_p0_act_n <= main_litedramcore_csr_dfi_p0_act_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_wrdata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en;
+    main_litedramcore_master_p0_wrdata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_wrdata <= main_litedramcore_ext_dfi_p0_wrdata;
         end else begin
-            litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
+            main_litedramcore_master_p0_wrdata <= main_litedramcore_slave_p0_wrdata;
         end
     end else begin
-        litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en;
+        main_litedramcore_master_p0_wrdata <= main_litedramcore_csr_dfi_p0_wrdata;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_wrdata_mask <= 4'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask;
+    main_litedramcore_master_p0_wrdata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_wrdata_en <= main_litedramcore_ext_dfi_p0_wrdata_en;
         end else begin
-            litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
+            main_litedramcore_master_p0_wrdata_en <= main_litedramcore_slave_p0_wrdata_en;
         end
     end else begin
-        litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask;
+        main_litedramcore_master_p0_wrdata_en <= main_litedramcore_csr_dfi_p0_wrdata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p0_rddata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en;
+    main_litedramcore_master_p0_wrdata_mask <= 4'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_ext_dfi_p0_wrdata_mask;
         end else begin
-            litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
+            main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_slave_p0_wrdata_mask;
         end
     end else begin
-        litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en;
+        main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_csr_dfi_p0_wrdata_mask;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_address <= 14'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address;
+    main_litedramcore_master_p0_rddata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p0_rddata_en <= main_litedramcore_ext_dfi_p0_rddata_en;
         end else begin
-            litedramcore_master_p1_address <= litedramcore_slave_p1_address;
+            main_litedramcore_master_p0_rddata_en <= main_litedramcore_slave_p0_rddata_en;
         end
     end else begin
-        litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address;
+        main_litedramcore_master_p0_rddata_en <= main_litedramcore_csr_dfi_p0_rddata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_bank <= 3'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank;
+    main_litedramcore_master_p1_address <= 14'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_address <= main_litedramcore_ext_dfi_p1_address;
         end else begin
-            litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
+            main_litedramcore_master_p1_address <= main_litedramcore_slave_p1_address;
         end
     end else begin
-        litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank;
+        main_litedramcore_master_p1_address <= main_litedramcore_csr_dfi_p1_address;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_cas_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n;
+    main_litedramcore_master_p1_bank <= 3'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_bank <= main_litedramcore_ext_dfi_p1_bank;
         end else begin
-            litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
+            main_litedramcore_master_p1_bank <= main_litedramcore_slave_p1_bank;
         end
     end else begin
-        litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n;
+        main_litedramcore_master_p1_bank <= main_litedramcore_csr_dfi_p1_bank;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_cs_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n;
+    main_litedramcore_master_p1_cas_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_cas_n <= main_litedramcore_ext_dfi_p1_cas_n;
         end else begin
-            litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
+            main_litedramcore_master_p1_cas_n <= main_litedramcore_slave_p1_cas_n;
         end
     end else begin
-        litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n;
+        main_litedramcore_master_p1_cas_n <= main_litedramcore_csr_dfi_p1_cas_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_ras_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n;
+    main_litedramcore_master_p1_cs_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_cs_n <= main_litedramcore_ext_dfi_p1_cs_n;
         end else begin
-            litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
+            main_litedramcore_master_p1_cs_n <= main_litedramcore_slave_p1_cs_n;
+            if (1'd0) begin
+                main_litedramcore_master_p1_cs_n <= {2{main_litedramcore_slave_p1_cs_n}};
+            end
         end
     end else begin
-        litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n;
+        main_litedramcore_master_p1_cs_n <= main_litedramcore_csr_dfi_p1_cs_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_we_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n;
+    main_litedramcore_master_p1_ras_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_ras_n <= main_litedramcore_ext_dfi_p1_ras_n;
         end else begin
-            litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
+            main_litedramcore_master_p1_ras_n <= main_litedramcore_slave_p1_ras_n;
         end
     end else begin
-        litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n;
+        main_litedramcore_master_p1_ras_n <= main_litedramcore_csr_dfi_p1_ras_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_cke <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke;
+    main_litedramcore_master_p1_we_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_we_n <= main_litedramcore_ext_dfi_p1_we_n;
         end else begin
-            litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
+            main_litedramcore_master_p1_we_n <= main_litedramcore_slave_p1_we_n;
         end
     end else begin
-        litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke;
+        main_litedramcore_master_p1_we_n <= main_litedramcore_csr_dfi_p1_we_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_odt <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt;
+    main_litedramcore_master_p1_cke <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_cke <= main_litedramcore_ext_dfi_p1_cke;
         end else begin
-            litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
+            main_litedramcore_master_p1_cke <= main_litedramcore_slave_p1_cke;
         end
     end else begin
-        litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt;
+        main_litedramcore_master_p1_cke <= main_litedramcore_csr_dfi_p1_cke;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_reset_n <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n;
+    main_litedramcore_master_p1_odt <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_odt <= main_litedramcore_ext_dfi_p1_odt;
         end else begin
-            litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+            main_litedramcore_master_p1_odt <= main_litedramcore_slave_p1_odt;
         end
     end else begin
-        litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n;
+        main_litedramcore_master_p1_odt <= main_litedramcore_csr_dfi_p1_odt;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_act_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n;
+    main_litedramcore_master_p1_reset_n <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_reset_n <= main_litedramcore_ext_dfi_p1_reset_n;
         end else begin
-            litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
+            main_litedramcore_master_p1_reset_n <= main_litedramcore_slave_p1_reset_n;
         end
     end else begin
-        litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n;
+        main_litedramcore_master_p1_reset_n <= main_litedramcore_csr_dfi_p1_reset_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_wrdata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata;
+    main_litedramcore_master_p1_act_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_act_n <= main_litedramcore_ext_dfi_p1_act_n;
         end else begin
-            litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
+            main_litedramcore_master_p1_act_n <= main_litedramcore_slave_p1_act_n;
         end
     end else begin
-        litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata;
+        main_litedramcore_master_p1_act_n <= main_litedramcore_csr_dfi_p1_act_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_wrdata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en;
+    main_litedramcore_master_p1_wrdata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_wrdata <= main_litedramcore_ext_dfi_p1_wrdata;
         end else begin
-            litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
+            main_litedramcore_master_p1_wrdata <= main_litedramcore_slave_p1_wrdata;
         end
     end else begin
-        litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en;
+        main_litedramcore_master_p1_wrdata <= main_litedramcore_csr_dfi_p1_wrdata;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_wrdata_mask <= 4'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask;
+    main_litedramcore_master_p1_wrdata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_wrdata_en <= main_litedramcore_ext_dfi_p1_wrdata_en;
         end else begin
-            litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
+            main_litedramcore_master_p1_wrdata_en <= main_litedramcore_slave_p1_wrdata_en;
         end
     end else begin
-        litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask;
+        main_litedramcore_master_p1_wrdata_en <= main_litedramcore_csr_dfi_p1_wrdata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p1_rddata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en;
+    main_litedramcore_master_p1_wrdata_mask <= 4'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_ext_dfi_p1_wrdata_mask;
         end else begin
-            litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
+            main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_slave_p1_wrdata_mask;
         end
     end else begin
-        litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en;
+        main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_csr_dfi_p1_wrdata_mask;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_address <= 14'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address;
+    main_litedramcore_master_p1_rddata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p1_rddata_en <= main_litedramcore_ext_dfi_p1_rddata_en;
         end else begin
-            litedramcore_master_p2_address <= litedramcore_slave_p2_address;
+            main_litedramcore_master_p1_rddata_en <= main_litedramcore_slave_p1_rddata_en;
         end
     end else begin
-        litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address;
+        main_litedramcore_master_p1_rddata_en <= main_litedramcore_csr_dfi_p1_rddata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_bank <= 3'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank;
+    main_litedramcore_master_p2_address <= 14'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_address <= main_litedramcore_ext_dfi_p2_address;
         end else begin
-            litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
+            main_litedramcore_master_p2_address <= main_litedramcore_slave_p2_address;
         end
     end else begin
-        litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank;
+        main_litedramcore_master_p2_address <= main_litedramcore_csr_dfi_p2_address;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_cas_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n;
+    main_litedramcore_master_p2_bank <= 3'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_bank <= main_litedramcore_ext_dfi_p2_bank;
         end else begin
-            litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
+            main_litedramcore_master_p2_bank <= main_litedramcore_slave_p2_bank;
         end
     end else begin
-        litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n;
+        main_litedramcore_master_p2_bank <= main_litedramcore_csr_dfi_p2_bank;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_cs_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n;
+    main_litedramcore_master_p2_cas_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_cas_n <= main_litedramcore_ext_dfi_p2_cas_n;
         end else begin
-            litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
+            main_litedramcore_master_p2_cas_n <= main_litedramcore_slave_p2_cas_n;
         end
     end else begin
-        litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n;
+        main_litedramcore_master_p2_cas_n <= main_litedramcore_csr_dfi_p2_cas_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_ras_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n;
+    main_litedramcore_master_p2_cs_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_cs_n <= main_litedramcore_ext_dfi_p2_cs_n;
         end else begin
-            litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
+            main_litedramcore_master_p2_cs_n <= main_litedramcore_slave_p2_cs_n;
+            if (1'd0) begin
+                main_litedramcore_master_p2_cs_n <= {2{main_litedramcore_slave_p2_cs_n}};
+            end
         end
     end else begin
-        litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n;
+        main_litedramcore_master_p2_cs_n <= main_litedramcore_csr_dfi_p2_cs_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_we_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n;
+    main_litedramcore_master_p2_ras_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_ras_n <= main_litedramcore_ext_dfi_p2_ras_n;
         end else begin
-            litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
+            main_litedramcore_master_p2_ras_n <= main_litedramcore_slave_p2_ras_n;
         end
     end else begin
-        litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n;
+        main_litedramcore_master_p2_ras_n <= main_litedramcore_csr_dfi_p2_ras_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_cke <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke;
+    main_litedramcore_master_p2_we_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_we_n <= main_litedramcore_ext_dfi_p2_we_n;
         end else begin
-            litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
+            main_litedramcore_master_p2_we_n <= main_litedramcore_slave_p2_we_n;
         end
     end else begin
-        litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke;
+        main_litedramcore_master_p2_we_n <= main_litedramcore_csr_dfi_p2_we_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_odt <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt;
+    main_litedramcore_master_p2_cke <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_cke <= main_litedramcore_ext_dfi_p2_cke;
         end else begin
-            litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
+            main_litedramcore_master_p2_cke <= main_litedramcore_slave_p2_cke;
         end
     end else begin
-        litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt;
+        main_litedramcore_master_p2_cke <= main_litedramcore_csr_dfi_p2_cke;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_reset_n <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n;
+    main_litedramcore_master_p2_odt <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_odt <= main_litedramcore_ext_dfi_p2_odt;
         end else begin
-            litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
+            main_litedramcore_master_p2_odt <= main_litedramcore_slave_p2_odt;
         end
     end else begin
-        litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n;
+        main_litedramcore_master_p2_odt <= main_litedramcore_csr_dfi_p2_odt;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_act_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n;
+    main_litedramcore_master_p2_reset_n <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_reset_n <= main_litedramcore_ext_dfi_p2_reset_n;
         end else begin
-            litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
+            main_litedramcore_master_p2_reset_n <= main_litedramcore_slave_p2_reset_n;
         end
     end else begin
-        litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n;
+        main_litedramcore_master_p2_reset_n <= main_litedramcore_csr_dfi_p2_reset_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_wrdata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata;
+    main_litedramcore_master_p2_act_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_act_n <= main_litedramcore_ext_dfi_p2_act_n;
         end else begin
-            litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
+            main_litedramcore_master_p2_act_n <= main_litedramcore_slave_p2_act_n;
         end
     end else begin
-        litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata;
+        main_litedramcore_master_p2_act_n <= main_litedramcore_csr_dfi_p2_act_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_wrdata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en;
+    main_litedramcore_master_p2_wrdata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_wrdata <= main_litedramcore_ext_dfi_p2_wrdata;
         end else begin
-            litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
+            main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata;
         end
     end else begin
-        litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en;
+        main_litedramcore_master_p2_wrdata <= main_litedramcore_csr_dfi_p2_wrdata;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_wrdata_mask <= 4'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask;
+    main_litedramcore_master_p2_wrdata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_wrdata_en <= main_litedramcore_ext_dfi_p2_wrdata_en;
         end else begin
-            litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
+            main_litedramcore_master_p2_wrdata_en <= main_litedramcore_slave_p2_wrdata_en;
         end
     end else begin
-        litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask;
+        main_litedramcore_master_p2_wrdata_en <= main_litedramcore_csr_dfi_p2_wrdata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p2_rddata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en;
+    main_litedramcore_master_p2_wrdata_mask <= 4'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_ext_dfi_p2_wrdata_mask;
         end else begin
-            litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
+            main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_slave_p2_wrdata_mask;
         end
     end else begin
-        litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en;
+        main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_csr_dfi_p2_wrdata_mask;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_address <= 14'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address;
+    main_litedramcore_master_p2_rddata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p2_rddata_en <= main_litedramcore_ext_dfi_p2_rddata_en;
         end else begin
-            litedramcore_master_p3_address <= litedramcore_slave_p3_address;
+            main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en;
         end
     end else begin
-        litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address;
+        main_litedramcore_master_p2_rddata_en <= main_litedramcore_csr_dfi_p2_rddata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_bank <= 3'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank;
+    main_litedramcore_master_p3_address <= 14'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_address <= main_litedramcore_ext_dfi_p3_address;
         end else begin
-            litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
+            main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address;
         end
     end else begin
-        litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank;
+        main_litedramcore_master_p3_address <= main_litedramcore_csr_dfi_p3_address;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_cas_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n;
+    main_litedramcore_master_p3_bank <= 3'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_bank <= main_litedramcore_ext_dfi_p3_bank;
         end else begin
-            litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
+            main_litedramcore_master_p3_bank <= main_litedramcore_slave_p3_bank;
         end
     end else begin
-        litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n;
+        main_litedramcore_master_p3_bank <= main_litedramcore_csr_dfi_p3_bank;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_cs_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n;
+    main_litedramcore_master_p3_cas_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_cas_n <= main_litedramcore_ext_dfi_p3_cas_n;
         end else begin
-            litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
+            main_litedramcore_master_p3_cas_n <= main_litedramcore_slave_p3_cas_n;
         end
     end else begin
-        litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n;
+        main_litedramcore_master_p3_cas_n <= main_litedramcore_csr_dfi_p3_cas_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_ras_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n;
+    main_litedramcore_master_p3_cs_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_cs_n <= main_litedramcore_ext_dfi_p3_cs_n;
         end else begin
-            litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
+            main_litedramcore_master_p3_cs_n <= main_litedramcore_slave_p3_cs_n;
+            if (1'd0) begin
+                main_litedramcore_master_p3_cs_n <= {2{main_litedramcore_slave_p3_cs_n}};
+            end
         end
     end else begin
-        litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n;
+        main_litedramcore_master_p3_cs_n <= main_litedramcore_csr_dfi_p3_cs_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_we_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n;
+    main_litedramcore_master_p3_ras_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_ras_n <= main_litedramcore_ext_dfi_p3_ras_n;
         end else begin
-            litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
+            main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n;
         end
     end else begin
-        litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n;
+        main_litedramcore_master_p3_ras_n <= main_litedramcore_csr_dfi_p3_ras_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_cke <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke;
+    main_litedramcore_master_p3_we_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_we_n <= main_litedramcore_ext_dfi_p3_we_n;
         end else begin
-            litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
+            main_litedramcore_master_p3_we_n <= main_litedramcore_slave_p3_we_n;
         end
     end else begin
-        litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke;
+        main_litedramcore_master_p3_we_n <= main_litedramcore_csr_dfi_p3_we_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_odt <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt;
+    main_litedramcore_master_p3_cke <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_cke <= main_litedramcore_ext_dfi_p3_cke;
         end else begin
-            litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
+            main_litedramcore_master_p3_cke <= main_litedramcore_slave_p3_cke;
         end
     end else begin
-        litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt;
+        main_litedramcore_master_p3_cke <= main_litedramcore_csr_dfi_p3_cke;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_reset_n <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n;
+    main_litedramcore_master_p3_odt <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_odt <= main_litedramcore_ext_dfi_p3_odt;
         end else begin
-            litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
+            main_litedramcore_master_p3_odt <= main_litedramcore_slave_p3_odt;
         end
     end else begin
-        litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n;
+        main_litedramcore_master_p3_odt <= main_litedramcore_csr_dfi_p3_odt;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_act_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n;
+    main_litedramcore_master_p3_reset_n <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_reset_n <= main_litedramcore_ext_dfi_p3_reset_n;
         end else begin
-            litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
+            main_litedramcore_master_p3_reset_n <= main_litedramcore_slave_p3_reset_n;
         end
     end else begin
-        litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n;
+        main_litedramcore_master_p3_reset_n <= main_litedramcore_csr_dfi_p3_reset_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_wrdata <= 32'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata;
+    main_litedramcore_master_p3_act_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_act_n <= main_litedramcore_ext_dfi_p3_act_n;
         end else begin
-            litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
+            main_litedramcore_master_p3_act_n <= main_litedramcore_slave_p3_act_n;
         end
     end else begin
-        litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata;
+        main_litedramcore_master_p3_act_n <= main_litedramcore_csr_dfi_p3_act_n;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_wrdata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en;
+    main_litedramcore_master_p3_wrdata <= 32'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_wrdata <= main_litedramcore_ext_dfi_p3_wrdata;
         end else begin
-            litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
+            main_litedramcore_master_p3_wrdata <= main_litedramcore_slave_p3_wrdata;
         end
     end else begin
-        litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en;
+        main_litedramcore_master_p3_wrdata <= main_litedramcore_csr_dfi_p3_wrdata;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_wrdata_mask <= 4'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask;
+    main_litedramcore_master_p3_wrdata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_wrdata_en <= main_litedramcore_ext_dfi_p3_wrdata_en;
         end else begin
-            litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
+            main_litedramcore_master_p3_wrdata_en <= main_litedramcore_slave_p3_wrdata_en;
         end
     end else begin
-        litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask;
+        main_litedramcore_master_p3_wrdata_en <= main_litedramcore_csr_dfi_p3_wrdata_en;
     end
 end
 always @(*) begin
-    litedramcore_master_p3_rddata_en <= 1'd0;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en;
+    main_litedramcore_master_p3_wrdata_mask <= 4'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_ext_dfi_p3_wrdata_mask;
         end else begin
-            litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
+            main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_slave_p3_wrdata_mask;
         end
     end else begin
-        litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en;
+        main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_csr_dfi_p3_wrdata_mask;
     end
 end
-assign litedramcore_csr_dfi_p0_cke = litedramcore_cke;
-assign litedramcore_csr_dfi_p1_cke = litedramcore_cke;
-assign litedramcore_csr_dfi_p2_cke = litedramcore_cke;
-assign litedramcore_csr_dfi_p3_cke = litedramcore_cke;
-assign litedramcore_csr_dfi_p0_odt = litedramcore_odt;
-assign litedramcore_csr_dfi_p1_odt = litedramcore_odt;
-assign litedramcore_csr_dfi_p2_odt = litedramcore_odt;
-assign litedramcore_csr_dfi_p3_odt = litedramcore_odt;
-assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n;
-assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n;
-assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n;
-assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n;
 always @(*) begin
-    litedramcore_csr_dfi_p0_we_n <= 1'd1;
-    if (litedramcore_phaseinjector0_command_issue_re) begin
-        litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
+    main_litedramcore_master_p3_rddata_en <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_rddata_en <= main_litedramcore_ext_dfi_p3_rddata_en;
+        end else begin
+            main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en;
+        end
     end else begin
-        litedramcore_csr_dfi_p0_we_n <= 1'd1;
+        main_litedramcore_master_p3_rddata_en <= main_litedramcore_csr_dfi_p3_rddata_en;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p0_cas_n <= 1'd1;
-    if (litedramcore_phaseinjector0_command_issue_re) begin
-        litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas);
+    main_litedramcore_csr_dfi_p0_cke <= 1'd0;
+    main_litedramcore_csr_dfi_p0_cke <= main_litedramcore_cke;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p1_cke <= 1'd0;
+    main_litedramcore_csr_dfi_p1_cke <= main_litedramcore_cke;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p2_cke <= 1'd0;
+    main_litedramcore_csr_dfi_p2_cke <= main_litedramcore_cke;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p3_cke <= 1'd0;
+    main_litedramcore_csr_dfi_p3_cke <= main_litedramcore_cke;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p0_odt <= 1'd0;
+    main_litedramcore_csr_dfi_p0_odt <= main_litedramcore_odt;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p1_odt <= 1'd0;
+    main_litedramcore_csr_dfi_p1_odt <= main_litedramcore_odt;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p2_odt <= 1'd0;
+    main_litedramcore_csr_dfi_p2_odt <= main_litedramcore_odt;
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p3_odt <= 1'd0;
+    main_litedramcore_csr_dfi_p3_odt <= main_litedramcore_odt;
+end
+assign main_litedramcore_csr_dfi_p0_reset_n = main_litedramcore_reset_n;
+assign main_litedramcore_csr_dfi_p1_reset_n = main_litedramcore_reset_n;
+assign main_litedramcore_csr_dfi_p2_reset_n = main_litedramcore_reset_n;
+assign main_litedramcore_csr_dfi_p3_reset_n = main_litedramcore_reset_n;
+always @(*) begin
+    main_litedramcore_csr_dfi_p0_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        main_litedramcore_csr_dfi_p0_we_n <= (~main_litedramcore_phaseinjector0_csrfield_we);
     end else begin
-        litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+        main_litedramcore_csr_dfi_p0_we_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p0_cs_n <= 1'd1;
-    if (litedramcore_phaseinjector0_command_issue_re) begin
-        litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}};
+    main_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        main_litedramcore_csr_dfi_p0_cas_n <= (~main_litedramcore_phaseinjector0_csrfield_cas);
     end else begin
-        litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
+        main_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p0_ras_n <= 1'd1;
-    if (litedramcore_phaseinjector0_command_issue_re) begin
-        litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras);
+    main_litedramcore_csr_dfi_p0_cs_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        if (main_litedramcore_phaseinjector0_csrfield_cs_top) begin
+            main_litedramcore_csr_dfi_p0_cs_n <= 2'd2;
+        end else begin
+            if (main_litedramcore_phaseinjector0_csrfield_cs_bottom) begin
+                main_litedramcore_csr_dfi_p0_cs_n <= 1'd1;
+            end else begin
+                main_litedramcore_csr_dfi_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_csrfield_cs)}};
+            end
+        end
     end else begin
-        litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+        main_litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
     end
 end
-assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage;
-assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage;
-assign litedramcore_csr_dfi_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_wren);
-assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_rden);
-assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
-assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
 always @(*) begin
-    litedramcore_csr_dfi_p1_we_n <= 1'd1;
-    if (litedramcore_phaseinjector1_command_issue_re) begin
-        litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
+    main_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        main_litedramcore_csr_dfi_p0_ras_n <= (~main_litedramcore_phaseinjector0_csrfield_ras);
     end else begin
-        litedramcore_csr_dfi_p1_we_n <= 1'd1;
+        main_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
     end
 end
+assign main_litedramcore_csr_dfi_p0_address = main_litedramcore_phaseinjector0_address_storage;
+assign main_litedramcore_csr_dfi_p0_bank = main_litedramcore_phaseinjector0_baddress_storage;
+assign main_litedramcore_csr_dfi_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_wren);
+assign main_litedramcore_csr_dfi_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_rden);
+assign main_litedramcore_csr_dfi_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage;
+assign main_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
 always @(*) begin
-    litedramcore_csr_dfi_p1_cas_n <= 1'd1;
-    if (litedramcore_phaseinjector1_command_issue_re) begin
-        litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas);
+    main_litedramcore_csr_dfi_p1_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        main_litedramcore_csr_dfi_p1_we_n <= (~main_litedramcore_phaseinjector1_csrfield_we);
     end else begin
-        litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+        main_litedramcore_csr_dfi_p1_we_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p1_cs_n <= 1'd1;
-    if (litedramcore_phaseinjector1_command_issue_re) begin
-        litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}};
+    main_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        main_litedramcore_csr_dfi_p1_cas_n <= (~main_litedramcore_phaseinjector1_csrfield_cas);
     end else begin
-        litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
+        main_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p1_ras_n <= 1'd1;
-    if (litedramcore_phaseinjector1_command_issue_re) begin
-        litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras);
+    main_litedramcore_csr_dfi_p1_cs_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        if (main_litedramcore_phaseinjector1_csrfield_cs_top) begin
+            main_litedramcore_csr_dfi_p1_cs_n <= 2'd2;
+        end else begin
+            if (main_litedramcore_phaseinjector1_csrfield_cs_bottom) begin
+                main_litedramcore_csr_dfi_p1_cs_n <= 1'd1;
+            end else begin
+                main_litedramcore_csr_dfi_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_csrfield_cs)}};
+            end
+        end
     end else begin
-        litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+        main_litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
     end
 end
-assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage;
-assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage;
-assign litedramcore_csr_dfi_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_wren);
-assign litedramcore_csr_dfi_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_rden);
-assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
-assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
 always @(*) begin
-    litedramcore_csr_dfi_p2_we_n <= 1'd1;
-    if (litedramcore_phaseinjector2_command_issue_re) begin
-        litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we);
+    main_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        main_litedramcore_csr_dfi_p1_ras_n <= (~main_litedramcore_phaseinjector1_csrfield_ras);
     end else begin
-        litedramcore_csr_dfi_p2_we_n <= 1'd1;
+        main_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
     end
 end
+assign main_litedramcore_csr_dfi_p1_address = main_litedramcore_phaseinjector1_address_storage;
+assign main_litedramcore_csr_dfi_p1_bank = main_litedramcore_phaseinjector1_baddress_storage;
+assign main_litedramcore_csr_dfi_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_wren);
+assign main_litedramcore_csr_dfi_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_rden);
+assign main_litedramcore_csr_dfi_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage;
+assign main_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
 always @(*) begin
-    litedramcore_csr_dfi_p2_cas_n <= 1'd1;
-    if (litedramcore_phaseinjector2_command_issue_re) begin
-        litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas);
+    main_litedramcore_csr_dfi_p2_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        main_litedramcore_csr_dfi_p2_we_n <= (~main_litedramcore_phaseinjector2_csrfield_we);
     end else begin
-        litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+        main_litedramcore_csr_dfi_p2_we_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p2_cs_n <= 1'd1;
-    if (litedramcore_phaseinjector2_command_issue_re) begin
-        litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}};
+    main_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        main_litedramcore_csr_dfi_p2_cas_n <= (~main_litedramcore_phaseinjector2_csrfield_cas);
     end else begin
-        litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
+        main_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p2_ras_n <= 1'd1;
-    if (litedramcore_phaseinjector2_command_issue_re) begin
-        litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras);
+    main_litedramcore_csr_dfi_p2_cs_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        if (main_litedramcore_phaseinjector2_csrfield_cs_top) begin
+            main_litedramcore_csr_dfi_p2_cs_n <= 2'd2;
+        end else begin
+            if (main_litedramcore_phaseinjector2_csrfield_cs_bottom) begin
+                main_litedramcore_csr_dfi_p2_cs_n <= 1'd1;
+            end else begin
+                main_litedramcore_csr_dfi_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_csrfield_cs)}};
+            end
+        end
     end else begin
-        litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+        main_litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
     end
 end
-assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage;
-assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage;
-assign litedramcore_csr_dfi_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_wren);
-assign litedramcore_csr_dfi_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_rden);
-assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
-assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
 always @(*) begin
-    litedramcore_csr_dfi_p3_we_n <= 1'd1;
-    if (litedramcore_phaseinjector3_command_issue_re) begin
-        litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we);
+    main_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        main_litedramcore_csr_dfi_p2_ras_n <= (~main_litedramcore_phaseinjector2_csrfield_ras);
     end else begin
-        litedramcore_csr_dfi_p3_we_n <= 1'd1;
+        main_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
     end
 end
+assign main_litedramcore_csr_dfi_p2_address = main_litedramcore_phaseinjector2_address_storage;
+assign main_litedramcore_csr_dfi_p2_bank = main_litedramcore_phaseinjector2_baddress_storage;
+assign main_litedramcore_csr_dfi_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_wren);
+assign main_litedramcore_csr_dfi_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_rden);
+assign main_litedramcore_csr_dfi_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage;
+assign main_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
 always @(*) begin
-    litedramcore_csr_dfi_p3_cas_n <= 1'd1;
-    if (litedramcore_phaseinjector3_command_issue_re) begin
-        litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas);
+    main_litedramcore_csr_dfi_p3_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        main_litedramcore_csr_dfi_p3_we_n <= (~main_litedramcore_phaseinjector3_csrfield_we);
     end else begin
-        litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+        main_litedramcore_csr_dfi_p3_we_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p3_cs_n <= 1'd1;
-    if (litedramcore_phaseinjector3_command_issue_re) begin
-        litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}};
+    main_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        main_litedramcore_csr_dfi_p3_cas_n <= (~main_litedramcore_phaseinjector3_csrfield_cas);
     end else begin
-        litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
+        main_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p3_ras_n <= 1'd1;
-    if (litedramcore_phaseinjector3_command_issue_re) begin
-        litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras);
+    main_litedramcore_csr_dfi_p3_cs_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        if (main_litedramcore_phaseinjector3_csrfield_cs_top) begin
+            main_litedramcore_csr_dfi_p3_cs_n <= 2'd2;
+        end else begin
+            if (main_litedramcore_phaseinjector3_csrfield_cs_bottom) begin
+                main_litedramcore_csr_dfi_p3_cs_n <= 1'd1;
+            end else begin
+                main_litedramcore_csr_dfi_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_csrfield_cs)}};
+            end
+        end
     end else begin
-        litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+        main_litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
     end
 end
-assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage;
-assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage;
-assign litedramcore_csr_dfi_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_wren);
-assign litedramcore_csr_dfi_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_rden);
-assign litedramcore_csr_dfi_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage;
-assign litedramcore_csr_dfi_p3_wrdata_mask = 1'd0;
-assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid;
-assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready;
-assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we;
-assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr;
-assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock;
-assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready;
-assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid;
-assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid;
-assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready;
-assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we;
-assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr;
-assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock;
-assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready;
-assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid;
-assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid;
-assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready;
-assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we;
-assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr;
-assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock;
-assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready;
-assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid;
-assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid;
-assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready;
-assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we;
-assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr;
-assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock;
-assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready;
-assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid;
-assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid;
-assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready;
-assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we;
-assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr;
-assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock;
-assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready;
-assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid;
-assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid;
-assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready;
-assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we;
-assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr;
-assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock;
-assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready;
-assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid;
-assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid;
-assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready;
-assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we;
-assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr;
-assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock;
-assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready;
-assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid;
-assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid;
-assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready;
-assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we;
-assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr;
-assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock;
-assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready;
-assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid;
-assign litedramcore_timer_wait = (~litedramcore_timer_done0);
-assign litedramcore_postponer_req_i = litedramcore_timer_done0;
-assign litedramcore_wants_refresh = litedramcore_postponer_req_o;
-assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0;
-assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done);
-assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0);
-assign litedramcore_timer_done0 = litedramcore_timer_done1;
-assign litedramcore_timer_count0 = litedramcore_timer_count1;
-assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0));
-assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0));
-assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0);
-assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
-assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
-always @(*) begin
-    litedramcore_refresher_next_state <= 2'd0;
-    litedramcore_refresher_next_state <= litedramcore_refresher_state;
-    case (litedramcore_refresher_state)
-        1'd1: begin
-            if (litedramcore_cmd_ready) begin
-                litedramcore_refresher_next_state <= 2'd2;
-            end
-        end
-        2'd2: begin
-            if (litedramcore_sequencer_done0) begin
-                if (litedramcore_wants_zqcs) begin
-                    litedramcore_refresher_next_state <= 2'd3;
+always @(*) begin
+    main_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        main_litedramcore_csr_dfi_p3_ras_n <= (~main_litedramcore_phaseinjector3_csrfield_ras);
+    end else begin
+        main_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+    end
+end
+assign main_litedramcore_csr_dfi_p3_address = main_litedramcore_phaseinjector3_address_storage;
+assign main_litedramcore_csr_dfi_p3_bank = main_litedramcore_phaseinjector3_baddress_storage;
+assign main_litedramcore_csr_dfi_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_wren);
+assign main_litedramcore_csr_dfi_p3_rddata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_rden);
+assign main_litedramcore_csr_dfi_p3_wrdata = main_litedramcore_phaseinjector3_wrdata_storage;
+assign main_litedramcore_csr_dfi_p3_wrdata_mask = 1'd0;
+assign main_litedramcore_bankmachine0_req_valid = main_litedramcore_interface_bank0_valid;
+assign main_litedramcore_interface_bank0_ready = main_litedramcore_bankmachine0_req_ready;
+assign main_litedramcore_bankmachine0_req_we = main_litedramcore_interface_bank0_we;
+assign main_litedramcore_bankmachine0_req_addr = main_litedramcore_interface_bank0_addr;
+assign main_litedramcore_interface_bank0_lock = main_litedramcore_bankmachine0_req_lock;
+assign main_litedramcore_interface_bank0_wdata_ready = main_litedramcore_bankmachine0_req_wdata_ready;
+assign main_litedramcore_interface_bank0_rdata_valid = main_litedramcore_bankmachine0_req_rdata_valid;
+assign main_litedramcore_bankmachine1_req_valid = main_litedramcore_interface_bank1_valid;
+assign main_litedramcore_interface_bank1_ready = main_litedramcore_bankmachine1_req_ready;
+assign main_litedramcore_bankmachine1_req_we = main_litedramcore_interface_bank1_we;
+assign main_litedramcore_bankmachine1_req_addr = main_litedramcore_interface_bank1_addr;
+assign main_litedramcore_interface_bank1_lock = main_litedramcore_bankmachine1_req_lock;
+assign main_litedramcore_interface_bank1_wdata_ready = main_litedramcore_bankmachine1_req_wdata_ready;
+assign main_litedramcore_interface_bank1_rdata_valid = main_litedramcore_bankmachine1_req_rdata_valid;
+assign main_litedramcore_bankmachine2_req_valid = main_litedramcore_interface_bank2_valid;
+assign main_litedramcore_interface_bank2_ready = main_litedramcore_bankmachine2_req_ready;
+assign main_litedramcore_bankmachine2_req_we = main_litedramcore_interface_bank2_we;
+assign main_litedramcore_bankmachine2_req_addr = main_litedramcore_interface_bank2_addr;
+assign main_litedramcore_interface_bank2_lock = main_litedramcore_bankmachine2_req_lock;
+assign main_litedramcore_interface_bank2_wdata_ready = main_litedramcore_bankmachine2_req_wdata_ready;
+assign main_litedramcore_interface_bank2_rdata_valid = main_litedramcore_bankmachine2_req_rdata_valid;
+assign main_litedramcore_bankmachine3_req_valid = main_litedramcore_interface_bank3_valid;
+assign main_litedramcore_interface_bank3_ready = main_litedramcore_bankmachine3_req_ready;
+assign main_litedramcore_bankmachine3_req_we = main_litedramcore_interface_bank3_we;
+assign main_litedramcore_bankmachine3_req_addr = main_litedramcore_interface_bank3_addr;
+assign main_litedramcore_interface_bank3_lock = main_litedramcore_bankmachine3_req_lock;
+assign main_litedramcore_interface_bank3_wdata_ready = main_litedramcore_bankmachine3_req_wdata_ready;
+assign main_litedramcore_interface_bank3_rdata_valid = main_litedramcore_bankmachine3_req_rdata_valid;
+assign main_litedramcore_bankmachine4_req_valid = main_litedramcore_interface_bank4_valid;
+assign main_litedramcore_interface_bank4_ready = main_litedramcore_bankmachine4_req_ready;
+assign main_litedramcore_bankmachine4_req_we = main_litedramcore_interface_bank4_we;
+assign main_litedramcore_bankmachine4_req_addr = main_litedramcore_interface_bank4_addr;
+assign main_litedramcore_interface_bank4_lock = main_litedramcore_bankmachine4_req_lock;
+assign main_litedramcore_interface_bank4_wdata_ready = main_litedramcore_bankmachine4_req_wdata_ready;
+assign main_litedramcore_interface_bank4_rdata_valid = main_litedramcore_bankmachine4_req_rdata_valid;
+assign main_litedramcore_bankmachine5_req_valid = main_litedramcore_interface_bank5_valid;
+assign main_litedramcore_interface_bank5_ready = main_litedramcore_bankmachine5_req_ready;
+assign main_litedramcore_bankmachine5_req_we = main_litedramcore_interface_bank5_we;
+assign main_litedramcore_bankmachine5_req_addr = main_litedramcore_interface_bank5_addr;
+assign main_litedramcore_interface_bank5_lock = main_litedramcore_bankmachine5_req_lock;
+assign main_litedramcore_interface_bank5_wdata_ready = main_litedramcore_bankmachine5_req_wdata_ready;
+assign main_litedramcore_interface_bank5_rdata_valid = main_litedramcore_bankmachine5_req_rdata_valid;
+assign main_litedramcore_bankmachine6_req_valid = main_litedramcore_interface_bank6_valid;
+assign main_litedramcore_interface_bank6_ready = main_litedramcore_bankmachine6_req_ready;
+assign main_litedramcore_bankmachine6_req_we = main_litedramcore_interface_bank6_we;
+assign main_litedramcore_bankmachine6_req_addr = main_litedramcore_interface_bank6_addr;
+assign main_litedramcore_interface_bank6_lock = main_litedramcore_bankmachine6_req_lock;
+assign main_litedramcore_interface_bank6_wdata_ready = main_litedramcore_bankmachine6_req_wdata_ready;
+assign main_litedramcore_interface_bank6_rdata_valid = main_litedramcore_bankmachine6_req_rdata_valid;
+assign main_litedramcore_bankmachine7_req_valid = main_litedramcore_interface_bank7_valid;
+assign main_litedramcore_interface_bank7_ready = main_litedramcore_bankmachine7_req_ready;
+assign main_litedramcore_bankmachine7_req_we = main_litedramcore_interface_bank7_we;
+assign main_litedramcore_bankmachine7_req_addr = main_litedramcore_interface_bank7_addr;
+assign main_litedramcore_interface_bank7_lock = main_litedramcore_bankmachine7_req_lock;
+assign main_litedramcore_interface_bank7_wdata_ready = main_litedramcore_bankmachine7_req_wdata_ready;
+assign main_litedramcore_interface_bank7_rdata_valid = main_litedramcore_bankmachine7_req_rdata_valid;
+assign main_litedramcore_timer_wait = (~main_litedramcore_timer_done0);
+assign main_litedramcore_postponer_req_i = main_litedramcore_timer_done0;
+assign main_litedramcore_wants_refresh = main_litedramcore_postponer_req_o;
+assign main_litedramcore_wants_zqcs = main_litedramcore_zqcs_timer_done0;
+assign main_litedramcore_zqcs_timer_wait = (~main_litedramcore_zqcs_executer_done);
+assign main_litedramcore_timer_done1 = (main_litedramcore_timer_count1 == 1'd0);
+assign main_litedramcore_timer_done0 = main_litedramcore_timer_done1;
+assign main_litedramcore_timer_count0 = main_litedramcore_timer_count1;
+assign main_litedramcore_sequencer_start1 = (main_litedramcore_sequencer_start0 | (main_litedramcore_sequencer_count != 1'd0));
+assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 & (main_litedramcore_sequencer_count == 1'd0));
+assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0);
+assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1;
+assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1;
+always @(*) begin
+    builder_refresher_next_state <= 2'd0;
+    builder_refresher_next_state <= builder_refresher_state;
+    case (builder_refresher_state)
+        1'd1: begin
+            if (main_litedramcore_cmd_ready) begin
+                builder_refresher_next_state <= 2'd2;
+            end
+        end
+        2'd2: begin
+            if (main_litedramcore_sequencer_done0) begin
+                if (main_litedramcore_wants_zqcs) begin
+                    builder_refresher_next_state <= 2'd3;
                 end else begin
-                    litedramcore_refresher_next_state <= 1'd0;
+                    builder_refresher_next_state <= 1'd0;
                 end
             end
         end
         2'd3: begin
-            if (litedramcore_zqcs_executer_done) begin
-                litedramcore_refresher_next_state <= 1'd0;
+            if (main_litedramcore_zqcs_executer_done) begin
+                builder_refresher_next_state <= 1'd0;
             end
         end
         default: begin
             if (1'd1) begin
-                if (litedramcore_wants_refresh) begin
-                    litedramcore_refresher_next_state <= 1'd1;
+                if (main_litedramcore_wants_refresh) begin
+                    builder_refresher_next_state <= 1'd1;
                 end
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_zqcs_executer_start <= 1'd0;
-    case (litedramcore_refresher_state)
+    main_litedramcore_cmd_valid <= 1'd0;
+    case (builder_refresher_state)
         1'd1: begin
+            main_litedramcore_cmd_valid <= 1'd1;
         end
         2'd2: begin
-            if (litedramcore_sequencer_done0) begin
-                if (litedramcore_wants_zqcs) begin
-                    litedramcore_zqcs_executer_start <= 1'd1;
+            main_litedramcore_cmd_valid <= 1'd1;
+            if (main_litedramcore_sequencer_done0) begin
+                if (main_litedramcore_wants_zqcs) begin
                 end else begin
+                    main_litedramcore_cmd_valid <= 1'd0;
                 end
             end
         end
         2'd3: begin
+            main_litedramcore_cmd_valid <= 1'd1;
+            if (main_litedramcore_zqcs_executer_done) begin
+                main_litedramcore_cmd_valid <= 1'd0;
+            end
         end
         default: begin
         end
     endcase
 end
 always @(*) begin
-    litedramcore_cmd_last <= 1'd0;
-    case (litedramcore_refresher_state)
+    main_litedramcore_zqcs_executer_start <= 1'd0;
+    case (builder_refresher_state)
         1'd1: begin
         end
         2'd2: begin
-            if (litedramcore_sequencer_done0) begin
-                if (litedramcore_wants_zqcs) begin
+            if (main_litedramcore_sequencer_done0) begin
+                if (main_litedramcore_wants_zqcs) begin
+                    main_litedramcore_zqcs_executer_start <= 1'd1;
                 end else begin
-                    litedramcore_cmd_last <= 1'd1;
                 end
             end
         end
         2'd3: begin
-            if (litedramcore_zqcs_executer_done) begin
-                litedramcore_cmd_last <= 1'd1;
-            end
         end
         default: begin
         end
     endcase
 end
 always @(*) begin
-    litedramcore_sequencer_start0 <= 1'd0;
-    case (litedramcore_refresher_state)
+    main_litedramcore_cmd_last <= 1'd0;
+    case (builder_refresher_state)
         1'd1: begin
-            if (litedramcore_cmd_ready) begin
-                litedramcore_sequencer_start0 <= 1'd1;
-            end
         end
         2'd2: begin
+            if (main_litedramcore_sequencer_done0) begin
+                if (main_litedramcore_wants_zqcs) begin
+                end else begin
+                    main_litedramcore_cmd_last <= 1'd1;
+                end
+            end
         end
         2'd3: begin
+            if (main_litedramcore_zqcs_executer_done) begin
+                main_litedramcore_cmd_last <= 1'd1;
+            end
         end
         default: begin
         end
     endcase
 end
 always @(*) begin
-    litedramcore_cmd_valid <= 1'd0;
-    case (litedramcore_refresher_state)
+    main_litedramcore_sequencer_start0 <= 1'd0;
+    case (builder_refresher_state)
         1'd1: begin
-            litedramcore_cmd_valid <= 1'd1;
+            if (main_litedramcore_cmd_ready) begin
+                main_litedramcore_sequencer_start0 <= 1'd1;
+            end
         end
         2'd2: begin
-            litedramcore_cmd_valid <= 1'd1;
-            if (litedramcore_sequencer_done0) begin
-                if (litedramcore_wants_zqcs) begin
-                end else begin
-                    litedramcore_cmd_valid <= 1'd0;
-                end
-            end
         end
         2'd3: begin
-            litedramcore_cmd_valid <= 1'd1;
-            if (litedramcore_zqcs_executer_done) begin
-                litedramcore_cmd_valid <= 1'd0;
-            end
-        end
-        default: begin
-        end
-    endcase
-end
-assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid;
-assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready;
-assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we;
-assign litedramcore_bankmachine0_sink_payload_addr = litedramcore_bankmachine0_req_addr;
-assign litedramcore_bankmachine0_sink_sink_valid = litedramcore_bankmachine0_source_valid;
-assign litedramcore_bankmachine0_source_ready = litedramcore_bankmachine0_sink_sink_ready;
-assign litedramcore_bankmachine0_sink_sink_first = litedramcore_bankmachine0_source_first;
-assign litedramcore_bankmachine0_sink_sink_last = litedramcore_bankmachine0_source_last;
-assign litedramcore_bankmachine0_sink_sink_payload_we = litedramcore_bankmachine0_source_payload_we;
-assign litedramcore_bankmachine0_sink_sink_payload_addr = litedramcore_bankmachine0_source_payload_addr;
-assign litedramcore_bankmachine0_source_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
-assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_source_valid | litedramcore_bankmachine0_source_source_valid);
-assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_source_source_payload_addr[20:7]);
-assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
-always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_a <= 14'd0;
-    if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
-        litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_source_source_payload_addr[20:7];
-    end else begin
-        litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
-assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
-assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
-always @(*) begin
-    litedramcore_bankmachine0_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine0_source_valid & litedramcore_bankmachine0_source_source_valid)) begin
-        if ((litedramcore_bankmachine0_source_payload_addr[20:7] != litedramcore_bankmachine0_source_source_payload_addr[20:7])) begin
-            litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine0_syncfifo0_din = {litedramcore_bankmachine0_fifo_in_last, litedramcore_bankmachine0_fifo_in_first, litedramcore_bankmachine0_fifo_in_payload_addr, litedramcore_bankmachine0_fifo_in_payload_we};
-assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
-assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
-assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
-assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
-assign litedramcore_bankmachine0_sink_ready = litedramcore_bankmachine0_syncfifo0_writable;
-assign litedramcore_bankmachine0_syncfifo0_we = litedramcore_bankmachine0_sink_valid;
-assign litedramcore_bankmachine0_fifo_in_first = litedramcore_bankmachine0_sink_first;
-assign litedramcore_bankmachine0_fifo_in_last = litedramcore_bankmachine0_sink_last;
-assign litedramcore_bankmachine0_fifo_in_payload_we = litedramcore_bankmachine0_sink_payload_we;
-assign litedramcore_bankmachine0_fifo_in_payload_addr = litedramcore_bankmachine0_sink_payload_addr;
-assign litedramcore_bankmachine0_source_valid = litedramcore_bankmachine0_syncfifo0_readable;
-assign litedramcore_bankmachine0_source_first = litedramcore_bankmachine0_fifo_out_first;
-assign litedramcore_bankmachine0_source_last = litedramcore_bankmachine0_fifo_out_last;
-assign litedramcore_bankmachine0_source_payload_we = litedramcore_bankmachine0_fifo_out_payload_we;
-assign litedramcore_bankmachine0_source_payload_addr = litedramcore_bankmachine0_fifo_out_payload_addr;
-assign litedramcore_bankmachine0_syncfifo0_re = litedramcore_bankmachine0_source_ready;
-always @(*) begin
-    litedramcore_bankmachine0_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine0_replace) begin
-        litedramcore_bankmachine0_wrport_adr <= (litedramcore_bankmachine0_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine0_wrport_adr <= litedramcore_bankmachine0_produce;
-    end
-end
-assign litedramcore_bankmachine0_wrport_dat_w = litedramcore_bankmachine0_syncfifo0_din;
-assign litedramcore_bankmachine0_wrport_we = (litedramcore_bankmachine0_syncfifo0_we & (litedramcore_bankmachine0_syncfifo0_writable | litedramcore_bankmachine0_replace));
-assign litedramcore_bankmachine0_do_read = (litedramcore_bankmachine0_syncfifo0_readable & litedramcore_bankmachine0_syncfifo0_re);
-assign litedramcore_bankmachine0_rdport_adr = litedramcore_bankmachine0_consume;
-assign litedramcore_bankmachine0_syncfifo0_dout = litedramcore_bankmachine0_rdport_dat_r;
-assign litedramcore_bankmachine0_syncfifo0_writable = (litedramcore_bankmachine0_level != 5'd16);
-assign litedramcore_bankmachine0_syncfifo0_readable = (litedramcore_bankmachine0_level != 1'd0);
-assign litedramcore_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready);
-assign litedramcore_bankmachine0_pipe_valid_sink_valid = litedramcore_bankmachine0_sink_sink_valid;
-assign litedramcore_bankmachine0_sink_sink_ready = litedramcore_bankmachine0_pipe_valid_sink_ready;
-assign litedramcore_bankmachine0_pipe_valid_sink_first = litedramcore_bankmachine0_sink_sink_first;
-assign litedramcore_bankmachine0_pipe_valid_sink_last = litedramcore_bankmachine0_sink_sink_last;
-assign litedramcore_bankmachine0_pipe_valid_sink_payload_we = litedramcore_bankmachine0_sink_sink_payload_we;
-assign litedramcore_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_bankmachine0_sink_sink_payload_addr;
-assign litedramcore_bankmachine0_source_source_valid = litedramcore_bankmachine0_pipe_valid_source_valid;
-assign litedramcore_bankmachine0_pipe_valid_source_ready = litedramcore_bankmachine0_source_source_ready;
-assign litedramcore_bankmachine0_source_source_first = litedramcore_bankmachine0_pipe_valid_source_first;
-assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_pipe_valid_source_last;
-assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine0_next_state <= 4'd0;
-    litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
-    case (litedramcore_bankmachine0_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                if (litedramcore_bankmachine0_cmd_ready) begin
-                    litedramcore_bankmachine0_next_state <= 3'd5;
+        end
+        default: begin
+        end
+    endcase
+end
+assign main_litedramcore_bankmachine0_sink_valid = main_litedramcore_bankmachine0_req_valid;
+assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_sink_ready;
+assign main_litedramcore_bankmachine0_sink_payload_we = main_litedramcore_bankmachine0_req_we;
+assign main_litedramcore_bankmachine0_sink_payload_addr = main_litedramcore_bankmachine0_req_addr;
+assign main_litedramcore_bankmachine0_sink_sink_valid = main_litedramcore_bankmachine0_source_valid;
+assign main_litedramcore_bankmachine0_source_ready = main_litedramcore_bankmachine0_sink_sink_ready;
+assign main_litedramcore_bankmachine0_sink_sink_first = main_litedramcore_bankmachine0_source_first;
+assign main_litedramcore_bankmachine0_sink_sink_last = main_litedramcore_bankmachine0_source_last;
+assign main_litedramcore_bankmachine0_sink_sink_payload_we = main_litedramcore_bankmachine0_source_payload_we;
+assign main_litedramcore_bankmachine0_sink_sink_payload_addr = main_litedramcore_bankmachine0_source_payload_addr;
+assign main_litedramcore_bankmachine0_source_source_ready = (main_litedramcore_bankmachine0_req_wdata_ready | main_litedramcore_bankmachine0_req_rdata_valid);
+assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_source_valid | main_litedramcore_bankmachine0_source_source_valid);
+assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_source_source_payload_addr[20:7]);
+assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
+always @(*) begin
+    main_litedramcore_bankmachine0_cmd_payload_a <= 14'd0;
+    if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine0_cmd_payload_a <= main_litedramcore_bankmachine0_source_source_payload_addr[20:7];
+    end else begin
+        main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write);
+assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
+assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine0_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine0_source_valid & main_litedramcore_bankmachine0_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine0_source_payload_addr[20:7] != main_litedramcore_bankmachine0_source_source_payload_addr[20:7])) begin
+            main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine0_syncfifo0_din = {main_litedramcore_bankmachine0_fifo_in_last, main_litedramcore_bankmachine0_fifo_in_first, main_litedramcore_bankmachine0_fifo_in_payload_addr, main_litedramcore_bankmachine0_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout;
+assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout;
+assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout;
+assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout;
+assign main_litedramcore_bankmachine0_sink_ready = main_litedramcore_bankmachine0_syncfifo0_writable;
+assign main_litedramcore_bankmachine0_syncfifo0_we = main_litedramcore_bankmachine0_sink_valid;
+assign main_litedramcore_bankmachine0_fifo_in_first = main_litedramcore_bankmachine0_sink_first;
+assign main_litedramcore_bankmachine0_fifo_in_last = main_litedramcore_bankmachine0_sink_last;
+assign main_litedramcore_bankmachine0_fifo_in_payload_we = main_litedramcore_bankmachine0_sink_payload_we;
+assign main_litedramcore_bankmachine0_fifo_in_payload_addr = main_litedramcore_bankmachine0_sink_payload_addr;
+assign main_litedramcore_bankmachine0_source_valid = main_litedramcore_bankmachine0_syncfifo0_readable;
+assign main_litedramcore_bankmachine0_source_first = main_litedramcore_bankmachine0_fifo_out_first;
+assign main_litedramcore_bankmachine0_source_last = main_litedramcore_bankmachine0_fifo_out_last;
+assign main_litedramcore_bankmachine0_source_payload_we = main_litedramcore_bankmachine0_fifo_out_payload_we;
+assign main_litedramcore_bankmachine0_source_payload_addr = main_litedramcore_bankmachine0_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine0_syncfifo0_re = main_litedramcore_bankmachine0_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine0_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine0_replace) begin
+        main_litedramcore_bankmachine0_wrport_adr <= (main_litedramcore_bankmachine0_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine0_wrport_adr <= main_litedramcore_bankmachine0_produce;
+    end
+end
+assign main_litedramcore_bankmachine0_wrport_dat_w = main_litedramcore_bankmachine0_syncfifo0_din;
+assign main_litedramcore_bankmachine0_wrport_we = (main_litedramcore_bankmachine0_syncfifo0_we & (main_litedramcore_bankmachine0_syncfifo0_writable | main_litedramcore_bankmachine0_replace));
+assign main_litedramcore_bankmachine0_do_read = (main_litedramcore_bankmachine0_syncfifo0_readable & main_litedramcore_bankmachine0_syncfifo0_re);
+assign main_litedramcore_bankmachine0_rdport_adr = main_litedramcore_bankmachine0_consume;
+assign main_litedramcore_bankmachine0_syncfifo0_dout = main_litedramcore_bankmachine0_rdport_dat_r;
+assign main_litedramcore_bankmachine0_syncfifo0_writable = (main_litedramcore_bankmachine0_level != 5'd16);
+assign main_litedramcore_bankmachine0_syncfifo0_readable = (main_litedramcore_bankmachine0_level != 1'd0);
+assign main_litedramcore_bankmachine0_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine0_pipe_valid_source_valid) | main_litedramcore_bankmachine0_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine0_pipe_valid_sink_valid = main_litedramcore_bankmachine0_sink_sink_valid;
+assign main_litedramcore_bankmachine0_sink_sink_ready = main_litedramcore_bankmachine0_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine0_pipe_valid_sink_first = main_litedramcore_bankmachine0_sink_sink_first;
+assign main_litedramcore_bankmachine0_pipe_valid_sink_last = main_litedramcore_bankmachine0_sink_sink_last;
+assign main_litedramcore_bankmachine0_pipe_valid_sink_payload_we = main_litedramcore_bankmachine0_sink_sink_payload_we;
+assign main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine0_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine0_source_source_valid = main_litedramcore_bankmachine0_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine0_pipe_valid_source_ready = main_litedramcore_bankmachine0_source_source_ready;
+assign main_litedramcore_bankmachine0_source_source_first = main_litedramcore_bankmachine0_pipe_valid_source_first;
+assign main_litedramcore_bankmachine0_source_source_last = main_litedramcore_bankmachine0_pipe_valid_source_last;
+assign main_litedramcore_bankmachine0_source_source_payload_we = main_litedramcore_bankmachine0_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine0_source_source_payload_addr = main_litedramcore_bankmachine0_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine0_next_state <= 4'd0;
+    builder_bankmachine0_next_state <= builder_bankmachine0_state;
+    case (builder_bankmachine0_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                if (main_litedramcore_bankmachine0_cmd_ready) begin
+                    builder_bankmachine0_next_state <= 3'd5;
                 end
             end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_next_state <= 3'd5;
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                builder_bankmachine0_next_state <= 3'd5;
             end
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                if (litedramcore_bankmachine0_cmd_ready) begin
-                    litedramcore_bankmachine0_next_state <= 3'd7;
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                if (main_litedramcore_bankmachine0_cmd_ready) begin
+                    builder_bankmachine0_next_state <= 3'd7;
                 end
             end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine0_refresh_req)) begin
-                litedramcore_bankmachine0_next_state <= 1'd0;
+            if ((~main_litedramcore_bankmachine0_refresh_req)) begin
+                builder_bankmachine0_next_state <= 1'd0;
             end
         end
         3'd5: begin
-            litedramcore_bankmachine0_next_state <= 3'd6;
+            builder_bankmachine0_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine0_next_state <= 2'd3;
+            builder_bankmachine0_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine0_next_state <= 4'd8;
+            builder_bankmachine0_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine0_next_state <= 1'd0;
+            builder_bankmachine0_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
-                litedramcore_bankmachine0_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine0_refresh_req) begin
+                builder_bankmachine0_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
-                                litedramcore_bankmachine0_next_state <= 2'd2;
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if ((main_litedramcore_bankmachine0_cmd_ready & main_litedramcore_bankmachine0_auto_precharge)) begin
+                                builder_bankmachine0_next_state <= 2'd2;
                             end
                         end else begin
-                            litedramcore_bankmachine0_next_state <= 1'd1;
+                            builder_bankmachine0_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine0_next_state <= 2'd3;
+                        builder_bankmachine0_next_state <= 2'd3;
                     end
                 end
             end
@@ -4888,8 +5306,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -4907,14 +5325,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
+                                main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
                             end else begin
-                                litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
                             end
                         end else begin
                         end
@@ -4926,8 +5344,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -4935,9 +5353,6 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine0_twtpcon_ready) begin
-                litedramcore_bankmachine0_refresh_gnt <= 1'd1;
-            end
         end
         3'd5: begin
         end
@@ -4948,20 +5363,32 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
+                                main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_row_open <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_row_open <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -4974,25 +5401,37 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
+                            end else begin
+                                main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_cmd_valid <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_cmd_valid <= 1'd1;
-            end
         end
         3'd4: begin
+            if (main_litedramcore_bankmachine0_twtpcon_ready) begin
+                main_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -5003,34 +5442,22 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            litedramcore_bankmachine0_cmd_valid <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_row_close <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_row_open <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
-            litedramcore_bankmachine0_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine0_row_close <= 1'd1;
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_row_open <= 1'd1;
+            end
         end
         3'd4: begin
-            litedramcore_bankmachine0_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -5045,15 +5472,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_valid <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -5067,19 +5497,34 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_row_close <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
+            main_litedramcore_bankmachine0_row_close <= 1'd1;
         end
         2'd2: begin
+            main_litedramcore_bankmachine0_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
+            main_litedramcore_bankmachine0_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -5090,34 +5535,19 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -5135,12 +5565,9 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
-            end
         end
         2'd2: begin
         end
@@ -5157,15 +5584,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
-                                litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
-                            end else begin
-                            end
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -5176,22 +5600,21 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -5206,9 +5629,12 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+            end
         end
         2'd2: begin
         end
@@ -5225,14 +5651,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
+                                main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
                             end else begin
-                                litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -5244,15 +5670,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         3'd4: begin
+            main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -5263,27 +5696,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
-                                litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine0_state)
+    main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5301,14 +5719,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
-                                litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
                             end else begin
+                                main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -5319,139 +5737,139 @@ always @(*) begin
         end
     endcase
 end
-assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid;
-assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready;
-assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we;
-assign litedramcore_bankmachine1_sink_payload_addr = litedramcore_bankmachine1_req_addr;
-assign litedramcore_bankmachine1_sink_sink_valid = litedramcore_bankmachine1_source_valid;
-assign litedramcore_bankmachine1_source_ready = litedramcore_bankmachine1_sink_sink_ready;
-assign litedramcore_bankmachine1_sink_sink_first = litedramcore_bankmachine1_source_first;
-assign litedramcore_bankmachine1_sink_sink_last = litedramcore_bankmachine1_source_last;
-assign litedramcore_bankmachine1_sink_sink_payload_we = litedramcore_bankmachine1_source_payload_we;
-assign litedramcore_bankmachine1_sink_sink_payload_addr = litedramcore_bankmachine1_source_payload_addr;
-assign litedramcore_bankmachine1_source_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
-assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_source_valid | litedramcore_bankmachine1_source_source_valid);
-assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_source_source_payload_addr[20:7]);
-assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
-always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_a <= 14'd0;
-    if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
-        litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_source_source_payload_addr[20:7];
-    end else begin
-        litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
-assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
-assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
-always @(*) begin
-    litedramcore_bankmachine1_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine1_source_valid & litedramcore_bankmachine1_source_source_valid)) begin
-        if ((litedramcore_bankmachine1_source_payload_addr[20:7] != litedramcore_bankmachine1_source_source_payload_addr[20:7])) begin
-            litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine1_syncfifo1_din = {litedramcore_bankmachine1_fifo_in_last, litedramcore_bankmachine1_fifo_in_first, litedramcore_bankmachine1_fifo_in_payload_addr, litedramcore_bankmachine1_fifo_in_payload_we};
-assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
-assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
-assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
-assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
-assign litedramcore_bankmachine1_sink_ready = litedramcore_bankmachine1_syncfifo1_writable;
-assign litedramcore_bankmachine1_syncfifo1_we = litedramcore_bankmachine1_sink_valid;
-assign litedramcore_bankmachine1_fifo_in_first = litedramcore_bankmachine1_sink_first;
-assign litedramcore_bankmachine1_fifo_in_last = litedramcore_bankmachine1_sink_last;
-assign litedramcore_bankmachine1_fifo_in_payload_we = litedramcore_bankmachine1_sink_payload_we;
-assign litedramcore_bankmachine1_fifo_in_payload_addr = litedramcore_bankmachine1_sink_payload_addr;
-assign litedramcore_bankmachine1_source_valid = litedramcore_bankmachine1_syncfifo1_readable;
-assign litedramcore_bankmachine1_source_first = litedramcore_bankmachine1_fifo_out_first;
-assign litedramcore_bankmachine1_source_last = litedramcore_bankmachine1_fifo_out_last;
-assign litedramcore_bankmachine1_source_payload_we = litedramcore_bankmachine1_fifo_out_payload_we;
-assign litedramcore_bankmachine1_source_payload_addr = litedramcore_bankmachine1_fifo_out_payload_addr;
-assign litedramcore_bankmachine1_syncfifo1_re = litedramcore_bankmachine1_source_ready;
-always @(*) begin
-    litedramcore_bankmachine1_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine1_replace) begin
-        litedramcore_bankmachine1_wrport_adr <= (litedramcore_bankmachine1_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine1_wrport_adr <= litedramcore_bankmachine1_produce;
-    end
-end
-assign litedramcore_bankmachine1_wrport_dat_w = litedramcore_bankmachine1_syncfifo1_din;
-assign litedramcore_bankmachine1_wrport_we = (litedramcore_bankmachine1_syncfifo1_we & (litedramcore_bankmachine1_syncfifo1_writable | litedramcore_bankmachine1_replace));
-assign litedramcore_bankmachine1_do_read = (litedramcore_bankmachine1_syncfifo1_readable & litedramcore_bankmachine1_syncfifo1_re);
-assign litedramcore_bankmachine1_rdport_adr = litedramcore_bankmachine1_consume;
-assign litedramcore_bankmachine1_syncfifo1_dout = litedramcore_bankmachine1_rdport_dat_r;
-assign litedramcore_bankmachine1_syncfifo1_writable = (litedramcore_bankmachine1_level != 5'd16);
-assign litedramcore_bankmachine1_syncfifo1_readable = (litedramcore_bankmachine1_level != 1'd0);
-assign litedramcore_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready);
-assign litedramcore_bankmachine1_pipe_valid_sink_valid = litedramcore_bankmachine1_sink_sink_valid;
-assign litedramcore_bankmachine1_sink_sink_ready = litedramcore_bankmachine1_pipe_valid_sink_ready;
-assign litedramcore_bankmachine1_pipe_valid_sink_first = litedramcore_bankmachine1_sink_sink_first;
-assign litedramcore_bankmachine1_pipe_valid_sink_last = litedramcore_bankmachine1_sink_sink_last;
-assign litedramcore_bankmachine1_pipe_valid_sink_payload_we = litedramcore_bankmachine1_sink_sink_payload_we;
-assign litedramcore_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_bankmachine1_sink_sink_payload_addr;
-assign litedramcore_bankmachine1_source_source_valid = litedramcore_bankmachine1_pipe_valid_source_valid;
-assign litedramcore_bankmachine1_pipe_valid_source_ready = litedramcore_bankmachine1_source_source_ready;
-assign litedramcore_bankmachine1_source_source_first = litedramcore_bankmachine1_pipe_valid_source_first;
-assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_pipe_valid_source_last;
-assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine1_next_state <= 4'd0;
-    litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
-    case (litedramcore_bankmachine1_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                if (litedramcore_bankmachine1_cmd_ready) begin
-                    litedramcore_bankmachine1_next_state <= 3'd5;
+assign main_litedramcore_bankmachine1_sink_valid = main_litedramcore_bankmachine1_req_valid;
+assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_sink_ready;
+assign main_litedramcore_bankmachine1_sink_payload_we = main_litedramcore_bankmachine1_req_we;
+assign main_litedramcore_bankmachine1_sink_payload_addr = main_litedramcore_bankmachine1_req_addr;
+assign main_litedramcore_bankmachine1_sink_sink_valid = main_litedramcore_bankmachine1_source_valid;
+assign main_litedramcore_bankmachine1_source_ready = main_litedramcore_bankmachine1_sink_sink_ready;
+assign main_litedramcore_bankmachine1_sink_sink_first = main_litedramcore_bankmachine1_source_first;
+assign main_litedramcore_bankmachine1_sink_sink_last = main_litedramcore_bankmachine1_source_last;
+assign main_litedramcore_bankmachine1_sink_sink_payload_we = main_litedramcore_bankmachine1_source_payload_we;
+assign main_litedramcore_bankmachine1_sink_sink_payload_addr = main_litedramcore_bankmachine1_source_payload_addr;
+assign main_litedramcore_bankmachine1_source_source_ready = (main_litedramcore_bankmachine1_req_wdata_ready | main_litedramcore_bankmachine1_req_rdata_valid);
+assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_source_valid | main_litedramcore_bankmachine1_source_source_valid);
+assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_source_source_payload_addr[20:7]);
+assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
+always @(*) begin
+    main_litedramcore_bankmachine1_cmd_payload_a <= 14'd0;
+    if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine1_cmd_payload_a <= main_litedramcore_bankmachine1_source_source_payload_addr[20:7];
+    end else begin
+        main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write);
+assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
+assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine1_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine1_source_valid & main_litedramcore_bankmachine1_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine1_source_payload_addr[20:7] != main_litedramcore_bankmachine1_source_source_payload_addr[20:7])) begin
+            main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine1_syncfifo1_din = {main_litedramcore_bankmachine1_fifo_in_last, main_litedramcore_bankmachine1_fifo_in_first, main_litedramcore_bankmachine1_fifo_in_payload_addr, main_litedramcore_bankmachine1_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout;
+assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout;
+assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout;
+assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout;
+assign main_litedramcore_bankmachine1_sink_ready = main_litedramcore_bankmachine1_syncfifo1_writable;
+assign main_litedramcore_bankmachine1_syncfifo1_we = main_litedramcore_bankmachine1_sink_valid;
+assign main_litedramcore_bankmachine1_fifo_in_first = main_litedramcore_bankmachine1_sink_first;
+assign main_litedramcore_bankmachine1_fifo_in_last = main_litedramcore_bankmachine1_sink_last;
+assign main_litedramcore_bankmachine1_fifo_in_payload_we = main_litedramcore_bankmachine1_sink_payload_we;
+assign main_litedramcore_bankmachine1_fifo_in_payload_addr = main_litedramcore_bankmachine1_sink_payload_addr;
+assign main_litedramcore_bankmachine1_source_valid = main_litedramcore_bankmachine1_syncfifo1_readable;
+assign main_litedramcore_bankmachine1_source_first = main_litedramcore_bankmachine1_fifo_out_first;
+assign main_litedramcore_bankmachine1_source_last = main_litedramcore_bankmachine1_fifo_out_last;
+assign main_litedramcore_bankmachine1_source_payload_we = main_litedramcore_bankmachine1_fifo_out_payload_we;
+assign main_litedramcore_bankmachine1_source_payload_addr = main_litedramcore_bankmachine1_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine1_syncfifo1_re = main_litedramcore_bankmachine1_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine1_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine1_replace) begin
+        main_litedramcore_bankmachine1_wrport_adr <= (main_litedramcore_bankmachine1_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine1_wrport_adr <= main_litedramcore_bankmachine1_produce;
+    end
+end
+assign main_litedramcore_bankmachine1_wrport_dat_w = main_litedramcore_bankmachine1_syncfifo1_din;
+assign main_litedramcore_bankmachine1_wrport_we = (main_litedramcore_bankmachine1_syncfifo1_we & (main_litedramcore_bankmachine1_syncfifo1_writable | main_litedramcore_bankmachine1_replace));
+assign main_litedramcore_bankmachine1_do_read = (main_litedramcore_bankmachine1_syncfifo1_readable & main_litedramcore_bankmachine1_syncfifo1_re);
+assign main_litedramcore_bankmachine1_rdport_adr = main_litedramcore_bankmachine1_consume;
+assign main_litedramcore_bankmachine1_syncfifo1_dout = main_litedramcore_bankmachine1_rdport_dat_r;
+assign main_litedramcore_bankmachine1_syncfifo1_writable = (main_litedramcore_bankmachine1_level != 5'd16);
+assign main_litedramcore_bankmachine1_syncfifo1_readable = (main_litedramcore_bankmachine1_level != 1'd0);
+assign main_litedramcore_bankmachine1_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine1_pipe_valid_source_valid) | main_litedramcore_bankmachine1_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine1_pipe_valid_sink_valid = main_litedramcore_bankmachine1_sink_sink_valid;
+assign main_litedramcore_bankmachine1_sink_sink_ready = main_litedramcore_bankmachine1_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine1_pipe_valid_sink_first = main_litedramcore_bankmachine1_sink_sink_first;
+assign main_litedramcore_bankmachine1_pipe_valid_sink_last = main_litedramcore_bankmachine1_sink_sink_last;
+assign main_litedramcore_bankmachine1_pipe_valid_sink_payload_we = main_litedramcore_bankmachine1_sink_sink_payload_we;
+assign main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine1_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine1_source_source_valid = main_litedramcore_bankmachine1_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine1_pipe_valid_source_ready = main_litedramcore_bankmachine1_source_source_ready;
+assign main_litedramcore_bankmachine1_source_source_first = main_litedramcore_bankmachine1_pipe_valid_source_first;
+assign main_litedramcore_bankmachine1_source_source_last = main_litedramcore_bankmachine1_pipe_valid_source_last;
+assign main_litedramcore_bankmachine1_source_source_payload_we = main_litedramcore_bankmachine1_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine1_source_source_payload_addr = main_litedramcore_bankmachine1_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine1_next_state <= 4'd0;
+    builder_bankmachine1_next_state <= builder_bankmachine1_state;
+    case (builder_bankmachine1_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                if (main_litedramcore_bankmachine1_cmd_ready) begin
+                    builder_bankmachine1_next_state <= 3'd5;
                 end
             end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_next_state <= 3'd5;
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                builder_bankmachine1_next_state <= 3'd5;
             end
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                if (litedramcore_bankmachine1_cmd_ready) begin
-                    litedramcore_bankmachine1_next_state <= 3'd7;
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                if (main_litedramcore_bankmachine1_cmd_ready) begin
+                    builder_bankmachine1_next_state <= 3'd7;
                 end
             end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine1_refresh_req)) begin
-                litedramcore_bankmachine1_next_state <= 1'd0;
+            if ((~main_litedramcore_bankmachine1_refresh_req)) begin
+                builder_bankmachine1_next_state <= 1'd0;
             end
         end
         3'd5: begin
-            litedramcore_bankmachine1_next_state <= 3'd6;
+            builder_bankmachine1_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine1_next_state <= 2'd3;
+            builder_bankmachine1_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine1_next_state <= 4'd8;
+            builder_bankmachine1_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine1_next_state <= 1'd0;
+            builder_bankmachine1_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
-                litedramcore_bankmachine1_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine1_refresh_req) begin
+                builder_bankmachine1_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
-                                litedramcore_bankmachine1_next_state <= 2'd2;
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if ((main_litedramcore_bankmachine1_cmd_ready & main_litedramcore_bankmachine1_auto_precharge)) begin
+                                builder_bankmachine1_next_state <= 2'd2;
                             end
                         end else begin
-                            litedramcore_bankmachine1_next_state <= 1'd1;
+                            builder_bankmachine1_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine1_next_state <= 2'd3;
+                        builder_bankmachine1_next_state <= 2'd3;
                     end
                 end
             end
@@ -5459,18 +5877,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
-            end
         end
         3'd4: begin
+            if (main_litedramcore_bankmachine1_twtpcon_ready) begin
+                main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -5485,13 +5903,16 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_row_open <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_row_open <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -5504,34 +5925,22 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -5545,22 +5954,34 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_row_close <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
-            end
+            main_litedramcore_bankmachine1_row_close <= 1'd1;
         end
         2'd2: begin
+            main_litedramcore_bankmachine1_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
+            main_litedramcore_bankmachine1_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -5571,41 +5992,22 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                                litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -5620,8 +6022,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5639,15 +6041,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
-                            end
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -5658,13 +6057,19 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -5677,28 +6082,16 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                                litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+            end
         end
         2'd2: begin
         end
@@ -5715,13 +6108,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                                litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
+                                main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -5734,15 +6127,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         3'd4: begin
+            main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -5753,27 +6153,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
@@ -5781,9 +6166,6 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine1_twtpcon_ready) begin
-                litedramcore_bankmachine1_refresh_gnt <= 1'd1;
-            end
         end
         3'd5: begin
         end
@@ -5794,20 +6176,32 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
+                            end else begin
+                                main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_row_open <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_row_open <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -5820,23 +6214,32 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
+                                main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
-                litedramcore_bankmachine1_cmd_valid <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_cmd_valid <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -5849,12 +6252,15 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            litedramcore_bankmachine1_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
+                                main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready;
+                            end else begin
+                            end
                         end else begin
                         end
                     end else begin
@@ -5865,18 +6271,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine1_row_close <= 1'd0;
-    case (litedramcore_bankmachine1_state)
+    main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine1_state)
         1'd1: begin
-            litedramcore_bankmachine1_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine1_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine1_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -5887,142 +6290,157 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
+                            end else begin
+                                main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
-assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid;
-assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready;
-assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we;
-assign litedramcore_bankmachine2_sink_payload_addr = litedramcore_bankmachine2_req_addr;
-assign litedramcore_bankmachine2_sink_sink_valid = litedramcore_bankmachine2_source_valid;
-assign litedramcore_bankmachine2_source_ready = litedramcore_bankmachine2_sink_sink_ready;
-assign litedramcore_bankmachine2_sink_sink_first = litedramcore_bankmachine2_source_first;
-assign litedramcore_bankmachine2_sink_sink_last = litedramcore_bankmachine2_source_last;
-assign litedramcore_bankmachine2_sink_sink_payload_we = litedramcore_bankmachine2_source_payload_we;
-assign litedramcore_bankmachine2_sink_sink_payload_addr = litedramcore_bankmachine2_source_payload_addr;
-assign litedramcore_bankmachine2_source_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
-assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_source_valid | litedramcore_bankmachine2_source_source_valid);
-assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_source_source_payload_addr[20:7]);
-assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
-always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_a <= 14'd0;
-    if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
-        litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_source_source_payload_addr[20:7];
-    end else begin
-        litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
-assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
-assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
-always @(*) begin
-    litedramcore_bankmachine2_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine2_source_valid & litedramcore_bankmachine2_source_source_valid)) begin
-        if ((litedramcore_bankmachine2_source_payload_addr[20:7] != litedramcore_bankmachine2_source_source_payload_addr[20:7])) begin
-            litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine2_syncfifo2_din = {litedramcore_bankmachine2_fifo_in_last, litedramcore_bankmachine2_fifo_in_first, litedramcore_bankmachine2_fifo_in_payload_addr, litedramcore_bankmachine2_fifo_in_payload_we};
-assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
-assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
-assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
-assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
-assign litedramcore_bankmachine2_sink_ready = litedramcore_bankmachine2_syncfifo2_writable;
-assign litedramcore_bankmachine2_syncfifo2_we = litedramcore_bankmachine2_sink_valid;
-assign litedramcore_bankmachine2_fifo_in_first = litedramcore_bankmachine2_sink_first;
-assign litedramcore_bankmachine2_fifo_in_last = litedramcore_bankmachine2_sink_last;
-assign litedramcore_bankmachine2_fifo_in_payload_we = litedramcore_bankmachine2_sink_payload_we;
-assign litedramcore_bankmachine2_fifo_in_payload_addr = litedramcore_bankmachine2_sink_payload_addr;
-assign litedramcore_bankmachine2_source_valid = litedramcore_bankmachine2_syncfifo2_readable;
-assign litedramcore_bankmachine2_source_first = litedramcore_bankmachine2_fifo_out_first;
-assign litedramcore_bankmachine2_source_last = litedramcore_bankmachine2_fifo_out_last;
-assign litedramcore_bankmachine2_source_payload_we = litedramcore_bankmachine2_fifo_out_payload_we;
-assign litedramcore_bankmachine2_source_payload_addr = litedramcore_bankmachine2_fifo_out_payload_addr;
-assign litedramcore_bankmachine2_syncfifo2_re = litedramcore_bankmachine2_source_ready;
-always @(*) begin
-    litedramcore_bankmachine2_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine2_replace) begin
-        litedramcore_bankmachine2_wrport_adr <= (litedramcore_bankmachine2_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine2_wrport_adr <= litedramcore_bankmachine2_produce;
-    end
-end
-assign litedramcore_bankmachine2_wrport_dat_w = litedramcore_bankmachine2_syncfifo2_din;
-assign litedramcore_bankmachine2_wrport_we = (litedramcore_bankmachine2_syncfifo2_we & (litedramcore_bankmachine2_syncfifo2_writable | litedramcore_bankmachine2_replace));
-assign litedramcore_bankmachine2_do_read = (litedramcore_bankmachine2_syncfifo2_readable & litedramcore_bankmachine2_syncfifo2_re);
-assign litedramcore_bankmachine2_rdport_adr = litedramcore_bankmachine2_consume;
-assign litedramcore_bankmachine2_syncfifo2_dout = litedramcore_bankmachine2_rdport_dat_r;
-assign litedramcore_bankmachine2_syncfifo2_writable = (litedramcore_bankmachine2_level != 5'd16);
-assign litedramcore_bankmachine2_syncfifo2_readable = (litedramcore_bankmachine2_level != 1'd0);
-assign litedramcore_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready);
-assign litedramcore_bankmachine2_pipe_valid_sink_valid = litedramcore_bankmachine2_sink_sink_valid;
-assign litedramcore_bankmachine2_sink_sink_ready = litedramcore_bankmachine2_pipe_valid_sink_ready;
-assign litedramcore_bankmachine2_pipe_valid_sink_first = litedramcore_bankmachine2_sink_sink_first;
-assign litedramcore_bankmachine2_pipe_valid_sink_last = litedramcore_bankmachine2_sink_sink_last;
-assign litedramcore_bankmachine2_pipe_valid_sink_payload_we = litedramcore_bankmachine2_sink_sink_payload_we;
-assign litedramcore_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_bankmachine2_sink_sink_payload_addr;
-assign litedramcore_bankmachine2_source_source_valid = litedramcore_bankmachine2_pipe_valid_source_valid;
-assign litedramcore_bankmachine2_pipe_valid_source_ready = litedramcore_bankmachine2_source_source_ready;
-assign litedramcore_bankmachine2_source_source_first = litedramcore_bankmachine2_pipe_valid_source_first;
-assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_pipe_valid_source_last;
-assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine2_next_state <= 4'd0;
-    litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
-    case (litedramcore_bankmachine2_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                if (litedramcore_bankmachine2_cmd_ready) begin
-                    litedramcore_bankmachine2_next_state <= 3'd5;
+assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid;
+assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready;
+assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we;
+assign main_litedramcore_bankmachine2_sink_payload_addr = main_litedramcore_bankmachine2_req_addr;
+assign main_litedramcore_bankmachine2_sink_sink_valid = main_litedramcore_bankmachine2_source_valid;
+assign main_litedramcore_bankmachine2_source_ready = main_litedramcore_bankmachine2_sink_sink_ready;
+assign main_litedramcore_bankmachine2_sink_sink_first = main_litedramcore_bankmachine2_source_first;
+assign main_litedramcore_bankmachine2_sink_sink_last = main_litedramcore_bankmachine2_source_last;
+assign main_litedramcore_bankmachine2_sink_sink_payload_we = main_litedramcore_bankmachine2_source_payload_we;
+assign main_litedramcore_bankmachine2_sink_sink_payload_addr = main_litedramcore_bankmachine2_source_payload_addr;
+assign main_litedramcore_bankmachine2_source_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid);
+assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_source_valid | main_litedramcore_bankmachine2_source_source_valid);
+assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_source_source_payload_addr[20:7]);
+assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
+always @(*) begin
+    main_litedramcore_bankmachine2_cmd_payload_a <= 14'd0;
+    if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine2_cmd_payload_a <= main_litedramcore_bankmachine2_source_source_payload_addr[20:7];
+    end else begin
+        main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write);
+assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
+assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine2_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine2_source_valid & main_litedramcore_bankmachine2_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine2_source_payload_addr[20:7] != main_litedramcore_bankmachine2_source_source_payload_addr[20:7])) begin
+            main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine2_syncfifo2_din = {main_litedramcore_bankmachine2_fifo_in_last, main_litedramcore_bankmachine2_fifo_in_first, main_litedramcore_bankmachine2_fifo_in_payload_addr, main_litedramcore_bankmachine2_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
+assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
+assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
+assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
+assign main_litedramcore_bankmachine2_sink_ready = main_litedramcore_bankmachine2_syncfifo2_writable;
+assign main_litedramcore_bankmachine2_syncfifo2_we = main_litedramcore_bankmachine2_sink_valid;
+assign main_litedramcore_bankmachine2_fifo_in_first = main_litedramcore_bankmachine2_sink_first;
+assign main_litedramcore_bankmachine2_fifo_in_last = main_litedramcore_bankmachine2_sink_last;
+assign main_litedramcore_bankmachine2_fifo_in_payload_we = main_litedramcore_bankmachine2_sink_payload_we;
+assign main_litedramcore_bankmachine2_fifo_in_payload_addr = main_litedramcore_bankmachine2_sink_payload_addr;
+assign main_litedramcore_bankmachine2_source_valid = main_litedramcore_bankmachine2_syncfifo2_readable;
+assign main_litedramcore_bankmachine2_source_first = main_litedramcore_bankmachine2_fifo_out_first;
+assign main_litedramcore_bankmachine2_source_last = main_litedramcore_bankmachine2_fifo_out_last;
+assign main_litedramcore_bankmachine2_source_payload_we = main_litedramcore_bankmachine2_fifo_out_payload_we;
+assign main_litedramcore_bankmachine2_source_payload_addr = main_litedramcore_bankmachine2_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine2_syncfifo2_re = main_litedramcore_bankmachine2_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine2_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine2_replace) begin
+        main_litedramcore_bankmachine2_wrport_adr <= (main_litedramcore_bankmachine2_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine2_wrport_adr <= main_litedramcore_bankmachine2_produce;
+    end
+end
+assign main_litedramcore_bankmachine2_wrport_dat_w = main_litedramcore_bankmachine2_syncfifo2_din;
+assign main_litedramcore_bankmachine2_wrport_we = (main_litedramcore_bankmachine2_syncfifo2_we & (main_litedramcore_bankmachine2_syncfifo2_writable | main_litedramcore_bankmachine2_replace));
+assign main_litedramcore_bankmachine2_do_read = (main_litedramcore_bankmachine2_syncfifo2_readable & main_litedramcore_bankmachine2_syncfifo2_re);
+assign main_litedramcore_bankmachine2_rdport_adr = main_litedramcore_bankmachine2_consume;
+assign main_litedramcore_bankmachine2_syncfifo2_dout = main_litedramcore_bankmachine2_rdport_dat_r;
+assign main_litedramcore_bankmachine2_syncfifo2_writable = (main_litedramcore_bankmachine2_level != 5'd16);
+assign main_litedramcore_bankmachine2_syncfifo2_readable = (main_litedramcore_bankmachine2_level != 1'd0);
+assign main_litedramcore_bankmachine2_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine2_pipe_valid_source_valid) | main_litedramcore_bankmachine2_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine2_pipe_valid_sink_valid = main_litedramcore_bankmachine2_sink_sink_valid;
+assign main_litedramcore_bankmachine2_sink_sink_ready = main_litedramcore_bankmachine2_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine2_pipe_valid_sink_first = main_litedramcore_bankmachine2_sink_sink_first;
+assign main_litedramcore_bankmachine2_pipe_valid_sink_last = main_litedramcore_bankmachine2_sink_sink_last;
+assign main_litedramcore_bankmachine2_pipe_valid_sink_payload_we = main_litedramcore_bankmachine2_sink_sink_payload_we;
+assign main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine2_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine2_source_source_valid = main_litedramcore_bankmachine2_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine2_pipe_valid_source_ready = main_litedramcore_bankmachine2_source_source_ready;
+assign main_litedramcore_bankmachine2_source_source_first = main_litedramcore_bankmachine2_pipe_valid_source_first;
+assign main_litedramcore_bankmachine2_source_source_last = main_litedramcore_bankmachine2_pipe_valid_source_last;
+assign main_litedramcore_bankmachine2_source_source_payload_we = main_litedramcore_bankmachine2_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine2_source_source_payload_addr = main_litedramcore_bankmachine2_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine2_next_state <= 4'd0;
+    builder_bankmachine2_next_state <= builder_bankmachine2_state;
+    case (builder_bankmachine2_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                if (main_litedramcore_bankmachine2_cmd_ready) begin
+                    builder_bankmachine2_next_state <= 3'd5;
                 end
             end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_next_state <= 3'd5;
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                builder_bankmachine2_next_state <= 3'd5;
             end
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                if (litedramcore_bankmachine2_cmd_ready) begin
-                    litedramcore_bankmachine2_next_state <= 3'd7;
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                if (main_litedramcore_bankmachine2_cmd_ready) begin
+                    builder_bankmachine2_next_state <= 3'd7;
                 end
             end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine2_refresh_req)) begin
-                litedramcore_bankmachine2_next_state <= 1'd0;
+            if ((~main_litedramcore_bankmachine2_refresh_req)) begin
+                builder_bankmachine2_next_state <= 1'd0;
             end
         end
         3'd5: begin
-            litedramcore_bankmachine2_next_state <= 3'd6;
+            builder_bankmachine2_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine2_next_state <= 2'd3;
+            builder_bankmachine2_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine2_next_state <= 4'd8;
+            builder_bankmachine2_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine2_next_state <= 1'd0;
+            builder_bankmachine2_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
-                litedramcore_bankmachine2_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine2_refresh_req) begin
+                builder_bankmachine2_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
-                                litedramcore_bankmachine2_next_state <= 2'd2;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if ((main_litedramcore_bankmachine2_cmd_ready & main_litedramcore_bankmachine2_auto_precharge)) begin
+                                builder_bankmachine2_next_state <= 2'd2;
                             end
                         end else begin
-                            litedramcore_bankmachine2_next_state <= 1'd1;
+                            builder_bankmachine2_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine2_next_state <= 2'd3;
+                        builder_bankmachine2_next_state <= 2'd3;
                     end
                 end
             end
@@ -6030,8 +6448,34 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine2_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6049,12 +6493,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -6065,18 +6509,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -6094,11 +6538,11 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
@@ -6116,13 +6560,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
-                                litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
+                                main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -6135,22 +6579,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -6165,8 +6609,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6184,14 +6628,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -6203,8 +6647,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6222,13 +6666,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
-                                litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
+                                main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -6241,8 +6685,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6260,13 +6704,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
-                                litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
+                                main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -6279,8 +6723,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6298,14 +6742,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            if (litedramcore_bankmachine2_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
+                                main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
                             end
                         end else begin
                         end
@@ -6317,8 +6761,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6326,8 +6770,8 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine2_twtpcon_ready) begin
-                litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+            if (main_litedramcore_bankmachine2_twtpcon_ready) begin
+                main_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
             end
         end
         3'd5: begin
@@ -6343,15 +6787,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_row_open <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_row_open <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -6369,18 +6813,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
-            if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
-                litedramcore_bankmachine2_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -6394,12 +6838,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine2_refresh_req) begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine2_source_source_valid) begin
-                    if (litedramcore_bankmachine2_row_opened) begin
-                        if (litedramcore_bankmachine2_row_hit) begin
-                            litedramcore_bankmachine2_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -6410,18 +6854,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine2_row_close <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+    main_litedramcore_bankmachine2_row_close <= 1'd0;
+    case (builder_bankmachine2_state)
         1'd1: begin
-            litedramcore_bankmachine2_row_close <= 1'd1;
+            main_litedramcore_bankmachine2_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine2_row_close <= 1'd1;
+            main_litedramcore_bankmachine2_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine2_row_close <= 1'd1;
+            main_litedramcore_bankmachine2_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -6435,165 +6879,209 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine2_state)
+assign main_litedramcore_bankmachine3_sink_valid = main_litedramcore_bankmachine3_req_valid;
+assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_sink_ready;
+assign main_litedramcore_bankmachine3_sink_payload_we = main_litedramcore_bankmachine3_req_we;
+assign main_litedramcore_bankmachine3_sink_payload_addr = main_litedramcore_bankmachine3_req_addr;
+assign main_litedramcore_bankmachine3_sink_sink_valid = main_litedramcore_bankmachine3_source_valid;
+assign main_litedramcore_bankmachine3_source_ready = main_litedramcore_bankmachine3_sink_sink_ready;
+assign main_litedramcore_bankmachine3_sink_sink_first = main_litedramcore_bankmachine3_source_first;
+assign main_litedramcore_bankmachine3_sink_sink_last = main_litedramcore_bankmachine3_source_last;
+assign main_litedramcore_bankmachine3_sink_sink_payload_we = main_litedramcore_bankmachine3_source_payload_we;
+assign main_litedramcore_bankmachine3_sink_sink_payload_addr = main_litedramcore_bankmachine3_source_payload_addr;
+assign main_litedramcore_bankmachine3_source_source_ready = (main_litedramcore_bankmachine3_req_wdata_ready | main_litedramcore_bankmachine3_req_rdata_valid);
+assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_source_valid | main_litedramcore_bankmachine3_source_source_valid);
+assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_source_source_payload_addr[20:7]);
+assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
+always @(*) begin
+    main_litedramcore_bankmachine3_cmd_payload_a <= 14'd0;
+    if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine3_cmd_payload_a <= main_litedramcore_bankmachine3_source_source_payload_addr[20:7];
+    end else begin
+        main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write);
+assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
+assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine3_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine3_source_valid & main_litedramcore_bankmachine3_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine3_source_payload_addr[20:7] != main_litedramcore_bankmachine3_source_source_payload_addr[20:7])) begin
+            main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine3_syncfifo3_din = {main_litedramcore_bankmachine3_fifo_in_last, main_litedramcore_bankmachine3_fifo_in_first, main_litedramcore_bankmachine3_fifo_in_payload_addr, main_litedramcore_bankmachine3_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout;
+assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout;
+assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout;
+assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout;
+assign main_litedramcore_bankmachine3_sink_ready = main_litedramcore_bankmachine3_syncfifo3_writable;
+assign main_litedramcore_bankmachine3_syncfifo3_we = main_litedramcore_bankmachine3_sink_valid;
+assign main_litedramcore_bankmachine3_fifo_in_first = main_litedramcore_bankmachine3_sink_first;
+assign main_litedramcore_bankmachine3_fifo_in_last = main_litedramcore_bankmachine3_sink_last;
+assign main_litedramcore_bankmachine3_fifo_in_payload_we = main_litedramcore_bankmachine3_sink_payload_we;
+assign main_litedramcore_bankmachine3_fifo_in_payload_addr = main_litedramcore_bankmachine3_sink_payload_addr;
+assign main_litedramcore_bankmachine3_source_valid = main_litedramcore_bankmachine3_syncfifo3_readable;
+assign main_litedramcore_bankmachine3_source_first = main_litedramcore_bankmachine3_fifo_out_first;
+assign main_litedramcore_bankmachine3_source_last = main_litedramcore_bankmachine3_fifo_out_last;
+assign main_litedramcore_bankmachine3_source_payload_we = main_litedramcore_bankmachine3_fifo_out_payload_we;
+assign main_litedramcore_bankmachine3_source_payload_addr = main_litedramcore_bankmachine3_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine3_syncfifo3_re = main_litedramcore_bankmachine3_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine3_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine3_replace) begin
+        main_litedramcore_bankmachine3_wrport_adr <= (main_litedramcore_bankmachine3_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine3_wrport_adr <= main_litedramcore_bankmachine3_produce;
+    end
+end
+assign main_litedramcore_bankmachine3_wrport_dat_w = main_litedramcore_bankmachine3_syncfifo3_din;
+assign main_litedramcore_bankmachine3_wrport_we = (main_litedramcore_bankmachine3_syncfifo3_we & (main_litedramcore_bankmachine3_syncfifo3_writable | main_litedramcore_bankmachine3_replace));
+assign main_litedramcore_bankmachine3_do_read = (main_litedramcore_bankmachine3_syncfifo3_readable & main_litedramcore_bankmachine3_syncfifo3_re);
+assign main_litedramcore_bankmachine3_rdport_adr = main_litedramcore_bankmachine3_consume;
+assign main_litedramcore_bankmachine3_syncfifo3_dout = main_litedramcore_bankmachine3_rdport_dat_r;
+assign main_litedramcore_bankmachine3_syncfifo3_writable = (main_litedramcore_bankmachine3_level != 5'd16);
+assign main_litedramcore_bankmachine3_syncfifo3_readable = (main_litedramcore_bankmachine3_level != 1'd0);
+assign main_litedramcore_bankmachine3_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine3_pipe_valid_source_valid) | main_litedramcore_bankmachine3_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine3_pipe_valid_sink_valid = main_litedramcore_bankmachine3_sink_sink_valid;
+assign main_litedramcore_bankmachine3_sink_sink_ready = main_litedramcore_bankmachine3_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine3_pipe_valid_sink_first = main_litedramcore_bankmachine3_sink_sink_first;
+assign main_litedramcore_bankmachine3_pipe_valid_sink_last = main_litedramcore_bankmachine3_sink_sink_last;
+assign main_litedramcore_bankmachine3_pipe_valid_sink_payload_we = main_litedramcore_bankmachine3_sink_sink_payload_we;
+assign main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine3_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine3_source_source_valid = main_litedramcore_bankmachine3_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine3_pipe_valid_source_ready = main_litedramcore_bankmachine3_source_source_ready;
+assign main_litedramcore_bankmachine3_source_source_first = main_litedramcore_bankmachine3_pipe_valid_source_first;
+assign main_litedramcore_bankmachine3_source_source_last = main_litedramcore_bankmachine3_pipe_valid_source_last;
+assign main_litedramcore_bankmachine3_source_source_payload_we = main_litedramcore_bankmachine3_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine3_source_source_payload_addr = main_litedramcore_bankmachine3_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine3_next_state <= 4'd0;
+    builder_bankmachine3_next_state <= builder_bankmachine3_state;
+    case (builder_bankmachine3_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                if (main_litedramcore_bankmachine3_cmd_ready) begin
+                    builder_bankmachine3_next_state <= 3'd5;
+                end
+            end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                builder_bankmachine3_next_state <= 3'd5;
+            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine2_trccon_ready) begin
-                litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                if (main_litedramcore_bankmachine3_cmd_ready) begin
+                    builder_bankmachine3_next_state <= 3'd7;
+                end
             end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine3_refresh_req)) begin
+                builder_bankmachine3_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine3_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine3_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine3_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine3_next_state <= 1'd0;
         end
         default: begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
+                builder_bankmachine3_next_state <= 3'd4;
+            end else begin
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin
+                                builder_bankmachine3_next_state <= 2'd2;
+                            end
+                        end else begin
+                            builder_bankmachine3_next_state <= 1'd1;
+                        end
+                    end else begin
+                        builder_bankmachine3_next_state <= 2'd3;
+                    end
+                end
+            end
         end
     endcase
 end
-assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid;
-assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready;
-assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we;
-assign litedramcore_bankmachine3_sink_payload_addr = litedramcore_bankmachine3_req_addr;
-assign litedramcore_bankmachine3_sink_sink_valid = litedramcore_bankmachine3_source_valid;
-assign litedramcore_bankmachine3_source_ready = litedramcore_bankmachine3_sink_sink_ready;
-assign litedramcore_bankmachine3_sink_sink_first = litedramcore_bankmachine3_source_first;
-assign litedramcore_bankmachine3_sink_sink_last = litedramcore_bankmachine3_source_last;
-assign litedramcore_bankmachine3_sink_sink_payload_we = litedramcore_bankmachine3_source_payload_we;
-assign litedramcore_bankmachine3_sink_sink_payload_addr = litedramcore_bankmachine3_source_payload_addr;
-assign litedramcore_bankmachine3_source_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
-assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_source_valid | litedramcore_bankmachine3_source_source_valid);
-assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_source_source_payload_addr[20:7]);
-assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
-always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_a <= 14'd0;
-    if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
-        litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_source_source_payload_addr[20:7];
-    end else begin
-        litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
-assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
-assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
-always @(*) begin
-    litedramcore_bankmachine3_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine3_source_valid & litedramcore_bankmachine3_source_source_valid)) begin
-        if ((litedramcore_bankmachine3_source_payload_addr[20:7] != litedramcore_bankmachine3_source_source_payload_addr[20:7])) begin
-            litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine3_syncfifo3_din = {litedramcore_bankmachine3_fifo_in_last, litedramcore_bankmachine3_fifo_in_first, litedramcore_bankmachine3_fifo_in_payload_addr, litedramcore_bankmachine3_fifo_in_payload_we};
-assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
-assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
-assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
-assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
-assign litedramcore_bankmachine3_sink_ready = litedramcore_bankmachine3_syncfifo3_writable;
-assign litedramcore_bankmachine3_syncfifo3_we = litedramcore_bankmachine3_sink_valid;
-assign litedramcore_bankmachine3_fifo_in_first = litedramcore_bankmachine3_sink_first;
-assign litedramcore_bankmachine3_fifo_in_last = litedramcore_bankmachine3_sink_last;
-assign litedramcore_bankmachine3_fifo_in_payload_we = litedramcore_bankmachine3_sink_payload_we;
-assign litedramcore_bankmachine3_fifo_in_payload_addr = litedramcore_bankmachine3_sink_payload_addr;
-assign litedramcore_bankmachine3_source_valid = litedramcore_bankmachine3_syncfifo3_readable;
-assign litedramcore_bankmachine3_source_first = litedramcore_bankmachine3_fifo_out_first;
-assign litedramcore_bankmachine3_source_last = litedramcore_bankmachine3_fifo_out_last;
-assign litedramcore_bankmachine3_source_payload_we = litedramcore_bankmachine3_fifo_out_payload_we;
-assign litedramcore_bankmachine3_source_payload_addr = litedramcore_bankmachine3_fifo_out_payload_addr;
-assign litedramcore_bankmachine3_syncfifo3_re = litedramcore_bankmachine3_source_ready;
-always @(*) begin
-    litedramcore_bankmachine3_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine3_replace) begin
-        litedramcore_bankmachine3_wrport_adr <= (litedramcore_bankmachine3_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine3_wrport_adr <= litedramcore_bankmachine3_produce;
-    end
-end
-assign litedramcore_bankmachine3_wrport_dat_w = litedramcore_bankmachine3_syncfifo3_din;
-assign litedramcore_bankmachine3_wrport_we = (litedramcore_bankmachine3_syncfifo3_we & (litedramcore_bankmachine3_syncfifo3_writable | litedramcore_bankmachine3_replace));
-assign litedramcore_bankmachine3_do_read = (litedramcore_bankmachine3_syncfifo3_readable & litedramcore_bankmachine3_syncfifo3_re);
-assign litedramcore_bankmachine3_rdport_adr = litedramcore_bankmachine3_consume;
-assign litedramcore_bankmachine3_syncfifo3_dout = litedramcore_bankmachine3_rdport_dat_r;
-assign litedramcore_bankmachine3_syncfifo3_writable = (litedramcore_bankmachine3_level != 5'd16);
-assign litedramcore_bankmachine3_syncfifo3_readable = (litedramcore_bankmachine3_level != 1'd0);
-assign litedramcore_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready);
-assign litedramcore_bankmachine3_pipe_valid_sink_valid = litedramcore_bankmachine3_sink_sink_valid;
-assign litedramcore_bankmachine3_sink_sink_ready = litedramcore_bankmachine3_pipe_valid_sink_ready;
-assign litedramcore_bankmachine3_pipe_valid_sink_first = litedramcore_bankmachine3_sink_sink_first;
-assign litedramcore_bankmachine3_pipe_valid_sink_last = litedramcore_bankmachine3_sink_sink_last;
-assign litedramcore_bankmachine3_pipe_valid_sink_payload_we = litedramcore_bankmachine3_sink_sink_payload_we;
-assign litedramcore_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_bankmachine3_sink_sink_payload_addr;
-assign litedramcore_bankmachine3_source_source_valid = litedramcore_bankmachine3_pipe_valid_source_valid;
-assign litedramcore_bankmachine3_pipe_valid_source_ready = litedramcore_bankmachine3_source_source_ready;
-assign litedramcore_bankmachine3_source_source_first = litedramcore_bankmachine3_pipe_valid_source_first;
-assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_pipe_valid_source_last;
-assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine3_next_state <= 4'd0;
-    litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
-    case (litedramcore_bankmachine3_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                if (litedramcore_bankmachine3_cmd_ready) begin
-                    litedramcore_bankmachine3_next_state <= 3'd5;
-                end
+always @(*) begin
+    main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine3_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                if (litedramcore_bankmachine3_cmd_ready) begin
-                    litedramcore_bankmachine3_next_state <= 3'd7;
-                end
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine3_refresh_req)) begin
-                litedramcore_bankmachine3_next_state <= 1'd0;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine3_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
             end
         end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
         3'd5: begin
-            litedramcore_bankmachine3_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine3_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine3_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine3_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
-                litedramcore_bankmachine3_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
-                                litedramcore_bankmachine3_next_state <= 2'd2;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
+                                main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+                            end else begin
                             end
                         end else begin
-                            litedramcore_bankmachine3_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine3_next_state <= 2'd3;
                     end
                 end
             end
@@ -6601,22 +7089,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -6631,8 +7119,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6650,14 +7138,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -6669,8 +7157,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6688,13 +7176,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
-                                litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
+                                main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -6707,8 +7195,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6726,13 +7214,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
-                                litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
+                                main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -6745,8 +7233,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6764,14 +7252,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
+                                main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
                             end
                         end else begin
                         end
@@ -6783,8 +7271,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6792,8 +7280,8 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine3_twtpcon_ready) begin
-                litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+            if (main_litedramcore_bankmachine3_twtpcon_ready) begin
+                main_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
             end
         end
         3'd5: begin
@@ -6809,15 +7297,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_row_open <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_row_open <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -6835,18 +7323,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -6860,12 +7348,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            litedramcore_bankmachine3_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -6876,18 +7364,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_row_close <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_row_close <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
-            litedramcore_bankmachine3_row_close <= 1'd1;
+            main_litedramcore_bankmachine3_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine3_row_close <= 1'd1;
+            main_litedramcore_bankmachine3_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine3_row_close <= 1'd1;
+            main_litedramcore_bankmachine3_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -6902,15 +7390,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -6928,8 +7416,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
@@ -6947,12 +7435,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -6962,42 +7450,149 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+assign main_litedramcore_bankmachine4_sink_valid = main_litedramcore_bankmachine4_req_valid;
+assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_sink_ready;
+assign main_litedramcore_bankmachine4_sink_payload_we = main_litedramcore_bankmachine4_req_we;
+assign main_litedramcore_bankmachine4_sink_payload_addr = main_litedramcore_bankmachine4_req_addr;
+assign main_litedramcore_bankmachine4_sink_sink_valid = main_litedramcore_bankmachine4_source_valid;
+assign main_litedramcore_bankmachine4_source_ready = main_litedramcore_bankmachine4_sink_sink_ready;
+assign main_litedramcore_bankmachine4_sink_sink_first = main_litedramcore_bankmachine4_source_first;
+assign main_litedramcore_bankmachine4_sink_sink_last = main_litedramcore_bankmachine4_source_last;
+assign main_litedramcore_bankmachine4_sink_sink_payload_we = main_litedramcore_bankmachine4_source_payload_we;
+assign main_litedramcore_bankmachine4_sink_sink_payload_addr = main_litedramcore_bankmachine4_source_payload_addr;
+assign main_litedramcore_bankmachine4_source_source_ready = (main_litedramcore_bankmachine4_req_wdata_ready | main_litedramcore_bankmachine4_req_rdata_valid);
+assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_source_valid | main_litedramcore_bankmachine4_source_source_valid);
+assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_source_source_payload_addr[20:7]);
+assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
+always @(*) begin
+    main_litedramcore_bankmachine4_cmd_payload_a <= 14'd0;
+    if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine4_cmd_payload_a <= main_litedramcore_bankmachine4_source_source_payload_addr[20:7];
+    end else begin
+        main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write);
+assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
+assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine4_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine4_source_valid & main_litedramcore_bankmachine4_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine4_source_payload_addr[20:7] != main_litedramcore_bankmachine4_source_source_payload_addr[20:7])) begin
+            main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine4_syncfifo4_din = {main_litedramcore_bankmachine4_fifo_in_last, main_litedramcore_bankmachine4_fifo_in_first, main_litedramcore_bankmachine4_fifo_in_payload_addr, main_litedramcore_bankmachine4_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout;
+assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout;
+assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout;
+assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout;
+assign main_litedramcore_bankmachine4_sink_ready = main_litedramcore_bankmachine4_syncfifo4_writable;
+assign main_litedramcore_bankmachine4_syncfifo4_we = main_litedramcore_bankmachine4_sink_valid;
+assign main_litedramcore_bankmachine4_fifo_in_first = main_litedramcore_bankmachine4_sink_first;
+assign main_litedramcore_bankmachine4_fifo_in_last = main_litedramcore_bankmachine4_sink_last;
+assign main_litedramcore_bankmachine4_fifo_in_payload_we = main_litedramcore_bankmachine4_sink_payload_we;
+assign main_litedramcore_bankmachine4_fifo_in_payload_addr = main_litedramcore_bankmachine4_sink_payload_addr;
+assign main_litedramcore_bankmachine4_source_valid = main_litedramcore_bankmachine4_syncfifo4_readable;
+assign main_litedramcore_bankmachine4_source_first = main_litedramcore_bankmachine4_fifo_out_first;
+assign main_litedramcore_bankmachine4_source_last = main_litedramcore_bankmachine4_fifo_out_last;
+assign main_litedramcore_bankmachine4_source_payload_we = main_litedramcore_bankmachine4_fifo_out_payload_we;
+assign main_litedramcore_bankmachine4_source_payload_addr = main_litedramcore_bankmachine4_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine4_syncfifo4_re = main_litedramcore_bankmachine4_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine4_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine4_replace) begin
+        main_litedramcore_bankmachine4_wrport_adr <= (main_litedramcore_bankmachine4_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine4_wrport_adr <= main_litedramcore_bankmachine4_produce;
+    end
+end
+assign main_litedramcore_bankmachine4_wrport_dat_w = main_litedramcore_bankmachine4_syncfifo4_din;
+assign main_litedramcore_bankmachine4_wrport_we = (main_litedramcore_bankmachine4_syncfifo4_we & (main_litedramcore_bankmachine4_syncfifo4_writable | main_litedramcore_bankmachine4_replace));
+assign main_litedramcore_bankmachine4_do_read = (main_litedramcore_bankmachine4_syncfifo4_readable & main_litedramcore_bankmachine4_syncfifo4_re);
+assign main_litedramcore_bankmachine4_rdport_adr = main_litedramcore_bankmachine4_consume;
+assign main_litedramcore_bankmachine4_syncfifo4_dout = main_litedramcore_bankmachine4_rdport_dat_r;
+assign main_litedramcore_bankmachine4_syncfifo4_writable = (main_litedramcore_bankmachine4_level != 5'd16);
+assign main_litedramcore_bankmachine4_syncfifo4_readable = (main_litedramcore_bankmachine4_level != 1'd0);
+assign main_litedramcore_bankmachine4_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine4_pipe_valid_source_valid) | main_litedramcore_bankmachine4_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine4_pipe_valid_sink_valid = main_litedramcore_bankmachine4_sink_sink_valid;
+assign main_litedramcore_bankmachine4_sink_sink_ready = main_litedramcore_bankmachine4_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine4_pipe_valid_sink_first = main_litedramcore_bankmachine4_sink_sink_first;
+assign main_litedramcore_bankmachine4_pipe_valid_sink_last = main_litedramcore_bankmachine4_sink_sink_last;
+assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_we = main_litedramcore_bankmachine4_sink_sink_payload_we;
+assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine4_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine4_source_source_valid = main_litedramcore_bankmachine4_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine4_pipe_valid_source_ready = main_litedramcore_bankmachine4_source_source_ready;
+assign main_litedramcore_bankmachine4_source_source_first = main_litedramcore_bankmachine4_pipe_valid_source_first;
+assign main_litedramcore_bankmachine4_source_source_last = main_litedramcore_bankmachine4_pipe_valid_source_last;
+assign main_litedramcore_bankmachine4_source_source_payload_we = main_litedramcore_bankmachine4_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine4_source_source_payload_addr = main_litedramcore_bankmachine4_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine4_next_state <= 4'd0;
+    builder_bankmachine4_next_state <= builder_bankmachine4_state;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                if (main_litedramcore_bankmachine4_cmd_ready) begin
+                    builder_bankmachine4_next_state <= 3'd5;
+                end
             end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                builder_bankmachine4_next_state <= 3'd5;
+            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine3_trccon_ready) begin
-                litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                if (main_litedramcore_bankmachine4_cmd_ready) begin
+                    builder_bankmachine4_next_state <= 3'd7;
+                end
             end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine4_refresh_req)) begin
+                builder_bankmachine4_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine4_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine4_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine4_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine4_next_state <= 1'd0;
         end
         default: begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
+                builder_bankmachine4_next_state <= 3'd4;
+            end else begin
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if ((main_litedramcore_bankmachine4_cmd_ready & main_litedramcore_bankmachine4_auto_precharge)) begin
+                                builder_bankmachine4_next_state <= 2'd2;
+                            end
+                        end else begin
+                            builder_bankmachine4_next_state <= 1'd1;
+                        end
+                    end else begin
+                        builder_bankmachine4_next_state <= 2'd3;
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine3_state)
+    main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
-                litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
-            end
         end
         2'd2: begin
         end
@@ -7014,13 +7609,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            if (litedramcore_bankmachine3_source_source_payload_we) begin
-                                litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
+                                main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -7032,139 +7627,38 @@ always @(*) begin
         end
     endcase
 end
-assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid;
-assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready;
-assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we;
-assign litedramcore_bankmachine4_sink_payload_addr = litedramcore_bankmachine4_req_addr;
-assign litedramcore_bankmachine4_sink_sink_valid = litedramcore_bankmachine4_source_valid;
-assign litedramcore_bankmachine4_source_ready = litedramcore_bankmachine4_sink_sink_ready;
-assign litedramcore_bankmachine4_sink_sink_first = litedramcore_bankmachine4_source_first;
-assign litedramcore_bankmachine4_sink_sink_last = litedramcore_bankmachine4_source_last;
-assign litedramcore_bankmachine4_sink_sink_payload_we = litedramcore_bankmachine4_source_payload_we;
-assign litedramcore_bankmachine4_sink_sink_payload_addr = litedramcore_bankmachine4_source_payload_addr;
-assign litedramcore_bankmachine4_source_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
-assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_source_valid | litedramcore_bankmachine4_source_source_valid);
-assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_source_source_payload_addr[20:7]);
-assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
-always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_a <= 14'd0;
-    if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
-        litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_source_source_payload_addr[20:7];
-    end else begin
-        litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
-assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
-assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
-always @(*) begin
-    litedramcore_bankmachine4_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine4_source_valid & litedramcore_bankmachine4_source_source_valid)) begin
-        if ((litedramcore_bankmachine4_source_payload_addr[20:7] != litedramcore_bankmachine4_source_source_payload_addr[20:7])) begin
-            litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine4_syncfifo4_din = {litedramcore_bankmachine4_fifo_in_last, litedramcore_bankmachine4_fifo_in_first, litedramcore_bankmachine4_fifo_in_payload_addr, litedramcore_bankmachine4_fifo_in_payload_we};
-assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
-assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
-assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
-assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
-assign litedramcore_bankmachine4_sink_ready = litedramcore_bankmachine4_syncfifo4_writable;
-assign litedramcore_bankmachine4_syncfifo4_we = litedramcore_bankmachine4_sink_valid;
-assign litedramcore_bankmachine4_fifo_in_first = litedramcore_bankmachine4_sink_first;
-assign litedramcore_bankmachine4_fifo_in_last = litedramcore_bankmachine4_sink_last;
-assign litedramcore_bankmachine4_fifo_in_payload_we = litedramcore_bankmachine4_sink_payload_we;
-assign litedramcore_bankmachine4_fifo_in_payload_addr = litedramcore_bankmachine4_sink_payload_addr;
-assign litedramcore_bankmachine4_source_valid = litedramcore_bankmachine4_syncfifo4_readable;
-assign litedramcore_bankmachine4_source_first = litedramcore_bankmachine4_fifo_out_first;
-assign litedramcore_bankmachine4_source_last = litedramcore_bankmachine4_fifo_out_last;
-assign litedramcore_bankmachine4_source_payload_we = litedramcore_bankmachine4_fifo_out_payload_we;
-assign litedramcore_bankmachine4_source_payload_addr = litedramcore_bankmachine4_fifo_out_payload_addr;
-assign litedramcore_bankmachine4_syncfifo4_re = litedramcore_bankmachine4_source_ready;
-always @(*) begin
-    litedramcore_bankmachine4_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine4_replace) begin
-        litedramcore_bankmachine4_wrport_adr <= (litedramcore_bankmachine4_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine4_wrport_adr <= litedramcore_bankmachine4_produce;
-    end
-end
-assign litedramcore_bankmachine4_wrport_dat_w = litedramcore_bankmachine4_syncfifo4_din;
-assign litedramcore_bankmachine4_wrport_we = (litedramcore_bankmachine4_syncfifo4_we & (litedramcore_bankmachine4_syncfifo4_writable | litedramcore_bankmachine4_replace));
-assign litedramcore_bankmachine4_do_read = (litedramcore_bankmachine4_syncfifo4_readable & litedramcore_bankmachine4_syncfifo4_re);
-assign litedramcore_bankmachine4_rdport_adr = litedramcore_bankmachine4_consume;
-assign litedramcore_bankmachine4_syncfifo4_dout = litedramcore_bankmachine4_rdport_dat_r;
-assign litedramcore_bankmachine4_syncfifo4_writable = (litedramcore_bankmachine4_level != 5'd16);
-assign litedramcore_bankmachine4_syncfifo4_readable = (litedramcore_bankmachine4_level != 1'd0);
-assign litedramcore_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready);
-assign litedramcore_bankmachine4_pipe_valid_sink_valid = litedramcore_bankmachine4_sink_sink_valid;
-assign litedramcore_bankmachine4_sink_sink_ready = litedramcore_bankmachine4_pipe_valid_sink_ready;
-assign litedramcore_bankmachine4_pipe_valid_sink_first = litedramcore_bankmachine4_sink_sink_first;
-assign litedramcore_bankmachine4_pipe_valid_sink_last = litedramcore_bankmachine4_sink_sink_last;
-assign litedramcore_bankmachine4_pipe_valid_sink_payload_we = litedramcore_bankmachine4_sink_sink_payload_we;
-assign litedramcore_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_bankmachine4_sink_sink_payload_addr;
-assign litedramcore_bankmachine4_source_source_valid = litedramcore_bankmachine4_pipe_valid_source_valid;
-assign litedramcore_bankmachine4_pipe_valid_source_ready = litedramcore_bankmachine4_source_source_ready;
-assign litedramcore_bankmachine4_source_source_first = litedramcore_bankmachine4_pipe_valid_source_first;
-assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_pipe_valid_source_last;
-assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine4_next_state <= 4'd0;
-    litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
-    case (litedramcore_bankmachine4_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                if (litedramcore_bankmachine4_cmd_ready) begin
-                    litedramcore_bankmachine4_next_state <= 3'd5;
-                end
-            end
+always @(*) begin
+    main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine4_state)
+        1'd1: begin
         end
         2'd2: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                if (litedramcore_bankmachine4_cmd_ready) begin
-                    litedramcore_bankmachine4_next_state <= 3'd7;
-                end
-            end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine4_refresh_req)) begin
-                litedramcore_bankmachine4_next_state <= 1'd0;
-            end
         end
         3'd5: begin
-            litedramcore_bankmachine4_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine4_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine4_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine4_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
-                litedramcore_bankmachine4_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
-                                litedramcore_bankmachine4_next_state <= 2'd2;
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
+                                main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready;
+                            end else begin
                             end
                         end else begin
-                            litedramcore_bankmachine4_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine4_next_state <= 2'd3;
                     end
                 end
             end
@@ -7172,8 +7666,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7191,14 +7685,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
+                                main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready;
                             end
                         end else begin
                         end
@@ -7210,8 +7704,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7219,8 +7713,8 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine4_twtpcon_ready) begin
-                litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+            if (main_litedramcore_bankmachine4_twtpcon_ready) begin
+                main_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
             end
         end
         3'd5: begin
@@ -7236,15 +7730,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_row_open <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_row_open <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -7262,18 +7756,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_valid <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -7287,12 +7781,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            litedramcore_bankmachine4_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -7303,18 +7797,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_row_close <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_row_close <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            litedramcore_bankmachine4_row_close <= 1'd1;
+            main_litedramcore_bankmachine4_row_close <= 1'd1;
         end
         2'd2: begin
-            litedramcore_bankmachine4_row_close <= 1'd1;
+            main_litedramcore_bankmachine4_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            litedramcore_bankmachine4_row_close <= 1'd1;
+            main_litedramcore_bankmachine4_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -7329,15 +7823,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -7355,8 +7849,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7374,12 +7868,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -7390,18 +7884,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -7419,11 +7913,11 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
@@ -7441,13 +7935,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
-                                litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
+                                main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -7460,22 +7954,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -7490,8 +7984,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine4_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7509,14 +8003,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -7527,38 +8021,139 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+assign main_litedramcore_bankmachine5_sink_valid = main_litedramcore_bankmachine5_req_valid;
+assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_sink_ready;
+assign main_litedramcore_bankmachine5_sink_payload_we = main_litedramcore_bankmachine5_req_we;
+assign main_litedramcore_bankmachine5_sink_payload_addr = main_litedramcore_bankmachine5_req_addr;
+assign main_litedramcore_bankmachine5_sink_sink_valid = main_litedramcore_bankmachine5_source_valid;
+assign main_litedramcore_bankmachine5_source_ready = main_litedramcore_bankmachine5_sink_sink_ready;
+assign main_litedramcore_bankmachine5_sink_sink_first = main_litedramcore_bankmachine5_source_first;
+assign main_litedramcore_bankmachine5_sink_sink_last = main_litedramcore_bankmachine5_source_last;
+assign main_litedramcore_bankmachine5_sink_sink_payload_we = main_litedramcore_bankmachine5_source_payload_we;
+assign main_litedramcore_bankmachine5_sink_sink_payload_addr = main_litedramcore_bankmachine5_source_payload_addr;
+assign main_litedramcore_bankmachine5_source_source_ready = (main_litedramcore_bankmachine5_req_wdata_ready | main_litedramcore_bankmachine5_req_rdata_valid);
+assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_source_valid | main_litedramcore_bankmachine5_source_source_valid);
+assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_source_source_payload_addr[20:7]);
+assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
+always @(*) begin
+    main_litedramcore_bankmachine5_cmd_payload_a <= 14'd0;
+    if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine5_cmd_payload_a <= main_litedramcore_bankmachine5_source_source_payload_addr[20:7];
+    end else begin
+        main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write);
+assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
+assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine5_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine5_source_valid & main_litedramcore_bankmachine5_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine5_source_payload_addr[20:7] != main_litedramcore_bankmachine5_source_source_payload_addr[20:7])) begin
+            main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine5_syncfifo5_din = {main_litedramcore_bankmachine5_fifo_in_last, main_litedramcore_bankmachine5_fifo_in_first, main_litedramcore_bankmachine5_fifo_in_payload_addr, main_litedramcore_bankmachine5_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout;
+assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout;
+assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout;
+assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout;
+assign main_litedramcore_bankmachine5_sink_ready = main_litedramcore_bankmachine5_syncfifo5_writable;
+assign main_litedramcore_bankmachine5_syncfifo5_we = main_litedramcore_bankmachine5_sink_valid;
+assign main_litedramcore_bankmachine5_fifo_in_first = main_litedramcore_bankmachine5_sink_first;
+assign main_litedramcore_bankmachine5_fifo_in_last = main_litedramcore_bankmachine5_sink_last;
+assign main_litedramcore_bankmachine5_fifo_in_payload_we = main_litedramcore_bankmachine5_sink_payload_we;
+assign main_litedramcore_bankmachine5_fifo_in_payload_addr = main_litedramcore_bankmachine5_sink_payload_addr;
+assign main_litedramcore_bankmachine5_source_valid = main_litedramcore_bankmachine5_syncfifo5_readable;
+assign main_litedramcore_bankmachine5_source_first = main_litedramcore_bankmachine5_fifo_out_first;
+assign main_litedramcore_bankmachine5_source_last = main_litedramcore_bankmachine5_fifo_out_last;
+assign main_litedramcore_bankmachine5_source_payload_we = main_litedramcore_bankmachine5_fifo_out_payload_we;
+assign main_litedramcore_bankmachine5_source_payload_addr = main_litedramcore_bankmachine5_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine5_syncfifo5_re = main_litedramcore_bankmachine5_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine5_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine5_replace) begin
+        main_litedramcore_bankmachine5_wrport_adr <= (main_litedramcore_bankmachine5_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine5_wrport_adr <= main_litedramcore_bankmachine5_produce;
+    end
+end
+assign main_litedramcore_bankmachine5_wrport_dat_w = main_litedramcore_bankmachine5_syncfifo5_din;
+assign main_litedramcore_bankmachine5_wrport_we = (main_litedramcore_bankmachine5_syncfifo5_we & (main_litedramcore_bankmachine5_syncfifo5_writable | main_litedramcore_bankmachine5_replace));
+assign main_litedramcore_bankmachine5_do_read = (main_litedramcore_bankmachine5_syncfifo5_readable & main_litedramcore_bankmachine5_syncfifo5_re);
+assign main_litedramcore_bankmachine5_rdport_adr = main_litedramcore_bankmachine5_consume;
+assign main_litedramcore_bankmachine5_syncfifo5_dout = main_litedramcore_bankmachine5_rdport_dat_r;
+assign main_litedramcore_bankmachine5_syncfifo5_writable = (main_litedramcore_bankmachine5_level != 5'd16);
+assign main_litedramcore_bankmachine5_syncfifo5_readable = (main_litedramcore_bankmachine5_level != 1'd0);
+assign main_litedramcore_bankmachine5_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine5_pipe_valid_source_valid) | main_litedramcore_bankmachine5_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine5_pipe_valid_sink_valid = main_litedramcore_bankmachine5_sink_sink_valid;
+assign main_litedramcore_bankmachine5_sink_sink_ready = main_litedramcore_bankmachine5_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine5_pipe_valid_sink_first = main_litedramcore_bankmachine5_sink_sink_first;
+assign main_litedramcore_bankmachine5_pipe_valid_sink_last = main_litedramcore_bankmachine5_sink_sink_last;
+assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_we = main_litedramcore_bankmachine5_sink_sink_payload_we;
+assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine5_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine5_source_source_valid = main_litedramcore_bankmachine5_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine5_pipe_valid_source_ready = main_litedramcore_bankmachine5_source_source_ready;
+assign main_litedramcore_bankmachine5_source_source_first = main_litedramcore_bankmachine5_pipe_valid_source_first;
+assign main_litedramcore_bankmachine5_source_source_last = main_litedramcore_bankmachine5_pipe_valid_source_last;
+assign main_litedramcore_bankmachine5_source_source_payload_we = main_litedramcore_bankmachine5_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine5_source_source_payload_addr = main_litedramcore_bankmachine5_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine5_next_state <= 4'd0;
+    builder_bankmachine5_next_state <= builder_bankmachine5_state;
+    case (builder_bankmachine5_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                if (main_litedramcore_bankmachine5_cmd_ready) begin
+                    builder_bankmachine5_next_state <= 3'd5;
+                end
+            end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                builder_bankmachine5_next_state <= 3'd5;
+            end
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                if (main_litedramcore_bankmachine5_cmd_ready) begin
+                    builder_bankmachine5_next_state <= 3'd7;
+                end
+            end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine5_refresh_req)) begin
+                builder_bankmachine5_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine5_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine5_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine5_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine5_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
+                builder_bankmachine5_next_state <= 3'd4;
             end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
-                                litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
-                            end else begin
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin
+                                builder_bankmachine5_next_state <= 2'd2;
                             end
                         end else begin
+                            builder_bankmachine5_next_state <= 1'd1;
                         end
                     end else begin
+                        builder_bankmachine5_next_state <= 2'd3;
                     end
                 end
             end
@@ -7566,8 +8161,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine4_state)
+    main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7575,6 +8170,9 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
+            if (main_litedramcore_bankmachine5_twtpcon_ready) begin
+                main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -7585,157 +8183,70 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
-                                litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine5_row_open <= 1'd0;
+    case (builder_bankmachine5_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_row_open <= 1'd1;
             end
         end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
     endcase
 end
-assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid;
-assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready;
-assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we;
-assign litedramcore_bankmachine5_sink_payload_addr = litedramcore_bankmachine5_req_addr;
-assign litedramcore_bankmachine5_sink_sink_valid = litedramcore_bankmachine5_source_valid;
-assign litedramcore_bankmachine5_source_ready = litedramcore_bankmachine5_sink_sink_ready;
-assign litedramcore_bankmachine5_sink_sink_first = litedramcore_bankmachine5_source_first;
-assign litedramcore_bankmachine5_sink_sink_last = litedramcore_bankmachine5_source_last;
-assign litedramcore_bankmachine5_sink_sink_payload_we = litedramcore_bankmachine5_source_payload_we;
-assign litedramcore_bankmachine5_sink_sink_payload_addr = litedramcore_bankmachine5_source_payload_addr;
-assign litedramcore_bankmachine5_source_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
-assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_source_valid | litedramcore_bankmachine5_source_source_valid);
-assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_source_source_payload_addr[20:7]);
-assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
-always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_a <= 14'd0;
-    if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
-        litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_source_source_payload_addr[20:7];
-    end else begin
-        litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
-assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
-assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
-always @(*) begin
-    litedramcore_bankmachine5_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine5_source_valid & litedramcore_bankmachine5_source_source_valid)) begin
-        if ((litedramcore_bankmachine5_source_payload_addr[20:7] != litedramcore_bankmachine5_source_source_payload_addr[20:7])) begin
-            litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine5_syncfifo5_din = {litedramcore_bankmachine5_fifo_in_last, litedramcore_bankmachine5_fifo_in_first, litedramcore_bankmachine5_fifo_in_payload_addr, litedramcore_bankmachine5_fifo_in_payload_we};
-assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
-assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
-assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
-assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
-assign litedramcore_bankmachine5_sink_ready = litedramcore_bankmachine5_syncfifo5_writable;
-assign litedramcore_bankmachine5_syncfifo5_we = litedramcore_bankmachine5_sink_valid;
-assign litedramcore_bankmachine5_fifo_in_first = litedramcore_bankmachine5_sink_first;
-assign litedramcore_bankmachine5_fifo_in_last = litedramcore_bankmachine5_sink_last;
-assign litedramcore_bankmachine5_fifo_in_payload_we = litedramcore_bankmachine5_sink_payload_we;
-assign litedramcore_bankmachine5_fifo_in_payload_addr = litedramcore_bankmachine5_sink_payload_addr;
-assign litedramcore_bankmachine5_source_valid = litedramcore_bankmachine5_syncfifo5_readable;
-assign litedramcore_bankmachine5_source_first = litedramcore_bankmachine5_fifo_out_first;
-assign litedramcore_bankmachine5_source_last = litedramcore_bankmachine5_fifo_out_last;
-assign litedramcore_bankmachine5_source_payload_we = litedramcore_bankmachine5_fifo_out_payload_we;
-assign litedramcore_bankmachine5_source_payload_addr = litedramcore_bankmachine5_fifo_out_payload_addr;
-assign litedramcore_bankmachine5_syncfifo5_re = litedramcore_bankmachine5_source_ready;
-always @(*) begin
-    litedramcore_bankmachine5_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine5_replace) begin
-        litedramcore_bankmachine5_wrport_adr <= (litedramcore_bankmachine5_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine5_wrport_adr <= litedramcore_bankmachine5_produce;
-    end
-end
-assign litedramcore_bankmachine5_wrport_dat_w = litedramcore_bankmachine5_syncfifo5_din;
-assign litedramcore_bankmachine5_wrport_we = (litedramcore_bankmachine5_syncfifo5_we & (litedramcore_bankmachine5_syncfifo5_writable | litedramcore_bankmachine5_replace));
-assign litedramcore_bankmachine5_do_read = (litedramcore_bankmachine5_syncfifo5_readable & litedramcore_bankmachine5_syncfifo5_re);
-assign litedramcore_bankmachine5_rdport_adr = litedramcore_bankmachine5_consume;
-assign litedramcore_bankmachine5_syncfifo5_dout = litedramcore_bankmachine5_rdport_dat_r;
-assign litedramcore_bankmachine5_syncfifo5_writable = (litedramcore_bankmachine5_level != 5'd16);
-assign litedramcore_bankmachine5_syncfifo5_readable = (litedramcore_bankmachine5_level != 1'd0);
-assign litedramcore_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready);
-assign litedramcore_bankmachine5_pipe_valid_sink_valid = litedramcore_bankmachine5_sink_sink_valid;
-assign litedramcore_bankmachine5_sink_sink_ready = litedramcore_bankmachine5_pipe_valid_sink_ready;
-assign litedramcore_bankmachine5_pipe_valid_sink_first = litedramcore_bankmachine5_sink_sink_first;
-assign litedramcore_bankmachine5_pipe_valid_sink_last = litedramcore_bankmachine5_sink_sink_last;
-assign litedramcore_bankmachine5_pipe_valid_sink_payload_we = litedramcore_bankmachine5_sink_sink_payload_we;
-assign litedramcore_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_bankmachine5_sink_sink_payload_addr;
-assign litedramcore_bankmachine5_source_source_valid = litedramcore_bankmachine5_pipe_valid_source_valid;
-assign litedramcore_bankmachine5_pipe_valid_source_ready = litedramcore_bankmachine5_source_source_ready;
-assign litedramcore_bankmachine5_source_source_first = litedramcore_bankmachine5_pipe_valid_source_first;
-assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_pipe_valid_source_last;
-assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine5_next_state <= 4'd0;
-    litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
-    case (litedramcore_bankmachine5_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                if (litedramcore_bankmachine5_cmd_ready) begin
-                    litedramcore_bankmachine5_next_state <= 3'd5;
-                end
+always @(*) begin
+    main_litedramcore_bankmachine5_cmd_valid <= 1'd0;
+    case (builder_bankmachine5_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                if (litedramcore_bankmachine5_cmd_ready) begin
-                    litedramcore_bankmachine5_next_state <= 3'd7;
-                end
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine5_refresh_req)) begin
-                litedramcore_bankmachine5_next_state <= 1'd0;
-            end
         end
         3'd5: begin
-            litedramcore_bankmachine5_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine5_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine5_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine5_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
-                litedramcore_bankmachine5_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
-                                litedramcore_bankmachine5_next_state <= 2'd2;
-                            end
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
                         end else begin
-                            litedramcore_bankmachine5_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine5_next_state <= 2'd3;
                     end
                 end
             end
@@ -7743,15 +8254,41 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_row_close <= 1'd0;
+    case (builder_bankmachine5_state)
+        1'd1: begin
+            main_litedramcore_bankmachine5_row_close <= 1'd1;
+        end
+        2'd2: begin
+            main_litedramcore_bankmachine5_row_close <= 1'd1;
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            main_litedramcore_bankmachine5_row_close <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -7769,8 +8306,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7788,12 +8325,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -7804,18 +8341,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -7833,11 +8370,11 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
@@ -7855,13 +8392,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
-                                litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
+                                main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -7874,22 +8411,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -7904,8 +8441,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7923,14 +8460,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -7942,8 +8479,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7961,13 +8498,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
-                                litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
+                                main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -7980,8 +8517,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -7999,13 +8536,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
-                                litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
+                                main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -8018,8 +8555,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8037,14 +8574,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
+                                main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
                             end
                         end else begin
                         end
@@ -8055,42 +8592,155 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine5_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+assign main_litedramcore_bankmachine6_sink_valid = main_litedramcore_bankmachine6_req_valid;
+assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_sink_ready;
+assign main_litedramcore_bankmachine6_sink_payload_we = main_litedramcore_bankmachine6_req_we;
+assign main_litedramcore_bankmachine6_sink_payload_addr = main_litedramcore_bankmachine6_req_addr;
+assign main_litedramcore_bankmachine6_sink_sink_valid = main_litedramcore_bankmachine6_source_valid;
+assign main_litedramcore_bankmachine6_source_ready = main_litedramcore_bankmachine6_sink_sink_ready;
+assign main_litedramcore_bankmachine6_sink_sink_first = main_litedramcore_bankmachine6_source_first;
+assign main_litedramcore_bankmachine6_sink_sink_last = main_litedramcore_bankmachine6_source_last;
+assign main_litedramcore_bankmachine6_sink_sink_payload_we = main_litedramcore_bankmachine6_source_payload_we;
+assign main_litedramcore_bankmachine6_sink_sink_payload_addr = main_litedramcore_bankmachine6_source_payload_addr;
+assign main_litedramcore_bankmachine6_source_source_ready = (main_litedramcore_bankmachine6_req_wdata_ready | main_litedramcore_bankmachine6_req_rdata_valid);
+assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_source_valid | main_litedramcore_bankmachine6_source_source_valid);
+assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_source_source_payload_addr[20:7]);
+assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
+always @(*) begin
+    main_litedramcore_bankmachine6_cmd_payload_a <= 14'd0;
+    if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine6_cmd_payload_a <= main_litedramcore_bankmachine6_source_source_payload_addr[20:7];
+    end else begin
+        main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write);
+assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
+assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine6_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine6_source_valid & main_litedramcore_bankmachine6_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine6_source_payload_addr[20:7] != main_litedramcore_bankmachine6_source_source_payload_addr[20:7])) begin
+            main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine6_syncfifo6_din = {main_litedramcore_bankmachine6_fifo_in_last, main_litedramcore_bankmachine6_fifo_in_first, main_litedramcore_bankmachine6_fifo_in_payload_addr, main_litedramcore_bankmachine6_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout;
+assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout;
+assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout;
+assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout;
+assign main_litedramcore_bankmachine6_sink_ready = main_litedramcore_bankmachine6_syncfifo6_writable;
+assign main_litedramcore_bankmachine6_syncfifo6_we = main_litedramcore_bankmachine6_sink_valid;
+assign main_litedramcore_bankmachine6_fifo_in_first = main_litedramcore_bankmachine6_sink_first;
+assign main_litedramcore_bankmachine6_fifo_in_last = main_litedramcore_bankmachine6_sink_last;
+assign main_litedramcore_bankmachine6_fifo_in_payload_we = main_litedramcore_bankmachine6_sink_payload_we;
+assign main_litedramcore_bankmachine6_fifo_in_payload_addr = main_litedramcore_bankmachine6_sink_payload_addr;
+assign main_litedramcore_bankmachine6_source_valid = main_litedramcore_bankmachine6_syncfifo6_readable;
+assign main_litedramcore_bankmachine6_source_first = main_litedramcore_bankmachine6_fifo_out_first;
+assign main_litedramcore_bankmachine6_source_last = main_litedramcore_bankmachine6_fifo_out_last;
+assign main_litedramcore_bankmachine6_source_payload_we = main_litedramcore_bankmachine6_fifo_out_payload_we;
+assign main_litedramcore_bankmachine6_source_payload_addr = main_litedramcore_bankmachine6_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine6_syncfifo6_re = main_litedramcore_bankmachine6_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine6_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine6_replace) begin
+        main_litedramcore_bankmachine6_wrport_adr <= (main_litedramcore_bankmachine6_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine6_wrport_adr <= main_litedramcore_bankmachine6_produce;
+    end
+end
+assign main_litedramcore_bankmachine6_wrport_dat_w = main_litedramcore_bankmachine6_syncfifo6_din;
+assign main_litedramcore_bankmachine6_wrport_we = (main_litedramcore_bankmachine6_syncfifo6_we & (main_litedramcore_bankmachine6_syncfifo6_writable | main_litedramcore_bankmachine6_replace));
+assign main_litedramcore_bankmachine6_do_read = (main_litedramcore_bankmachine6_syncfifo6_readable & main_litedramcore_bankmachine6_syncfifo6_re);
+assign main_litedramcore_bankmachine6_rdport_adr = main_litedramcore_bankmachine6_consume;
+assign main_litedramcore_bankmachine6_syncfifo6_dout = main_litedramcore_bankmachine6_rdport_dat_r;
+assign main_litedramcore_bankmachine6_syncfifo6_writable = (main_litedramcore_bankmachine6_level != 5'd16);
+assign main_litedramcore_bankmachine6_syncfifo6_readable = (main_litedramcore_bankmachine6_level != 1'd0);
+assign main_litedramcore_bankmachine6_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine6_pipe_valid_source_valid) | main_litedramcore_bankmachine6_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine6_pipe_valid_sink_valid = main_litedramcore_bankmachine6_sink_sink_valid;
+assign main_litedramcore_bankmachine6_sink_sink_ready = main_litedramcore_bankmachine6_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine6_pipe_valid_sink_first = main_litedramcore_bankmachine6_sink_sink_first;
+assign main_litedramcore_bankmachine6_pipe_valid_sink_last = main_litedramcore_bankmachine6_sink_sink_last;
+assign main_litedramcore_bankmachine6_pipe_valid_sink_payload_we = main_litedramcore_bankmachine6_sink_sink_payload_we;
+assign main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine6_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine6_source_source_valid = main_litedramcore_bankmachine6_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine6_pipe_valid_source_ready = main_litedramcore_bankmachine6_source_source_ready;
+assign main_litedramcore_bankmachine6_source_source_first = main_litedramcore_bankmachine6_pipe_valid_source_first;
+assign main_litedramcore_bankmachine6_source_source_last = main_litedramcore_bankmachine6_pipe_valid_source_last;
+assign main_litedramcore_bankmachine6_source_source_payload_we = main_litedramcore_bankmachine6_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine6_source_source_payload_addr = main_litedramcore_bankmachine6_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine6_next_state <= 4'd0;
+    builder_bankmachine6_next_state <= builder_bankmachine6_state;
+    case (builder_bankmachine6_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                if (main_litedramcore_bankmachine6_cmd_ready) begin
+                    builder_bankmachine6_next_state <= 3'd5;
+                end
+            end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                builder_bankmachine6_next_state <= 3'd5;
+            end
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                if (main_litedramcore_bankmachine6_cmd_ready) begin
+                    builder_bankmachine6_next_state <= 3'd7;
+                end
+            end
         end
         3'd4: begin
-            if (litedramcore_bankmachine5_twtpcon_ready) begin
-                litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+            if ((~main_litedramcore_bankmachine6_refresh_req)) begin
+                builder_bankmachine6_next_state <= 1'd0;
             end
         end
         3'd5: begin
+            builder_bankmachine6_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine6_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine6_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine6_next_state <= 1'd0;
         end
         default: begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
+                builder_bankmachine6_next_state <= 3'd4;
+            end else begin
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if ((main_litedramcore_bankmachine6_cmd_ready & main_litedramcore_bankmachine6_auto_precharge)) begin
+                                builder_bankmachine6_next_state <= 2'd2;
+                            end
+                        end else begin
+                            builder_bankmachine6_next_state <= 1'd1;
+                        end
+                    end else begin
+                        builder_bankmachine6_next_state <= 2'd3;
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_row_open <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -8108,19 +8758,13 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
-            if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
-                litedramcore_bankmachine5_cmd_valid <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine5_trccon_ready) begin
-                litedramcore_bankmachine5_cmd_valid <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -8133,12 +8777,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            litedramcore_bankmachine5_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -8149,18 +8793,21 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine5_row_close <= 1'd0;
-    case (litedramcore_bankmachine5_state)
+    main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
-            litedramcore_bankmachine5_row_close <= 1'd1;
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+            end
         end
         2'd2: begin
-            litedramcore_bankmachine5_row_close <= 1'd1;
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+            end
         end
         3'd4: begin
-            litedramcore_bankmachine5_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -8174,139 +8821,41 @@ always @(*) begin
         end
     endcase
 end
-assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid;
-assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready;
-assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we;
-assign litedramcore_bankmachine6_sink_payload_addr = litedramcore_bankmachine6_req_addr;
-assign litedramcore_bankmachine6_sink_sink_valid = litedramcore_bankmachine6_source_valid;
-assign litedramcore_bankmachine6_source_ready = litedramcore_bankmachine6_sink_sink_ready;
-assign litedramcore_bankmachine6_sink_sink_first = litedramcore_bankmachine6_source_first;
-assign litedramcore_bankmachine6_sink_sink_last = litedramcore_bankmachine6_source_last;
-assign litedramcore_bankmachine6_sink_sink_payload_we = litedramcore_bankmachine6_source_payload_we;
-assign litedramcore_bankmachine6_sink_sink_payload_addr = litedramcore_bankmachine6_source_payload_addr;
-assign litedramcore_bankmachine6_source_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
-assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_source_valid | litedramcore_bankmachine6_source_source_valid);
-assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_source_source_payload_addr[20:7]);
-assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
-always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_a <= 14'd0;
-    if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
-        litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_source_source_payload_addr[20:7];
-    end else begin
-        litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
-assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
-assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
-always @(*) begin
-    litedramcore_bankmachine6_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine6_source_valid & litedramcore_bankmachine6_source_source_valid)) begin
-        if ((litedramcore_bankmachine6_source_payload_addr[20:7] != litedramcore_bankmachine6_source_source_payload_addr[20:7])) begin
-            litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine6_syncfifo6_din = {litedramcore_bankmachine6_fifo_in_last, litedramcore_bankmachine6_fifo_in_first, litedramcore_bankmachine6_fifo_in_payload_addr, litedramcore_bankmachine6_fifo_in_payload_we};
-assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
-assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
-assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
-assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
-assign litedramcore_bankmachine6_sink_ready = litedramcore_bankmachine6_syncfifo6_writable;
-assign litedramcore_bankmachine6_syncfifo6_we = litedramcore_bankmachine6_sink_valid;
-assign litedramcore_bankmachine6_fifo_in_first = litedramcore_bankmachine6_sink_first;
-assign litedramcore_bankmachine6_fifo_in_last = litedramcore_bankmachine6_sink_last;
-assign litedramcore_bankmachine6_fifo_in_payload_we = litedramcore_bankmachine6_sink_payload_we;
-assign litedramcore_bankmachine6_fifo_in_payload_addr = litedramcore_bankmachine6_sink_payload_addr;
-assign litedramcore_bankmachine6_source_valid = litedramcore_bankmachine6_syncfifo6_readable;
-assign litedramcore_bankmachine6_source_first = litedramcore_bankmachine6_fifo_out_first;
-assign litedramcore_bankmachine6_source_last = litedramcore_bankmachine6_fifo_out_last;
-assign litedramcore_bankmachine6_source_payload_we = litedramcore_bankmachine6_fifo_out_payload_we;
-assign litedramcore_bankmachine6_source_payload_addr = litedramcore_bankmachine6_fifo_out_payload_addr;
-assign litedramcore_bankmachine6_syncfifo6_re = litedramcore_bankmachine6_source_ready;
-always @(*) begin
-    litedramcore_bankmachine6_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine6_replace) begin
-        litedramcore_bankmachine6_wrport_adr <= (litedramcore_bankmachine6_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine6_wrport_adr <= litedramcore_bankmachine6_produce;
-    end
-end
-assign litedramcore_bankmachine6_wrport_dat_w = litedramcore_bankmachine6_syncfifo6_din;
-assign litedramcore_bankmachine6_wrport_we = (litedramcore_bankmachine6_syncfifo6_we & (litedramcore_bankmachine6_syncfifo6_writable | litedramcore_bankmachine6_replace));
-assign litedramcore_bankmachine6_do_read = (litedramcore_bankmachine6_syncfifo6_readable & litedramcore_bankmachine6_syncfifo6_re);
-assign litedramcore_bankmachine6_rdport_adr = litedramcore_bankmachine6_consume;
-assign litedramcore_bankmachine6_syncfifo6_dout = litedramcore_bankmachine6_rdport_dat_r;
-assign litedramcore_bankmachine6_syncfifo6_writable = (litedramcore_bankmachine6_level != 5'd16);
-assign litedramcore_bankmachine6_syncfifo6_readable = (litedramcore_bankmachine6_level != 1'd0);
-assign litedramcore_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready);
-assign litedramcore_bankmachine6_pipe_valid_sink_valid = litedramcore_bankmachine6_sink_sink_valid;
-assign litedramcore_bankmachine6_sink_sink_ready = litedramcore_bankmachine6_pipe_valid_sink_ready;
-assign litedramcore_bankmachine6_pipe_valid_sink_first = litedramcore_bankmachine6_sink_sink_first;
-assign litedramcore_bankmachine6_pipe_valid_sink_last = litedramcore_bankmachine6_sink_sink_last;
-assign litedramcore_bankmachine6_pipe_valid_sink_payload_we = litedramcore_bankmachine6_sink_sink_payload_we;
-assign litedramcore_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_bankmachine6_sink_sink_payload_addr;
-assign litedramcore_bankmachine6_source_source_valid = litedramcore_bankmachine6_pipe_valid_source_valid;
-assign litedramcore_bankmachine6_pipe_valid_source_ready = litedramcore_bankmachine6_source_source_ready;
-assign litedramcore_bankmachine6_source_source_first = litedramcore_bankmachine6_pipe_valid_source_first;
-assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_pipe_valid_source_last;
-assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine6_next_state <= 4'd0;
-    litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
-    case (litedramcore_bankmachine6_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                if (litedramcore_bankmachine6_cmd_ready) begin
-                    litedramcore_bankmachine6_next_state <= 3'd5;
-                end
+always @(*) begin
+    main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine6_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                if (litedramcore_bankmachine6_cmd_ready) begin
-                    litedramcore_bankmachine6_next_state <= 3'd7;
-                end
-            end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine6_refresh_req)) begin
-                litedramcore_bankmachine6_next_state <= 1'd0;
-            end
         end
         3'd5: begin
-            litedramcore_bankmachine6_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine6_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine6_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine6_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
-                litedramcore_bankmachine6_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
-                                litedramcore_bankmachine6_next_state <= 2'd2;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
+                                main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+                            end else begin
                             end
                         end else begin
-                            litedramcore_bankmachine6_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine6_next_state <= 2'd3;
                     end
                 end
             end
@@ -8314,56 +8863,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine6_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
-            end
-        end
-        3'd4: begin
+            main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -8378,12 +8893,9 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
-            end
         end
         2'd2: begin
         end
@@ -8400,14 +8912,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
-                                litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
                             end else begin
+                                main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -8419,38 +8931,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine6_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
-            end
-        end
-        3'd4: begin
-            litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8468,14 +8950,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
+                                main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
                             end else begin
-                                litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -8487,8 +8969,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8506,13 +8988,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
-                                litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
+                                main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -8525,8 +9007,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8544,14 +9026,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
-                                litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
                             end else begin
+                                main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
                             end
                         end else begin
                         end
@@ -8563,8 +9045,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8572,6 +9054,9 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
+            if (main_litedramcore_bankmachine6_twtpcon_ready) begin
+                main_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -8582,37 +9067,22 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            if (litedramcore_bankmachine6_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_row_open <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_row_open <= 1'd1;
+            end
         end
         3'd4: begin
-            if (litedramcore_bankmachine6_twtpcon_ready) begin
-                litedramcore_bankmachine6_refresh_gnt <= 1'd1;
-            end
         end
         3'd5: begin
         end
@@ -8627,15 +9097,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_row_open <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -8649,25 +9122,34 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine6_row_close <= 1'd0;
+    case (builder_bankmachine6_state)
         1'd1: begin
-            if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
-                litedramcore_bankmachine6_cmd_valid <= 1'd1;
-            end
+            main_litedramcore_bankmachine6_row_close <= 1'd1;
         end
         2'd2: begin
+            main_litedramcore_bankmachine6_row_close <= 1'd1;
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_cmd_valid <= 1'd1;
-            end
         end
         3'd4: begin
+            main_litedramcore_bankmachine6_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -8678,57 +9160,161 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine6_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine6_source_source_valid) begin
-                    if (litedramcore_bankmachine6_row_opened) begin
-                        if (litedramcore_bankmachine6_row_hit) begin
-                            litedramcore_bankmachine6_cmd_valid <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine6_row_close <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+assign main_litedramcore_bankmachine7_sink_valid = main_litedramcore_bankmachine7_req_valid;
+assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_sink_ready;
+assign main_litedramcore_bankmachine7_sink_payload_we = main_litedramcore_bankmachine7_req_we;
+assign main_litedramcore_bankmachine7_sink_payload_addr = main_litedramcore_bankmachine7_req_addr;
+assign main_litedramcore_bankmachine7_sink_sink_valid = main_litedramcore_bankmachine7_source_valid;
+assign main_litedramcore_bankmachine7_source_ready = main_litedramcore_bankmachine7_sink_sink_ready;
+assign main_litedramcore_bankmachine7_sink_sink_first = main_litedramcore_bankmachine7_source_first;
+assign main_litedramcore_bankmachine7_sink_sink_last = main_litedramcore_bankmachine7_source_last;
+assign main_litedramcore_bankmachine7_sink_sink_payload_we = main_litedramcore_bankmachine7_source_payload_we;
+assign main_litedramcore_bankmachine7_sink_sink_payload_addr = main_litedramcore_bankmachine7_source_payload_addr;
+assign main_litedramcore_bankmachine7_source_source_ready = (main_litedramcore_bankmachine7_req_wdata_ready | main_litedramcore_bankmachine7_req_rdata_valid);
+assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_source_valid | main_litedramcore_bankmachine7_source_source_valid);
+assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_source_source_payload_addr[20:7]);
+assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
+always @(*) begin
+    main_litedramcore_bankmachine7_cmd_payload_a <= 14'd0;
+    if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine7_cmd_payload_a <= main_litedramcore_bankmachine7_source_source_payload_addr[20:7];
+    end else begin
+        main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write);
+assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
+assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine7_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine7_source_valid & main_litedramcore_bankmachine7_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine7_source_payload_addr[20:7] != main_litedramcore_bankmachine7_source_source_payload_addr[20:7])) begin
+            main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine7_syncfifo7_din = {main_litedramcore_bankmachine7_fifo_in_last, main_litedramcore_bankmachine7_fifo_in_first, main_litedramcore_bankmachine7_fifo_in_payload_addr, main_litedramcore_bankmachine7_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout;
+assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout;
+assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout;
+assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout;
+assign main_litedramcore_bankmachine7_sink_ready = main_litedramcore_bankmachine7_syncfifo7_writable;
+assign main_litedramcore_bankmachine7_syncfifo7_we = main_litedramcore_bankmachine7_sink_valid;
+assign main_litedramcore_bankmachine7_fifo_in_first = main_litedramcore_bankmachine7_sink_first;
+assign main_litedramcore_bankmachine7_fifo_in_last = main_litedramcore_bankmachine7_sink_last;
+assign main_litedramcore_bankmachine7_fifo_in_payload_we = main_litedramcore_bankmachine7_sink_payload_we;
+assign main_litedramcore_bankmachine7_fifo_in_payload_addr = main_litedramcore_bankmachine7_sink_payload_addr;
+assign main_litedramcore_bankmachine7_source_valid = main_litedramcore_bankmachine7_syncfifo7_readable;
+assign main_litedramcore_bankmachine7_source_first = main_litedramcore_bankmachine7_fifo_out_first;
+assign main_litedramcore_bankmachine7_source_last = main_litedramcore_bankmachine7_fifo_out_last;
+assign main_litedramcore_bankmachine7_source_payload_we = main_litedramcore_bankmachine7_fifo_out_payload_we;
+assign main_litedramcore_bankmachine7_source_payload_addr = main_litedramcore_bankmachine7_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine7_syncfifo7_re = main_litedramcore_bankmachine7_source_ready;
+always @(*) begin
+    main_litedramcore_bankmachine7_wrport_adr <= 4'd0;
+    if (main_litedramcore_bankmachine7_replace) begin
+        main_litedramcore_bankmachine7_wrport_adr <= (main_litedramcore_bankmachine7_produce - 1'd1);
+    end else begin
+        main_litedramcore_bankmachine7_wrport_adr <= main_litedramcore_bankmachine7_produce;
+    end
+end
+assign main_litedramcore_bankmachine7_wrport_dat_w = main_litedramcore_bankmachine7_syncfifo7_din;
+assign main_litedramcore_bankmachine7_wrport_we = (main_litedramcore_bankmachine7_syncfifo7_we & (main_litedramcore_bankmachine7_syncfifo7_writable | main_litedramcore_bankmachine7_replace));
+assign main_litedramcore_bankmachine7_do_read = (main_litedramcore_bankmachine7_syncfifo7_readable & main_litedramcore_bankmachine7_syncfifo7_re);
+assign main_litedramcore_bankmachine7_rdport_adr = main_litedramcore_bankmachine7_consume;
+assign main_litedramcore_bankmachine7_syncfifo7_dout = main_litedramcore_bankmachine7_rdport_dat_r;
+assign main_litedramcore_bankmachine7_syncfifo7_writable = (main_litedramcore_bankmachine7_level != 5'd16);
+assign main_litedramcore_bankmachine7_syncfifo7_readable = (main_litedramcore_bankmachine7_level != 1'd0);
+assign main_litedramcore_bankmachine7_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine7_pipe_valid_source_valid) | main_litedramcore_bankmachine7_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine7_pipe_valid_sink_valid = main_litedramcore_bankmachine7_sink_sink_valid;
+assign main_litedramcore_bankmachine7_sink_sink_ready = main_litedramcore_bankmachine7_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine7_pipe_valid_sink_first = main_litedramcore_bankmachine7_sink_sink_first;
+assign main_litedramcore_bankmachine7_pipe_valid_sink_last = main_litedramcore_bankmachine7_sink_sink_last;
+assign main_litedramcore_bankmachine7_pipe_valid_sink_payload_we = main_litedramcore_bankmachine7_sink_sink_payload_we;
+assign main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine7_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine7_source_source_valid = main_litedramcore_bankmachine7_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine7_pipe_valid_source_ready = main_litedramcore_bankmachine7_source_source_ready;
+assign main_litedramcore_bankmachine7_source_source_first = main_litedramcore_bankmachine7_pipe_valid_source_first;
+assign main_litedramcore_bankmachine7_source_source_last = main_litedramcore_bankmachine7_pipe_valid_source_last;
+assign main_litedramcore_bankmachine7_source_source_payload_we = main_litedramcore_bankmachine7_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine7_source_source_payload_addr = main_litedramcore_bankmachine7_pipe_valid_source_payload_addr;
+always @(*) begin
+    builder_bankmachine7_next_state <= 4'd0;
+    builder_bankmachine7_next_state <= builder_bankmachine7_state;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            litedramcore_bankmachine6_row_close <= 1'd1;
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                if (main_litedramcore_bankmachine7_cmd_ready) begin
+                    builder_bankmachine7_next_state <= 3'd5;
+                end
+            end
         end
         2'd2: begin
-            litedramcore_bankmachine6_row_close <= 1'd1;
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                builder_bankmachine7_next_state <= 3'd5;
+            end
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                if (main_litedramcore_bankmachine7_cmd_ready) begin
+                    builder_bankmachine7_next_state <= 3'd7;
+                end
+            end
         end
         3'd4: begin
-            litedramcore_bankmachine6_row_close <= 1'd1;
+            if ((~main_litedramcore_bankmachine7_refresh_req)) begin
+                builder_bankmachine7_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine7_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine7_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine7_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine7_next_state <= 1'd0;
         end
         default: begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
+                builder_bankmachine7_next_state <= 3'd4;
+            end else begin
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if ((main_litedramcore_bankmachine7_cmd_ready & main_litedramcore_bankmachine7_auto_precharge)) begin
+                                builder_bankmachine7_next_state <= 2'd2;
+                            end
+                        end else begin
+                            builder_bankmachine7_next_state <= 1'd1;
+                        end
+                    end else begin
+                        builder_bankmachine7_next_state <= 2'd3;
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine6_state)
+    main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -8745,139 +9331,41 @@ always @(*) begin
         end
     endcase
 end
-assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid;
-assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready;
-assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we;
-assign litedramcore_bankmachine7_sink_payload_addr = litedramcore_bankmachine7_req_addr;
-assign litedramcore_bankmachine7_sink_sink_valid = litedramcore_bankmachine7_source_valid;
-assign litedramcore_bankmachine7_source_ready = litedramcore_bankmachine7_sink_sink_ready;
-assign litedramcore_bankmachine7_sink_sink_first = litedramcore_bankmachine7_source_first;
-assign litedramcore_bankmachine7_sink_sink_last = litedramcore_bankmachine7_source_last;
-assign litedramcore_bankmachine7_sink_sink_payload_we = litedramcore_bankmachine7_source_payload_we;
-assign litedramcore_bankmachine7_sink_sink_payload_addr = litedramcore_bankmachine7_source_payload_addr;
-assign litedramcore_bankmachine7_source_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
-assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_source_valid | litedramcore_bankmachine7_source_source_valid);
-assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_source_source_payload_addr[20:7]);
-assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
-always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_a <= 14'd0;
-    if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
-        litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_source_source_payload_addr[20:7];
-    end else begin
-        litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
-assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
-assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
-always @(*) begin
-    litedramcore_bankmachine7_auto_precharge <= 1'd0;
-    if ((litedramcore_bankmachine7_source_valid & litedramcore_bankmachine7_source_source_valid)) begin
-        if ((litedramcore_bankmachine7_source_payload_addr[20:7] != litedramcore_bankmachine7_source_source_payload_addr[20:7])) begin
-            litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
-        end
-    end
-end
-assign litedramcore_bankmachine7_syncfifo7_din = {litedramcore_bankmachine7_fifo_in_last, litedramcore_bankmachine7_fifo_in_first, litedramcore_bankmachine7_fifo_in_payload_addr, litedramcore_bankmachine7_fifo_in_payload_we};
-assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
-assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
-assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
-assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
-assign litedramcore_bankmachine7_sink_ready = litedramcore_bankmachine7_syncfifo7_writable;
-assign litedramcore_bankmachine7_syncfifo7_we = litedramcore_bankmachine7_sink_valid;
-assign litedramcore_bankmachine7_fifo_in_first = litedramcore_bankmachine7_sink_first;
-assign litedramcore_bankmachine7_fifo_in_last = litedramcore_bankmachine7_sink_last;
-assign litedramcore_bankmachine7_fifo_in_payload_we = litedramcore_bankmachine7_sink_payload_we;
-assign litedramcore_bankmachine7_fifo_in_payload_addr = litedramcore_bankmachine7_sink_payload_addr;
-assign litedramcore_bankmachine7_source_valid = litedramcore_bankmachine7_syncfifo7_readable;
-assign litedramcore_bankmachine7_source_first = litedramcore_bankmachine7_fifo_out_first;
-assign litedramcore_bankmachine7_source_last = litedramcore_bankmachine7_fifo_out_last;
-assign litedramcore_bankmachine7_source_payload_we = litedramcore_bankmachine7_fifo_out_payload_we;
-assign litedramcore_bankmachine7_source_payload_addr = litedramcore_bankmachine7_fifo_out_payload_addr;
-assign litedramcore_bankmachine7_syncfifo7_re = litedramcore_bankmachine7_source_ready;
-always @(*) begin
-    litedramcore_bankmachine7_wrport_adr <= 4'd0;
-    if (litedramcore_bankmachine7_replace) begin
-        litedramcore_bankmachine7_wrport_adr <= (litedramcore_bankmachine7_produce - 1'd1);
-    end else begin
-        litedramcore_bankmachine7_wrport_adr <= litedramcore_bankmachine7_produce;
-    end
-end
-assign litedramcore_bankmachine7_wrport_dat_w = litedramcore_bankmachine7_syncfifo7_din;
-assign litedramcore_bankmachine7_wrport_we = (litedramcore_bankmachine7_syncfifo7_we & (litedramcore_bankmachine7_syncfifo7_writable | litedramcore_bankmachine7_replace));
-assign litedramcore_bankmachine7_do_read = (litedramcore_bankmachine7_syncfifo7_readable & litedramcore_bankmachine7_syncfifo7_re);
-assign litedramcore_bankmachine7_rdport_adr = litedramcore_bankmachine7_consume;
-assign litedramcore_bankmachine7_syncfifo7_dout = litedramcore_bankmachine7_rdport_dat_r;
-assign litedramcore_bankmachine7_syncfifo7_writable = (litedramcore_bankmachine7_level != 5'd16);
-assign litedramcore_bankmachine7_syncfifo7_readable = (litedramcore_bankmachine7_level != 1'd0);
-assign litedramcore_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready);
-assign litedramcore_bankmachine7_pipe_valid_sink_valid = litedramcore_bankmachine7_sink_sink_valid;
-assign litedramcore_bankmachine7_sink_sink_ready = litedramcore_bankmachine7_pipe_valid_sink_ready;
-assign litedramcore_bankmachine7_pipe_valid_sink_first = litedramcore_bankmachine7_sink_sink_first;
-assign litedramcore_bankmachine7_pipe_valid_sink_last = litedramcore_bankmachine7_sink_sink_last;
-assign litedramcore_bankmachine7_pipe_valid_sink_payload_we = litedramcore_bankmachine7_sink_sink_payload_we;
-assign litedramcore_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_bankmachine7_sink_sink_payload_addr;
-assign litedramcore_bankmachine7_source_source_valid = litedramcore_bankmachine7_pipe_valid_source_valid;
-assign litedramcore_bankmachine7_pipe_valid_source_ready = litedramcore_bankmachine7_source_source_ready;
-assign litedramcore_bankmachine7_source_source_first = litedramcore_bankmachine7_pipe_valid_source_first;
-assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_pipe_valid_source_last;
-assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we;
-assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr;
-always @(*) begin
-    litedramcore_bankmachine7_next_state <= 4'd0;
-    litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
-    case (litedramcore_bankmachine7_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                if (litedramcore_bankmachine7_cmd_ready) begin
-                    litedramcore_bankmachine7_next_state <= 3'd5;
-                end
+always @(*) begin
+    main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine7_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
             end
         end
         2'd2: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_next_state <= 3'd5;
-            end
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                if (litedramcore_bankmachine7_cmd_ready) begin
-                    litedramcore_bankmachine7_next_state <= 3'd7;
-                end
-            end
         end
         3'd4: begin
-            if ((~litedramcore_bankmachine7_refresh_req)) begin
-                litedramcore_bankmachine7_next_state <= 1'd0;
-            end
         end
         3'd5: begin
-            litedramcore_bankmachine7_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_bankmachine7_next_state <= 2'd3;
         end
         3'd7: begin
-            litedramcore_bankmachine7_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_bankmachine7_next_state <= 1'd0;
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
-                litedramcore_bankmachine7_next_state <= 3'd4;
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
-                                litedramcore_bankmachine7_next_state <= 2'd2;
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
+                                main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+                            end else begin
                             end
                         end else begin
-                            litedramcore_bankmachine7_next_state <= 1'd1;
                         end
                     end else begin
-                        litedramcore_bankmachine7_next_state <= 2'd3;
                     end
                 end
             end
@@ -8885,22 +9373,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
-            litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+            main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -8915,8 +9403,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8934,14 +9422,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -8953,8 +9441,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -8972,13 +9460,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
-                                litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
+                                main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -8991,8 +9479,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9010,13 +9498,13 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
-                                litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
+                                main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -9029,8 +9517,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9048,14 +9536,14 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
                             end else begin
-                                litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
+                                main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
                             end
                         end else begin
                         end
@@ -9067,8 +9555,8 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_refresh_gnt <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9076,8 +9564,8 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
-            if (litedramcore_bankmachine7_twtpcon_ready) begin
-                litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+            if (main_litedramcore_bankmachine7_twtpcon_ready) begin
+                main_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
             end
         end
         3'd5: begin
@@ -9093,15 +9581,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_row_open <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_row_open <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_row_open <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -9119,18 +9607,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_valid <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_cmd_valid <= 1'd1;
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_cmd_valid <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -9144,12 +9632,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            litedramcore_bankmachine7_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -9160,67 +9648,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_row_close <= 1'd0;
-    case (litedramcore_bankmachine7_state)
-        1'd1: begin
-            litedramcore_bankmachine7_row_close <= 1'd1;
-        end
-        2'd2: begin
-            litedramcore_bankmachine7_row_close <= 1'd1;
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            litedramcore_bankmachine7_row_close <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
-    case (litedramcore_bankmachine7_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_row_close <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd2: begin
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -9231,34 +9670,19 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (litedramcore_bankmachine7_trccon_ready) begin
-                litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -9276,12 +9700,9 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
-    case (litedramcore_bankmachine7_state)
+    main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine7_state)
         1'd1: begin
-            if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
-                litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
-            end
         end
         2'd2: begin
         end
@@ -9298,15 +9719,12 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
             end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            if (litedramcore_bankmachine7_source_source_payload_we) begin
-                                litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
-                            end else begin
-                            end
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -9316,266 +9734,266 @@ always @(*) begin
         end
     endcase
 end
-assign litedramcore_rdcmdphase = (a7ddrphy_rdphase_storage - 1'd1);
-assign litedramcore_wrcmdphase = (a7ddrphy_wrphase_storage - 1'd1);
-assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
-assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
-assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready);
-assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read));
-assign litedramcore_cas_allowed = litedramcore_tccdcon_ready;
-assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
-assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read));
-assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write));
-assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0);
-assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0);
-assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt);
-assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata};
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign main_litedramcore_nphases = (main_a7ddrphy_rdphase_storage - 1'd1);
+assign main_litedramcore_rdphase = (main_a7ddrphy_wrphase_storage - 1'd1);
+assign main_litedramcore_trrdcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we)));
+assign main_litedramcore_tfawcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we)));
+assign main_litedramcore_ras_allowed = (main_litedramcore_trrdcon_ready & main_litedramcore_tfawcon_ready);
+assign main_litedramcore_tccdcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_cmd_payload_is_write | main_litedramcore_choose_req_cmd_payload_is_read));
+assign main_litedramcore_cas_allowed = main_litedramcore_tccdcon_ready;
+assign main_litedramcore_twtrcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+assign main_litedramcore_read_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_read) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_read)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_read)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_read)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_read)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_read)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_read)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_read));
+assign main_litedramcore_write_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_write) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_write)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_write)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_write)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_write)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_write)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_write)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_write));
+assign main_litedramcore_max_time0 = (main_litedramcore_time0 == 1'd0);
+assign main_litedramcore_max_time1 = (main_litedramcore_time1 == 1'd0);
+assign main_litedramcore_bankmachine0_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine1_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine2_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine3_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine4_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine5_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine6_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine7_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_go_to_refresh = (((((((main_litedramcore_bankmachine0_refresh_gnt & main_litedramcore_bankmachine1_refresh_gnt) & main_litedramcore_bankmachine2_refresh_gnt) & main_litedramcore_bankmachine3_refresh_gnt) & main_litedramcore_bankmachine4_refresh_gnt) & main_litedramcore_bankmachine5_refresh_gnt) & main_litedramcore_bankmachine6_refresh_gnt) & main_litedramcore_bankmachine7_refresh_gnt);
+assign main_litedramcore_interface_rdata = {main_litedramcore_dfi_p3_rddata, main_litedramcore_dfi_p2_rddata, main_litedramcore_dfi_p1_rddata, main_litedramcore_dfi_p0_rddata};
+assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
+assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
+assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
+assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
+assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
+assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
+assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
+assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
 always @(*) begin
-    litedramcore_choose_cmd_valids <= 8'd0;
-    litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
-    litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids <= 8'd0;
+    main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+    main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
 end
-assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
-assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
-assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1;
-assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
-assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
-assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
-assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
+assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids;
+assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_self0;
+assign main_litedramcore_choose_cmd_cmd_payload_a = builder_rhs_self1;
+assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_self2;
+assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_self3;
+assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_self4;
+assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_self5;
 always @(*) begin
-    litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
-    if (litedramcore_choose_cmd_cmd_valid) begin
-        litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
+    main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
+    if (main_litedramcore_choose_cmd_cmd_valid) begin
+        main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_self0;
     end
 end
 always @(*) begin
-    litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
-    if (litedramcore_choose_cmd_cmd_valid) begin
-        litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
+    main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
+    if (main_litedramcore_choose_cmd_cmd_valid) begin
+        main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_self1;
     end
 end
 always @(*) begin
-    litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
-    if (litedramcore_choose_cmd_cmd_valid) begin
-        litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
+    main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
+    if (main_litedramcore_choose_cmd_cmd_valid) begin
+        main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_self2;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine0_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
-        litedramcore_bankmachine0_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine0_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin
+        main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
-        litedramcore_bankmachine0_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin
+        main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine1_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
-        litedramcore_bankmachine1_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine1_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin
+        main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
-        litedramcore_bankmachine1_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin
+        main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine2_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
-        litedramcore_bankmachine2_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine2_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin
+        main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
-        litedramcore_bankmachine2_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin
+        main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine3_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
-        litedramcore_bankmachine3_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine3_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin
+        main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
-        litedramcore_bankmachine3_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin
+        main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
-        litedramcore_bankmachine4_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine4_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin
+        main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
-        litedramcore_bankmachine4_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin
+        main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine5_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
-        litedramcore_bankmachine5_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine5_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin
+        main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
-        litedramcore_bankmachine5_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin
+        main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine6_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
-        litedramcore_bankmachine6_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine6_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin
+        main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
-        litedramcore_bankmachine6_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin
+        main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
     end
 end
 always @(*) begin
-    litedramcore_bankmachine7_cmd_ready <= 1'd0;
-    if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
-        litedramcore_bankmachine7_cmd_ready <= 1'd1;
+    main_litedramcore_bankmachine7_cmd_ready <= 1'd0;
+    if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin
+        main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
     end
-    if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
-        litedramcore_bankmachine7_cmd_ready <= 1'd1;
+    if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin
+        main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
     end
 end
-assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
+assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid));
 always @(*) begin
-    litedramcore_choose_req_valids <= 8'd0;
-    litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
-    litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids <= 8'd0;
+    main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+    main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
 end
-assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
-assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
-assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7;
-assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8;
-assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9;
-assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
-assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
+assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids;
+assign main_litedramcore_choose_req_cmd_valid = builder_rhs_self6;
+assign main_litedramcore_choose_req_cmd_payload_a = builder_rhs_self7;
+assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_self8;
+assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_self9;
+assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_self10;
+assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_self11;
 always @(*) begin
-    litedramcore_choose_req_cmd_payload_cas <= 1'd0;
-    if (litedramcore_choose_req_cmd_valid) begin
-        litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
+    main_litedramcore_choose_req_cmd_payload_cas <= 1'd0;
+    if (main_litedramcore_choose_req_cmd_valid) begin
+        main_litedramcore_choose_req_cmd_payload_cas <= builder_t_self3;
     end
 end
 always @(*) begin
-    litedramcore_choose_req_cmd_payload_ras <= 1'd0;
-    if (litedramcore_choose_req_cmd_valid) begin
-        litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
+    main_litedramcore_choose_req_cmd_payload_ras <= 1'd0;
+    if (main_litedramcore_choose_req_cmd_valid) begin
+        main_litedramcore_choose_req_cmd_payload_ras <= builder_t_self4;
     end
 end
 always @(*) begin
-    litedramcore_choose_req_cmd_payload_we <= 1'd0;
-    if (litedramcore_choose_req_cmd_valid) begin
-        litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
+    main_litedramcore_choose_req_cmd_payload_we <= 1'd0;
+    if (main_litedramcore_choose_req_cmd_valid) begin
+        main_litedramcore_choose_req_cmd_payload_we <= builder_t_self5;
     end
 end
-assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
-assign litedramcore_dfi_p0_reset_n = 1'd1;
-assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}};
-assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}};
-assign litedramcore_dfi_p1_reset_n = 1'd1;
-assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}};
-assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}};
-assign litedramcore_dfi_p2_reset_n = 1'd1;
-assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}};
-assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}};
-assign litedramcore_dfi_p3_reset_n = 1'd1;
-assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}};
-assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}};
-assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]);
+assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid));
+assign main_litedramcore_dfi_p0_reset_n = 1'd1;
+assign main_litedramcore_dfi_p0_cke = {1{main_litedramcore_steerer4}};
+assign main_litedramcore_dfi_p0_odt = {1{main_litedramcore_steerer5}};
+assign main_litedramcore_dfi_p1_reset_n = 1'd1;
+assign main_litedramcore_dfi_p1_cke = {1{main_litedramcore_steerer6}};
+assign main_litedramcore_dfi_p1_odt = {1{main_litedramcore_steerer7}};
+assign main_litedramcore_dfi_p2_reset_n = 1'd1;
+assign main_litedramcore_dfi_p2_cke = {1{main_litedramcore_steerer8}};
+assign main_litedramcore_dfi_p2_odt = {1{main_litedramcore_steerer9}};
+assign main_litedramcore_dfi_p3_reset_n = 1'd1;
+assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer10}};
+assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer11}};
+assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]);
 always @(*) begin
-    litedramcore_multiplexer_next_state <= 4'd0;
-    litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
-    case (litedramcore_multiplexer_state)
+    builder_multiplexer_next_state <= 4'd0;
+    builder_multiplexer_next_state <= builder_multiplexer_state;
+    case (builder_multiplexer_state)
         1'd1: begin
-            if (litedramcore_read_available) begin
-                if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
-                    litedramcore_multiplexer_next_state <= 2'd3;
+            if (main_litedramcore_read_available) begin
+                if (((~main_litedramcore_write_available) | main_litedramcore_max_time1)) begin
+                    builder_multiplexer_next_state <= 2'd3;
                 end
             end
-            if (litedramcore_go_to_refresh) begin
-                litedramcore_multiplexer_next_state <= 2'd2;
+            if (main_litedramcore_go_to_refresh) begin
+                builder_multiplexer_next_state <= 2'd2;
             end
         end
         2'd2: begin
-            if (litedramcore_cmd_last) begin
-                litedramcore_multiplexer_next_state <= 1'd0;
+            if (main_litedramcore_cmd_last) begin
+                builder_multiplexer_next_state <= 1'd0;
             end
         end
         2'd3: begin
-            if (litedramcore_twtrcon_ready) begin
-                litedramcore_multiplexer_next_state <= 1'd0;
+            if (main_litedramcore_twtrcon_ready) begin
+                builder_multiplexer_next_state <= 1'd0;
             end
         end
         3'd4: begin
-            litedramcore_multiplexer_next_state <= 3'd5;
+            builder_multiplexer_next_state <= 3'd5;
         end
         3'd5: begin
-            litedramcore_multiplexer_next_state <= 3'd6;
+            builder_multiplexer_next_state <= 3'd6;
         end
         3'd6: begin
-            litedramcore_multiplexer_next_state <= 3'd7;
+            builder_multiplexer_next_state <= 3'd7;
         end
         3'd7: begin
-            litedramcore_multiplexer_next_state <= 4'd8;
+            builder_multiplexer_next_state <= 4'd8;
         end
         4'd8: begin
-            litedramcore_multiplexer_next_state <= 4'd9;
+            builder_multiplexer_next_state <= 4'd9;
         end
         4'd9: begin
-            litedramcore_multiplexer_next_state <= 4'd10;
+            builder_multiplexer_next_state <= 4'd10;
         end
         4'd10: begin
-            litedramcore_multiplexer_next_state <= 1'd1;
+            builder_multiplexer_next_state <= 1'd1;
         end
         default: begin
-            if (litedramcore_write_available) begin
-                if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
-                    litedramcore_multiplexer_next_state <= 3'd4;
+            if (main_litedramcore_write_available) begin
+                if (((~main_litedramcore_read_available) | main_litedramcore_max_time0)) begin
+                    builder_multiplexer_next_state <= 3'd4;
                 end
             end
-            if (litedramcore_go_to_refresh) begin
-                litedramcore_multiplexer_next_state <= 2'd2;
+            if (main_litedramcore_go_to_refresh) begin
+                builder_multiplexer_next_state <= 2'd2;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_steerer_sel0 <= 2'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_steerer0 <= 2'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer_sel0 <= 1'd0;
-            if ((a7ddrphy_wrphase_storage == 1'd0)) begin
-                litedramcore_steerer_sel0 <= 2'd2;
+            main_litedramcore_steerer0 <= 1'd0;
+            if ((main_a7ddrphy_wrphase_storage == 1'd0)) begin
+                main_litedramcore_steerer0 <= 2'd2;
             end
-            if ((litedramcore_wrcmdphase == 1'd0)) begin
-                litedramcore_steerer_sel0 <= 1'd1;
+            if ((main_litedramcore_rdphase == 1'd0)) begin
+                main_litedramcore_steerer0 <= 1'd1;
             end
         end
         2'd2: begin
-            litedramcore_steerer_sel0 <= 2'd3;
+            main_litedramcore_steerer0 <= 2'd3;
         end
         2'd3: begin
         end
@@ -9594,23 +10012,23 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_steerer_sel0 <= 1'd0;
-            if ((a7ddrphy_rdphase_storage == 1'd0)) begin
-                litedramcore_steerer_sel0 <= 2'd2;
+            main_litedramcore_steerer0 <= 1'd0;
+            if ((main_a7ddrphy_rdphase_storage == 1'd0)) begin
+                main_litedramcore_steerer0 <= 2'd2;
             end
-            if ((litedramcore_rdcmdphase == 1'd0)) begin
-                litedramcore_steerer_sel0 <= 1'd1;
+            if ((main_litedramcore_nphases == 1'd0)) begin
+                main_litedramcore_steerer0 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_cmd_ready <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_cmd_ready <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
         end
         2'd2: begin
-            litedramcore_cmd_ready <= 1'd1;
+            main_litedramcore_cmd_ready <= 1'd1;
         end
         2'd3: begin
         end
@@ -9633,15 +10051,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_steerer_sel1 <= 2'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_steerer1 <= 2'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer_sel1 <= 1'd0;
-            if ((a7ddrphy_wrphase_storage == 1'd1)) begin
-                litedramcore_steerer_sel1 <= 2'd2;
+            main_litedramcore_steerer1 <= 1'd0;
+            if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin
+                main_litedramcore_steerer1 <= 2'd2;
             end
-            if ((litedramcore_wrcmdphase == 1'd1)) begin
-                litedramcore_steerer_sel1 <= 1'd1;
+            if ((main_litedramcore_rdphase == 1'd1)) begin
+                main_litedramcore_steerer1 <= 1'd1;
             end
         end
         2'd2: begin
@@ -9663,26 +10081,26 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_steerer_sel1 <= 1'd0;
-            if ((a7ddrphy_rdphase_storage == 1'd1)) begin
-                litedramcore_steerer_sel1 <= 2'd2;
+            main_litedramcore_steerer1 <= 1'd0;
+            if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin
+                main_litedramcore_steerer1 <= 2'd2;
             end
-            if ((litedramcore_rdcmdphase == 1'd1)) begin
-                litedramcore_steerer_sel1 <= 1'd1;
+            if ((main_litedramcore_nphases == 1'd1)) begin
+                main_litedramcore_steerer1 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_steerer_sel2 <= 2'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_steerer2 <= 2'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer_sel2 <= 1'd0;
-            if ((a7ddrphy_wrphase_storage == 2'd2)) begin
-                litedramcore_steerer_sel2 <= 2'd2;
+            main_litedramcore_steerer2 <= 1'd0;
+            if ((main_a7ddrphy_wrphase_storage == 2'd2)) begin
+                main_litedramcore_steerer2 <= 2'd2;
             end
-            if ((litedramcore_wrcmdphase == 2'd2)) begin
-                litedramcore_steerer_sel2 <= 1'd1;
+            if ((main_litedramcore_rdphase == 2'd2)) begin
+                main_litedramcore_steerer2 <= 1'd1;
             end
         end
         2'd2: begin
@@ -9704,23 +10122,23 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_steerer_sel2 <= 1'd0;
-            if ((a7ddrphy_rdphase_storage == 2'd2)) begin
-                litedramcore_steerer_sel2 <= 2'd2;
+            main_litedramcore_steerer2 <= 1'd0;
+            if ((main_a7ddrphy_rdphase_storage == 2'd2)) begin
+                main_litedramcore_steerer2 <= 2'd2;
             end
-            if ((litedramcore_rdcmdphase == 2'd2)) begin
-                litedramcore_steerer_sel2 <= 1'd1;
+            if ((main_litedramcore_nphases == 2'd2)) begin
+                main_litedramcore_steerer2 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_cmd_want_activates <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_choose_cmd_want_activates <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
             if (1'd0) begin
             end else begin
-                litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+                main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
             end
         end
         2'd2: begin
@@ -9744,21 +10162,21 @@ always @(*) begin
         default: begin
             if (1'd0) begin
             end else begin
-                litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+                main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_steerer_sel3 <= 2'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_steerer3 <= 2'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer_sel3 <= 1'd0;
-            if ((a7ddrphy_wrphase_storage == 2'd3)) begin
-                litedramcore_steerer_sel3 <= 2'd2;
+            main_litedramcore_steerer3 <= 1'd0;
+            if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin
+                main_litedramcore_steerer3 <= 2'd2;
             end
-            if ((litedramcore_wrcmdphase == 2'd3)) begin
-                litedramcore_steerer_sel3 <= 1'd1;
+            if ((main_litedramcore_rdphase == 2'd3)) begin
+                main_litedramcore_steerer3 <= 1'd1;
             end
         end
         2'd2: begin
@@ -9780,19 +10198,19 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_steerer_sel3 <= 1'd0;
-            if ((a7ddrphy_rdphase_storage == 2'd3)) begin
-                litedramcore_steerer_sel3 <= 2'd2;
+            main_litedramcore_steerer3 <= 1'd0;
+            if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin
+                main_litedramcore_steerer3 <= 2'd2;
             end
-            if ((litedramcore_rdcmdphase == 2'd3)) begin
-                litedramcore_steerer_sel3 <= 1'd1;
+            if ((main_litedramcore_nphases == 2'd3)) begin
+                main_litedramcore_steerer3 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_en0 <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_en0 <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9814,17 +10232,17 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_en0 <= 1'd1;
+            main_litedramcore_en0 <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_cmd_cmd_ready <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
             if (1'd0) begin
             end else begin
-                litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+                main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
             end
         end
         2'd2: begin
@@ -9848,14 +10266,14 @@ always @(*) begin
         default: begin
             if (1'd0) begin
             end else begin
-                litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+                main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_req_want_reads <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_choose_req_want_reads <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
         end
         2'd2: begin
@@ -9877,15 +10295,15 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            litedramcore_choose_req_want_reads <= 1'd1;
+            main_litedramcore_choose_req_want_reads <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_req_want_writes <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_choose_req_want_writes <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_choose_req_want_writes <= 1'd1;
+            main_litedramcore_choose_req_want_writes <= 1'd1;
         end
         2'd2: begin
         end
@@ -9910,14 +10328,10 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_choose_req_cmd_ready <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_en1 <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            if (1'd0) begin
-                litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
-            end else begin
-                litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
-            end
+            main_litedramcore_en1 <= 1'd1;
         end
         2'd2: begin
         end
@@ -9938,19 +10352,18 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            if (1'd0) begin
-                litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
-            end else begin
-                litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_en1 <= 1'd0;
-    case (litedramcore_multiplexer_state)
+    main_litedramcore_choose_req_cmd_ready <= 1'd0;
+    case (builder_multiplexer_state)
         1'd1: begin
-            litedramcore_en1 <= 1'd1;
+            if (1'd0) begin
+                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+            end else begin
+                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
+            end
         end
         2'd2: begin
         end
@@ -9971,2011 +10384,2013 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
+            if (1'd0) begin
+                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+            end else begin
+                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
+            end
         end
     endcase
 end
-assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
-assign litedramcore_interface_bank0_addr = rhs_array_muxed12;
-assign litedramcore_interface_bank0_we = rhs_array_muxed13;
-assign litedramcore_interface_bank0_valid = rhs_array_muxed14;
-assign litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock));
-assign litedramcore_interface_bank1_addr = rhs_array_muxed15;
-assign litedramcore_interface_bank1_we = rhs_array_muxed16;
-assign litedramcore_interface_bank1_valid = rhs_array_muxed17;
-assign litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock));
-assign litedramcore_interface_bank2_addr = rhs_array_muxed18;
-assign litedramcore_interface_bank2_we = rhs_array_muxed19;
-assign litedramcore_interface_bank2_valid = rhs_array_muxed20;
-assign litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock));
-assign litedramcore_interface_bank3_addr = rhs_array_muxed21;
-assign litedramcore_interface_bank3_we = rhs_array_muxed22;
-assign litedramcore_interface_bank3_valid = rhs_array_muxed23;
-assign litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock));
-assign litedramcore_interface_bank4_addr = rhs_array_muxed24;
-assign litedramcore_interface_bank4_we = rhs_array_muxed25;
-assign litedramcore_interface_bank4_valid = rhs_array_muxed26;
-assign litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock));
-assign litedramcore_interface_bank5_addr = rhs_array_muxed27;
-assign litedramcore_interface_bank5_we = rhs_array_muxed28;
-assign litedramcore_interface_bank5_valid = rhs_array_muxed29;
-assign litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock));
-assign litedramcore_interface_bank6_addr = rhs_array_muxed30;
-assign litedramcore_interface_bank6_we = rhs_array_muxed31;
-assign litedramcore_interface_bank6_valid = rhs_array_muxed32;
-assign litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)};
-assign litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock));
-assign litedramcore_interface_bank7_addr = rhs_array_muxed33;
-assign litedramcore_interface_bank7_we = rhs_array_muxed34;
-assign litedramcore_interface_bank7_valid = rhs_array_muxed35;
-assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready));
-assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1;
-assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8;
-always @(*) begin
-    litedramcore_interface_wdata <= 128'd0;
-    case ({litedramcore_new_master_wdata_ready1})
+assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock));
+assign main_litedramcore_interface_bank0_addr = builder_rhs_self12;
+assign main_litedramcore_interface_bank0_we = builder_rhs_self13;
+assign main_litedramcore_interface_bank0_valid = builder_rhs_self14;
+assign builder_roundrobin1_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin1_ce = ((~main_litedramcore_interface_bank1_valid) & (~main_litedramcore_interface_bank1_lock));
+assign main_litedramcore_interface_bank1_addr = builder_rhs_self15;
+assign main_litedramcore_interface_bank1_we = builder_rhs_self16;
+assign main_litedramcore_interface_bank1_valid = builder_rhs_self17;
+assign builder_roundrobin2_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin2_ce = ((~main_litedramcore_interface_bank2_valid) & (~main_litedramcore_interface_bank2_lock));
+assign main_litedramcore_interface_bank2_addr = builder_rhs_self18;
+assign main_litedramcore_interface_bank2_we = builder_rhs_self19;
+assign main_litedramcore_interface_bank2_valid = builder_rhs_self20;
+assign builder_roundrobin3_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin3_ce = ((~main_litedramcore_interface_bank3_valid) & (~main_litedramcore_interface_bank3_lock));
+assign main_litedramcore_interface_bank3_addr = builder_rhs_self21;
+assign main_litedramcore_interface_bank3_we = builder_rhs_self22;
+assign main_litedramcore_interface_bank3_valid = builder_rhs_self23;
+assign builder_roundrobin4_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin4_ce = ((~main_litedramcore_interface_bank4_valid) & (~main_litedramcore_interface_bank4_lock));
+assign main_litedramcore_interface_bank4_addr = builder_rhs_self24;
+assign main_litedramcore_interface_bank4_we = builder_rhs_self25;
+assign main_litedramcore_interface_bank4_valid = builder_rhs_self26;
+assign builder_roundrobin5_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin5_ce = ((~main_litedramcore_interface_bank5_valid) & (~main_litedramcore_interface_bank5_lock));
+assign main_litedramcore_interface_bank5_addr = builder_rhs_self27;
+assign main_litedramcore_interface_bank5_we = builder_rhs_self28;
+assign main_litedramcore_interface_bank5_valid = builder_rhs_self29;
+assign builder_roundrobin6_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin6_ce = ((~main_litedramcore_interface_bank6_valid) & (~main_litedramcore_interface_bank6_lock));
+assign main_litedramcore_interface_bank6_addr = builder_rhs_self30;
+assign main_litedramcore_interface_bank6_we = builder_rhs_self31;
+assign main_litedramcore_interface_bank6_valid = builder_rhs_self32;
+assign builder_roundrobin7_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin7_ce = ((~main_litedramcore_interface_bank7_valid) & (~main_litedramcore_interface_bank7_lock));
+assign main_litedramcore_interface_bank7_addr = builder_rhs_self33;
+assign main_litedramcore_interface_bank7_we = builder_rhs_self34;
+assign main_litedramcore_interface_bank7_valid = builder_rhs_self35;
+assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready));
+assign main_user_port_wdata_ready = builder_new_master_wdata_ready1;
+assign main_user_port_rdata_valid = builder_new_master_rdata_valid8;
+always @(*) begin
+    main_litedramcore_interface_wdata <= 128'd0;
+    case ({builder_new_master_wdata_ready1})
         1'd1: begin
-            litedramcore_interface_wdata <= user_port_wdata_payload_data;
+            main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data;
         end
         default: begin
-            litedramcore_interface_wdata <= 1'd0;
+            main_litedramcore_interface_wdata <= 1'd0;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_interface_wdata_we <= 16'd0;
-    case ({litedramcore_new_master_wdata_ready1})
+    main_litedramcore_interface_wdata_we <= 16'd0;
+    case ({builder_new_master_wdata_ready1})
         1'd1: begin
-            litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
+            main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we;
         end
         default: begin
-            litedramcore_interface_wdata_we <= 1'd0;
+            main_litedramcore_interface_wdata_we <= 1'd0;
         end
     endcase
 end
-assign user_port_rdata_payload_data = litedramcore_interface_rdata;
-assign litedramcore_roundrobin0_grant = 1'd0;
-assign litedramcore_roundrobin1_grant = 1'd0;
-assign litedramcore_roundrobin2_grant = 1'd0;
-assign litedramcore_roundrobin3_grant = 1'd0;
-assign litedramcore_roundrobin4_grant = 1'd0;
-assign litedramcore_roundrobin5_grant = 1'd0;
-assign litedramcore_roundrobin6_grant = 1'd0;
-assign litedramcore_roundrobin7_grant = 1'd0;
-always @(*) begin
-    litedramcore_next_state <= 2'd0;
-    litedramcore_next_state <= litedramcore_state;
-    case (litedramcore_state)
+assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata;
+assign builder_roundrobin0_grant = 1'd0;
+assign builder_roundrobin1_grant = 1'd0;
+assign builder_roundrobin2_grant = 1'd0;
+assign builder_roundrobin3_grant = 1'd0;
+assign builder_roundrobin4_grant = 1'd0;
+assign builder_roundrobin5_grant = 1'd0;
+assign builder_roundrobin6_grant = 1'd0;
+assign builder_roundrobin7_grant = 1'd0;
+always @(*) begin
+    builder_next_state <= 2'd0;
+    builder_next_state <= builder_state;
+    case (builder_state)
         1'd1: begin
-            litedramcore_next_state <= 2'd2;
+            builder_next_state <= 2'd2;
         end
         2'd2: begin
-            litedramcore_next_state <= 1'd0;
+            builder_next_state <= 1'd0;
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_next_state <= 1'd1;
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_next_state <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_we_next_value2 <= 1'd0;
-    case (litedramcore_state)
+    builder_interface1_adr_next_value1 <= 14'd0;
+    case (builder_state)
         1'd1: begin
-            litedramcore_we_next_value2 <= 1'd0;
+            builder_interface1_adr_next_value1 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_adr_next_value1 <= builder_interface0_adr[29:0];
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_we_next_value_ce2 <= 1'd0;
-    case (litedramcore_state)
+    builder_interface0_ack <= 1'd0;
+    case (builder_state)
         1'd1: begin
-            litedramcore_we_next_value_ce2 <= 1'd1;
         end
         2'd2: begin
+            builder_interface0_ack <= 1'd1;
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_we_next_value_ce2 <= 1'd1;
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_wishbone_ack <= 1'd0;
-    case (litedramcore_state)
+    builder_interface1_adr_next_value_ce1 <= 1'd0;
+    case (builder_state)
         1'd1: begin
+            builder_interface1_adr_next_value_ce1 <= 1'd1;
         end
         2'd2: begin
-            litedramcore_wishbone_ack <= 1'd1;
         end
         default: begin
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_adr_next_value_ce1 <= 1'd1;
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_wishbone_dat_r <= 32'd0;
-    case (litedramcore_state)
+    builder_interface1_we_next_value2 <= 1'd0;
+    case (builder_state)
         1'd1: begin
+            builder_interface1_we_next_value2 <= 1'd0;
         end
         2'd2: begin
-            litedramcore_wishbone_dat_r <= litedramcore_dat_r;
         end
         default: begin
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_we_next_value2 <= (builder_interface0_we & (builder_interface0_sel != 1'd0));
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_dat_w_next_value0 <= 32'd0;
-    case (litedramcore_state)
+    builder_interface1_we_next_value_ce2 <= 1'd0;
+    case (builder_state)
         1'd1: begin
+            builder_interface1_we_next_value_ce2 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
-            litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_we_next_value_ce2 <= 1'd1;
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_dat_w_next_value_ce0 <= 1'd0;
-    case (litedramcore_state)
+    builder_interface0_dat_r <= 32'd0;
+    case (builder_state)
         1'd1: begin
         end
         2'd2: begin
+            builder_interface0_dat_r <= builder_interface1_dat_r;
         end
         default: begin
-            litedramcore_dat_w_next_value_ce0 <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_adr_next_value1 <= 14'd0;
-    case (litedramcore_state)
+    builder_interface1_dat_w_next_value0 <= 32'd0;
+    case (builder_state)
         1'd1: begin
-            litedramcore_adr_next_value1 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
-            end
+            builder_interface1_dat_w_next_value0 <= builder_interface0_dat_w;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_adr_next_value_ce1 <= 1'd0;
-    case (litedramcore_state)
+    builder_interface1_dat_w_next_value_ce0 <= 1'd0;
+    case (builder_state)
         1'd1: begin
-            litedramcore_adr_next_value_ce1 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
-            if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-                litedramcore_adr_next_value_ce1 <= 1'd1;
-            end
+            builder_interface1_dat_w_next_value_ce0 <= 1'd1;
         end
     endcase
 end
-assign litedramcore_wishbone_adr = wb_bus_adr;
-assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
-assign wb_bus_dat_r = litedramcore_wishbone_dat_r;
-assign litedramcore_wishbone_sel = wb_bus_sel;
-assign litedramcore_wishbone_cyc = wb_bus_cyc;
-assign litedramcore_wishbone_stb = wb_bus_stb;
-assign wb_bus_ack = litedramcore_wishbone_ack;
-assign litedramcore_wishbone_we = wb_bus_we;
-assign litedramcore_wishbone_cti = wb_bus_cti;
-assign litedramcore_wishbone_bte = wb_bus_bte;
-assign wb_bus_err = litedramcore_wishbone_err;
-assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
-assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
+assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0);
+assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank0_init_done0_we <= 1'd0;
-    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank0_init_done0_we <= (~interface0_bank_bus_we);
+    builder_csrbank0_init_done0_we <= 1'd0;
+    if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank0_init_done0_re <= 1'd0;
-    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank0_init_done0_re <= interface0_bank_bus_we;
+    builder_csrbank0_init_done0_re <= 1'd0;
+    if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
     end
 end
-assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
+assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank0_init_error0_re <= 1'd0;
-    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank0_init_error0_re <= interface0_bank_bus_we;
+    builder_csrbank0_init_error0_we <= 1'd0;
+    if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank0_init_error0_we <= 1'd0;
-    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank0_init_error0_we <= (~interface0_bank_bus_we);
+    builder_csrbank0_init_error0_re <= 1'd0;
+    if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
     end
 end
-assign csrbank0_init_done0_w = init_done_storage;
-assign csrbank0_init_error0_w = init_error_storage;
-assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
-assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0];
+assign builder_csrbank0_init_done0_w = main_init_done_storage;
+assign builder_csrbank0_init_error0_w = main_init_error_storage;
+assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
+assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank1_rst0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank1_rst0_re <= interface1_bank_bus_we;
+    builder_csrbank1_rst0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank1_rst0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank1_rst0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_rst0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
     end
 end
-assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
+assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    csrbank1_dly_sel0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_dly_sel0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_dly_sel0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank1_dly_sel0_re <= interface1_bank_bus_we;
+    builder_csrbank1_dly_sel0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
+assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0];
 always @(*) begin
-    csrbank1_half_sys8x_taps0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
+        builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank1_half_sys8x_taps0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we;
+    builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
+        builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
     end
 end
-assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0];
+assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank1_wlevel_en0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank1_wlevel_en0_re <= interface1_bank_bus_we;
+    builder_csrbank1_wlevel_en0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
+        builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_wlevel_en0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_wlevel_en0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
+        builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_wlevel_strobe_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
-        a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we;
+    main_a7ddrphy_wlevel_strobe_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
+        main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    a7ddrphy_wlevel_strobe_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
-        a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_wlevel_strobe_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
+        main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_rdly_dq_rst_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
+    main_a7ddrphy_rdly_dq_rst_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
+        main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    a7ddrphy_rdly_dq_rst_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_rdly_dq_rst_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
+        main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_rdly_dq_inc_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
+    main_a7ddrphy_rdly_dq_inc_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
+        main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    a7ddrphy_rdly_dq_inc_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_rdly_dq_inc_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
+        main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
-        a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
+        main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
-        a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
+    main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
+        main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
     end
 end
-assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
-        a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
+        main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
-        a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we;
+    main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
+        main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
     end
 end
-assign a7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
-        a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
+        main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
-        a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
+    main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
+        main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
     end
 end
-assign a7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
+assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
-        a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we);
+    main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
+        main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
-        a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we;
+    main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
+        main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
     end
 end
-assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0];
+assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    csrbank1_rdphase0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
-        csrbank1_rdphase0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_rdphase0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
+        builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_rdphase0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
-        csrbank1_rdphase0_re <= interface1_bank_bus_we;
+    builder_csrbank1_rdphase0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
+        builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
     end
 end
-assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0];
+assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    csrbank1_wrphase0_re <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
-        csrbank1_wrphase0_re <= interface1_bank_bus_we;
+    builder_csrbank1_wrphase0_we <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
+        builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank1_wrphase0_we <= 1'd0;
-    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
-        csrbank1_wrphase0_we <= (~interface1_bank_bus_we);
+    builder_csrbank1_wrphase0_re <= 1'd0;
+    if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
+        builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
     end
 end
-assign csrbank1_rst0_w = a7ddrphy_rst_storage;
-assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0];
-assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0];
-assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage;
-assign csrbank1_rdphase0_w = a7ddrphy_rdphase_storage[1:0];
-assign csrbank1_wrphase0_w = a7ddrphy_wrphase_storage[1:0];
-assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2);
-assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
+assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage;
+assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0];
+assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0];
+assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage;
+assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0];
+assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0];
+assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
+assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
 always @(*) begin
-    csrbank2_dfii_control0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_control0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_control0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank2_dfii_control0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_control0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
+        builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
+assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi0_command0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_command0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_command0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
+        builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
+assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    litedramcore_phaseinjector0_command_issue_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
-        litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
+    main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
+        main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    litedramcore_phaseinjector0_command_issue_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
-        litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
+    main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
+        main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[13:0];
+assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[13:0];
 always @(*) begin
-    csrbank2_dfii_pi0_address0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_address0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
+        builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_address0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
+        builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank2_dfii_pi0_baddress0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
-        csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
+        builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_baddress0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
-        csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
+        builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
-        csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
+        builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
-        csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
+        builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi0_rddata_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
-        csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi0_rddata_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
+        builder_csrbank2_dfii_pi0_rddata_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_rddata_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
-        csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi0_rddata_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
+        builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
+assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi1_command0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
-        csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
+        builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_command0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
-        csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_command0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
+        builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
+assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    litedramcore_phaseinjector1_command_issue_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
-        litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
+    main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
+        main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    litedramcore_phaseinjector1_command_issue_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
-        litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we;
+    main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
+        main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[13:0];
+assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[13:0];
 always @(*) begin
-    csrbank2_dfii_pi1_address0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
-        csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
+        builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_address0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
-        csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_address0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
+        builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank2_dfii_pi1_baddress0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
-        csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
+        builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_baddress0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
-        csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
+        builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
-        csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
+        builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
-        csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
+        builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi1_rddata_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
-        csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi1_rddata_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
+        builder_csrbank2_dfii_pi1_rddata_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_rddata_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
-        csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi1_rddata_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
+        builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0];
+assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi2_command0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
-        csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_command0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
+        builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_command0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
-        csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_command0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
+        builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0];
+assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    litedramcore_phaseinjector2_command_issue_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
-        litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we);
+    main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
+        main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    litedramcore_phaseinjector2_command_issue_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
-        litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we;
+    main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
+        main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[13:0];
+assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[13:0];
 always @(*) begin
-    csrbank2_dfii_pi2_address0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
-        csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
+        builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_address0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
-        csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_address0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
+        builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank2_dfii_pi2_baddress0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
-        csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
+        builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_baddress0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
-        csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
+        builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
-        csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+        builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
-        csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+        builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi2_rddata_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
-        csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi2_rddata_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+        builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi2_rddata_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
-        csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi2_rddata_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+        builder_csrbank2_dfii_pi2_rddata_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0];
+assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi3_command0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
-        csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_command0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
+        builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_command0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
-        csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
+        builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0];
+assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    litedramcore_phaseinjector3_command_issue_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
-        litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we;
+    main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
+        main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    litedramcore_phaseinjector3_command_issue_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
-        litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we);
+    main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
+        main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[13:0];
+assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[13:0];
 always @(*) begin
-    csrbank2_dfii_pi3_address0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
-        csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_address0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
+        builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_address0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
-        csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
+        builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank2_dfii_pi3_baddress0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
-        csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+        builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_baddress0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
-        csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+        builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
-        csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
+        builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
-        csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
+        builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
     end
 end
-assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-    csrbank2_dfii_pi3_rddata_we <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
-        csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we);
+    builder_csrbank2_dfii_pi3_rddata_we <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
+        builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we);
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi3_rddata_re <= 1'd0;
-    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
-        csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we;
+    builder_csrbank2_dfii_pi3_rddata_re <= 1'd0;
+    if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
+        builder_csrbank2_dfii_pi3_rddata_re <= builder_interface2_bank_bus_we;
     end
 end
-assign litedramcore_sel = litedramcore_storage[0];
-assign litedramcore_cke = litedramcore_storage[1];
-assign litedramcore_odt = litedramcore_storage[2];
-assign litedramcore_reset_n = litedramcore_storage[3];
-assign csrbank2_dfii_control0_w = litedramcore_storage[3:0];
-assign litedramcore_phaseinjector0_csrfield_cs = litedramcore_phaseinjector0_command_storage[0];
-assign litedramcore_phaseinjector0_csrfield_we = litedramcore_phaseinjector0_command_storage[1];
-assign litedramcore_phaseinjector0_csrfield_cas = litedramcore_phaseinjector0_command_storage[2];
-assign litedramcore_phaseinjector0_csrfield_ras = litedramcore_phaseinjector0_command_storage[3];
-assign litedramcore_phaseinjector0_csrfield_wren = litedramcore_phaseinjector0_command_storage[4];
-assign litedramcore_phaseinjector0_csrfield_rden = litedramcore_phaseinjector0_command_storage[5];
-assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
-assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0];
-assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
-assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
-assign csrbank2_dfii_pi0_rddata_w = litedramcore_phaseinjector0_rddata_status[31:0];
-assign litedramcore_phaseinjector0_rddata_we = csrbank2_dfii_pi0_rddata_we;
-assign litedramcore_phaseinjector1_csrfield_cs = litedramcore_phaseinjector1_command_storage[0];
-assign litedramcore_phaseinjector1_csrfield_we = litedramcore_phaseinjector1_command_storage[1];
-assign litedramcore_phaseinjector1_csrfield_cas = litedramcore_phaseinjector1_command_storage[2];
-assign litedramcore_phaseinjector1_csrfield_ras = litedramcore_phaseinjector1_command_storage[3];
-assign litedramcore_phaseinjector1_csrfield_wren = litedramcore_phaseinjector1_command_storage[4];
-assign litedramcore_phaseinjector1_csrfield_rden = litedramcore_phaseinjector1_command_storage[5];
-assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
-assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[13:0];
-assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
-assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
-assign csrbank2_dfii_pi1_rddata_w = litedramcore_phaseinjector1_rddata_status[31:0];
-assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata_we;
-assign litedramcore_phaseinjector2_csrfield_cs = litedramcore_phaseinjector2_command_storage[0];
-assign litedramcore_phaseinjector2_csrfield_we = litedramcore_phaseinjector2_command_storage[1];
-assign litedramcore_phaseinjector2_csrfield_cas = litedramcore_phaseinjector2_command_storage[2];
-assign litedramcore_phaseinjector2_csrfield_ras = litedramcore_phaseinjector2_command_storage[3];
-assign litedramcore_phaseinjector2_csrfield_wren = litedramcore_phaseinjector2_command_storage[4];
-assign litedramcore_phaseinjector2_csrfield_rden = litedramcore_phaseinjector2_command_storage[5];
-assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
-assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[13:0];
-assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
-assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0];
-assign csrbank2_dfii_pi2_rddata_w = litedramcore_phaseinjector2_rddata_status[31:0];
-assign litedramcore_phaseinjector2_rddata_we = csrbank2_dfii_pi2_rddata_we;
-assign litedramcore_phaseinjector3_csrfield_cs = litedramcore_phaseinjector3_command_storage[0];
-assign litedramcore_phaseinjector3_csrfield_we = litedramcore_phaseinjector3_command_storage[1];
-assign litedramcore_phaseinjector3_csrfield_cas = litedramcore_phaseinjector3_command_storage[2];
-assign litedramcore_phaseinjector3_csrfield_ras = litedramcore_phaseinjector3_command_storage[3];
-assign litedramcore_phaseinjector3_csrfield_wren = litedramcore_phaseinjector3_command_storage[4];
-assign litedramcore_phaseinjector3_csrfield_rden = litedramcore_phaseinjector3_command_storage[5];
-assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
-assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[13:0];
-assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
-assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0];
-assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_rddata_status[31:0];
-assign litedramcore_phaseinjector3_rddata_we = csrbank2_dfii_pi3_rddata_we;
-assign csr_interconnect_adr = litedramcore_adr;
-assign csr_interconnect_we = litedramcore_we;
-assign csr_interconnect_dat_w = litedramcore_dat_w;
-assign litedramcore_dat_r = csr_interconnect_dat_r;
-assign interface0_bank_bus_adr = csr_interconnect_adr;
-assign interface1_bank_bus_adr = csr_interconnect_adr;
-assign interface2_bank_bus_adr = csr_interconnect_adr;
-assign interface0_bank_bus_we = csr_interconnect_we;
-assign interface1_bank_bus_we = csr_interconnect_we;
-assign interface2_bank_bus_we = csr_interconnect_we;
-assign interface0_bank_bus_dat_w = csr_interconnect_dat_w;
-assign interface1_bank_bus_dat_w = csr_interconnect_dat_w;
-assign interface2_bank_bus_dat_w = csr_interconnect_dat_w;
-assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
-always @(*) begin
-    rhs_array_muxed0 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+assign main_litedramcore_sel = main_litedramcore_storage[0];
+assign main_litedramcore_cke = main_litedramcore_storage[1];
+assign main_litedramcore_odt = main_litedramcore_storage[2];
+assign main_litedramcore_reset_n = main_litedramcore_storage[3];
+assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0];
+assign main_litedramcore_phaseinjector0_csrfield_cs = main_litedramcore_phaseinjector0_command_storage[0];
+assign main_litedramcore_phaseinjector0_csrfield_we = main_litedramcore_phaseinjector0_command_storage[1];
+assign main_litedramcore_phaseinjector0_csrfield_cas = main_litedramcore_phaseinjector0_command_storage[2];
+assign main_litedramcore_phaseinjector0_csrfield_ras = main_litedramcore_phaseinjector0_command_storage[3];
+assign main_litedramcore_phaseinjector0_csrfield_wren = main_litedramcore_phaseinjector0_command_storage[4];
+assign main_litedramcore_phaseinjector0_csrfield_rden = main_litedramcore_phaseinjector0_command_storage[5];
+assign main_litedramcore_phaseinjector0_csrfield_cs_top = main_litedramcore_phaseinjector0_command_storage[6];
+assign main_litedramcore_phaseinjector0_csrfield_cs_bottom = main_litedramcore_phaseinjector0_command_storage[7];
+assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[7:0];
+assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[13:0];
+assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0];
+assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we;
+assign main_litedramcore_phaseinjector1_csrfield_cs = main_litedramcore_phaseinjector1_command_storage[0];
+assign main_litedramcore_phaseinjector1_csrfield_we = main_litedramcore_phaseinjector1_command_storage[1];
+assign main_litedramcore_phaseinjector1_csrfield_cas = main_litedramcore_phaseinjector1_command_storage[2];
+assign main_litedramcore_phaseinjector1_csrfield_ras = main_litedramcore_phaseinjector1_command_storage[3];
+assign main_litedramcore_phaseinjector1_csrfield_wren = main_litedramcore_phaseinjector1_command_storage[4];
+assign main_litedramcore_phaseinjector1_csrfield_rden = main_litedramcore_phaseinjector1_command_storage[5];
+assign main_litedramcore_phaseinjector1_csrfield_cs_top = main_litedramcore_phaseinjector1_command_storage[6];
+assign main_litedramcore_phaseinjector1_csrfield_cs_bottom = main_litedramcore_phaseinjector1_command_storage[7];
+assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[7:0];
+assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[13:0];
+assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0];
+assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we;
+assign main_litedramcore_phaseinjector2_csrfield_cs = main_litedramcore_phaseinjector2_command_storage[0];
+assign main_litedramcore_phaseinjector2_csrfield_we = main_litedramcore_phaseinjector2_command_storage[1];
+assign main_litedramcore_phaseinjector2_csrfield_cas = main_litedramcore_phaseinjector2_command_storage[2];
+assign main_litedramcore_phaseinjector2_csrfield_ras = main_litedramcore_phaseinjector2_command_storage[3];
+assign main_litedramcore_phaseinjector2_csrfield_wren = main_litedramcore_phaseinjector2_command_storage[4];
+assign main_litedramcore_phaseinjector2_csrfield_rden = main_litedramcore_phaseinjector2_command_storage[5];
+assign main_litedramcore_phaseinjector2_csrfield_cs_top = main_litedramcore_phaseinjector2_command_storage[6];
+assign main_litedramcore_phaseinjector2_csrfield_cs_bottom = main_litedramcore_phaseinjector2_command_storage[7];
+assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[7:0];
+assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[13:0];
+assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0];
+assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we;
+assign main_litedramcore_phaseinjector3_csrfield_cs = main_litedramcore_phaseinjector3_command_storage[0];
+assign main_litedramcore_phaseinjector3_csrfield_we = main_litedramcore_phaseinjector3_command_storage[1];
+assign main_litedramcore_phaseinjector3_csrfield_cas = main_litedramcore_phaseinjector3_command_storage[2];
+assign main_litedramcore_phaseinjector3_csrfield_ras = main_litedramcore_phaseinjector3_command_storage[3];
+assign main_litedramcore_phaseinjector3_csrfield_wren = main_litedramcore_phaseinjector3_command_storage[4];
+assign main_litedramcore_phaseinjector3_csrfield_rden = main_litedramcore_phaseinjector3_command_storage[5];
+assign main_litedramcore_phaseinjector3_csrfield_cs_top = main_litedramcore_phaseinjector3_command_storage[6];
+assign main_litedramcore_phaseinjector3_csrfield_cs_bottom = main_litedramcore_phaseinjector3_command_storage[7];
+assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[7:0];
+assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[13:0];
+assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0];
+assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0];
+assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we;
+assign builder_adr = builder_interface1_adr;
+assign builder_we = builder_interface1_we;
+assign builder_dat_w = builder_interface1_dat_w;
+assign builder_interface1_dat_r = builder_dat_r;
+assign builder_interface0_bank_bus_adr = builder_adr;
+assign builder_interface1_bank_bus_adr = builder_adr;
+assign builder_interface2_bank_bus_adr = builder_adr;
+assign builder_interface0_bank_bus_we = builder_we;
+assign builder_interface1_bank_bus_we = builder_we;
+assign builder_interface2_bank_bus_we = builder_we;
+assign builder_interface0_bank_bus_dat_w = builder_dat_w;
+assign builder_interface1_bank_bus_dat_w = builder_dat_w;
+assign builder_interface2_bank_bus_dat_w = builder_dat_w;
+assign builder_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r);
+always @(*) begin
+    builder_rhs_self0 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[0];
         end
         1'd1: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[1];
         end
         2'd2: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[2];
         end
         2'd3: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[3];
         end
         3'd4: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[4];
         end
         3'd5: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[5];
         end
         3'd6: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[6];
         end
         default: begin
-            rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
+            builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[7];
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed1 <= 14'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_rhs_self1 <= 14'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine0_cmd_payload_a;
         end
         1'd1: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine1_cmd_payload_a;
         end
         2'd2: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine2_cmd_payload_a;
         end
         2'd3: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine3_cmd_payload_a;
         end
         3'd4: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine4_cmd_payload_a;
         end
         3'd5: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine5_cmd_payload_a;
         end
         3'd6: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine6_cmd_payload_a;
         end
         default: begin
-            rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
+            builder_rhs_self1 <= main_litedramcore_bankmachine7_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed2 <= 3'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_rhs_self2 <= 3'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine0_cmd_payload_ba;
         end
         1'd1: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine1_cmd_payload_ba;
         end
         2'd2: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine2_cmd_payload_ba;
         end
         2'd3: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine3_cmd_payload_ba;
         end
         3'd4: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine4_cmd_payload_ba;
         end
         3'd5: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine5_cmd_payload_ba;
         end
         3'd6: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine6_cmd_payload_ba;
         end
         default: begin
-            rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
+            builder_rhs_self2 <= main_litedramcore_bankmachine7_cmd_payload_ba;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed3 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_rhs_self3 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine0_cmd_payload_is_read;
         end
         1'd1: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine1_cmd_payload_is_read;
         end
         2'd2: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine2_cmd_payload_is_read;
         end
         2'd3: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine3_cmd_payload_is_read;
         end
         3'd4: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine4_cmd_payload_is_read;
         end
         3'd5: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine5_cmd_payload_is_read;
         end
         3'd6: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine6_cmd_payload_is_read;
         end
         default: begin
-            rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
+            builder_rhs_self3 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed4 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_rhs_self4 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine0_cmd_payload_is_write;
         end
         1'd1: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine1_cmd_payload_is_write;
         end
         2'd2: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine2_cmd_payload_is_write;
         end
         2'd3: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine3_cmd_payload_is_write;
         end
         3'd4: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine4_cmd_payload_is_write;
         end
         3'd5: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine5_cmd_payload_is_write;
         end
         3'd6: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine6_cmd_payload_is_write;
         end
         default: begin
-            rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
+            builder_rhs_self4 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed5 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_rhs_self5 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd;
         end
         1'd1: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd;
         end
         2'd2: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd;
         end
         2'd3: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd;
         end
         3'd4: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd;
         end
         3'd5: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd;
         end
         3'd6: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd;
         end
         default: begin
-            rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+            builder_rhs_self5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed0 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_t_self0 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine0_cmd_payload_cas;
         end
         1'd1: begin
-            t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine1_cmd_payload_cas;
         end
         2'd2: begin
-            t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine2_cmd_payload_cas;
         end
         2'd3: begin
-            t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine3_cmd_payload_cas;
         end
         3'd4: begin
-            t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine4_cmd_payload_cas;
         end
         3'd5: begin
-            t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine5_cmd_payload_cas;
         end
         3'd6: begin
-            t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine6_cmd_payload_cas;
         end
         default: begin
-            t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
+            builder_t_self0 <= main_litedramcore_bankmachine7_cmd_payload_cas;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed1 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_t_self1 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine0_cmd_payload_ras;
         end
         1'd1: begin
-            t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine1_cmd_payload_ras;
         end
         2'd2: begin
-            t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine2_cmd_payload_ras;
         end
         2'd3: begin
-            t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine3_cmd_payload_ras;
         end
         3'd4: begin
-            t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine4_cmd_payload_ras;
         end
         3'd5: begin
-            t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine5_cmd_payload_ras;
         end
         3'd6: begin
-            t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine6_cmd_payload_ras;
         end
         default: begin
-            t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
+            builder_t_self1 <= main_litedramcore_bankmachine7_cmd_payload_ras;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed2 <= 1'd0;
-    case (litedramcore_choose_cmd_grant)
+    builder_t_self2 <= 1'd0;
+    case (main_litedramcore_choose_cmd_grant)
         1'd0: begin
-            t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine0_cmd_payload_we;
         end
         1'd1: begin
-            t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine1_cmd_payload_we;
         end
         2'd2: begin
-            t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine2_cmd_payload_we;
         end
         2'd3: begin
-            t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine3_cmd_payload_we;
         end
         3'd4: begin
-            t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine4_cmd_payload_we;
         end
         3'd5: begin
-            t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine5_cmd_payload_we;
         end
         3'd6: begin
-            t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine6_cmd_payload_we;
         end
         default: begin
-            t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
+            builder_t_self2 <= main_litedramcore_bankmachine7_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed6 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self6 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[0];
         end
         1'd1: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[1];
         end
         2'd2: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[2];
         end
         2'd3: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[3];
         end
         3'd4: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[4];
         end
         3'd5: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[5];
         end
         3'd6: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[6];
         end
         default: begin
-            rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
+            builder_rhs_self6 <= main_litedramcore_choose_req_valids[7];
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed7 <= 14'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self7 <= 14'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine0_cmd_payload_a;
         end
         1'd1: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine1_cmd_payload_a;
         end
         2'd2: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine2_cmd_payload_a;
         end
         2'd3: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine3_cmd_payload_a;
         end
         3'd4: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine4_cmd_payload_a;
         end
         3'd5: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine5_cmd_payload_a;
         end
         3'd6: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine6_cmd_payload_a;
         end
         default: begin
-            rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
+            builder_rhs_self7 <= main_litedramcore_bankmachine7_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed8 <= 3'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self8 <= 3'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine0_cmd_payload_ba;
         end
         1'd1: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine1_cmd_payload_ba;
         end
         2'd2: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine2_cmd_payload_ba;
         end
         2'd3: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine3_cmd_payload_ba;
         end
         3'd4: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine4_cmd_payload_ba;
         end
         3'd5: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine5_cmd_payload_ba;
         end
         3'd6: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine6_cmd_payload_ba;
         end
         default: begin
-            rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
+            builder_rhs_self8 <= main_litedramcore_bankmachine7_cmd_payload_ba;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed9 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self9 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine0_cmd_payload_is_read;
         end
         1'd1: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine1_cmd_payload_is_read;
         end
         2'd2: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine2_cmd_payload_is_read;
         end
         2'd3: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine3_cmd_payload_is_read;
         end
         3'd4: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine4_cmd_payload_is_read;
         end
         3'd5: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine5_cmd_payload_is_read;
         end
         3'd6: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine6_cmd_payload_is_read;
         end
         default: begin
-            rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
+            builder_rhs_self9 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed10 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self10 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine0_cmd_payload_is_write;
         end
         1'd1: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine1_cmd_payload_is_write;
         end
         2'd2: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine2_cmd_payload_is_write;
         end
         2'd3: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine3_cmd_payload_is_write;
         end
         3'd4: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine4_cmd_payload_is_write;
         end
         3'd5: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine5_cmd_payload_is_write;
         end
         3'd6: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine6_cmd_payload_is_write;
         end
         default: begin
-            rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
+            builder_rhs_self10 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed11 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_rhs_self11 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd;
         end
         1'd1: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd;
         end
         2'd2: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd;
         end
         2'd3: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd;
         end
         3'd4: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd;
         end
         3'd5: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd;
         end
         3'd6: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd;
         end
         default: begin
-            rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+            builder_rhs_self11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed3 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_t_self3 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine0_cmd_payload_cas;
         end
         1'd1: begin
-            t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine1_cmd_payload_cas;
         end
         2'd2: begin
-            t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine2_cmd_payload_cas;
         end
         2'd3: begin
-            t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine3_cmd_payload_cas;
         end
         3'd4: begin
-            t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine4_cmd_payload_cas;
         end
         3'd5: begin
-            t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine5_cmd_payload_cas;
         end
         3'd6: begin
-            t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine6_cmd_payload_cas;
         end
         default: begin
-            t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
+            builder_t_self3 <= main_litedramcore_bankmachine7_cmd_payload_cas;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed4 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_t_self4 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine0_cmd_payload_ras;
         end
         1'd1: begin
-            t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine1_cmd_payload_ras;
         end
         2'd2: begin
-            t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine2_cmd_payload_ras;
         end
         2'd3: begin
-            t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine3_cmd_payload_ras;
         end
         3'd4: begin
-            t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine4_cmd_payload_ras;
         end
         3'd5: begin
-            t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine5_cmd_payload_ras;
         end
         3'd6: begin
-            t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine6_cmd_payload_ras;
         end
         default: begin
-            t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
+            builder_t_self4 <= main_litedramcore_bankmachine7_cmd_payload_ras;
         end
     endcase
 end
 always @(*) begin
-    t_array_muxed5 <= 1'd0;
-    case (litedramcore_choose_req_grant)
+    builder_t_self5 <= 1'd0;
+    case (main_litedramcore_choose_req_grant)
         1'd0: begin
-            t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine0_cmd_payload_we;
         end
         1'd1: begin
-            t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine1_cmd_payload_we;
         end
         2'd2: begin
-            t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine2_cmd_payload_we;
         end
         2'd3: begin
-            t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine3_cmd_payload_we;
         end
         3'd4: begin
-            t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine4_cmd_payload_we;
         end
         3'd5: begin
-            t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine5_cmd_payload_we;
         end
         3'd6: begin
-            t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine6_cmd_payload_we;
         end
         default: begin
-            t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
+            builder_t_self5 <= main_litedramcore_bankmachine7_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed12 <= 21'd0;
-    case (litedramcore_roundrobin0_grant)
+    builder_rhs_self12 <= 21'd0;
+    case (builder_roundrobin0_grant)
         default: begin
-            rhs_array_muxed12 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self12 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed13 <= 1'd0;
-    case (litedramcore_roundrobin0_grant)
+    builder_rhs_self13 <= 1'd0;
+    case (builder_roundrobin0_grant)
         default: begin
-            rhs_array_muxed13 <= user_port_cmd_payload_we;
+            builder_rhs_self13 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed14 <= 1'd0;
-    case (litedramcore_roundrobin0_grant)
+    builder_rhs_self14 <= 1'd0;
+    case (builder_roundrobin0_grant)
         default: begin
-            rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed15 <= 21'd0;
-    case (litedramcore_roundrobin1_grant)
+    builder_rhs_self15 <= 21'd0;
+    case (builder_roundrobin1_grant)
         default: begin
-            rhs_array_muxed15 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self15 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed16 <= 1'd0;
-    case (litedramcore_roundrobin1_grant)
+    builder_rhs_self16 <= 1'd0;
+    case (builder_roundrobin1_grant)
         default: begin
-            rhs_array_muxed16 <= user_port_cmd_payload_we;
+            builder_rhs_self16 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed17 <= 1'd0;
-    case (litedramcore_roundrobin1_grant)
+    builder_rhs_self17 <= 1'd0;
+    case (builder_roundrobin1_grant)
         default: begin
-            rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed18 <= 21'd0;
-    case (litedramcore_roundrobin2_grant)
+    builder_rhs_self18 <= 21'd0;
+    case (builder_roundrobin2_grant)
         default: begin
-            rhs_array_muxed18 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self18 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed19 <= 1'd0;
-    case (litedramcore_roundrobin2_grant)
+    builder_rhs_self19 <= 1'd0;
+    case (builder_roundrobin2_grant)
         default: begin
-            rhs_array_muxed19 <= user_port_cmd_payload_we;
+            builder_rhs_self19 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed20 <= 1'd0;
-    case (litedramcore_roundrobin2_grant)
+    builder_rhs_self20 <= 1'd0;
+    case (builder_roundrobin2_grant)
         default: begin
-            rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed21 <= 21'd0;
-    case (litedramcore_roundrobin3_grant)
+    builder_rhs_self21 <= 21'd0;
+    case (builder_roundrobin3_grant)
         default: begin
-            rhs_array_muxed21 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self21 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed22 <= 1'd0;
-    case (litedramcore_roundrobin3_grant)
+    builder_rhs_self22 <= 1'd0;
+    case (builder_roundrobin3_grant)
         default: begin
-            rhs_array_muxed22 <= user_port_cmd_payload_we;
+            builder_rhs_self22 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed23 <= 1'd0;
-    case (litedramcore_roundrobin3_grant)
+    builder_rhs_self23 <= 1'd0;
+    case (builder_roundrobin3_grant)
         default: begin
-            rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed24 <= 21'd0;
-    case (litedramcore_roundrobin4_grant)
+    builder_rhs_self24 <= 21'd0;
+    case (builder_roundrobin4_grant)
         default: begin
-            rhs_array_muxed24 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self24 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed25 <= 1'd0;
-    case (litedramcore_roundrobin4_grant)
+    builder_rhs_self25 <= 1'd0;
+    case (builder_roundrobin4_grant)
         default: begin
-            rhs_array_muxed25 <= user_port_cmd_payload_we;
+            builder_rhs_self25 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed26 <= 1'd0;
-    case (litedramcore_roundrobin4_grant)
+    builder_rhs_self26 <= 1'd0;
+    case (builder_roundrobin4_grant)
         default: begin
-            rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed27 <= 21'd0;
-    case (litedramcore_roundrobin5_grant)
+    builder_rhs_self27 <= 21'd0;
+    case (builder_roundrobin5_grant)
         default: begin
-            rhs_array_muxed27 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self27 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed28 <= 1'd0;
-    case (litedramcore_roundrobin5_grant)
+    builder_rhs_self28 <= 1'd0;
+    case (builder_roundrobin5_grant)
         default: begin
-            rhs_array_muxed28 <= user_port_cmd_payload_we;
+            builder_rhs_self28 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed29 <= 1'd0;
-    case (litedramcore_roundrobin5_grant)
+    builder_rhs_self29 <= 1'd0;
+    case (builder_roundrobin5_grant)
         default: begin
-            rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed30 <= 21'd0;
-    case (litedramcore_roundrobin6_grant)
+    builder_rhs_self30 <= 21'd0;
+    case (builder_roundrobin6_grant)
         default: begin
-            rhs_array_muxed30 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self30 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed31 <= 1'd0;
-    case (litedramcore_roundrobin6_grant)
+    builder_rhs_self31 <= 1'd0;
+    case (builder_roundrobin6_grant)
         default: begin
-            rhs_array_muxed31 <= user_port_cmd_payload_we;
+            builder_rhs_self31 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed32 <= 1'd0;
-    case (litedramcore_roundrobin6_grant)
+    builder_rhs_self32 <= 1'd0;
+    case (builder_roundrobin6_grant)
         default: begin
-            rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed33 <= 21'd0;
-    case (litedramcore_roundrobin7_grant)
+    builder_rhs_self33 <= 21'd0;
+    case (builder_roundrobin7_grant)
         default: begin
-            rhs_array_muxed33 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+            builder_rhs_self33 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed34 <= 1'd0;
-    case (litedramcore_roundrobin7_grant)
+    builder_rhs_self34 <= 1'd0;
+    case (builder_roundrobin7_grant)
         default: begin
-            rhs_array_muxed34 <= user_port_cmd_payload_we;
+            builder_rhs_self34 <= main_user_port_cmd_payload_we;
         end
     endcase
 end
 always @(*) begin
-    rhs_array_muxed35 <= 1'd0;
-    case (litedramcore_roundrobin7_grant)
+    builder_rhs_self35 <= 1'd0;
+    case (builder_roundrobin7_grant)
         default: begin
-            rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
+            builder_rhs_self35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid);
         end
     endcase
 end
 always @(*) begin
-    array_muxed0 <= 3'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self0 <= 3'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed0 <= litedramcore_nop_ba[2:0];
+            builder_self0 <= main_litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed1 <= 14'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self1 <= 14'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed1 <= litedramcore_nop_a;
+            builder_self1 <= main_litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
+            builder_self1 <= main_litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
+            builder_self1 <= main_litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed1 <= litedramcore_cmd_payload_a;
+            builder_self1 <= main_litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed2 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self2 <= 1'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed2 <= 1'd0;
+            builder_self2 <= 1'd0;
         end
         1'd1: begin
-            array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+            builder_self2 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+            builder_self2 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+            builder_self2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed3 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self3 <= 1'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed3 <= 1'd0;
+            builder_self3 <= 1'd0;
         end
         1'd1: begin
-            array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+            builder_self3 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+            builder_self3 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+            builder_self3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed4 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self4 <= 1'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed4 <= 1'd0;
+            builder_self4 <= 1'd0;
         end
         1'd1: begin
-            array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+            builder_self4 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+            builder_self4 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+            builder_self4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed5 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self5 <= 1'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed5 <= 1'd0;
+            builder_self5 <= 1'd0;
         end
         1'd1: begin
-            array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+            builder_self5 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+            builder_self5 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+            builder_self5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed6 <= 1'd0;
-    case (litedramcore_steerer_sel0)
+    builder_self6 <= 1'd0;
+    case (main_litedramcore_steerer0)
         1'd0: begin
-            array_muxed6 <= 1'd0;
+            builder_self6 <= 1'd0;
         end
         1'd1: begin
-            array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+            builder_self6 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+            builder_self6 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+            builder_self6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
         end
     endcase
 end
 always @(*) begin
-    array_muxed7 <= 3'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self7 <= 3'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed7 <= litedramcore_nop_ba[2:0];
+            builder_self7 <= main_litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed8 <= 14'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self8 <= 14'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed8 <= litedramcore_nop_a;
+            builder_self8 <= main_litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
+            builder_self8 <= main_litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
+            builder_self8 <= main_litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed8 <= litedramcore_cmd_payload_a;
+            builder_self8 <= main_litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed9 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self9 <= 1'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed9 <= 1'd0;
+            builder_self9 <= 1'd0;
         end
         1'd1: begin
-            array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+            builder_self9 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+            builder_self9 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+            builder_self9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed10 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self10 <= 1'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed10 <= 1'd0;
+            builder_self10 <= 1'd0;
         end
         1'd1: begin
-            array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+            builder_self10 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+            builder_self10 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+            builder_self10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed11 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self11 <= 1'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed11 <= 1'd0;
+            builder_self11 <= 1'd0;
         end
         1'd1: begin
-            array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+            builder_self11 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+            builder_self11 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+            builder_self11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed12 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self12 <= 1'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed12 <= 1'd0;
+            builder_self12 <= 1'd0;
         end
         1'd1: begin
-            array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+            builder_self12 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+            builder_self12 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+            builder_self12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed13 <= 1'd0;
-    case (litedramcore_steerer_sel1)
+    builder_self13 <= 1'd0;
+    case (main_litedramcore_steerer1)
         1'd0: begin
-            array_muxed13 <= 1'd0;
+            builder_self13 <= 1'd0;
         end
         1'd1: begin
-            array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+            builder_self13 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+            builder_self13 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+            builder_self13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
         end
     endcase
 end
 always @(*) begin
-    array_muxed14 <= 3'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self14 <= 3'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed14 <= litedramcore_nop_ba[2:0];
+            builder_self14 <= main_litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed14 <= litedramcore_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed15 <= 14'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self15 <= 14'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed15 <= litedramcore_nop_a;
+            builder_self15 <= main_litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a;
+            builder_self15 <= main_litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed15 <= litedramcore_choose_req_cmd_payload_a;
+            builder_self15 <= main_litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed15 <= litedramcore_cmd_payload_a;
+            builder_self15 <= main_litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed16 <= 1'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self16 <= 1'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed16 <= 1'd0;
+            builder_self16 <= 1'd0;
         end
         1'd1: begin
-            array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+            builder_self16 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+            builder_self16 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+            builder_self16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed17 <= 1'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self17 <= 1'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed17 <= 1'd0;
+            builder_self17 <= 1'd0;
         end
         1'd1: begin
-            array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+            builder_self17 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+            builder_self17 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+            builder_self17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed18 <= 1'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self18 <= 1'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed18 <= 1'd0;
+            builder_self18 <= 1'd0;
         end
         1'd1: begin
-            array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+            builder_self18 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+            builder_self18 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+            builder_self18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed19 <= 1'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self19 <= 1'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed19 <= 1'd0;
+            builder_self19 <= 1'd0;
         end
         1'd1: begin
-            array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+            builder_self19 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+            builder_self19 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+            builder_self19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed20 <= 1'd0;
-    case (litedramcore_steerer_sel2)
+    builder_self20 <= 1'd0;
+    case (main_litedramcore_steerer2)
         1'd0: begin
-            array_muxed20 <= 1'd0;
+            builder_self20 <= 1'd0;
         end
         1'd1: begin
-            array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+            builder_self20 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+            builder_self20 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+            builder_self20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
         end
     endcase
 end
 always @(*) begin
-    array_muxed21 <= 3'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self21 <= 3'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed21 <= litedramcore_nop_ba[2:0];
+            builder_self21 <= main_litedramcore_nop_ba[2:0];
         end
         1'd1: begin
-            array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
         end
         2'd2: begin
-            array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
         end
         default: begin
-            array_muxed21 <= litedramcore_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_cmd_payload_ba[2:0];
         end
     endcase
 end
 always @(*) begin
-    array_muxed22 <= 14'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self22 <= 14'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed22 <= litedramcore_nop_a;
+            builder_self22 <= main_litedramcore_nop_a;
         end
         1'd1: begin
-            array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a;
+            builder_self22 <= main_litedramcore_choose_cmd_cmd_payload_a;
         end
         2'd2: begin
-            array_muxed22 <= litedramcore_choose_req_cmd_payload_a;
+            builder_self22 <= main_litedramcore_choose_req_cmd_payload_a;
         end
         default: begin
-            array_muxed22 <= litedramcore_cmd_payload_a;
+            builder_self22 <= main_litedramcore_cmd_payload_a;
         end
     endcase
 end
 always @(*) begin
-    array_muxed23 <= 1'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self23 <= 1'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed23 <= 1'd0;
+            builder_self23 <= 1'd0;
         end
         1'd1: begin
-            array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+            builder_self23 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
         end
         2'd2: begin
-            array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+            builder_self23 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
         end
         default: begin
-            array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+            builder_self23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
         end
     endcase
 end
 always @(*) begin
-    array_muxed24 <= 1'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self24 <= 1'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed24 <= 1'd0;
+            builder_self24 <= 1'd0;
         end
         1'd1: begin
-            array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+            builder_self24 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
         end
         2'd2: begin
-            array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+            builder_self24 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
         end
         default: begin
-            array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+            builder_self24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
         end
     endcase
 end
 always @(*) begin
-    array_muxed25 <= 1'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self25 <= 1'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed25 <= 1'd0;
+            builder_self25 <= 1'd0;
         end
         1'd1: begin
-            array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+            builder_self25 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
         end
         2'd2: begin
-            array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+            builder_self25 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
         end
         default: begin
-            array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+            builder_self25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
         end
     endcase
 end
 always @(*) begin
-    array_muxed26 <= 1'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self26 <= 1'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed26 <= 1'd0;
+            builder_self26 <= 1'd0;
         end
         1'd1: begin
-            array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+            builder_self26 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
         end
         2'd2: begin
-            array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+            builder_self26 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
         end
         default: begin
-            array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+            builder_self26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
         end
     endcase
 end
 always @(*) begin
-    array_muxed27 <= 1'd0;
-    case (litedramcore_steerer_sel3)
+    builder_self27 <= 1'd0;
+    case (main_litedramcore_steerer3)
         1'd0: begin
-            array_muxed27 <= 1'd0;
+            builder_self27 <= 1'd0;
         end
         1'd1: begin
-            array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+            builder_self27 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
         end
         2'd2: begin
-            array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+            builder_self27 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
         end
         default: begin
-            array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+            builder_self27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
         end
     endcase
 end
-assign xilinxasyncresetsynchronizerimpl0 = (~locked);
-assign xilinxasyncresetsynchronizerimpl1 = (~locked);
-assign xilinxasyncresetsynchronizerimpl2 = (~locked);
-assign xilinxasyncresetsynchronizerimpl3 = (~locked);
+assign builder_xilinxasyncresetsynchronizerimpl0_async_reset = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl1_async_reset = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl2_async_reset = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl3_async_reset = (~main_locked);
 
 
 //------------------------------------------------------------------------------
@@ -11983,1044 +12398,1044 @@ assign xilinxasyncresetsynchronizerimpl3 = (~locked);
 //------------------------------------------------------------------------------
 
 always @(posedge iodelay_clk) begin
-    if ((reset_counter != 1'd0)) begin
-        reset_counter <= (reset_counter - 1'd1);
+    if ((main_reset_counter != 1'd0)) begin
+        main_reset_counter <= (main_reset_counter - 1'd1);
     end else begin
-        ic_reset <= 1'd0;
+        main_ic_reset <= 1'd0;
     end
     if (iodelay_rst) begin
-        reset_counter <= 4'd15;
-        ic_reset <= 1'd1;
+        main_reset_counter <= 4'd15;
+        main_ic_reset <= 1'd1;
     end
 end
 
 always @(posedge sys_clk) begin
-    a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline;
-    a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
-    a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0;
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1);
+    main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline;
+    main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
+    main_a7ddrphy_dqspattern_o1 <= main_a7ddrphy_dqspattern_o0;
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip0_value0 <= (main_a7ddrphy_bitslip0_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip0_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip0_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1);
+    main_a7ddrphy_bitslip0_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip0_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip1_value0 <= (main_a7ddrphy_bitslip1_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip1_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip1_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1);
+    main_a7ddrphy_bitslip1_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip1_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip0_value1 <= (main_a7ddrphy_bitslip0_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip0_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip0_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1);
+    main_a7ddrphy_bitslip0_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[2], main_a7ddrphy_dfi_p3_wrdata_mask[0], main_a7ddrphy_dfi_p2_wrdata_mask[2], main_a7ddrphy_dfi_p2_wrdata_mask[0], main_a7ddrphy_dfi_p1_wrdata_mask[2], main_a7ddrphy_dfi_p1_wrdata_mask[0], main_a7ddrphy_dfi_p0_wrdata_mask[2], main_a7ddrphy_dfi_p0_wrdata_mask[0]}, main_a7ddrphy_bitslip0_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip1_value1 <= (main_a7ddrphy_bitslip1_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip1_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip1_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]};
-    a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline;
-    a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1);
+    main_a7ddrphy_bitslip1_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[3], main_a7ddrphy_dfi_p3_wrdata_mask[1], main_a7ddrphy_dfi_p2_wrdata_mask[3], main_a7ddrphy_dfi_p2_wrdata_mask[1], main_a7ddrphy_dfi_p1_wrdata_mask[3], main_a7ddrphy_dfi_p1_wrdata_mask[1], main_a7ddrphy_dfi_p0_wrdata_mask[3], main_a7ddrphy_dfi_p0_wrdata_mask[1]}, main_a7ddrphy_bitslip1_r1[15:8]};
+    main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dq_oe_delay_tappeddelayline;
+    main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip0_value2 <= (main_a7ddrphy_bitslip0_value2 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip0_value2 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip0_value2 <= 3'd7;
     end
-    a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1);
+    main_a7ddrphy_bitslip0_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[16], main_a7ddrphy_dfi_p3_wrdata[0], main_a7ddrphy_dfi_p2_wrdata[16], main_a7ddrphy_dfi_p2_wrdata[0], main_a7ddrphy_dfi_p1_wrdata[16], main_a7ddrphy_dfi_p1_wrdata[0], main_a7ddrphy_dfi_p0_wrdata[16], main_a7ddrphy_dfi_p0_wrdata[0]}, main_a7ddrphy_bitslip0_r2[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip0_value3 <= (main_a7ddrphy_bitslip0_value3 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip0_value3 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip0_value3 <= 3'd7;
     end
-    a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1);
+    main_a7ddrphy_bitslip0_r3 <= {main_a7ddrphy_bitslip03, main_a7ddrphy_bitslip0_r3[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip1_value2 <= (main_a7ddrphy_bitslip1_value2 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip1_value2 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip1_value2 <= 3'd7;
     end
-    a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1);
+    main_a7ddrphy_bitslip1_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[17], main_a7ddrphy_dfi_p3_wrdata[1], main_a7ddrphy_dfi_p2_wrdata[17], main_a7ddrphy_dfi_p2_wrdata[1], main_a7ddrphy_dfi_p1_wrdata[17], main_a7ddrphy_dfi_p1_wrdata[1], main_a7ddrphy_dfi_p0_wrdata[17], main_a7ddrphy_dfi_p0_wrdata[1]}, main_a7ddrphy_bitslip1_r2[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip1_value3 <= (main_a7ddrphy_bitslip1_value3 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip1_value3 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip1_value3 <= 3'd7;
     end
-    a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1);
+    main_a7ddrphy_bitslip1_r3 <= {main_a7ddrphy_bitslip13, main_a7ddrphy_bitslip1_r3[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip2_value0 <= (main_a7ddrphy_bitslip2_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip2_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip2_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1);
+    main_a7ddrphy_bitslip2_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[18], main_a7ddrphy_dfi_p3_wrdata[2], main_a7ddrphy_dfi_p2_wrdata[18], main_a7ddrphy_dfi_p2_wrdata[2], main_a7ddrphy_dfi_p1_wrdata[18], main_a7ddrphy_dfi_p1_wrdata[2], main_a7ddrphy_dfi_p0_wrdata[18], main_a7ddrphy_dfi_p0_wrdata[2]}, main_a7ddrphy_bitslip2_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip2_value1 <= (main_a7ddrphy_bitslip2_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip2_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip2_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1);
+    main_a7ddrphy_bitslip2_r1 <= {main_a7ddrphy_bitslip21, main_a7ddrphy_bitslip2_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip3_value0 <= (main_a7ddrphy_bitslip3_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip3_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip3_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1);
+    main_a7ddrphy_bitslip3_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[19], main_a7ddrphy_dfi_p3_wrdata[3], main_a7ddrphy_dfi_p2_wrdata[19], main_a7ddrphy_dfi_p2_wrdata[3], main_a7ddrphy_dfi_p1_wrdata[19], main_a7ddrphy_dfi_p1_wrdata[3], main_a7ddrphy_dfi_p0_wrdata[19], main_a7ddrphy_dfi_p0_wrdata[3]}, main_a7ddrphy_bitslip3_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip3_value1 <= (main_a7ddrphy_bitslip3_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip3_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip3_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1);
+    main_a7ddrphy_bitslip3_r1 <= {main_a7ddrphy_bitslip31, main_a7ddrphy_bitslip3_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip4_value0 <= (main_a7ddrphy_bitslip4_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip4_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip4_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1);
+    main_a7ddrphy_bitslip4_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[20], main_a7ddrphy_dfi_p3_wrdata[4], main_a7ddrphy_dfi_p2_wrdata[20], main_a7ddrphy_dfi_p2_wrdata[4], main_a7ddrphy_dfi_p1_wrdata[20], main_a7ddrphy_dfi_p1_wrdata[4], main_a7ddrphy_dfi_p0_wrdata[20], main_a7ddrphy_dfi_p0_wrdata[4]}, main_a7ddrphy_bitslip4_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip4_value1 <= (main_a7ddrphy_bitslip4_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip4_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip4_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1);
+    main_a7ddrphy_bitslip4_r1 <= {main_a7ddrphy_bitslip41, main_a7ddrphy_bitslip4_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip5_value0 <= (main_a7ddrphy_bitslip5_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip5_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip5_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1);
+    main_a7ddrphy_bitslip5_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[21], main_a7ddrphy_dfi_p3_wrdata[5], main_a7ddrphy_dfi_p2_wrdata[21], main_a7ddrphy_dfi_p2_wrdata[5], main_a7ddrphy_dfi_p1_wrdata[21], main_a7ddrphy_dfi_p1_wrdata[5], main_a7ddrphy_dfi_p0_wrdata[21], main_a7ddrphy_dfi_p0_wrdata[5]}, main_a7ddrphy_bitslip5_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip5_value1 <= (main_a7ddrphy_bitslip5_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip5_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip5_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1);
+    main_a7ddrphy_bitslip5_r1 <= {main_a7ddrphy_bitslip51, main_a7ddrphy_bitslip5_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip6_value0 <= (main_a7ddrphy_bitslip6_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip6_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip6_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1);
+    main_a7ddrphy_bitslip6_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[22], main_a7ddrphy_dfi_p3_wrdata[6], main_a7ddrphy_dfi_p2_wrdata[22], main_a7ddrphy_dfi_p2_wrdata[6], main_a7ddrphy_dfi_p1_wrdata[22], main_a7ddrphy_dfi_p1_wrdata[6], main_a7ddrphy_dfi_p0_wrdata[22], main_a7ddrphy_dfi_p0_wrdata[6]}, main_a7ddrphy_bitslip6_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip6_value1 <= (main_a7ddrphy_bitslip6_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip6_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip6_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1);
+    main_a7ddrphy_bitslip6_r1 <= {main_a7ddrphy_bitslip61, main_a7ddrphy_bitslip6_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip7_value0 <= (main_a7ddrphy_bitslip7_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip7_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip7_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1);
+    main_a7ddrphy_bitslip7_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[23], main_a7ddrphy_dfi_p3_wrdata[7], main_a7ddrphy_dfi_p2_wrdata[23], main_a7ddrphy_dfi_p2_wrdata[7], main_a7ddrphy_dfi_p1_wrdata[23], main_a7ddrphy_dfi_p1_wrdata[7], main_a7ddrphy_dfi_p0_wrdata[23], main_a7ddrphy_dfi_p0_wrdata[7]}, main_a7ddrphy_bitslip7_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip7_value1 <= (main_a7ddrphy_bitslip7_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip7_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip7_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1);
+    main_a7ddrphy_bitslip7_r1 <= {main_a7ddrphy_bitslip71, main_a7ddrphy_bitslip7_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip8_value0 <= (main_a7ddrphy_bitslip8_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip8_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip8_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1);
+    main_a7ddrphy_bitslip8_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[24], main_a7ddrphy_dfi_p3_wrdata[8], main_a7ddrphy_dfi_p2_wrdata[24], main_a7ddrphy_dfi_p2_wrdata[8], main_a7ddrphy_dfi_p1_wrdata[24], main_a7ddrphy_dfi_p1_wrdata[8], main_a7ddrphy_dfi_p0_wrdata[24], main_a7ddrphy_dfi_p0_wrdata[8]}, main_a7ddrphy_bitslip8_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip8_value1 <= (main_a7ddrphy_bitslip8_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip8_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip8_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1);
+    main_a7ddrphy_bitslip8_r1 <= {main_a7ddrphy_bitslip81, main_a7ddrphy_bitslip8_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip9_value0 <= (main_a7ddrphy_bitslip9_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip9_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip9_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1);
+    main_a7ddrphy_bitslip9_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[25], main_a7ddrphy_dfi_p3_wrdata[9], main_a7ddrphy_dfi_p2_wrdata[25], main_a7ddrphy_dfi_p2_wrdata[9], main_a7ddrphy_dfi_p1_wrdata[25], main_a7ddrphy_dfi_p1_wrdata[9], main_a7ddrphy_dfi_p0_wrdata[25], main_a7ddrphy_dfi_p0_wrdata[9]}, main_a7ddrphy_bitslip9_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip9_value1 <= (main_a7ddrphy_bitslip9_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip9_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip9_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1);
+    main_a7ddrphy_bitslip9_r1 <= {main_a7ddrphy_bitslip91, main_a7ddrphy_bitslip9_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip10_value0 <= (main_a7ddrphy_bitslip10_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip10_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip10_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1);
+    main_a7ddrphy_bitslip10_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[26], main_a7ddrphy_dfi_p3_wrdata[10], main_a7ddrphy_dfi_p2_wrdata[26], main_a7ddrphy_dfi_p2_wrdata[10], main_a7ddrphy_dfi_p1_wrdata[26], main_a7ddrphy_dfi_p1_wrdata[10], main_a7ddrphy_dfi_p0_wrdata[26], main_a7ddrphy_dfi_p0_wrdata[10]}, main_a7ddrphy_bitslip10_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip10_value1 <= (main_a7ddrphy_bitslip10_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip10_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip10_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1);
+    main_a7ddrphy_bitslip10_r1 <= {main_a7ddrphy_bitslip101, main_a7ddrphy_bitslip10_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip11_value0 <= (main_a7ddrphy_bitslip11_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip11_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip11_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1);
+    main_a7ddrphy_bitslip11_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[27], main_a7ddrphy_dfi_p3_wrdata[11], main_a7ddrphy_dfi_p2_wrdata[27], main_a7ddrphy_dfi_p2_wrdata[11], main_a7ddrphy_dfi_p1_wrdata[27], main_a7ddrphy_dfi_p1_wrdata[11], main_a7ddrphy_dfi_p0_wrdata[27], main_a7ddrphy_dfi_p0_wrdata[11]}, main_a7ddrphy_bitslip11_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip11_value1 <= (main_a7ddrphy_bitslip11_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip11_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip11_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1);
+    main_a7ddrphy_bitslip11_r1 <= {main_a7ddrphy_bitslip111, main_a7ddrphy_bitslip11_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip12_value0 <= (main_a7ddrphy_bitslip12_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip12_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip12_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1);
+    main_a7ddrphy_bitslip12_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[28], main_a7ddrphy_dfi_p3_wrdata[12], main_a7ddrphy_dfi_p2_wrdata[28], main_a7ddrphy_dfi_p2_wrdata[12], main_a7ddrphy_dfi_p1_wrdata[28], main_a7ddrphy_dfi_p1_wrdata[12], main_a7ddrphy_dfi_p0_wrdata[28], main_a7ddrphy_dfi_p0_wrdata[12]}, main_a7ddrphy_bitslip12_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip12_value1 <= (main_a7ddrphy_bitslip12_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip12_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip12_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1);
+    main_a7ddrphy_bitslip12_r1 <= {main_a7ddrphy_bitslip121, main_a7ddrphy_bitslip12_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip13_value0 <= (main_a7ddrphy_bitslip13_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip13_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip13_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1);
+    main_a7ddrphy_bitslip13_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[29], main_a7ddrphy_dfi_p3_wrdata[13], main_a7ddrphy_dfi_p2_wrdata[29], main_a7ddrphy_dfi_p2_wrdata[13], main_a7ddrphy_dfi_p1_wrdata[29], main_a7ddrphy_dfi_p1_wrdata[13], main_a7ddrphy_dfi_p0_wrdata[29], main_a7ddrphy_dfi_p0_wrdata[13]}, main_a7ddrphy_bitslip13_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip13_value1 <= (main_a7ddrphy_bitslip13_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip13_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip13_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1);
+    main_a7ddrphy_bitslip13_r1 <= {main_a7ddrphy_bitslip131, main_a7ddrphy_bitslip13_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip14_value0 <= (main_a7ddrphy_bitslip14_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip14_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip14_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1);
+    main_a7ddrphy_bitslip14_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[30], main_a7ddrphy_dfi_p3_wrdata[14], main_a7ddrphy_dfi_p2_wrdata[30], main_a7ddrphy_dfi_p2_wrdata[14], main_a7ddrphy_dfi_p1_wrdata[30], main_a7ddrphy_dfi_p1_wrdata[14], main_a7ddrphy_dfi_p0_wrdata[30], main_a7ddrphy_dfi_p0_wrdata[14]}, main_a7ddrphy_bitslip14_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip14_value1 <= (main_a7ddrphy_bitslip14_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip14_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip14_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1);
+    main_a7ddrphy_bitslip14_r1 <= {main_a7ddrphy_bitslip141, main_a7ddrphy_bitslip14_r1[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip15_value0 <= (main_a7ddrphy_bitslip15_value0 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip15_value0 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip15_value0 <= 3'd7;
     end
-    a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]};
-    if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
-        a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1);
+    main_a7ddrphy_bitslip15_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[31], main_a7ddrphy_dfi_p3_wrdata[15], main_a7ddrphy_dfi_p2_wrdata[31], main_a7ddrphy_dfi_p2_wrdata[15], main_a7ddrphy_dfi_p1_wrdata[31], main_a7ddrphy_dfi_p1_wrdata[15], main_a7ddrphy_dfi_p0_wrdata[31], main_a7ddrphy_dfi_p0_wrdata[15]}, main_a7ddrphy_bitslip15_r0[15:8]};
+    if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+        main_a7ddrphy_bitslip15_value1 <= (main_a7ddrphy_bitslip15_value1 + 1'd1);
     end
-    if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
-        a7ddrphy_bitslip15_value1 <= 3'd7;
+    if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+        main_a7ddrphy_bitslip15_value1 <= 3'd7;
     end
-    a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]};
-    a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en);
-    a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0;
-    a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1;
-    a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2;
-    a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3;
-    a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4;
-    a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5;
-    a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6;
-    a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en);
-    a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0;
-    a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1;
-    if (litedramcore_csr_dfi_p0_rddata_valid) begin
-        litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata;
+    main_a7ddrphy_bitslip15_r1 <= {main_a7ddrphy_bitslip151, main_a7ddrphy_bitslip15_r1[15:8]};
+    main_a7ddrphy_rddata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_rddata_en | main_a7ddrphy_dfi_p1_rddata_en) | main_a7ddrphy_dfi_p2_rddata_en) | main_a7ddrphy_dfi_p3_rddata_en);
+    main_a7ddrphy_rddata_en_tappeddelayline1 <= main_a7ddrphy_rddata_en_tappeddelayline0;
+    main_a7ddrphy_rddata_en_tappeddelayline2 <= main_a7ddrphy_rddata_en_tappeddelayline1;
+    main_a7ddrphy_rddata_en_tappeddelayline3 <= main_a7ddrphy_rddata_en_tappeddelayline2;
+    main_a7ddrphy_rddata_en_tappeddelayline4 <= main_a7ddrphy_rddata_en_tappeddelayline3;
+    main_a7ddrphy_rddata_en_tappeddelayline5 <= main_a7ddrphy_rddata_en_tappeddelayline4;
+    main_a7ddrphy_rddata_en_tappeddelayline6 <= main_a7ddrphy_rddata_en_tappeddelayline5;
+    main_a7ddrphy_rddata_en_tappeddelayline7 <= main_a7ddrphy_rddata_en_tappeddelayline6;
+    main_a7ddrphy_wrdata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_wrdata_en | main_a7ddrphy_dfi_p1_wrdata_en) | main_a7ddrphy_dfi_p2_wrdata_en) | main_a7ddrphy_dfi_p3_wrdata_en);
+    main_a7ddrphy_wrdata_en_tappeddelayline1 <= main_a7ddrphy_wrdata_en_tappeddelayline0;
+    main_a7ddrphy_wrdata_en_tappeddelayline2 <= main_a7ddrphy_wrdata_en_tappeddelayline1;
+    if (main_litedramcore_csr_dfi_p0_rddata_valid) begin
+        main_litedramcore_phaseinjector0_rddata_status <= main_litedramcore_csr_dfi_p0_rddata;
     end
-    if (litedramcore_csr_dfi_p1_rddata_valid) begin
-        litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata;
+    if (main_litedramcore_csr_dfi_p1_rddata_valid) begin
+        main_litedramcore_phaseinjector1_rddata_status <= main_litedramcore_csr_dfi_p1_rddata;
     end
-    if (litedramcore_csr_dfi_p2_rddata_valid) begin
-        litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata;
+    if (main_litedramcore_csr_dfi_p2_rddata_valid) begin
+        main_litedramcore_phaseinjector2_rddata_status <= main_litedramcore_csr_dfi_p2_rddata;
     end
-    if (litedramcore_csr_dfi_p3_rddata_valid) begin
-        litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata;
-    end
-    if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
-        litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
+    if (main_litedramcore_csr_dfi_p3_rddata_valid) begin
+        main_litedramcore_phaseinjector3_rddata_status <= main_litedramcore_csr_dfi_p3_rddata;
+    end
+    if ((main_litedramcore_timer_wait & (~main_litedramcore_timer_done0))) begin
+        main_litedramcore_timer_count1 <= (main_litedramcore_timer_count1 - 1'd1);
     end else begin
-        litedramcore_timer_count1 <= 10'd781;
+        main_litedramcore_timer_count1 <= 10'd781;
     end
-    litedramcore_postponer_req_o <= 1'd0;
-    if (litedramcore_postponer_req_i) begin
-        litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
-        if ((litedramcore_postponer_count == 1'd0)) begin
-            litedramcore_postponer_count <= 1'd0;
-            litedramcore_postponer_req_o <= 1'd1;
-        end
+    main_litedramcore_postponer_req_o <= 1'd0;
+    if (main_litedramcore_postponer_req_i) begin
+        main_litedramcore_postponer_count <= (main_litedramcore_postponer_count - 1'd1);
+        if ((main_litedramcore_postponer_count == 1'd0)) begin
+            main_litedramcore_postponer_count <= 1'd0;
+            main_litedramcore_postponer_req_o <= 1'd1;
+        end
     end
-    if (litedramcore_sequencer_start0) begin
-        litedramcore_sequencer_count <= 1'd0;
-    end else begin
-        if (litedramcore_sequencer_done1) begin
-            if ((litedramcore_sequencer_count != 1'd0)) begin
-                litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
-            end
-        end
-    end
-    litedramcore_cmd_payload_a <= 1'd0;
-    litedramcore_cmd_payload_ba <= 1'd0;
-    litedramcore_cmd_payload_cas <= 1'd0;
-    litedramcore_cmd_payload_ras <= 1'd0;
-    litedramcore_cmd_payload_we <= 1'd0;
-    litedramcore_sequencer_done1 <= 1'd0;
-    if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
-        litedramcore_cmd_payload_a <= 11'd1024;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd1;
-        litedramcore_cmd_payload_we <= 1'd1;
-    end
-    if ((litedramcore_sequencer_counter == 2'd3)) begin
-        litedramcore_cmd_payload_a <= 11'd1024;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd1;
-        litedramcore_cmd_payload_ras <= 1'd1;
-        litedramcore_cmd_payload_we <= 1'd0;
-    end
-    if ((litedramcore_sequencer_counter == 6'd35)) begin
-        litedramcore_cmd_payload_a <= 1'd0;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd0;
-        litedramcore_cmd_payload_we <= 1'd0;
-        litedramcore_sequencer_done1 <= 1'd1;
-    end
-    if ((litedramcore_sequencer_counter == 6'd35)) begin
-        litedramcore_sequencer_counter <= 1'd0;
-    end else begin
-        if ((litedramcore_sequencer_counter != 1'd0)) begin
-            litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
+    if (main_litedramcore_sequencer_start0) begin
+        main_litedramcore_sequencer_count <= 1'd0;
+    end else begin
+        if (main_litedramcore_sequencer_done1) begin
+            if ((main_litedramcore_sequencer_count != 1'd0)) begin
+                main_litedramcore_sequencer_count <= (main_litedramcore_sequencer_count - 1'd1);
+            end
+        end
+    end
+    main_litedramcore_cmd_payload_a <= 1'd0;
+    main_litedramcore_cmd_payload_ba <= 1'd0;
+    main_litedramcore_cmd_payload_cas <= 1'd0;
+    main_litedramcore_cmd_payload_ras <= 1'd0;
+    main_litedramcore_cmd_payload_we <= 1'd0;
+    main_litedramcore_sequencer_done1 <= 1'd0;
+    if ((main_litedramcore_sequencer_start1 & (main_litedramcore_sequencer_trigger == 1'd0))) begin
+        main_litedramcore_cmd_payload_a <= 11'd1024;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd1;
+        main_litedramcore_cmd_payload_we <= 1'd1;
+    end
+    if ((main_litedramcore_sequencer_trigger == 2'd3)) begin
+        main_litedramcore_cmd_payload_a <= 11'd1024;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd1;
+        main_litedramcore_cmd_payload_ras <= 1'd1;
+        main_litedramcore_cmd_payload_we <= 1'd0;
+    end
+    if ((main_litedramcore_sequencer_trigger == 6'd35)) begin
+        main_litedramcore_cmd_payload_a <= 1'd0;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd0;
+        main_litedramcore_cmd_payload_we <= 1'd0;
+        main_litedramcore_sequencer_done1 <= 1'd1;
+    end
+    if ((main_litedramcore_sequencer_trigger == 6'd35)) begin
+        main_litedramcore_sequencer_trigger <= 1'd0;
+    end else begin
+        if ((main_litedramcore_sequencer_trigger != 1'd0)) begin
+            main_litedramcore_sequencer_trigger <= (main_litedramcore_sequencer_trigger + 1'd1);
         end else begin
-            if (litedramcore_sequencer_start1) begin
-                litedramcore_sequencer_counter <= 1'd1;
+            if (main_litedramcore_sequencer_start1) begin
+                main_litedramcore_sequencer_trigger <= 1'd1;
             end
         end
     end
-    if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
-        litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
+    if ((main_litedramcore_zqcs_timer_wait & (~main_litedramcore_zqcs_timer_done0))) begin
+        main_litedramcore_zqcs_timer_count1 <= (main_litedramcore_zqcs_timer_count1 - 1'd1);
     end else begin
-        litedramcore_zqcs_timer_count1 <= 27'd99999999;
-    end
-    litedramcore_zqcs_executer_done <= 1'd0;
-    if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
-        litedramcore_cmd_payload_a <= 11'd1024;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd1;
-        litedramcore_cmd_payload_we <= 1'd1;
-    end
-    if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
-        litedramcore_cmd_payload_a <= 1'd0;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd0;
-        litedramcore_cmd_payload_we <= 1'd1;
-    end
-    if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
-        litedramcore_cmd_payload_a <= 1'd0;
-        litedramcore_cmd_payload_ba <= 1'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd0;
-        litedramcore_cmd_payload_we <= 1'd0;
-        litedramcore_zqcs_executer_done <= 1'd1;
-    end
-    if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
-        litedramcore_zqcs_executer_counter <= 1'd0;
+        main_litedramcore_zqcs_timer_count1 <= 27'd99999999;
+    end
+    main_litedramcore_zqcs_executer_done <= 1'd0;
+    if ((main_litedramcore_zqcs_executer_start & (main_litedramcore_zqcs_executer_trigger == 1'd0))) begin
+        main_litedramcore_cmd_payload_a <= 11'd1024;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd1;
+        main_litedramcore_cmd_payload_we <= 1'd1;
+    end
+    if ((main_litedramcore_zqcs_executer_trigger == 2'd3)) begin
+        main_litedramcore_cmd_payload_a <= 1'd0;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd0;
+        main_litedramcore_cmd_payload_we <= 1'd1;
+    end
+    if ((main_litedramcore_zqcs_executer_trigger == 5'd19)) begin
+        main_litedramcore_cmd_payload_a <= 1'd0;
+        main_litedramcore_cmd_payload_ba <= 1'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd0;
+        main_litedramcore_cmd_payload_we <= 1'd0;
+        main_litedramcore_zqcs_executer_done <= 1'd1;
+    end
+    if ((main_litedramcore_zqcs_executer_trigger == 5'd19)) begin
+        main_litedramcore_zqcs_executer_trigger <= 1'd0;
     end else begin
-        if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
-            litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
+        if ((main_litedramcore_zqcs_executer_trigger != 1'd0)) begin
+            main_litedramcore_zqcs_executer_trigger <= (main_litedramcore_zqcs_executer_trigger + 1'd1);
         end else begin
-            if (litedramcore_zqcs_executer_start) begin
-                litedramcore_zqcs_executer_counter <= 1'd1;
+            if (main_litedramcore_zqcs_executer_start) begin
+                main_litedramcore_zqcs_executer_trigger <= 1'd1;
             end
         end
     end
-    litedramcore_refresher_state <= litedramcore_refresher_next_state;
-    if (litedramcore_bankmachine0_row_close) begin
-        litedramcore_bankmachine0_row_opened <= 1'd0;
+    builder_refresher_state <= builder_refresher_next_state;
+    if (main_litedramcore_bankmachine0_row_close) begin
+        main_litedramcore_bankmachine0_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine0_row_open) begin
-            litedramcore_bankmachine0_row_opened <= 1'd1;
-            litedramcore_bankmachine0_row <= litedramcore_bankmachine0_source_source_payload_addr[20:7];
+        if (main_litedramcore_bankmachine0_row_open) begin
+            main_litedramcore_bankmachine0_row_opened <= 1'd1;
+            main_litedramcore_bankmachine0_row <= main_litedramcore_bankmachine0_source_source_payload_addr[20:7];
         end
     end
-    if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin
-        litedramcore_bankmachine0_produce <= (litedramcore_bankmachine0_produce + 1'd1);
+    if (((main_litedramcore_bankmachine0_syncfifo0_we & main_litedramcore_bankmachine0_syncfifo0_writable) & (~main_litedramcore_bankmachine0_replace))) begin
+        main_litedramcore_bankmachine0_produce <= (main_litedramcore_bankmachine0_produce + 1'd1);
     end
-    if (litedramcore_bankmachine0_do_read) begin
-        litedramcore_bankmachine0_consume <= (litedramcore_bankmachine0_consume + 1'd1);
+    if (main_litedramcore_bankmachine0_do_read) begin
+        main_litedramcore_bankmachine0_consume <= (main_litedramcore_bankmachine0_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin
-        if ((~litedramcore_bankmachine0_do_read)) begin
-            litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level + 1'd1);
+    if (((main_litedramcore_bankmachine0_syncfifo0_we & main_litedramcore_bankmachine0_syncfifo0_writable) & (~main_litedramcore_bankmachine0_replace))) begin
+        if ((~main_litedramcore_bankmachine0_do_read)) begin
+            main_litedramcore_bankmachine0_level <= (main_litedramcore_bankmachine0_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine0_do_read) begin
-            litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level - 1'd1);
+        if (main_litedramcore_bankmachine0_do_read) begin
+            main_litedramcore_bankmachine0_level <= (main_litedramcore_bankmachine0_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine0_pipe_valid_source_valid <= litedramcore_bankmachine0_pipe_valid_sink_valid;
-        litedramcore_bankmachine0_pipe_valid_source_first <= litedramcore_bankmachine0_pipe_valid_sink_first;
-        litedramcore_bankmachine0_pipe_valid_source_last <= litedramcore_bankmachine0_pipe_valid_sink_last;
-        litedramcore_bankmachine0_pipe_valid_source_payload_we <= litedramcore_bankmachine0_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine0_pipe_valid_source_valid) | main_litedramcore_bankmachine0_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine0_pipe_valid_source_valid <= main_litedramcore_bankmachine0_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine0_pipe_valid_source_first <= main_litedramcore_bankmachine0_pipe_valid_sink_first;
+        main_litedramcore_bankmachine0_pipe_valid_source_last <= main_litedramcore_bankmachine0_pipe_valid_sink_last;
+        main_litedramcore_bankmachine0_pipe_valid_source_payload_we <= main_litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine0_twtpcon_valid) begin
-        litedramcore_bankmachine0_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine0_twtpcon_valid) begin
+        main_litedramcore_bankmachine0_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
-            litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine0_twtpcon_ready)) begin
+            main_litedramcore_bankmachine0_twtpcon_count <= (main_litedramcore_bankmachine0_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine0_trccon_valid) begin
-        litedramcore_bankmachine0_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine0_trccon_valid) begin
+        main_litedramcore_bankmachine0_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine0_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine0_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine0_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine0_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine0_trccon_ready)) begin
-            litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine0_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine0_trccon_ready)) begin
+            main_litedramcore_bankmachine0_trccon_count <= (main_litedramcore_bankmachine0_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine0_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine0_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine0_trascon_valid) begin
-        litedramcore_bankmachine0_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine0_trascon_valid) begin
+        main_litedramcore_bankmachine0_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine0_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine0_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine0_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine0_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine0_trascon_ready)) begin
-            litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine0_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine0_trascon_ready)) begin
+            main_litedramcore_bankmachine0_trascon_count <= (main_litedramcore_bankmachine0_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine0_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine0_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
-    if (litedramcore_bankmachine1_row_close) begin
-        litedramcore_bankmachine1_row_opened <= 1'd0;
+    builder_bankmachine0_state <= builder_bankmachine0_next_state;
+    if (main_litedramcore_bankmachine1_row_close) begin
+        main_litedramcore_bankmachine1_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine1_row_open) begin
-            litedramcore_bankmachine1_row_opened <= 1'd1;
-            litedramcore_bankmachine1_row <= litedramcore_bankmachine1_source_source_payload_addr[20:7];
+        if (main_litedramcore_bankmachine1_row_open) begin
+            main_litedramcore_bankmachine1_row_opened <= 1'd1;
+            main_litedramcore_bankmachine1_row <= main_litedramcore_bankmachine1_source_source_payload_addr[20:7];
         end
     end
-    if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin
-        litedramcore_bankmachine1_produce <= (litedramcore_bankmachine1_produce + 1'd1);
+    if (((main_litedramcore_bankmachine1_syncfifo1_we & main_litedramcore_bankmachine1_syncfifo1_writable) & (~main_litedramcore_bankmachine1_replace))) begin
+        main_litedramcore_bankmachine1_produce <= (main_litedramcore_bankmachine1_produce + 1'd1);
     end
-    if (litedramcore_bankmachine1_do_read) begin
-        litedramcore_bankmachine1_consume <= (litedramcore_bankmachine1_consume + 1'd1);
+    if (main_litedramcore_bankmachine1_do_read) begin
+        main_litedramcore_bankmachine1_consume <= (main_litedramcore_bankmachine1_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin
-        if ((~litedramcore_bankmachine1_do_read)) begin
-            litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level + 1'd1);
+    if (((main_litedramcore_bankmachine1_syncfifo1_we & main_litedramcore_bankmachine1_syncfifo1_writable) & (~main_litedramcore_bankmachine1_replace))) begin
+        if ((~main_litedramcore_bankmachine1_do_read)) begin
+            main_litedramcore_bankmachine1_level <= (main_litedramcore_bankmachine1_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine1_do_read) begin
-            litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level - 1'd1);
+        if (main_litedramcore_bankmachine1_do_read) begin
+            main_litedramcore_bankmachine1_level <= (main_litedramcore_bankmachine1_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine1_pipe_valid_source_valid <= litedramcore_bankmachine1_pipe_valid_sink_valid;
-        litedramcore_bankmachine1_pipe_valid_source_first <= litedramcore_bankmachine1_pipe_valid_sink_first;
-        litedramcore_bankmachine1_pipe_valid_source_last <= litedramcore_bankmachine1_pipe_valid_sink_last;
-        litedramcore_bankmachine1_pipe_valid_source_payload_we <= litedramcore_bankmachine1_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine1_pipe_valid_source_valid) | main_litedramcore_bankmachine1_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine1_pipe_valid_source_valid <= main_litedramcore_bankmachine1_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine1_pipe_valid_source_first <= main_litedramcore_bankmachine1_pipe_valid_sink_first;
+        main_litedramcore_bankmachine1_pipe_valid_source_last <= main_litedramcore_bankmachine1_pipe_valid_sink_last;
+        main_litedramcore_bankmachine1_pipe_valid_source_payload_we <= main_litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine1_twtpcon_valid) begin
-        litedramcore_bankmachine1_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine1_twtpcon_valid) begin
+        main_litedramcore_bankmachine1_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
-            litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine1_twtpcon_ready)) begin
+            main_litedramcore_bankmachine1_twtpcon_count <= (main_litedramcore_bankmachine1_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine1_trccon_valid) begin
-        litedramcore_bankmachine1_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine1_trccon_valid) begin
+        main_litedramcore_bankmachine1_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine1_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine1_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine1_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine1_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine1_trccon_ready)) begin
-            litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine1_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine1_trccon_ready)) begin
+            main_litedramcore_bankmachine1_trccon_count <= (main_litedramcore_bankmachine1_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine1_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine1_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine1_trascon_valid) begin
-        litedramcore_bankmachine1_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine1_trascon_valid) begin
+        main_litedramcore_bankmachine1_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine1_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine1_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine1_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine1_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine1_trascon_ready)) begin
-            litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine1_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine1_trascon_ready)) begin
+            main_litedramcore_bankmachine1_trascon_count <= (main_litedramcore_bankmachine1_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine1_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine1_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
-    if (litedramcore_bankmachine2_row_close) begin
-        litedramcore_bankmachine2_row_opened <= 1'd0;
+    builder_bankmachine1_state <= builder_bankmachine1_next_state;
+    if (main_litedramcore_bankmachine2_row_close) begin
+        main_litedramcore_bankmachine2_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine2_row_open) begin
-            litedramcore_bankmachine2_row_opened <= 1'd1;
-            litedramcore_bankmachine2_row <= litedramcore_bankmachine2_source_source_payload_addr[20:7];
+        if (main_litedramcore_bankmachine2_row_open) begin
+            main_litedramcore_bankmachine2_row_opened <= 1'd1;
+            main_litedramcore_bankmachine2_row <= main_litedramcore_bankmachine2_source_source_payload_addr[20:7];
         end
     end
-    if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin
-        litedramcore_bankmachine2_produce <= (litedramcore_bankmachine2_produce + 1'd1);
+    if (((main_litedramcore_bankmachine2_syncfifo2_we & main_litedramcore_bankmachine2_syncfifo2_writable) & (~main_litedramcore_bankmachine2_replace))) begin
+        main_litedramcore_bankmachine2_produce <= (main_litedramcore_bankmachine2_produce + 1'd1);
     end
-    if (litedramcore_bankmachine2_do_read) begin
-        litedramcore_bankmachine2_consume <= (litedramcore_bankmachine2_consume + 1'd1);
+    if (main_litedramcore_bankmachine2_do_read) begin
+        main_litedramcore_bankmachine2_consume <= (main_litedramcore_bankmachine2_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin
-        if ((~litedramcore_bankmachine2_do_read)) begin
-            litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level + 1'd1);
+    if (((main_litedramcore_bankmachine2_syncfifo2_we & main_litedramcore_bankmachine2_syncfifo2_writable) & (~main_litedramcore_bankmachine2_replace))) begin
+        if ((~main_litedramcore_bankmachine2_do_read)) begin
+            main_litedramcore_bankmachine2_level <= (main_litedramcore_bankmachine2_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine2_do_read) begin
-            litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level - 1'd1);
+        if (main_litedramcore_bankmachine2_do_read) begin
+            main_litedramcore_bankmachine2_level <= (main_litedramcore_bankmachine2_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine2_pipe_valid_source_valid <= litedramcore_bankmachine2_pipe_valid_sink_valid;
-        litedramcore_bankmachine2_pipe_valid_source_first <= litedramcore_bankmachine2_pipe_valid_sink_first;
-        litedramcore_bankmachine2_pipe_valid_source_last <= litedramcore_bankmachine2_pipe_valid_sink_last;
-        litedramcore_bankmachine2_pipe_valid_source_payload_we <= litedramcore_bankmachine2_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine2_pipe_valid_source_valid) | main_litedramcore_bankmachine2_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine2_pipe_valid_source_valid <= main_litedramcore_bankmachine2_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine2_pipe_valid_source_first <= main_litedramcore_bankmachine2_pipe_valid_sink_first;
+        main_litedramcore_bankmachine2_pipe_valid_source_last <= main_litedramcore_bankmachine2_pipe_valid_sink_last;
+        main_litedramcore_bankmachine2_pipe_valid_source_payload_we <= main_litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine2_twtpcon_valid) begin
-        litedramcore_bankmachine2_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine2_twtpcon_valid) begin
+        main_litedramcore_bankmachine2_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
-            litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine2_twtpcon_ready)) begin
+            main_litedramcore_bankmachine2_twtpcon_count <= (main_litedramcore_bankmachine2_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine2_trccon_valid) begin
-        litedramcore_bankmachine2_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine2_trccon_valid) begin
+        main_litedramcore_bankmachine2_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine2_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine2_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine2_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine2_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine2_trccon_ready)) begin
-            litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine2_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine2_trccon_ready)) begin
+            main_litedramcore_bankmachine2_trccon_count <= (main_litedramcore_bankmachine2_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine2_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine2_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine2_trascon_valid) begin
-        litedramcore_bankmachine2_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine2_trascon_valid) begin
+        main_litedramcore_bankmachine2_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine2_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine2_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine2_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine2_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine2_trascon_ready)) begin
-            litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine2_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine2_trascon_ready)) begin
+            main_litedramcore_bankmachine2_trascon_count <= (main_litedramcore_bankmachine2_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine2_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine2_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
-    if (litedramcore_bankmachine3_row_close) begin
-        litedramcore_bankmachine3_row_opened <= 1'd0;
+    builder_bankmachine2_state <= builder_bankmachine2_next_state;
+    if (main_litedramcore_bankmachine3_row_close) begin
+        main_litedramcore_bankmachine3_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine3_row_open) begin
-            litedramcore_bankmachine3_row_opened <= 1'd1;
-            litedramcore_bankmachine3_row <= litedramcore_bankmachine3_source_source_payload_addr[20:7];
+        if (main_litedramcore_bankmachine3_row_open) begin
+            main_litedramcore_bankmachine3_row_opened <= 1'd1;
+            main_litedramcore_bankmachine3_row <= main_litedramcore_bankmachine3_source_source_payload_addr[20:7];
         end
     end
-    if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin
-        litedramcore_bankmachine3_produce <= (litedramcore_bankmachine3_produce + 1'd1);
+    if (((main_litedramcore_bankmachine3_syncfifo3_we & main_litedramcore_bankmachine3_syncfifo3_writable) & (~main_litedramcore_bankmachine3_replace))) begin
+        main_litedramcore_bankmachine3_produce <= (main_litedramcore_bankmachine3_produce + 1'd1);
     end
-    if (litedramcore_bankmachine3_do_read) begin
-        litedramcore_bankmachine3_consume <= (litedramcore_bankmachine3_consume + 1'd1);
+    if (main_litedramcore_bankmachine3_do_read) begin
+        main_litedramcore_bankmachine3_consume <= (main_litedramcore_bankmachine3_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin
-        if ((~litedramcore_bankmachine3_do_read)) begin
-            litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level + 1'd1);
+    if (((main_litedramcore_bankmachine3_syncfifo3_we & main_litedramcore_bankmachine3_syncfifo3_writable) & (~main_litedramcore_bankmachine3_replace))) begin
+        if ((~main_litedramcore_bankmachine3_do_read)) begin
+            main_litedramcore_bankmachine3_level <= (main_litedramcore_bankmachine3_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine3_do_read) begin
-            litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level - 1'd1);
+        if (main_litedramcore_bankmachine3_do_read) begin
+            main_litedramcore_bankmachine3_level <= (main_litedramcore_bankmachine3_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine3_pipe_valid_source_valid <= litedramcore_bankmachine3_pipe_valid_sink_valid;
-        litedramcore_bankmachine3_pipe_valid_source_first <= litedramcore_bankmachine3_pipe_valid_sink_first;
-        litedramcore_bankmachine3_pipe_valid_source_last <= litedramcore_bankmachine3_pipe_valid_sink_last;
-        litedramcore_bankmachine3_pipe_valid_source_payload_we <= litedramcore_bankmachine3_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine3_pipe_valid_source_valid) | main_litedramcore_bankmachine3_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine3_pipe_valid_source_valid <= main_litedramcore_bankmachine3_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine3_pipe_valid_source_first <= main_litedramcore_bankmachine3_pipe_valid_sink_first;
+        main_litedramcore_bankmachine3_pipe_valid_source_last <= main_litedramcore_bankmachine3_pipe_valid_sink_last;
+        main_litedramcore_bankmachine3_pipe_valid_source_payload_we <= main_litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine3_twtpcon_valid) begin
-        litedramcore_bankmachine3_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine3_twtpcon_valid) begin
+        main_litedramcore_bankmachine3_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
-            litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine3_twtpcon_ready)) begin
+            main_litedramcore_bankmachine3_twtpcon_count <= (main_litedramcore_bankmachine3_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine3_trccon_valid) begin
-        litedramcore_bankmachine3_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine3_trccon_valid) begin
+        main_litedramcore_bankmachine3_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine3_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine3_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine3_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine3_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine3_trccon_ready)) begin
-            litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine3_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine3_trccon_ready)) begin
+            main_litedramcore_bankmachine3_trccon_count <= (main_litedramcore_bankmachine3_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine3_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine3_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine3_trascon_valid) begin
-        litedramcore_bankmachine3_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine3_trascon_valid) begin
+        main_litedramcore_bankmachine3_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine3_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine3_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine3_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine3_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine3_trascon_ready)) begin
-            litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine3_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine3_trascon_ready)) begin
+            main_litedramcore_bankmachine3_trascon_count <= (main_litedramcore_bankmachine3_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine3_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine3_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
-    if (litedramcore_bankmachine4_row_close) begin
-        litedramcore_bankmachine4_row_opened <= 1'd0;
+    builder_bankmachine3_state <= builder_bankmachine3_next_state;
+    if (main_litedramcore_bankmachine4_row_close) begin
+        main_litedramcore_bankmachine4_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine4_row_open) begin
-            litedramcore_bankmachine4_row_opened <= 1'd1;
-            litedramcore_bankmachine4_row <= litedramcore_bankmachine4_source_source_payload_addr[20:7];
+        if (main_litedramcore_bankmachine4_row_open) begin
+            main_litedramcore_bankmachine4_row_opened <= 1'd1;
+            main_litedramcore_bankmachine4_row <= main_litedramcore_bankmachine4_source_source_payload_addr[20:7];
         end
     end
-    if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin
-        litedramcore_bankmachine4_produce <= (litedramcore_bankmachine4_produce + 1'd1);
+    if (((main_litedramcore_bankmachine4_syncfifo4_we & main_litedramcore_bankmachine4_syncfifo4_writable) & (~main_litedramcore_bankmachine4_replace))) begin
+        main_litedramcore_bankmachine4_produce <= (main_litedramcore_bankmachine4_produce + 1'd1);
     end
-    if (litedramcore_bankmachine4_do_read) begin
-        litedramcore_bankmachine4_consume <= (litedramcore_bankmachine4_consume + 1'd1);
+    if (main_litedramcore_bankmachine4_do_read) begin
+        main_litedramcore_bankmachine4_consume <= (main_litedramcore_bankmachine4_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin
-        if ((~litedramcore_bankmachine4_do_read)) begin
-            litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level + 1'd1);
+    if (((main_litedramcore_bankmachine4_syncfifo4_we & main_litedramcore_bankmachine4_syncfifo4_writable) & (~main_litedramcore_bankmachine4_replace))) begin
+        if ((~main_litedramcore_bankmachine4_do_read)) begin
+            main_litedramcore_bankmachine4_level <= (main_litedramcore_bankmachine4_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine4_do_read) begin
-            litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level - 1'd1);
+        if (main_litedramcore_bankmachine4_do_read) begin
+            main_litedramcore_bankmachine4_level <= (main_litedramcore_bankmachine4_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine4_pipe_valid_source_valid <= litedramcore_bankmachine4_pipe_valid_sink_valid;
-        litedramcore_bankmachine4_pipe_valid_source_first <= litedramcore_bankmachine4_pipe_valid_sink_first;
-        litedramcore_bankmachine4_pipe_valid_source_last <= litedramcore_bankmachine4_pipe_valid_sink_last;
-        litedramcore_bankmachine4_pipe_valid_source_payload_we <= litedramcore_bankmachine4_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine4_pipe_valid_source_valid) | main_litedramcore_bankmachine4_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine4_pipe_valid_source_valid <= main_litedramcore_bankmachine4_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine4_pipe_valid_source_first <= main_litedramcore_bankmachine4_pipe_valid_sink_first;
+        main_litedramcore_bankmachine4_pipe_valid_source_last <= main_litedramcore_bankmachine4_pipe_valid_sink_last;
+        main_litedramcore_bankmachine4_pipe_valid_source_payload_we <= main_litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine4_twtpcon_valid) begin
-        litedramcore_bankmachine4_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine4_twtpcon_valid) begin
+        main_litedramcore_bankmachine4_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
-            litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine4_twtpcon_ready)) begin
+            main_litedramcore_bankmachine4_twtpcon_count <= (main_litedramcore_bankmachine4_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine4_trccon_valid) begin
-        litedramcore_bankmachine4_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine4_trccon_valid) begin
+        main_litedramcore_bankmachine4_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine4_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine4_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine4_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine4_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine4_trccon_ready)) begin
-            litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine4_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine4_trccon_ready)) begin
+            main_litedramcore_bankmachine4_trccon_count <= (main_litedramcore_bankmachine4_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine4_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine4_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine4_trascon_valid) begin
-        litedramcore_bankmachine4_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine4_trascon_valid) begin
+        main_litedramcore_bankmachine4_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine4_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine4_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine4_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine4_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine4_trascon_ready)) begin
-            litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine4_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine4_trascon_ready)) begin
+            main_litedramcore_bankmachine4_trascon_count <= (main_litedramcore_bankmachine4_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine4_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine4_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
-    if (litedramcore_bankmachine5_row_close) begin
-        litedramcore_bankmachine5_row_opened <= 1'd0;
+    builder_bankmachine4_state <= builder_bankmachine4_next_state;
+    if (main_litedramcore_bankmachine5_row_close) begin
+        main_litedramcore_bankmachine5_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine5_row_open) begin
-            litedramcore_bankmachine5_row_opened <= 1'd1;
-            litedramcore_bankmachine5_row <= litedramcore_bankmachine5_source_source_payload_addr[20:7];
+        if (main_litedramcore_bankmachine5_row_open) begin
+            main_litedramcore_bankmachine5_row_opened <= 1'd1;
+            main_litedramcore_bankmachine5_row <= main_litedramcore_bankmachine5_source_source_payload_addr[20:7];
         end
     end
-    if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin
-        litedramcore_bankmachine5_produce <= (litedramcore_bankmachine5_produce + 1'd1);
+    if (((main_litedramcore_bankmachine5_syncfifo5_we & main_litedramcore_bankmachine5_syncfifo5_writable) & (~main_litedramcore_bankmachine5_replace))) begin
+        main_litedramcore_bankmachine5_produce <= (main_litedramcore_bankmachine5_produce + 1'd1);
     end
-    if (litedramcore_bankmachine5_do_read) begin
-        litedramcore_bankmachine5_consume <= (litedramcore_bankmachine5_consume + 1'd1);
+    if (main_litedramcore_bankmachine5_do_read) begin
+        main_litedramcore_bankmachine5_consume <= (main_litedramcore_bankmachine5_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin
-        if ((~litedramcore_bankmachine5_do_read)) begin
-            litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level + 1'd1);
+    if (((main_litedramcore_bankmachine5_syncfifo5_we & main_litedramcore_bankmachine5_syncfifo5_writable) & (~main_litedramcore_bankmachine5_replace))) begin
+        if ((~main_litedramcore_bankmachine5_do_read)) begin
+            main_litedramcore_bankmachine5_level <= (main_litedramcore_bankmachine5_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine5_do_read) begin
-            litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level - 1'd1);
+        if (main_litedramcore_bankmachine5_do_read) begin
+            main_litedramcore_bankmachine5_level <= (main_litedramcore_bankmachine5_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine5_pipe_valid_source_valid <= litedramcore_bankmachine5_pipe_valid_sink_valid;
-        litedramcore_bankmachine5_pipe_valid_source_first <= litedramcore_bankmachine5_pipe_valid_sink_first;
-        litedramcore_bankmachine5_pipe_valid_source_last <= litedramcore_bankmachine5_pipe_valid_sink_last;
-        litedramcore_bankmachine5_pipe_valid_source_payload_we <= litedramcore_bankmachine5_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine5_pipe_valid_source_valid) | main_litedramcore_bankmachine5_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine5_pipe_valid_source_valid <= main_litedramcore_bankmachine5_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine5_pipe_valid_source_first <= main_litedramcore_bankmachine5_pipe_valid_sink_first;
+        main_litedramcore_bankmachine5_pipe_valid_source_last <= main_litedramcore_bankmachine5_pipe_valid_sink_last;
+        main_litedramcore_bankmachine5_pipe_valid_source_payload_we <= main_litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine5_twtpcon_valid) begin
-        litedramcore_bankmachine5_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine5_twtpcon_valid) begin
+        main_litedramcore_bankmachine5_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
-            litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine5_twtpcon_ready)) begin
+            main_litedramcore_bankmachine5_twtpcon_count <= (main_litedramcore_bankmachine5_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine5_trccon_valid) begin
-        litedramcore_bankmachine5_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine5_trccon_valid) begin
+        main_litedramcore_bankmachine5_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine5_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine5_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine5_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine5_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine5_trccon_ready)) begin
-            litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine5_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine5_trccon_ready)) begin
+            main_litedramcore_bankmachine5_trccon_count <= (main_litedramcore_bankmachine5_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine5_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine5_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine5_trascon_valid) begin
-        litedramcore_bankmachine5_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine5_trascon_valid) begin
+        main_litedramcore_bankmachine5_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine5_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine5_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine5_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine5_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine5_trascon_ready)) begin
-            litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine5_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine5_trascon_ready)) begin
+            main_litedramcore_bankmachine5_trascon_count <= (main_litedramcore_bankmachine5_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine5_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine5_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
-    if (litedramcore_bankmachine6_row_close) begin
-        litedramcore_bankmachine6_row_opened <= 1'd0;
+    builder_bankmachine5_state <= builder_bankmachine5_next_state;
+    if (main_litedramcore_bankmachine6_row_close) begin
+        main_litedramcore_bankmachine6_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine6_row_open) begin
-            litedramcore_bankmachine6_row_opened <= 1'd1;
-            litedramcore_bankmachine6_row <= litedramcore_bankmachine6_source_source_payload_addr[20:7];
+        if (main_litedramcore_bankmachine6_row_open) begin
+            main_litedramcore_bankmachine6_row_opened <= 1'd1;
+            main_litedramcore_bankmachine6_row <= main_litedramcore_bankmachine6_source_source_payload_addr[20:7];
         end
     end
-    if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin
-        litedramcore_bankmachine6_produce <= (litedramcore_bankmachine6_produce + 1'd1);
+    if (((main_litedramcore_bankmachine6_syncfifo6_we & main_litedramcore_bankmachine6_syncfifo6_writable) & (~main_litedramcore_bankmachine6_replace))) begin
+        main_litedramcore_bankmachine6_produce <= (main_litedramcore_bankmachine6_produce + 1'd1);
     end
-    if (litedramcore_bankmachine6_do_read) begin
-        litedramcore_bankmachine6_consume <= (litedramcore_bankmachine6_consume + 1'd1);
+    if (main_litedramcore_bankmachine6_do_read) begin
+        main_litedramcore_bankmachine6_consume <= (main_litedramcore_bankmachine6_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin
-        if ((~litedramcore_bankmachine6_do_read)) begin
-            litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level + 1'd1);
+    if (((main_litedramcore_bankmachine6_syncfifo6_we & main_litedramcore_bankmachine6_syncfifo6_writable) & (~main_litedramcore_bankmachine6_replace))) begin
+        if ((~main_litedramcore_bankmachine6_do_read)) begin
+            main_litedramcore_bankmachine6_level <= (main_litedramcore_bankmachine6_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine6_do_read) begin
-            litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level - 1'd1);
+        if (main_litedramcore_bankmachine6_do_read) begin
+            main_litedramcore_bankmachine6_level <= (main_litedramcore_bankmachine6_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine6_pipe_valid_source_valid <= litedramcore_bankmachine6_pipe_valid_sink_valid;
-        litedramcore_bankmachine6_pipe_valid_source_first <= litedramcore_bankmachine6_pipe_valid_sink_first;
-        litedramcore_bankmachine6_pipe_valid_source_last <= litedramcore_bankmachine6_pipe_valid_sink_last;
-        litedramcore_bankmachine6_pipe_valid_source_payload_we <= litedramcore_bankmachine6_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine6_pipe_valid_source_valid) | main_litedramcore_bankmachine6_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine6_pipe_valid_source_valid <= main_litedramcore_bankmachine6_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine6_pipe_valid_source_first <= main_litedramcore_bankmachine6_pipe_valid_sink_first;
+        main_litedramcore_bankmachine6_pipe_valid_source_last <= main_litedramcore_bankmachine6_pipe_valid_sink_last;
+        main_litedramcore_bankmachine6_pipe_valid_source_payload_we <= main_litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine6_twtpcon_valid) begin
-        litedramcore_bankmachine6_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine6_twtpcon_valid) begin
+        main_litedramcore_bankmachine6_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
-            litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine6_twtpcon_ready)) begin
+            main_litedramcore_bankmachine6_twtpcon_count <= (main_litedramcore_bankmachine6_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine6_trccon_valid) begin
-        litedramcore_bankmachine6_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine6_trccon_valid) begin
+        main_litedramcore_bankmachine6_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine6_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine6_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine6_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine6_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine6_trccon_ready)) begin
-            litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine6_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine6_trccon_ready)) begin
+            main_litedramcore_bankmachine6_trccon_count <= (main_litedramcore_bankmachine6_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine6_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine6_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine6_trascon_valid) begin
-        litedramcore_bankmachine6_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine6_trascon_valid) begin
+        main_litedramcore_bankmachine6_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine6_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine6_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine6_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine6_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine6_trascon_ready)) begin
-            litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine6_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine6_trascon_ready)) begin
+            main_litedramcore_bankmachine6_trascon_count <= (main_litedramcore_bankmachine6_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine6_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine6_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
-    if (litedramcore_bankmachine7_row_close) begin
-        litedramcore_bankmachine7_row_opened <= 1'd0;
+    builder_bankmachine6_state <= builder_bankmachine6_next_state;
+    if (main_litedramcore_bankmachine7_row_close) begin
+        main_litedramcore_bankmachine7_row_opened <= 1'd0;
     end else begin
-        if (litedramcore_bankmachine7_row_open) begin
-            litedramcore_bankmachine7_row_opened <= 1'd1;
-            litedramcore_bankmachine7_row <= litedramcore_bankmachine7_source_source_payload_addr[20:7];
+        if (main_litedramcore_bankmachine7_row_open) begin
+            main_litedramcore_bankmachine7_row_opened <= 1'd1;
+            main_litedramcore_bankmachine7_row <= main_litedramcore_bankmachine7_source_source_payload_addr[20:7];
         end
     end
-    if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin
-        litedramcore_bankmachine7_produce <= (litedramcore_bankmachine7_produce + 1'd1);
+    if (((main_litedramcore_bankmachine7_syncfifo7_we & main_litedramcore_bankmachine7_syncfifo7_writable) & (~main_litedramcore_bankmachine7_replace))) begin
+        main_litedramcore_bankmachine7_produce <= (main_litedramcore_bankmachine7_produce + 1'd1);
     end
-    if (litedramcore_bankmachine7_do_read) begin
-        litedramcore_bankmachine7_consume <= (litedramcore_bankmachine7_consume + 1'd1);
+    if (main_litedramcore_bankmachine7_do_read) begin
+        main_litedramcore_bankmachine7_consume <= (main_litedramcore_bankmachine7_consume + 1'd1);
     end
-    if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin
-        if ((~litedramcore_bankmachine7_do_read)) begin
-            litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level + 1'd1);
+    if (((main_litedramcore_bankmachine7_syncfifo7_we & main_litedramcore_bankmachine7_syncfifo7_writable) & (~main_litedramcore_bankmachine7_replace))) begin
+        if ((~main_litedramcore_bankmachine7_do_read)) begin
+            main_litedramcore_bankmachine7_level <= (main_litedramcore_bankmachine7_level + 1'd1);
         end
     end else begin
-        if (litedramcore_bankmachine7_do_read) begin
-            litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level - 1'd1);
+        if (main_litedramcore_bankmachine7_do_read) begin
+            main_litedramcore_bankmachine7_level <= (main_litedramcore_bankmachine7_level - 1'd1);
         end
     end
-    if (((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready)) begin
-        litedramcore_bankmachine7_pipe_valid_source_valid <= litedramcore_bankmachine7_pipe_valid_sink_valid;
-        litedramcore_bankmachine7_pipe_valid_source_first <= litedramcore_bankmachine7_pipe_valid_sink_first;
-        litedramcore_bankmachine7_pipe_valid_source_last <= litedramcore_bankmachine7_pipe_valid_sink_last;
-        litedramcore_bankmachine7_pipe_valid_source_payload_we <= litedramcore_bankmachine7_pipe_valid_sink_payload_we;
-        litedramcore_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
+    if (((~main_litedramcore_bankmachine7_pipe_valid_source_valid) | main_litedramcore_bankmachine7_pipe_valid_source_ready)) begin
+        main_litedramcore_bankmachine7_pipe_valid_source_valid <= main_litedramcore_bankmachine7_pipe_valid_sink_valid;
+        main_litedramcore_bankmachine7_pipe_valid_source_first <= main_litedramcore_bankmachine7_pipe_valid_sink_first;
+        main_litedramcore_bankmachine7_pipe_valid_source_last <= main_litedramcore_bankmachine7_pipe_valid_sink_last;
+        main_litedramcore_bankmachine7_pipe_valid_source_payload_we <= main_litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+        main_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
     end
-    if (litedramcore_bankmachine7_twtpcon_valid) begin
-        litedramcore_bankmachine7_twtpcon_count <= 3'd5;
+    if (main_litedramcore_bankmachine7_twtpcon_valid) begin
+        main_litedramcore_bankmachine7_twtpcon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+            main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+            main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
-            litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
-            if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
-                litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine7_twtpcon_ready)) begin
+            main_litedramcore_bankmachine7_twtpcon_count <= (main_litedramcore_bankmachine7_twtpcon_count - 1'd1);
+            if ((main_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
+                main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine7_trccon_valid) begin
-        litedramcore_bankmachine7_trccon_count <= 3'd5;
+    if (main_litedramcore_bankmachine7_trccon_valid) begin
+        main_litedramcore_bankmachine7_trccon_count <= 3'd5;
         if (1'd0) begin
-            litedramcore_bankmachine7_trccon_ready <= 1'd1;
+            main_litedramcore_bankmachine7_trccon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine7_trccon_ready <= 1'd0;
+            main_litedramcore_bankmachine7_trccon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine7_trccon_ready)) begin
-            litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
-            if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
-                litedramcore_bankmachine7_trccon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine7_trccon_ready)) begin
+            main_litedramcore_bankmachine7_trccon_count <= (main_litedramcore_bankmachine7_trccon_count - 1'd1);
+            if ((main_litedramcore_bankmachine7_trccon_count == 1'd1)) begin
+                main_litedramcore_bankmachine7_trccon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_bankmachine7_trascon_valid) begin
-        litedramcore_bankmachine7_trascon_count <= 3'd4;
+    if (main_litedramcore_bankmachine7_trascon_valid) begin
+        main_litedramcore_bankmachine7_trascon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_bankmachine7_trascon_ready <= 1'd1;
+            main_litedramcore_bankmachine7_trascon_ready <= 1'd1;
         end else begin
-            litedramcore_bankmachine7_trascon_ready <= 1'd0;
+            main_litedramcore_bankmachine7_trascon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_bankmachine7_trascon_ready)) begin
-            litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
-            if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
-                litedramcore_bankmachine7_trascon_ready <= 1'd1;
+        if ((~main_litedramcore_bankmachine7_trascon_ready)) begin
+            main_litedramcore_bankmachine7_trascon_count <= (main_litedramcore_bankmachine7_trascon_count - 1'd1);
+            if ((main_litedramcore_bankmachine7_trascon_count == 1'd1)) begin
+                main_litedramcore_bankmachine7_trascon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
-    if ((~litedramcore_en0)) begin
-        litedramcore_time0 <= 5'd31;
+    builder_bankmachine7_state <= builder_bankmachine7_next_state;
+    if ((~main_litedramcore_en0)) begin
+        main_litedramcore_time0 <= 5'd31;
     end else begin
-        if ((~litedramcore_max_time0)) begin
-            litedramcore_time0 <= (litedramcore_time0 - 1'd1);
+        if ((~main_litedramcore_max_time0)) begin
+            main_litedramcore_time0 <= (main_litedramcore_time0 - 1'd1);
         end
     end
-    if ((~litedramcore_en1)) begin
-        litedramcore_time1 <= 4'd15;
+    if ((~main_litedramcore_en1)) begin
+        main_litedramcore_time1 <= 4'd15;
     end else begin
-        if ((~litedramcore_max_time1)) begin
-            litedramcore_time1 <= (litedramcore_time1 - 1'd1);
+        if ((~main_litedramcore_max_time1)) begin
+            main_litedramcore_time1 <= (main_litedramcore_time1 - 1'd1);
         end
     end
-    if (litedramcore_choose_cmd_ce) begin
-        case (litedramcore_choose_cmd_grant)
+    if (main_litedramcore_choose_cmd_ce) begin
+        case (main_litedramcore_choose_cmd_grant)
             1'd0: begin
-                if (litedramcore_choose_cmd_request[1]) begin
-                    litedramcore_choose_cmd_grant <= 1'd1;
+                if (main_litedramcore_choose_cmd_request[1]) begin
+                    main_litedramcore_choose_cmd_grant <= 1'd1;
                 end else begin
-                    if (litedramcore_choose_cmd_request[2]) begin
-                        litedramcore_choose_cmd_grant <= 2'd2;
+                    if (main_litedramcore_choose_cmd_request[2]) begin
+                        main_litedramcore_choose_cmd_grant <= 2'd2;
                     end else begin
-                        if (litedramcore_choose_cmd_request[3]) begin
-                            litedramcore_choose_cmd_grant <= 2'd3;
+                        if (main_litedramcore_choose_cmd_request[3]) begin
+                            main_litedramcore_choose_cmd_grant <= 2'd3;
                         end else begin
-                            if (litedramcore_choose_cmd_request[4]) begin
-                                litedramcore_choose_cmd_grant <= 3'd4;
+                            if (main_litedramcore_choose_cmd_request[4]) begin
+                                main_litedramcore_choose_cmd_grant <= 3'd4;
                             end else begin
-                                if (litedramcore_choose_cmd_request[5]) begin
-                                    litedramcore_choose_cmd_grant <= 3'd5;
+                                if (main_litedramcore_choose_cmd_request[5]) begin
+                                    main_litedramcore_choose_cmd_grant <= 3'd5;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[6]) begin
-                                        litedramcore_choose_cmd_grant <= 3'd6;
+                                    if (main_litedramcore_choose_cmd_request[6]) begin
+                                        main_litedramcore_choose_cmd_grant <= 3'd6;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[7]) begin
-                                            litedramcore_choose_cmd_grant <= 3'd7;
+                                        if (main_litedramcore_choose_cmd_request[7]) begin
+                                            main_litedramcore_choose_cmd_grant <= 3'd7;
                                         end
                                     end
                                 end
@@ -13030,26 +13445,26 @@ always @(posedge sys_clk) begin
                 end
             end
             1'd1: begin
-                if (litedramcore_choose_cmd_request[2]) begin
-                    litedramcore_choose_cmd_grant <= 2'd2;
+                if (main_litedramcore_choose_cmd_request[2]) begin
+                    main_litedramcore_choose_cmd_grant <= 2'd2;
                 end else begin
-                    if (litedramcore_choose_cmd_request[3]) begin
-                        litedramcore_choose_cmd_grant <= 2'd3;
+                    if (main_litedramcore_choose_cmd_request[3]) begin
+                        main_litedramcore_choose_cmd_grant <= 2'd3;
                     end else begin
-                        if (litedramcore_choose_cmd_request[4]) begin
-                            litedramcore_choose_cmd_grant <= 3'd4;
+                        if (main_litedramcore_choose_cmd_request[4]) begin
+                            main_litedramcore_choose_cmd_grant <= 3'd4;
                         end else begin
-                            if (litedramcore_choose_cmd_request[5]) begin
-                                litedramcore_choose_cmd_grant <= 3'd5;
+                            if (main_litedramcore_choose_cmd_request[5]) begin
+                                main_litedramcore_choose_cmd_grant <= 3'd5;
                             end else begin
-                                if (litedramcore_choose_cmd_request[6]) begin
-                                    litedramcore_choose_cmd_grant <= 3'd6;
+                                if (main_litedramcore_choose_cmd_request[6]) begin
+                                    main_litedramcore_choose_cmd_grant <= 3'd6;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[7]) begin
-                                        litedramcore_choose_cmd_grant <= 3'd7;
+                                    if (main_litedramcore_choose_cmd_request[7]) begin
+                                        main_litedramcore_choose_cmd_grant <= 3'd7;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[0]) begin
-                                            litedramcore_choose_cmd_grant <= 1'd0;
+                                        if (main_litedramcore_choose_cmd_request[0]) begin
+                                            main_litedramcore_choose_cmd_grant <= 1'd0;
                                         end
                                     end
                                 end
@@ -13059,26 +13474,26 @@ always @(posedge sys_clk) begin
                 end
             end
             2'd2: begin
-                if (litedramcore_choose_cmd_request[3]) begin
-                    litedramcore_choose_cmd_grant <= 2'd3;
+                if (main_litedramcore_choose_cmd_request[3]) begin
+                    main_litedramcore_choose_cmd_grant <= 2'd3;
                 end else begin
-                    if (litedramcore_choose_cmd_request[4]) begin
-                        litedramcore_choose_cmd_grant <= 3'd4;
+                    if (main_litedramcore_choose_cmd_request[4]) begin
+                        main_litedramcore_choose_cmd_grant <= 3'd4;
                     end else begin
-                        if (litedramcore_choose_cmd_request[5]) begin
-                            litedramcore_choose_cmd_grant <= 3'd5;
+                        if (main_litedramcore_choose_cmd_request[5]) begin
+                            main_litedramcore_choose_cmd_grant <= 3'd5;
                         end else begin
-                            if (litedramcore_choose_cmd_request[6]) begin
-                                litedramcore_choose_cmd_grant <= 3'd6;
+                            if (main_litedramcore_choose_cmd_request[6]) begin
+                                main_litedramcore_choose_cmd_grant <= 3'd6;
                             end else begin
-                                if (litedramcore_choose_cmd_request[7]) begin
-                                    litedramcore_choose_cmd_grant <= 3'd7;
+                                if (main_litedramcore_choose_cmd_request[7]) begin
+                                    main_litedramcore_choose_cmd_grant <= 3'd7;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[0]) begin
-                                        litedramcore_choose_cmd_grant <= 1'd0;
+                                    if (main_litedramcore_choose_cmd_request[0]) begin
+                                        main_litedramcore_choose_cmd_grant <= 1'd0;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[1]) begin
-                                            litedramcore_choose_cmd_grant <= 1'd1;
+                                        if (main_litedramcore_choose_cmd_request[1]) begin
+                                            main_litedramcore_choose_cmd_grant <= 1'd1;
                                         end
                                     end
                                 end
@@ -13088,26 +13503,26 @@ always @(posedge sys_clk) begin
                 end
             end
             2'd3: begin
-                if (litedramcore_choose_cmd_request[4]) begin
-                    litedramcore_choose_cmd_grant <= 3'd4;
+                if (main_litedramcore_choose_cmd_request[4]) begin
+                    main_litedramcore_choose_cmd_grant <= 3'd4;
                 end else begin
-                    if (litedramcore_choose_cmd_request[5]) begin
-                        litedramcore_choose_cmd_grant <= 3'd5;
+                    if (main_litedramcore_choose_cmd_request[5]) begin
+                        main_litedramcore_choose_cmd_grant <= 3'd5;
                     end else begin
-                        if (litedramcore_choose_cmd_request[6]) begin
-                            litedramcore_choose_cmd_grant <= 3'd6;
+                        if (main_litedramcore_choose_cmd_request[6]) begin
+                            main_litedramcore_choose_cmd_grant <= 3'd6;
                         end else begin
-                            if (litedramcore_choose_cmd_request[7]) begin
-                                litedramcore_choose_cmd_grant <= 3'd7;
+                            if (main_litedramcore_choose_cmd_request[7]) begin
+                                main_litedramcore_choose_cmd_grant <= 3'd7;
                             end else begin
-                                if (litedramcore_choose_cmd_request[0]) begin
-                                    litedramcore_choose_cmd_grant <= 1'd0;
+                                if (main_litedramcore_choose_cmd_request[0]) begin
+                                    main_litedramcore_choose_cmd_grant <= 1'd0;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[1]) begin
-                                        litedramcore_choose_cmd_grant <= 1'd1;
+                                    if (main_litedramcore_choose_cmd_request[1]) begin
+                                        main_litedramcore_choose_cmd_grant <= 1'd1;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[2]) begin
-                                            litedramcore_choose_cmd_grant <= 2'd2;
+                                        if (main_litedramcore_choose_cmd_request[2]) begin
+                                            main_litedramcore_choose_cmd_grant <= 2'd2;
                                         end
                                     end
                                 end
@@ -13117,26 +13532,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd4: begin
-                if (litedramcore_choose_cmd_request[5]) begin
-                    litedramcore_choose_cmd_grant <= 3'd5;
+                if (main_litedramcore_choose_cmd_request[5]) begin
+                    main_litedramcore_choose_cmd_grant <= 3'd5;
                 end else begin
-                    if (litedramcore_choose_cmd_request[6]) begin
-                        litedramcore_choose_cmd_grant <= 3'd6;
+                    if (main_litedramcore_choose_cmd_request[6]) begin
+                        main_litedramcore_choose_cmd_grant <= 3'd6;
                     end else begin
-                        if (litedramcore_choose_cmd_request[7]) begin
-                            litedramcore_choose_cmd_grant <= 3'd7;
+                        if (main_litedramcore_choose_cmd_request[7]) begin
+                            main_litedramcore_choose_cmd_grant <= 3'd7;
                         end else begin
-                            if (litedramcore_choose_cmd_request[0]) begin
-                                litedramcore_choose_cmd_grant <= 1'd0;
+                            if (main_litedramcore_choose_cmd_request[0]) begin
+                                main_litedramcore_choose_cmd_grant <= 1'd0;
                             end else begin
-                                if (litedramcore_choose_cmd_request[1]) begin
-                                    litedramcore_choose_cmd_grant <= 1'd1;
+                                if (main_litedramcore_choose_cmd_request[1]) begin
+                                    main_litedramcore_choose_cmd_grant <= 1'd1;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[2]) begin
-                                        litedramcore_choose_cmd_grant <= 2'd2;
+                                    if (main_litedramcore_choose_cmd_request[2]) begin
+                                        main_litedramcore_choose_cmd_grant <= 2'd2;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[3]) begin
-                                            litedramcore_choose_cmd_grant <= 2'd3;
+                                        if (main_litedramcore_choose_cmd_request[3]) begin
+                                            main_litedramcore_choose_cmd_grant <= 2'd3;
                                         end
                                     end
                                 end
@@ -13146,26 +13561,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd5: begin
-                if (litedramcore_choose_cmd_request[6]) begin
-                    litedramcore_choose_cmd_grant <= 3'd6;
+                if (main_litedramcore_choose_cmd_request[6]) begin
+                    main_litedramcore_choose_cmd_grant <= 3'd6;
                 end else begin
-                    if (litedramcore_choose_cmd_request[7]) begin
-                        litedramcore_choose_cmd_grant <= 3'd7;
+                    if (main_litedramcore_choose_cmd_request[7]) begin
+                        main_litedramcore_choose_cmd_grant <= 3'd7;
                     end else begin
-                        if (litedramcore_choose_cmd_request[0]) begin
-                            litedramcore_choose_cmd_grant <= 1'd0;
+                        if (main_litedramcore_choose_cmd_request[0]) begin
+                            main_litedramcore_choose_cmd_grant <= 1'd0;
                         end else begin
-                            if (litedramcore_choose_cmd_request[1]) begin
-                                litedramcore_choose_cmd_grant <= 1'd1;
+                            if (main_litedramcore_choose_cmd_request[1]) begin
+                                main_litedramcore_choose_cmd_grant <= 1'd1;
                             end else begin
-                                if (litedramcore_choose_cmd_request[2]) begin
-                                    litedramcore_choose_cmd_grant <= 2'd2;
+                                if (main_litedramcore_choose_cmd_request[2]) begin
+                                    main_litedramcore_choose_cmd_grant <= 2'd2;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[3]) begin
-                                        litedramcore_choose_cmd_grant <= 2'd3;
+                                    if (main_litedramcore_choose_cmd_request[3]) begin
+                                        main_litedramcore_choose_cmd_grant <= 2'd3;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[4]) begin
-                                            litedramcore_choose_cmd_grant <= 3'd4;
+                                        if (main_litedramcore_choose_cmd_request[4]) begin
+                                            main_litedramcore_choose_cmd_grant <= 3'd4;
                                         end
                                     end
                                 end
@@ -13175,26 +13590,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd6: begin
-                if (litedramcore_choose_cmd_request[7]) begin
-                    litedramcore_choose_cmd_grant <= 3'd7;
+                if (main_litedramcore_choose_cmd_request[7]) begin
+                    main_litedramcore_choose_cmd_grant <= 3'd7;
                 end else begin
-                    if (litedramcore_choose_cmd_request[0]) begin
-                        litedramcore_choose_cmd_grant <= 1'd0;
+                    if (main_litedramcore_choose_cmd_request[0]) begin
+                        main_litedramcore_choose_cmd_grant <= 1'd0;
                     end else begin
-                        if (litedramcore_choose_cmd_request[1]) begin
-                            litedramcore_choose_cmd_grant <= 1'd1;
+                        if (main_litedramcore_choose_cmd_request[1]) begin
+                            main_litedramcore_choose_cmd_grant <= 1'd1;
                         end else begin
-                            if (litedramcore_choose_cmd_request[2]) begin
-                                litedramcore_choose_cmd_grant <= 2'd2;
+                            if (main_litedramcore_choose_cmd_request[2]) begin
+                                main_litedramcore_choose_cmd_grant <= 2'd2;
                             end else begin
-                                if (litedramcore_choose_cmd_request[3]) begin
-                                    litedramcore_choose_cmd_grant <= 2'd3;
+                                if (main_litedramcore_choose_cmd_request[3]) begin
+                                    main_litedramcore_choose_cmd_grant <= 2'd3;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[4]) begin
-                                        litedramcore_choose_cmd_grant <= 3'd4;
+                                    if (main_litedramcore_choose_cmd_request[4]) begin
+                                        main_litedramcore_choose_cmd_grant <= 3'd4;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[5]) begin
-                                            litedramcore_choose_cmd_grant <= 3'd5;
+                                        if (main_litedramcore_choose_cmd_request[5]) begin
+                                            main_litedramcore_choose_cmd_grant <= 3'd5;
                                         end
                                     end
                                 end
@@ -13204,26 +13619,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd7: begin
-                if (litedramcore_choose_cmd_request[0]) begin
-                    litedramcore_choose_cmd_grant <= 1'd0;
+                if (main_litedramcore_choose_cmd_request[0]) begin
+                    main_litedramcore_choose_cmd_grant <= 1'd0;
                 end else begin
-                    if (litedramcore_choose_cmd_request[1]) begin
-                        litedramcore_choose_cmd_grant <= 1'd1;
+                    if (main_litedramcore_choose_cmd_request[1]) begin
+                        main_litedramcore_choose_cmd_grant <= 1'd1;
                     end else begin
-                        if (litedramcore_choose_cmd_request[2]) begin
-                            litedramcore_choose_cmd_grant <= 2'd2;
+                        if (main_litedramcore_choose_cmd_request[2]) begin
+                            main_litedramcore_choose_cmd_grant <= 2'd2;
                         end else begin
-                            if (litedramcore_choose_cmd_request[3]) begin
-                                litedramcore_choose_cmd_grant <= 2'd3;
+                            if (main_litedramcore_choose_cmd_request[3]) begin
+                                main_litedramcore_choose_cmd_grant <= 2'd3;
                             end else begin
-                                if (litedramcore_choose_cmd_request[4]) begin
-                                    litedramcore_choose_cmd_grant <= 3'd4;
+                                if (main_litedramcore_choose_cmd_request[4]) begin
+                                    main_litedramcore_choose_cmd_grant <= 3'd4;
                                 end else begin
-                                    if (litedramcore_choose_cmd_request[5]) begin
-                                        litedramcore_choose_cmd_grant <= 3'd5;
+                                    if (main_litedramcore_choose_cmd_request[5]) begin
+                                        main_litedramcore_choose_cmd_grant <= 3'd5;
                                     end else begin
-                                        if (litedramcore_choose_cmd_request[6]) begin
-                                            litedramcore_choose_cmd_grant <= 3'd6;
+                                        if (main_litedramcore_choose_cmd_request[6]) begin
+                                            main_litedramcore_choose_cmd_grant <= 3'd6;
                                         end
                                     end
                                 end
@@ -13234,29 +13649,29 @@ always @(posedge sys_clk) begin
             end
         endcase
     end
-    if (litedramcore_choose_req_ce) begin
-        case (litedramcore_choose_req_grant)
+    if (main_litedramcore_choose_req_ce) begin
+        case (main_litedramcore_choose_req_grant)
             1'd0: begin
-                if (litedramcore_choose_req_request[1]) begin
-                    litedramcore_choose_req_grant <= 1'd1;
+                if (main_litedramcore_choose_req_request[1]) begin
+                    main_litedramcore_choose_req_grant <= 1'd1;
                 end else begin
-                    if (litedramcore_choose_req_request[2]) begin
-                        litedramcore_choose_req_grant <= 2'd2;
+                    if (main_litedramcore_choose_req_request[2]) begin
+                        main_litedramcore_choose_req_grant <= 2'd2;
                     end else begin
-                        if (litedramcore_choose_req_request[3]) begin
-                            litedramcore_choose_req_grant <= 2'd3;
+                        if (main_litedramcore_choose_req_request[3]) begin
+                            main_litedramcore_choose_req_grant <= 2'd3;
                         end else begin
-                            if (litedramcore_choose_req_request[4]) begin
-                                litedramcore_choose_req_grant <= 3'd4;
+                            if (main_litedramcore_choose_req_request[4]) begin
+                                main_litedramcore_choose_req_grant <= 3'd4;
                             end else begin
-                                if (litedramcore_choose_req_request[5]) begin
-                                    litedramcore_choose_req_grant <= 3'd5;
+                                if (main_litedramcore_choose_req_request[5]) begin
+                                    main_litedramcore_choose_req_grant <= 3'd5;
                                 end else begin
-                                    if (litedramcore_choose_req_request[6]) begin
-                                        litedramcore_choose_req_grant <= 3'd6;
+                                    if (main_litedramcore_choose_req_request[6]) begin
+                                        main_litedramcore_choose_req_grant <= 3'd6;
                                     end else begin
-                                        if (litedramcore_choose_req_request[7]) begin
-                                            litedramcore_choose_req_grant <= 3'd7;
+                                        if (main_litedramcore_choose_req_request[7]) begin
+                                            main_litedramcore_choose_req_grant <= 3'd7;
                                         end
                                     end
                                 end
@@ -13266,26 +13681,26 @@ always @(posedge sys_clk) begin
                 end
             end
             1'd1: begin
-                if (litedramcore_choose_req_request[2]) begin
-                    litedramcore_choose_req_grant <= 2'd2;
+                if (main_litedramcore_choose_req_request[2]) begin
+                    main_litedramcore_choose_req_grant <= 2'd2;
                 end else begin
-                    if (litedramcore_choose_req_request[3]) begin
-                        litedramcore_choose_req_grant <= 2'd3;
+                    if (main_litedramcore_choose_req_request[3]) begin
+                        main_litedramcore_choose_req_grant <= 2'd3;
                     end else begin
-                        if (litedramcore_choose_req_request[4]) begin
-                            litedramcore_choose_req_grant <= 3'd4;
+                        if (main_litedramcore_choose_req_request[4]) begin
+                            main_litedramcore_choose_req_grant <= 3'd4;
                         end else begin
-                            if (litedramcore_choose_req_request[5]) begin
-                                litedramcore_choose_req_grant <= 3'd5;
+                            if (main_litedramcore_choose_req_request[5]) begin
+                                main_litedramcore_choose_req_grant <= 3'd5;
                             end else begin
-                                if (litedramcore_choose_req_request[6]) begin
-                                    litedramcore_choose_req_grant <= 3'd6;
+                                if (main_litedramcore_choose_req_request[6]) begin
+                                    main_litedramcore_choose_req_grant <= 3'd6;
                                 end else begin
-                                    if (litedramcore_choose_req_request[7]) begin
-                                        litedramcore_choose_req_grant <= 3'd7;
+                                    if (main_litedramcore_choose_req_request[7]) begin
+                                        main_litedramcore_choose_req_grant <= 3'd7;
                                     end else begin
-                                        if (litedramcore_choose_req_request[0]) begin
-                                            litedramcore_choose_req_grant <= 1'd0;
+                                        if (main_litedramcore_choose_req_request[0]) begin
+                                            main_litedramcore_choose_req_grant <= 1'd0;
                                         end
                                     end
                                 end
@@ -13295,26 +13710,26 @@ always @(posedge sys_clk) begin
                 end
             end
             2'd2: begin
-                if (litedramcore_choose_req_request[3]) begin
-                    litedramcore_choose_req_grant <= 2'd3;
+                if (main_litedramcore_choose_req_request[3]) begin
+                    main_litedramcore_choose_req_grant <= 2'd3;
                 end else begin
-                    if (litedramcore_choose_req_request[4]) begin
-                        litedramcore_choose_req_grant <= 3'd4;
+                    if (main_litedramcore_choose_req_request[4]) begin
+                        main_litedramcore_choose_req_grant <= 3'd4;
                     end else begin
-                        if (litedramcore_choose_req_request[5]) begin
-                            litedramcore_choose_req_grant <= 3'd5;
+                        if (main_litedramcore_choose_req_request[5]) begin
+                            main_litedramcore_choose_req_grant <= 3'd5;
                         end else begin
-                            if (litedramcore_choose_req_request[6]) begin
-                                litedramcore_choose_req_grant <= 3'd6;
+                            if (main_litedramcore_choose_req_request[6]) begin
+                                main_litedramcore_choose_req_grant <= 3'd6;
                             end else begin
-                                if (litedramcore_choose_req_request[7]) begin
-                                    litedramcore_choose_req_grant <= 3'd7;
+                                if (main_litedramcore_choose_req_request[7]) begin
+                                    main_litedramcore_choose_req_grant <= 3'd7;
                                 end else begin
-                                    if (litedramcore_choose_req_request[0]) begin
-                                        litedramcore_choose_req_grant <= 1'd0;
+                                    if (main_litedramcore_choose_req_request[0]) begin
+                                        main_litedramcore_choose_req_grant <= 1'd0;
                                     end else begin
-                                        if (litedramcore_choose_req_request[1]) begin
-                                            litedramcore_choose_req_grant <= 1'd1;
+                                        if (main_litedramcore_choose_req_request[1]) begin
+                                            main_litedramcore_choose_req_grant <= 1'd1;
                                         end
                                     end
                                 end
@@ -13324,26 +13739,26 @@ always @(posedge sys_clk) begin
                 end
             end
             2'd3: begin
-                if (litedramcore_choose_req_request[4]) begin
-                    litedramcore_choose_req_grant <= 3'd4;
+                if (main_litedramcore_choose_req_request[4]) begin
+                    main_litedramcore_choose_req_grant <= 3'd4;
                 end else begin
-                    if (litedramcore_choose_req_request[5]) begin
-                        litedramcore_choose_req_grant <= 3'd5;
+                    if (main_litedramcore_choose_req_request[5]) begin
+                        main_litedramcore_choose_req_grant <= 3'd5;
                     end else begin
-                        if (litedramcore_choose_req_request[6]) begin
-                            litedramcore_choose_req_grant <= 3'd6;
+                        if (main_litedramcore_choose_req_request[6]) begin
+                            main_litedramcore_choose_req_grant <= 3'd6;
                         end else begin
-                            if (litedramcore_choose_req_request[7]) begin
-                                litedramcore_choose_req_grant <= 3'd7;
+                            if (main_litedramcore_choose_req_request[7]) begin
+                                main_litedramcore_choose_req_grant <= 3'd7;
                             end else begin
-                                if (litedramcore_choose_req_request[0]) begin
-                                    litedramcore_choose_req_grant <= 1'd0;
+                                if (main_litedramcore_choose_req_request[0]) begin
+                                    main_litedramcore_choose_req_grant <= 1'd0;
                                 end else begin
-                                    if (litedramcore_choose_req_request[1]) begin
-                                        litedramcore_choose_req_grant <= 1'd1;
+                                    if (main_litedramcore_choose_req_request[1]) begin
+                                        main_litedramcore_choose_req_grant <= 1'd1;
                                     end else begin
-                                        if (litedramcore_choose_req_request[2]) begin
-                                            litedramcore_choose_req_grant <= 2'd2;
+                                        if (main_litedramcore_choose_req_request[2]) begin
+                                            main_litedramcore_choose_req_grant <= 2'd2;
                                         end
                                     end
                                 end
@@ -13353,26 +13768,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd4: begin
-                if (litedramcore_choose_req_request[5]) begin
-                    litedramcore_choose_req_grant <= 3'd5;
+                if (main_litedramcore_choose_req_request[5]) begin
+                    main_litedramcore_choose_req_grant <= 3'd5;
                 end else begin
-                    if (litedramcore_choose_req_request[6]) begin
-                        litedramcore_choose_req_grant <= 3'd6;
+                    if (main_litedramcore_choose_req_request[6]) begin
+                        main_litedramcore_choose_req_grant <= 3'd6;
                     end else begin
-                        if (litedramcore_choose_req_request[7]) begin
-                            litedramcore_choose_req_grant <= 3'd7;
+                        if (main_litedramcore_choose_req_request[7]) begin
+                            main_litedramcore_choose_req_grant <= 3'd7;
                         end else begin
-                            if (litedramcore_choose_req_request[0]) begin
-                                litedramcore_choose_req_grant <= 1'd0;
+                            if (main_litedramcore_choose_req_request[0]) begin
+                                main_litedramcore_choose_req_grant <= 1'd0;
                             end else begin
-                                if (litedramcore_choose_req_request[1]) begin
-                                    litedramcore_choose_req_grant <= 1'd1;
+                                if (main_litedramcore_choose_req_request[1]) begin
+                                    main_litedramcore_choose_req_grant <= 1'd1;
                                 end else begin
-                                    if (litedramcore_choose_req_request[2]) begin
-                                        litedramcore_choose_req_grant <= 2'd2;
+                                    if (main_litedramcore_choose_req_request[2]) begin
+                                        main_litedramcore_choose_req_grant <= 2'd2;
                                     end else begin
-                                        if (litedramcore_choose_req_request[3]) begin
-                                            litedramcore_choose_req_grant <= 2'd3;
+                                        if (main_litedramcore_choose_req_request[3]) begin
+                                            main_litedramcore_choose_req_grant <= 2'd3;
                                         end
                                     end
                                 end
@@ -13382,26 +13797,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd5: begin
-                if (litedramcore_choose_req_request[6]) begin
-                    litedramcore_choose_req_grant <= 3'd6;
+                if (main_litedramcore_choose_req_request[6]) begin
+                    main_litedramcore_choose_req_grant <= 3'd6;
                 end else begin
-                    if (litedramcore_choose_req_request[7]) begin
-                        litedramcore_choose_req_grant <= 3'd7;
+                    if (main_litedramcore_choose_req_request[7]) begin
+                        main_litedramcore_choose_req_grant <= 3'd7;
                     end else begin
-                        if (litedramcore_choose_req_request[0]) begin
-                            litedramcore_choose_req_grant <= 1'd0;
+                        if (main_litedramcore_choose_req_request[0]) begin
+                            main_litedramcore_choose_req_grant <= 1'd0;
                         end else begin
-                            if (litedramcore_choose_req_request[1]) begin
-                                litedramcore_choose_req_grant <= 1'd1;
+                            if (main_litedramcore_choose_req_request[1]) begin
+                                main_litedramcore_choose_req_grant <= 1'd1;
                             end else begin
-                                if (litedramcore_choose_req_request[2]) begin
-                                    litedramcore_choose_req_grant <= 2'd2;
+                                if (main_litedramcore_choose_req_request[2]) begin
+                                    main_litedramcore_choose_req_grant <= 2'd2;
                                 end else begin
-                                    if (litedramcore_choose_req_request[3]) begin
-                                        litedramcore_choose_req_grant <= 2'd3;
+                                    if (main_litedramcore_choose_req_request[3]) begin
+                                        main_litedramcore_choose_req_grant <= 2'd3;
                                     end else begin
-                                        if (litedramcore_choose_req_request[4]) begin
-                                            litedramcore_choose_req_grant <= 3'd4;
+                                        if (main_litedramcore_choose_req_request[4]) begin
+                                            main_litedramcore_choose_req_grant <= 3'd4;
                                         end
                                     end
                                 end
@@ -13411,26 +13826,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd6: begin
-                if (litedramcore_choose_req_request[7]) begin
-                    litedramcore_choose_req_grant <= 3'd7;
+                if (main_litedramcore_choose_req_request[7]) begin
+                    main_litedramcore_choose_req_grant <= 3'd7;
                 end else begin
-                    if (litedramcore_choose_req_request[0]) begin
-                        litedramcore_choose_req_grant <= 1'd0;
+                    if (main_litedramcore_choose_req_request[0]) begin
+                        main_litedramcore_choose_req_grant <= 1'd0;
                     end else begin
-                        if (litedramcore_choose_req_request[1]) begin
-                            litedramcore_choose_req_grant <= 1'd1;
+                        if (main_litedramcore_choose_req_request[1]) begin
+                            main_litedramcore_choose_req_grant <= 1'd1;
                         end else begin
-                            if (litedramcore_choose_req_request[2]) begin
-                                litedramcore_choose_req_grant <= 2'd2;
+                            if (main_litedramcore_choose_req_request[2]) begin
+                                main_litedramcore_choose_req_grant <= 2'd2;
                             end else begin
-                                if (litedramcore_choose_req_request[3]) begin
-                                    litedramcore_choose_req_grant <= 2'd3;
+                                if (main_litedramcore_choose_req_request[3]) begin
+                                    main_litedramcore_choose_req_grant <= 2'd3;
                                 end else begin
-                                    if (litedramcore_choose_req_request[4]) begin
-                                        litedramcore_choose_req_grant <= 3'd4;
+                                    if (main_litedramcore_choose_req_request[4]) begin
+                                        main_litedramcore_choose_req_grant <= 3'd4;
                                     end else begin
-                                        if (litedramcore_choose_req_request[5]) begin
-                                            litedramcore_choose_req_grant <= 3'd5;
+                                        if (main_litedramcore_choose_req_request[5]) begin
+                                            main_litedramcore_choose_req_grant <= 3'd5;
                                         end
                                     end
                                 end
@@ -13440,26 +13855,26 @@ always @(posedge sys_clk) begin
                 end
             end
             3'd7: begin
-                if (litedramcore_choose_req_request[0]) begin
-                    litedramcore_choose_req_grant <= 1'd0;
+                if (main_litedramcore_choose_req_request[0]) begin
+                    main_litedramcore_choose_req_grant <= 1'd0;
                 end else begin
-                    if (litedramcore_choose_req_request[1]) begin
-                        litedramcore_choose_req_grant <= 1'd1;
+                    if (main_litedramcore_choose_req_request[1]) begin
+                        main_litedramcore_choose_req_grant <= 1'd1;
                     end else begin
-                        if (litedramcore_choose_req_request[2]) begin
-                            litedramcore_choose_req_grant <= 2'd2;
+                        if (main_litedramcore_choose_req_request[2]) begin
+                            main_litedramcore_choose_req_grant <= 2'd2;
                         end else begin
-                            if (litedramcore_choose_req_request[3]) begin
-                                litedramcore_choose_req_grant <= 2'd3;
+                            if (main_litedramcore_choose_req_request[3]) begin
+                                main_litedramcore_choose_req_grant <= 2'd3;
                             end else begin
-                                if (litedramcore_choose_req_request[4]) begin
-                                    litedramcore_choose_req_grant <= 3'd4;
+                                if (main_litedramcore_choose_req_request[4]) begin
+                                    main_litedramcore_choose_req_grant <= 3'd4;
                                 end else begin
-                                    if (litedramcore_choose_req_request[5]) begin
-                                        litedramcore_choose_req_grant <= 3'd5;
+                                    if (main_litedramcore_choose_req_request[5]) begin
+                                        main_litedramcore_choose_req_grant <= 3'd5;
                                     end else begin
-                                        if (litedramcore_choose_req_request[6]) begin
-                                            litedramcore_choose_req_grant <= 3'd6;
+                                        if (main_litedramcore_choose_req_request[6]) begin
+                                            main_litedramcore_choose_req_grant <= 3'd6;
                                         end
                                     end
                                 end
@@ -13470,644 +13885,644 @@ always @(posedge sys_clk) begin
             end
         endcase
     end
-    litedramcore_dfi_p0_cs_n <= 1'd0;
-    litedramcore_dfi_p0_bank <= array_muxed0;
-    litedramcore_dfi_p0_address <= array_muxed1;
-    litedramcore_dfi_p0_cas_n <= (~array_muxed2);
-    litedramcore_dfi_p0_ras_n <= (~array_muxed3);
-    litedramcore_dfi_p0_we_n <= (~array_muxed4);
-    litedramcore_dfi_p0_rddata_en <= array_muxed5;
-    litedramcore_dfi_p0_wrdata_en <= array_muxed6;
-    litedramcore_dfi_p1_cs_n <= 1'd0;
-    litedramcore_dfi_p1_bank <= array_muxed7;
-    litedramcore_dfi_p1_address <= array_muxed8;
-    litedramcore_dfi_p1_cas_n <= (~array_muxed9);
-    litedramcore_dfi_p1_ras_n <= (~array_muxed10);
-    litedramcore_dfi_p1_we_n <= (~array_muxed11);
-    litedramcore_dfi_p1_rddata_en <= array_muxed12;
-    litedramcore_dfi_p1_wrdata_en <= array_muxed13;
-    litedramcore_dfi_p2_cs_n <= 1'd0;
-    litedramcore_dfi_p2_bank <= array_muxed14;
-    litedramcore_dfi_p2_address <= array_muxed15;
-    litedramcore_dfi_p2_cas_n <= (~array_muxed16);
-    litedramcore_dfi_p2_ras_n <= (~array_muxed17);
-    litedramcore_dfi_p2_we_n <= (~array_muxed18);
-    litedramcore_dfi_p2_rddata_en <= array_muxed19;
-    litedramcore_dfi_p2_wrdata_en <= array_muxed20;
-    litedramcore_dfi_p3_cs_n <= 1'd0;
-    litedramcore_dfi_p3_bank <= array_muxed21;
-    litedramcore_dfi_p3_address <= array_muxed22;
-    litedramcore_dfi_p3_cas_n <= (~array_muxed23);
-    litedramcore_dfi_p3_ras_n <= (~array_muxed24);
-    litedramcore_dfi_p3_we_n <= (~array_muxed25);
-    litedramcore_dfi_p3_rddata_en <= array_muxed26;
-    litedramcore_dfi_p3_wrdata_en <= array_muxed27;
-    if (litedramcore_trrdcon_valid) begin
-        litedramcore_trrdcon_count <= 1'd1;
+    main_litedramcore_dfi_p0_cs_n <= 1'd0;
+    main_litedramcore_dfi_p0_bank <= builder_self0;
+    main_litedramcore_dfi_p0_address <= builder_self1;
+    main_litedramcore_dfi_p0_cas_n <= (~builder_self2);
+    main_litedramcore_dfi_p0_ras_n <= (~builder_self3);
+    main_litedramcore_dfi_p0_we_n <= (~builder_self4);
+    main_litedramcore_dfi_p0_rddata_en <= builder_self5;
+    main_litedramcore_dfi_p0_wrdata_en <= builder_self6;
+    main_litedramcore_dfi_p1_cs_n <= 1'd0;
+    main_litedramcore_dfi_p1_bank <= builder_self7;
+    main_litedramcore_dfi_p1_address <= builder_self8;
+    main_litedramcore_dfi_p1_cas_n <= (~builder_self9);
+    main_litedramcore_dfi_p1_ras_n <= (~builder_self10);
+    main_litedramcore_dfi_p1_we_n <= (~builder_self11);
+    main_litedramcore_dfi_p1_rddata_en <= builder_self12;
+    main_litedramcore_dfi_p1_wrdata_en <= builder_self13;
+    main_litedramcore_dfi_p2_cs_n <= 1'd0;
+    main_litedramcore_dfi_p2_bank <= builder_self14;
+    main_litedramcore_dfi_p2_address <= builder_self15;
+    main_litedramcore_dfi_p2_cas_n <= (~builder_self16);
+    main_litedramcore_dfi_p2_ras_n <= (~builder_self17);
+    main_litedramcore_dfi_p2_we_n <= (~builder_self18);
+    main_litedramcore_dfi_p2_rddata_en <= builder_self19;
+    main_litedramcore_dfi_p2_wrdata_en <= builder_self20;
+    main_litedramcore_dfi_p3_cs_n <= 1'd0;
+    main_litedramcore_dfi_p3_bank <= builder_self21;
+    main_litedramcore_dfi_p3_address <= builder_self22;
+    main_litedramcore_dfi_p3_cas_n <= (~builder_self23);
+    main_litedramcore_dfi_p3_ras_n <= (~builder_self24);
+    main_litedramcore_dfi_p3_we_n <= (~builder_self25);
+    main_litedramcore_dfi_p3_rddata_en <= builder_self26;
+    main_litedramcore_dfi_p3_wrdata_en <= builder_self27;
+    if (main_litedramcore_trrdcon_valid) begin
+        main_litedramcore_trrdcon_count <= 1'd1;
         if (1'd0) begin
-            litedramcore_trrdcon_ready <= 1'd1;
+            main_litedramcore_trrdcon_ready <= 1'd1;
         end else begin
-            litedramcore_trrdcon_ready <= 1'd0;
+            main_litedramcore_trrdcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_trrdcon_ready)) begin
-            litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
-            if ((litedramcore_trrdcon_count == 1'd1)) begin
-                litedramcore_trrdcon_ready <= 1'd1;
+        if ((~main_litedramcore_trrdcon_ready)) begin
+            main_litedramcore_trrdcon_count <= (main_litedramcore_trrdcon_count - 1'd1);
+            if ((main_litedramcore_trrdcon_count == 1'd1)) begin
+                main_litedramcore_trrdcon_ready <= 1'd1;
             end
         end
     end
-    litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
-    if ((litedramcore_tfawcon_count < 3'd4)) begin
-        if ((litedramcore_tfawcon_count == 2'd3)) begin
-            litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
+    main_litedramcore_tfawcon_window <= {main_litedramcore_tfawcon_window, main_litedramcore_tfawcon_valid};
+    if ((main_litedramcore_tfawcon_count < 3'd4)) begin
+        if ((main_litedramcore_tfawcon_count == 2'd3)) begin
+            main_litedramcore_tfawcon_ready <= (~main_litedramcore_tfawcon_valid);
         end else begin
-            litedramcore_tfawcon_ready <= 1'd1;
+            main_litedramcore_tfawcon_ready <= 1'd1;
         end
     end
-    if (litedramcore_tccdcon_valid) begin
-        litedramcore_tccdcon_count <= 1'd0;
+    if (main_litedramcore_tccdcon_valid) begin
+        main_litedramcore_tccdcon_count <= 1'd0;
         if (1'd1) begin
-            litedramcore_tccdcon_ready <= 1'd1;
+            main_litedramcore_tccdcon_ready <= 1'd1;
         end else begin
-            litedramcore_tccdcon_ready <= 1'd0;
+            main_litedramcore_tccdcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_tccdcon_ready)) begin
-            litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
-            if ((litedramcore_tccdcon_count == 1'd1)) begin
-                litedramcore_tccdcon_ready <= 1'd1;
+        if ((~main_litedramcore_tccdcon_ready)) begin
+            main_litedramcore_tccdcon_count <= (main_litedramcore_tccdcon_count - 1'd1);
+            if ((main_litedramcore_tccdcon_count == 1'd1)) begin
+                main_litedramcore_tccdcon_ready <= 1'd1;
             end
         end
     end
-    if (litedramcore_twtrcon_valid) begin
-        litedramcore_twtrcon_count <= 3'd4;
+    if (main_litedramcore_twtrcon_valid) begin
+        main_litedramcore_twtrcon_count <= 3'd4;
         if (1'd0) begin
-            litedramcore_twtrcon_ready <= 1'd1;
+            main_litedramcore_twtrcon_ready <= 1'd1;
         end else begin
-            litedramcore_twtrcon_ready <= 1'd0;
+            main_litedramcore_twtrcon_ready <= 1'd0;
         end
     end else begin
-        if ((~litedramcore_twtrcon_ready)) begin
-            litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
-            if ((litedramcore_twtrcon_count == 1'd1)) begin
-                litedramcore_twtrcon_ready <= 1'd1;
-            end
-        end
-    end
-    litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
-    litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
-    litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
-    litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
-    litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
-    litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
-    litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
-    litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
-    litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
-    litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
-    litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
-    litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
-    litedramcore_state <= litedramcore_next_state;
-    if (litedramcore_dat_w_next_value_ce0) begin
-        litedramcore_dat_w <= litedramcore_dat_w_next_value0;
-    end
-    if (litedramcore_adr_next_value_ce1) begin
-        litedramcore_adr <= litedramcore_adr_next_value1;
-    end
-    if (litedramcore_we_next_value_ce2) begin
-        litedramcore_we <= litedramcore_we_next_value2;
-    end
-    interface0_bank_bus_dat_r <= 1'd0;
-    if (csrbank0_sel) begin
-        case (interface0_bank_bus_adr[8:0])
+        if ((~main_litedramcore_twtrcon_ready)) begin
+            main_litedramcore_twtrcon_count <= (main_litedramcore_twtrcon_count - 1'd1);
+            if ((main_litedramcore_twtrcon_count == 1'd1)) begin
+                main_litedramcore_twtrcon_ready <= 1'd1;
+            end
+        end
+    end
+    builder_multiplexer_state <= builder_multiplexer_next_state;
+    builder_new_master_wdata_ready0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_wdata_ready)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_wdata_ready)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_wdata_ready)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_wdata_ready)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_wdata_ready)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_wdata_ready)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_wdata_ready)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_wdata_ready));
+    builder_new_master_wdata_ready1 <= builder_new_master_wdata_ready0;
+    builder_new_master_rdata_valid0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_rdata_valid)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_rdata_valid)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_rdata_valid)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_rdata_valid)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_rdata_valid)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_rdata_valid)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_rdata_valid)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_rdata_valid));
+    builder_new_master_rdata_valid1 <= builder_new_master_rdata_valid0;
+    builder_new_master_rdata_valid2 <= builder_new_master_rdata_valid1;
+    builder_new_master_rdata_valid3 <= builder_new_master_rdata_valid2;
+    builder_new_master_rdata_valid4 <= builder_new_master_rdata_valid3;
+    builder_new_master_rdata_valid5 <= builder_new_master_rdata_valid4;
+    builder_new_master_rdata_valid6 <= builder_new_master_rdata_valid5;
+    builder_new_master_rdata_valid7 <= builder_new_master_rdata_valid6;
+    builder_new_master_rdata_valid8 <= builder_new_master_rdata_valid7;
+    builder_state <= builder_next_state;
+    if (builder_interface1_dat_w_next_value_ce0) begin
+        builder_interface1_dat_w <= builder_interface1_dat_w_next_value0;
+    end
+    if (builder_interface1_adr_next_value_ce1) begin
+        builder_interface1_adr <= builder_interface1_adr_next_value1;
+    end
+    if (builder_interface1_we_next_value_ce2) begin
+        builder_interface1_we <= builder_interface1_we_next_value2;
+    end
+    builder_interface0_bank_bus_dat_r <= 1'd0;
+    if (builder_csrbank0_sel) begin
+        case (builder_interface0_bank_bus_adr[8:0])
             1'd0: begin
-                interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
+                builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_done0_w;
             end
             1'd1: begin
-                interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
+                builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_error0_w;
             end
         endcase
     end
-    if (csrbank0_init_done0_re) begin
-        init_done_storage <= csrbank0_init_done0_r;
+    if (builder_csrbank0_init_done0_re) begin
+        main_init_done_storage <= builder_csrbank0_init_done0_r;
     end
-    init_done_re <= csrbank0_init_done0_re;
-    if (csrbank0_init_error0_re) begin
-        init_error_storage <= csrbank0_init_error0_r;
+    main_init_done_re <= builder_csrbank0_init_done0_re;
+    if (builder_csrbank0_init_error0_re) begin
+        main_init_error_storage <= builder_csrbank0_init_error0_r;
     end
-    init_error_re <= csrbank0_init_error0_re;
-    interface1_bank_bus_dat_r <= 1'd0;
-    if (csrbank1_sel) begin
-        case (interface1_bank_bus_adr[8:0])
+    main_init_error_re <= builder_csrbank0_init_error0_re;
+    builder_interface1_bank_bus_dat_r <= 1'd0;
+    if (builder_csrbank1_sel) begin
+        case (builder_interface1_bank_bus_adr[8:0])
             1'd0: begin
-                interface1_bank_bus_dat_r <= csrbank1_rst0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_rst0_w;
             end
             1'd1: begin
-                interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_dly_sel0_w;
             end
             2'd2: begin
-                interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_half_sys8x_taps0_w;
             end
             2'd3: begin
-                interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_wlevel_en0_w;
             end
             3'd4: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wlevel_strobe_w;
             end
             3'd5: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_rst_w;
             end
             3'd6: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_inc_w;
             end
             3'd7: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_rst_w;
             end
             4'd8: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_w;
             end
             4'd9: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_rst_w;
             end
             4'd10: begin
-                interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w;
+                builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_w;
             end
             4'd11: begin
-                interface1_bank_bus_dat_r <= csrbank1_rdphase0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_rdphase0_w;
             end
             4'd12: begin
-                interface1_bank_bus_dat_r <= csrbank1_wrphase0_w;
+                builder_interface1_bank_bus_dat_r <= builder_csrbank1_wrphase0_w;
             end
         endcase
     end
-    if (csrbank1_rst0_re) begin
-        a7ddrphy_rst_storage <= csrbank1_rst0_r;
+    if (builder_csrbank1_rst0_re) begin
+        main_a7ddrphy_rst_storage <= builder_csrbank1_rst0_r;
     end
-    a7ddrphy_rst_re <= csrbank1_rst0_re;
-    if (csrbank1_dly_sel0_re) begin
-        a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r;
+    main_a7ddrphy_rst_re <= builder_csrbank1_rst0_re;
+    if (builder_csrbank1_dly_sel0_re) begin
+        main_a7ddrphy_dly_sel_storage[1:0] <= builder_csrbank1_dly_sel0_r;
     end
-    a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
-    if (csrbank1_half_sys8x_taps0_re) begin
-        a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r;
+    main_a7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re;
+    if (builder_csrbank1_half_sys8x_taps0_re) begin
+        main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r;
     end
-    a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re;
-    if (csrbank1_wlevel_en0_re) begin
-        a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r;
+    main_a7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re;
+    if (builder_csrbank1_wlevel_en0_re) begin
+        main_a7ddrphy_wlevel_en_storage <= builder_csrbank1_wlevel_en0_r;
     end
-    a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re;
-    if (csrbank1_rdphase0_re) begin
-        a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r;
+    main_a7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re;
+    if (builder_csrbank1_rdphase0_re) begin
+        main_a7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r;
     end
-    a7ddrphy_rdphase_re <= csrbank1_rdphase0_re;
-    if (csrbank1_wrphase0_re) begin
-        a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r;
+    main_a7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re;
+    if (builder_csrbank1_wrphase0_re) begin
+        main_a7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r;
     end
-    a7ddrphy_wrphase_re <= csrbank1_wrphase0_re;
-    interface2_bank_bus_dat_r <= 1'd0;
-    if (csrbank2_sel) begin
-        case (interface2_bank_bus_adr[8:0])
+    main_a7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re;
+    builder_interface2_bank_bus_dat_r <= 1'd0;
+    if (builder_csrbank2_sel) begin
+        case (builder_interface2_bank_bus_adr[8:0])
             1'd0: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_control0_w;
             end
             1'd1: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_command0_w;
             end
             2'd2: begin
-                interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
+                builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w;
             end
             2'd3: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w;
             end
             3'd4: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w;
             end
             3'd5: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w;
             end
             3'd6: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata_w;
             end
             3'd7: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w;
             end
             4'd8: begin
-                interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
+                builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w;
             end
             4'd9: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w;
             end
             4'd10: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w;
             end
             4'd11: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w;
             end
             4'd12: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata_w;
             end
             4'd13: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w;
             end
             4'd14: begin
-                interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
+                builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w;
             end
             4'd15: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w;
             end
             5'd16: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w;
             end
             5'd17: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w;
             end
             5'd18: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata_w;
             end
             5'd19: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w;
             end
             5'd20: begin
-                interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
+                builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w;
             end
             5'd21: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w;
             end
             5'd22: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w;
             end
             5'd23: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w;
             end
             5'd24: begin
-                interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w;
+                builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata_w;
             end
         endcase
     end
-    if (csrbank2_dfii_control0_re) begin
-        litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
+    if (builder_csrbank2_dfii_control0_re) begin
+        main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r;
     end
-    litedramcore_re <= csrbank2_dfii_control0_re;
-    if (csrbank2_dfii_pi0_command0_re) begin
-        litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
+    main_litedramcore_re <= builder_csrbank2_dfii_control0_re;
+    if (builder_csrbank2_dfii_pi0_command0_re) begin
+        main_litedramcore_phaseinjector0_command_storage[7:0] <= builder_csrbank2_dfii_pi0_command0_r;
     end
-    litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
-    if (csrbank2_dfii_pi0_address0_re) begin
-        litedramcore_phaseinjector0_address_storage[13:0] <= csrbank2_dfii_pi0_address0_r;
+    main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re;
+    if (builder_csrbank2_dfii_pi0_address0_re) begin
+        main_litedramcore_phaseinjector0_address_storage[13:0] <= builder_csrbank2_dfii_pi0_address0_r;
     end
-    litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
-    if (csrbank2_dfii_pi0_baddress0_re) begin
-        litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
+    main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re;
+    if (builder_csrbank2_dfii_pi0_baddress0_re) begin
+        main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r;
     end
-    litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
-    if (csrbank2_dfii_pi0_wrdata0_re) begin
-        litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
+    main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re;
+    if (builder_csrbank2_dfii_pi0_wrdata0_re) begin
+        main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r;
     end
-    litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
-    litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re;
-    if (csrbank2_dfii_pi1_command0_re) begin
-        litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
+    main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re;
+    main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re;
+    if (builder_csrbank2_dfii_pi1_command0_re) begin
+        main_litedramcore_phaseinjector1_command_storage[7:0] <= builder_csrbank2_dfii_pi1_command0_r;
     end
-    litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
-    if (csrbank2_dfii_pi1_address0_re) begin
-        litedramcore_phaseinjector1_address_storage[13:0] <= csrbank2_dfii_pi1_address0_r;
+    main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re;
+    if (builder_csrbank2_dfii_pi1_address0_re) begin
+        main_litedramcore_phaseinjector1_address_storage[13:0] <= builder_csrbank2_dfii_pi1_address0_r;
     end
-    litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
-    if (csrbank2_dfii_pi1_baddress0_re) begin
-        litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
+    main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re;
+    if (builder_csrbank2_dfii_pi1_baddress0_re) begin
+        main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r;
     end
-    litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
-    if (csrbank2_dfii_pi1_wrdata0_re) begin
-        litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
+    main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re;
+    if (builder_csrbank2_dfii_pi1_wrdata0_re) begin
+        main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r;
     end
-    litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
-    litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re;
-    if (csrbank2_dfii_pi2_command0_re) begin
-        litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
+    main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re;
+    main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re;
+    if (builder_csrbank2_dfii_pi2_command0_re) begin
+        main_litedramcore_phaseinjector2_command_storage[7:0] <= builder_csrbank2_dfii_pi2_command0_r;
     end
-    litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
-    if (csrbank2_dfii_pi2_address0_re) begin
-        litedramcore_phaseinjector2_address_storage[13:0] <= csrbank2_dfii_pi2_address0_r;
+    main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re;
+    if (builder_csrbank2_dfii_pi2_address0_re) begin
+        main_litedramcore_phaseinjector2_address_storage[13:0] <= builder_csrbank2_dfii_pi2_address0_r;
     end
-    litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
-    if (csrbank2_dfii_pi2_baddress0_re) begin
-        litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
+    main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re;
+    if (builder_csrbank2_dfii_pi2_baddress0_re) begin
+        main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r;
     end
-    litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
-    if (csrbank2_dfii_pi2_wrdata0_re) begin
-        litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
+    main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re;
+    if (builder_csrbank2_dfii_pi2_wrdata0_re) begin
+        main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r;
     end
-    litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
-    litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re;
-    if (csrbank2_dfii_pi3_command0_re) begin
-        litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
+    main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re;
+    main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re;
+    if (builder_csrbank2_dfii_pi3_command0_re) begin
+        main_litedramcore_phaseinjector3_command_storage[7:0] <= builder_csrbank2_dfii_pi3_command0_r;
     end
-    litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
-    if (csrbank2_dfii_pi3_address0_re) begin
-        litedramcore_phaseinjector3_address_storage[13:0] <= csrbank2_dfii_pi3_address0_r;
+    main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re;
+    if (builder_csrbank2_dfii_pi3_address0_re) begin
+        main_litedramcore_phaseinjector3_address_storage[13:0] <= builder_csrbank2_dfii_pi3_address0_r;
     end
-    litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
-    if (csrbank2_dfii_pi3_baddress0_re) begin
-        litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
+    main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re;
+    if (builder_csrbank2_dfii_pi3_baddress0_re) begin
+        main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r;
     end
-    litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
-    if (csrbank2_dfii_pi3_wrdata0_re) begin
-        litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
+    main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re;
+    if (builder_csrbank2_dfii_pi3_wrdata0_re) begin
+        main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r;
     end
-    litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
-    litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re;
+    main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re;
+    main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re;
     if (sys_rst) begin
-        a7ddrphy_rst_storage <= 1'd0;
-        a7ddrphy_rst_re <= 1'd0;
-        a7ddrphy_dly_sel_storage <= 2'd0;
-        a7ddrphy_dly_sel_re <= 1'd0;
-        a7ddrphy_half_sys8x_taps_storage <= 5'd8;
-        a7ddrphy_half_sys8x_taps_re <= 1'd0;
-        a7ddrphy_wlevel_en_storage <= 1'd0;
-        a7ddrphy_wlevel_en_re <= 1'd0;
-        a7ddrphy_rdphase_storage <= 2'd2;
-        a7ddrphy_rdphase_re <= 1'd0;
-        a7ddrphy_wrphase_storage <= 2'd3;
-        a7ddrphy_wrphase_re <= 1'd0;
-        a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
-        a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
-        a7ddrphy_dqspattern_o1 <= 8'd0;
-        a7ddrphy_bitslip0_value0 <= 3'd7;
-        a7ddrphy_bitslip1_value0 <= 3'd7;
-        a7ddrphy_bitslip0_value1 <= 3'd7;
-        a7ddrphy_bitslip1_value1 <= 3'd7;
-        a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
-        a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
-        a7ddrphy_bitslip0_value2 <= 3'd7;
-        a7ddrphy_bitslip0_value3 <= 3'd7;
-        a7ddrphy_bitslip1_value2 <= 3'd7;
-        a7ddrphy_bitslip1_value3 <= 3'd7;
-        a7ddrphy_bitslip2_value0 <= 3'd7;
-        a7ddrphy_bitslip2_value1 <= 3'd7;
-        a7ddrphy_bitslip3_value0 <= 3'd7;
-        a7ddrphy_bitslip3_value1 <= 3'd7;
-        a7ddrphy_bitslip4_value0 <= 3'd7;
-        a7ddrphy_bitslip4_value1 <= 3'd7;
-        a7ddrphy_bitslip5_value0 <= 3'd7;
-        a7ddrphy_bitslip5_value1 <= 3'd7;
-        a7ddrphy_bitslip6_value0 <= 3'd7;
-        a7ddrphy_bitslip6_value1 <= 3'd7;
-        a7ddrphy_bitslip7_value0 <= 3'd7;
-        a7ddrphy_bitslip7_value1 <= 3'd7;
-        a7ddrphy_bitslip8_value0 <= 3'd7;
-        a7ddrphy_bitslip8_value1 <= 3'd7;
-        a7ddrphy_bitslip9_value0 <= 3'd7;
-        a7ddrphy_bitslip9_value1 <= 3'd7;
-        a7ddrphy_bitslip10_value0 <= 3'd7;
-        a7ddrphy_bitslip10_value1 <= 3'd7;
-        a7ddrphy_bitslip11_value0 <= 3'd7;
-        a7ddrphy_bitslip11_value1 <= 3'd7;
-        a7ddrphy_bitslip12_value0 <= 3'd7;
-        a7ddrphy_bitslip12_value1 <= 3'd7;
-        a7ddrphy_bitslip13_value0 <= 3'd7;
-        a7ddrphy_bitslip13_value1 <= 3'd7;
-        a7ddrphy_bitslip14_value0 <= 3'd7;
-        a7ddrphy_bitslip14_value1 <= 3'd7;
-        a7ddrphy_bitslip15_value0 <= 3'd7;
-        a7ddrphy_bitslip15_value1 <= 3'd7;
-        a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
-        a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
-        a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
-        a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
-        a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
-        litedramcore_storage <= 4'd1;
-        litedramcore_re <= 1'd0;
-        litedramcore_phaseinjector0_command_storage <= 6'd0;
-        litedramcore_phaseinjector0_command_re <= 1'd0;
-        litedramcore_phaseinjector0_address_re <= 1'd0;
-        litedramcore_phaseinjector0_baddress_re <= 1'd0;
-        litedramcore_phaseinjector0_wrdata_re <= 1'd0;
-        litedramcore_phaseinjector0_rddata_status <= 32'd0;
-        litedramcore_phaseinjector0_rddata_re <= 1'd0;
-        litedramcore_phaseinjector1_command_storage <= 6'd0;
-        litedramcore_phaseinjector1_command_re <= 1'd0;
-        litedramcore_phaseinjector1_address_re <= 1'd0;
-        litedramcore_phaseinjector1_baddress_re <= 1'd0;
-        litedramcore_phaseinjector1_wrdata_re <= 1'd0;
-        litedramcore_phaseinjector1_rddata_status <= 32'd0;
-        litedramcore_phaseinjector1_rddata_re <= 1'd0;
-        litedramcore_phaseinjector2_command_storage <= 6'd0;
-        litedramcore_phaseinjector2_command_re <= 1'd0;
-        litedramcore_phaseinjector2_address_re <= 1'd0;
-        litedramcore_phaseinjector2_baddress_re <= 1'd0;
-        litedramcore_phaseinjector2_wrdata_re <= 1'd0;
-        litedramcore_phaseinjector2_rddata_status <= 32'd0;
-        litedramcore_phaseinjector2_rddata_re <= 1'd0;
-        litedramcore_phaseinjector3_command_storage <= 6'd0;
-        litedramcore_phaseinjector3_command_re <= 1'd0;
-        litedramcore_phaseinjector3_address_re <= 1'd0;
-        litedramcore_phaseinjector3_baddress_re <= 1'd0;
-        litedramcore_phaseinjector3_wrdata_re <= 1'd0;
-        litedramcore_phaseinjector3_rddata_status <= 32'd0;
-        litedramcore_phaseinjector3_rddata_re <= 1'd0;
-        litedramcore_dfi_p0_address <= 14'd0;
-        litedramcore_dfi_p0_bank <= 3'd0;
-        litedramcore_dfi_p0_cas_n <= 1'd1;
-        litedramcore_dfi_p0_cs_n <= 1'd1;
-        litedramcore_dfi_p0_ras_n <= 1'd1;
-        litedramcore_dfi_p0_we_n <= 1'd1;
-        litedramcore_dfi_p0_wrdata_en <= 1'd0;
-        litedramcore_dfi_p0_rddata_en <= 1'd0;
-        litedramcore_dfi_p1_address <= 14'd0;
-        litedramcore_dfi_p1_bank <= 3'd0;
-        litedramcore_dfi_p1_cas_n <= 1'd1;
-        litedramcore_dfi_p1_cs_n <= 1'd1;
-        litedramcore_dfi_p1_ras_n <= 1'd1;
-        litedramcore_dfi_p1_we_n <= 1'd1;
-        litedramcore_dfi_p1_wrdata_en <= 1'd0;
-        litedramcore_dfi_p1_rddata_en <= 1'd0;
-        litedramcore_dfi_p2_address <= 14'd0;
-        litedramcore_dfi_p2_bank <= 3'd0;
-        litedramcore_dfi_p2_cas_n <= 1'd1;
-        litedramcore_dfi_p2_cs_n <= 1'd1;
-        litedramcore_dfi_p2_ras_n <= 1'd1;
-        litedramcore_dfi_p2_we_n <= 1'd1;
-        litedramcore_dfi_p2_wrdata_en <= 1'd0;
-        litedramcore_dfi_p2_rddata_en <= 1'd0;
-        litedramcore_dfi_p3_address <= 14'd0;
-        litedramcore_dfi_p3_bank <= 3'd0;
-        litedramcore_dfi_p3_cas_n <= 1'd1;
-        litedramcore_dfi_p3_cs_n <= 1'd1;
-        litedramcore_dfi_p3_ras_n <= 1'd1;
-        litedramcore_dfi_p3_we_n <= 1'd1;
-        litedramcore_dfi_p3_wrdata_en <= 1'd0;
-        litedramcore_dfi_p3_rddata_en <= 1'd0;
-        litedramcore_cmd_payload_a <= 14'd0;
-        litedramcore_cmd_payload_ba <= 3'd0;
-        litedramcore_cmd_payload_cas <= 1'd0;
-        litedramcore_cmd_payload_ras <= 1'd0;
-        litedramcore_cmd_payload_we <= 1'd0;
-        litedramcore_timer_count1 <= 10'd781;
-        litedramcore_postponer_req_o <= 1'd0;
-        litedramcore_postponer_count <= 1'd0;
-        litedramcore_sequencer_done1 <= 1'd0;
-        litedramcore_sequencer_counter <= 6'd0;
-        litedramcore_sequencer_count <= 1'd0;
-        litedramcore_zqcs_timer_count1 <= 27'd99999999;
-        litedramcore_zqcs_executer_done <= 1'd0;
-        litedramcore_zqcs_executer_counter <= 5'd0;
-        litedramcore_bankmachine0_level <= 5'd0;
-        litedramcore_bankmachine0_produce <= 4'd0;
-        litedramcore_bankmachine0_consume <= 4'd0;
-        litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 21'd0;
-        litedramcore_bankmachine0_row <= 14'd0;
-        litedramcore_bankmachine0_row_opened <= 1'd0;
-        litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine0_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine0_trccon_ready <= 1'd0;
-        litedramcore_bankmachine0_trccon_count <= 3'd0;
-        litedramcore_bankmachine0_trascon_ready <= 1'd0;
-        litedramcore_bankmachine0_trascon_count <= 3'd0;
-        litedramcore_bankmachine1_level <= 5'd0;
-        litedramcore_bankmachine1_produce <= 4'd0;
-        litedramcore_bankmachine1_consume <= 4'd0;
-        litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 21'd0;
-        litedramcore_bankmachine1_row <= 14'd0;
-        litedramcore_bankmachine1_row_opened <= 1'd0;
-        litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine1_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine1_trccon_ready <= 1'd0;
-        litedramcore_bankmachine1_trccon_count <= 3'd0;
-        litedramcore_bankmachine1_trascon_ready <= 1'd0;
-        litedramcore_bankmachine1_trascon_count <= 3'd0;
-        litedramcore_bankmachine2_level <= 5'd0;
-        litedramcore_bankmachine2_produce <= 4'd0;
-        litedramcore_bankmachine2_consume <= 4'd0;
-        litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 21'd0;
-        litedramcore_bankmachine2_row <= 14'd0;
-        litedramcore_bankmachine2_row_opened <= 1'd0;
-        litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine2_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine2_trccon_ready <= 1'd0;
-        litedramcore_bankmachine2_trccon_count <= 3'd0;
-        litedramcore_bankmachine2_trascon_ready <= 1'd0;
-        litedramcore_bankmachine2_trascon_count <= 3'd0;
-        litedramcore_bankmachine3_level <= 5'd0;
-        litedramcore_bankmachine3_produce <= 4'd0;
-        litedramcore_bankmachine3_consume <= 4'd0;
-        litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 21'd0;
-        litedramcore_bankmachine3_row <= 14'd0;
-        litedramcore_bankmachine3_row_opened <= 1'd0;
-        litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine3_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine3_trccon_ready <= 1'd0;
-        litedramcore_bankmachine3_trccon_count <= 3'd0;
-        litedramcore_bankmachine3_trascon_ready <= 1'd0;
-        litedramcore_bankmachine3_trascon_count <= 3'd0;
-        litedramcore_bankmachine4_level <= 5'd0;
-        litedramcore_bankmachine4_produce <= 4'd0;
-        litedramcore_bankmachine4_consume <= 4'd0;
-        litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 21'd0;
-        litedramcore_bankmachine4_row <= 14'd0;
-        litedramcore_bankmachine4_row_opened <= 1'd0;
-        litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine4_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine4_trccon_ready <= 1'd0;
-        litedramcore_bankmachine4_trccon_count <= 3'd0;
-        litedramcore_bankmachine4_trascon_ready <= 1'd0;
-        litedramcore_bankmachine4_trascon_count <= 3'd0;
-        litedramcore_bankmachine5_level <= 5'd0;
-        litedramcore_bankmachine5_produce <= 4'd0;
-        litedramcore_bankmachine5_consume <= 4'd0;
-        litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 21'd0;
-        litedramcore_bankmachine5_row <= 14'd0;
-        litedramcore_bankmachine5_row_opened <= 1'd0;
-        litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine5_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine5_trccon_ready <= 1'd0;
-        litedramcore_bankmachine5_trccon_count <= 3'd0;
-        litedramcore_bankmachine5_trascon_ready <= 1'd0;
-        litedramcore_bankmachine5_trascon_count <= 3'd0;
-        litedramcore_bankmachine6_level <= 5'd0;
-        litedramcore_bankmachine6_produce <= 4'd0;
-        litedramcore_bankmachine6_consume <= 4'd0;
-        litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 21'd0;
-        litedramcore_bankmachine6_row <= 14'd0;
-        litedramcore_bankmachine6_row_opened <= 1'd0;
-        litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine6_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine6_trccon_ready <= 1'd0;
-        litedramcore_bankmachine6_trccon_count <= 3'd0;
-        litedramcore_bankmachine6_trascon_ready <= 1'd0;
-        litedramcore_bankmachine6_trascon_count <= 3'd0;
-        litedramcore_bankmachine7_level <= 5'd0;
-        litedramcore_bankmachine7_produce <= 4'd0;
-        litedramcore_bankmachine7_consume <= 4'd0;
-        litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0;
-        litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0;
-        litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 21'd0;
-        litedramcore_bankmachine7_row <= 14'd0;
-        litedramcore_bankmachine7_row_opened <= 1'd0;
-        litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
-        litedramcore_bankmachine7_twtpcon_count <= 3'd0;
-        litedramcore_bankmachine7_trccon_ready <= 1'd0;
-        litedramcore_bankmachine7_trccon_count <= 3'd0;
-        litedramcore_bankmachine7_trascon_ready <= 1'd0;
-        litedramcore_bankmachine7_trascon_count <= 3'd0;
-        litedramcore_choose_cmd_grant <= 3'd0;
-        litedramcore_choose_req_grant <= 3'd0;
-        litedramcore_trrdcon_ready <= 1'd0;
-        litedramcore_trrdcon_count <= 1'd0;
-        litedramcore_tfawcon_ready <= 1'd1;
-        litedramcore_tfawcon_window <= 5'd0;
-        litedramcore_tccdcon_ready <= 1'd0;
-        litedramcore_tccdcon_count <= 1'd0;
-        litedramcore_twtrcon_ready <= 1'd0;
-        litedramcore_twtrcon_count <= 3'd0;
-        litedramcore_time0 <= 5'd0;
-        litedramcore_time1 <= 4'd0;
-        init_done_storage <= 1'd0;
-        init_done_re <= 1'd0;
-        init_error_storage <= 1'd0;
-        init_error_re <= 1'd0;
-        litedramcore_we <= 1'd0;
-        litedramcore_refresher_state <= 2'd0;
-        litedramcore_bankmachine0_state <= 4'd0;
-        litedramcore_bankmachine1_state <= 4'd0;
-        litedramcore_bankmachine2_state <= 4'd0;
-        litedramcore_bankmachine3_state <= 4'd0;
-        litedramcore_bankmachine4_state <= 4'd0;
-        litedramcore_bankmachine5_state <= 4'd0;
-        litedramcore_bankmachine6_state <= 4'd0;
-        litedramcore_bankmachine7_state <= 4'd0;
-        litedramcore_multiplexer_state <= 4'd0;
-        litedramcore_new_master_wdata_ready0 <= 1'd0;
-        litedramcore_new_master_wdata_ready1 <= 1'd0;
-        litedramcore_new_master_rdata_valid0 <= 1'd0;
-        litedramcore_new_master_rdata_valid1 <= 1'd0;
-        litedramcore_new_master_rdata_valid2 <= 1'd0;
-        litedramcore_new_master_rdata_valid3 <= 1'd0;
-        litedramcore_new_master_rdata_valid4 <= 1'd0;
-        litedramcore_new_master_rdata_valid5 <= 1'd0;
-        litedramcore_new_master_rdata_valid6 <= 1'd0;
-        litedramcore_new_master_rdata_valid7 <= 1'd0;
-        litedramcore_new_master_rdata_valid8 <= 1'd0;
-        litedramcore_state <= 2'd0;
+        main_a7ddrphy_rst_storage <= 1'd0;
+        main_a7ddrphy_rst_re <= 1'd0;
+        main_a7ddrphy_dly_sel_storage <= 2'd0;
+        main_a7ddrphy_dly_sel_re <= 1'd0;
+        main_a7ddrphy_half_sys8x_taps_storage <= 5'd8;
+        main_a7ddrphy_half_sys8x_taps_re <= 1'd0;
+        main_a7ddrphy_wlevel_en_storage <= 1'd0;
+        main_a7ddrphy_wlevel_en_re <= 1'd0;
+        main_a7ddrphy_rdphase_storage <= 2'd2;
+        main_a7ddrphy_rdphase_re <= 1'd0;
+        main_a7ddrphy_wrphase_storage <= 2'd3;
+        main_a7ddrphy_wrphase_re <= 1'd0;
+        main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+        main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+        main_a7ddrphy_dqspattern_o1 <= 8'd0;
+        main_a7ddrphy_bitslip0_value0 <= 3'd7;
+        main_a7ddrphy_bitslip1_value0 <= 3'd7;
+        main_a7ddrphy_bitslip0_value1 <= 3'd7;
+        main_a7ddrphy_bitslip1_value1 <= 3'd7;
+        main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+        main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+        main_a7ddrphy_bitslip0_value2 <= 3'd7;
+        main_a7ddrphy_bitslip0_value3 <= 3'd7;
+        main_a7ddrphy_bitslip1_value2 <= 3'd7;
+        main_a7ddrphy_bitslip1_value3 <= 3'd7;
+        main_a7ddrphy_bitslip2_value0 <= 3'd7;
+        main_a7ddrphy_bitslip2_value1 <= 3'd7;
+        main_a7ddrphy_bitslip3_value0 <= 3'd7;
+        main_a7ddrphy_bitslip3_value1 <= 3'd7;
+        main_a7ddrphy_bitslip4_value0 <= 3'd7;
+        main_a7ddrphy_bitslip4_value1 <= 3'd7;
+        main_a7ddrphy_bitslip5_value0 <= 3'd7;
+        main_a7ddrphy_bitslip5_value1 <= 3'd7;
+        main_a7ddrphy_bitslip6_value0 <= 3'd7;
+        main_a7ddrphy_bitslip6_value1 <= 3'd7;
+        main_a7ddrphy_bitslip7_value0 <= 3'd7;
+        main_a7ddrphy_bitslip7_value1 <= 3'd7;
+        main_a7ddrphy_bitslip8_value0 <= 3'd7;
+        main_a7ddrphy_bitslip8_value1 <= 3'd7;
+        main_a7ddrphy_bitslip9_value0 <= 3'd7;
+        main_a7ddrphy_bitslip9_value1 <= 3'd7;
+        main_a7ddrphy_bitslip10_value0 <= 3'd7;
+        main_a7ddrphy_bitslip10_value1 <= 3'd7;
+        main_a7ddrphy_bitslip11_value0 <= 3'd7;
+        main_a7ddrphy_bitslip11_value1 <= 3'd7;
+        main_a7ddrphy_bitslip12_value0 <= 3'd7;
+        main_a7ddrphy_bitslip12_value1 <= 3'd7;
+        main_a7ddrphy_bitslip13_value0 <= 3'd7;
+        main_a7ddrphy_bitslip13_value1 <= 3'd7;
+        main_a7ddrphy_bitslip14_value0 <= 3'd7;
+        main_a7ddrphy_bitslip14_value1 <= 3'd7;
+        main_a7ddrphy_bitslip15_value0 <= 3'd7;
+        main_a7ddrphy_bitslip15_value1 <= 3'd7;
+        main_a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
+        main_a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
+        main_a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
+        main_a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
+        main_a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
+        main_litedramcore_storage <= 4'd1;
+        main_litedramcore_re <= 1'd0;
+        main_litedramcore_phaseinjector0_command_storage <= 8'd0;
+        main_litedramcore_phaseinjector0_command_re <= 1'd0;
+        main_litedramcore_phaseinjector0_address_re <= 1'd0;
+        main_litedramcore_phaseinjector0_baddress_re <= 1'd0;
+        main_litedramcore_phaseinjector0_wrdata_re <= 1'd0;
+        main_litedramcore_phaseinjector0_rddata_status <= 32'd0;
+        main_litedramcore_phaseinjector0_rddata_re <= 1'd0;
+        main_litedramcore_phaseinjector1_command_storage <= 8'd0;
+        main_litedramcore_phaseinjector1_command_re <= 1'd0;
+        main_litedramcore_phaseinjector1_address_re <= 1'd0;
+        main_litedramcore_phaseinjector1_baddress_re <= 1'd0;
+        main_litedramcore_phaseinjector1_wrdata_re <= 1'd0;
+        main_litedramcore_phaseinjector1_rddata_status <= 32'd0;
+        main_litedramcore_phaseinjector1_rddata_re <= 1'd0;
+        main_litedramcore_phaseinjector2_command_storage <= 8'd0;
+        main_litedramcore_phaseinjector2_command_re <= 1'd0;
+        main_litedramcore_phaseinjector2_address_re <= 1'd0;
+        main_litedramcore_phaseinjector2_baddress_re <= 1'd0;
+        main_litedramcore_phaseinjector2_wrdata_re <= 1'd0;
+        main_litedramcore_phaseinjector2_rddata_status <= 32'd0;
+        main_litedramcore_phaseinjector2_rddata_re <= 1'd0;
+        main_litedramcore_phaseinjector3_command_storage <= 8'd0;
+        main_litedramcore_phaseinjector3_command_re <= 1'd0;
+        main_litedramcore_phaseinjector3_address_re <= 1'd0;
+        main_litedramcore_phaseinjector3_baddress_re <= 1'd0;
+        main_litedramcore_phaseinjector3_wrdata_re <= 1'd0;
+        main_litedramcore_phaseinjector3_rddata_status <= 32'd0;
+        main_litedramcore_phaseinjector3_rddata_re <= 1'd0;
+        main_litedramcore_dfi_p0_address <= 14'd0;
+        main_litedramcore_dfi_p0_bank <= 3'd0;
+        main_litedramcore_dfi_p0_cas_n <= 1'd1;
+        main_litedramcore_dfi_p0_cs_n <= 1'd1;
+        main_litedramcore_dfi_p0_ras_n <= 1'd1;
+        main_litedramcore_dfi_p0_we_n <= 1'd1;
+        main_litedramcore_dfi_p0_wrdata_en <= 1'd0;
+        main_litedramcore_dfi_p0_rddata_en <= 1'd0;
+        main_litedramcore_dfi_p1_address <= 14'd0;
+        main_litedramcore_dfi_p1_bank <= 3'd0;
+        main_litedramcore_dfi_p1_cas_n <= 1'd1;
+        main_litedramcore_dfi_p1_cs_n <= 1'd1;
+        main_litedramcore_dfi_p1_ras_n <= 1'd1;
+        main_litedramcore_dfi_p1_we_n <= 1'd1;
+        main_litedramcore_dfi_p1_wrdata_en <= 1'd0;
+        main_litedramcore_dfi_p1_rddata_en <= 1'd0;
+        main_litedramcore_dfi_p2_address <= 14'd0;
+        main_litedramcore_dfi_p2_bank <= 3'd0;
+        main_litedramcore_dfi_p2_cas_n <= 1'd1;
+        main_litedramcore_dfi_p2_cs_n <= 1'd1;
+        main_litedramcore_dfi_p2_ras_n <= 1'd1;
+        main_litedramcore_dfi_p2_we_n <= 1'd1;
+        main_litedramcore_dfi_p2_wrdata_en <= 1'd0;
+        main_litedramcore_dfi_p2_rddata_en <= 1'd0;
+        main_litedramcore_dfi_p3_address <= 14'd0;
+        main_litedramcore_dfi_p3_bank <= 3'd0;
+        main_litedramcore_dfi_p3_cas_n <= 1'd1;
+        main_litedramcore_dfi_p3_cs_n <= 1'd1;
+        main_litedramcore_dfi_p3_ras_n <= 1'd1;
+        main_litedramcore_dfi_p3_we_n <= 1'd1;
+        main_litedramcore_dfi_p3_wrdata_en <= 1'd0;
+        main_litedramcore_dfi_p3_rddata_en <= 1'd0;
+        main_litedramcore_cmd_payload_a <= 14'd0;
+        main_litedramcore_cmd_payload_ba <= 3'd0;
+        main_litedramcore_cmd_payload_cas <= 1'd0;
+        main_litedramcore_cmd_payload_ras <= 1'd0;
+        main_litedramcore_cmd_payload_we <= 1'd0;
+        main_litedramcore_timer_count1 <= 10'd781;
+        main_litedramcore_postponer_req_o <= 1'd0;
+        main_litedramcore_postponer_count <= 1'd0;
+        main_litedramcore_sequencer_done1 <= 1'd0;
+        main_litedramcore_sequencer_trigger <= 6'd0;
+        main_litedramcore_sequencer_count <= 1'd0;
+        main_litedramcore_zqcs_timer_count1 <= 27'd99999999;
+        main_litedramcore_zqcs_executer_done <= 1'd0;
+        main_litedramcore_zqcs_executer_trigger <= 5'd0;
+        main_litedramcore_bankmachine0_level <= 5'd0;
+        main_litedramcore_bankmachine0_produce <= 4'd0;
+        main_litedramcore_bankmachine0_consume <= 4'd0;
+        main_litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 21'd0;
+        main_litedramcore_bankmachine0_row <= 14'd0;
+        main_litedramcore_bankmachine0_row_opened <= 1'd0;
+        main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine0_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine0_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine0_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine0_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine0_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine1_level <= 5'd0;
+        main_litedramcore_bankmachine1_produce <= 4'd0;
+        main_litedramcore_bankmachine1_consume <= 4'd0;
+        main_litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 21'd0;
+        main_litedramcore_bankmachine1_row <= 14'd0;
+        main_litedramcore_bankmachine1_row_opened <= 1'd0;
+        main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine1_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine1_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine1_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine1_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine1_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine2_level <= 5'd0;
+        main_litedramcore_bankmachine2_produce <= 4'd0;
+        main_litedramcore_bankmachine2_consume <= 4'd0;
+        main_litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 21'd0;
+        main_litedramcore_bankmachine2_row <= 14'd0;
+        main_litedramcore_bankmachine2_row_opened <= 1'd0;
+        main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine2_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine2_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine2_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine2_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine2_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine3_level <= 5'd0;
+        main_litedramcore_bankmachine3_produce <= 4'd0;
+        main_litedramcore_bankmachine3_consume <= 4'd0;
+        main_litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 21'd0;
+        main_litedramcore_bankmachine3_row <= 14'd0;
+        main_litedramcore_bankmachine3_row_opened <= 1'd0;
+        main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine3_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine3_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine3_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine3_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine3_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine4_level <= 5'd0;
+        main_litedramcore_bankmachine4_produce <= 4'd0;
+        main_litedramcore_bankmachine4_consume <= 4'd0;
+        main_litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 21'd0;
+        main_litedramcore_bankmachine4_row <= 14'd0;
+        main_litedramcore_bankmachine4_row_opened <= 1'd0;
+        main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine4_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine4_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine4_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine4_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine4_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine5_level <= 5'd0;
+        main_litedramcore_bankmachine5_produce <= 4'd0;
+        main_litedramcore_bankmachine5_consume <= 4'd0;
+        main_litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 21'd0;
+        main_litedramcore_bankmachine5_row <= 14'd0;
+        main_litedramcore_bankmachine5_row_opened <= 1'd0;
+        main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine5_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine5_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine5_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine5_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine5_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine6_level <= 5'd0;
+        main_litedramcore_bankmachine6_produce <= 4'd0;
+        main_litedramcore_bankmachine6_consume <= 4'd0;
+        main_litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 21'd0;
+        main_litedramcore_bankmachine6_row <= 14'd0;
+        main_litedramcore_bankmachine6_row_opened <= 1'd0;
+        main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine6_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine6_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine6_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine6_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine6_trascon_count <= 3'd0;
+        main_litedramcore_bankmachine7_level <= 5'd0;
+        main_litedramcore_bankmachine7_produce <= 4'd0;
+        main_litedramcore_bankmachine7_consume <= 4'd0;
+        main_litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0;
+        main_litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0;
+        main_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 21'd0;
+        main_litedramcore_bankmachine7_row <= 14'd0;
+        main_litedramcore_bankmachine7_row_opened <= 1'd0;
+        main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+        main_litedramcore_bankmachine7_twtpcon_count <= 3'd0;
+        main_litedramcore_bankmachine7_trccon_ready <= 1'd0;
+        main_litedramcore_bankmachine7_trccon_count <= 3'd0;
+        main_litedramcore_bankmachine7_trascon_ready <= 1'd0;
+        main_litedramcore_bankmachine7_trascon_count <= 3'd0;
+        main_litedramcore_choose_cmd_grant <= 3'd0;
+        main_litedramcore_choose_req_grant <= 3'd0;
+        main_litedramcore_trrdcon_ready <= 1'd0;
+        main_litedramcore_trrdcon_count <= 1'd0;
+        main_litedramcore_tfawcon_ready <= 1'd1;
+        main_litedramcore_tfawcon_window <= 5'd0;
+        main_litedramcore_tccdcon_ready <= 1'd0;
+        main_litedramcore_tccdcon_count <= 1'd0;
+        main_litedramcore_twtrcon_ready <= 1'd0;
+        main_litedramcore_twtrcon_count <= 3'd0;
+        main_litedramcore_time0 <= 5'd0;
+        main_litedramcore_time1 <= 4'd0;
+        main_init_done_storage <= 1'd0;
+        main_init_done_re <= 1'd0;
+        main_init_error_storage <= 1'd0;
+        main_init_error_re <= 1'd0;
+        builder_interface1_we <= 1'd0;
+        builder_refresher_state <= 2'd0;
+        builder_bankmachine0_state <= 4'd0;
+        builder_bankmachine1_state <= 4'd0;
+        builder_bankmachine2_state <= 4'd0;
+        builder_bankmachine3_state <= 4'd0;
+        builder_bankmachine4_state <= 4'd0;
+        builder_bankmachine5_state <= 4'd0;
+        builder_bankmachine6_state <= 4'd0;
+        builder_bankmachine7_state <= 4'd0;
+        builder_multiplexer_state <= 4'd0;
+        builder_new_master_wdata_ready0 <= 1'd0;
+        builder_new_master_wdata_ready1 <= 1'd0;
+        builder_new_master_rdata_valid0 <= 1'd0;
+        builder_new_master_rdata_valid1 <= 1'd0;
+        builder_new_master_rdata_valid2 <= 1'd0;
+        builder_new_master_rdata_valid3 <= 1'd0;
+        builder_new_master_rdata_valid4 <= 1'd0;
+        builder_new_master_rdata_valid5 <= 1'd0;
+        builder_new_master_rdata_valid6 <= 1'd0;
+        builder_new_master_rdata_valid7 <= 1'd0;
+        builder_new_master_rdata_valid8 <= 1'd0;
+        builder_state <= 2'd0;
     end
 end
 
@@ -14116,1911 +14531,2624 @@ end
 // Specialized Logic
 //------------------------------------------------------------------------------
 
+//------------------------------------------------------------------------------
+// Instance BUFG of BUFG Module.
+//------------------------------------------------------------------------------
 BUFG BUFG(
-	.I(clkout0),
-	.O(clkout_buf0)
+	// Inputs.
+	.I (main_clkout0),
+
+	// Outputs.
+	.O (main_clkout_buf0)
 );
 
+//------------------------------------------------------------------------------
+// Instance BUFG_1 of BUFG Module.
+//------------------------------------------------------------------------------
 BUFG BUFG_1(
-	.I(clkout1),
-	.O(clkout_buf1)
+	// Inputs.
+	.I (main_clkout1),
+
+	// Outputs.
+	.O (main_clkout_buf1)
 );
 
+//------------------------------------------------------------------------------
+// Instance BUFG_2 of BUFG Module.
+//------------------------------------------------------------------------------
 BUFG BUFG_2(
-	.I(clkout2),
-	.O(clkout_buf2)
+	// Inputs.
+	.I (main_clkout2),
+
+	// Outputs.
+	.O (main_clkout_buf2)
 );
 
+//------------------------------------------------------------------------------
+// Instance BUFG_3 of BUFG Module.
+//------------------------------------------------------------------------------
 BUFG BUFG_3(
-	.I(clkout3),
-	.O(clkout_buf3)
+	// Inputs.
+	.I (main_clkout3),
+
+	// Outputs.
+	.O (main_clkout_buf3)
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYCTRL of IDELAYCTRL Module.
+//------------------------------------------------------------------------------
 IDELAYCTRL IDELAYCTRL(
-	.REFCLK(iodelay_clk),
-	.RST(ic_reset)
+	// Inputs.
+	.REFCLK (iodelay_clk),
+	.RST    (main_ic_reset)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(1'd0),
-	.D2(1'd1),
-	.D3(1'd0),
-	.D4(1'd1),
-	.D5(1'd0),
-	.D6(1'd1),
-	.D7(1'd0),
-	.D8(1'd1),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(a7ddrphy_sd_clk_se_nodelay)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (1'd0),
+	.D2     (1'd1),
+	.D3     (1'd0),
+	.D4     (1'd1),
+	.D5     (1'd0),
+	.D6     (1'd1),
+	.D7     (1'd0),
+	.D8     (1'd1),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_sd_clk_se_nodelay)
 );
 
+//------------------------------------------------------------------------------
+// Instance OBUFDS of OBUFDS Module.
+//------------------------------------------------------------------------------
 OBUFDS OBUFDS(
-	.I(a7ddrphy_sd_clk_se_nodelay),
-	.O(ddram_clk_p),
-	.OB(ddram_clk_n)
+	// Inputs.
+	.I  (main_a7ddrphy_sd_clk_se_nodelay),
+
+	// Outputs.
+	.O  (ddram_clk_p),
+	.OB (ddram_clk_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_1 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_1 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_reset_n),
-	.D2(a7ddrphy_dfi_p0_reset_n),
-	.D3(a7ddrphy_dfi_p1_reset_n),
-	.D4(a7ddrphy_dfi_p1_reset_n),
-	.D5(a7ddrphy_dfi_p2_reset_n),
-	.D6(a7ddrphy_dfi_p2_reset_n),
-	.D7(a7ddrphy_dfi_p3_reset_n),
-	.D8(a7ddrphy_dfi_p3_reset_n),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_reset_n)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_reset_n),
+	.D2     (main_a7ddrphy_dfi_p0_reset_n),
+	.D3     (main_a7ddrphy_dfi_p1_reset_n),
+	.D4     (main_a7ddrphy_dfi_p1_reset_n),
+	.D5     (main_a7ddrphy_dfi_p2_reset_n),
+	.D6     (main_a7ddrphy_dfi_p2_reset_n),
+	.D7     (main_a7ddrphy_dfi_p3_reset_n),
+	.D8     (main_a7ddrphy_dfi_p3_reset_n),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_reset_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_2 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_2 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_cs_n),
-	.D2(a7ddrphy_dfi_p0_cs_n),
-	.D3(a7ddrphy_dfi_p1_cs_n),
-	.D4(a7ddrphy_dfi_p1_cs_n),
-	.D5(a7ddrphy_dfi_p2_cs_n),
-	.D6(a7ddrphy_dfi_p2_cs_n),
-	.D7(a7ddrphy_dfi_p3_cs_n),
-	.D8(a7ddrphy_dfi_p3_cs_n),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_cs_n)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_cs_n),
+	.D2     (main_a7ddrphy_dfi_p0_cs_n),
+	.D3     (main_a7ddrphy_dfi_p1_cs_n),
+	.D4     (main_a7ddrphy_dfi_p1_cs_n),
+	.D5     (main_a7ddrphy_dfi_p2_cs_n),
+	.D6     (main_a7ddrphy_dfi_p2_cs_n),
+	.D7     (main_a7ddrphy_dfi_p3_cs_n),
+	.D8     (main_a7ddrphy_dfi_p3_cs_n),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_cs_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_3 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_3 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[0]),
-	.D2(a7ddrphy_dfi_p0_address[0]),
-	.D3(a7ddrphy_dfi_p1_address[0]),
-	.D4(a7ddrphy_dfi_p1_address[0]),
-	.D5(a7ddrphy_dfi_p2_address[0]),
-	.D6(a7ddrphy_dfi_p2_address[0]),
-	.D7(a7ddrphy_dfi_p3_address[0]),
-	.D8(a7ddrphy_dfi_p3_address[0]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[0])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[0]),
+	.D2     (main_a7ddrphy_dfi_p0_address[0]),
+	.D3     (main_a7ddrphy_dfi_p1_address[0]),
+	.D4     (main_a7ddrphy_dfi_p1_address[0]),
+	.D5     (main_a7ddrphy_dfi_p2_address[0]),
+	.D6     (main_a7ddrphy_dfi_p2_address[0]),
+	.D7     (main_a7ddrphy_dfi_p3_address[0]),
+	.D8     (main_a7ddrphy_dfi_p3_address[0]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_4 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_4 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[1]),
-	.D2(a7ddrphy_dfi_p0_address[1]),
-	.D3(a7ddrphy_dfi_p1_address[1]),
-	.D4(a7ddrphy_dfi_p1_address[1]),
-	.D5(a7ddrphy_dfi_p2_address[1]),
-	.D6(a7ddrphy_dfi_p2_address[1]),
-	.D7(a7ddrphy_dfi_p3_address[1]),
-	.D8(a7ddrphy_dfi_p3_address[1]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[1])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[1]),
+	.D2     (main_a7ddrphy_dfi_p0_address[1]),
+	.D3     (main_a7ddrphy_dfi_p1_address[1]),
+	.D4     (main_a7ddrphy_dfi_p1_address[1]),
+	.D5     (main_a7ddrphy_dfi_p2_address[1]),
+	.D6     (main_a7ddrphy_dfi_p2_address[1]),
+	.D7     (main_a7ddrphy_dfi_p3_address[1]),
+	.D8     (main_a7ddrphy_dfi_p3_address[1]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[1])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_5 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_5 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[2]),
-	.D2(a7ddrphy_dfi_p0_address[2]),
-	.D3(a7ddrphy_dfi_p1_address[2]),
-	.D4(a7ddrphy_dfi_p1_address[2]),
-	.D5(a7ddrphy_dfi_p2_address[2]),
-	.D6(a7ddrphy_dfi_p2_address[2]),
-	.D7(a7ddrphy_dfi_p3_address[2]),
-	.D8(a7ddrphy_dfi_p3_address[2]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[2])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[2]),
+	.D2     (main_a7ddrphy_dfi_p0_address[2]),
+	.D3     (main_a7ddrphy_dfi_p1_address[2]),
+	.D4     (main_a7ddrphy_dfi_p1_address[2]),
+	.D5     (main_a7ddrphy_dfi_p2_address[2]),
+	.D6     (main_a7ddrphy_dfi_p2_address[2]),
+	.D7     (main_a7ddrphy_dfi_p3_address[2]),
+	.D8     (main_a7ddrphy_dfi_p3_address[2]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[2])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_6 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_6 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[3]),
-	.D2(a7ddrphy_dfi_p0_address[3]),
-	.D3(a7ddrphy_dfi_p1_address[3]),
-	.D4(a7ddrphy_dfi_p1_address[3]),
-	.D5(a7ddrphy_dfi_p2_address[3]),
-	.D6(a7ddrphy_dfi_p2_address[3]),
-	.D7(a7ddrphy_dfi_p3_address[3]),
-	.D8(a7ddrphy_dfi_p3_address[3]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[3])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[3]),
+	.D2     (main_a7ddrphy_dfi_p0_address[3]),
+	.D3     (main_a7ddrphy_dfi_p1_address[3]),
+	.D4     (main_a7ddrphy_dfi_p1_address[3]),
+	.D5     (main_a7ddrphy_dfi_p2_address[3]),
+	.D6     (main_a7ddrphy_dfi_p2_address[3]),
+	.D7     (main_a7ddrphy_dfi_p3_address[3]),
+	.D8     (main_a7ddrphy_dfi_p3_address[3]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_7 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_7 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[4]),
-	.D2(a7ddrphy_dfi_p0_address[4]),
-	.D3(a7ddrphy_dfi_p1_address[4]),
-	.D4(a7ddrphy_dfi_p1_address[4]),
-	.D5(a7ddrphy_dfi_p2_address[4]),
-	.D6(a7ddrphy_dfi_p2_address[4]),
-	.D7(a7ddrphy_dfi_p3_address[4]),
-	.D8(a7ddrphy_dfi_p3_address[4]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[4])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[4]),
+	.D2     (main_a7ddrphy_dfi_p0_address[4]),
+	.D3     (main_a7ddrphy_dfi_p1_address[4]),
+	.D4     (main_a7ddrphy_dfi_p1_address[4]),
+	.D5     (main_a7ddrphy_dfi_p2_address[4]),
+	.D6     (main_a7ddrphy_dfi_p2_address[4]),
+	.D7     (main_a7ddrphy_dfi_p3_address[4]),
+	.D8     (main_a7ddrphy_dfi_p3_address[4]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[4])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_8 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_8 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[5]),
-	.D2(a7ddrphy_dfi_p0_address[5]),
-	.D3(a7ddrphy_dfi_p1_address[5]),
-	.D4(a7ddrphy_dfi_p1_address[5]),
-	.D5(a7ddrphy_dfi_p2_address[5]),
-	.D6(a7ddrphy_dfi_p2_address[5]),
-	.D7(a7ddrphy_dfi_p3_address[5]),
-	.D8(a7ddrphy_dfi_p3_address[5]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[5])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[5]),
+	.D2     (main_a7ddrphy_dfi_p0_address[5]),
+	.D3     (main_a7ddrphy_dfi_p1_address[5]),
+	.D4     (main_a7ddrphy_dfi_p1_address[5]),
+	.D5     (main_a7ddrphy_dfi_p2_address[5]),
+	.D6     (main_a7ddrphy_dfi_p2_address[5]),
+	.D7     (main_a7ddrphy_dfi_p3_address[5]),
+	.D8     (main_a7ddrphy_dfi_p3_address[5]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[5])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_9 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_9 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[6]),
-	.D2(a7ddrphy_dfi_p0_address[6]),
-	.D3(a7ddrphy_dfi_p1_address[6]),
-	.D4(a7ddrphy_dfi_p1_address[6]),
-	.D5(a7ddrphy_dfi_p2_address[6]),
-	.D6(a7ddrphy_dfi_p2_address[6]),
-	.D7(a7ddrphy_dfi_p3_address[6]),
-	.D8(a7ddrphy_dfi_p3_address[6]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[6])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[6]),
+	.D2     (main_a7ddrphy_dfi_p0_address[6]),
+	.D3     (main_a7ddrphy_dfi_p1_address[6]),
+	.D4     (main_a7ddrphy_dfi_p1_address[6]),
+	.D5     (main_a7ddrphy_dfi_p2_address[6]),
+	.D6     (main_a7ddrphy_dfi_p2_address[6]),
+	.D7     (main_a7ddrphy_dfi_p3_address[6]),
+	.D8     (main_a7ddrphy_dfi_p3_address[6]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[6])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_10 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_10 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[7]),
-	.D2(a7ddrphy_dfi_p0_address[7]),
-	.D3(a7ddrphy_dfi_p1_address[7]),
-	.D4(a7ddrphy_dfi_p1_address[7]),
-	.D5(a7ddrphy_dfi_p2_address[7]),
-	.D6(a7ddrphy_dfi_p2_address[7]),
-	.D7(a7ddrphy_dfi_p3_address[7]),
-	.D8(a7ddrphy_dfi_p3_address[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[7])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[7]),
+	.D2     (main_a7ddrphy_dfi_p0_address[7]),
+	.D3     (main_a7ddrphy_dfi_p1_address[7]),
+	.D4     (main_a7ddrphy_dfi_p1_address[7]),
+	.D5     (main_a7ddrphy_dfi_p2_address[7]),
+	.D6     (main_a7ddrphy_dfi_p2_address[7]),
+	.D7     (main_a7ddrphy_dfi_p3_address[7]),
+	.D8     (main_a7ddrphy_dfi_p3_address[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[7])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_11 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_11 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[8]),
-	.D2(a7ddrphy_dfi_p0_address[8]),
-	.D3(a7ddrphy_dfi_p1_address[8]),
-	.D4(a7ddrphy_dfi_p1_address[8]),
-	.D5(a7ddrphy_dfi_p2_address[8]),
-	.D6(a7ddrphy_dfi_p2_address[8]),
-	.D7(a7ddrphy_dfi_p3_address[8]),
-	.D8(a7ddrphy_dfi_p3_address[8]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[8])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[8]),
+	.D2     (main_a7ddrphy_dfi_p0_address[8]),
+	.D3     (main_a7ddrphy_dfi_p1_address[8]),
+	.D4     (main_a7ddrphy_dfi_p1_address[8]),
+	.D5     (main_a7ddrphy_dfi_p2_address[8]),
+	.D6     (main_a7ddrphy_dfi_p2_address[8]),
+	.D7     (main_a7ddrphy_dfi_p3_address[8]),
+	.D8     (main_a7ddrphy_dfi_p3_address[8]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[8])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_12 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_12 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[9]),
-	.D2(a7ddrphy_dfi_p0_address[9]),
-	.D3(a7ddrphy_dfi_p1_address[9]),
-	.D4(a7ddrphy_dfi_p1_address[9]),
-	.D5(a7ddrphy_dfi_p2_address[9]),
-	.D6(a7ddrphy_dfi_p2_address[9]),
-	.D7(a7ddrphy_dfi_p3_address[9]),
-	.D8(a7ddrphy_dfi_p3_address[9]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[9])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[9]),
+	.D2     (main_a7ddrphy_dfi_p0_address[9]),
+	.D3     (main_a7ddrphy_dfi_p1_address[9]),
+	.D4     (main_a7ddrphy_dfi_p1_address[9]),
+	.D5     (main_a7ddrphy_dfi_p2_address[9]),
+	.D6     (main_a7ddrphy_dfi_p2_address[9]),
+	.D7     (main_a7ddrphy_dfi_p3_address[9]),
+	.D8     (main_a7ddrphy_dfi_p3_address[9]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[9])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_13 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_13 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[10]),
-	.D2(a7ddrphy_dfi_p0_address[10]),
-	.D3(a7ddrphy_dfi_p1_address[10]),
-	.D4(a7ddrphy_dfi_p1_address[10]),
-	.D5(a7ddrphy_dfi_p2_address[10]),
-	.D6(a7ddrphy_dfi_p2_address[10]),
-	.D7(a7ddrphy_dfi_p3_address[10]),
-	.D8(a7ddrphy_dfi_p3_address[10]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[10])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[10]),
+	.D2     (main_a7ddrphy_dfi_p0_address[10]),
+	.D3     (main_a7ddrphy_dfi_p1_address[10]),
+	.D4     (main_a7ddrphy_dfi_p1_address[10]),
+	.D5     (main_a7ddrphy_dfi_p2_address[10]),
+	.D6     (main_a7ddrphy_dfi_p2_address[10]),
+	.D7     (main_a7ddrphy_dfi_p3_address[10]),
+	.D8     (main_a7ddrphy_dfi_p3_address[10]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[10])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_14 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_14 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[11]),
-	.D2(a7ddrphy_dfi_p0_address[11]),
-	.D3(a7ddrphy_dfi_p1_address[11]),
-	.D4(a7ddrphy_dfi_p1_address[11]),
-	.D5(a7ddrphy_dfi_p2_address[11]),
-	.D6(a7ddrphy_dfi_p2_address[11]),
-	.D7(a7ddrphy_dfi_p3_address[11]),
-	.D8(a7ddrphy_dfi_p3_address[11]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[11])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[11]),
+	.D2     (main_a7ddrphy_dfi_p0_address[11]),
+	.D3     (main_a7ddrphy_dfi_p1_address[11]),
+	.D4     (main_a7ddrphy_dfi_p1_address[11]),
+	.D5     (main_a7ddrphy_dfi_p2_address[11]),
+	.D6     (main_a7ddrphy_dfi_p2_address[11]),
+	.D7     (main_a7ddrphy_dfi_p3_address[11]),
+	.D8     (main_a7ddrphy_dfi_p3_address[11]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[11])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_15 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_15 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[12]),
-	.D2(a7ddrphy_dfi_p0_address[12]),
-	.D3(a7ddrphy_dfi_p1_address[12]),
-	.D4(a7ddrphy_dfi_p1_address[12]),
-	.D5(a7ddrphy_dfi_p2_address[12]),
-	.D6(a7ddrphy_dfi_p2_address[12]),
-	.D7(a7ddrphy_dfi_p3_address[12]),
-	.D8(a7ddrphy_dfi_p3_address[12]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[12])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[12]),
+	.D2     (main_a7ddrphy_dfi_p0_address[12]),
+	.D3     (main_a7ddrphy_dfi_p1_address[12]),
+	.D4     (main_a7ddrphy_dfi_p1_address[12]),
+	.D5     (main_a7ddrphy_dfi_p2_address[12]),
+	.D6     (main_a7ddrphy_dfi_p2_address[12]),
+	.D7     (main_a7ddrphy_dfi_p3_address[12]),
+	.D8     (main_a7ddrphy_dfi_p3_address[12]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[12])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_16 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_16 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_address[13]),
-	.D2(a7ddrphy_dfi_p0_address[13]),
-	.D3(a7ddrphy_dfi_p1_address[13]),
-	.D4(a7ddrphy_dfi_p1_address[13]),
-	.D5(a7ddrphy_dfi_p2_address[13]),
-	.D6(a7ddrphy_dfi_p2_address[13]),
-	.D7(a7ddrphy_dfi_p3_address[13]),
-	.D8(a7ddrphy_dfi_p3_address[13]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_a[13])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_address[13]),
+	.D2     (main_a7ddrphy_dfi_p0_address[13]),
+	.D3     (main_a7ddrphy_dfi_p1_address[13]),
+	.D4     (main_a7ddrphy_dfi_p1_address[13]),
+	.D5     (main_a7ddrphy_dfi_p2_address[13]),
+	.D6     (main_a7ddrphy_dfi_p2_address[13]),
+	.D7     (main_a7ddrphy_dfi_p3_address[13]),
+	.D8     (main_a7ddrphy_dfi_p3_address[13]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_a[13])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_17 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_17 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_bank[0]),
-	.D2(a7ddrphy_dfi_p0_bank[0]),
-	.D3(a7ddrphy_dfi_p1_bank[0]),
-	.D4(a7ddrphy_dfi_p1_bank[0]),
-	.D5(a7ddrphy_dfi_p2_bank[0]),
-	.D6(a7ddrphy_dfi_p2_bank[0]),
-	.D7(a7ddrphy_dfi_p3_bank[0]),
-	.D8(a7ddrphy_dfi_p3_bank[0]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(a7ddrphy_pads_ba[0])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_bank[0]),
+	.D2     (main_a7ddrphy_dfi_p0_bank[0]),
+	.D3     (main_a7ddrphy_dfi_p1_bank[0]),
+	.D4     (main_a7ddrphy_dfi_p1_bank[0]),
+	.D5     (main_a7ddrphy_dfi_p2_bank[0]),
+	.D6     (main_a7ddrphy_dfi_p2_bank[0]),
+	.D7     (main_a7ddrphy_dfi_p3_bank[0]),
+	.D8     (main_a7ddrphy_dfi_p3_bank[0]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_pads_ba[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_18 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_18 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_bank[1]),
-	.D2(a7ddrphy_dfi_p0_bank[1]),
-	.D3(a7ddrphy_dfi_p1_bank[1]),
-	.D4(a7ddrphy_dfi_p1_bank[1]),
-	.D5(a7ddrphy_dfi_p2_bank[1]),
-	.D6(a7ddrphy_dfi_p2_bank[1]),
-	.D7(a7ddrphy_dfi_p3_bank[1]),
-	.D8(a7ddrphy_dfi_p3_bank[1]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(a7ddrphy_pads_ba[1])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_bank[1]),
+	.D2     (main_a7ddrphy_dfi_p0_bank[1]),
+	.D3     (main_a7ddrphy_dfi_p1_bank[1]),
+	.D4     (main_a7ddrphy_dfi_p1_bank[1]),
+	.D5     (main_a7ddrphy_dfi_p2_bank[1]),
+	.D6     (main_a7ddrphy_dfi_p2_bank[1]),
+	.D7     (main_a7ddrphy_dfi_p3_bank[1]),
+	.D8     (main_a7ddrphy_dfi_p3_bank[1]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_pads_ba[1])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_19 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_19 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_bank[2]),
-	.D2(a7ddrphy_dfi_p0_bank[2]),
-	.D3(a7ddrphy_dfi_p1_bank[2]),
-	.D4(a7ddrphy_dfi_p1_bank[2]),
-	.D5(a7ddrphy_dfi_p2_bank[2]),
-	.D6(a7ddrphy_dfi_p2_bank[2]),
-	.D7(a7ddrphy_dfi_p3_bank[2]),
-	.D8(a7ddrphy_dfi_p3_bank[2]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(a7ddrphy_pads_ba[2])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_bank[2]),
+	.D2     (main_a7ddrphy_dfi_p0_bank[2]),
+	.D3     (main_a7ddrphy_dfi_p1_bank[2]),
+	.D4     (main_a7ddrphy_dfi_p1_bank[2]),
+	.D5     (main_a7ddrphy_dfi_p2_bank[2]),
+	.D6     (main_a7ddrphy_dfi_p2_bank[2]),
+	.D7     (main_a7ddrphy_dfi_p3_bank[2]),
+	.D8     (main_a7ddrphy_dfi_p3_bank[2]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_pads_ba[2])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_20 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_20 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_ras_n),
-	.D2(a7ddrphy_dfi_p0_ras_n),
-	.D3(a7ddrphy_dfi_p1_ras_n),
-	.D4(a7ddrphy_dfi_p1_ras_n),
-	.D5(a7ddrphy_dfi_p2_ras_n),
-	.D6(a7ddrphy_dfi_p2_ras_n),
-	.D7(a7ddrphy_dfi_p3_ras_n),
-	.D8(a7ddrphy_dfi_p3_ras_n),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_ras_n)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_ras_n),
+	.D2     (main_a7ddrphy_dfi_p0_ras_n),
+	.D3     (main_a7ddrphy_dfi_p1_ras_n),
+	.D4     (main_a7ddrphy_dfi_p1_ras_n),
+	.D5     (main_a7ddrphy_dfi_p2_ras_n),
+	.D6     (main_a7ddrphy_dfi_p2_ras_n),
+	.D7     (main_a7ddrphy_dfi_p3_ras_n),
+	.D8     (main_a7ddrphy_dfi_p3_ras_n),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_ras_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_21 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_21 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_cas_n),
-	.D2(a7ddrphy_dfi_p0_cas_n),
-	.D3(a7ddrphy_dfi_p1_cas_n),
-	.D4(a7ddrphy_dfi_p1_cas_n),
-	.D5(a7ddrphy_dfi_p2_cas_n),
-	.D6(a7ddrphy_dfi_p2_cas_n),
-	.D7(a7ddrphy_dfi_p3_cas_n),
-	.D8(a7ddrphy_dfi_p3_cas_n),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_cas_n)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_cas_n),
+	.D2     (main_a7ddrphy_dfi_p0_cas_n),
+	.D3     (main_a7ddrphy_dfi_p1_cas_n),
+	.D4     (main_a7ddrphy_dfi_p1_cas_n),
+	.D5     (main_a7ddrphy_dfi_p2_cas_n),
+	.D6     (main_a7ddrphy_dfi_p2_cas_n),
+	.D7     (main_a7ddrphy_dfi_p3_cas_n),
+	.D8     (main_a7ddrphy_dfi_p3_cas_n),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_cas_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_22 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_22 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_we_n),
-	.D2(a7ddrphy_dfi_p0_we_n),
-	.D3(a7ddrphy_dfi_p1_we_n),
-	.D4(a7ddrphy_dfi_p1_we_n),
-	.D5(a7ddrphy_dfi_p2_we_n),
-	.D6(a7ddrphy_dfi_p2_we_n),
-	.D7(a7ddrphy_dfi_p3_we_n),
-	.D8(a7ddrphy_dfi_p3_we_n),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_we_n)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_we_n),
+	.D2     (main_a7ddrphy_dfi_p0_we_n),
+	.D3     (main_a7ddrphy_dfi_p1_we_n),
+	.D4     (main_a7ddrphy_dfi_p1_we_n),
+	.D5     (main_a7ddrphy_dfi_p2_we_n),
+	.D6     (main_a7ddrphy_dfi_p2_we_n),
+	.D7     (main_a7ddrphy_dfi_p3_we_n),
+	.D8     (main_a7ddrphy_dfi_p3_we_n),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_we_n)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_23 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_23 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_cke),
-	.D2(a7ddrphy_dfi_p0_cke),
-	.D3(a7ddrphy_dfi_p1_cke),
-	.D4(a7ddrphy_dfi_p1_cke),
-	.D5(a7ddrphy_dfi_p2_cke),
-	.D6(a7ddrphy_dfi_p2_cke),
-	.D7(a7ddrphy_dfi_p3_cke),
-	.D8(a7ddrphy_dfi_p3_cke),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_cke)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_cke),
+	.D2     (main_a7ddrphy_dfi_p0_cke),
+	.D3     (main_a7ddrphy_dfi_p1_cke),
+	.D4     (main_a7ddrphy_dfi_p1_cke),
+	.D5     (main_a7ddrphy_dfi_p2_cke),
+	.D6     (main_a7ddrphy_dfi_p2_cke),
+	.D7     (main_a7ddrphy_dfi_p3_cke),
+	.D8     (main_a7ddrphy_dfi_p3_cke),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_cke)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_24 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_24 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_dfi_p0_odt),
-	.D2(a7ddrphy_dfi_p0_odt),
-	.D3(a7ddrphy_dfi_p1_odt),
-	.D4(a7ddrphy_dfi_p1_odt),
-	.D5(a7ddrphy_dfi_p2_odt),
-	.D6(a7ddrphy_dfi_p2_odt),
-	.D7(a7ddrphy_dfi_p3_odt),
-	.D8(a7ddrphy_dfi_p3_odt),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_odt)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_dfi_p0_odt),
+	.D2     (main_a7ddrphy_dfi_p0_odt),
+	.D3     (main_a7ddrphy_dfi_p1_odt),
+	.D4     (main_a7ddrphy_dfi_p1_odt),
+	.D5     (main_a7ddrphy_dfi_p2_odt),
+	.D6     (main_a7ddrphy_dfi_p2_odt),
+	.D7     (main_a7ddrphy_dfi_p3_odt),
+	.D8     (main_a7ddrphy_dfi_p3_odt),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_odt)
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_25 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_25 (
-	.CLK(sys4x_dqs_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip00[0]),
-	.D2(a7ddrphy_bitslip00[1]),
-	.D3(a7ddrphy_bitslip00[2]),
-	.D4(a7ddrphy_bitslip00[3]),
-	.D5(a7ddrphy_bitslip00[4]),
-	.D6(a7ddrphy_bitslip00[5]),
-	.D7(a7ddrphy_bitslip00[6]),
-	.D8(a7ddrphy_bitslip00[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OFB(a7ddrphy0),
-	.OQ(a7ddrphy_dqs_o_no_delay0),
-	.TQ(a7ddrphy_dqs_t0)
+	// Inputs.
+	.CLK    (sys4x_dqs_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip00[0]),
+	.D2     (main_a7ddrphy_bitslip00[1]),
+	.D3     (main_a7ddrphy_bitslip00[2]),
+	.D4     (main_a7ddrphy_bitslip00[3]),
+	.D5     (main_a7ddrphy_bitslip00[4]),
+	.D6     (main_a7ddrphy_bitslip00[5]),
+	.D7     (main_a7ddrphy_bitslip00[6]),
+	.D8     (main_a7ddrphy_bitslip00[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OFB    (main_a7ddrphy0),
+	.OQ     (main_a7ddrphy_dqs_o_no_delay0),
+	.TQ     (main_a7ddrphy_dqs_t0)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUFDS of IOBUFDS Module.
+//------------------------------------------------------------------------------
 IOBUFDS IOBUFDS(
-	.I(a7ddrphy_dqs_o_no_delay0),
-	.T(a7ddrphy_dqs_t0),
-	.IO(ddram_dqs_p[0]),
-	.IOB(ddram_dqs_n[0])
+	// Inputs.
+	.I   (main_a7ddrphy_dqs_o_no_delay0),
+	.T   (main_a7ddrphy_dqs_t0),
+
+	// InOuts.
+	.IO  (ddram_dqs_p[0]),
+	.IOB (ddram_dqs_n[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_26 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_26 (
-	.CLK(sys4x_dqs_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip10[0]),
-	.D2(a7ddrphy_bitslip10[1]),
-	.D3(a7ddrphy_bitslip10[2]),
-	.D4(a7ddrphy_bitslip10[3]),
-	.D5(a7ddrphy_bitslip10[4]),
-	.D6(a7ddrphy_bitslip10[5]),
-	.D7(a7ddrphy_bitslip10[6]),
-	.D8(a7ddrphy_bitslip10[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OFB(a7ddrphy1),
-	.OQ(a7ddrphy_dqs_o_no_delay1),
-	.TQ(a7ddrphy_dqs_t1)
+	// Inputs.
+	.CLK    (sys4x_dqs_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip10[0]),
+	.D2     (main_a7ddrphy_bitslip10[1]),
+	.D3     (main_a7ddrphy_bitslip10[2]),
+	.D4     (main_a7ddrphy_bitslip10[3]),
+	.D5     (main_a7ddrphy_bitslip10[4]),
+	.D6     (main_a7ddrphy_bitslip10[5]),
+	.D7     (main_a7ddrphy_bitslip10[6]),
+	.D8     (main_a7ddrphy_bitslip10[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OFB    (main_a7ddrphy1),
+	.OQ     (main_a7ddrphy_dqs_o_no_delay1),
+	.TQ     (main_a7ddrphy_dqs_t1)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUFDS_1 of IOBUFDS Module.
+//------------------------------------------------------------------------------
 IOBUFDS IOBUFDS_1(
-	.I(a7ddrphy_dqs_o_no_delay1),
-	.T(a7ddrphy_dqs_t1),
-	.IO(ddram_dqs_p[1]),
-	.IOB(ddram_dqs_n[1])
+	// Inputs.
+	.I   (main_a7ddrphy_dqs_o_no_delay1),
+	.T   (main_a7ddrphy_dqs_t1),
+
+	// InOuts.
+	.IO  (ddram_dqs_p[1]),
+	.IOB (ddram_dqs_n[1])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_27 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_27 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip01[0]),
-	.D2(a7ddrphy_bitslip01[1]),
-	.D3(a7ddrphy_bitslip01[2]),
-	.D4(a7ddrphy_bitslip01[3]),
-	.D5(a7ddrphy_bitslip01[4]),
-	.D6(a7ddrphy_bitslip01[5]),
-	.D7(a7ddrphy_bitslip01[6]),
-	.D8(a7ddrphy_bitslip01[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_dm[0])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip01[0]),
+	.D2     (main_a7ddrphy_bitslip01[1]),
+	.D3     (main_a7ddrphy_bitslip01[2]),
+	.D4     (main_a7ddrphy_bitslip01[3]),
+	.D5     (main_a7ddrphy_bitslip01[4]),
+	.D6     (main_a7ddrphy_bitslip01[5]),
+	.D7     (main_a7ddrphy_bitslip01[6]),
+	.D8     (main_a7ddrphy_bitslip01[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_dm[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_28 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_28 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip11[0]),
-	.D2(a7ddrphy_bitslip11[1]),
-	.D3(a7ddrphy_bitslip11[2]),
-	.D4(a7ddrphy_bitslip11[3]),
-	.D5(a7ddrphy_bitslip11[4]),
-	.D6(a7ddrphy_bitslip11[5]),
-	.D7(a7ddrphy_bitslip11[6]),
-	.D8(a7ddrphy_bitslip11[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.OQ(ddram_dm[1])
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip11[0]),
+	.D2     (main_a7ddrphy_bitslip11[1]),
+	.D3     (main_a7ddrphy_bitslip11[2]),
+	.D4     (main_a7ddrphy_bitslip11[3]),
+	.D5     (main_a7ddrphy_bitslip11[4]),
+	.D6     (main_a7ddrphy_bitslip11[5]),
+	.D7     (main_a7ddrphy_bitslip11[6]),
+	.D8     (main_a7ddrphy_bitslip11[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.OQ     (ddram_dm[1])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_29 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_29 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip02[0]),
-	.D2(a7ddrphy_bitslip02[1]),
-	.D3(a7ddrphy_bitslip02[2]),
-	.D4(a7ddrphy_bitslip02[3]),
-	.D5(a7ddrphy_bitslip02[4]),
-	.D6(a7ddrphy_bitslip02[5]),
-	.D7(a7ddrphy_bitslip02[6]),
-	.D8(a7ddrphy_bitslip02[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay0),
-	.TQ(a7ddrphy_dq_t0)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip02[0]),
+	.D2     (main_a7ddrphy_bitslip02[1]),
+	.D3     (main_a7ddrphy_bitslip02[2]),
+	.D4     (main_a7ddrphy_bitslip02[3]),
+	.D5     (main_a7ddrphy_bitslip02[4]),
+	.D6     (main_a7ddrphy_bitslip02[5]),
+	.D7     (main_a7ddrphy_bitslip02[6]),
+	.D8     (main_a7ddrphy_bitslip02[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay0),
+	.TQ     (main_a7ddrphy_dq_t0)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed0),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip03[7]),
-	.Q2(a7ddrphy_bitslip03[6]),
-	.Q3(a7ddrphy_bitslip03[5]),
-	.Q4(a7ddrphy_bitslip03[4]),
-	.Q5(a7ddrphy_bitslip03[3]),
-	.Q6(a7ddrphy_bitslip03[2]),
-	.Q7(a7ddrphy_bitslip03[1]),
-	.Q8(a7ddrphy_bitslip03[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed0),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip03[7]),
+	.Q2      (main_a7ddrphy_bitslip03[6]),
+	.Q3      (main_a7ddrphy_bitslip03[5]),
+	.Q4      (main_a7ddrphy_bitslip03[4]),
+	.Q5      (main_a7ddrphy_bitslip03[3]),
+	.Q6      (main_a7ddrphy_bitslip03[2]),
+	.Q7      (main_a7ddrphy_bitslip03[1]),
+	.Q8      (main_a7ddrphy_bitslip03[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay0),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed0)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay0),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed0)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF(
-	.I(a7ddrphy_dq_o_nodelay0),
-	.T(a7ddrphy_dq_t0),
-	.IO(ddram_dq[0]),
-	.O(a7ddrphy_dq_i_nodelay0)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay0),
+	.T  (main_a7ddrphy_dq_t0),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay0),
+
+	// InOuts.
+	.IO (ddram_dq[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_30 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_30 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip12[0]),
-	.D2(a7ddrphy_bitslip12[1]),
-	.D3(a7ddrphy_bitslip12[2]),
-	.D4(a7ddrphy_bitslip12[3]),
-	.D5(a7ddrphy_bitslip12[4]),
-	.D6(a7ddrphy_bitslip12[5]),
-	.D7(a7ddrphy_bitslip12[6]),
-	.D8(a7ddrphy_bitslip12[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay1),
-	.TQ(a7ddrphy_dq_t1)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip12[0]),
+	.D2     (main_a7ddrphy_bitslip12[1]),
+	.D3     (main_a7ddrphy_bitslip12[2]),
+	.D4     (main_a7ddrphy_bitslip12[3]),
+	.D5     (main_a7ddrphy_bitslip12[4]),
+	.D6     (main_a7ddrphy_bitslip12[5]),
+	.D7     (main_a7ddrphy_bitslip12[6]),
+	.D8     (main_a7ddrphy_bitslip12[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay1),
+	.TQ     (main_a7ddrphy_dq_t1)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_1 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_1 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip13[7]),
-	.Q2(a7ddrphy_bitslip13[6]),
-	.Q3(a7ddrphy_bitslip13[5]),
-	.Q4(a7ddrphy_bitslip13[4]),
-	.Q5(a7ddrphy_bitslip13[3]),
-	.Q6(a7ddrphy_bitslip13[2]),
-	.Q7(a7ddrphy_bitslip13[1]),
-	.Q8(a7ddrphy_bitslip13[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed1),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip13[7]),
+	.Q2      (main_a7ddrphy_bitslip13[6]),
+	.Q3      (main_a7ddrphy_bitslip13[5]),
+	.Q4      (main_a7ddrphy_bitslip13[4]),
+	.Q5      (main_a7ddrphy_bitslip13[3]),
+	.Q6      (main_a7ddrphy_bitslip13[2]),
+	.Q7      (main_a7ddrphy_bitslip13[1]),
+	.Q8      (main_a7ddrphy_bitslip13[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_1 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_1 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay1),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed1)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay1),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed1)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_1 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_1(
-	.I(a7ddrphy_dq_o_nodelay1),
-	.T(a7ddrphy_dq_t1),
-	.IO(ddram_dq[1]),
-	.O(a7ddrphy_dq_i_nodelay1)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay1),
+	.T  (main_a7ddrphy_dq_t1),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay1),
+
+	// InOuts.
+	.IO (ddram_dq[1])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_31 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_31 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip20[0]),
-	.D2(a7ddrphy_bitslip20[1]),
-	.D3(a7ddrphy_bitslip20[2]),
-	.D4(a7ddrphy_bitslip20[3]),
-	.D5(a7ddrphy_bitslip20[4]),
-	.D6(a7ddrphy_bitslip20[5]),
-	.D7(a7ddrphy_bitslip20[6]),
-	.D8(a7ddrphy_bitslip20[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay2),
-	.TQ(a7ddrphy_dq_t2)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip20[0]),
+	.D2     (main_a7ddrphy_bitslip20[1]),
+	.D3     (main_a7ddrphy_bitslip20[2]),
+	.D4     (main_a7ddrphy_bitslip20[3]),
+	.D5     (main_a7ddrphy_bitslip20[4]),
+	.D6     (main_a7ddrphy_bitslip20[5]),
+	.D7     (main_a7ddrphy_bitslip20[6]),
+	.D8     (main_a7ddrphy_bitslip20[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay2),
+	.TQ     (main_a7ddrphy_dq_t2)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_2 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_2 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed2),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip21[7]),
-	.Q2(a7ddrphy_bitslip21[6]),
-	.Q3(a7ddrphy_bitslip21[5]),
-	.Q4(a7ddrphy_bitslip21[4]),
-	.Q5(a7ddrphy_bitslip21[3]),
-	.Q6(a7ddrphy_bitslip21[2]),
-	.Q7(a7ddrphy_bitslip21[1]),
-	.Q8(a7ddrphy_bitslip21[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed2),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip21[7]),
+	.Q2      (main_a7ddrphy_bitslip21[6]),
+	.Q3      (main_a7ddrphy_bitslip21[5]),
+	.Q4      (main_a7ddrphy_bitslip21[4]),
+	.Q5      (main_a7ddrphy_bitslip21[3]),
+	.Q6      (main_a7ddrphy_bitslip21[2]),
+	.Q7      (main_a7ddrphy_bitslip21[1]),
+	.Q8      (main_a7ddrphy_bitslip21[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_2 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_2 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay2),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed2)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay2),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed2)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_2 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_2(
-	.I(a7ddrphy_dq_o_nodelay2),
-	.T(a7ddrphy_dq_t2),
-	.IO(ddram_dq[2]),
-	.O(a7ddrphy_dq_i_nodelay2)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay2),
+	.T  (main_a7ddrphy_dq_t2),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay2),
+
+	// InOuts.
+	.IO (ddram_dq[2])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_32 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_32 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip30[0]),
-	.D2(a7ddrphy_bitslip30[1]),
-	.D3(a7ddrphy_bitslip30[2]),
-	.D4(a7ddrphy_bitslip30[3]),
-	.D5(a7ddrphy_bitslip30[4]),
-	.D6(a7ddrphy_bitslip30[5]),
-	.D7(a7ddrphy_bitslip30[6]),
-	.D8(a7ddrphy_bitslip30[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay3),
-	.TQ(a7ddrphy_dq_t3)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip30[0]),
+	.D2     (main_a7ddrphy_bitslip30[1]),
+	.D3     (main_a7ddrphy_bitslip30[2]),
+	.D4     (main_a7ddrphy_bitslip30[3]),
+	.D5     (main_a7ddrphy_bitslip30[4]),
+	.D6     (main_a7ddrphy_bitslip30[5]),
+	.D7     (main_a7ddrphy_bitslip30[6]),
+	.D8     (main_a7ddrphy_bitslip30[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay3),
+	.TQ     (main_a7ddrphy_dq_t3)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_3 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_3 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed3),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip31[7]),
-	.Q2(a7ddrphy_bitslip31[6]),
-	.Q3(a7ddrphy_bitslip31[5]),
-	.Q4(a7ddrphy_bitslip31[4]),
-	.Q5(a7ddrphy_bitslip31[3]),
-	.Q6(a7ddrphy_bitslip31[2]),
-	.Q7(a7ddrphy_bitslip31[1]),
-	.Q8(a7ddrphy_bitslip31[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed3),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip31[7]),
+	.Q2      (main_a7ddrphy_bitslip31[6]),
+	.Q3      (main_a7ddrphy_bitslip31[5]),
+	.Q4      (main_a7ddrphy_bitslip31[4]),
+	.Q5      (main_a7ddrphy_bitslip31[3]),
+	.Q6      (main_a7ddrphy_bitslip31[2]),
+	.Q7      (main_a7ddrphy_bitslip31[1]),
+	.Q8      (main_a7ddrphy_bitslip31[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_3 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_3 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay3),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed3)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay3),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed3)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_3 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_3(
-	.I(a7ddrphy_dq_o_nodelay3),
-	.T(a7ddrphy_dq_t3),
-	.IO(ddram_dq[3]),
-	.O(a7ddrphy_dq_i_nodelay3)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay3),
+	.T  (main_a7ddrphy_dq_t3),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay3),
+
+	// InOuts.
+	.IO (ddram_dq[3])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_33 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_33 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip40[0]),
-	.D2(a7ddrphy_bitslip40[1]),
-	.D3(a7ddrphy_bitslip40[2]),
-	.D4(a7ddrphy_bitslip40[3]),
-	.D5(a7ddrphy_bitslip40[4]),
-	.D6(a7ddrphy_bitslip40[5]),
-	.D7(a7ddrphy_bitslip40[6]),
-	.D8(a7ddrphy_bitslip40[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay4),
-	.TQ(a7ddrphy_dq_t4)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip40[0]),
+	.D2     (main_a7ddrphy_bitslip40[1]),
+	.D3     (main_a7ddrphy_bitslip40[2]),
+	.D4     (main_a7ddrphy_bitslip40[3]),
+	.D5     (main_a7ddrphy_bitslip40[4]),
+	.D6     (main_a7ddrphy_bitslip40[5]),
+	.D7     (main_a7ddrphy_bitslip40[6]),
+	.D8     (main_a7ddrphy_bitslip40[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay4),
+	.TQ     (main_a7ddrphy_dq_t4)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_4 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_4 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed4),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip41[7]),
-	.Q2(a7ddrphy_bitslip41[6]),
-	.Q3(a7ddrphy_bitslip41[5]),
-	.Q4(a7ddrphy_bitslip41[4]),
-	.Q5(a7ddrphy_bitslip41[3]),
-	.Q6(a7ddrphy_bitslip41[2]),
-	.Q7(a7ddrphy_bitslip41[1]),
-	.Q8(a7ddrphy_bitslip41[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed4),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip41[7]),
+	.Q2      (main_a7ddrphy_bitslip41[6]),
+	.Q3      (main_a7ddrphy_bitslip41[5]),
+	.Q4      (main_a7ddrphy_bitslip41[4]),
+	.Q5      (main_a7ddrphy_bitslip41[3]),
+	.Q6      (main_a7ddrphy_bitslip41[2]),
+	.Q7      (main_a7ddrphy_bitslip41[1]),
+	.Q8      (main_a7ddrphy_bitslip41[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_4 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_4 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay4),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed4)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay4),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed4)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_4 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_4(
-	.I(a7ddrphy_dq_o_nodelay4),
-	.T(a7ddrphy_dq_t4),
-	.IO(ddram_dq[4]),
-	.O(a7ddrphy_dq_i_nodelay4)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay4),
+	.T  (main_a7ddrphy_dq_t4),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay4),
+
+	// InOuts.
+	.IO (ddram_dq[4])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_34 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_34 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip50[0]),
-	.D2(a7ddrphy_bitslip50[1]),
-	.D3(a7ddrphy_bitslip50[2]),
-	.D4(a7ddrphy_bitslip50[3]),
-	.D5(a7ddrphy_bitslip50[4]),
-	.D6(a7ddrphy_bitslip50[5]),
-	.D7(a7ddrphy_bitslip50[6]),
-	.D8(a7ddrphy_bitslip50[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay5),
-	.TQ(a7ddrphy_dq_t5)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip50[0]),
+	.D2     (main_a7ddrphy_bitslip50[1]),
+	.D3     (main_a7ddrphy_bitslip50[2]),
+	.D4     (main_a7ddrphy_bitslip50[3]),
+	.D5     (main_a7ddrphy_bitslip50[4]),
+	.D6     (main_a7ddrphy_bitslip50[5]),
+	.D7     (main_a7ddrphy_bitslip50[6]),
+	.D8     (main_a7ddrphy_bitslip50[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay5),
+	.TQ     (main_a7ddrphy_dq_t5)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_5 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_5 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed5),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip51[7]),
-	.Q2(a7ddrphy_bitslip51[6]),
-	.Q3(a7ddrphy_bitslip51[5]),
-	.Q4(a7ddrphy_bitslip51[4]),
-	.Q5(a7ddrphy_bitslip51[3]),
-	.Q6(a7ddrphy_bitslip51[2]),
-	.Q7(a7ddrphy_bitslip51[1]),
-	.Q8(a7ddrphy_bitslip51[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed5),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip51[7]),
+	.Q2      (main_a7ddrphy_bitslip51[6]),
+	.Q3      (main_a7ddrphy_bitslip51[5]),
+	.Q4      (main_a7ddrphy_bitslip51[4]),
+	.Q5      (main_a7ddrphy_bitslip51[3]),
+	.Q6      (main_a7ddrphy_bitslip51[2]),
+	.Q7      (main_a7ddrphy_bitslip51[1]),
+	.Q8      (main_a7ddrphy_bitslip51[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_5 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_5 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay5),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed5)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay5),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed5)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_5 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_5(
-	.I(a7ddrphy_dq_o_nodelay5),
-	.T(a7ddrphy_dq_t5),
-	.IO(ddram_dq[5]),
-	.O(a7ddrphy_dq_i_nodelay5)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay5),
+	.T  (main_a7ddrphy_dq_t5),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay5),
+
+	// InOuts.
+	.IO (ddram_dq[5])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_35 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_35 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip60[0]),
-	.D2(a7ddrphy_bitslip60[1]),
-	.D3(a7ddrphy_bitslip60[2]),
-	.D4(a7ddrphy_bitslip60[3]),
-	.D5(a7ddrphy_bitslip60[4]),
-	.D6(a7ddrphy_bitslip60[5]),
-	.D7(a7ddrphy_bitslip60[6]),
-	.D8(a7ddrphy_bitslip60[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay6),
-	.TQ(a7ddrphy_dq_t6)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip60[0]),
+	.D2     (main_a7ddrphy_bitslip60[1]),
+	.D3     (main_a7ddrphy_bitslip60[2]),
+	.D4     (main_a7ddrphy_bitslip60[3]),
+	.D5     (main_a7ddrphy_bitslip60[4]),
+	.D6     (main_a7ddrphy_bitslip60[5]),
+	.D7     (main_a7ddrphy_bitslip60[6]),
+	.D8     (main_a7ddrphy_bitslip60[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay6),
+	.TQ     (main_a7ddrphy_dq_t6)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_6 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_6 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed6),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip61[7]),
-	.Q2(a7ddrphy_bitslip61[6]),
-	.Q3(a7ddrphy_bitslip61[5]),
-	.Q4(a7ddrphy_bitslip61[4]),
-	.Q5(a7ddrphy_bitslip61[3]),
-	.Q6(a7ddrphy_bitslip61[2]),
-	.Q7(a7ddrphy_bitslip61[1]),
-	.Q8(a7ddrphy_bitslip61[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed6),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip61[7]),
+	.Q2      (main_a7ddrphy_bitslip61[6]),
+	.Q3      (main_a7ddrphy_bitslip61[5]),
+	.Q4      (main_a7ddrphy_bitslip61[4]),
+	.Q5      (main_a7ddrphy_bitslip61[3]),
+	.Q6      (main_a7ddrphy_bitslip61[2]),
+	.Q7      (main_a7ddrphy_bitslip61[1]),
+	.Q8      (main_a7ddrphy_bitslip61[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_6 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_6 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay6),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed6)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay6),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed6)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_6 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_6(
-	.I(a7ddrphy_dq_o_nodelay6),
-	.T(a7ddrphy_dq_t6),
-	.IO(ddram_dq[6]),
-	.O(a7ddrphy_dq_i_nodelay6)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay6),
+	.T  (main_a7ddrphy_dq_t6),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay6),
+
+	// InOuts.
+	.IO (ddram_dq[6])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_36 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_36 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip70[0]),
-	.D2(a7ddrphy_bitslip70[1]),
-	.D3(a7ddrphy_bitslip70[2]),
-	.D4(a7ddrphy_bitslip70[3]),
-	.D5(a7ddrphy_bitslip70[4]),
-	.D6(a7ddrphy_bitslip70[5]),
-	.D7(a7ddrphy_bitslip70[6]),
-	.D8(a7ddrphy_bitslip70[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay7),
-	.TQ(a7ddrphy_dq_t7)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip70[0]),
+	.D2     (main_a7ddrphy_bitslip70[1]),
+	.D3     (main_a7ddrphy_bitslip70[2]),
+	.D4     (main_a7ddrphy_bitslip70[3]),
+	.D5     (main_a7ddrphy_bitslip70[4]),
+	.D6     (main_a7ddrphy_bitslip70[5]),
+	.D7     (main_a7ddrphy_bitslip70[6]),
+	.D8     (main_a7ddrphy_bitslip70[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay7),
+	.TQ     (main_a7ddrphy_dq_t7)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_7 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_7 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed7),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip71[7]),
-	.Q2(a7ddrphy_bitslip71[6]),
-	.Q3(a7ddrphy_bitslip71[5]),
-	.Q4(a7ddrphy_bitslip71[4]),
-	.Q5(a7ddrphy_bitslip71[3]),
-	.Q6(a7ddrphy_bitslip71[2]),
-	.Q7(a7ddrphy_bitslip71[1]),
-	.Q8(a7ddrphy_bitslip71[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed7),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip71[7]),
+	.Q2      (main_a7ddrphy_bitslip71[6]),
+	.Q3      (main_a7ddrphy_bitslip71[5]),
+	.Q4      (main_a7ddrphy_bitslip71[4]),
+	.Q5      (main_a7ddrphy_bitslip71[3]),
+	.Q6      (main_a7ddrphy_bitslip71[2]),
+	.Q7      (main_a7ddrphy_bitslip71[1]),
+	.Q8      (main_a7ddrphy_bitslip71[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_7 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_7 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay7),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed7)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay7),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed7)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_7 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_7(
-	.I(a7ddrphy_dq_o_nodelay7),
-	.T(a7ddrphy_dq_t7),
-	.IO(ddram_dq[7]),
-	.O(a7ddrphy_dq_i_nodelay7)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay7),
+	.T  (main_a7ddrphy_dq_t7),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay7),
+
+	// InOuts.
+	.IO (ddram_dq[7])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_37 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_37 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip80[0]),
-	.D2(a7ddrphy_bitslip80[1]),
-	.D3(a7ddrphy_bitslip80[2]),
-	.D4(a7ddrphy_bitslip80[3]),
-	.D5(a7ddrphy_bitslip80[4]),
-	.D6(a7ddrphy_bitslip80[5]),
-	.D7(a7ddrphy_bitslip80[6]),
-	.D8(a7ddrphy_bitslip80[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay8),
-	.TQ(a7ddrphy_dq_t8)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip80[0]),
+	.D2     (main_a7ddrphy_bitslip80[1]),
+	.D3     (main_a7ddrphy_bitslip80[2]),
+	.D4     (main_a7ddrphy_bitslip80[3]),
+	.D5     (main_a7ddrphy_bitslip80[4]),
+	.D6     (main_a7ddrphy_bitslip80[5]),
+	.D7     (main_a7ddrphy_bitslip80[6]),
+	.D8     (main_a7ddrphy_bitslip80[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay8),
+	.TQ     (main_a7ddrphy_dq_t8)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_8 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_8 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed8),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip81[7]),
-	.Q2(a7ddrphy_bitslip81[6]),
-	.Q3(a7ddrphy_bitslip81[5]),
-	.Q4(a7ddrphy_bitslip81[4]),
-	.Q5(a7ddrphy_bitslip81[3]),
-	.Q6(a7ddrphy_bitslip81[2]),
-	.Q7(a7ddrphy_bitslip81[1]),
-	.Q8(a7ddrphy_bitslip81[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed8),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip81[7]),
+	.Q2      (main_a7ddrphy_bitslip81[6]),
+	.Q3      (main_a7ddrphy_bitslip81[5]),
+	.Q4      (main_a7ddrphy_bitslip81[4]),
+	.Q5      (main_a7ddrphy_bitslip81[3]),
+	.Q6      (main_a7ddrphy_bitslip81[2]),
+	.Q7      (main_a7ddrphy_bitslip81[1]),
+	.Q8      (main_a7ddrphy_bitslip81[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_8 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_8 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay8),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed8)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay8),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed8)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_8 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_8(
-	.I(a7ddrphy_dq_o_nodelay8),
-	.T(a7ddrphy_dq_t8),
-	.IO(ddram_dq[8]),
-	.O(a7ddrphy_dq_i_nodelay8)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay8),
+	.T  (main_a7ddrphy_dq_t8),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay8),
+
+	// InOuts.
+	.IO (ddram_dq[8])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_38 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_38 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip90[0]),
-	.D2(a7ddrphy_bitslip90[1]),
-	.D3(a7ddrphy_bitslip90[2]),
-	.D4(a7ddrphy_bitslip90[3]),
-	.D5(a7ddrphy_bitslip90[4]),
-	.D6(a7ddrphy_bitslip90[5]),
-	.D7(a7ddrphy_bitslip90[6]),
-	.D8(a7ddrphy_bitslip90[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay9),
-	.TQ(a7ddrphy_dq_t9)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip90[0]),
+	.D2     (main_a7ddrphy_bitslip90[1]),
+	.D3     (main_a7ddrphy_bitslip90[2]),
+	.D4     (main_a7ddrphy_bitslip90[3]),
+	.D5     (main_a7ddrphy_bitslip90[4]),
+	.D6     (main_a7ddrphy_bitslip90[5]),
+	.D7     (main_a7ddrphy_bitslip90[6]),
+	.D8     (main_a7ddrphy_bitslip90[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay9),
+	.TQ     (main_a7ddrphy_dq_t9)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_9 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_9 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed9),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip91[7]),
-	.Q2(a7ddrphy_bitslip91[6]),
-	.Q3(a7ddrphy_bitslip91[5]),
-	.Q4(a7ddrphy_bitslip91[4]),
-	.Q5(a7ddrphy_bitslip91[3]),
-	.Q6(a7ddrphy_bitslip91[2]),
-	.Q7(a7ddrphy_bitslip91[1]),
-	.Q8(a7ddrphy_bitslip91[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed9),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip91[7]),
+	.Q2      (main_a7ddrphy_bitslip91[6]),
+	.Q3      (main_a7ddrphy_bitslip91[5]),
+	.Q4      (main_a7ddrphy_bitslip91[4]),
+	.Q5      (main_a7ddrphy_bitslip91[3]),
+	.Q6      (main_a7ddrphy_bitslip91[2]),
+	.Q7      (main_a7ddrphy_bitslip91[1]),
+	.Q8      (main_a7ddrphy_bitslip91[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_9 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_9 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay9),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed9)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay9),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed9)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_9 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_9(
-	.I(a7ddrphy_dq_o_nodelay9),
-	.T(a7ddrphy_dq_t9),
-	.IO(ddram_dq[9]),
-	.O(a7ddrphy_dq_i_nodelay9)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay9),
+	.T  (main_a7ddrphy_dq_t9),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay9),
+
+	// InOuts.
+	.IO (ddram_dq[9])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_39 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_39 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip100[0]),
-	.D2(a7ddrphy_bitslip100[1]),
-	.D3(a7ddrphy_bitslip100[2]),
-	.D4(a7ddrphy_bitslip100[3]),
-	.D5(a7ddrphy_bitslip100[4]),
-	.D6(a7ddrphy_bitslip100[5]),
-	.D7(a7ddrphy_bitslip100[6]),
-	.D8(a7ddrphy_bitslip100[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay10),
-	.TQ(a7ddrphy_dq_t10)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip100[0]),
+	.D2     (main_a7ddrphy_bitslip100[1]),
+	.D3     (main_a7ddrphy_bitslip100[2]),
+	.D4     (main_a7ddrphy_bitslip100[3]),
+	.D5     (main_a7ddrphy_bitslip100[4]),
+	.D6     (main_a7ddrphy_bitslip100[5]),
+	.D7     (main_a7ddrphy_bitslip100[6]),
+	.D8     (main_a7ddrphy_bitslip100[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay10),
+	.TQ     (main_a7ddrphy_dq_t10)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_10 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_10 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed10),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip101[7]),
-	.Q2(a7ddrphy_bitslip101[6]),
-	.Q3(a7ddrphy_bitslip101[5]),
-	.Q4(a7ddrphy_bitslip101[4]),
-	.Q5(a7ddrphy_bitslip101[3]),
-	.Q6(a7ddrphy_bitslip101[2]),
-	.Q7(a7ddrphy_bitslip101[1]),
-	.Q8(a7ddrphy_bitslip101[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed10),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip101[7]),
+	.Q2      (main_a7ddrphy_bitslip101[6]),
+	.Q3      (main_a7ddrphy_bitslip101[5]),
+	.Q4      (main_a7ddrphy_bitslip101[4]),
+	.Q5      (main_a7ddrphy_bitslip101[3]),
+	.Q6      (main_a7ddrphy_bitslip101[2]),
+	.Q7      (main_a7ddrphy_bitslip101[1]),
+	.Q8      (main_a7ddrphy_bitslip101[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_10 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_10 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay10),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed10)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay10),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed10)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_10 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_10(
-	.I(a7ddrphy_dq_o_nodelay10),
-	.T(a7ddrphy_dq_t10),
-	.IO(ddram_dq[10]),
-	.O(a7ddrphy_dq_i_nodelay10)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay10),
+	.T  (main_a7ddrphy_dq_t10),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay10),
+
+	// InOuts.
+	.IO (ddram_dq[10])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_40 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_40 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip110[0]),
-	.D2(a7ddrphy_bitslip110[1]),
-	.D3(a7ddrphy_bitslip110[2]),
-	.D4(a7ddrphy_bitslip110[3]),
-	.D5(a7ddrphy_bitslip110[4]),
-	.D6(a7ddrphy_bitslip110[5]),
-	.D7(a7ddrphy_bitslip110[6]),
-	.D8(a7ddrphy_bitslip110[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay11),
-	.TQ(a7ddrphy_dq_t11)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip110[0]),
+	.D2     (main_a7ddrphy_bitslip110[1]),
+	.D3     (main_a7ddrphy_bitslip110[2]),
+	.D4     (main_a7ddrphy_bitslip110[3]),
+	.D5     (main_a7ddrphy_bitslip110[4]),
+	.D6     (main_a7ddrphy_bitslip110[5]),
+	.D7     (main_a7ddrphy_bitslip110[6]),
+	.D8     (main_a7ddrphy_bitslip110[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay11),
+	.TQ     (main_a7ddrphy_dq_t11)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_11 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_11 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed11),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip111[7]),
-	.Q2(a7ddrphy_bitslip111[6]),
-	.Q3(a7ddrphy_bitslip111[5]),
-	.Q4(a7ddrphy_bitslip111[4]),
-	.Q5(a7ddrphy_bitslip111[3]),
-	.Q6(a7ddrphy_bitslip111[2]),
-	.Q7(a7ddrphy_bitslip111[1]),
-	.Q8(a7ddrphy_bitslip111[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed11),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip111[7]),
+	.Q2      (main_a7ddrphy_bitslip111[6]),
+	.Q3      (main_a7ddrphy_bitslip111[5]),
+	.Q4      (main_a7ddrphy_bitslip111[4]),
+	.Q5      (main_a7ddrphy_bitslip111[3]),
+	.Q6      (main_a7ddrphy_bitslip111[2]),
+	.Q7      (main_a7ddrphy_bitslip111[1]),
+	.Q8      (main_a7ddrphy_bitslip111[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_11 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_11 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay11),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed11)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay11),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed11)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_11 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_11(
-	.I(a7ddrphy_dq_o_nodelay11),
-	.T(a7ddrphy_dq_t11),
-	.IO(ddram_dq[11]),
-	.O(a7ddrphy_dq_i_nodelay11)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay11),
+	.T  (main_a7ddrphy_dq_t11),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay11),
+
+	// InOuts.
+	.IO (ddram_dq[11])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_41 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_41 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip120[0]),
-	.D2(a7ddrphy_bitslip120[1]),
-	.D3(a7ddrphy_bitslip120[2]),
-	.D4(a7ddrphy_bitslip120[3]),
-	.D5(a7ddrphy_bitslip120[4]),
-	.D6(a7ddrphy_bitslip120[5]),
-	.D7(a7ddrphy_bitslip120[6]),
-	.D8(a7ddrphy_bitslip120[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay12),
-	.TQ(a7ddrphy_dq_t12)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip120[0]),
+	.D2     (main_a7ddrphy_bitslip120[1]),
+	.D3     (main_a7ddrphy_bitslip120[2]),
+	.D4     (main_a7ddrphy_bitslip120[3]),
+	.D5     (main_a7ddrphy_bitslip120[4]),
+	.D6     (main_a7ddrphy_bitslip120[5]),
+	.D7     (main_a7ddrphy_bitslip120[6]),
+	.D8     (main_a7ddrphy_bitslip120[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay12),
+	.TQ     (main_a7ddrphy_dq_t12)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_12 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_12 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed12),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip121[7]),
-	.Q2(a7ddrphy_bitslip121[6]),
-	.Q3(a7ddrphy_bitslip121[5]),
-	.Q4(a7ddrphy_bitslip121[4]),
-	.Q5(a7ddrphy_bitslip121[3]),
-	.Q6(a7ddrphy_bitslip121[2]),
-	.Q7(a7ddrphy_bitslip121[1]),
-	.Q8(a7ddrphy_bitslip121[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed12),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip121[7]),
+	.Q2      (main_a7ddrphy_bitslip121[6]),
+	.Q3      (main_a7ddrphy_bitslip121[5]),
+	.Q4      (main_a7ddrphy_bitslip121[4]),
+	.Q5      (main_a7ddrphy_bitslip121[3]),
+	.Q6      (main_a7ddrphy_bitslip121[2]),
+	.Q7      (main_a7ddrphy_bitslip121[1]),
+	.Q8      (main_a7ddrphy_bitslip121[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_12 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_12 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay12),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed12)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay12),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed12)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_12 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_12(
-	.I(a7ddrphy_dq_o_nodelay12),
-	.T(a7ddrphy_dq_t12),
-	.IO(ddram_dq[12]),
-	.O(a7ddrphy_dq_i_nodelay12)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay12),
+	.T  (main_a7ddrphy_dq_t12),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay12),
+
+	// InOuts.
+	.IO (ddram_dq[12])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_42 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_42 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip130[0]),
-	.D2(a7ddrphy_bitslip130[1]),
-	.D3(a7ddrphy_bitslip130[2]),
-	.D4(a7ddrphy_bitslip130[3]),
-	.D5(a7ddrphy_bitslip130[4]),
-	.D6(a7ddrphy_bitslip130[5]),
-	.D7(a7ddrphy_bitslip130[6]),
-	.D8(a7ddrphy_bitslip130[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay13),
-	.TQ(a7ddrphy_dq_t13)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip130[0]),
+	.D2     (main_a7ddrphy_bitslip130[1]),
+	.D3     (main_a7ddrphy_bitslip130[2]),
+	.D4     (main_a7ddrphy_bitslip130[3]),
+	.D5     (main_a7ddrphy_bitslip130[4]),
+	.D6     (main_a7ddrphy_bitslip130[5]),
+	.D7     (main_a7ddrphy_bitslip130[6]),
+	.D8     (main_a7ddrphy_bitslip130[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay13),
+	.TQ     (main_a7ddrphy_dq_t13)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_13 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_13 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed13),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip131[7]),
-	.Q2(a7ddrphy_bitslip131[6]),
-	.Q3(a7ddrphy_bitslip131[5]),
-	.Q4(a7ddrphy_bitslip131[4]),
-	.Q5(a7ddrphy_bitslip131[3]),
-	.Q6(a7ddrphy_bitslip131[2]),
-	.Q7(a7ddrphy_bitslip131[1]),
-	.Q8(a7ddrphy_bitslip131[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed13),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip131[7]),
+	.Q2      (main_a7ddrphy_bitslip131[6]),
+	.Q3      (main_a7ddrphy_bitslip131[5]),
+	.Q4      (main_a7ddrphy_bitslip131[4]),
+	.Q5      (main_a7ddrphy_bitslip131[3]),
+	.Q6      (main_a7ddrphy_bitslip131[2]),
+	.Q7      (main_a7ddrphy_bitslip131[1]),
+	.Q8      (main_a7ddrphy_bitslip131[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_13 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_13 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay13),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed13)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay13),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed13)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_13 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_13(
-	.I(a7ddrphy_dq_o_nodelay13),
-	.T(a7ddrphy_dq_t13),
-	.IO(ddram_dq[13]),
-	.O(a7ddrphy_dq_i_nodelay13)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay13),
+	.T  (main_a7ddrphy_dq_t13),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay13),
+
+	// InOuts.
+	.IO (ddram_dq[13])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_43 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_43 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip140[0]),
-	.D2(a7ddrphy_bitslip140[1]),
-	.D3(a7ddrphy_bitslip140[2]),
-	.D4(a7ddrphy_bitslip140[3]),
-	.D5(a7ddrphy_bitslip140[4]),
-	.D6(a7ddrphy_bitslip140[5]),
-	.D7(a7ddrphy_bitslip140[6]),
-	.D8(a7ddrphy_bitslip140[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay14),
-	.TQ(a7ddrphy_dq_t14)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip140[0]),
+	.D2     (main_a7ddrphy_bitslip140[1]),
+	.D3     (main_a7ddrphy_bitslip140[2]),
+	.D4     (main_a7ddrphy_bitslip140[3]),
+	.D5     (main_a7ddrphy_bitslip140[4]),
+	.D6     (main_a7ddrphy_bitslip140[5]),
+	.D7     (main_a7ddrphy_bitslip140[6]),
+	.D8     (main_a7ddrphy_bitslip140[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay14),
+	.TQ     (main_a7ddrphy_dq_t14)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_14 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_14 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed14),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip141[7]),
-	.Q2(a7ddrphy_bitslip141[6]),
-	.Q3(a7ddrphy_bitslip141[5]),
-	.Q4(a7ddrphy_bitslip141[4]),
-	.Q5(a7ddrphy_bitslip141[3]),
-	.Q6(a7ddrphy_bitslip141[2]),
-	.Q7(a7ddrphy_bitslip141[1]),
-	.Q8(a7ddrphy_bitslip141[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed14),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip141[7]),
+	.Q2      (main_a7ddrphy_bitslip141[6]),
+	.Q3      (main_a7ddrphy_bitslip141[5]),
+	.Q4      (main_a7ddrphy_bitslip141[4]),
+	.Q5      (main_a7ddrphy_bitslip141[3]),
+	.Q6      (main_a7ddrphy_bitslip141[2]),
+	.Q7      (main_a7ddrphy_bitslip141[1]),
+	.Q8      (main_a7ddrphy_bitslip141[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_14 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_14 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay14),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed14)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay14),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed14)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_14 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_14(
-	.I(a7ddrphy_dq_o_nodelay14),
-	.T(a7ddrphy_dq_t14),
-	.IO(ddram_dq[14]),
-	.O(a7ddrphy_dq_i_nodelay14)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay14),
+	.T  (main_a7ddrphy_dq_t14),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay14),
+
+	// InOuts.
+	.IO (ddram_dq[14])
 );
 
+//------------------------------------------------------------------------------
+// Instance OSERDESE2_44 of OSERDESE2 Module.
+//------------------------------------------------------------------------------
 OSERDESE2 #(
-	.DATA_RATE_OQ("DDR"),
-	.DATA_RATE_TQ("BUF"),
-	.DATA_WIDTH(4'd8),
-	.SERDES_MODE("MASTER"),
-	.TRISTATE_WIDTH(1'd1)
+	// Parameters.
+	.DATA_RATE_OQ   ("DDR"),
+	.DATA_RATE_TQ   ("BUF"),
+	.DATA_WIDTH     (4'd8),
+	.SERDES_MODE    ("MASTER"),
+	.TRISTATE_WIDTH (1'd1)
 ) OSERDESE2_44 (
-	.CLK(sys4x_clk),
-	.CLKDIV(sys_clk),
-	.D1(a7ddrphy_bitslip150[0]),
-	.D2(a7ddrphy_bitslip150[1]),
-	.D3(a7ddrphy_bitslip150[2]),
-	.D4(a7ddrphy_bitslip150[3]),
-	.D5(a7ddrphy_bitslip150[4]),
-	.D6(a7ddrphy_bitslip150[5]),
-	.D7(a7ddrphy_bitslip150[6]),
-	.D8(a7ddrphy_bitslip150[7]),
-	.OCE(1'd1),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
-	.TCE(1'd1),
-	.OQ(a7ddrphy_dq_o_nodelay15),
-	.TQ(a7ddrphy_dq_t15)
+	// Inputs.
+	.CLK    (sys4x_clk),
+	.CLKDIV (sys_clk),
+	.D1     (main_a7ddrphy_bitslip150[0]),
+	.D2     (main_a7ddrphy_bitslip150[1]),
+	.D3     (main_a7ddrphy_bitslip150[2]),
+	.D4     (main_a7ddrphy_bitslip150[3]),
+	.D5     (main_a7ddrphy_bitslip150[4]),
+	.D6     (main_a7ddrphy_bitslip150[5]),
+	.D7     (main_a7ddrphy_bitslip150[6]),
+	.D8     (main_a7ddrphy_bitslip150[7]),
+	.OCE    (1'd1),
+	.RST    ((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1     ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE    (1'd1),
+
+	// Outputs.
+	.OQ     (main_a7ddrphy_dq_o_nodelay15),
+	.TQ     (main_a7ddrphy_dq_t15)
 );
 
+//------------------------------------------------------------------------------
+// Instance ISERDESE2_15 of ISERDESE2 Module.
+//------------------------------------------------------------------------------
 ISERDESE2 #(
-	.DATA_RATE("DDR"),
-	.DATA_WIDTH(4'd8),
-	.INTERFACE_TYPE("NETWORKING"),
-	.IOBDELAY("IFD"),
-	.NUM_CE(1'd1),
-	.SERDES_MODE("MASTER")
+	// Parameters.
+	.DATA_RATE      ("DDR"),
+	.DATA_WIDTH     (4'd8),
+	.INTERFACE_TYPE ("NETWORKING"),
+	.IOBDELAY       ("IFD"),
+	.NUM_CE         (1'd1),
+	.SERDES_MODE    ("MASTER")
 ) ISERDESE2_15 (
-	.BITSLIP(1'd0),
-	.CE1(1'd1),
-	.CLK(sys4x_clk),
-	.CLKB((~sys4x_clk)),
-	.CLKDIV(sys_clk),
-	.DDLY(a7ddrphy_dq_i_delayed15),
-	.RST((sys_rst | a7ddrphy_rst_storage)),
-	.Q1(a7ddrphy_bitslip151[7]),
-	.Q2(a7ddrphy_bitslip151[6]),
-	.Q3(a7ddrphy_bitslip151[5]),
-	.Q4(a7ddrphy_bitslip151[4]),
-	.Q5(a7ddrphy_bitslip151[3]),
-	.Q6(a7ddrphy_bitslip151[2]),
-	.Q7(a7ddrphy_bitslip151[1]),
-	.Q8(a7ddrphy_bitslip151[0])
+	// Inputs.
+	.BITSLIP (1'd0),
+	.CE1     (1'd1),
+	.CLK     (sys4x_clk),
+	.CLKB    ((~sys4x_clk)),
+	.CLKDIV  (sys_clk),
+	.DDLY    (main_a7ddrphy_dq_i_delayed15),
+	.RST     ((sys_rst | main_a7ddrphy_rst_storage)),
+
+	// Outputs.
+	.Q1      (main_a7ddrphy_bitslip151[7]),
+	.Q2      (main_a7ddrphy_bitslip151[6]),
+	.Q3      (main_a7ddrphy_bitslip151[5]),
+	.Q4      (main_a7ddrphy_bitslip151[4]),
+	.Q5      (main_a7ddrphy_bitslip151[3]),
+	.Q6      (main_a7ddrphy_bitslip151[2]),
+	.Q7      (main_a7ddrphy_bitslip151[1]),
+	.Q8      (main_a7ddrphy_bitslip151[0])
 );
 
+//------------------------------------------------------------------------------
+// Instance IDELAYE2_15 of IDELAYE2 Module.
+//------------------------------------------------------------------------------
 IDELAYE2 #(
-	.CINVCTRL_SEL("FALSE"),
-	.DELAY_SRC("IDATAIN"),
-	.HIGH_PERFORMANCE_MODE("TRUE"),
-	.IDELAY_TYPE("VARIABLE"),
-	.IDELAY_VALUE(1'd0),
-	.PIPE_SEL("FALSE"),
-	.REFCLK_FREQUENCY(200.0),
-	.SIGNAL_PATTERN("DATA")
+	// Parameters.
+	.CINVCTRL_SEL          ("FALSE"),
+	.DELAY_SRC             ("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE ("TRUE"),
+	.IDELAY_TYPE           ("VARIABLE"),
+	.IDELAY_VALUE          (1'd0),
+	.PIPE_SEL              ("FALSE"),
+	.REFCLK_FREQUENCY      (200.0),
+	.SIGNAL_PATTERN        ("DATA")
 ) IDELAYE2_15 (
-	.C(sys_clk),
-	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
-	.IDATAIN(a7ddrphy_dq_i_nodelay15),
-	.INC(1'd1),
-	.LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)),
-	.LDPIPEEN(1'd0),
-	.DATAOUT(a7ddrphy_dq_i_delayed15)
+	// Inputs.
+	.C        (sys_clk),
+	.CE       ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN  (main_a7ddrphy_dq_i_nodelay15),
+	.INC      (1'd1),
+	.LD       (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN (1'd0),
+
+	// Outputs.
+	.DATAOUT  (main_a7ddrphy_dq_i_delayed15)
 );
 
+//------------------------------------------------------------------------------
+// Instance IOBUF_15 of IOBUF Module.
+//------------------------------------------------------------------------------
 IOBUF IOBUF_15(
-	.I(a7ddrphy_dq_o_nodelay15),
-	.T(a7ddrphy_dq_t15),
-	.IO(ddram_dq[15]),
-	.O(a7ddrphy_dq_i_nodelay15)
+	// Inputs.
+	.I  (main_a7ddrphy_dq_o_nodelay15),
+	.T  (main_a7ddrphy_dq_t15),
+
+	// Outputs.
+	.O  (main_a7ddrphy_dq_i_nodelay15),
+
+	// InOuts.
+	.IO (ddram_dq[15])
 );
 
 //------------------------------------------------------------------------------
@@ -16031,14 +17159,14 @@ IOBUF IOBUF_15(
 reg [23:0] storage[0:15];
 reg [23:0] storage_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine0_wrport_we)
-		storage[litedramcore_bankmachine0_wrport_adr] <= litedramcore_bankmachine0_wrport_dat_w;
-	storage_dat0 <= storage[litedramcore_bankmachine0_wrport_adr];
+	if (main_litedramcore_bankmachine0_wrport_we)
+		storage[main_litedramcore_bankmachine0_wrport_adr] <= main_litedramcore_bankmachine0_wrport_dat_w;
+	storage_dat0 <= storage[main_litedramcore_bankmachine0_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine0_wrport_dat_r = storage_dat0;
-assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine0_rdport_adr];
+assign main_litedramcore_bankmachine0_wrport_dat_r = storage_dat0;
+assign main_litedramcore_bankmachine0_rdport_dat_r = storage[main_litedramcore_bankmachine0_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16049,14 +17177,14 @@ assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine
 reg [23:0] storage_1[0:15];
 reg [23:0] storage_1_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine1_wrport_we)
-		storage_1[litedramcore_bankmachine1_wrport_adr] <= litedramcore_bankmachine1_wrport_dat_w;
-	storage_1_dat0 <= storage_1[litedramcore_bankmachine1_wrport_adr];
+	if (main_litedramcore_bankmachine1_wrport_we)
+		storage_1[main_litedramcore_bankmachine1_wrport_adr] <= main_litedramcore_bankmachine1_wrport_dat_w;
+	storage_1_dat0 <= storage_1[main_litedramcore_bankmachine1_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0;
-assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachine1_rdport_adr];
+assign main_litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0;
+assign main_litedramcore_bankmachine1_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16067,14 +17195,14 @@ assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachi
 reg [23:0] storage_2[0:15];
 reg [23:0] storage_2_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine2_wrport_we)
-		storage_2[litedramcore_bankmachine2_wrport_adr] <= litedramcore_bankmachine2_wrport_dat_w;
-	storage_2_dat0 <= storage_2[litedramcore_bankmachine2_wrport_adr];
+	if (main_litedramcore_bankmachine2_wrport_we)
+		storage_2[main_litedramcore_bankmachine2_wrport_adr] <= main_litedramcore_bankmachine2_wrport_dat_w;
+	storage_2_dat0 <= storage_2[main_litedramcore_bankmachine2_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0;
-assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachine2_rdport_adr];
+assign main_litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0;
+assign main_litedramcore_bankmachine2_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16085,14 +17213,14 @@ assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachi
 reg [23:0] storage_3[0:15];
 reg [23:0] storage_3_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine3_wrport_we)
-		storage_3[litedramcore_bankmachine3_wrport_adr] <= litedramcore_bankmachine3_wrport_dat_w;
-	storage_3_dat0 <= storage_3[litedramcore_bankmachine3_wrport_adr];
+	if (main_litedramcore_bankmachine3_wrport_we)
+		storage_3[main_litedramcore_bankmachine3_wrport_adr] <= main_litedramcore_bankmachine3_wrport_dat_w;
+	storage_3_dat0 <= storage_3[main_litedramcore_bankmachine3_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0;
-assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachine3_rdport_adr];
+assign main_litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0;
+assign main_litedramcore_bankmachine3_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16103,14 +17231,14 @@ assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachi
 reg [23:0] storage_4[0:15];
 reg [23:0] storage_4_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine4_wrport_we)
-		storage_4[litedramcore_bankmachine4_wrport_adr] <= litedramcore_bankmachine4_wrport_dat_w;
-	storage_4_dat0 <= storage_4[litedramcore_bankmachine4_wrport_adr];
+	if (main_litedramcore_bankmachine4_wrport_we)
+		storage_4[main_litedramcore_bankmachine4_wrport_adr] <= main_litedramcore_bankmachine4_wrport_dat_w;
+	storage_4_dat0 <= storage_4[main_litedramcore_bankmachine4_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0;
-assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachine4_rdport_adr];
+assign main_litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0;
+assign main_litedramcore_bankmachine4_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16121,14 +17249,14 @@ assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachi
 reg [23:0] storage_5[0:15];
 reg [23:0] storage_5_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine5_wrport_we)
-		storage_5[litedramcore_bankmachine5_wrport_adr] <= litedramcore_bankmachine5_wrport_dat_w;
-	storage_5_dat0 <= storage_5[litedramcore_bankmachine5_wrport_adr];
+	if (main_litedramcore_bankmachine5_wrport_we)
+		storage_5[main_litedramcore_bankmachine5_wrport_adr] <= main_litedramcore_bankmachine5_wrport_dat_w;
+	storage_5_dat0 <= storage_5[main_litedramcore_bankmachine5_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0;
-assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachine5_rdport_adr];
+assign main_litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0;
+assign main_litedramcore_bankmachine5_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16139,14 +17267,14 @@ assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachi
 reg [23:0] storage_6[0:15];
 reg [23:0] storage_6_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine6_wrport_we)
-		storage_6[litedramcore_bankmachine6_wrport_adr] <= litedramcore_bankmachine6_wrport_dat_w;
-	storage_6_dat0 <= storage_6[litedramcore_bankmachine6_wrport_adr];
+	if (main_litedramcore_bankmachine6_wrport_we)
+		storage_6[main_litedramcore_bankmachine6_wrport_adr] <= main_litedramcore_bankmachine6_wrport_dat_w;
+	storage_6_dat0 <= storage_6[main_litedramcore_bankmachine6_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0;
-assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachine6_rdport_adr];
+assign main_litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0;
+assign main_litedramcore_bankmachine6_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_rdport_adr];
 
 
 //------------------------------------------------------------------------------
@@ -16157,197 +17285,308 @@ assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachi
 reg [23:0] storage_7[0:15];
 reg [23:0] storage_7_dat0;
 always @(posedge sys_clk) begin
-	if (litedramcore_bankmachine7_wrport_we)
-		storage_7[litedramcore_bankmachine7_wrport_adr] <= litedramcore_bankmachine7_wrport_dat_w;
-	storage_7_dat0 <= storage_7[litedramcore_bankmachine7_wrport_adr];
+	if (main_litedramcore_bankmachine7_wrport_we)
+		storage_7[main_litedramcore_bankmachine7_wrport_adr] <= main_litedramcore_bankmachine7_wrport_dat_w;
+	storage_7_dat0 <= storage_7[main_litedramcore_bankmachine7_wrport_adr];
 end
 always @(posedge sys_clk) begin
 end
-assign litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0;
-assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachine7_rdport_adr];
+assign main_litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0;
+assign main_litedramcore_bankmachine7_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_rdport_adr];
 
 
+//------------------------------------------------------------------------------
+// Instance FDCE of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(reset),
-	.Q(litedramcore_reset0)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (main_reset),
+
+	// Outputs.
+	.Q   (builder_reset0)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_1 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_1(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset0),
-	.Q(litedramcore_reset1)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset0),
+
+	// Outputs.
+	.Q   (builder_reset1)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_2 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_2(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset1),
-	.Q(litedramcore_reset2)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset1),
+
+	// Outputs.
+	.Q   (builder_reset2)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_3 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_3(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset2),
-	.Q(litedramcore_reset3)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset2),
+
+	// Outputs.
+	.Q   (builder_reset3)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_4 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_4(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset3),
-	.Q(litedramcore_reset4)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset3),
+
+	// Outputs.
+	.Q   (builder_reset4)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_5 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_5(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset4),
-	.Q(litedramcore_reset5)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset4),
+
+	// Outputs.
+	.Q   (builder_reset5)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_6 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_6(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset5),
-	.Q(litedramcore_reset6)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset5),
+
+	// Outputs.
+	.Q   (builder_reset6)
 );
 
+//------------------------------------------------------------------------------
+// Instance FDCE_7 of FDCE Module.
+//------------------------------------------------------------------------------
 FDCE FDCE_7(
-	.C(clkin),
-	.CE(1'd1),
-	.CLR(1'd0),
-	.D(litedramcore_reset6),
-	.Q(litedramcore_reset7)
+	// Inputs.
+	.C   (main_clkin),
+	.CE  (1'd1),
+	.CLR (1'd0),
+	.D   (builder_reset6),
+
+	// Outputs.
+	.Q   (builder_reset7)
 );
 
+//------------------------------------------------------------------------------
+// Instance PLLE2_ADV of PLLE2_ADV Module.
+//------------------------------------------------------------------------------
 PLLE2_ADV #(
-	.CLKFBOUT_MULT(6'd32),
-	.CLKIN1_PERIOD(20.0),
-	.CLKOUT0_DIVIDE(4'd8),
-	.CLKOUT0_PHASE(1'd0),
-	.CLKOUT1_DIVIDE(5'd16),
-	.CLKOUT1_PHASE(1'd0),
-	.CLKOUT2_DIVIDE(3'd4),
-	.CLKOUT2_PHASE(1'd0),
-	.CLKOUT3_DIVIDE(3'd4),
-	.CLKOUT3_PHASE(7'd90),
-	.DIVCLK_DIVIDE(1'd1),
-	.REF_JITTER1(0.01),
-	.STARTUP_WAIT("FALSE")
+	// Parameters.
+	.CLKFBOUT_MULT  (6'd32),
+	.CLKIN1_PERIOD  (20.0),
+	.CLKOUT0_DIVIDE (4'd8),
+	.CLKOUT0_PHASE  (1'd0),
+	.CLKOUT1_DIVIDE (5'd16),
+	.CLKOUT1_PHASE  (1'd0),
+	.CLKOUT2_DIVIDE (3'd4),
+	.CLKOUT2_PHASE  (1'd0),
+	.CLKOUT3_DIVIDE (3'd4),
+	.CLKOUT3_PHASE  (7'd90),
+	.DIVCLK_DIVIDE  (1'd1),
+	.REF_JITTER1    (0.01),
+	.STARTUP_WAIT   ("FALSE")
 ) PLLE2_ADV (
-	.CLKFBIN(litedramcore_pll_fb),
-	.CLKIN1(clkin),
-	.PWRDWN(power_down),
-	.RST(litedramcore_reset7),
-	.CLKFBOUT(litedramcore_pll_fb),
-	.CLKOUT0(clkout0),
-	.CLKOUT1(clkout1),
-	.CLKOUT2(clkout2),
-	.CLKOUT3(clkout3),
-	.LOCKED(locked)
+	// Inputs.
+	.CLKFBIN  (builder_pll_fb),
+	.CLKIN1   (main_clkin),
+	.PWRDWN   (main_power_down),
+	.RST      (builder_reset7),
+
+	// Outputs.
+	.CLKFBOUT (builder_pll_fb),
+	.CLKOUT0  (main_clkout0),
+	.CLKOUT1  (main_clkout1),
+	.CLKOUT2  (main_clkout2),
+	.CLKOUT3  (main_clkout3),
+	.LOCKED   (main_locked)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE (
-	.C(iodelay_clk),
-	.CE(1'd1),
-	.D(1'd0),
-	.PRE(xilinxasyncresetsynchronizerimpl0),
-	.Q(xilinxasyncresetsynchronizerimpl0_rst_meta)
+	// Inputs.
+	.C   (iodelay_clk),
+	.CE  (1'd1),
+	.D   (1'd0),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl0_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_1 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_1 (
-	.C(iodelay_clk),
-	.CE(1'd1),
-	.D(xilinxasyncresetsynchronizerimpl0_rst_meta),
-	.PRE(xilinxasyncresetsynchronizerimpl0),
-	.Q(iodelay_rst)
+	// Inputs.
+	.C   (iodelay_clk),
+	.CE  (1'd1),
+	.D   (builder_xilinxasyncresetsynchronizerimpl0_rst_meta),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset),
+
+	// Outputs.
+	.Q   (iodelay_rst)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_2 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_2 (
-	.C(sys_clk),
-	.CE(1'd1),
-	.D(1'd0),
-	.PRE(xilinxasyncresetsynchronizerimpl1),
-	.Q(xilinxasyncresetsynchronizerimpl1_rst_meta)
+	// Inputs.
+	.C   (sys_clk),
+	.CE  (1'd1),
+	.D   (1'd0),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl1_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_3 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_3 (
-	.C(sys_clk),
-	.CE(1'd1),
-	.D(xilinxasyncresetsynchronizerimpl1_rst_meta),
-	.PRE(xilinxasyncresetsynchronizerimpl1),
-	.Q(sys_rst)
+	// Inputs.
+	.C   (sys_clk),
+	.CE  (1'd1),
+	.D   (builder_xilinxasyncresetsynchronizerimpl1_rst_meta),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset),
+
+	// Outputs.
+	.Q   (sys_rst)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_4 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_4 (
-	.C(sys4x_clk),
-	.CE(1'd1),
-	.D(1'd0),
-	.PRE(xilinxasyncresetsynchronizerimpl2),
-	.Q(xilinxasyncresetsynchronizerimpl2_rst_meta)
+	// Inputs.
+	.C   (sys4x_clk),
+	.CE  (1'd1),
+	.D   (1'd0),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl2_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_5 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_5 (
-	.C(sys4x_clk),
-	.CE(1'd1),
-	.D(xilinxasyncresetsynchronizerimpl2_rst_meta),
-	.PRE(xilinxasyncresetsynchronizerimpl2),
-	.Q(xilinxasyncresetsynchronizerimpl2_expr)
+	// Inputs.
+	.C   (sys4x_clk),
+	.CE  (1'd1),
+	.D   (builder_xilinxasyncresetsynchronizerimpl2_rst_meta),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl2_expr)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_6 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_6 (
-	.C(sys4x_dqs_clk),
-	.CE(1'd1),
-	.D(1'd0),
-	.PRE(xilinxasyncresetsynchronizerimpl3),
-	.Q(xilinxasyncresetsynchronizerimpl3_rst_meta)
+	// Inputs.
+	.C   (sys4x_dqs_clk),
+	.CE  (1'd1),
+	.D   (1'd0),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl3_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *)
+//------------------------------------------------------------------------------
+// Instance FDPE_7 of FDPE Module.
+//------------------------------------------------------------------------------
 FDPE #(
-	.INIT(1'd1)
+	// Parameters.
+	.INIT (1'd1)
 ) FDPE_7 (
-	.C(sys4x_dqs_clk),
-	.CE(1'd1),
-	.D(xilinxasyncresetsynchronizerimpl3_rst_meta),
-	.PRE(xilinxasyncresetsynchronizerimpl3),
-	.Q(xilinxasyncresetsynchronizerimpl3_expr)
+	// Inputs.
+	.C   (sys4x_dqs_clk),
+	.CE  (1'd1),
+	.D   (builder_xilinxasyncresetsynchronizerimpl3_rst_meta),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset),
+
+	// Outputs.
+	.Q   (builder_xilinxasyncresetsynchronizerimpl3_expr)
 );
 
 endmodule
 
 // -----------------------------------------------------------------------------
-//  Auto-Generated by LiteX on 2022-10-28 19:01:25.
+//  Auto-Generated by LiteX on 2024-04-01 10:12:10.
 //------------------------------------------------------------------------------