From 32919435a3cfe585573195bd4819e2ee5fc9fdcd Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Tue, 9 Dec 2025 11:20:23 +1100 Subject: [PATCH] FPU: Allow mtfsb* to set FPSCR[FX] implicitly If mtfsb1 causes an individual exception bit to go from 0 to 1, that should set FX as well. Arrange for this by setting update_fx to 1. Also make sure mcrfs doesn't copy the reserved FPSCR bit. Signed-off-by: Paul Mackerras --- fpu.vhdl | 3 ++- tests/fpu/fpu.c | 6 +++--- tests/test_fpu.bin | Bin 33136 -> 33136 bytes 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/fpu.vhdl b/fpu.vhdl index 84cec59..84f968b 100644 --- a/fpu.vhdl +++ b/fpu.vhdl @@ -1438,7 +1438,7 @@ begin for i in 0 to 7 loop if i = j then k := (7 - i) * 4; - v.cr_result := r.fpscr(k + 3 downto k); + v.cr_result := r.fpscr(k + 3 downto k) and fpscr_mask(k + 3 downto k); fpscr_mask(k + 3 downto k) := "0000"; end if; end loop; @@ -1505,6 +1505,7 @@ begin v.fpscr(31 - i) := r.insn(6); end if; end loop; + update_fx := '1'; v.instr_done := '1'; when DO_MTFSFI => diff --git a/tests/fpu/fpu.c b/tests/fpu/fpu.c index 784d81f..824e764 100644 --- a/tests/fpu/fpu.c +++ b/tests/fpu/fpu.c @@ -351,15 +351,15 @@ int test4(long arg) fpscr = fpscr_eval((fpscr & 0x0fffffff) | 0x70000000); if (get_fpscr() != fpscr) return 16 * i + 27; - asm("mtfsb0 21"); + asm("mtfsb0 21"); /* VXSOFT */ fpscr = fpscr_eval(fpscr & ~(1 << (31-21))); if (get_fpscr() != fpscr) return 16 * i + 28; asm("mtfsb1 21"); - fpscr = fpscr_eval(fpscr | (1 << (31-21))); + fpscr = fpscr_eval(fpscr | (1 << (31-21)) | (1ul << 31)); if (get_fpscr() != fpscr) return 16 * i + 29; - asm("mtfsb0 24"); + asm("mtfsb0 24"); /* OE */ fpscr = fpscr_eval(fpscr & ~(1 << (31-24))); if (get_fpscr() != fpscr) return 16 * i + 30; diff --git a/tests/test_fpu.bin b/tests/test_fpu.bin index 13aad7d991130e9b93d1a92205d76ed09e19bf49..4280dd2468e42c411dccace1f3377962c0b207f4 100755 GIT binary patch delta 1631 zcmZ9Me@I(b6vyv*t3@wh_f}7d538f$UlRfsQzPj zu#vGPdrmS-Zv>b^XRXmyv`L$;k4JM@Objo75%tTQ$$96OsEhNncpgq-U?;2rd4)%Ch6JM)Y>*FgQeAnL3^+MLOnn1150;AYr?1Q_wV621%d~PgoO|GTq zb)8t5*BG%fuVG@I*Cjcsd)Qtd6^_4-ui1)mtG*1zFxR9rU0F>}<^nPQeUkL8gC`d| zGcJZm;|aFOOU+@(bP5bOZ)&1I^US*3k;mz)44~hv&g~^t={JLC&8LLp*?S?F3t=3y zEIRGjU+K=n#7egfY`6G?&I2j8Tb4p$VH5XTj%jBfrTa}1EB#8aLi7p4uachzM?|%d zwTTV3V_JC0Z+j)(k1nU^qk45&_29&iRi`!44CRSeyyS5nC#^nsirF?jgwSczX?vE_ zJvxY$vE9InHeW_n7Hf%Pt}PFr*v!11?Yj2JUSxMt( z|DqzV;tzISO%)EK%kVJ$2KLDO;s$nbR@}gMh?O_+8jd`{Df!S zZuk(V-0J*$%aU}SHs-CG`ll+!JS*7HdIWPknHdu+lGK8JPa&E-1@s w=S^=*QjEty?I`s|>h)OV(^YjpktDA0mP0*8JwjSF&<8cHUFJR6@7po_2h=EoqW}N^ delta 1672 zcmZ9MVMtq76vyw$49U8sjdN-fXKO00#^{n5V-k~CGv^eNn1)qW8Lp97*gp87Y(h3; z6I}-@DAS!5I;dmmaMZCvB^CCeLfsS`te~u;3Uk$|tDUt(rHoR?+qqdXUc7J*@ArS_ zoOjN9=e|UrB+(}s?1zrAf%-g{!MVIfP@*dT9(Zso|1+4v-h+*B8-F4@h1se`xPh%? zFJg>r2R>BY0|QQ~8zsB%;l6@5U?%P_2ukD?#jJ@j7QorVui$*)DHw|z57o;wody5t zClZmcfd#EMWx;T3N~>W3t2ch>=)63T6%35;3hq$Bxv=eT!CjXq4l7xotGY;dtB?uy z!G8pIKVyRRt6+E_<(Iw3?-2RDOMYJRJH`U%qAVC_Px-Fl+^Z$IrF0j_OUjOy&+qot zF}7rXIj+!~0H)DpFuhi|NhNHIM3gLQ4Xu0}X-To1^UjZv2F}k`BHTwpnwc1=i8`jS zF3EzS!5sY3aRjuuV0aTQV1=>7?|dY$SGuv%M` z9&uAv+;as-jNPz|no2#KL4Re5QMExu?Mz3qc#%|`pE&tM(s&~-VqnK@fmDXeI9ge+ z8Tl(SYB9yhRyV$m+(CsYAI9;h$pXXJX6lwMZV7HV8tu6Ut~z-0(f3D^FJ%FtD&IBv zFte{QVsT$FVsT$X#JsP;R8>pZS{0ER53r^&T&~H*?W!Y^SOV46W!Yb>XEt;J{pOtP zE>d}0CsGOSVwd@})Vx2P;IX-k3RhL@%$FWy#(zT0KY<`zb?_I&8#zmwINL0KSbbV* zRHU zirF=K=t5VGPSd%P8PP^8F7p-+)cBwR7s=9)+jT9yf21N(Lw=T6Jml@f;$iR;^I;Hw z0VipEAkt%c1+Uw?VG*?slgqrEc`iFsoIaOroJHr-ODsN@*KpWTB5jbRU(fFjHB8`B zhfXuTl&n0;4-n5bLM-kz3mcqoLkwe13w)0Y&Vq*F`+}R-EhX>U{0Pu<=ScfT@=-Y5 z&kX4kNv->TZI-lA(tiC#aQC3C_OK*+A0NM@#(vfF@t)e8=U_HI5WxEXhOf|Aeue-^yBt=Oz<=I zdh8&_36CD`;wIT^Sm@P56MD(6V-MN$c%5t!E|R^4ie^3hhEB4tV<*{F9431i?=+j> zB!Vv|cWO%zqPzxLrL^m48&K=hX*;$Bfh&9|X-8>?NGk`rpvAR|v