From 336f0e0690e391700ea4e636824f641927e20512 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Wed, 23 Oct 2019 14:00:30 +1100 Subject: [PATCH] ram: Ack stores early Stores only need a single cycle, so we can ack them early if there isn't an older ack already in the pipeline Signed-off-by: Benjamin Herrenschmidt --- wishbone_bram_wrapper.vhdl | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/wishbone_bram_wrapper.vhdl b/wishbone_bram_wrapper.vhdl index a711c3d..14520b5 100644 --- a/wishbone_bram_wrapper.vhdl +++ b/wishbone_bram_wrapper.vhdl @@ -67,8 +67,16 @@ begin ack_buf <= '0'; ack <= '0'; else - ack <= wishbone_in.stb; - ack_buf <= ack; + -- On loads, we have a delay cycle due to BRAM bufferring + -- but not on stores. So try to send an early ack on a + -- store if we aren't behind an existing load ack. + -- + if ram_we = '1' and ack = '0' then + ack_buf <= '1'; + else + ack <= wishbone_in.stb; + ack_buf <= ack; + end if; end if; end if; end process;