diff --git a/dram_tb.vhdl b/dram_tb.vhdl index d08544c..f368e2f 100644 --- a/dram_tb.vhdl +++ b/dram_tb.vhdl @@ -236,14 +236,14 @@ begin wb_read(a); wait_acks(1); read_data(d); - assert d = x"0123456789abcdef" report "bad data" severity failure; + assert d = x"0123456789abcdef" report "bad data, got " & to_hstring(d) severity failure; report "Simple read hit..."; clr_acks; wb_read(a); wait_acks(1); read_data(d); - assert d = x"0123456789abcdef" report "bad data" severity failure; + assert d = x"0123456789abcdef" report "bad data, got " & to_hstring(d) severity failure; report "Back to back 4 stores 4 reads on hit..."; clr_acks; diff --git a/fpga/arty_a7.xdc b/fpga/arty_a7.xdc index 9bd0226..71d691a 100644 --- a/fpga/arty_a7.xdc +++ b/fpga/arty_a7.xdc @@ -1,232 +1,298 @@ +################################################################################ +# clkin, reset, uart pins... +################################################################################ + set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { ext_clk }]; -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { ext_clk }]; set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { ext_rst }]; set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart_main_tx }]; set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { uart_main_rx }]; -##Pmod Header JC: UART (bottom) +################################################################################ +# Pmod Header JC: UART (bottom) +################################################################################ -set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_cts_n }]; -set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_tx }]; -set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rx }]; -set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rts_n }]; +#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_cts_n }]; +#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_tx }]; +#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rx }]; +#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rts_n }]; + +################################################################################ +# RGB LEDs +################################################################################ -# LEDs set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; +################################################################################ # DRAM (generated by LiteX) - ## ddram:0.a -set_property LOC R2 [get_ports ddram_a[0]] -set_property SLEW FAST [get_ports ddram_a[0]] -set_property IOSTANDARD SSTL135 [get_ports ddram_a[0]] - ## ddram:0.a -set_property LOC M6 [get_ports ddram_a[1]] -set_property SLEW FAST [get_ports ddram_a[1]] -set_property IOSTANDARD SSTL135 [get_ports ddram_a[1]] - ## ddram:0.a -set_property LOC N4 [get_ports ddram_a[2]] -set_property SLEW FAST [get_ports ddram_a[2]] -set_property IOSTANDARD SSTL135 [get_ports ddram_a[2]] - ## ddram:0.a -set_property LOC T1 [get_ports ddram_a[3]] -set_property SLEW FAST [get_ports ddram_a[3]] -set_property IOSTANDARD SSTL135 [get_ports ddram_a[3]] - ## ddram:0.a -set_property LOC N6 [get_ports ddram_a[4]] -set_property SLEW FAST [get_ports ddram_a[4]] -set_property IOSTANDARD SSTL135 [get_ports ddram_a[4]] - ## ddram:0.a -set_property LOC R7 [get_ports ddram_a[5]] -set_property SLEW FAST [get_ports ddram_a[5]] -set_property IOSTANDARD SSTL135 [get_ports ddram_a[5]] - ## ddram:0.a -set_property LOC V6 [get_ports ddram_a[6]] -set_property SLEW FAST [get_ports ddram_a[6]] -set_property IOSTANDARD SSTL135 [get_ports ddram_a[6]] - ## ddram:0.a -set_property LOC U7 [get_ports ddram_a[7]] -set_property SLEW FAST [get_ports ddram_a[7]] -set_property IOSTANDARD SSTL135 [get_ports ddram_a[7]] - ## ddram:0.a -set_property LOC R8 [get_ports ddram_a[8]] -set_property SLEW FAST [get_ports ddram_a[8]] -set_property IOSTANDARD SSTL135 [get_ports ddram_a[8]] - ## ddram:0.a -set_property LOC V7 [get_ports ddram_a[9]] -set_property SLEW FAST [get_ports ddram_a[9]] -set_property IOSTANDARD SSTL135 [get_ports ddram_a[9]] - ## ddram:0.a -set_property LOC R6 [get_ports ddram_a[10]] -set_property SLEW FAST [get_ports ddram_a[10]] -set_property IOSTANDARD SSTL135 [get_ports ddram_a[10]] - ## ddram:0.a -set_property LOC U6 [get_ports ddram_a[11]] -set_property SLEW FAST [get_ports ddram_a[11]] -set_property IOSTANDARD SSTL135 [get_ports ddram_a[11]] - ## ddram:0.a -set_property LOC T6 [get_ports ddram_a[12]] -set_property SLEW FAST [get_ports ddram_a[12]] -set_property IOSTANDARD SSTL135 [get_ports ddram_a[12]] - ## ddram:0.a -set_property LOC T8 [get_ports ddram_a[13]] -set_property SLEW FAST [get_ports ddram_a[13]] -set_property IOSTANDARD SSTL135 [get_ports ddram_a[13]] - ## ddram:0.ba -set_property LOC R1 [get_ports ddram_ba[0]] -set_property SLEW FAST [get_ports ddram_ba[0]] -set_property IOSTANDARD SSTL135 [get_ports ddram_ba[0]] - ## ddram:0.ba -set_property LOC P4 [get_ports ddram_ba[1]] -set_property SLEW FAST [get_ports ddram_ba[1]] -set_property IOSTANDARD SSTL135 [get_ports ddram_ba[1]] - ## ddram:0.ba -set_property LOC P2 [get_ports ddram_ba[2]] -set_property SLEW FAST [get_ports ddram_ba[2]] -set_property IOSTANDARD SSTL135 [get_ports ddram_ba[2]] - ## ddram:0.ras_n -set_property LOC P3 [get_ports ddram_ras_n] -set_property SLEW FAST [get_ports ddram_ras_n] -set_property IOSTANDARD SSTL135 [get_ports ddram_ras_n] - ## ddram:0.cas_n -set_property LOC M4 [get_ports ddram_cas_n] -set_property SLEW FAST [get_ports ddram_cas_n] -set_property IOSTANDARD SSTL135 [get_ports ddram_cas_n] - ## ddram:0.we_n -set_property LOC P5 [get_ports ddram_we_n] -set_property SLEW FAST [get_ports ddram_we_n] -set_property IOSTANDARD SSTL135 [get_ports ddram_we_n] - ## ddram:0.cs_n -set_property LOC U8 [get_ports ddram_cs_n] -set_property SLEW FAST [get_ports ddram_cs_n] -set_property IOSTANDARD SSTL135 [get_ports ddram_cs_n] - ## ddram:0.dm -set_property LOC L1 [get_ports ddram_dm[0]] -set_property SLEW FAST [get_ports ddram_dm[0]] -set_property IOSTANDARD SSTL135 [get_ports ddram_dm[0]] - ## ddram:0.dm -set_property LOC U1 [get_ports ddram_dm[1]] -set_property SLEW FAST [get_ports ddram_dm[1]] -set_property IOSTANDARD SSTL135 [get_ports ddram_dm[1]] - ## ddram:0.dq -set_property LOC K5 [get_ports ddram_dq[0]] -set_property SLEW FAST [get_ports ddram_dq[0]] -set_property IOSTANDARD SSTL135 [get_ports ddram_dq[0]] -set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[0]] - ## ddram:0.dq -set_property LOC L3 [get_ports ddram_dq[1]] -set_property SLEW FAST [get_ports ddram_dq[1]] -set_property IOSTANDARD SSTL135 [get_ports ddram_dq[1]] -set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[1]] - ## ddram:0.dq -set_property LOC K3 [get_ports ddram_dq[2]] -set_property SLEW FAST [get_ports ddram_dq[2]] -set_property IOSTANDARD SSTL135 [get_ports ddram_dq[2]] -set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[2]] - ## ddram:0.dq -set_property LOC L6 [get_ports ddram_dq[3]] -set_property SLEW FAST [get_ports ddram_dq[3]] -set_property IOSTANDARD SSTL135 [get_ports ddram_dq[3]] -set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[3]] - ## ddram:0.dq -set_property LOC M3 [get_ports ddram_dq[4]] -set_property SLEW FAST [get_ports ddram_dq[4]] -set_property IOSTANDARD SSTL135 [get_ports ddram_dq[4]] -set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[4]] - ## ddram:0.dq -set_property LOC M1 [get_ports ddram_dq[5]] -set_property SLEW FAST [get_ports ddram_dq[5]] -set_property IOSTANDARD SSTL135 [get_ports ddram_dq[5]] -set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[5]] - ## ddram:0.dq -set_property LOC L4 [get_ports ddram_dq[6]] -set_property SLEW FAST [get_ports ddram_dq[6]] -set_property IOSTANDARD SSTL135 [get_ports ddram_dq[6]] -set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[6]] - ## ddram:0.dq -set_property LOC M2 [get_ports ddram_dq[7]] -set_property SLEW FAST [get_ports ddram_dq[7]] -set_property IOSTANDARD SSTL135 [get_ports ddram_dq[7]] -set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[7]] - ## ddram:0.dq -set_property LOC V4 [get_ports ddram_dq[8]] -set_property SLEW FAST [get_ports ddram_dq[8]] -set_property IOSTANDARD SSTL135 [get_ports ddram_dq[8]] -set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[8]] - ## ddram:0.dq -set_property LOC T5 [get_ports ddram_dq[9]] -set_property SLEW FAST [get_ports ddram_dq[9]] -set_property IOSTANDARD SSTL135 [get_ports ddram_dq[9]] -set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[9]] - ## ddram:0.dq -set_property LOC U4 [get_ports ddram_dq[10]] -set_property SLEW FAST [get_ports ddram_dq[10]] -set_property IOSTANDARD SSTL135 [get_ports ddram_dq[10]] -set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[10]] - ## ddram:0.dq -set_property LOC V5 [get_ports ddram_dq[11]] -set_property SLEW FAST [get_ports ddram_dq[11]] -set_property IOSTANDARD SSTL135 [get_ports ddram_dq[11]] -set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[11]] - ## ddram:0.dq -set_property LOC V1 [get_ports ddram_dq[12]] -set_property SLEW FAST [get_ports ddram_dq[12]] -set_property IOSTANDARD SSTL135 [get_ports ddram_dq[12]] -set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[12]] - ## ddram:0.dq -set_property LOC T3 [get_ports ddram_dq[13]] -set_property SLEW FAST [get_ports ddram_dq[13]] -set_property IOSTANDARD SSTL135 [get_ports ddram_dq[13]] -set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[13]] - ## ddram:0.dq -set_property LOC U3 [get_ports ddram_dq[14]] -set_property SLEW FAST [get_ports ddram_dq[14]] -set_property IOSTANDARD SSTL135 [get_ports ddram_dq[14]] -set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[14]] - ## ddram:0.dq -set_property LOC R3 [get_ports ddram_dq[15]] -set_property SLEW FAST [get_ports ddram_dq[15]] -set_property IOSTANDARD SSTL135 [get_ports ddram_dq[15]] -set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[15]] - ## ddram:0.dqs_p -set_property LOC N2 [get_ports ddram_dqs_p[0]] -set_property SLEW FAST [get_ports ddram_dqs_p[0]] -set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[0]] - ## ddram:0.dqs_p -set_property LOC U2 [get_ports ddram_dqs_p[1]] -set_property SLEW FAST [get_ports ddram_dqs_p[1]] -set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[1]] - ## ddram:0.dqs_n -set_property LOC N1 [get_ports ddram_dqs_n[0]] -set_property SLEW FAST [get_ports ddram_dqs_n[0]] -set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[0]] - ## ddram:0.dqs_n -set_property LOC V2 [get_ports ddram_dqs_n[1]] -set_property SLEW FAST [get_ports ddram_dqs_n[1]] -set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[1]] - ## ddram:0.clk_p -set_property LOC U9 [get_ports ddram_clk_p] -set_property SLEW FAST [get_ports ddram_clk_p] -set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_p] - ## ddram:0.clk_n -set_property LOC V9 [get_ports ddram_clk_n] -set_property SLEW FAST [get_ports ddram_clk_n] -set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_n] - ## ddram:0.cke -set_property LOC N5 [get_ports ddram_cke] -set_property SLEW FAST [get_ports ddram_cke] -set_property IOSTANDARD SSTL135 [get_ports ddram_cke] - ## ddram:0.odt -set_property LOC R5 [get_ports ddram_odt] -set_property SLEW FAST [get_ports ddram_odt] -set_property IOSTANDARD SSTL135 [get_ports ddram_odt] - ## ddram:0.reset_n -set_property LOC K6 [get_ports ddram_reset_n] -set_property SLEW FAST [get_ports ddram_reset_n] -set_property IOSTANDARD SSTL135 [get_ports ddram_reset_n] +################################################################################ + +# ddram:0.a +set_property LOC R2 [get_ports {ddram_a[0]}] +set_property SLEW FAST [get_ports {ddram_a[0]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[0]}] + +# ddram:0.a +set_property LOC M6 [get_ports {ddram_a[1]}] +set_property SLEW FAST [get_ports {ddram_a[1]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[1]}] + +# ddram:0.a +set_property LOC N4 [get_ports {ddram_a[2]}] +set_property SLEW FAST [get_ports {ddram_a[2]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[2]}] + +# ddram:0.a +set_property LOC T1 [get_ports {ddram_a[3]}] +set_property SLEW FAST [get_ports {ddram_a[3]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[3]}] + +# ddram:0.a +set_property LOC N6 [get_ports {ddram_a[4]}] +set_property SLEW FAST [get_ports {ddram_a[4]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[4]}] + +# ddram:0.a +set_property LOC R7 [get_ports {ddram_a[5]}] +set_property SLEW FAST [get_ports {ddram_a[5]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[5]}] + +# ddram:0.a +set_property LOC V6 [get_ports {ddram_a[6]}] +set_property SLEW FAST [get_ports {ddram_a[6]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[6]}] + +# ddram:0.a +set_property LOC U7 [get_ports {ddram_a[7]}] +set_property SLEW FAST [get_ports {ddram_a[7]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[7]}] + +# ddram:0.a +set_property LOC R8 [get_ports {ddram_a[8]}] +set_property SLEW FAST [get_ports {ddram_a[8]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[8]}] + +# ddram:0.a +set_property LOC V7 [get_ports {ddram_a[9]}] +set_property SLEW FAST [get_ports {ddram_a[9]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[9]}] + +# ddram:0.a +set_property LOC R6 [get_ports {ddram_a[10]}] +set_property SLEW FAST [get_ports {ddram_a[10]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[10]}] + +# ddram:0.a +set_property LOC U6 [get_ports {ddram_a[11]}] +set_property SLEW FAST [get_ports {ddram_a[11]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[11]}] + +# ddram:0.a +set_property LOC T6 [get_ports {ddram_a[12]}] +set_property SLEW FAST [get_ports {ddram_a[12]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[12]}] + +# ddram:0.a +set_property LOC T8 [get_ports {ddram_a[13]}] +set_property SLEW FAST [get_ports {ddram_a[13]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[13]}] + +# ddram:0.ba +set_property LOC R1 [get_ports {ddram_ba[0]}] +set_property SLEW FAST [get_ports {ddram_ba[0]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[0]}] + +# ddram:0.ba +set_property LOC P4 [get_ports {ddram_ba[1]}] +set_property SLEW FAST [get_ports {ddram_ba[1]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[1]}] + +# ddram:0.ba +set_property LOC P2 [get_ports {ddram_ba[2]}] +set_property SLEW FAST [get_ports {ddram_ba[2]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[2]}] + +# ddram:0.ras_n +set_property LOC P3 [get_ports {ddram_ras_n}] +set_property SLEW FAST [get_ports {ddram_ras_n}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_ras_n}] + +# ddram:0.cas_n +set_property LOC M4 [get_ports {ddram_cas_n}] +set_property SLEW FAST [get_ports {ddram_cas_n}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_cas_n}] + +# ddram:0.we_n +set_property LOC P5 [get_ports {ddram_we_n}] +set_property SLEW FAST [get_ports {ddram_we_n}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_we_n}] + +# ddram:0.cs_n +set_property LOC U8 [get_ports {ddram_cs_n}] +set_property SLEW FAST [get_ports {ddram_cs_n}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_cs_n}] + +# ddram:0.dm +set_property LOC L1 [get_ports {ddram_dm[0]}] +set_property SLEW FAST [get_ports {ddram_dm[0]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dm[0]}] + +# ddram:0.dm +set_property LOC U1 [get_ports {ddram_dm[1]}] +set_property SLEW FAST [get_ports {ddram_dm[1]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dm[1]}] + +# ddram:0.dq +set_property LOC K5 [get_ports {ddram_dq[0]}] +set_property SLEW FAST [get_ports {ddram_dq[0]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[0]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[0]}] + +# ddram:0.dq +set_property LOC L3 [get_ports {ddram_dq[1]}] +set_property SLEW FAST [get_ports {ddram_dq[1]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[1]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[1]}] + +# ddram:0.dq +set_property LOC K3 [get_ports {ddram_dq[2]}] +set_property SLEW FAST [get_ports {ddram_dq[2]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[2]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[2]}] + +# ddram:0.dq +set_property LOC L6 [get_ports {ddram_dq[3]}] +set_property SLEW FAST [get_ports {ddram_dq[3]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[3]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[3]}] + +# ddram:0.dq +set_property LOC M3 [get_ports {ddram_dq[4]}] +set_property SLEW FAST [get_ports {ddram_dq[4]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[4]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[4]}] + +# ddram:0.dq +set_property LOC M1 [get_ports {ddram_dq[5]}] +set_property SLEW FAST [get_ports {ddram_dq[5]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[5]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[5]}] + +# ddram:0.dq +set_property LOC L4 [get_ports {ddram_dq[6]}] +set_property SLEW FAST [get_ports {ddram_dq[6]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[6]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[6]}] + +# ddram:0.dq +set_property LOC M2 [get_ports {ddram_dq[7]}] +set_property SLEW FAST [get_ports {ddram_dq[7]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[7]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[7]}] + +# ddram:0.dq +set_property LOC V4 [get_ports {ddram_dq[8]}] +set_property SLEW FAST [get_ports {ddram_dq[8]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[8]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[8]}] + +# ddram:0.dq +set_property LOC T5 [get_ports {ddram_dq[9]}] +set_property SLEW FAST [get_ports {ddram_dq[9]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[9]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[9]}] + +# ddram:0.dq +set_property LOC U4 [get_ports {ddram_dq[10]}] +set_property SLEW FAST [get_ports {ddram_dq[10]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[10]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[10]}] + +# ddram:0.dq +set_property LOC V5 [get_ports {ddram_dq[11]}] +set_property SLEW FAST [get_ports {ddram_dq[11]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[11]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[11]}] + +# ddram:0.dq +set_property LOC V1 [get_ports {ddram_dq[12]}] +set_property SLEW FAST [get_ports {ddram_dq[12]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[12]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[12]}] + +# ddram:0.dq +set_property LOC T3 [get_ports {ddram_dq[13]}] +set_property SLEW FAST [get_ports {ddram_dq[13]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[13]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[13]}] + +# ddram:0.dq +set_property LOC U3 [get_ports {ddram_dq[14]}] +set_property SLEW FAST [get_ports {ddram_dq[14]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[14]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[14]}] + +# ddram:0.dq +set_property LOC R3 [get_ports {ddram_dq[15]}] +set_property SLEW FAST [get_ports {ddram_dq[15]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[15]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[15]}] + +# ddram:0.dqs_p +set_property LOC N2 [get_ports {ddram_dqs_p[0]}] +set_property SLEW FAST [get_ports {ddram_dqs_p[0]}] +set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_p[0]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[0]}] + +# ddram:0.dqs_p +set_property LOC U2 [get_ports {ddram_dqs_p[1]}] +set_property SLEW FAST [get_ports {ddram_dqs_p[1]}] +set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_p[1]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[1]}] + +# ddram:0.dqs_n +set_property LOC N1 [get_ports {ddram_dqs_n[0]}] +set_property SLEW FAST [get_ports {ddram_dqs_n[0]}] +set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_n[0]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[0]}] + +# ddram:0.dqs_n +set_property LOC V2 [get_ports {ddram_dqs_n[1]}] +set_property SLEW FAST [get_ports {ddram_dqs_n[1]}] +set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_n[1]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[1]}] + +# ddram:0.clk_p +set_property LOC U9 [get_ports {ddram_clk_p}] +set_property SLEW FAST [get_ports {ddram_clk_p}] +set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_clk_p}] + +# ddram:0.clk_n +set_property LOC V9 [get_ports {ddram_clk_n}] +set_property SLEW FAST [get_ports {ddram_clk_n}] +set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_clk_n}] + +# ddram:0.cke +set_property LOC N5 [get_ports {ddram_cke}] +set_property SLEW FAST [get_ports {ddram_cke}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_cke}] + +# ddram:0.odt +set_property LOC R5 [get_ports {ddram_odt}] +set_property SLEW FAST [get_ports {ddram_odt}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_odt}] + +# ddram:0.reset_n +set_property LOC K6 [get_ports {ddram_reset_n}] +set_property SLEW FAST [get_ports {ddram_reset_n}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_reset_n}] + +################################################################################ +# Design constraints and bitsteam attributes +################################################################################ #Internal VREF set_property INTERNAL_VREF 0.675 [get_iobanks 34] @@ -237,3 +303,17 @@ set_property CFGBVS VCCO [current_design] set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] set_property CONFIG_MODE SPIx4 [current_design] + +################################################################################ +# Clock constraints +################################################################################ + +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { ext_clk }]; + +################################################################################ +# False path constraints (from LiteX as they relate to LiteDRAM) +################################################################################ + +set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]] + +set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]] diff --git a/fpga/nexys-video.xdc b/fpga/nexys-video.xdc index aa840c7..358c382 100644 --- a/fpga/nexys-video.xdc +++ b/fpga/nexys-video.xdc @@ -1,231 +1,293 @@ +################################################################################ +# clkin, reset, uart pins... +################################################################################ + set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports ext_clk] -create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports ext_clk] set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS15} [get_ports ext_rst] set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports uart_main_tx] set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports uart_main_rx] -##Pmod Header JA: UART (bottom) +################################################################################ +# Pmod Header JC: UART (bottom) +################################################################################ + +#set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_cts_n }]; +#set_property -dict { PACKAGE_PIN AA21 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_tx }]; +#set_property -dict { PACKAGE_PIN AA20 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rx }]; +#set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rts_n }]; -set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_cts_n }]; -set_property -dict { PACKAGE_PIN AA21 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_tx }]; -set_property -dict { PACKAGE_PIN AA20 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rx }]; -set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rts_n }]; +################################################################################ +# LEDs +################################################################################ -# LEDs (no colors, just normal LEDs here) set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { led0 }]; set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led1 }]; +################################################################################ # DRAM (generated by LiteX) - ## ddram:0.a -set_property LOC M2 [get_ports ddram_a[0]] -set_property SLEW FAST [get_ports ddram_a[0]] -set_property IOSTANDARD SSTL15 [get_ports ddram_a[0]] - ## ddram:0.a -set_property LOC M5 [get_ports ddram_a[1]] -set_property SLEW FAST [get_ports ddram_a[1]] -set_property IOSTANDARD SSTL15 [get_ports ddram_a[1]] - ## ddram:0.a -set_property LOC M3 [get_ports ddram_a[2]] -set_property SLEW FAST [get_ports ddram_a[2]] -set_property IOSTANDARD SSTL15 [get_ports ddram_a[2]] - ## ddram:0.a -set_property LOC M1 [get_ports ddram_a[3]] -set_property SLEW FAST [get_ports ddram_a[3]] -set_property IOSTANDARD SSTL15 [get_ports ddram_a[3]] - ## ddram:0.a -set_property LOC L6 [get_ports ddram_a[4]] -set_property SLEW FAST [get_ports ddram_a[4]] -set_property IOSTANDARD SSTL15 [get_ports ddram_a[4]] - ## ddram:0.a -set_property LOC P1 [get_ports ddram_a[5]] -set_property SLEW FAST [get_ports ddram_a[5]] -set_property IOSTANDARD SSTL15 [get_ports ddram_a[5]] - ## ddram:0.a -set_property LOC N3 [get_ports ddram_a[6]] -set_property SLEW FAST [get_ports ddram_a[6]] -set_property IOSTANDARD SSTL15 [get_ports ddram_a[6]] - ## ddram:0.a -set_property LOC N2 [get_ports ddram_a[7]] -set_property SLEW FAST [get_ports ddram_a[7]] -set_property IOSTANDARD SSTL15 [get_ports ddram_a[7]] - ## ddram:0.a -set_property LOC M6 [get_ports ddram_a[8]] -set_property SLEW FAST [get_ports ddram_a[8]] -set_property IOSTANDARD SSTL15 [get_ports ddram_a[8]] - ## ddram:0.a -set_property LOC R1 [get_ports ddram_a[9]] -set_property SLEW FAST [get_ports ddram_a[9]] -set_property IOSTANDARD SSTL15 [get_ports ddram_a[9]] - ## ddram:0.a -set_property LOC L5 [get_ports ddram_a[10]] -set_property SLEW FAST [get_ports ddram_a[10]] -set_property IOSTANDARD SSTL15 [get_ports ddram_a[10]] - ## ddram:0.a -set_property LOC N5 [get_ports ddram_a[11]] -set_property SLEW FAST [get_ports ddram_a[11]] -set_property IOSTANDARD SSTL15 [get_ports ddram_a[11]] - ## ddram:0.a -set_property LOC N4 [get_ports ddram_a[12]] -set_property SLEW FAST [get_ports ddram_a[12]] -set_property IOSTANDARD SSTL15 [get_ports ddram_a[12]] - ## ddram:0.a -set_property LOC P2 [get_ports ddram_a[13]] -set_property SLEW FAST [get_ports ddram_a[13]] -set_property IOSTANDARD SSTL15 [get_ports ddram_a[13]] - ## ddram:0.a -set_property LOC P6 [get_ports ddram_a[14]] -set_property SLEW FAST [get_ports ddram_a[14]] -set_property IOSTANDARD SSTL15 [get_ports ddram_a[14]] - ## ddram:0.ba -set_property LOC L3 [get_ports ddram_ba[0]] -set_property SLEW FAST [get_ports ddram_ba[0]] -set_property IOSTANDARD SSTL15 [get_ports ddram_ba[0]] - ## ddram:0.ba -set_property LOC K6 [get_ports ddram_ba[1]] -set_property SLEW FAST [get_ports ddram_ba[1]] -set_property IOSTANDARD SSTL15 [get_ports ddram_ba[1]] - ## ddram:0.ba -set_property LOC L4 [get_ports ddram_ba[2]] -set_property SLEW FAST [get_ports ddram_ba[2]] -set_property IOSTANDARD SSTL15 [get_ports ddram_ba[2]] - ## ddram:0.ras_n -set_property LOC J4 [get_ports ddram_ras_n] -set_property SLEW FAST [get_ports ddram_ras_n] -set_property IOSTANDARD SSTL15 [get_ports ddram_ras_n] - ## ddram:0.cas_n -set_property LOC K3 [get_ports ddram_cas_n] -set_property SLEW FAST [get_ports ddram_cas_n] -set_property IOSTANDARD SSTL15 [get_ports ddram_cas_n] - ## ddram:0.we_n -set_property LOC L1 [get_ports ddram_we_n] -set_property SLEW FAST [get_ports ddram_we_n] -set_property IOSTANDARD SSTL15 [get_ports ddram_we_n] - ## ddram:0.dm -set_property LOC G3 [get_ports ddram_dm[0]] -set_property SLEW FAST [get_ports ddram_dm[0]] -set_property IOSTANDARD SSTL15 [get_ports ddram_dm[0]] - ## ddram:0.dm -set_property LOC F1 [get_ports ddram_dm[1]] -set_property SLEW FAST [get_ports ddram_dm[1]] -set_property IOSTANDARD SSTL15 [get_ports ddram_dm[1]] - ## ddram:0.dq -set_property LOC G2 [get_ports ddram_dq[0]] -set_property SLEW FAST [get_ports ddram_dq[0]] -set_property IOSTANDARD SSTL15 [get_ports ddram_dq[0]] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[0]] - ## ddram:0.dq -set_property LOC H4 [get_ports ddram_dq[1]] -set_property SLEW FAST [get_ports ddram_dq[1]] -set_property IOSTANDARD SSTL15 [get_ports ddram_dq[1]] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[1]] - ## ddram:0.dq -set_property LOC H5 [get_ports ddram_dq[2]] -set_property SLEW FAST [get_ports ddram_dq[2]] -set_property IOSTANDARD SSTL15 [get_ports ddram_dq[2]] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[2]] - ## ddram:0.dq -set_property LOC J1 [get_ports ddram_dq[3]] -set_property SLEW FAST [get_ports ddram_dq[3]] -set_property IOSTANDARD SSTL15 [get_ports ddram_dq[3]] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[3]] - ## ddram:0.dq -set_property LOC K1 [get_ports ddram_dq[4]] -set_property SLEW FAST [get_ports ddram_dq[4]] -set_property IOSTANDARD SSTL15 [get_ports ddram_dq[4]] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[4]] - ## ddram:0.dq -set_property LOC H3 [get_ports ddram_dq[5]] -set_property SLEW FAST [get_ports ddram_dq[5]] -set_property IOSTANDARD SSTL15 [get_ports ddram_dq[5]] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[5]] - ## ddram:0.dq -set_property LOC H2 [get_ports ddram_dq[6]] -set_property SLEW FAST [get_ports ddram_dq[6]] -set_property IOSTANDARD SSTL15 [get_ports ddram_dq[6]] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[6]] - ## ddram:0.dq -set_property LOC J5 [get_ports ddram_dq[7]] -set_property SLEW FAST [get_ports ddram_dq[7]] -set_property IOSTANDARD SSTL15 [get_ports ddram_dq[7]] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[7]] - ## ddram:0.dq -set_property LOC E3 [get_ports ddram_dq[8]] -set_property SLEW FAST [get_ports ddram_dq[8]] -set_property IOSTANDARD SSTL15 [get_ports ddram_dq[8]] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[8]] - ## ddram:0.dq -set_property LOC B2 [get_ports ddram_dq[9]] -set_property SLEW FAST [get_ports ddram_dq[9]] -set_property IOSTANDARD SSTL15 [get_ports ddram_dq[9]] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[9]] - ## ddram:0.dq -set_property LOC F3 [get_ports ddram_dq[10]] -set_property SLEW FAST [get_ports ddram_dq[10]] -set_property IOSTANDARD SSTL15 [get_ports ddram_dq[10]] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[10]] - ## ddram:0.dq -set_property LOC D2 [get_ports ddram_dq[11]] -set_property SLEW FAST [get_ports ddram_dq[11]] -set_property IOSTANDARD SSTL15 [get_ports ddram_dq[11]] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[11]] - ## ddram:0.dq -set_property LOC C2 [get_ports ddram_dq[12]] -set_property SLEW FAST [get_ports ddram_dq[12]] -set_property IOSTANDARD SSTL15 [get_ports ddram_dq[12]] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[12]] - ## ddram:0.dq -set_property LOC A1 [get_ports ddram_dq[13]] -set_property SLEW FAST [get_ports ddram_dq[13]] -set_property IOSTANDARD SSTL15 [get_ports ddram_dq[13]] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[13]] - ## ddram:0.dq -set_property LOC E2 [get_ports ddram_dq[14]] -set_property SLEW FAST [get_ports ddram_dq[14]] -set_property IOSTANDARD SSTL15 [get_ports ddram_dq[14]] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[14]] - ## ddram:0.dq -set_property LOC B1 [get_ports ddram_dq[15]] -set_property SLEW FAST [get_ports ddram_dq[15]] -set_property IOSTANDARD SSTL15 [get_ports ddram_dq[15]] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[15]] - ## ddram:0.dqs_p -set_property LOC K2 [get_ports ddram_dqs_p[0]] -set_property SLEW FAST [get_ports ddram_dqs_p[0]] -set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_p[0]] - ## ddram:0.dqs_p -set_property LOC E1 [get_ports ddram_dqs_p[1]] -set_property SLEW FAST [get_ports ddram_dqs_p[1]] -set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_p[1]] - ## ddram:0.dqs_n -set_property LOC J2 [get_ports ddram_dqs_n[0]] -set_property SLEW FAST [get_ports ddram_dqs_n[0]] -set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_n[0]] - ## ddram:0.dqs_n -set_property LOC D1 [get_ports ddram_dqs_n[1]] -set_property SLEW FAST [get_ports ddram_dqs_n[1]] -set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_n[1]] - ## ddram:0.clk_p -set_property LOC P5 [get_ports ddram_clk_p] -set_property SLEW FAST [get_ports ddram_clk_p] -set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_clk_p] - ## ddram:0.clk_n -set_property LOC P4 [get_ports ddram_clk_n] -set_property SLEW FAST [get_ports ddram_clk_n] -set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_clk_n] - ## ddram:0.cke -set_property LOC J6 [get_ports ddram_cke] -set_property SLEW FAST [get_ports ddram_cke] -set_property IOSTANDARD SSTL15 [get_ports ddram_cke] - ## ddram:0.odt -set_property LOC K4 [get_ports ddram_odt] -set_property SLEW FAST [get_ports ddram_odt] -set_property IOSTANDARD SSTL15 [get_ports ddram_odt] - ## ddram:0.reset_n -set_property LOC G1 [get_ports ddram_reset_n] -set_property SLEW FAST [get_ports ddram_reset_n] -set_property IOSTANDARD SSTL15 [get_ports ddram_reset_n] +################################################################################ + +# ddram:0.a +set_property LOC M2 [get_ports {ddram_a[0]}] +set_property SLEW FAST [get_ports {ddram_a[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[0]}] + +# ddram:0.a +set_property LOC M5 [get_ports {ddram_a[1]}] +set_property SLEW FAST [get_ports {ddram_a[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[1]}] + +# ddram:0.a +set_property LOC M3 [get_ports {ddram_a[2]}] +set_property SLEW FAST [get_ports {ddram_a[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[2]}] + +# ddram:0.a +set_property LOC M1 [get_ports {ddram_a[3]}] +set_property SLEW FAST [get_ports {ddram_a[3]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[3]}] + +# ddram:0.a +set_property LOC L6 [get_ports {ddram_a[4]}] +set_property SLEW FAST [get_ports {ddram_a[4]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[4]}] + +# ddram:0.a +set_property LOC P1 [get_ports {ddram_a[5]}] +set_property SLEW FAST [get_ports {ddram_a[5]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[5]}] + +# ddram:0.a +set_property LOC N3 [get_ports {ddram_a[6]}] +set_property SLEW FAST [get_ports {ddram_a[6]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[6]}] + +# ddram:0.a +set_property LOC N2 [get_ports {ddram_a[7]}] +set_property SLEW FAST [get_ports {ddram_a[7]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[7]}] + +# ddram:0.a +set_property LOC M6 [get_ports {ddram_a[8]}] +set_property SLEW FAST [get_ports {ddram_a[8]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[8]}] + +# ddram:0.a +set_property LOC R1 [get_ports {ddram_a[9]}] +set_property SLEW FAST [get_ports {ddram_a[9]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[9]}] + +# ddram:0.a +set_property LOC L5 [get_ports {ddram_a[10]}] +set_property SLEW FAST [get_ports {ddram_a[10]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[10]}] + +# ddram:0.a +set_property LOC N5 [get_ports {ddram_a[11]}] +set_property SLEW FAST [get_ports {ddram_a[11]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[11]}] + +# ddram:0.a +set_property LOC N4 [get_ports {ddram_a[12]}] +set_property SLEW FAST [get_ports {ddram_a[12]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[12]}] + +# ddram:0.a +set_property LOC P2 [get_ports {ddram_a[13]}] +set_property SLEW FAST [get_ports {ddram_a[13]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[13]}] + +# ddram:0.a +set_property LOC P6 [get_ports {ddram_a[14]}] +set_property SLEW FAST [get_ports {ddram_a[14]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[14]}] + +# ddram:0.ba +set_property LOC L3 [get_ports {ddram_ba[0]}] +set_property SLEW FAST [get_ports {ddram_ba[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[0]}] + +# ddram:0.ba +set_property LOC K6 [get_ports {ddram_ba[1]}] +set_property SLEW FAST [get_ports {ddram_ba[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[1]}] + +# ddram:0.ba +set_property LOC L4 [get_ports {ddram_ba[2]}] +set_property SLEW FAST [get_ports {ddram_ba[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[2]}] + +# ddram:0.ras_n +set_property LOC J4 [get_ports {ddram_ras_n}] +set_property SLEW FAST [get_ports {ddram_ras_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_ras_n}] + +# ddram:0.cas_n +set_property LOC K3 [get_ports {ddram_cas_n}] +set_property SLEW FAST [get_ports {ddram_cas_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_cas_n}] + +# ddram:0.we_n +set_property LOC L1 [get_ports {ddram_we_n}] +set_property SLEW FAST [get_ports {ddram_we_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_we_n}] + +# ddram:0.dm +set_property LOC G3 [get_ports {ddram_dm[0]}] +set_property SLEW FAST [get_ports {ddram_dm[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[0]}] + +# ddram:0.dm +set_property LOC F1 [get_ports {ddram_dm[1]}] +set_property SLEW FAST [get_ports {ddram_dm[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[1]}] + +# ddram:0.dq +set_property LOC G2 [get_ports {ddram_dq[0]}] +set_property SLEW FAST [get_ports {ddram_dq[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[0]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[0]}] + +# ddram:0.dq +set_property LOC H4 [get_ports {ddram_dq[1]}] +set_property SLEW FAST [get_ports {ddram_dq[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[1]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[1]}] + +# ddram:0.dq +set_property LOC H5 [get_ports {ddram_dq[2]}] +set_property SLEW FAST [get_ports {ddram_dq[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[2]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[2]}] + +# ddram:0.dq +set_property LOC J1 [get_ports {ddram_dq[3]}] +set_property SLEW FAST [get_ports {ddram_dq[3]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[3]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[3]}] + +# ddram:0.dq +set_property LOC K1 [get_ports {ddram_dq[4]}] +set_property SLEW FAST [get_ports {ddram_dq[4]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[4]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[4]}] + +# ddram:0.dq +set_property LOC H3 [get_ports {ddram_dq[5]}] +set_property SLEW FAST [get_ports {ddram_dq[5]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[5]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[5]}] + +# ddram:0.dq +set_property LOC H2 [get_ports {ddram_dq[6]}] +set_property SLEW FAST [get_ports {ddram_dq[6]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[6]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[6]}] + +# ddram:0.dq +set_property LOC J5 [get_ports {ddram_dq[7]}] +set_property SLEW FAST [get_ports {ddram_dq[7]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[7]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[7]}] + +# ddram:0.dq +set_property LOC E3 [get_ports {ddram_dq[8]}] +set_property SLEW FAST [get_ports {ddram_dq[8]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[8]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[8]}] + +# ddram:0.dq +set_property LOC B2 [get_ports {ddram_dq[9]}] +set_property SLEW FAST [get_ports {ddram_dq[9]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[9]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[9]}] + +# ddram:0.dq +set_property LOC F3 [get_ports {ddram_dq[10]}] +set_property SLEW FAST [get_ports {ddram_dq[10]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[10]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[10]}] + +# ddram:0.dq +set_property LOC D2 [get_ports {ddram_dq[11]}] +set_property SLEW FAST [get_ports {ddram_dq[11]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[11]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[11]}] + +# ddram:0.dq +set_property LOC C2 [get_ports {ddram_dq[12]}] +set_property SLEW FAST [get_ports {ddram_dq[12]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[12]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[12]}] + +# ddram:0.dq +set_property LOC A1 [get_ports {ddram_dq[13]}] +set_property SLEW FAST [get_ports {ddram_dq[13]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[13]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[13]}] + +# ddram:0.dq +set_property LOC E2 [get_ports {ddram_dq[14]}] +set_property SLEW FAST [get_ports {ddram_dq[14]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[14]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[14]}] + +# ddram:0.dq +set_property LOC B1 [get_ports {ddram_dq[15]}] +set_property SLEW FAST [get_ports {ddram_dq[15]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[15]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[15]}] + +# ddram:0.dqs_p +set_property LOC K2 [get_ports {ddram_dqs_p[0]}] +set_property SLEW FAST [get_ports {ddram_dqs_p[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[0]}] + +# ddram:0.dqs_p +set_property LOC E1 [get_ports {ddram_dqs_p[1]}] +set_property SLEW FAST [get_ports {ddram_dqs_p[1]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[1]}] + +# ddram:0.dqs_n +set_property LOC J2 [get_ports {ddram_dqs_n[0]}] +set_property SLEW FAST [get_ports {ddram_dqs_n[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[0]}] + +# ddram:0.dqs_n +set_property LOC D1 [get_ports {ddram_dqs_n[1]}] +set_property SLEW FAST [get_ports {ddram_dqs_n[1]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[1]}] + +# ddram:0.clk_p +set_property LOC P5 [get_ports {ddram_clk_p}] +set_property SLEW FAST [get_ports {ddram_clk_p}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_p}] + +# ddram:0.clk_n +set_property LOC P4 [get_ports {ddram_clk_n}] +set_property SLEW FAST [get_ports {ddram_clk_n}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_n}] + +# ddram:0.cke +set_property LOC J6 [get_ports {ddram_cke}] +set_property SLEW FAST [get_ports {ddram_cke}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_cke}] + +# ddram:0.odt +set_property LOC K4 [get_ports {ddram_odt}] +set_property SLEW FAST [get_ports {ddram_odt}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_odt}] + +# ddram:0.reset_n +set_property LOC G1 [get_ports {ddram_reset_n}] +set_property SLEW FAST [get_ports {ddram_reset_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_reset_n}] + +################################################################################ +# Design constraints and bitsteam attributes +################################################################################ #Internal VREF set_property INTERNAL_VREF 0.750 [get_iobanks 35] @@ -236,3 +298,17 @@ set_property CFGBVS VCCO [current_design] set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] set_property CONFIG_MODE SPIx4 [current_design] + +################################################################################ +# Clock constraints +################################################################################ + +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { ext_clk }]; + +################################################################################ +# False path constraints (from LiteX as they relate to LiteDRAM) +################################################################################ + +set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]] + +set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]] diff --git a/litedram/extras/litedram-wrapper-l2.vhdl b/litedram/extras/litedram-wrapper-l2.vhdl index f2392f6..61b4867 100644 --- a/litedram/extras/litedram-wrapper-l2.vhdl +++ b/litedram/extras/litedram-wrapper-l2.vhdl @@ -235,20 +235,27 @@ architecture behaviour of litedram_wrapper is -- Cache state machine type state_t is (IDLE, -- Normal load hit processing + REFILL_CLR_TAG, -- Cache refill clear tag REFILL_WAIT_ACK); -- Cache refill wait ack signal state : state_t; - -- Latched WB request. - signal wb_req : wishbone_master_out := wishbone_master_out_init; + -- Latched WB request + signal wb_req : wishbone_master_out := wishbone_master_out_init; + -- Stashed WB request + signal wb_stash : wishbone_master_out := wishbone_master_out_init; -- Read pipeline (to handle cache RAM latency) - signal read_ack_0 : std_ulogic; - signal read_ack_1 : std_ulogic; + signal read_ack_0 : std_ulogic := '0'; + signal read_ack_1 : std_ulogic := '0'; signal read_ad3_0 : std_ulogic; signal read_ad3_1 : std_ulogic; signal read_way_0 : way_t; signal read_way_1 : way_t; + -- Store ack pipeline + signal store_ack_0 : std_ulogic := '0'; + signal store_ack_1 : std_ulogic := '0'; + -- Async signals decoding latched request type req_op_t is (OP_NONE, OP_LOAD_HIT, @@ -266,6 +273,7 @@ architecture behaviour of litedram_wrapper is signal req_we : std_ulogic_vector(DRAM_SBITS-1 downto 0); signal req_wdata : std_ulogic_vector(DRAM_DBITS-1 downto 0); signal accept_store : std_ulogic; + signal stall : std_ulogic; -- Line refill command signals and latches signal refill_cmd_valid : std_ulogic; @@ -573,31 +581,54 @@ begin request_latch: process(system_clk) begin if rising_edge(system_clk) then - -- We can latch a new request if we are idle (for now). We also - -- latch the absence of request. This is a pipeline that takes - -- one per-cycle unless non-IDLE. - -- - if wb_out.stall = '0' then - -- Avoid constantly updating addr/data for unrelated requests - if wb_in.cyc = '1' then - wb_req <= wb_in; + + -- Implement a stash buffer. If we are stalled and stash is + -- free, fill it up. This will generate a WB stall on the + -- next cycle. + if stall = '1' and wb_out.stall = '0' and wb_in.cyc = '1' and wb_in.stb = '1' then + wb_stash <= wb_in; + if TRACE then + report "stashed wb req ! addr:" & to_hstring(wb_in.adr) & + " we:" & std_ulogic'image(wb_in.we) & + " sel:" & to_hstring(wb_in.sel); + end if; + end if; + + -- We aren't stalled, see what we can do + if stall = '0' then + if wb_stash.cyc = '1' then + -- Something in stash ! use it and clear stash + wb_req <= wb_stash; + wb_stash.cyc <= '0'; + if TRACE then + report "unstashed wb req ! addr:" & to_hstring(wb_stash.adr) & + " we:" & std_ulogic'image(wb_stash.we) & + " sel:" & to_hstring(wb_stash.sel); + end if; else - wb_req.cyc <= wb_in.cyc; - wb_req.stb <= wb_in.stb; - end if; + -- Grab request from WB + if wb_in.cyc = '1' then + wb_req <= wb_in; + else + wb_req.cyc <= wb_in.cyc; + wb_req.stb <= wb_in.stb; + end if; - if TRACE then - if wb_in.cyc = '1' and wb_in.stb = '1' then - report "latch new wb req ! addr:" & to_hstring(wb_in.adr) & - " we:" & std_ulogic'image(wb_in.we) & - " sel:" & to_hstring(wb_in.sel); + if TRACE then + if wb_in.cyc = '1' and wb_in.stb = '1' then + report "latch new wb req ! addr:" & to_hstring(wb_in.adr) & + " we:" & std_ulogic'image(wb_in.we) & + " sel:" & to_hstring(wb_in.sel); + end if; end if; end if; end if; end if; end process; - -- + -- Stall when stash is full + wb_out.stall <= wb_stash.cyc; + -- -- Read response pipeline -- @@ -629,6 +660,16 @@ begin end if; end process; + -- + -- Store acks pipeline + -- + store_ack_pipe: process(system_clk) + begin + if rising_edge(system_clk) then + store_ack_1 <= store_ack_0; + end if; + end process; + wb_reponse: process(all) variable rdata : std_ulogic_vector(DRAM_DBITS-1 downto 0); variable store_done : std_ulogic; @@ -668,14 +709,14 @@ begin when IDLE => case req_op is when OP_LOAD_MISS => - wb_out.stall <= '1'; + stall <= '1'; when OP_STORE_MISS | OP_STORE_HIT => - wb_out.stall <= not accept_store; + stall <= not accept_store; when others => - wb_out.stall <= '0'; + stall <= '0'; end case; - when REFILL_WAIT_ACK => - wb_out.stall <= '1'; + when others => + stall <= '1'; end case; -- Data out mux @@ -689,15 +730,16 @@ begin store_done := '0'; end if; - -- Generate ACKs on read hits and store complete + -- Pipeline store acks + store_ack_0 <= store_done; + + -- Generate Wishbone ACKs on read hits and store complete -- - -- XXXX TODO: This can happen on store right behind loads ! - -- This probably need to be fixed by putting store acks in - -- the same pipeline as the read acks. TOOD: Create a testbench - -- to exercise those corner cases as the core can't yet. + -- This can happen on store right behind loads ! This is why + -- we don't accept a new store right behind a load ack above. -- - wb_out.ack <= read_ack_1 or store_done; - assert read_ack_0 = '0' or store_done = '0' report + wb_out.ack <= read_ack_1 or store_ack_1; + assert read_ack_1 = '0' or store_ack_1 = '0' report "Read ack and store ack collision !" severity failure; end process; @@ -859,7 +901,6 @@ begin refill_machine : process(system_clk) variable tagset : cache_tags_set_t; variable cmds_done : boolean; - variable replace_way : way_t; variable wait_qdrain : boolean; begin if rising_edge(system_clk) then @@ -887,23 +928,10 @@ begin -- We need to read a cache line if req_op = OP_LOAD_MISS and not wait_qdrain then -- Grab way to replace - replace_way := to_integer(unsigned(plru_victim(req_index))); - - -- Force misses on that way while refilling that line - cache_valids(req_index)(replace_way) <= '0'; - - -- Store new tag in selected way - for i in 0 to NUM_WAYS-1 loop - if i = replace_way then - tagset := cache_tags(req_index); - write_tag(i, tagset, req_tag); - cache_tags(req_index) <= tagset; - end if; - end loop; + refill_way <= to_integer(unsigned(plru_victim(req_index))); -- Keep track of our index and way for subsequent stores refill_index <= req_index; - refill_way <= replace_way; refill_row <= get_row(req_laddr); -- Prep for first DRAM read @@ -921,10 +949,27 @@ begin end if; -- Track that we had one request sent + state <= REFILL_CLR_TAG; + end if; + + when REFILL_CLR_TAG | REFILL_WAIT_ACK => + + -- Delayed tag clearing to help timing on PLRU output + if state = REFILL_CLR_TAG then + -- Force misses on that way while refilling that line + cache_valids(req_index)(refill_way) <= '0'; + + -- Store new tag in selected way + for i in 0 to NUM_WAYS-1 loop + if i = refill_way then + tagset := cache_tags(refill_index); + write_tag(i, tagset, req_tag); + cache_tags(refill_index) <= tagset; + end if; + end loop; state <= REFILL_WAIT_ACK; end if; - when REFILL_WAIT_ACK => -- Commands are all sent if user_port0_cmd_valid is 0 cmds_done := refill_cmd_valid = '0';