diff --git a/countzero_tb.vhdl b/countzero_tb.vhdl index c51d4a7..f8319b9 100644 --- a/countzero_tb.vhdl +++ b/countzero_tb.vhdl @@ -19,8 +19,7 @@ architecture behave of countzero_tb is constant clk_period: time := 10 ns; signal rs: std_ulogic_vector(63 downto 0); signal is_32bit, count_right: std_ulogic := '0'; - signal result: std_ulogic_vector(63 downto 0); - signal randno: std_ulogic_vector(63 downto 0); + signal res: std_ulogic_vector(63 downto 0); signal clk: std_ulogic; begin @@ -28,7 +27,7 @@ begin port map ( clk => clk, rs => rs, - result => result, + result => res, count_right => count_right, is_32bit => is_32bit ); @@ -55,21 +54,17 @@ begin is_32bit <= '0'; count_right <= '0'; wait for clk_period; - assert result = x"0000000000000040" - report "bad cntlzd 0 = " & to_hstring(result); + check_equal(res, 16#40#, result("for cntlzd")); count_right <= '1'; wait for clk_period; - assert result = x"0000000000000040" - report "bad cnttzd 0 = " & to_hstring(result); + check_equal(res, 16#40#, result("for cnttzd")); is_32bit <= '1'; count_right <= '0'; wait for clk_period; - assert result = x"0000000000000020" - report "bad cntlzw 0 = " & to_hstring(result); + check_equal(res, 16#20#, result("for cntlzw")); count_right <= '1'; wait for clk_period; - assert result = x"0000000000000020" - report "bad cnttzw 0 = " & to_hstring(result); + check_equal(res, 16#20#, result("for cnttzw")); elsif run("Test cntlzd/w") then count_right <= '0'; @@ -80,17 +75,14 @@ begin rs <= r; is_32bit <= '0'; wait for clk_period; - assert to_integer(unsigned(result)) = i - report "bad cntlzd " & to_hstring(rs) & " -> " & to_hstring(result); + check_equal(res, i, result("for cntlzd " & to_hstring(rs))); rs <= r(31 downto 0) & r(63 downto 32); is_32bit <= '1'; wait for clk_period; if i < 32 then - assert to_integer(unsigned(result)) = i - report "bad cntlzw " & to_hstring(rs) & " -> " & to_hstring(result); + check_equal(res, i, result("for cntlzw " & to_hstring(rs))); else - assert to_integer(unsigned(result)) = 32 - report "bad cntlzw " & to_hstring(rs) & " -> " & to_hstring(result); + check_equal(res, 32, result("for cntlzw " & to_hstring(rs))); end if; r := '0' & r(63 downto 1); end loop; @@ -105,16 +97,13 @@ begin rs <= r; is_32bit <= '0'; wait for clk_period; - assert to_integer(unsigned(result)) = i - report "bad cnttzd " & to_hstring(rs) & " -> " & to_hstring(result); + check_equal(res, i, result("for cnttzd " & to_hstring(rs))); is_32bit <= '1'; wait for clk_period; if i < 32 then - assert to_integer(unsigned(result)) = i - report "bad cnttzw " & to_hstring(rs) & " -> " & to_hstring(result); + check_equal(res, i, result("for cnttzw " & to_hstring(rs))); else - assert to_integer(unsigned(result)) = 32 - report "bad cnttzw " & to_hstring(rs) & " -> " & to_hstring(result); + check_equal(res, 32, result("for cnttzw " & to_hstring(rs))); end if; r := r(62 downto 0) & '0'; end loop; diff --git a/divider_tb.vhdl b/divider_tb.vhdl index 4fee8f7..76e5baa 100644 --- a/divider_tb.vhdl +++ b/divider_tb.vhdl @@ -67,7 +67,7 @@ begin d1.divisor <= x"0000000000001111"; wait for clk_period; - assert d2.valid = '0'; + check_false(?? d2.valid, result("for valid")); d1.valid <= '0'; @@ -78,16 +78,16 @@ begin end if; end loop; - assert d2.valid = '1'; - assert d2.write_reg_data = x"000000000000f001" report "result " & to_hstring(d2.write_reg_data); + check_true(?? d2.valid, result("for valid")); + check_equal(d2.write_reg_data, 16#f001#); wait for clk_period; - assert d2.valid = '0' report "valid"; + check_false(?? d2.valid, result("for valid")); d1.valid <= '1'; wait for clk_period; - assert d2.valid = '0' report "valid"; + check_false(?? d2.valid, result("for valid")); d1.valid <= '0'; @@ -98,11 +98,11 @@ begin end if; end loop; - assert d2.valid = '1'; - assert d2.write_reg_data = x"000000000000f001" report "result " & to_hstring(d2.write_reg_data); + check_true(?? d2.valid, result("for valid")); + check_equal(d2.write_reg_data, 16#f001#); wait for clk_period; - assert d2.valid = '0'; + check_false(?? d2.valid, result("for valid")); elsif run("Test divd") then divd_loop : for dlength in 1 to 8 loop @@ -126,14 +126,13 @@ begin exit; end if; end loop; - assert d2.valid = '1'; + check_true(?? d2.valid, result("for valid")); behave_rt := (others => '0'); if rb /= x"0000000000000000" and (ra /= x"8000000000000000" or rb /= x"ffffffffffffffff") then behave_rt := ppc_divd(ra, rb); end if; - assert to_hstring(behave_rt) = to_hstring(d2.write_reg_data) - report "bad divd expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data); + check_equal(d2.write_reg_data, behave_rt, result("for divd")); end loop; end loop; end loop; @@ -158,14 +157,13 @@ begin exit; end if; end loop; - assert d2.valid = '1'; + check_true(?? d2.valid, result("for valid")); behave_rt := (others => '0'); if rb /= x"0000000000000000" then behave_rt := ppc_divdu(ra, rb); end if; - assert to_hstring(behave_rt) = to_hstring(d2.write_reg_data) - report "bad divdu expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data); + check_equal(d2.write_reg_data, behave_rt, result("for divdu")); end loop; end loop; end loop; @@ -193,7 +191,7 @@ begin exit; end if; end loop; - assert d2.valid = '1'; + check_true(?? d2.valid, result("for valid")); behave_rt := (others => '0'); if rb /= x"0000000000000000" then @@ -204,8 +202,7 @@ begin behave_rt := q128(63 downto 0); end if; end if; - assert to_hstring(behave_rt) = to_hstring(d2.write_reg_data) - report "bad divde expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data) & " for ra = " & to_hstring(ra) & " rb = " & to_hstring(rb); + check_equal(d2.write_reg_data, behave_rt, result("for divde")); end loop; end loop; end loop; @@ -231,7 +228,7 @@ begin exit; end if; end loop; - assert d2.valid = '1'; + check_true(?? d2.valid, result("for valid")); behave_rt := (others => '0'); if unsigned(rb) > unsigned(ra) then @@ -239,8 +236,7 @@ begin q128 := std_ulogic_vector(unsigned(d128) / unsigned(rb)); behave_rt := q128(63 downto 0); end if; - assert to_hstring(behave_rt) = to_hstring(d2.write_reg_data) - report "bad divdeu expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data) & " for ra = " & to_hstring(ra) & " rb = " & to_hstring(rb); + check_equal(d2.write_reg_data, behave_rt, result("for divdeu")); end loop; end loop; end loop; @@ -268,14 +264,13 @@ begin exit; end if; end loop; - assert d2.valid = '1'; + check_true(?? d2.valid, result("for valid")); behave_rt := (others => '0'); if rb /= x"0000000000000000" and (ra /= x"ffffffff80000000" or rb /= x"ffffffffffffffff") then behave_rt := ppc_divw(ra, rb); end if; - assert behave_rt = d2.write_reg_data - report "bad divw expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data); + check_equal(d2.write_reg_data, behave_rt, result("for divw")); end loop; end loop; end loop; @@ -301,14 +296,13 @@ begin exit; end if; end loop; - assert d2.valid = '1'; + check_true(?? d2.valid, result("for valid")); behave_rt := (others => '0'); if rb /= x"0000000000000000" then behave_rt := ppc_divwu(ra, rb); end if; - assert behave_rt = d2.write_reg_data - report "bad divwu expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data); + check_equal(d2.write_reg_data, behave_rt, result("for divwu")); end loop; end loop; end loop; @@ -336,7 +330,7 @@ begin exit; end if; end loop; - assert d2.valid = '1'; + check_true(?? d2.valid, result("for valid")); behave_rt := (others => '0'); if rb /= x"0000000000000000" then @@ -345,8 +339,7 @@ begin q64(63 downto 31) = x"ffffffff" & '1' then behave_rt := x"00000000" & q64(31 downto 0); end if; - assert behave_rt = d2.write_reg_data - report "bad divwe expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data) & " for ra = " & to_hstring(ra) & " rb = " & to_hstring(rb); + check_equal(d2.write_reg_data, behave_rt, result("for divwe")); end if; end loop; end loop; @@ -373,14 +366,13 @@ begin exit; end if; end loop; - assert d2.valid = '1'; + check_true(?? d2.valid, result("for valid")); behave_rt := (others => '0'); if unsigned(rb(31 downto 0)) > unsigned(ra(63 downto 32)) then behave_rt := std_ulogic_vector(unsigned(ra) / unsigned(rb)); end if; - assert behave_rt = d2.write_reg_data - report "bad divweu expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data) & " for ra = " & to_hstring(ra) & " rb = " & to_hstring(rb); + check_equal(d2.write_reg_data, behave_rt, result("for divweu")); end loop; end loop; end loop; @@ -408,14 +400,13 @@ begin exit; end if; end loop; - assert d2.valid = '1'; + check_true(?? d2.valid, result("for valid")); behave_rt := (others => '0'); if rb /= x"0000000000000000" then behave_rt := std_ulogic_vector(signed(ra) rem signed(rb)); end if; - assert behave_rt = d2.write_reg_data - report "bad modsd expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data); + check_equal(d2.write_reg_data, behave_rt, result("for modsd")); end loop; end loop; end loop; @@ -441,14 +432,13 @@ begin exit; end if; end loop; - assert d2.valid = '1'; + check_true(?? d2.valid, result("for valid")); behave_rt := (others => '0'); if rb /= x"0000000000000000" then behave_rt := std_ulogic_vector(unsigned(ra) rem unsigned(rb)); end if; - assert behave_rt = d2.write_reg_data - report "bad modud expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data); + check_equal(d2.write_reg_data, behave_rt, result("for modud")); end loop; end loop; end loop; @@ -477,7 +467,7 @@ begin exit; end if; end loop; - assert d2.valid = '1'; + check_true(?? d2.valid, result("for valid")); behave_rt := (others => '0'); if rb /= x"0000000000000000" then @@ -488,8 +478,7 @@ begin behave_rt := x"ffffffff" & rem32; end if; end if; - assert behave_rt = d2.write_reg_data - report "bad modsw expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data); + check_equal(d2.write_reg_data, behave_rt, result("for modsw")); end loop; end loop; end loop; @@ -516,14 +505,13 @@ begin exit; end if; end loop; - assert d2.valid = '1'; + check_true(?? d2.valid, result("for valid")); behave_rt := (others => '0'); if rb /= x"0000000000000000" then behave_rt := x"00000000" & std_ulogic_vector(unsigned(ra(31 downto 0)) rem unsigned(rb(31 downto 0))); end if; - assert behave_rt(31 downto 0) = d2.write_reg_data(31 downto 0) - report "bad moduw expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data); + check_equal(d2.write_reg_data(31 downto 0), behave_rt(31 downto 0), result("for moduw")); end loop; end loop; end loop; diff --git a/multiply_tb.vhdl b/multiply_tb.vhdl index 57a9386..5b13e14 100644 --- a/multiply_tb.vhdl +++ b/multiply_tb.vhdl @@ -67,33 +67,33 @@ begin m1.data2 <= x"0000000000001111"; wait for clk_period; - assert m2.valid = '0'; + check_false(?? m2.valid, result("for valid")); m1.valid <= '0'; wait for clk_period; - assert m2.valid = '0'; + check_false(?? m2.valid, result("for valid")); wait for clk_period; - assert m2.valid = '0'; + check_false(?? m2.valid, result("for valid")); wait for clk_period; - assert m2.valid = '1'; - assert m2.result = x"00000000000000000000000001111000"; + check_true(?? m2.valid, result("for valid")); + check_equal(m2.result, 16#1111000#); wait for clk_period; - assert m2.valid = '0'; + check_false(?? m2.valid, result("for valid")); m1.valid <= '1'; wait for clk_period; - assert m2.valid = '0'; + check_false(?? m2.valid, result("for valid")); m1.valid <= '0'; wait for clk_period * (pipeline_depth-1); - assert m2.valid = '1'; - assert m2.result = x"00000000000000000000000001111000"; + check_true(?? m2.valid, result("for valid")); + check_equal(m2.result, 16#1111000#); elsif run("Test mulld") then mulld_loop : for i in 0 to 1000 loop @@ -115,10 +115,8 @@ begin wait for clk_period * (pipeline_depth-1); - assert m2.valid = '1'; - - assert to_hstring(behave_rt) = to_hstring(m2.result(63 downto 0)) - report "bad mulld expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.result(63 downto 0)); + check_true(?? m2.valid, result("for valid")); + check_equal(m2.result(63 downto 0), behave_rt, result("for mulld " & to_hstring(behave_rt))); end loop; elsif run("Test mulhdu") then @@ -140,10 +138,8 @@ begin wait for clk_period * (pipeline_depth-1); - assert m2.valid = '1'; - - assert to_hstring(behave_rt) = to_hstring(m2.result(127 downto 64)) - report "bad mulhdu expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.result(127 downto 64)); + check_true(?? m2.valid, result("for valid")); + check_equal(m2.result(127 downto 64), behave_rt, result("for mulhdu " & to_hstring(behave_rt))); end loop; elsif run("Test mulhd") then @@ -166,10 +162,8 @@ begin wait for clk_period * (pipeline_depth-1); - assert m2.valid = '1'; - - assert to_hstring(behave_rt) = to_hstring(m2.result(127 downto 64)) - report "bad mulhd expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.result(127 downto 64)); + check_true(?? m2.valid, result("for valid")); + check_equal(m2.result(127 downto 64), behave_rt, result("for mulhd " & to_hstring(behave_rt))); end loop; elsif run("Test mullw") then @@ -194,10 +188,8 @@ begin wait for clk_period * (pipeline_depth-1); - assert m2.valid = '1'; - - assert to_hstring(behave_rt) = to_hstring(m2.result(63 downto 0)) - report "bad mullw expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.result(63 downto 0)); + check_true(?? m2.valid, result("for valid")); + check_equal(m2.result(63 downto 0), behave_rt, result("for mullw " & to_hstring(behave_rt))); end loop; elsif run("Test mulhw") then @@ -222,11 +214,8 @@ begin wait for clk_period * (pipeline_depth-1); - assert m2.valid = '1'; - - assert to_hstring(behave_rt) = to_hstring(m2.result(63 downto 32) & m2.result(63 downto 32)) - report "bad mulhw expected " & to_hstring(behave_rt) & " got " & - to_hstring(m2.result(63 downto 32) & m2.result(63 downto 32)); + check_true(?? m2.valid, result("for valid")); + check_equal(m2.result(63 downto 32) & m2.result(63 downto 32), behave_rt, result("for mulhw " & to_hstring(behave_rt))); end loop; elsif run("Test mulhwu") then @@ -250,11 +239,8 @@ begin wait for clk_period * (pipeline_depth-1); - assert m2.valid = '1'; - - assert to_hstring(behave_rt) = to_hstring(m2.result(63 downto 32) & m2.result(63 downto 32)) - report "bad mulhwu expected " & to_hstring(behave_rt) & " got " & - to_hstring(m2.result(63 downto 32) & m2.result(63 downto 32)); + check_true(?? m2.valid, result("for valid")); + check_equal(m2.result(63 downto 32) & m2.result(63 downto 32), behave_rt, result("for mulhwu " & to_hstring(behave_rt))); end loop; elsif run("Test mulli") then @@ -278,10 +264,8 @@ begin wait for clk_period * (pipeline_depth-1); - assert m2.valid = '1'; - - assert to_hstring(behave_rt) = to_hstring(m2.result(63 downto 0)) - report "bad mulli expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.result(63 downto 0)); + check_true(?? m2.valid, result("for valid")); + check_equal(m2.result(63 downto 0), behave_rt, result("for mulli " & to_hstring(behave_rt))); end loop; end if; end loop; diff --git a/plru_tb.vhdl b/plru_tb.vhdl index 78f0e94..63ca52d 100644 --- a/plru_tb.vhdl +++ b/plru_tb.vhdl @@ -58,56 +58,56 @@ begin wait for 4*clk_period; - report "accessing 1:"; + info("accessing 1:"); acc <= "001"; acc_en <= '1'; wait for clk_period; - report "lru:" & to_hstring(lru); + info("lru:" & to_hstring(lru)); - report "accessing 2:"; + info("accessing 2:"); acc <= "010"; wait for clk_period; - report "lru:" & to_hstring(lru); + info("lru:" & to_hstring(lru)); - report "accessing 7:"; + info("accessing 7:"); acc <= "111"; wait for clk_period; - report "lru:" & to_hstring(lru); + info("lru:" & to_hstring(lru)); - report "accessing 4:"; + info("accessing 4:"); acc <= "100"; wait for clk_period; - report "lru:" & to_hstring(lru); + info("lru:" & to_hstring(lru)); - report "accessing 3:"; + info("accessing 3:"); acc <= "011"; wait for clk_period; - report "lru:" & to_hstring(lru); + info("lru:" & to_hstring(lru)); - report "accessing 5:"; + info("accessing 5:"); acc <= "101"; wait for clk_period; - report "lru:" & to_hstring(lru); + info("lru:" & to_hstring(lru)); - report "accessing 3:"; + info("accessing 3:"); acc <= "011"; wait for clk_period; - report "lru:" & to_hstring(lru); + info("lru:" & to_hstring(lru)); - report "accessing 5:"; + info("accessing 5:"); acc <= "101"; wait for clk_period; - report "lru:" & to_hstring(lru); + info("lru:" & to_hstring(lru)); - report "accessing 6:"; + info("accessing 6:"); acc <= "110"; wait for clk_period; - report "lru:" & to_hstring(lru); + info("lru:" & to_hstring(lru)); - report "accessing 0:"; + info("accessing 0:"); acc <= "000"; wait for clk_period; - report "lru:" & to_hstring(lru); + info("lru:" & to_hstring(lru)); test_runner_cleanup(runner); end process; diff --git a/rotator_tb.vhdl b/rotator_tb.vhdl index 781027f..50eba2c 100644 --- a/rotator_tb.vhdl +++ b/rotator_tb.vhdl @@ -23,7 +23,7 @@ architecture behave of rotator_tb is signal shift: std_ulogic_vector(6 downto 0) := (others => '0'); signal insn: std_ulogic_vector(31 downto 0) := (others => '0'); signal is_32bit, right_shift, arith, clear_left, clear_right: std_ulogic := '0'; - signal result: std_ulogic_vector(63 downto 0); + signal res: std_ulogic_vector(63 downto 0); signal carry_out: std_ulogic; signal extsw: std_ulogic; @@ -40,7 +40,7 @@ begin clear_left => clear_left, clear_right => clear_right, sign_ext_rs => extsw, - result => result, + result => res, carry_out => carry_out ); @@ -50,7 +50,11 @@ begin variable rnd : RandomPType; begin rnd.InitSeed(stim_process'path_name); - + + -- TODO: Consider making debug messages visible with a command line option + -- rather than uncommenting this line: + -- show(display_handler, debug); + test_runner_setup(runner, runner_cfg); while test_suite loop @@ -68,8 +72,7 @@ begin insn <= x"00000" & '0' & rnd.RandSlv(10) & '0'; wait for clk_period; behave_ra := ppc_rlwinm(rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn)); - assert behave_ra = result - report "bad rlwnm expected " & to_hstring(behave_ra) & " got " & to_hstring(result); + check_equal(res, behave_ra, result("for rlwnm")); end loop; elsif run("Test rlwimi") then @@ -85,8 +88,7 @@ begin insn <= x"00000" & '0' & rnd.RandSlv(10) & '0'; wait for clk_period; behave_ra := ppc_rlwimi(ra, rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn)); - assert behave_ra = result - report "bad rlwimi expected " & to_hstring(behave_ra) & " got " & to_hstring(result); + check_equal(res, behave_ra, result("for rlwnimi")); end loop; elsif run("Test rld[i]cl") then @@ -102,8 +104,7 @@ begin insn <= x"00000" & '0' & rnd.RandSlv(10) & '0'; wait for clk_period; behave_ra := ppc_rldicl(rs, shift(5 downto 0), insn_mb(insn)); - assert behave_ra = result - report "bad rldicl expected " & to_hstring(behave_ra) & " got " & to_hstring(result); + check_equal(res, behave_ra, result("for rldicl")); end loop; elsif run("Test rld[i]cr") then @@ -119,13 +120,12 @@ begin insn <= x"00000" & '0' & rnd.RandSlv(10) & '0'; wait for clk_period; behave_ra := ppc_rldicr(rs, shift(5 downto 0), insn_me(insn)); - --report "rs = " & to_hstring(rs); - --report "ra = " & to_hstring(ra); - --report "shift = " & to_hstring(shift); - --report "insn me = " & to_hstring(insn_me(insn)); - --report "result = " & to_hstring(result); - assert behave_ra = result - report "bad rldicr expected " & to_hstring(behave_ra) & " got " & to_hstring(result); + debug("rs = " & to_hstring(rs)); + debug("ra = " & to_hstring(ra)); + debug("shift = " & to_hstring(shift)); + debug("insn me = " & to_hstring(insn_me(insn))); + debug("result = " & to_hstring(res)); + check_equal(res, behave_ra, result("for rldicr")); end loop; elsif run("Test rldic") then @@ -141,8 +141,7 @@ begin insn <= x"00000" & '0' & rnd.RandSlv(10) & '0'; wait for clk_period; behave_ra := ppc_rldic(rs, shift(5 downto 0), insn_mb(insn)); - assert behave_ra = result - report "bad rldic expected " & to_hstring(behave_ra) & " got " & to_hstring(result); + check_equal(res, behave_ra, result("for rldic")); end loop; elsif run("Test rldimi") then @@ -158,8 +157,7 @@ begin insn <= x"00000" & '0' & rnd.RandSlv(10) & '0'; wait for clk_period; behave_ra := ppc_rldimi(ra, rs, shift(5 downto 0), insn_mb(insn)); - assert behave_ra = result - report "bad rldimi expected " & to_hstring(behave_ra) & " got " & to_hstring(result); + check_equal(res, behave_ra, result("for rldimi")); end loop; elsif run("Test slw") then @@ -174,8 +172,7 @@ begin shift <= rnd.RandSlv(7); wait for clk_period; behave_ra := ppc_slw(rs, std_ulogic_vector(resize(unsigned(shift), 64))); - assert behave_ra = result - report "bad slw expected " & to_hstring(behave_ra) & " got " & to_hstring(result); + check_equal(res, behave_ra, result("for slv")); end loop; elsif run("Test sld") then @@ -190,8 +187,7 @@ begin shift <= rnd.RandSlv(7); wait for clk_period; behave_ra := ppc_sld(rs, std_ulogic_vector(resize(unsigned(shift), 64))); - assert behave_ra = result - report "bad sld expected " & to_hstring(behave_ra) & " got " & to_hstring(result); + check_equal(res, behave_ra, result("for sld")); end loop; elsif run("Test srw") then @@ -206,8 +202,7 @@ begin shift <= rnd.RandSlv(7); wait for clk_period; behave_ra := ppc_srw(rs, std_ulogic_vector(resize(unsigned(shift), 64))); - assert behave_ra = result - report "bad srw expected " & to_hstring(behave_ra) & " got " & to_hstring(result); + check_equal(res, behave_ra, result("for srw")); end loop; elsif run("Test srd") then @@ -222,8 +217,7 @@ begin shift <= rnd.RandSlv(7); wait for clk_period; behave_ra := ppc_srd(rs, std_ulogic_vector(resize(unsigned(shift), 64))); - assert behave_ra = result - report "bad srd expected " & to_hstring(behave_ra) & " got " & to_hstring(result); + check_equal(res, behave_ra, result("for srd")); end loop; elsif run("Test sraw[i]") then @@ -238,12 +232,12 @@ begin shift <= '0' & rnd.RandSlv(6); wait for clk_period; behave_ca_ra := ppc_sraw(rs, std_ulogic_vector(resize(unsigned(shift), 64))); - --report "rs = " & to_hstring(rs); - --report "ra = " & to_hstring(ra); - --report "shift = " & to_hstring(shift); - --report "result = " & to_hstring(carry_out & result); - assert behave_ca_ra(63 downto 0) = result and behave_ca_ra(64) = carry_out - report "bad sraw expected " & to_hstring(behave_ca_ra) & " got " & to_hstring(carry_out & result); + debug("rs = " & to_hstring(rs)); + debug("ra = " & to_hstring(ra)); + debug("shift = " & to_hstring(shift)); + debug("result = " & to_hstring(carry_out & res)); + check_equal(res, behave_ca_ra(63 downto 0), result("for sraw")); + check_equal(carry_out, behave_ca_ra(64), result("for sraw carry_out")); end loop; elsif run("Test srad[i]") then @@ -258,12 +252,12 @@ begin shift <= rnd.RandSlv(7); wait for clk_period; behave_ca_ra := ppc_srad(rs, std_ulogic_vector(resize(unsigned(shift), 64))); - --report "rs = " & to_hstring(rs); - --report "ra = " & to_hstring(ra); - --report "shift = " & to_hstring(shift); - --report "result = " & to_hstring(carry_out & result); - assert behave_ca_ra(63 downto 0) = result and behave_ca_ra(64) = carry_out - report "bad srad expected " & to_hstring(behave_ca_ra) & " got " & to_hstring(carry_out & result); + debug("rs = " & to_hstring(rs)); + debug("ra = " & to_hstring(ra)); + debug("shift = " & to_hstring(shift)); + debug("result = " & to_hstring(carry_out & res)); + check_equal(res, behave_ca_ra(63 downto 0), result("for srad")); + check_equal(carry_out, behave_ca_ra(64), result("for srad carry_out")); end loop; elsif run("Test extswsli") then @@ -282,12 +276,11 @@ begin behave_ra(63 downto 32) := (others => rs(31)); behave_ra := std_ulogic_vector(shift_left(unsigned(behave_ra), to_integer(unsigned(shift)))); - --report "rs = " & to_hstring(rs); - --report "ra = " & to_hstring(ra); - --report "shift = " & to_hstring(shift); - --report "result = " & to_hstring(carry_out & result); - assert behave_ra = result - report "bad extswsli expected " & to_hstring(behave_ra) & " got " & to_hstring(result); + debug("rs = " & to_hstring(rs)); + debug("ra = " & to_hstring(ra)); + debug("shift = " & to_hstring(shift)); + debug("result = " & to_hstring(carry_out & res)); + check_equal(res, behave_ra, result("for extswsli")); end loop; end if; end loop; diff --git a/run.py b/run.py index 4d78f0f..2ffbc9e 100644 --- a/run.py +++ b/run.py @@ -7,8 +7,8 @@ prj.add_osvvm() root = Path(__file__).parent lib = prj.add_library("lib") -lib.add_source_files(root / "litedram/extras/*.vhdl") -lib.add_source_files(root / "litedram/generated/sim/*.vhdl") +lib.add_source_files(root / "litedram" / "extras" / "*.vhdl") +lib.add_source_files(root / "litedram" / "generated" / "sim" / "*.vhdl") # Use multiply.vhd and not xilinx-mult.vhd. Use VHDL-based random. vhdl_files = glob(str(root / "*.vhdl")) @@ -22,6 +22,8 @@ vhdl_files = [ lib.add_source_files(vhdl_files) unisim = prj.add_library("unisim") -unisim.add_source_files(root / "sim-unisim/*.vhdl") +unisim.add_source_files(root / "sim-unisim" / "*.vhdl") + +prj.set_sim_option("disable_ieee_warnings", True) prj.main()