diff --git a/utils.vhdl b/utils.vhdl
index 7238641..4ccc3b5 100644
--- a/utils.vhdl
+++ b/utils.vhdl
@@ -5,6 +5,7 @@ use ieee.numeric_std.all;
 package utils is
 
     function log2(i : natural) return integer;
+    function log2ceil(i : natural) return integer;
     function ispow2(i : integer) return boolean;
 
 end utils;
@@ -22,6 +23,17 @@ package body utils is
         return ret;
     end function;
 
+    function log2ceil(i : natural) return integer is
+        variable tmp : integer := i;
+        variable ret : integer := 0;
+    begin
+        while tmp >= 1 loop
+            ret  := ret + 1;
+            tmp := tmp / 2;
+        end loop;
+        return ret;
+    end function;
+
     function ispow2(i : integer) return boolean is
     begin
         if to_integer(to_unsigned(i, 32) and to_unsigned(i - 1, 32)) = 0 then
diff --git a/wishbone_bram_wrapper.vhdl b/wishbone_bram_wrapper.vhdl
index 14520b5..2cf2a17 100644
--- a/wishbone_bram_wrapper.vhdl
+++ b/wishbone_bram_wrapper.vhdl
@@ -24,7 +24,7 @@ entity wishbone_bram_wrapper is
 end entity wishbone_bram_wrapper;
 
 architecture behaviour of wishbone_bram_wrapper is
-    constant ram_addr_bits : integer := log2(MEMORY_SIZE) - 3;
+    constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE) - 3;
 
     -- RAM interface
     signal ram_addr : std_logic_vector(ram_addr_bits - 1 downto 0);