From 5eb351b4bec8496d917f4dff0b9c1447508d97c3 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Tue, 15 Dec 2020 14:27:26 +1100 Subject: [PATCH] Reset JTAG/DMI request is never initialized and we leak X state control signals to other parts of the core (eg dmi_wr). Add a reset. Signed-off-by: Anton Blanchard --- dmi_dtm_xilinx.vhdl | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/dmi_dtm_xilinx.vhdl b/dmi_dtm_xilinx.vhdl index ed92e95..69d8996 100644 --- a/dmi_dtm_xilinx.vhdl +++ b/dmi_dtm_xilinx.vhdl @@ -222,11 +222,12 @@ begin -- jtag_req latch. Could be split into 3 processes but it's probably -- not worthwhile. -- - shifter: process(jtag_clk, jtag_reset) + shifter: process(jtag_clk, jtag_reset, sys_reset) begin - if jtag_reset = '1' then + if jtag_reset = '1' or sys_reset = '1' then shiftr <= (others => '0'); jtag_req <= '0'; + request <= (others => '0'); elsif rising_edge(jtag_clk) then -- Handle jtag "commands" when sel is 1