From 67b6117ebf05f7f499aa8020b091bd82104c117b Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Sat, 13 Jun 2020 22:29:54 +1000 Subject: [PATCH] soc: Slight cleanup of IRQ assignments Use a separate process to assign selected interrupts to the interrupt array, and document them. There's only one interrupt *for now* but that will change and this way is clearer. Signed-off-by: Benjamin Herrenschmidt --- include/microwatt_soc.h | 5 +++++ soc.vhdl | 13 ++++++++++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/include/microwatt_soc.h b/include/microwatt_soc.h index e0042fb..39820e6 100644 --- a/include/microwatt_soc.h +++ b/include/microwatt_soc.h @@ -17,6 +17,11 @@ #define SPI_FLASH_BASE 0xf0000000 /* SPI Flash memory map */ #define DRAM_INIT_BASE 0xff000000 /* Internal DRAM init firmware */ +/* + * Interrupt numbers + */ +#define IRQ_UART0 0 + /* * Register definitions for the syscon registers */ diff --git a/soc.vhdl b/soc.vhdl index 2f9fe68..ceaf9a9 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -33,6 +33,9 @@ use work.wishbone_types.all; -- IO bus, this will be fixed when it's moved out of litedram and -- into the main SoC once we have a common "firmware". +-- Interrupt numbers: +-- +-- 0 : UART0 entity soc is generic ( @@ -118,6 +121,7 @@ architecture behaviour of soc is signal wb_uart0_in : wb_io_master_out; signal wb_uart0_out : wb_io_slave_out; signal uart0_dat8 : std_ulogic_vector(7 downto 0); + signal uart0_irq : std_ulogic; -- SPI Flash controller signals: signal wb_spiflash_in : wb_io_master_out; @@ -568,7 +572,7 @@ begin reset => rst_uart, txd => uart0_txd, rxd => uart0_rxd, - irq => int_level_in(0), + irq => uart0_irq, wb_adr_in => wb_uart0_in.adr(11 downto 0), wb_dat_in => wb_uart0_in.dat(7 downto 0), wb_dat_out => uart0_dat8, @@ -621,6 +625,13 @@ begin core_irq_out => core_ext_irq ); + -- Assign external interrupts + interrupts: process(all) + begin + int_level_in <= (others => '0'); + int_level_in(0) <= uart0_irq; + end process; + -- BRAM Memory slave bram: if MEMORY_SIZE /= 0 generate bram0: entity work.wishbone_bram_wrapper