diff --git a/fpga/mw_soc_memory.vhdl b/fpga/mw_soc_memory.vhdl
index 1c6fdc1..e9ace36 100644
--- a/fpga/mw_soc_memory.vhdl
+++ b/fpga/mw_soc_memory.vhdl
@@ -92,10 +92,8 @@ begin
 			    state <= ACK;
 			end if;
 		    when ACK =>
-			if wishbone_in.stb = '0' then
-			    read_ack <= '0';
-			    state <= IDLE;
-			end if;
+			read_ack <= '0';
+			state <= IDLE;
 		    end case;
 		else
 		    state <= IDLE;